Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> Synapses <s> We present a model of spike-driven synaptic plasticity inspired by experimental observations and motivated by the desire to build an electronic hardware device that can learn to classify complex stimuli in a semisupervised fashion. During training, patterns of activity are sequentially imposed on the input neurons, and an additional instructor signal drives the output neurons toward the desired activity. The network is made of integrate-and-fire neurons with constant leak and a floor. The synapses are bistable, and they are modified by the arrival of presynaptic spikes. The sign of the change is determined by both the depolarization and the state of a variable that integrates the postsynaptic action potentials. Following the training phase, the instructor signal is removed, and the output neurons are driven purely by the activity of the input neurons weighted by the plastic synapses. In the absence of stimulation, the synapses preserve their internal state indefinitely. Memories are also very robust to the disruptive action of spontaneous activity. A network of 2000 input neurons is shown to be able to classify correctly a large number (thousands) of highly overlapping patterns (300 classes of preprocessed Latex characters, 30 patterns per class, and a subset of the NIST characters data set) and to generalize with performances that are better than or comparable to those of artificial neural networks. Finally we show that the synaptic dynamics is compatible with many of the experimental observations on the induction of long-term modifications (spike-timing-dependent plasticity and its dependence on both the postsynaptic depolarization and the frequency of pre- and postsynaptic neurons). <s> BIB001 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> Synapses <s> Neuromorphic systems are gaining increasing importance in an era where CMOS digital computing techniques are meeting hard physical limits. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. Towards this end, the authors provide a glimpse at what the technology evolution roadmap looks like for these systems so that Neuromorphic engineers may gain the same benefit of anticipation and foresight that IC designers gained from Moore's law many years ago. Scaling of energy efficiency, performance, and size will be discussed as well as how the implementation and application space of Neuromorphic systems are expected to evolve over time. <s> BIB002 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> Synapses <s> In this paper, we describe the design of Neurogrid, a neuromorphic system for simulating large-scale neural models in real time. Neuromorphic systems realize the function of biological neural systems by emulating their structure. Designers of such systems face three major design choices: 1) whether to emulate the four neural elementsVaxonal arbor, synapse, dendritic tree, and somaVwith dedicated or shared electronic circuits; 2) whether to implement these electronic circuits in an analog or digital manner; and 3) whether to interconnect arrays of these silicon neurons with a mesh or a tree network. The choices we made were: 1) we emulated all neural elements except the soma with shared electronic circuits; this choice maximized the number of synaptic connections; 2) we realizedallelectroniccircuitsexcept those foraxonal arbors in an analog manner; this choice maximized energy efficiency; and <s> BIB003 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> Synapses <s> We discuss the design of an experimentation platform intended for prototyping low-cost analog neural networks for on-chip integration with analog/RF circuits. The objective of such integration is to support various tasks, such as self-test, self-tuning, and trust/aging monitoring, which require classification of analog measurements obtained from on-chip sensors. Particular emphasis is given to cost-efficient implementation reflected in: 1) low energy and area budgets of circuits dedicated to neural networks; 2) robust learning in presence of analog inaccuracies; and 3) long-term retention of learned functionality. Our chip consists of a reconfigurable array of synapses and neurons operating below threshold and featuring sub- $\mu \text{W}$ power consumption. The synapse circuits employ dual-mode weight storage: 1) a dynamic mode, for fast bidirectional weight updates during training and 2) a nonvolatile mode, for permanent storage of learned functionality. We discuss a robust learning strategy, and we evaluate the system performance on several benchmark problems, such as the XOR2-6 and two-spirals classification tasks. <s> BIB004 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> Synapses <s> The application of biologically inspired methods in design and control has a long tradition in robotics. Unlike previous approaches in this direction, the emerging field of neurorobotics not only mimics biological mechanisms at a relatively high level of abstraction but employs highly realistic simulations of actual biological nervous systems. Even today, carrying out these simulations efficiently at appropriate timescales is challenging. Neuromorphic chip designs specially tailored to this task therefore offer an interesting perspective for neurorobotics. Unlike Von Neumann CPUs, these chips cannot be simply programmed with a standard programming language. Like real brains, their functionality is determined by the structure of neural connectivity and synaptic efficacies. Enabling higher cognitive functions for neurorobotics consequently requires the application of neurobiological learning algorithms to adjust synaptic weights in a biologically plausible way. In this paper, we therefore investigate how to program neuromorphic chips by means of learning. First, we provide an overview over selected neuromorphic chip designs and analyze them in terms of neural computation, communication systems and software infrastructure. On the theoretical side, we review neurobiological learning techniques. Based on this overview, we then examine on-die implementations of these learning algorithms on the considered neuromorphic chips. A final discussion puts the findings of this work into context and highlights how neuromorphic hardware can potentially advance the field of autonomous robot systems. The paper thus gives an in-depth overview of neuromorphic implementations of basic mechanisms of synaptic plasticity which are required to realize advanced cognitive capabilities with spiking neural networks. <s> BIB005 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> Synapses <s> Implementing compact, low-power artificial neural processing systems with real-time on-line learning abilities is still an open challenge. In this paper we present a full-custom mixed-signal VLSI device with neuromorphic learning circuits that emulate the biophysics of real spiking neurons and dynamic synapses for exploring the properties of computational neuroscience models and for building brain-inspired computing systems. The proposed architecture allows the on-chip configuration of a wide range of network connectivities, including recurrent and deep networks, with short-term and long-term plasticity. The device comprises 128 K analog synapse and 256 neuron circuits with biologically plausible dynamics and bi-stable spike-based plasticity mechanisms that endow it with on-line learning abilities. In addition to the analog circuits, the device comprises also asynchronous digital logic circuits for setting different synapse and neuron properties as well as different network configurations. This prototype device, fabricated using a 180 nm 1P6M CMOS process, occupies an area of 51.4 mm(2), and consumes approximately 4 mW for typical experiments, for example involving attractor networks. Here we describe the details of the overall architecture and of the individual circuits and present experimental results that showcase its potential. By supporting a wide range of cortical-like computational modules comprising plasticity mechanisms, this device will enable the realization of intelligent autonomous systems with on-line learning capabilities. <s> BIB006
The role of synapses in biological systems was first defined in 1897 by Charles Sherrington, who introduced the term synapse as the structure at the point of contact between two neurons which communicate. Projecting this definition onto VLSI circuits, synapses can implement a multiplication between the neuron input signal and its corresponding synaptic weight, in the case of classical neural networks BIB004 . In pulse-based neural networks, along with multiplication, synapses can also carry out linear or nonlinear integration of the input spikes with elaborate temporal dynamics and short-term plasticity (STP) and long-term plasticity (LTP) mechanisms. Synaptic plasticity, i.e., the ability of synapses to adapt their gain over time in response to increases or decreases in their activity, is extremely important in biological neural systems, as it is generally accepted that learning in the brain and formation of memories arise from synaptic modifications  . Indeed, the ability of biological synapses to exhibit STP and LTP is one of their fundamental features. In general, STP produces dynamic modulation of the synaptic strength by the timing of the input stimulation, whereas LTP produces long-term modifications on the synaptic gain based on the presynaptic and postsynaptic history BIB005 . A more detailed description on plasticity mechanisms is provided in the next section. Silicon synapses which are able to reproduce the physics of real synapses have been demonstrated by several groups BIB006 , BIB003 . In these implementations, the response of the synapse I syn , i.e., the postsynaptic current (PSC), is a decaying exponential and is typically modeled as where fall is typically in the order of 0.5-2 ms BIB002 . The main concern about neuromorphic synaptic models with learning capability is the storage of the synaptic weights, which are bounded and have limited precision. This constraint makes memory retrieval impossible, when new experiences, continuously producing new memories, saturate the storage capacity BIB001 . To address this problem, several synaptic storage implementations have been proposed, as follows.