Analog Integrated Current Drivers for Bioimpedance Applications: A Review <s> Open Loop Integrated Current Drivers <s> A high-swing, high-performance CMOS telescopic operational amplifier is described. The high swing of the op-amp is achieved by employing the tail and current source transistors in the deep linear region. The resulting degradation in differential gain, common-mode rejection ratio (CMRR), and other amplifier characteristics are compensated by applying regulated-cascode differential gain enhancement and a replica-tail feedback technique. A prototype of the op-amp has been built in a 0.81-/spl mu/m CMOS process. Operating from a power supply of 3.3 V, it achieves a differential swing of /spl plusmn/2.15 V, a differential gain of 90 dB, unity-gain frequency of 90 MHz, and >50-dB CMRR. It is shown, analytically and through simulations, that the operational amplifier maintains its high CMRR even at high frequencies. <s> BIB001 </s> Analog Integrated Current Drivers for Bioimpedance Applications: A Review <s> Open Loop Integrated Current Drivers <s> In this paper, the design of a specific integrated circuit for the measurement of tissue impedances is presented. The circuit will be part of a multi-micro-sensor system intended to be used in cardiac surgery for sensing biomedical parameters in living bodies. Myocardium tissue impedance is one of these parameters which allows ischemia detection. The designed chip will be used in a four-electrode based setup where the effect of electrode interfaces are cancelled by design. The chip includes a circuit to generate the stimulus signals (sinusoidal current) and the circuitry to measure the magnitude and phase of the tissue impedance. Several integrated circuits have been designed, fabricated and tested, in a 0.8-/spl mu/m CMOS process, working at 3 V of power supply. Some of them including building blocks, and other with the whole measurement system. Experimental tests have shown the circuit feasibility giving expected results for both in-vitro and in-vivo test conditions. <s> BIB002 </s> Analog Integrated Current Drivers for Bioimpedance Applications: A Review <s> Open Loop Integrated Current Drivers <s> A hinge mechanism for a foldable portable telephone is disclosed. The hinge includes a first cylindrical member coupled to a main body portion and a second cylindrical member coupled to a foldable portion. The first cylindrical member has a first cylindrical hollow formed therein and the inner side wall of the first cylindrical hollow has positioning recesses formed in a predetermined pattern corresponding to the opened and closed positions. The second cylindrical member has a second cylindrical hollow formed therein and a plurality of holes formed in a side wall thereof. The second cylindrical member is rotatably fit in the first cylindrical hollow of the first cylindrical member. An elastic cylinder is fit in the second cylindrical hollow. A hard ball freely fit in each of the holes and the hard balls fit in the holes are pinched between the elastic cylinder and the inner side wall of the first cylindrical hollow to allow each sphere to be fit into a corresponding one of the positioning recesses. <s> BIB003 </s> Analog Integrated Current Drivers for Bioimpedance Applications: A Review <s> Open Loop Integrated Current Drivers <s> A low power highly sensitive Thoracic Impedance Variance (TIV) and Electrocardiogram (ECG) monitoring SoC is designed and implemented into a poultice-like plaster sensor for wearable cardiac monitoring. 0.1 Ω TIV detection is possible with a sensitivity of 3.17 V/Ω and SNR > 40 dB. This is achieved with the help of a high quality (Q-factor > 30) balanced sinusoidal current source and low noise reconfigurable readout electronics. A cm-range 13.56 MHz fabric inductor coupling is adopted to start/stop the SoC remotely. Moreover, a 5% duty-cycled Body Channel Communication (BCC) is exploited for 0.2 nJ/b 1 Mbps energy efficient external data communication. The proposed SoC occupies 5 mm × 5 mm including pads in a standard 0.18 μm 1P6M CMOS technology. It dissipates a peak power of 3.9 mW when operating in body channel receiver mode, and consumes 2.4 mW when operating in TIV and ECG detection mode. The SoC is integrated on a 15 cm × 15 cm fabric circuit board together with a flexible battery to form a compact wearable sensor. With 25 adhesive screen-printed fabric electrodes, detection of TIV and ECG at 16 different sites of the heart is possible, allowing optimal detection sites to be configured to accommodate different user dependencies. <s> BIB004 </s> Analog Integrated Current Drivers for Bioimpedance Applications: A Review <s> Open Loop Integrated Current Drivers <s> A multi-modal spectroscopy IC combining the impedance spectroscopy (IMPS) and the multi-wavelength near-infrared spectroscopy (mNIRS) is proposed for high precision non-invasive glucose level estimation. A frequency sweep (10kHz - 76kHz) sinusoidal oscillator (FSSO) is proposed for high resolution (500 steps) for IMPS. The output voltage swing of the FSSO is stabilized by an adaptive gain control (AGC). The measurement results of the IMPS and mNIRS are combined by an artificial neural network (ANN) in external smart device so that mean absolute relative difference (mARD) is enhanced to 8.3% from 15% of IMPS, 15% - 20% of mNIRS. A proposed 12.5mm 2 0.18μm CMOS chip consumes peak power of 38mW at 1.5V. <s> BIB005 </s> Analog Integrated Current Drivers for Bioimpedance Applications: A Review <s> Open Loop Integrated Current Drivers <s> A bioelectrical impedance IC with an intermediate frequency shifting chopper (IFSC) technique driven by a merged clock is presented. The proposed technique enables high-frequency impedance measurements with a narrow bandwidth low-power instrumentation amplifier (IA). The conventional series-connected double choppers required for the frequency shifting operation are replaced with a single chopper driven by a XNOR-merged clock. The proposed IC can measure bioelectrical impedance at a maximum excitation frequency of 1.24 MHz in an IA bandwidth of only 30 kHz. A DC trimming technique that uses a dummy impedance and anti-phase current source can adjust the output offset and prevent output saturation. This DC trimming technique also enables shifting of the impedance measurement scope. The proposed IC is fabricated using 0.13- $\mu \text{m}$ CMOS process, and is shown to achieve a dynamic range of 97.1 dB, and 52 $\mu \text{W}$ of power consumption. <s> BIB006
In BIB003 , an integrated current driver was introduced using standard 0.18 µm CMOS technology. The schematic is shown in Figure 1 . In BIB003 , an integrated current driver was introduced using standard 0.18 μm CMOS technology. The schematic is shown in Figure 1 . This fully differential current driver employed four current sources in an H-bridge configuration. The two current sources, M1 and M10, are active during the positive half cycle of the sinusoidal reference input, while current sources, M6 and M11, are active in the negative half cycle BIB003 . Therefore, the current can flow in both directions through the load. Cascode transistor configuration with differential gain-boosting op-amps (A3, A7) were used to increase the output impedance of the current drivers. Due to symmetry of the system, the output impedance can be approximated by: Where gmi is the transconductance and roi is the drain to source resistance of the ith transistor. Simulations yield a high output impedance of approximately 10.2 MΩ at 1 MHz and a THD of 1% at 10 MHz for an output current of 107 μAp-p BIB003 . The system operates in open loop configuration, and the output current accuracy is directly affected by internal parameters of the system. Since in an open loop system the gain variation is large, even a very small input can saturate the system. No information regarding the phase error is provided. In this system, the output current was sensitive to the mismatch of the current source transistors. In order to have proper settling behavior for the system, the unity gain frequency of A3 and A7 should be less than the second pole of the main current driver BIB001 . Therefore, large transistor ratios (W/L) for the current source were necessary to increase the overall output capacitance of the current source, with respect to the A3 and A7 output capacitors. As the frequency was increased, the open loop gain started to roll off at the -3dB of the system. Limited bandwidth of the current driver is an important factor in the reduction of output impedance at high frequencies. This is due to the fact that, as the frequency increases, the effects of the parasitic This fully differential current driver employed four current sources in an H-bridge configuration. The two current sources, M1 and M10, are active during the positive half cycle of the sinusoidal reference input, while current sources, M6 and M11, are active in the negative half cycle BIB003 . Therefore, the current can flow in both directions through the load. Cascode transistor configuration with differential gain-boosting op-amps (A3, A7) were used to increase the output impedance of the current drivers. Due to symmetry of the system, the output impedance can be approximated by: where g mi is the transconductance and r oi is the drain to source resistance of the i th transistor. Simulations yield a high output impedance of approximately 10.2 MΩ at 1 MHz and a THD of 1% at 10 MHz for an output current of 107 µA p-p BIB003 . The system operates in open loop configuration, and the output current accuracy is directly affected by internal parameters of the system. Since in an open loop system the gain variation is large, even a very small input can saturate the system. No information regarding the phase error is provided. In this system, the output current was sensitive to the mismatch of the current source transistors. In order to have proper settling behavior for the system, the unity gain frequency of A 3 and A 7 should be less than the second pole of the main current driver BIB001 . Therefore, large transistor ratios (W/L) for the current source were necessary to increase the overall output capacitance of the current source, with respect to the A 3 and A 7 output capacitors. As the frequency was increased, the open loop gain started to roll off at the -3dB of the system. Limited bandwidth of the current driver is an important factor in the reduction of output impedance at high frequencies. This is due to the fact that, as the frequency increases, the effects of the parasitic capacitors at the output of the current driver dominate. This results in a phase delay between the input and output, which can cause errors in impedance measurements. The current driver proposed in BIB004 is shown in Figure 2 and was realized in a 0.18 µm standard CMOS technology. It is composed of two fully differential amplifiers (FDA1 and FDA2) with an RC frequency selective network that produces an input sinusoidal voltage, followed by a VCCS, formed by transistors M3 and M4 and resistor R 1 BIB004 . The FDA is a two-stage folded cascode with source followers at the output stage in order to achieve low output impedance to effectively drive the frequency selective RC bridge network BIB004 . The RC frequency selective network generated a 90 kHz balanced sinusoidal voltage signal V SW + and V SW − . The 2 bit-DAC output adjusts the gate voltages of transistors M3 and M4 that results in variable sinusoidal voltage of 0.22 V p-p to 0.78 V p-p BIB004 . The output current is defined as: The output impedance of the V/I converter is given by: where g mi is the transconductance of transistor M i . Based on Equation (2), the output current is inversely proportional to R 1 . However, the absolute value of R 1 can vary up to 20% which leads to inaccurate current measurements unless it is laser trimmed. According to Equation (3), a large output impedance can be achieved for small transconductance of transistors M3 and M4, or large R 1 . The system operated at 90 kHz and generated four-step controllable balanced sinusoidal currents of 100 µA p-p -350 µA p-p. The current driver operates in open loop configuration, and the output current is heavily dependent on internal parameters of the system, including the variation of the two FDAs that generate V SW + and V SW − . Moreover, the 2 bit-DAC limits the output current to four values only. Any offset generated by DAC and FDA will alter V SW + and V SW − and I − and I + respectively. Measured results verify a variation of 1% in the output current for loads less than 5.6 kΩ at 90 kHz BIB004 . Thus, the output impedance can be realized to be in excess of 560 kΩ at 90 kHz. Additionally, THD of the output current is stated to be less than 1% for 250 µA p-p measured at 90 kHz BIB004 . The overall power consumption is 2 mW. An analogous architecture was adopted by the same group in another study BIB005 , where instead of a DAC, an adaptive gain control was utilized to stabilize the output voltage swing of FDA. The oscillation frequency can be controlled by tunable resistor R. The operational frequency range of the driver was from 10 to 76 kHz. Different values of current were achieved through variable transconductance gain (1/R 1 ). The voltage to current (V-I) converter translated the differential sinusoidal voltage from FDAs into balanced currents of 80, 200, and 400 µA via a variable transconductance gain of 1/R 1 = 200 µA/V, 500 µA/V and 1 mA/V, respectively. The same equations for output current and output impedance as the previous current driver applies here. A THD of less than 0.2% was achieved for 200 µA p-p BIB005 . The current driver in BIB006 generates square currents up to 169 µA, and was fabricated in 0.13 µm technology with a supply voltage of 1.2 V. The amplitude of the excitation was set by an 8-bit current DAC, which is programmed from 0 to 169 µA in 256 steps. The schematic of this triple cascode current driver is shown in Figure 3 . . Current driver BIB004 . The current driver in BIB006 generates square currents up to 169 μA, and was fabricated in 0.13 μm technology with a supply voltage of 1.2 V. The amplitude of the excitation was set by an 8-bit current DAC, which is programmed from 0 to 169 μA in 256 steps. The schematic of this triple cascode current driver is shown in Figure 3 . A triple cascode architecture was used to achieve high output impedance. The biasing of cascodes was implemented via resistor division. Two chopper switches were used to average the mismatches among the cascode mirrors BIB006 . The switch at the output is to set the frequency of the alternating current. The output impedance of the current driver is defined as: Current driver BIB004 . A triple cascode architecture was used to achieve high output impedance. The biasing of cascodes was implemented via resistor division. Two chopper switches were used to average the mismatches among the cascode mirrors BIB006 . The switch at the output is to set the frequency of the alternating current. The output impedance of the current driver is defined as: Z o = g m7 r o7 r o8 r o9 g m13 r o13 r o14 r o15 . Current driver BIB004 . The current driver in BIB006 generates square currents up to 169 μA, and was fabricated in 0.13 μm technology with a supply voltage of 1.2 V. The amplitude of the excitation was set by an 8-bit current DAC, which is programmed from 0 to 169 μA in 256 steps. The schematic of this triple cascode current driver is shown in Figure 3 . A triple cascode architecture was used to achieve high output impedance. The biasing of cascodes was implemented via resistor division. Two chopper switches were used to average the mismatches among the cascode mirrors BIB006 . The switch at the output is to set the frequency of the alternating current. The output impedance of the current driver is defined as: Figure 3 . Circuit schematic of triple cascode current driver BIB006 . Figure 3 . Circuit schematic of triple cascode current driver BIB006 . In this architecture, the offset resulting from the mismatch of the cascode current mirrors is eliminated by use of choppers. In processes with small supply voltages, cascodes can be a limiting factor in the output swing. In this system, although the presence of triple cascode increases the output impedance, it severely limits the output current amplitudes, as each cascode consumes at least an effective gate driving voltage. Any transistor in the signal path translates into a pole in the transfer function. Achieving a high phase margin is not an easy task BIB001 . The on-chip resistors are prone to mismatch. Using them as a biasing technique to drive the cascodes may not be an optimum option, as the variation from fabrication may cause some transistors to go in to the triode region and reduce the output impedance of the driver. When high frequency operation is considered, all the parasitic capacitors from triple cascode, in addition to stray capacitors, will result in phase imbalance between the input and output. A sinusoidal current driver based on ramp integrator and fabricated in 0.8 µm process with 3 V supply was discussed in BIB002 . The block diagram of the current driver is illustrated in Figure 4 . The output is fed to a voltage to current buffer that is used to define the limits of the current amplitude and to reduce the loading effects. The system works at three distinct frequencies of 1, 8, and 16 kHz through a 2-bit digital control capacitor bank denoted by letter S. The maximum output current is 7 µA p . The oscillation frequency is defined as BIB002  where V I is a constant reference voltage generated on-chip, C I is the integrator capacitor, g m is the transconductance of the OTA, and V H −V L is the allowable voltage swing for the integrator output BIB002 . 