Multi-Channel Neural Recording Implants: A Review <s> Circuit Techniques <s> The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. ::: Table of contents ::: ::: 1 Introduction to Analog Design ::: 2 Basic MOS Device Physics ::: 3 Single-Stage Amplifiers ::: 4 Differential Amplifiers ::: 5 Passive and Active Current Mirrors ::: 6 Frequency Response of Amplifiers ::: 7 Noise ::: 8 Feedback ::: 9 Operational Amplifiers ::: 10 Stability and Frequency Compensation ::: 11 Bandgap References ::: 12 Introduction to Switched-Capacitor Circuits ::: 13 Nonlinearity and Mismatch ::: 14 Oscillators ::: 15 Phase-Locked Loops ::: 16 Short-Channel Effects and Device Models ::: 17 CMOS Processing Technology ::: 18 Layout and Packaging <s> BIB001 </s> Multi-Channel Neural Recording Implants: A Review <s> Circuit Techniques <s> There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff. <s> BIB002 </s> Multi-Channel Neural Recording Implants: A Review <s> Circuit Techniques <s> We present in this paper a low-power bioamplifier suitable for massive integration in dense multichannel recording devices. This bioamplifier achieves reduced-size compared to previous designs by means of active low-frequency suppression. An active integrator located in the feedback path of a low-noise amplifier is employed for placing a highpass cutoff frequency within the transfer function. A very long integrating time constant is achieved using a small integrated capacitor and a MOS-bipolar equivalent resistor. This configuration rejects unwanted low-frequency contents without the need for input RC networks or large feedback capacitors. Therefore, the bioamplifier high-input impedance and small size are preserved. The bioamplifier, implemented in a 0.18-mum CMOS process, has been designed for neural recording of action potentials, and optimised through a transconductance-ef-ficiency design methodology for micropower operation. Measured performance and results obtained from in vivo recordings are presented. The integrated bioamplifier provides a midband gain of 50 dB, and achieves an input-referred noise of 5.6 muVrms. It occupies less than 0.050 mm2 of chip area and dissipates 8.6 muW. <s> BIB003 </s> Multi-Channel Neural Recording Implants: A Review <s> Circuit Techniques <s> The accelerating pace of research in neuroscience has created a considerable demand for neural interfacing microsystems capable of monitoring the activity of large groups of neurons. These emerging tools have revealed a tremendous potential for the advancement of knowledge in brain research and for the development of useful clinical applications. They can extract the relevant control signals directly from the brain enabling individuals with severe disabilities to communicate their intentions to other devices, like computers or various prostheses. Such microsystems are self-contained devices composed of a neural probe attached with an integrated circuit for extracting neural signals from multiple channels, and transferring the data outside the body. The greatest challenge facing development of such emerging devices into viable clinical systems involves addressing their small form factor and low-power consumption constraints, while providing superior resolution. In this paper, we survey the recent progress in the design and the implementation of multi-channel neural recording Microsystems, with particular emphasis on the design of recording and telemetry electronics. An overview of the numerous neural signal modalities is given and the existing microsystem topologies are covered. We present energy-efficient sensory circuits to retrieve weak signals from neural probes and we compare them. We cover data management and smart power scheduling approaches, and we review advances in low-power telemetry. Finally, we conclude by summarizing the remaining challenges and by highlighting the emerging trends in the field. <s> BIB004 </s> Multi-Channel Neural Recording Implants: A Review <s> Circuit Techniques <s> In this paper, an in-depth design methodology for fully-integrated tunable low-noise amplifiers for neural recording applications is presented. In this methodology, a modified system design is proposed to optimize the area/noise/linearity performance. A novel linear pseudo-resistor with a wide range of tunability is also proposed. As a case study, a low-noise tunable and reconfigurable amplifier for neural recording applications is designed and simulated in a 0.18 $\mu{\rm m}$ complementary metal–oxide–semiconductor process in all process corners. Simulated characteristics of the amplifier include tunable gain of 54 dB, tunable high-cutoff frequency of 10 kHz, programmable low-cutoff frequency ranging from 4 to 300 Hz, and power consumption of 20.8 $\mu{\rm W}$ at 1.8 V. According to postlayout simulations, integrated input-referred noise of the amplifier is 2.6 $\mu{\rm V}_{\rm rms}$ and 2.38 $\mu{\rm V}_{\rm rms}$ over the 0.5 Hz–50 kHz frequency range for low-cutoff frequency of 4 and 300 Hz, respectively. The amplifier also provides output voltage swing of 1 ${\rm V}_{\rm P-P}$ with total harmonic distortion of -46.24 dB at 300 Hz, and -45.97 dB at 10 kHz. <s> BIB005 </s> Multi-Channel Neural Recording Implants: A Review <s> Circuit Techniques <s> A system-on-chip (SoC) neural recording interface with 64 channels, 64 16-tap programmable mixed-signal FIR filters and a fully integrated 915 MHz OOK/FSK PLL-based wireless transmitter is presented. Each recording channel has a fully differential amplifier with 54 dB gain and utilizes a tunable low-distortion subthreshold MOS-resistor to reject DC offsets with an input-referred noise of 6.5 μV and a CMRR of 75 dB. Each channel contains a modified 8-bit SAR ADC with an ENOB of 7.8-bits and can provide analog-digital multiplication by modifying the the sampling phase of the ADC. It is used in conjunction with 12-bit digital adders and registers to implement 64 programmable transposed FIR filters. The 915 MHz FSK/OOK transmitter offers data rates up to 1.5 Mbps and a maximum output power of 0 dBm. The 4×3 mm2 chip fabricated in a 0.13 μm CMOS process dissipates 5.03 mW from a 1.2 V supply. Experimental measurements characterize the electrical performance of the wireless SoC. In vivo measurement results from freely moving rats are also presented. <s> BIB006 </s> Multi-Channel Neural Recording Implants: A Review <s> Circuit Techniques <s> This paper introduces an area- and power-efficient approach for compressive recording of cortical signals used in an implantable system prior to transmission. Recent research on compressive sensing has shown promising results for sub-Nyquist sampling of sparse biological signals. Still, any large-scale implementation of this technique faces critical issues caused by the increased hardware intensity. The cost of implementing compressive sensing in a multichannel system in terms of area usage can be significantly higher than a conventional data acquisition system without compression. To tackle this issue, a new multichannel compressive sensing scheme which exploits the spatial sparsity of the signals recorded from the electrodes of the sensor array is proposed. The analysis shows that using this method, the power efficiency is preserved to a great extent while the area overhead is significantly reduced resulting in an improved power-area product. The proposed circuit architecture is implemented in a UMC 0.18 ${\mbi \mu}$ m CMOS technology. Extensive performance analysis and design optimization has been done resulting in a low-noise, compact and power-efficient implementation. The results of simulations and subsequent reconstructions show the possibility of recovering fourfold compressed intracranial EEG signals with an SNR as high as 21.8 dB, while consuming 10.5 ${\mbi \mu}$ W of power within an effective area of 250 ${\mbi \mu}$ m $\, \times \,$ 250 ${\mbi \mu}$ m per channel. <s> BIB007
The IRN value of an OTA varies based on its architecture. For example, a two-stage OTA (or Miller OTA) could have a lower IRN compared to folded cascade architecture, due to the lower number of transistors in the first stage. However, in general and in the same condition of bias current and transistor sizes, the differential pair transistors have a maximum contribution in the IRN value of various OTA architectures. Also, the transistor of the tail current source (the current source that is connected to the differential pair) in all architectures as well as in the cascode transistors in the telescopic or folded cascode architectures has the minimum contribution in the IRN value. As presented in Table 1 , neural signals have very low frequency components and small band width. For the frequencies higher than the corner frequency ( f c ) in an LNA, the thermal noise is dominant and for the frequencies lower than ( f c ), the flicker noise is dominant, where both of these noises should be mitigated. For example, in BIB002 and BIB003 , ( f c ) is reported as 100 and 300 Hz, respectively. In BIB004 , the IRN of the thermal noise is calculated and tabulated for different OTA architectures. Equation (3), presents the flicker noise power of a MOS transistor BIB001 . where C ox is the gate oxide capacitance per unit area, and K is a process dependent constant for a MOS transistor. W and L are the width and length of a MOS transistor, respectively. To reduce the flicker noise power of an OTA, the differential pair transistors should be a PMOS type, which have lower K compared to the NMOS transistors and according to Equation (3), the size chosen should be large. In addition, based on the IRN equations of the thermal and flicker noise in various OTA architectures, increasing the transconductance of the differential pair (g m ) compared to other transistors reduces the IRN that corresponds to both thermal and flicker noise. Therefore, by biasing the differential pair in the subthreshold region, the g m of these transistors could be maximized. This can be achieved by increasing the W/L ratio of the differential pair for a constant bias current. Increasing the W/L ratio also decreases the flicker noise of the differential pair. As explained in Section 4.1.1, for the CFN topology, increasing the C I based on Equation (1), increases the midband gain of the neural amplifier and results in a reduction of the IRN. This is why the gain of the first stage (LNA) is usually designed to be significantly higher than the following stages. Also, for a given gain, increasing the width of the differential pair, decreases the flicker noise power of the OTA in Equation (1) on one hand, and increases the C in on the other hand. Therefore, as a trade off, there is an optimum point for the W where IRN is minimized. The low noise neural amplifier in BIB002 BIB005 BIB006 BIB007 has been designed to consider the circuit noise reduction techniques explained in this section, but without considering the systematic technique of the following section.