DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> Inductively Coupled Ditherless DCO <s> An all-digital phase-locked loop (ADPLL) with all components working with time interval or period signals is demonstrated. The ADPLL consists mainly of a free-running ring oscillator (FRO), a time to digital converter (TDC), a digitally controlled oscillator (DCO), a digital divider and a digital loop filter. In the proposed architecture, the TDC and DCO have an equal time resolution from the common FRO. The digital divider keeps the loop gain constant when the frequency multiplication factor changes. As a result, the ADPLL is inherently stable regardless of the variations of the process, supply voltage and temperature (PVT). The ADPLL is fabricated in 0.13 ?m CMOS process. Measurement results show that it works well over wide operation conditions, with the input frequencies ranging from 37.5 KHz to 25 MHz, frequency multiplication factors from 10 to 255, output frequencies from 10 MHz to 500 MHz, and supply voltages from 0.6 V to 1.6 V. <s> BIB001 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> Inductively Coupled Ditherless DCO <s> A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) is presented. The time-windowed TDC uses a two-step structure with an inverter- and a Vernier-delay time-quantizer to improve time resolution, which results in low phase noise. Time-windowed operation is implemented in the TDC, in which a single-shot pulse-based operation is used for low power consumption. The test chip implemented in 90-nm CMOS technology exhibits in-band phase noise of , where the loop-bandwidth is set to 500 kHz with a 40-MHz reference signal, and out-band noise of at a 1-MHz offset frequency. The chip core occupies 0.37 and the measured power consumption is 8.1 mA from a 1.2-V power supply. <s> BIB002 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> Inductively Coupled Ditherless DCO <s> This paper proposes an oppositely coupled varactor pair and reports the measured results for applying to a test digitally controlled oscillator (DCO). The pair exploits the differences between the accumulation region capacitance and inversion region capacitance of pMOS varactors. The novel varactor pairs provide much smaller switchable capacitances than those of other approaches, and hence, the test DCO for verifying the property of the pair achieves the high-frequency resolution. The pairs and test DCO are implemented in a 0.18-μm CMOS process. The switchable discrete capacitance of 32 aF is obtained by using the novel varactor pairs, and the test DCO has a frequency resolution of about 110 kHz at 5.8 GHz. Furthermore, ΔC of 4-aF and 14-kHz frequency resolution can be obtained through the dithering processes. The test DCO achieves a low phase noise of -117.6 dBc/Hz at 1-MHz offset from 5.8 GHz. <s> BIB003 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> Inductively Coupled Ditherless DCO <s> This brief presents a wide frequency range digitally controlled oscillator (DCO) with low supply sensitivity and low power consumption. We propose a compensation scheme employing feedforward inverters to suppress supply noise. Both wide frequency range and fine resolution are obtained using a hierarchical architecture consisting of a coarse delay chain and an interpolator. The proposed DCO was fabricated in a 0.13-μm CMOS process. It successfully eliminates noise components due to supply variation. The phase noise at 1-MHz frequency offset from the carrier frequency of 700 MHz is -106.3 dBc/Hz. The frequency range of the DCO is measured from 320 MHz to 1.25 GHz. <s> BIB004 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> Inductively Coupled Ditherless DCO <s> This paper presents a two-point modulator architecture which is immune to the nonlinear effect of the digitally-controlled oscillator (DCO). By utilizing a 1 bit ΔΣ modulation with embedded finite-impulse response (FIR) filtering the high-pass modulation path does not suffer from the DCO gain nonlinearity, thus requiring absolute gain calibration only. The digital FIR filter in the high-pass modulation path not only suppresses quantization noise but also reduces noise coupling with time-interleaved switching of partitioned capacitors. A hybrid FIR filtering method is also employed for the low-pass modulation path to enhance the linearity of the fractional-N phase-locked loop (PLL). A 1.8 GHz two-point modulator based on a semi-digital PLL is implemented in 65 nm CMOS consuming 6.9 mW from a 1 V supply. At the divide-by-2 output frequency of 913.2 MHz, the error-vector magnitude (EVM) values of 1.79% and 1.63% are achieved with 1.08 Mb/s and 270 kb/s GMSK modulation respectively. When the 1.08 Mb/s GFSK modulation is performed with the same PLL parameters, the EVM value of 1.96% is achieved. <s> BIB005 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> Inductively Coupled Ditherless DCO <s> This paper describes a digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer. That is the PLL's second-order transfer function does not have a closed-loop zero. Such a PLL does not exhibit overshoots in the phase step response and achieves fast settling. Unlike the previously-reported peaking-free PLLs the proposed PLL implements the peaking-free loop filter directly in digital domain without requiring additional components. A time-to-digital converter (TDC) is implemented as a set of three binary phase-frequency detectors that oversample the timing error with time-varying offsets achieving a linear TDC gain and PLL bandwidth insensitive to the jitter condition. And a 9.2-GHz digitally-controlled LC oscillator (DCO) with transformer-based tuning realizes a predictable DCO gain set by a ratio between two digitally-controlled currents. The prototype 9.2-GHz-output digital PLL fabricated in a 65nm CMOS demonstrates a fast settling time of 1.58-μs with 690-kHz bandwidth. The PLL has a 3.477-psrms divided clock jitter and -120dBc/Hz phase noise at 10MHz offset while dissipating 63.9-mW at a 1.2-V supply. <s> BIB006
A DCO can limit the phase noise near the band edge from its quantization noise. To reduce to quantization noise, DCO dithering using a ∆∑ modulator has been used. Extra phase noise will be introduced when charge injected into the LC-tank through dithering if it were not properly retimed with a DCO clock BIB003 , BIB001 BIB002 , BIB005 [34] [35] BIB006 BIB004 . A capacitor divider used to reduce the effective tuning step-size through shunt and reduce series combination of fixed capacitors with digital tuning varactors. However, this technique consumes metal-oxide-metal (MOM) and metal-insulator-metal (MIM) capacitors. This would limit the achievable tuning range. Digital tuning varactors also can be applied to the source nods of the cross-coupled transistor to improve the tuning resolution. An inductively coupled DCO reported can solve the DCO problems BIB006 . Circuit design and inductor layout of an inductive coupled DCO is shown in Figure 7 .