Reduction of Power Consumption in FPGAs - An Overview <s> Copyright © 2012 MECS I.J. Information Engineering and Electronic Business, 2012, 5, 50-69 <s> In this paper we study the technology mapping problem of FPGA architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mapping depth of the circuit will not increase compared to the circuit with a single Vdd. We first design a single-Vdd mapping algorithm that achieves better power results than the latest published low-power mapping algorithms. We then show that our dual-Vdd mapping algorithm can further improve power savings by up to 11.6% over the single-Vdd mapper. In addition, we investigate the best low-Vdd/high-Vdd ratio for the largest power reduction among several dual-Vdd combinations. To our knowledge, this is the first work on dual-Vdd mapping for FPGA architectures. <s> BIB001 </s> Reduction of Power Consumption in FPGAs - An Overview <s> Copyright © 2012 MECS I.J. Information Engineering and Electronic Business, 2012, 5, 50-69 <s> Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult problem because both register binding and port assignment to reduce total multiplexer connectivity during high-level synthesis are NP-complete problems. We first formulate a k-cofamily-based register binding algorithm targeting the multiplexer optimization problem. We then further reduce the multiplexer width through an efficient port assignment algorithm. Experimental results show that we are 44% better overall than the left-edge register binding algorithm on the total usage of multiplexer inputs and 7% better than a bipartite graph-based algorithm. For large designs, we are able to achieve significantly better results consistently. After technology mapping, placement and routing for an FPGA architecture, it shows considerably positive impacts on chip area, delay and power consumption. <s> BIB002
A dual-VDD FPGA presents a more complex problem to FPGA CAD tools. CAD tools must select specific LUTs to operate at each supply voltage, and then assign these LUTs to logic blocks with the appropriate supply. To address these issues, algorithms for dual-VDD mapping and clustering have been developed in conjunction with the architecture work mentioned above BIB001 BIB002 . Pre-defined dual-VDD FPGA b) Configurable dual-VDD logic block According to authors in  , there are three major strategies in FPGA power consumption reduction. First, changes can be done at the system level (e.g. simplification of the algorithms used). Secondly, if the architecture of FPGA is already fixed, a designer may change the logic partitioning, mapping, placement and routing. Finally, if no changes at all are possible, enhancing operating conditions of the device may be still promising (this includes changes in the capacitance, the supply voltage, and the clock frequency). The various techniques used for reducing dynamic power are broadly covered under following schemes:  Reducing Dynamic Power on Clock Scheme  Reducing Logic Power  Reducing RAM Power  Reducing I/O Power The various techniques for dynamic power reduction under the above schemes are indicated in the following sections: