Hardware Decoders for Polar Codes: An Overview <s> C. Unrolled Decoders <s> In modern communication systems the required data rates are continuously increasing. High speed transmissions can easily generate throughputs far beyond 1 Tbit/s. To ensure error free communication, channel codes like Low-Density Parity Check (LDPC) codes are utilized. However state-of-the-art LDPC decoders can process only data rates in the range of 10 to 50 Gbit/s. This results in a gap in decoder performance which has to be closed. Therefore we propose a new ultra high speed LDPC decoder architecture. We show that our architecture significantly reduces the routing congestion which poses a big problem for fully parallel, high speed LDPC decoders. The presented 65nm ASIC implementation runs at 257 MHz and consumes an area of 12 mm2The resulting system throughput is 160 Gbit/s, it is the fastest LDPC decoder which has been published up to now. At the same time we show that extremely parallel architectures do not only increase the maximum throughput but also increase area and power efficiency in comparison to state-of-the-art decoders. <s> BIB001 </s> Hardware Decoders for Polar Codes: An Overview <s> C. Unrolled Decoders <s> Polar codes provably achieve the symmetric capacity of a memoryless channel while having an explicit construction. The adoption of polar codes however, has been hampered by the low throughput of their decoding algorithm. This work aims to increase the throughput of polar decoding hardware by an order of magnitude relative to successive-cancellation decoders and is more than 8 times faster than the current fastest polar decoder. We present an algorithm, architecture, and FPGA implementation of a flexible, gigabit-per-second polar decoder. <s> BIB002 </s> Hardware Decoders for Polar Codes: An Overview <s> C. Unrolled Decoders <s> This is the first in a two-part series of papers on unrolled polar decoders. In this paper (Part I), we present a family of architectures for hardware polar decoders using a reduced-complexity successive-cancellation decoding algorithm. The resulting fully-unrolled architectures are capable of achieving a coded throughput in excess of 400 Gbps on an FPGA, two orders of magnitude greater than current state-of-the-art polar decoders. Moreover, the proposed architectures are flexible in a way that makes it possible to explore the trade-off between resource usage and throughput. <s> BIB003
First applied to polar decoders in  and  , improved and generalized in BIB003 , unrolling is a technique that has been successfully applied to other types of decoders before, such as the high-speed LDPC decoders of BIB001 . An unrolled polar decoder instantiates processing elements for each and every node in the decoder tree of a specific polar code. This way, each processing element can process a different received vector. By inserting registers at each decoder stage, a new frame can be loaded and an estimated codeword output at every clock cycle. While this deeply-pipelined architecture provides very high throughput, it requires a significant amount of memory for data persistence that increases with the code length. As a compromise, an initiation interval I greater than 1 can be defined where a new frame is fed to the decoder every I clock cycles. The period at which estimated codewords are output is also of I clock cycles. Table I shows FPGA implementation results for both configurable and unrolled Fast-SSC decoders. The decoder of BIB002 was the first polar decoder to reach a throughput of 1 Gbps. The decoder of  is an improvement over BIB002 where support for other constituent codes was added to improve the throughput in decoding lower-rate codes. The last three rows of Table I are results for the unrolled decoders of BIB003 showing that throughputs in the hundreds of Gbps are achievable at the cost of area and resource usage. 