DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> Ring DCOs <s> This paper discusses novel architectures and circuit techniques for DPLLs. These include: methods to have a wide temperature range in the digitally controlled oscillator (DCO) for ring-oscillator based DPLLs, re-circulating time to digital converter (TDC) architecture to support a large input phase error range, efficient, modular, divider architectures that provide 50% output duty cycle, while allowing dynamic programmability of the division ratio, and fractional DPLL approaches for spur cancellation and low power operation. The techniques described in the paper have been used to build DPLLs for serializer-deserializer (SerDes), processor clock generation, and wireless connectivity applications in 65 nm and 45 nm CMOS. These implementations are briefly discussed and representative silicon results are presented. <s> BIB001 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> Ring DCOs <s> A highly-digital clock multiplication architecture that achieves excellent jitter and mitigates supply noise is presented. The proposed architecture utilizes a calibration-free digital multiplying delay-locked loop (MDLL) to decouple the tradeoff between time-to-digital converter (TDC) resolution and oscillator phase noise in digital phase-locked loops (PLLs). Both reduction in jitter accumulation down to sub-picosecond levels and improved supply noise rejection over conventional PLL architectures is demonstrated with low power consumption. A digital PLL that employs a 1-bit TDC and a low power regulator that seeks to improve supply noise immunity without increasing loop delay is presented and used to compare with the proposed MDLL. The prototype MDLL and DPLL chips are fabricated in a 0.13 μm CMOS technology and operate from a nominal 1.1 V supply. The proposed MDLL achieves an integrated jitter of 400 fs rms at 1.5 GHz output frequency from a 375 MHz reference clock, while consuming 890 μ W. The worst-case supply noise sensitivity of the MDLL is 20 fspp/mVpp which translates to a jitter degradation of 3.8 ps in the presence of 200 mV supply noise. The proposed clock multipliers occupy active die areas of 0.25 mm2 and 0.2 mm2 for the MDLL and DPLL, respectively. <s> BIB002 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> Ring DCOs <s> A reference-less half-rate digital clock and data recovery (CDR) circuit employing a phase-rotating phase-locked loop (PRPLL) as phase interpolator is presented. By implementing the proportional control in phase domain within the PRPLL, the proposed CDR decouples jitter transfer (JTRAN) bandwidth from jitter tolerance (JTOL) corner frequency, eliminates jitter peaking, and removes JTRAN dependence on bang-bang phase detector gain. Fabricated in a 90 nm CMOS process, the prototype CDR achieves error-free operation (BER <; 10-12) with PRBS data sequences ranging from PRBS7 to PRBS31. At 5 Gb/s, it consumes 13.1 mW power and achieves a recovered clock long-term jitter of 5.0 ps rms/44.0 ps pp when operating with PRBS31 input data. The measured JTRAN bandwidth is 2 MHz and JTOL corner frequency is 16 MHz. The CDR is tolerant to 110 mV pp of sinusoidal noise on the DCO supply voltage at the worst case noise frequency of 7 MHz. At 2.5 GHz, the PRPLL consumes 2.9 mW and achieves -134 dBc/Hz phase noise at 1 MHz frequency offset. The differential and integral non-linearity of its digital-to-phase transfer characteristic are within ±0.2 LSB and ±0.4 LSB, respectively. <s> BIB003
DCO reported with mechanism to digitally change its frequency and an oscillator core. There are two broad categories of oscillator used in ADPLL. The first is LC oscillator and the other is ring oscillator  BIB001 BIB002 . LC oscillators are area-intensive but produce much better phase noise while ring oscillators are very are-efficient but have relatively have high phase noise. A vast majority radio frequency application generally requires LC oscillator. On the other hand, CDR use ring oscillator and PLLs used for clock generation BIB003 . Figure 10 shows commonly used ring oscillator topologies. Figure 10 (a) is a single-ended ring oscillator. It used an odd number of inverter (usually 3 or 5). It is the most popular as it has the most power and area efficient topology. The frequency of this oscillator can be very wide range by using a digital to analog converter (DAC). Figure 10 (b) shows a differential amplifier stages can be used to build a fully differential ring oscillator. A differential ring oscillator (DRO) can use an even number of stages which can be a distinct advantage. DRO is useful in some applications that need an even number of output clock phase. One problem for using differential amplifiers stage is that by simply use means of a current mode, DAC hardly achieve the frequency control. Therefore, either capacitors or resistors inside the stages need to be tuned. Although this is feasible, it is hard to produce a large tuning range while keeping a fine resolution without increasing the area consume. To overcome this problem, a pseudo differential architecture show in Figure 10 (c) is proposed. A pseudo differential architecture is a single ended current controlled ring whose outputs are cross-coupled through latches. This it to force differential operation and ensure equally space output phases. The latch should be carefully sized because it adds power and phase noise. Dynamically decrease the latch size after the oscillation stabilizes will reduce latch power and improving the oscillator phase noise.