Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview <s> . The design point <s> We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables us to design complex analog cells from scratch within reasonable CPU time. Three different specification types are covered: strong constraints on the electrical performance of the cells, weak constraints on this performance, and design objectives. A mathematical cost function is proposed and a bunch of heuristics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique is also presented to yield designs with reduced variability in the performance parameters, under random variations of the transistor technological parameters. Several CMOS analog cells with complexity levels up to 48 transistors are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed methodology. <s> BIB001 </s> Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview <s> . The design point <s> Many real-world search and optimization problems involve inequality and/or equality constraints and are thus posed as constrained optimization problems. In trying to solve constrained optimization problems using genetic algorithms (GAs) or classical optimization methods, penalty function methods have been the most popular approach, because of their simplicity and ease of implementation. However, since the penalty function approach is generic and applicable to any type of constraint (linear or nonlinear), their performance is not always satisfactory. Thus, researchers have developed sophisticated penalty functions specific to the problem at hand and the search algorithm used for optimization. However, the most difficult aspect of the penalty function approach is to find appropriate penalty parameters needed to guide the search towards the constrained optimum. In this paper, GA's population-based approach and ability to make pair-wise comparison in tournament selection operator are exploited to devise a penalty function approach that does not require any penalty parameter. Careful comparisons among feasible and infeasible solutions are made so as to provide a search direction towards the feasible region. Once sufficient feasible solutions are found, a niching method (along with a controlled mutation operator) is used to maintain diversity among feasible solutions. This allows a real-parameter GA's crossover operator to continuously find better feasible solutions, gradually leading the search near the true optimum solution. GAs with this constraint handling approach have been tested on nine problems commonly used in the literature, including an engineering design problem. In all cases, the proposed approach has been able to repeatedly find solutions closer to the true optimum solution than that reported earlier. <s> BIB002 </s> Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview <s> . The design point <s> An optimization tool for radio frequency integrated circuits (RFICs) based on an elitist nondominated sorting genetic algorithm is introduced. It casts RF circuit synthesis as a multi-objective optimization problem and produces multiple solutions along the Pareto optimal front. Optimization is followed by sensitivity assessment wherein Monte Carlo simulations are performed for the Pareto points with respect to process, voltage, and temperature variations. The tool is validated in the synthesis of a 5.2-GHz direct-conversion receiver front-end that includes a common-gate differential low-noise amplifier, I/Q down-conversion mixers, and a quadrature voltage-controlled oscillator in a 250-nm SiGe BiCMOS process. <s> BIB003 </s> Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview <s> . The design point <s> The paper gives an overview of methods and tools that are needed to design and embed analogue and RF blocks in mixed-signal integrated systems on chip (SoC). The design of these SoCs is characterised by growing design complexities and shortening time to market constraints. This requires new mixed-signal design methodologies and flows, including high-level architectural explorations and techniques for analogue behavioural modelling. This also calls for new methods to increase analogue design productivity, such as the reuse of analogue blocks as well as the adoption of analogue and RF circuit and layout synthesis tools. Also, more detailed modelling and verification tools are needed that can analyse signal integrity and crosstalk problems, especially noise coupling problems caused by the embedding of the analogue circuits in a digital environment. Solutions that already exist today are presented, and challenges that still remain to be solved are outlined. <s> BIB004 </s> Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview <s> . The design point <s> Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based global optimization algorithm to generate the nominal pareto front efficiently using a simulator-in-a-loop approach. The solutions on this pareto front combined with efficient Monte Carlo approximation ideas are then used to compute the yield-aware pareto fronts. We show experimental results for both the nominal and yield-aware pareto fronts for power and phase noise for a voltage controlled oscillator (VCO) circuit. The presented methodology computes yield-aware pareto fronts in approximately 5-6 times the time required for a single circuit synthesis run and is thus practically efficient. We also show applications of yield-aware paretos to find the optimal VCO circuit to meet the system level specifications of a phase locked loop. <s> BIB005 </s> Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview <s> . The design point <s> This paper presents two simulation-based methods for the calculation of the feasible performance values of analog integrated circuits. The first method computes the Pareto-optimal tradeoffs of competing performances at full simulator accuracy. Additionally, it identifies and evaluates the technological and structural constraints that prevent further performance improvement. The second method computes linear approximations to the feasible performance regions of circuits with a large number of performances. Both techniques allow a comparison of different circuit topologies with respect to their performance capabilities and contribute to hierarchical circuit sizing. The presented methods are validated by experimental results of Pareto-front computation and feasible performance region computation of operational amplifiers and hierarchical sizing of filters. <s> BIB006 </s> Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview <s> . The design point <s> One of the main tasks in analog design is the sizing of the circuit parameters, such as transistor lengths and widths, in order to obtain optimal circuit performances, such as high gain or low power consumption. In most cases one performance can only be optimized at cost of others, therefore a sizing must aim at an optimal trade-off between the important circuit performances. In this paper we present a new deterministic method to calculate the complete range of performance trade-offs, the so-called Pareto-optimal front, of a given circuit topology. Known deterministic methods solve a set of constrained multi-objective optimization problems independently of each other. The presented method minimizes a set of Goal Attainment (GA) optimization problems simultaneously. In a parallel algorithm, the individual GA optimization processes compare and exchange their iterative solutions. This leads to a significant improvement in the efficiency and quality of analog trade-off design. <s> BIB007 </s> Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview <s> . The design point <s> This paper presents a 3rd-order continuous-time Delta-Sigma modulator with a resolution of 10 bits for a 10 MHz signal bandwidth. It is designed in a standard 0.18 μm CMOS technology and consumes only 6 mW. After the design/selection of the topologies for the integrators, comparator and D/A converters, optimal sizing of the complete modulator was ensured by using a hierarchical bottom-up, multi-objective evolutionary design methodology. With this methodology, a set of Pareto-optimal modulator designs is generated by using Pareto-optimal performance solutions of the hierarchically decomposed lower-level subblocks. From the generated Pareto-optimal design set, a final optimal design is chosen that complies with the specifications for the 802.11a/b/g WLAN standard and has minimal power consumption. <s> BIB008 </s> Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview <s> . The design point <s> We present a novel heuristic for optimizing analog circuit performances. It deals with generating the Pareto front using the topological properties of the feasible solution space. This heuristic allows us generating optimal values of circuit parameters in reduced computation time and memory consumption. Unlike basic metaheuristics, it does not need optimization background from the user in order to be easily adapted to different applications. It can thus be smoothly integrated into an automated design flow. This novel approach enables us to further improve (good) performances that were already reached using other optimizing techniques. Robustness of the algorithm was proved using specific difficult test problems. <s> BIB009 </s> Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview <s> . The design point <s> Multimode Pareto-optimal fronts are presented. This is a novel concept that can be key in the design of reconfigurable analogue circuits, because it contains information not only on the trade-offs among the circuit performances, but also on its reconfiguration capabilities. A method to generate the front, relying on evolutionary optimisation, and a general dominance sorting algorithm that guides the optimisation, are both described. <s> BIB010 </s> Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview <s> . The design point <s> This paper investigates a hybrid evolutionary-based design system for automated sizing of analog integrated circuits (ICs). A new algorithm, called competitive co-evolutionary differential evolution (CODE), is proposed to design analog ICs with practical user-defined specifications. On the basis of the combination of HSPICE and MATLAB, the system links circuit performances, evaluated through electrical simulation, to the optimization system in the MATLAB environment, once a circuit topology is selected. The system has been tested by typical and hard-to-design cases, such as complex analog blocks with stringent design requirements. The results show that the design specifications are closely met, even in highly-constrained situations. Comparisons with available methods like genetic algorithms and differential evolution, which use static penalty functions to handle design constraints, have also been carried out, showing that the proposed algorithm offers important advantages in terms of optimization quality and robustness. Moreover, the algorithm is shown to be efficient. <s> BIB011 </s> Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview <s> . The design point <s> The trade-off between competing design objectives is often decided at the beginning of the analog sizing process by assigning weights to the design objectives. Architectural design, however, requires the knowledge of all possible optimal trade-offs of a building block. Methods for Pareto optimization provide the set of all optimal trade-offs, the so-called Pareto front. The next generation of analog Pareto optimization tools additionally has to consider the manufacturing variations. This paper describes an approach to this challenging problem. First, analog Pareto optimization will be developed as a set of specific nonlinear programming problems that provide a discretization of the Pareto front of competing performance features. Second, a general problem formulation to consider manufacturing variations and operating ranges of circuit parameters in analog Pareto optimization will be presented. Third, an efficient solution approach to the resulting tolerance Pareto optimization problem will be described. It is based on a combination of nominal Pareto optimization and realistic worst-case analysis on discrete Pareto points. It provides high efficiency at acceptable loss in accuracy. Copyright © 2008 John Wiley & Sons, Ltd. <s> BIB012
A x is said to be non-dominated if there is no other design that dominates it. The non-dominated set of the entire feasible performance space is known as the Pareto-optimal front. The concepts of dominance and Pareto-optimal front are illustrated in Figure 1 for a two-dimensional performance space. In fact, the weighted sum approach above corresponds to obtaining a single point of the POF in Figure 1 . In principle, it is possible to generate the POF by repetitively applying the same approach with different values of the weights. One problem with this method is that it cannot provide solutions in possible non-convex parts of the Pareto front because a convex weighted sum of objectives converges only to the convex parts of the Front. For instance, for k=2, the optimization problem in (1) is transformed as follows: As illustrated in Figure 2a , Equation (2) represents a straight line in the plane 1 2 ( , ) f f . Thus minimizing eq f is nothing but minimizing the constant c of equation (3): It is clear, as it is shown in Figure 2b , that varying the weighting coefficients 1 2 ( , ) ω ω cannot allow sweeping the entire Pareto front. Besides, Figure 2c shows how much, in some cases, obtained solutions are sensitive to a small variation of these weightings BIB009 . Moreover, the weighting approach does not ensure, a priori, a homogeneous distribution of designs over the Pareto front. That is, a uniform assignment of weights does not mean that the Pareto front will be uniformly sampled. More importantly, as the number of samples increases, the approach becomes less efficient than the application of a truly multi-objective optimization algorithm. In most cases, the POF generation problem in AMS/RF circuits has been addressed by means of evolutionary computation algorithms BIB003 , BIB009 - BIB010 . An exception is the approach reported in BIB006 , that makes use of the normal boundary intersection method. The biggest drawback of this method is that it might get stuck at local minima due to the optimization algorithms applied. An improvement, reported in BIB007 , is to try to escape from local minima thanks to the exchange of solutions between the optimization algorithms that are executed in parallel. IV. CONSTRAINT HANDLING AMS/RF design problems are usually heavily constrained optimization problems. The quality of the final results strongly depends on the mechanism used to handle A first approach is to simply reject candidate individuals that do not meet the constraints. Though its implementation is very simple, it, however, exhibits an important drawback. On one hand, increasingly demanding performance specifications impose severe constraints to circuit sizing methods. On the other hand, the design variable space has usually a large number of dimensions. It infers from these two trends that the feasible design space can represent only a small region of the complete design space. It may therefore happen that when the initial population is sampled in the design space, no individual is feasible and, hence, the algorithm gets stuck. Another widely used alternative is the static penalty function (PF) approach. In this method, the constrained optimization problem is transformed into an unconstrained one by minimizing the following function: where ( , ) d x F is a distance metric of the infeasible point to the feasible region F. It may simply be zero if no constraint violation occurs and is a positive number, otherwise. The definition of this distance metric includes the penalty coefficients that are used to stress the importance of a particular constraint violation over others. W is a weight coefficient to set a global importance of the constraints with respect to the objective functions. A major problem is that the results are sensitive to the values of the penalty coefficients and there is no general rule for setting them. A possible solution to palliate this problem has been published in BIB011 , where the optimization problem is transformed into the minimization of an augmented Lagrangian and a competitive co-evolution process automatically adapts the Lagrange multipliers. One of the most effective techniques reported so far is the selection-based approach BIB002 . In this approach, the selection rules for a couple of candidate solutions in the population are: Precursor of this technique was the constraint handling mechanism in BIB001 , essentially based on the same principle, although intended to compare a parent and a child solution, as the optimization algorithm was derived from simulated annealing. The selection mechanism is based on using a different cost function sign at the feasible and infeasible region. The static penalty function approach can be easily extended to the multi-objective case by just adding a weighted sum of the objective function values to the fitness function. However, this approach suffers from the same drawbacks already discussed for the single-objective case. The selection-based approach can be easily extended to the multi-objective case by just using a dominance comparison criterion instead of the objective function comparison. Candidate solutions obey the same selection aforementioned rules (the case of a single-objective problem), but when two solutions are feasible, respective objectives have to be compared: 1. if one of them dominates the other, choose the nondominated one; 2. if no solution dominates each other, choose one of them randomly. V. CHALLENGES Unlike the simple mathematical functions that are usually posed as benchmarks in the EC field, the fitness function evaluation in AMS/RF design problems is comparatively much more expensive, especially if a high level of accuracy is desired. Moreover, many design automation approaches are dealing with simulation-based optimization. Therefore, the investigation of more efficient algorithms that can provide a better trade-off of exploration (global search) and exploitation (local search) with fewer evaluations of the fitness function remains an important challenge. Besides the constraint handling challenge already discussed, the efficient and accurate computation of the Pareto front constitutes a major challenge. Regarding constraints, and although problems of penalty function approaches are avoided, the calculation of the smallest constraint violation when both solutions are infeasible is still built as a weighted sum of the violation of each constraint. Experiments show that the convergence and extension of the POF may be heavily affected by the weights assigned to the constraint violations. An additional problem appears, especially in modern deep submicron technologies, due to the increasing random and systematic process variations. Process parameter variations map into variations of constraints and objectives, affecting the yield of manufactured circuits BIB004 . This problem may become especially dangerous in multi-objective optimization problems, because the effort of optimization algorithms to improve each objective as much as possible may severely increase the impact that process parameter variances pose on the objectives. That is, the obtained POF may be very good at the nominal design point but such point may be at the tail of the corresponding probability density function when parametric variations are considered. Therefore, incorporation of variability information in the optimization process becomes increasingly important BIB012 - BIB005 . Again, variability and yield assessment is a costly process and their incorporation must consider appropriate trade-offs of accuracy/efficiency on the fitness evaluation side (e.g., from the high-accuracy, low-efficiency of Montecarlo-based methods to the low-accuracy, high-efficiency of regressionbased methods) and more efficient search procedures on the optimization engine side. In order to compare performances of different multiobjective optimization algorithms or even compare the sets of Pareto points from two independent runs of the same algorithm (e.g., with different algorithm parameter settings), appropriate POF quality evaluation metrics are needed  . POF evaluation and comparison criteria, which include different features of the POF, have been investigated extensively in the evolutionary computation (EC) field  . However, not all POF quality metrics seem to be suitable to analog design problems, and certainly not all needs of multiobjective analog synthesis are appropriately represented by the available metrics in the EC literature. Evaluation metrics basically address convergence and diversity. Most convergence metrics use the so-called true POF. Unlike mathematical benchmarks commonly used, the true POF is unknown in AMS/RF design problems. Moreover, the extent or a controlled non-uniformity of the POF may be important, aspects that have received little attention in the EC literature  . Most practical circuits are too complex to consider their design following a flat approach. Therefore, they require the application of hierarchical decomposition and design techniques. An important research area is the model of application of multi-objective optimization approaches in hierarchical problems. A model of application is the so-called multi-objective bottom-up optimization approach BIB008 , in which the POF of the different blocks are composed bottomup across the different hierarchical levels. Some conditions must be met for such composition and a number of interconnection constraints arise. However, the POFs can also be used as feasibility hyper-surfaces for an optimal top-down hierarchical design approach.