Multi-Channel Neural Recording Implants: A Review <s> Multistage Amplifiers <s> There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff. <s> BIB001 </s> Multi-Channel Neural Recording Implants: A Review <s> Multistage Amplifiers <s> Two thin-film microelectrode arrays with integrated circuitry have been developed for extracellular neural recording in behaving animals. An eight-site probe for simultaneous neural recording and stimulation has been designed that includes on-chip amplifiers that can be individually bypassed, allowing direct access to the iridium sites for electrical stimulation. The on-probe amplifiers have a gain of 38.9 dB, an upper-cutoff frequency of 9.9 kHz, and an input-referred noise of 9.2 /spl mu/V /sub rms/ integrated from 100 Hz to 10 kHz. The low-frequency cutoff of the amplifier is tunable to allow the recording of field potentials and minimize stimulus artifact. The amplifier consumes 68 /spl mu/W from /spl plusmn/1.5 V supplies and occupies 0.177 mm/sup 2/ in 3 /spl mu/m features. In vivo recordings have shown that the preamplifiers can record single-unit activity 1 ms after the onset of stimulation on sites as close as 20 /spl mu/m to the stimulating electrode. A second neural recording array has been developed which multiplexes 32 neural signals onto four output data leads. Providing gain on this array eliminates the need for bulky head-mounted circuitry and reduces motion artifacts. The time-division multiplexing circuitry has crosstalk between consecutive channels of less than 6% at a sample rate of 20 kHz per channel. Amplified, time-division-multiplexed multichannel neural recording allows the large-scale recording of neuronal activity in freely behaving small animals with minimum number of interconnect leads. <s> BIB002 </s> Multi-Channel Neural Recording Implants: A Review <s> Multistage Amplifiers <s> We have developed a fully differential low-power low-noise preamplifier with multiple adjustable parameters for biopotential and neural recording applications. Common mode feedback has been utilized to guarantee the amplifier functionality by forcing the output DC level to a desired voltage. A switch is added to the output to achieve fast settling time in case the amplifier is saturated. The amplifier has been implemented in the AMI 1.5-mum 2M2P standard CMOS process and occupies 0.201 mm2 on chip. The amplifier current consumption is 8 muA at plusmn1.7 V supply, with two measured AC gains of 39.3 dB and 45.6 dB. The low cutoff frequency is 4-bit programmable from 0.015 Hz to 700 Hz. The high cutoff frequency can be adjusted from 120 Hz to 12 kHz at negligible load and 40 Hz to 4 kHz with a 2 pF active probe loading. The measured input referred noise is 3.6 muV over 20 Hz ~ 10 kHz. The amplifier also provides rail-to-rail input DC range, maximum input offset of 0.7 mV, common mode tuning range of plusmn600 mV, and output swing of plusmn0.9 V with minimum distortion. <s> BIB003 </s> Multi-Channel Neural Recording Implants: A Review <s> Multistage Amplifiers <s> A current biased pseudo-resistor for implantable extracellular neural signal recording applications is introduced in this work. The pseudo-resistor, which is biased in the subthreshold region, is able to realize a very large resistance while keeping the silicon area small. A wide range of resistances can also be implemented by changing the bias current. Issues concerning the linearity of the pseudo-resistor and the frequency response of the pseudo-resistor bias are discussed in this paper. The chips were fabricated in a 0.5 micron 3M2P CMOS process and the test results show that the current biasing method is able to realize more reliable resistance than the voltage biasing method. <s> BIB004 </s> Multi-Channel Neural Recording Implants: A Review <s> Multistage Amplifiers <s> Power and chip area are the most important parameters in designing a neural recording system in vivo. This paper reports a design methodology for an optimized integrated neural recording system. Electrode noise is considered in determining the ADC's resolution to prevent over-design of the ADC, which leads to unnecessary power consumption and chip area. The optimal transconductance and gain of the pre-amplifiers, which minimizes the power-area product of the amplifier, are mathematically derived. A numerical example using actual circuit parameters is shown to demonstrate the design methodology. A tradeoff between the power consumption of the system and the chip area in terms of the multiplexing ratio is investigated and the optimal number of channels per ADC is selected to achieve the minimum power-area product for the entire system. Following the proposed design methodology, a chip has been designed in 0.35 mum CMOS process, with the multiplexing ratio of 16:1, resulting in total chip area of 2.5 mm times 2.0 mm and power consumption of 5.3 mW from plusmn1.65 V. <s> BIB005 </s> Multi-Channel Neural Recording Implants: A Review <s> Multistage Amplifiers <s> This paper reports an implantable microsystem capable of recording neural activity simultaneously on 64 channels, wirelessly transmitting spike occurrences to an external interface. The microsystem also allows the user to examine the spike waveforms on any channel with 8 bit resolution. Signals are amplified by 60 dB with a programmable bandwidth from < 100 Hz to 10 kHz. The input-referred noise is 8 ?Vrms. The channel scan rate for spike detection is 62.5 kS/sec using a 2 MHz clock. The system dissipates 14.4 mW at 1.8 V, weighs 275 mg, and measures 1.4 cm 1.55 cm. <s> BIB006 </s> Multi-Channel Neural Recording Implants: A Review <s> Multistage Amplifiers <s> This paper presents a fully integrated programmable biomedical sensor interface chip dedicated to the processing of various types of biomedical signals. The chip, optimized for high power efficiency, contains a low noise amplifier, a tunable bandpass filter, a programmable gain stage, and a successive approximation register analog-to-digital converter. A novel balanced tunable pseudo-resistor is proposed to achieve low signal distortion and high dynamic range under low voltage operations. A 53 nW, 30 kHz relaxation oscillator is included on-chip for low power consumption and full integration. The design was fabricated in a 0.35 μm standard CMOS process and tested at 1 V supply. The analog front-end has measured frequency response from 4.5 mHz to 292 Hz, programmable gains from 45.6 dB to 60 dB, input referred noise of 2.5 μV rms in the amplifier bandwidth, a noise efficiency factor (NEF) of 3.26, and a low distortion of less than 0.6% with full voltage swing at the ADC input. The system consumes 445 nA in the 31 Hz narrowband mode for heart rate detection and 895 nA in the 292 Hz wideband mode for ECG recording. <s> BIB007 </s> Multi-Channel Neural Recording Implants: A Review <s> Multistage Amplifiers <s> This paper presents a power efficient architecture for a neural spike recording channel. The channel offers a selfcalibration ::: operation mode and can be used both for signal tracking (to raw digitize the acquired neural waveform) and ::: feature extraction (to build a PWL approximation of the spikes in order to reduce data bandwidth on the RF-link). The ::: neural threshold voltage is adaptively calculated during the spike detection period using basic digital operations. The ::: neural input signal is amplified and filtered using a LNA, reconfigurable Band-Pass Filter, followed by a fully ::: reconfigurable 8-bit ADC. The key element is the ADC architecture. It is a binary search data converter with a SCimplementation. ::: Due to its architecture, it can be programmed to work either as a PGA, S&H or ADC. In order to allow ::: power saving, inactive blocks are powered off depending on the selected operation mode, ADC sampling frequency is ::: reconfigured and bias current is dynamically adapted during the conversion. Due to the ADC low input capacitance, the ::: power consumption of the input LNA can be decreased and the overall power consumption of the channel is low. The ::: prototype was implemented using a CMOS 0.13um standard process, and it occupies 400um x 400um. Simulations from ::: extracted layout show very promising results. The power consumption of the complete channel for the signal tracking ::: operations is 2.8uW, and is increased to 3.0uW when the feature extraction operation is performed, one of the lowest ::: reported. <s> BIB008 </s> Multi-Channel Neural Recording Implants: A Review <s> Multistage Amplifiers <s> In this paper, an in-depth design methodology for fully-integrated tunable low-noise amplifiers for neural recording applications is presented. In this methodology, a modified system design is proposed to optimize the area/noise/linearity performance. A novel linear pseudo-resistor with a wide range of tunability is also proposed. As a case study, a low-noise tunable and reconfigurable amplifier for neural recording applications is designed and simulated in a 0.18 $\mu{\rm m}$ complementary metal–oxide–semiconductor process in all process corners. Simulated characteristics of the amplifier include tunable gain of 54 dB, tunable high-cutoff frequency of 10 kHz, programmable low-cutoff frequency ranging from 4 to 300 Hz, and power consumption of 20.8 $\mu{\rm W}$ at 1.8 V. According to postlayout simulations, integrated input-referred noise of the amplifier is 2.6 $\mu{\rm V}_{\rm rms}$ and 2.38 $\mu{\rm V}_{\rm rms}$ over the 0.5 Hz–50 kHz frequency range for low-cutoff frequency of 4 and 300 Hz, respectively. The amplifier also provides output voltage swing of 1 ${\rm V}_{\rm P-P}$ with total harmonic distortion of -46.24 dB at 300 Hz, and -45.97 dB at 10 kHz. <s> BIB009 </s> Multi-Channel Neural Recording Implants: A Review <s> Multistage Amplifiers <s> This paper describes an activity-dependent intracortical microstimulation (ICMS) system-on-chip (SoC) that converts extracellular neural spikes recorded from one brain region to electrical stimuli delivered to another brain region in real time in vivo. The 10.9-mm 2 SoC incorporates two identical 4-channel modules, each comprising an analog recording front-end with total input noise voltage of 3.12 μV rms and noise efficiency factor (NEF) of 2.68, 5.9-μW 10-bit successive approximation register analog-to-digital converters (SAR ADCs), 12.4-μW digital spike discrimination processor, and a programmable constant-current microstimulating back-end that delivers up to 94.5 μA with 6-bit resolution to stimulate the cortical tissue when triggered by neural activity. For autonomous operation, the SoC also integrates biasing and clock generation circuitry, frequency-shift-keyed (FSK) transmitter at 433 MHz, and dc-dc converter that generates a power supply of 5.05 V for the microstimulating back-end from a single 1.5-V battery. Measured results from electrical performance characterization and biological experiments with anesthetized rats are presented from a prototype chip fabricated in AMS 0.35 μm two-poly four-metal (2P/4M) CMOS. A noise analysis for the selected low-noise amplifier (LNA) topology is presented that obtains a minimum NEF of 2.33 for a practical design given the technology parameters and power supply voltage. Future considerations in the SoC design with respect to silicon area and power consumption when increasing the number of channels are also discussed. <s> BIB010 </s> Multi-Channel Neural Recording Implants: A Review <s> Multistage Amplifiers <s> This paper describes a micropower low-noise neural front-end circuit capable of recording epileptic fast ripples (FR). The front-end circuit consisting of a preamplifier followed by a 6th-order bandpass filter is designed for signal sensing in a future epileptic deep brain stimulator. A current-splitting technique is combined with an output-branch current scaling technique in a folded-cascode amplifier structure to improve the noise and power tradeoff in the preamplifier. In measurements, the preamplifier exhibits 39.4 dB DC gain, 0.36 Hz to 1.3 kHz of -3 dB bandwidth, and 3.07 μVrms total input-referred noise while consuming 2.4 μW from a 2.8 V power supply provided by an on-chip regulator circuit. A noise efficiency factor (NEF) of 3.09 is achieved with minimal power consumption and is one of the lowest published to date. The 6th-order follow-the-leader feedback elliptic bandpass filter passes FR signals and provides -110 dB/decade attenuation to out-of-band frequency components. In measurements, the entire front-end circuit achieves a mid-band gain of 38.5 dB, a bandwidth from 250 to 486 Hz, and a total input-referred noise of 2.48 μVrms while consuming 4.5 μW from the 2.8 V power supply. The front-end NEF achieved is 7.6. To the authors' knowledge, the proposed epileptic seizure- detection system is the first to achieve the FR-recording functionality. The chip is fabricated in a standard 0.6 μm CMOS process. Die size is 0.45 mm2. <s> BIB011 </s> Multi-Channel Neural Recording Implants: A Review <s> Multistage Amplifiers <s> A compact and low-distortion neural recording amplifier is presented. The amplifier consists of two stages of amplification using capacitive feedback to set a gain of 54dB. To minimize flicker noise in the 1st stage, internal chopping is utilized at the folded node of the OTA, resulting in flicker noise contribution from the input differential pair only. A low-distortion constant-V GS feedback circuit to set a low frequency high-pass pole is introduced. It is less sensitive to the output swing than the conventional sub-threshold MOS circuit. The amplifier fabricated in a standard 1.2V 0.13µm CMOS technology occupies 125×175µm2 and achieves an NEF of 4.4, an input-referred noise of 4.7µV over a 5kHz bandwidth, a CMRR of 75dB and a THD of −50dB for a 0.6V output swing. <s> BIB012 </s> Multi-Channel Neural Recording Implants: A Review <s> Multistage Amplifiers <s> A system-on-chip (SoC) neural recording interface with 64 channels, 64 16-tap programmable mixed-signal FIR filters and a fully integrated 915 MHz OOK/FSK PLL-based wireless transmitter is presented. Each recording channel has a fully differential amplifier with 54 dB gain and utilizes a tunable low-distortion subthreshold MOS-resistor to reject DC offsets with an input-referred noise of 6.5 μV and a CMRR of 75 dB. Each channel contains a modified 8-bit SAR ADC with an ENOB of 7.8-bits and can provide analog-digital multiplication by modifying the the sampling phase of the ADC. It is used in conjunction with 12-bit digital adders and registers to implement 64 programmable transposed FIR filters. The 915 MHz FSK/OOK transmitter offers data rates up to 1.5 Mbps and a maximum output power of 0 dBm. The 4×3 mm2 chip fabricated in a 0.13 μm CMOS process dissipates 5.03 mW from a 1.2 V supply. Experimental measurements characterize the electrical performance of the wireless SoC. In vivo measurement results from freely moving rats are also presented. <s> BIB013 </s> Multi-Channel Neural Recording Implants: A Review <s> Multistage Amplifiers <s> A low-distortion super-GOhm subthreshold MOS resistor is designed, fabricated and experimentally validated. The circuit is utilized as a feedback element in the body of a two-stage neural recording amplifier. Linearity is experimentally validated for 0.5 Hz to 5 kHz input frequency and over 0.3 to 0.9 V output voltage dynamic range. The implemented pseudo resistor is also tunable, making the high-pass filter pole adjustable. The circuit is fabricated in 0.13-μm CMOS process and consumes 96 nW from a 1.2 V supply to realize an over 500 GΩ resistance. <s> BIB014 </s> Multi-Channel Neural Recording Implants: A Review <s> Multistage Amplifiers <s> An ultra wideband (UWB) 64-channel responsive neural stimulator system-on-chip (SoC) is presented. It demonstrates the first on-chip neural vector analyzer capable of wirelessly monitoring magnitude, phase and phase synchronization of neural signals. In a closed-loop, abnormal phase synchrony triggers the programmable-waveform biphasic current-mode neural stimulator. To implement these functionalities, the SoC integrates 64 neural recording amplifiers with tunable switched-capacitor (SC) bandpass filters, 64 multiplying 8-bit SAR ADCs, 64 programmable 16-tap FIR filters, a tri-core CORDIC processor, 64 biphasic current stimulation channels, and a 3.1-10.6 GHz UWB wireless transmitter onto a 4 mm × 3 mm 0.13 μm CMOS die. To minimize both the area and power dissipation of the SoC, the SAR ADC is re-used as a multiplier for FIR filtering and as a DAC and duty cycle controller for the biphasic neural stimulator. The SoC has been validated in the early detection and abortion of seizures in freely moving rodents on-line and in early seizure detection in humans off-line. <s> BIB015 </s> Multi-Channel Neural Recording Implants: A Review <s> Multistage Amplifiers <s> A 65 nm CMOS 4.78 mm 2 integrated neuromodulation SoC consumes 348 µA from an unregulated 1.2 V to 1.8 V supply while operating 64 acquisition channels with epoch compression at an average firing rate of 50 Hz and engaging two stimulators with a pulse width of 250 µs/phase, differential current of 150 µA, and a pulse frequency of 100 Hz. Compared to the state of the art, this represents the lowest area and power for the highest integration complexity achieved to date. <s> BIB016 </s> Multi-Channel Neural Recording Implants: A Review <s> Multistage Amplifiers <s> Multichannel neural amplifiers are commonly implemented with a shared reference whose input impedance is several times lower than that of the corresponding signal inputs. This huge impedance mismatch significantly degrades the total common mode rejection ratio (TCMRR) regardless of the amplifier’s intrinsic CMRR (ICMRR). This study reports a multichannel neural amplifier system that eliminates this impedance mismatch problem by using single-ended CMOS-inverter-based preamplifiers for both the reference and signal inputs. A common-mode feedback (CMFB) loop through the supply rails of the preamplifiers is implemented to enhance their ac input common mode range to $220\;\text{mV}_\text{pp}$ and their ICMRR to more than 90 dB at low frequencies. The ICMRR is maintained above 80 dB up to 1 kHz by minimizing the load drive mismatch between the signal and reference preamplifiers. Implemented in a CMOS 65 nm process, this 16-channel amplifier system operates at 1 V and consumes $118\; \upmu\text{W}$ . It has input referred noise of $4.13\; \upmu\text{V}_\text{rms}$ , leading to a noise efficiency factor (NEF) and a power efficiency factor (PEF) of 3.19 and 10.17, respectively. In vivo recordings of cortical neurons of a macaque were successfully acquired, demonstrating the ability of the amplifier to acquire neural signals in an unshielded environment. <s> BIB017
In the literature, there are reports of single stage amplifier designs for biomedical implants that are mostly implemented as capacitive coupled with the microelectrode sensors  BIB002 BIB004 BIB003 BIB006 . One-stage neural amplifiers face the following challenges. In the case of DC-coupled neural amplifiers that are generally designed as open loop structures with high gain, the midband gain is very sensitive to process variation. In addition, the gain variation causes undesired variation in the low-cutoff frequency ( f L ). On the other hand, in the case of AC-coupled, very popular and commonly-used conventional CFN topology shown in Figure 3a , has the following drawbacks. The midband gain (A M ) of such an amplifier is obtained by C I C F . For a specific and fixed value of A M , the minimum possible value is chosen for C F to minimize the C I and, consequently, the chip area. The C F is usually chosen in the range 100-200 fF to be larger than the neighborhood parasitic capacitances. Therefore, to have a high gain, the C I has to be increased A M times greater than the C F , which results in a huge chip area and very low input impedance. Also, the latter factor itself causes attenuation of the neural signal in the input of the amplifier, which in turn reduces the total gain of the amplifier and the CMRR. Furthermore, in the scaled and advanced technologies, the transconductance (g m ) reduces due to short-channel effects of MOS transistors, which creates challenges and difficulties in designing high gain OTAs. To overcome these challenges, amplifiers are designed in two or three stages in the AFE of the neural recording systems. Utilizing AC-coupled multistage amplifiers reduces the input capacitors' value that leads to a reduction in the chip area at the expense of slightly increasing the power consumption. A few examples of such multistage amplifiers are provided in BIB005 BIB008  BIB016 BIB017 . In order to have low IRN, the first stage is designed as a low noise amplifier (LNA). The other stages (i.e., the second and third stages) are designed to provide enough gain and linearity. Also, tuning the gain, as well as the f L and f H , is carried out in the second or third stages. Although it may be observed in BIB007 that f L and f H are tuned in the first stage of the neural amplifier, this is not desirable as it affects the IRN. It has been proven by Isoperimetric Theorem in mathematics that for two or three-stage AC-coupled amplifiers (assuming that the main area of the neural amplifier is consumed by the capacitors), the maximum total gain for a specific area or the minimum area for a specific total gain is obtained when the gains at all stages are equal. However, further design considerations, such as lowering the IRN, causes the first stage of the neural amplifier, which is an LNA, to be designed with higher gain compared to the other stages BIB007 BIB009 . Another challenge seen in both single-stage and multistage amplifiers (in the second or third stage) is that the high output swing of the OTA varies the feedback resistance of the MOS pseudoresistor in the CFN topology of Figure 3a . This variation increases the non-linearity of the amplifier and consequently increases the distortion and makes the high-pass pole frequency variable with time BIB012 . Figure 5a illustrates a solution to this problem that is exploited in BIB013 BIB014 BIB015 . In these designs, the front-end amplifiers are composed of two stages, in which the second stage utilizes a source follower such as that in Figure 5a to provide a constant voltage for the gate-source terminals of the MOS pseudoresistors, while the output swing is high. This technique increases the linearity of the amplifier significantly. Nowadays, many designed and proposed front-end amplifiers have two or three stages. The design in Figure 5b utilizes of two stages BIB013 BIB014 . The gain of the first and second stages are as 39 and 14, respectively. To increase the linearity in the first stage, NMOS transistors are used as pseudoresistors and in the second stage as shown in this figure, NMOS and PMOS transistors accompanied by a source follower, are used. The pseudoresistors are all thick-oxide transistors, which provide higher resistance compared to the standard CMOS transistors. The high-pass pole frequency is adjusted with the bias current of the source followers in the second stage. This happens while, the low-pass pole frequency is determined by C L . This extra and large capacitor is used in BIB001 BIB010 BIB011 , which, in all of these designs, causes an overhead in the consuming area. The architecture shown in Figure 6a utilizes three stages for amplification BIB009 . The first stage is an LNA, the second stage is band-pass filter where the low and high-cutoff frequencies are adjusted. The third stage behaves like a variable gain amplifier (VGA) and a buffer. The gains of the first, second, and third stages are 50, 2, and 5, respectively. As illustrated in Figure 6b , the second stage utilizes a current-controlled pseudoresistor, that uses a cross-coupled architecture to provide a symmetrical resistance with high linearity in the range of 0.2 V. This voltage is at the voltage swing range of the second stage. The low-cutoff frequency of these circuits is determined by the bias current of the current sources, while altering the value of C L2 tunes the high-cutoff frequency. 