Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> 1) Digital memory cells: A viable solution to the <s> We present a model of spike-driven synaptic plasticity inspired by experimental observations and motivated by the desire to build an electronic hardware device that can learn to classify complex stimuli in a semisupervised fashion. During training, patterns of activity are sequentially imposed on the input neurons, and an additional instructor signal drives the output neurons toward the desired activity. The network is made of integrate-and-fire neurons with constant leak and a floor. The synapses are bistable, and they are modified by the arrival of presynaptic spikes. The sign of the change is determined by both the depolarization and the state of a variable that integrates the postsynaptic action potentials. Following the training phase, the instructor signal is removed, and the output neurons are driven purely by the activity of the input neurons weighted by the plastic synapses. In the absence of stimulation, the synapses preserve their internal state indefinitely. Memories are also very robust to the disruptive action of spontaneous activity. A network of 2000 input neurons is shown to be able to classify correctly a large number (thousands) of highly overlapping patterns (300 classes of preprocessed Latex characters, 30 patterns per class, and a subset of the NIST characters data set) and to generalize with performances that are better than or comparable to those of artificial neural networks. Finally we show that the synaptic dynamics is compatible with many of the experimental observations on the induction of long-term modifications (spike-timing-dependent plasticity and its dependence on both the postsynaptic depolarization and the frequency of pre- and postsynaptic neurons). <s> BIB001 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> 1) Digital memory cells: A viable solution to the <s> We discuss the design of an experimentation platform intended for prototyping low-cost analog neural networks for on-chip integration with analog/RF circuits. The objective of such integration is to support various tasks, such as self-test, self-tuning, and trust/aging monitoring, which require classification of analog measurements obtained from on-chip sensors. Particular emphasis is given to cost-efficient implementation reflected in: 1) low energy and area budgets of circuits dedicated to neural networks; 2) robust learning in presence of analog inaccuracies; and 3) long-term retention of learned functionality. Our chip consists of a reconfigurable array of synapses and neurons operating below threshold and featuring sub- $\mu \text{W}$ power consumption. The synapse circuits employ dual-mode weight storage: 1) a dynamic mode, for fast bidirectional weight updates during training and 2) a nonvolatile mode, for permanent storage of learned functionality. We discuss a robust learning strategy, and we evaluate the system performance on several benchmark problems, such as the XOR2-6 and two-spirals classification tasks. <s> BIB002 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> 1) Digital memory cells: A viable solution to the <s> We present a novel one-transistor/one-resistor (1T1R) synapse for neuromorphic networks, based on phase change memory (PCM) technology. The synapse is capable of spike-timing dependent plasticity (STDP), where gradual potentiation relies on set transition, namely crystallization, in the PCM, while depression is achieved via reset or amorphization of a chalcogenide active volume. STDP characteristics are demonstrated by experiments under variable initial conditions and number of pulses. Finally, we support the applicability of the 1T1R synapse for learning and recognition of visual patterns by simulations of fully connected neuromorphic networks with 2 or 3 layers with high recognition efficiency. The proposed scheme provides a feasible low-power solution for on-line unsupervised machine learning in smart reconfigurable sensors. <s> BIB003 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> 1) Digital memory cells: A viable solution to the <s> As CMOS technology begins to face significant scaling challenges, considerable research efforts are being directed to investigate alternative device technologies that can serve as a replacement for CMOS. Spintronic devices, which utilize the spin of electrons as the state variable for computation, have recently emerged as one of the leading candidates for post-CMOS technology. Recent experiments have shown that a nano-magnet can be switched by a spin-polarized current and this has led to a number of novel device proposals over the past few years. In this paper, we provide a review of different mechanisms that manipulate the state of a nano-magnet using current-induced spin-transfer torque and demonstrate how such mechanisms have been engineered to develop device structures for energy-efficient on-chip memory and logic. <s> BIB004
problem is digital memory cells. However, if the processing of the synapse is to be analog, additional analog-to-digital converter (ADC) and digital-to-analog-converter (DAC) are required to interface between the analog and digital worlds, thus, occupying more space on the chip die and increasing complexity and power consumption. 2) Capacitive storage: Capacitive storage provides a simple and analog alternative to digital memory cells. However, if the storage capacitance is connected to a transmission gate, the unavoidable leakage would call for mechanisms to mitigate the issue, e.g., using a bigger capacitor, at the cost of sacrificing area and power. 3) Floating-gate (FG) transistors: A completely analog, long-term, asynchronously accessible and nonvolatile storage can be realized using FG transistors. Employing a single FG device has enabled both PSC generation and long-term storage. Moreover, arraying single FG devices in a mesh architecture allows support of LTP learning approaches BIB002 . The major drawback of the FG device stems from the difficulties of precisely controlling the erase and programming process. 4) Bistable synapse: Using only two stable synaptic states can solve the problem of long-term storage, as has been shown in BIB001 . In this work, memory is preserved even in the absence of stimuli, or when the presynaptic activity is low, by using a bistable circuit that restores the synaptic state to either its high or its low rail, depending on whether the weight is above or below a certain threshold. Bistable synaptic dynamics make the synaptic weight more robust against spurious spikes, yet at the cost of plasticity sensitivity to temporal spike patterns, since multiple spike patterns may lead to the same binary synaptic weights  . 5) Nanodevice technologies: Recent advances in nanotechnology have resulted in new devices which can carry out long-term multivalued weight storage and also allow for synaptic plasticity. Three such devices are the memristor  ,  , the phase change memory BIB003 , and the spin-transfer torque magnetic memory BIB004 . 