Survey of Memory Management Techniques for HPC and Cloud Computing <s> II. SCOPE OF MEMORY MANAGEMENT <s> As the trends driven by Moore’s law come to an end, increased heterogeneity at all levels of computing is required to deliver the computing performance needed for emerging applications, leading to the proliferation of various application- or domain-specific accelerators. This in turn demands more memory bandwidth, as heterogeneous computing with accelerators consumes data at a much higher rate than traditional homogeneous computing, limiting the computing performance. To tackle this challenge, this article presents a conceptual near-memory acceleration architecture; demonstrates its practicality and plausibility using a recent experimental platform from IBM, as well as its potential impact on performance and energy efficiency; and discusses the need for adopting a high-level synthesis approach for such a near-memory acceleration architecture. Subsequently, this article concludes with future research directions for broad adoption of near-memory acceleration. <s> BIB001 </s> Survey of Memory Management Techniques for HPC and Cloud Computing <s> II. SCOPE OF MEMORY MANAGEMENT <s> This study analyzes the memory capacity requirements of important HPC benchmarks and applications. We find that the High Performance Conjugate Gradients benchmark could be an important success story for 3D-stacked memories in HPC, but High-performance Linpack is likely to be constrained by 3D memory capacity. <s> BIB002
Traditionally, HPC systems are designed in a way that all nodes can run at peak performance simultaneously. It allows performing computational intensive applications and benchmarks, such as High-Performance Linpack, with maximum performance. Such systems are built on a close interaction between CPU and memory. When the system is scaled, the CPUs and the memory, since they are physically coupled, they get upgraded proportionally, thereby keeping the processor-memory ratio constant. However, the memory bandwidth based on the traditional processor-memory interconnection technology will limit also the performance of heterogeneous architectures with accelerators. In this case, the memory in fact consumed at a higher rate, proportionally to their processing capabilities BIB001 . The current trend in HPC system design is to increase the number of memory channels per CPU and the number of I/Os in each double data rate (DDR) memory generation. This will increase the price and the memory system power consumption BIB002 . Modern HPC architectures meet new challenges.