Multi-Channel Neural Recording Implants: A Review <s> AC-Coupled Neural Amplifiers <s> There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff. <s> BIB001 </s> Multi-Channel Neural Recording Implants: A Review <s> AC-Coupled Neural Amplifiers <s> We present the design and testing of a 16-channel analog amplifier for processing neural signals. Each channel has the following features: (1) variable gain (70-94 dB), (2) four high pass Bessel filter poles (f(-3 dB)=445 Hz), (3) five low pass Bessel filter poles (f(-3 dB)=6.6 kHz), and (4) differential amplification with a user selectable reference channel to reject common mode background biological noise. Processed signals are time division multiplexed and sampled by an on-board 12-bit analog to digital converter at up to 62.5k samples/s per channel. The board is powered by two low dropout voltage regulators which may be supplied by a single battery. The board measures 8.1 cm x 9.9 cm, weighs 50 g, and consumes up to 130 mW. Its low input-referred noise (1.0 microV(RMS)) makes it possible to process low amplitude neural signals; the board was successfully tested in vivo to process cortically derived extracellular action potentials in primates. Signals processed by this board were compared to those generated by a commercially available system and were found to be nearly identical. Background noise generated by mastication was substantially attenuated by the selectable reference circuit. The described circuit is light weight and low power and is used as a component of a wearable multichannel neural telemetry system. <s> BIB002 </s> Multi-Channel Neural Recording Implants: A Review <s> AC-Coupled Neural Amplifiers <s> This paper presents a low-power low-noise fully integrated bandpass operational amplifier for a variety of biomedical neural recording applications. A standard two-stage CMOS amplifier in a closed-loop resistive feedback configuration provides a stable ac gain of 39.3 dB at 1 kHz. A subthreshold PMOS input transistor is utilized to clamp the large and random dc open circuit potentials that normally exist at the electrode-electrolyte interface. The low cutoff frequency of the amplifier is programmable up to 50 Hz, while its high cutoff frequency is measured to be 9.1 kHz. The tolerable dc input range is measured to be at least /spl plusmn/0.25 V with a dc rejection factor of at least 29 dB. The amplifier occupies 0.107 mm/sup 2/ in die area, and dissipates 115 /spl mu/W from a 3 V power supply. The total measured input-referred noise voltage in the frequency range of 0.1-10 kHz is 7.8 /spl mu/V/sub rms/. It is fabricated using AMI 1.5 /spl mu/m double-poly double-metal n-well CMOS process. This paper presents full characterization of the dc, ac, and noise performance of this amplifier through in vitro measurements in saline using two different neural recording electrodes. <s> BIB003 </s> Multi-Channel Neural Recording Implants: A Review <s> AC-Coupled Neural Amplifiers <s> This paper describes an ultralow-power neural recording amplifier. The amplifier appears to be the lowest power and most energy-efficient neural recording amplifier reported to date. We describe low-noise design techniques that help the neural amplifier achieve input-referred noise that is near the theoretical limit of any amplifier using a differential pair as an input stage. Since neural amplifiers must include differential input pairs in practice to allow robust rejection of common-mode and power supply noise, our design appears to be near the optimum allowed by theory. The bandwidth of the amplifier can be adjusted for recording either neural spikes or local field potentials (LFPs). When configured for recording neural spikes, the amplifier yielded a midband gain of 40.8 dB and a -3-dB bandwidth from 45 Hz to 5.32 kHz; the amplifier's input-referred noise was measured to be 3.06 muVrms while consuming 7.56 muW of power from a 2.8-V supply corresponding to a noise efficiency factor (NEF) of 2.67 with the theoretical limit being 2.02. When configured for recording LFPs, the amplifier achieved a midband gain of 40.9 dB and a -3-dB bandwidth from 392 mHz to 295 Hz; the input-referred noise was 1.66 muVrms while consuming 2.08 muW from a 2.8-V supply corresponding to an NEF of 3.21. The amplifier was fabricated in AMI's 0.5-mum CMOS process and occupies 0.16 mm2 of chip area. We obtained successful recordings of action potentials from the robust nucleus of the arcopallium (RA) of an anesthesized zebra finch brain with the amplifier. Our experimental measurements of the amplifier's performance including its noise were in good accord with theory and circuit simulations. <s> BIB004 </s> Multi-Channel Neural Recording Implants: A Review <s> AC-Coupled Neural Amplifiers <s> Recent work in field of neuroprosthetics has demonstrated that by observing the simultaneous activity of many neurons in specific regions of the brain, it is possible to produce control signals that allow animals or humans to drive cursors or prosthetic limbs directly through thoughts. As neuroprosthetic devices transition from experimental to clinical use, there is a need for fully-implantable amplification and telemetry electronics in close proximity to the recording sites. To address these needs, we developed a prototype integrated circuit for wireless neural recording from a 100-channel microelectrode array. The design of both the system-level architecture and the individual circuits were driven by severe power constraints for small implantable devices; chronically heating tissue by only a few degrees Celsius leads to cell death. Due to the high data rate produced by 100 neural signals, the system must perform data reduction as well. We use a combination of a low-power ADC and an array of "spike detectors" to reduce the transmitted data rate while preserving critical information. The complete system receives power and commands (at 6.5 kb/s) wirelessly over a 2.64-MHz inductive link and transmits neural data back at a data rate of 330 kb/s using a fully-integrated 433-MHz FSK transmitter. The 4.7times5.9 mm2 chip was fabricated in a 0.5-mum 3M2P CMOS process and consumes 13.5 mW of power. While cross-chip interference limits performance in single-chip operation, a two-chip system was used to record neural signals from a Utah Electrode Array in cat cortex and transmit the digitized signals wirelessly to a receiver <s> BIB005 </s> Multi-Channel Neural Recording Implants: A Review <s> AC-Coupled Neural Amplifiers <s> This paper presents a fully integrated programmable biomedical sensor interface chip dedicated to the processing of various types of biomedical signals. The chip, optimized for high power efficiency, contains a low noise amplifier, a tunable bandpass filter, a programmable gain stage, and a successive approximation register analog-to-digital converter. A novel balanced tunable pseudo-resistor is proposed to achieve low signal distortion and high dynamic range under low voltage operations. A 53 nW, 30 kHz relaxation oscillator is included on-chip for low power consumption and full integration. The design was fabricated in a 0.35 μm standard CMOS process and tested at 1 V supply. The analog front-end has measured frequency response from 4.5 mHz to 292 Hz, programmable gains from 45.6 dB to 60 dB, input referred noise of 2.5 μV rms in the amplifier bandwidth, a noise efficiency factor (NEF) of 3.26, and a low distortion of less than 0.6% with full voltage swing at the ADC input. The system consumes 445 nA in the 31 Hz narrowband mode for heart rate detection and 895 nA in the 292 Hz wideband mode for ECG recording. <s> BIB006 </s> Multi-Channel Neural Recording Implants: A Review <s> AC-Coupled Neural Amplifiers <s> This paper describes a novel low-power, low-noise amplifier for neural recording applications. The bioamplifier achieves the best power-size tradeoff compared to the previous design. By means of a new active feedback configuration, the DC offset is rejected without the large capacitors. An active differentiator with an amplifier in the feedback path places a high-pass cutting frequency in the transfer function. The midband gain consists of the passive components, and is insensitive to the mismatch of process. The bioamplifier has been implemented in the Chartered 0.35-μm 2P4M CMOS process and occupies 0.022mm2 of chip area. The current consumption of amplifier is 2μA at ±1.5V supply. The bioamplifier achieves a midband gain of 46dB and a −3dB bandwidth from 13Hz to 8.9kHz. The input-referred noise is 5.7μV rms corresponding to an NEF of 3.1. <s> BIB007 </s> Multi-Channel Neural Recording Implants: A Review <s> AC-Coupled Neural Amplifiers <s> This paper presents a low-voltage low-power 16-channel interface chip dedicated for implantable neural signal recording. It consists of 16 front-end channels with tunable band-pass filtering and gain settings, multiplexed to a 10-bit SAR ADC for simultaneous recording. To comply with the implantation safety issue while maintaining comparable performance, the overall system is optimized to achieve low power dissipation and efficient power distribution among each individual blocks. A power efficient OTA topology is adopted in the front-end amplifier and a novel dual-capacitive-array SAR ADC is chosen to achieve better power efficiency. A prototype fabricated in a 0.35-µm CMOS technology achieves a NEF of 2.16 and THD of 0.53% at full output swing while providing output data rate of 16 kS/s per channel. The interface consumes 60.3-µW total power from a 1-V supply. <s> BIB008 </s> Multi-Channel Neural Recording Implants: A Review <s> AC-Coupled Neural Amplifiers <s> We present an inductively powered 32-channel wireless integrated neural recording (WINeR) system-on-a-chip (SoC) to be ultimately used for one or more small freely behaving animals. The inductive powering is intended to relieve the animals from carrying bulky batteries used in other wireless systems, and enables long recording sessions. The WINeR system uses time-division multiplexing along with a novel power scheduling method that reduces the current in unused low-noise amplifiers (LNAs) to cut the total SoC power consumption. In addition, an on-chip high-efficiency active rectifier with optimized coils help improve the overall system power efficiency, which is controlled in a closed loop to supply stable power to the WINeR regardless of the coil displacements. The WINeR SoC has been implemented in a 0.5-μ m standard complementary metal-oxide semiconductor process, measuring 4.9×3.3 mm2 and consuming 5.85 mW at ±1.5 V when 12 out of 32 LNAs are active at any time by power scheduling. Measured input-referred noise for the entire system, including the receiver located at 1.2 m, is 4.95 μVrms in the 1 Hz~10 kHz range when the system is inductively powered with 7-cm separation between aligned coils. <s> BIB009 </s> Multi-Channel Neural Recording Implants: A Review <s> AC-Coupled Neural Amplifiers <s> This paper describes a neurostimulation IC for use in advanced closed-loop neurostimulation applications, such as deep brain stimulation (DBS) for treatment and research of neurological disorders including Parkinson's disease. This system senses and filters neural activity with eight pre-amplifiers, a 200 kS/s 8-bit log ADC and digital filters and incorporates 64 programmable current-stimulation channels. The entire device, implemented in 0.18 μm CMOS, occupies 2.7 mm2 and consumes 89 μW in normal operation mode and 271 μW in configuration mode from a 1.8 V supply. <s> BIB010 </s> Multi-Channel Neural Recording Implants: A Review <s> AC-Coupled Neural Amplifiers <s> Epilepsy is one of the most common neurological disorders and affects more than 50 million individuals worldwide. Neurosurgery is an option for patients and intracranial EEG monitoring needs to be performed before surgery, which requires a multi-channel implantable EEG device. This paper presents a 1V 32-channel reconfigurable sensor interface IC for intracranial EEG recording. The power consumption of the overall system including amplification, filtering, and 10b ADC is 22µW, which makes it suitable for other implantable applications such as deep-brain stimulation. <s> BIB011 </s> Multi-Channel Neural Recording Implants: A Review <s> AC-Coupled Neural Amplifiers <s> This paper describes an activity-dependent intracortical microstimulation (ICMS) system-on-chip (SoC) that converts extracellular neural spikes recorded from one brain region to electrical stimuli delivered to another brain region in real time in vivo. The 10.9-mm 2 SoC incorporates two identical 4-channel modules, each comprising an analog recording front-end with total input noise voltage of 3.12 μV rms and noise efficiency factor (NEF) of 2.68, 5.9-μW 10-bit successive approximation register analog-to-digital converters (SAR ADCs), 12.4-μW digital spike discrimination processor, and a programmable constant-current microstimulating back-end that delivers up to 94.5 μA with 6-bit resolution to stimulate the cortical tissue when triggered by neural activity. For autonomous operation, the SoC also integrates biasing and clock generation circuitry, frequency-shift-keyed (FSK) transmitter at 433 MHz, and dc-dc converter that generates a power supply of 5.05 V for the microstimulating back-end from a single 1.5-V battery. Measured results from electrical performance characterization and biological experiments with anesthetized rats are presented from a prototype chip fabricated in AMS 0.35 μm two-poly four-metal (2P/4M) CMOS. A noise analysis for the selected low-noise amplifier (LNA) topology is presented that obtains a minimum NEF of 2.33 for a practical design given the technology parameters and power supply voltage. Future considerations in the SoC design with respect to silicon area and power consumption when increasing the number of channels are also discussed. <s> BIB012 </s> Multi-Channel Neural Recording Implants: A Review <s> AC-Coupled Neural Amplifiers <s> Chronic recording of neural signals is indispensable in designing efficient brain-machine interfaces and to elucidate human neurophysiology. The advent of multichannel micro-electrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system can vary over time due to change in electrode-neuron distance and background noise. We propose a neural amplifier in UMC 130 nm, 1P8M complementary metal-oxide-semiconductor (CMOS) technology. It can be biased adaptively from 200 nA to 2 μA, modulating input referred noise from 9.92 μV to 3.9 μV. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier and obviates the need of large input capacitance. The amplifier achieves a noise efficiency factor of 2.58. The amplifier can pass signal from 5 Hz to 7 kHz and the bandwidth of the amplifier can be tuned for rejecting low field potentials (LFP) and power line interference. The amplifier achieves a mid-band voltage gain of 37 dB. In vitro experiments are performed to validate the applicability of the neural low noise amplifier in neural recording systems. <s> BIB013 </s> Multi-Channel Neural Recording Implants: A Review <s> AC-Coupled Neural Amplifiers <s> Rapid development in miniature implantable electronics are expediting advances in neuroscience by allowing observation and control of neural activities. The first stage of an implantable biosignal recording system, a low-noise biopotential amplifier (BPA), is critical to the overall power and noise performance of the system. In order to integrate a large number of front-end amplifiers in multichannel implantable systems, the power consumption of each amplifier must be minimized. This paper introduces a closed-loop complementary-input amplifier, which has a bandwidth of 0.05 Hz to 10.5 kHz, an input-referred noise of 2.2 μ Vrms, and a power dissipation of 12 μW. As a point of comparison, a standard telescopic-cascode closed-loop amplifier with a 0.4 Hz to 8.5 kHz bandwidth, input-referred noise of 3.2 μ Vrms, and power dissipation of 12.5 μW is presented. Also for comparison, we show results from an open-loop complementary-input amplifier that exhibits an input-referred noise of 3.6 μ Vrms while consuming 800 nW of power. The two closed-loop amplifiers are fabricated in a 0.13 μ m CMOS process. The open-loop amplifier is fabricated in a 0.5 μm SOI-BiCMOS process. All three amplifiers operate with a 1 V supply. <s> BIB014
One of the most popular neural amplifier topologies is the closed-loop capacitive feedback amplifier introduced in BIB001 , which is also known as the conventional capacitive feedback network (CFN) topology BIB009 BIB004 BIB012 BIB006 BIB005 BIB010 . Figure 3a shows the conventional circuit architecture of this topology. A large capacitor C I at the input is used to block the tissue DC offset. The gain of this amplifier is equal to C I C F . To implement the high-pass pole, a capacitor C F is set in parallel with a highly resistive element R F in the feedback path. The main drawback of this topology is its large area due to the huge input capacitor C I . To achieve high gain and low-cutoff frequency at the range of 1 Hz and lower, a huge capacitor at the input of the amplifier is required. This large capacitor (C I ) occupies a large chip area and results in reduced input impedance of the neural amplifier. For this reason, this structure is not suitable for multi-channel applications. Using two or three gain stages could reduce the size of the capacitors and, consequently, the chip area, at the cost of increased power consumption. The total input-referred noise of the amplifier is presented as BIB001 V 2 ni,amp = where C F is the feedback capacitor, C I is the input capacitor, C in is the OTA input terminal capacitance, V 2 ni is the OTA input-referred noise power and V 2 ni,amp is the input-referred noise power of the whole neural amplifier. Equation  shows that increasing the gain of the neural amplifier, or in other words increasing the value of C I , for a constant C F , reduces the overall input-referred noise (IRN). In addition, for constant gain, increasing the sizes of the differential pair transistors on the one hand decreases the IRN power of the OTA (V 2 ni ), and, on the other hand, increases the size of the OTA input capacitance C in which, according to Equation (1), results in increasing the noise multiplication factor. As a trade-off, there is an optimum point for the size of the differential pair to minimize the overall IRN power of the neural amplifier for a specific gain. By replacing the feedback capacitor C F in the conventional CFN topology shown in Figure 3a to a T-capacitor network topology in Figure 3b , the total equivalent feedback capacitor is reduced  . Therefore, a similar gain is maintained with a smaller C I capacitor. However, this comes at the cost of increased low-cutoff frequency due to the reduced effective feedback capacitance. In order to maintain the same low-cutoff frequency, the feedback resistor has to increase. Increasing the feedback resistor, increases the input referred noise of the whole neural amplifier. Another topology of the AC-coupled neural amplifier is shown in Figure 3c . In this topology, a high-pass filter (HPF) followed by a resistive feedback non-inverting amplifier is used to cancel the DC offset BIB003 . The HPF is composed of an electrode capacitance and a high resistive PMOS where the bias current is programmable. The operating point of M P in Figure 3c determines the amount of resistance and the low-cutoff frequency. Since the value of the electrode capacitance varies significantly from one electrode to the other, the low-cutoff frequency is not accurate. In BIB002 , the same structure is used to design multi-channel AFE to construct a neural signal recording utilizing off-the-shelf components. This structure is used with an on-chip AC-coupled capacitor in the literature. However, in these designs, large off-chip resistors or active on-chip resistors implemented with MOS transistors biased in the subthreshold region are used, which increase the IRN. Figure 3d shows an open loop network (OLN) topology. It is similar to that of Figure 3c , while utilizing an open loop amplifier BIB013 . This topology can consume smaller silicon area compared to CFN topology, however it suffers from non-accurate gain and also sensitivity to the technology process deviation. Capacitive amplifier feedback network (CAFN) topology is another topology that removes the tissue voltage offset using a coupling capacitor shown in Figure 3e BIB007 . This structure is a band-pass amplifier where its midband gain (A m ) is calculated by . As explained in BIB007 and  , C3 has to be maximized to decrease the input referred noise. For a given gain, the ratio of C 3 /C 4 has to increase and the ratio of C 2 /C 1 has to decrease. By increasing C 3 /C 4 and decreasing C 2 /C 1 , the input referred noise gets close to the CFN topology of Figure 3a . In conclusion, the added complexity to this structure does not significantly improve its parameters. Even in some cases, with the same conditions, the noise, power consumption and chip area of this neural amplifier deteriorates compared to the CFN structure of Figure 3a . The topology shown in Figure 3f is a Miller compensated CFN (MCCFN) topology, which is similar to the conventional CFN topology, but it uses two OTAs in series. In some implementations, such as in BIB008 BIB011 , no Miller compensation capacitors are utilized in the OTAs. However, in other implementations, such as BIB014 , a Miller compensation capacitor is used in the second OTA (OTA 2 ) to make the non-dominant pole further away for better stability. In addition, in the design presented in  a Miller compensation capacitor is used in OTA 1 to create a double pole in the low-cutoff frequency. In the design of a single stage neural amplifier with high gain, this topology can provide a fair trade off between output swing, DC gain, noise, and power consumption. This advantage is realized by utilizing the OTA 2 in this structure, which increases the open loop gain. In addition, by designing the OTA 2 as a high-swing OTA in this structure, we can increase the output swing. Designing neural amplifiers with this topology (MCCFN) can result in low power and low noise with a low-noise efficiency factor (NEF) compared to the other topologies. However, in advanced technologies, where the neural amplifiers are designed in multistage architecture, there is no significant advantage compared to the conventional CFN topology. Note that high-cutoff frequency in all AC-coupled topologies of Figure 3 is determined by the frequency response of OTA 1 .