Survey of Memory Management Techniques for HPC and Cloud Computing <s> A. ACCESS PATTERNS <s> In modern shared-memory architectures, it is important to map threads and data in a way that increases the locality of their memory accesses, thereby improving performance and energy efficiency. Threads that access shared data should be mapped close to each other in the memory hierarchy, while the data they access should be mapped to their NUMA node, which is called sharing-aware mapping. In this paper, we propose SAMMU, which adds sharing-awareness to the memory management unit in current architectures. SAMMU analyzes the memory access behavior in hardware and provides information to the operating system so it can perform an online mapping of threads and data. In the evaluation with a wide range of parallel applications, performance was improved by upi¾źto 35.7i¾ź% 13.1i¾ź% on average. <s> BIB001 </s> Survey of Memory Management Techniques for HPC and Cloud Computing <s> A. ACCESS PATTERNS <s> Memory technology is one of the cornerstones of heterogeneous multi-core system efficiency. Many memory techniques are developed to give good performance within the lowest possible energy budget. These technologies open new opportunities for the memory system architecture that serves as the primary means for data storage and data sharing between multiple heterogeneous cores. In this paper, we study existing state of the art memories, discuss a conventional memory system and propose a novel hardware mechanism for heterogeneous multi-core memory system called Pattern Aware Memory System (PAMS). The PAMS supports static and dynamic data structures using descriptors and specialized scratchpad memory. In order to prove the proposed memory system, we implemented and tested it on real-prototype and simulator environments. The benchmarking results on real-prototype hardware show that PAMS achieves a maximum speedup of 12.83x and 1.23x for static and dynamic data structures respectively. When compared to the Baseline System, the PAMS consumes up to 4.8 times less program memory for static and dynamic data structures respectively. The PAMS consumes 4.6% and 1.6 times less dynamic power and energy respectively. The results of simulator environment show that the PAMS transfers data-structures up to 5.12x faster than the baseline system. Support for both static and dynamic data-structures and memory access patterns.Specialized scratchpad memory is integrated to map complex access patterns.The data manager accesses, reuses and feeds complex patterns to the processing core.Complex patterns are managed at run-time, without the support of a master core.Can be integrated with soft/hard soft processor core.Support trace driven simulation and FPGA based real prototyping environment. <s> BIB002
Regarding the limitation of the data read and write latency for the eDRAM integrated to the same silicon chip with the processing logic, BIB002 aims at hiding the on-chip communication mechanism between the applications local memory management. The local memory management system called Pattern Aware Memory System (PAMS) operates independently from the master core. It accelerates both static and dynamic data structures and their access patterns based on the information provided by pre-compiled pattern descriptors. In addition to this, PAMS controls data movements between the main and the scratchpad memories. Sharing-Aware Memory Management Unit (SAMMU) BIB001 analyses the memory access behaviour on the hardware level. It also provides information to the operating system to perform an online thread-and data-mapping to increase the locality, thus improving performance. SAMMU extends the operations of the MMU to gather information about the threads and NUMA nodes that accessed the particular physical pages without stalling the application execution. A general scheme of the access pattern usage is shown in Figure 2 . The mechanism that utilises hardware event counters or pre-compiled pattern descriptors to track specific events allows estimating the impact caused by contention on share hardware resources. Pattern Aware Memory Controller is in charge to optimise memory allocation and can be considered on the different levels of the memory hierarchy. 