Hardware Decoders for Polar Codes: An Overview <s> C. Memory-Efficient BP Decoders <s> A 1.48mm 2 1024-bit belief propagation polar decoder is designed in 65nm CMOS. A unidirectional processing reduces the memory size to 45Kb, and simplifies the processing element. A double-column 1024-parallel architecture enables a 4.68Gb/s throughput. A bit-splitting latch-based register file accommodates logic in memory for an 85% density. The architecture and circuit techniques reduce the power to 478mW for an efficiency of 15.5pJ/b/iteration at 1.0V. At 475mV, the efficiency is improved to 3.6pJ/b/iteration for a throughput of 780Mb/s. <s> BIB001 </s> Hardware Decoders for Polar Codes: An Overview <s> C. Memory-Efficient BP Decoders <s> Polar codes have become increasingly popular recently because of their capacity achieving property. In this paper, a memory efficient stage-combined belief propagation (BP) decoder design for polar codes is presented. Firstly, we briefly reviewed the conventional BP decoding algorithm. Then a stage-combined BP decoding algorithm which combines two adjacent stages into one stage and the corresponding belief message updating rules are introduced. Based on this stage-combined decoding algorithm, a memory-efficient polar BP decoder is designed. The demonstrated decoder design achieves 50% memory and decoding latency reduction in the cost of some combinational logic complexity overhead. The proposed decoder is synthesized under TSMC 45nm Low Power CMOS technology. It achieves 0.96 Gb/s throughput with 14.2mm ::: 2 ::: area when code length N=2 ::: 16 ::: which reduces 51.5% decoder area compared with the conventional decoder design. <s> BIB002
It was observed in BIB001 that, if a single-column decoder follows a round-trip schedule, N messages instead of 2N need to be updated each time. Thus, the memory requirement is reduced in half. In BIB002 , two adjacent columns are combined into one so that intermediate messages need not to be stored. However, the corresponding message updating rules have to be modified accordingly. As a result, the overall memory usage is significantly reduced, at the cost of some combinational logic overhead.