Analog Integrated Current Drivers for Bioimpedance Applications: A Review <s> 13 <s> This paper describes the design of an active electrode integrated circuit (IC) for a wearable electrical impedance tomography (EIT) system required for real time monitoring of neonatal lung function. The IC comprises a wideband high power current driver (up to 6 mAp-p output current), a low noise voltage amplifier and two shape sensor buffers. The IC has been designed in a 0.35-μm CMOS technology. It operates from ±9 V power supplies and occupies a total die area of 5 mm2. Post-layout simulations are presented. <s> BIB001 </s> Analog Integrated Current Drivers for Bioimpedance Applications: A Review <s> 13 <s> This paper presents an integrated fully differential current driver for wearable multi-frequency electrical impedance tomography (EIT). The integrated circuit (IC) comprises a wideband current driver (up to 500 kHz) functioning as the master for current sourcing, and a differential voltage receiver with common-mode feedback configuration as the slave for current sinking. The IC is fabricated in a 0.18-μm CMOS technology. It operates from ±1.65 V power supplies and occupies a total die area of less than 0.05 mm2. The current driver has a measured output impedance of 750 kΩ at 500 kHz and provides a common-mode signal reduction of 32 dB at 500 kHz. The application of the IC in a wearable EIT lung monitoring system is presented. <s> BIB002 </s> Analog Integrated Current Drivers for Bioimpedance Applications: A Review <s> 13 <s> A high specification, wearable, electrical impedance tomography (EIT) system with 32 active electrodes is presented. Each electrode has an application specific integrated circuit (ASIC) mounted on a flexible printed circuit board, which is then wrapped inside a disposable fabric cover containing silver-coated electrodes to form the wearable belt. It is connected to a central hub that operates all the 32 ASICs. Each ASIC comprises a high-performance current driver capable of up to 6 mAp-p output, a voltage buffer for EIT and heart rate signal recording as well as contact impedance monitoring, and a sensor buffer that provides multi-parameter sensing. The ASIC was designed in a CMOS 0.35- $\mu \text{m}$ high-voltage process technology. It operates from ±9 V power supplies and occupies a total die area of 3.9 mm2. The EIT system has a bandwidth of 500 kHz and employs two parallel data acquisition channels to achieve a frame rate of 107 frames/s, the fastest wearable EIT system reported to date. Measured results show that the system has a measurement accuracy of 98.88% and a minimum EIT detectability of 0.86 $\Omega $ /frame. Its successful operation in capturing EIT lung respiration and heart rate biosignals from a volunteer is demonstrated. <s> BIB003
where Aloop is the overall open loop gain of the current driver and Rload is the load. Where roOTA is the output impedance Iout and ADDTA is the open loop gain of the DDTA. . System level architecture and circuit level design of the current driver of an active electrode IC for wearable Electrical Impedance Tomography (EIT) (Reproduced from BIB001 BIB003 , with permission from the IEEE). The DDTA circuit compares two differential input signals (V1, V2). In this design, a fully differential output is provided by adding a duplicate of the output branch so that it can be connected to the wideband OTA BIB001 . Four source-degenerating transistors MD are added to the cross-coupled input pairs of the DDTA to achieve a high output current amplitude with low distortion. Using the four triode-transistors MC for common mode feedback, a bias voltage VCM can set the common mode voltage at the circuit's output. In the design, the OTA, a DC biasing stage (comprising M29 to M33), is configured to a feedback loop with M24 and M27 to provide a biasing voltage for transistors M27 and M28, and to set the DC level at Iout BIB003 . In this system two single-ended current drivers have been utilized to provide source and sink currents for the corresponding electrodes, while a differential current driver with common mode feedback (CMFB) could be used to reduce the overall power consumption and size of the system. Any mismatch between the source and the sink currents would force the unmatched current to flow through the output impedance node of the current drivers, which results in a large common mode signal that can cause measurement errors, or even saturate the driver output. In an analogous design in BIB003 , a fully differential current driver is proposed, as shown in Figure  12 . In Active Electrode-1 ,the source current is configured as in BIB001 , while the sink current is provided from the central hub. A fully differential voltage signal is generated from the central hub as input to the current driver. The current driver sources a current of I+ and the main buffer B1 senses the voltage Vf directly on the load and feeds it back to the central hub, while the differential receiver amplifier senses Vf and generates an output voltage, which provides a voltage to generate sink current I- BIB003 . In this topology, the feedback amplifier generating the sink current is a negative feedback voltage amplifier which, by sensing the common mode signal, generates a voltage at its output which results in a sink current that matches the source current. Providing the voltage gain of the amplifier is high enough, the common mode is removed. Figure 11 . System level architecture and circuit level design of the current driver of an active electrode IC for wearable Electrical Impedance Tomography (EIT) (Reproduced from BIB001 BIB003 , with permission from the IEEE). The DDTA circuit compares two differential input signals (V1, V2). In this design, a fully differential output is provided by adding a duplicate of the output branch so that it can be connected to the wideband OTA BIB001 . Four source-degenerating transistors M D are added to the cross-coupled input pairs of the DDTA to achieve a high output current amplitude with low distortion. Using the four triode-transistors M C for common mode feedback, a bias voltage VCM can set the common mode voltage at the circuit's output. In the design, the OTA, a DC biasing stage (comprising M29 to M33), is configured to a feedback loop with M24 and M27 to provide a biasing voltage for transistors M27 and M28, and to set the DC level at I out BIB003 . In this system two single-ended current drivers have been utilized to provide source and sink currents for the corresponding electrodes, while a differential current driver with common mode feedback (CMFB) could be used to reduce the overall power consumption and size of the system. Any mismatch between the source and the sink currents would force the unmatched current to flow through the output impedance node of the current drivers, which results in a large common mode signal that can cause measurement errors, or even saturate the driver output. In an analogous design in BIB003 , a fully differential current driver is proposed, as shown in Figure 12 . In Active Electrode-1, the source current is configured as in BIB001 , while the sink current is provided from the central hub. A fully differential voltage signal is generated from the central hub as input to the current driver. The current driver sources a current of I+ and the main buffer B1 senses the voltage Vf directly on the load and feeds it back to the central hub, while the differential receiver amplifier senses Vf and generates an output voltage, which provides a voltage to generate sink current I- BIB003 . In this topology, the feedback amplifier generating the sink current is a negative feedback voltage amplifier which, by sensing the common mode signal, generates a voltage at its output which results in a sink current that matches the source current. Providing the voltage gain of the amplifier is high enough, the common mode is removed. The output phase error of 4° at 500 kHz is not a good comparison with respect to other systems, where no phase errors were achieved at such frequency. Meanwhile, having the sense resistor offchip provides more stable results and much less process variation as opposed to on-chip sense resistor, where the transconductance of the system is inversely proportional to its value. The current driver has a bandwidth of 500 kHz. The output impedance is 1.12 MΩ at 500 kHz. The maximum output current is 6 mA BIB003 . The design takes advantage of the closed loop architecture in terms of bandwidth and stability. The current driver in BIB002 is an enhanced version of BIB003 for wearable EIT systems where a builtin common mode signal reduction is added. The driver chip is fabricated in 0.18 μm CMOS technology and operates with ± 1.65 V supply, with total die area of 0.05 mm 2 . Figure 13 shows the block diagram of the proposed current driver along with circuit level design. As illustrated in Figure 13 , the master current driver consists of a DDTA followed by an OTA to enhance the overall transconductance. The slave differential voltage receiver (DVR) measures the voltage across the load and, through feedback, forces the common-mode voltage across the load to be zero BIB002 . Therefore, it sinks the current sourced by the master driver to form a complete current path. Figure 12 . Current driver topology with sink current provided from central hub (Reproduced from BIB003 with permission from the IEEE). The output phase error of 4 • at 500 kHz is not a good comparison with respect to other systems, where no phase errors were achieved at such frequency. Meanwhile, having the sense resistor off-chip provides more stable results and much less process variation as opposed to on-chip sense resistor, where the transconductance of the system is inversely proportional to its value. The current driver has a bandwidth of 500 kHz. The output impedance is 1.12 MΩ at 500 kHz. The maximum output current is 6 mA BIB003 . The design takes advantage of the closed loop architecture in terms of bandwidth and stability. The current driver in BIB002 is an enhanced version of BIB003 for wearable EIT systems where a built-in common mode signal reduction is added. The driver chip is fabricated in 0.18 µm CMOS technology and operates with ± 1.65 V supply, with total die area of 0.05 mm 2 . Figure 13 shows the block diagram of the proposed current driver along with circuit level design. As illustrated in Figure 13 , the master current driver consists of a DDTA followed by an OTA to enhance the overall transconductance. The slave differential voltage receiver (DVR) measures the voltage across the load and, through feedback, forces the common-mode voltage across the load to be zero BIB002 . Therefore, it sinks the current sourced by the master driver to form a complete current path. The output phase error of 4° at 500 kHz is not a good comparison with respect to other systems, where no phase errors were achieved at such frequency. Meanwhile, having the sense resistor offchip provides more stable results and much less process variation as opposed to on-chip sense resistor, where the transconductance of the system is inversely proportional to its value. The current driver has a bandwidth of 500 kHz. The output impedance is 1.12 MΩ at 500 kHz. The maximum output current is 6 mA BIB003 . The design takes advantage of the closed loop architecture in terms of bandwidth and stability. The current driver in BIB002 is an enhanced version of BIB003 for wearable EIT systems where a builtin common mode signal reduction is added. The driver chip is fabricated in 0.18 μm CMOS technology and operates with ± 1.65 V supply, with total die area of 0.05 mm 2 . Figure 13 shows the block diagram of the proposed current driver along with circuit level design. As illustrated in Figure 13 , the master current driver consists of a DDTA followed by an OTA to enhance the overall transconductance. The slave differential voltage receiver (DVR) measures the voltage across the load and, through feedback, forces the common-mode voltage across the load to be zero BIB002 . Therefore, it sinks the current sourced by the master driver to form a complete current path. The transconductance of the current driver is: The output impedance is: The measurement results of the current driver chip show an output impedance of 750 kΩ at 500 kHz with maximum output current of 1mA p-p and THD of 42 dB BIB002 . There is no information provided about any potential phase error. As explained earlier in previous current drivers, a higher bandwidth is not easily achieved, as the capacitor effects in higher frequency results in lower output impedance, degraded current accuracy, and phase errors.