DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> DISCUSSION AND CONCLUDING REMARK <s> For an all-digital phase-locked loop, the frequency range supported is often segmented, and this could cause significant jitter when the operating condition (such as the supply voltage and/or the temperature) changes. To address this issue, we present a scheme, called smooth code-jumping, that can stitch together the segmented frequency profile of a digitally controlled oscillator (DCO) into a continuous range, and thereby reduce the jitter significantly. This scheme incorporates a new mirror-DCO-based calibration scheme to take into account process variations. We validate this scheme by test chips in 0.18-μm CMOS technology. Measurement results show that, when operating at 1 GHz, the rms jitter is 4.3 ps (0.43%UI) and the peak-to-peak jitter is 35.6 ps (3.56%UI), respectively. <s> BIB001 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> DISCUSSION AND CONCLUDING REMARK <s> A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with wideband frequency modulation (FM) for FMCW radar applications is proposed. The fractional-N ADPLL employs a high-resolution 60 GHz digitally-controlled oscillator (DCO) and is capable of multi-rate two-point FM. It achieves a measured rms jitter of 590.2 fs, while the loop settles within 3 μs. The measured reference spur is only -74 dBc, the fractional spurs are below -62 dBc, with no other significant spurs. A closed-loop DCO gain linearization scheme realizes a GHz-level triangular chirp across multiple DCO tuning banks with a measured frequency error (i.e., nonlinearity) in the FMCW ramp of only 117 kHz rms for a 62 GHz carrier with 1.22 GHz bandwidth. The synthesizer is transformer-coupled to a 3-stage neutralized power amplifier (PA) that delivers +5 dBm to a 50 Ω load. Implemented in 65 nm CMOS, the transmitter prototype (including PA) consumes 89 mW from a 1.2 V supply. <s> BIB002 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> DISCUSSION AND CONCLUDING REMARK <s> The proposed all-digital frequency locked loop features a digitally controlled oscillator, a counter & latch as a frequency sensor and an accumulator in the control loop. The number of oscillation cycles are counted during a logic high of the reference signal and it is subtracted from a desired value set by the user, thus an error signal is obtained. The error is accumulated, and a digital control word is formed for the digitally controlled oscillator. Discrete time domain equations are devised for the proposed ADFLL, and the convergence to the desired frequency is proven. Moreover, the analysis is completed with the s-domain linearized model of the system. Numerical results comprise simulations carried out in (i) a logic simulator for the Verilog behavioral description of the ADFLL and (ii) a PSPICE simulation for the s-domain model. <s> BIB003 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> DISCUSSION AND CONCLUDING REMARK <s> In this paper an all-digital frequency locked loop — which is composed of a digitally controlled oscillator, a counter and a latch (with the scope of frequency detection) and an accumulator in the control loop — is modeled in the z-domain considering two significant error sources that occur in its structure: the finite resolution of the digital signals and the inaccuracy of the frequency detection. The developed discrete time model was implemented in LabVIEW and it was compared against a structural description of the frequency locked loop achieved in Verilog. Simulation results for digitally controlled oscillator with 8, 10 and 12 bits resolution were obtained for both models. Employing a low resolution digitally controlled oscillator the loop can achieve frequency lock in less time, but its jitter performance is worst. The jitter can be improved if higher resolution is used, at the cost of a higher frequency lock time. The peak-to-peak jitter performance was plotted against the resolution of the digitally controlled oscillator that is helpful to determine the minimum for a desiredjitter. <s> BIB004 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> DISCUSSION AND CONCLUDING REMARK <s> A digitally controlled current-mode quadrature oscillator (DCC-MQO) is proposed. The circuit consist of four cascaded log-domain first order low-pass filter and a digitally programmable current division network. The lossy log-domain integrator gain and time constant can be adjusted using the bias currents of the logarithmic and exponential building blocks. The programmable current division network provides the bias currents for the log-domain cells which can be adjusted using a digital control word. The building blocks were implemented in a generic 180nm BiCMOS process and Spice simulation were performed to demonstrate de viability of the design. <s> BIB005
This review article presented various design topologies of digital controlled oscillator (DCO) designs in ADPLL. Table 1 provides a quick summary to aid the reader about different DCO techniques advantages and disadvantages. The understanding of basic principle and consideration are vital in designing DCO. Table 2 summarize the design performance of different ADPLL applications used DCO reported from 2010 to 2018. The table also compare important DCO  parameters including CMOS process design technology, input power supply (voltage) and power consumption (Watt) of the circuits. Furthermore, chip area, DCO resolution and frequency range are included for quick understanding. Varactor pairs in DCO scheme found consume more power compare the rest of the design technique. This is one of the drawbacks in obtaining a better DCO performance is terms of resolution and good jitter. Despite the fact of high power consumption, it does not affect much to the chip area. BIB002 have achieved the first 60GHz ADPLL by using three tuning bank design in the DCO scheme. Besides having a good frequency range, it produces good jitter, ultra-fast settling, and very low spur but this varactor pair scheme suffers high power consumption consuming more power to the circuit. Inductive coupled ditherless DCO design scheme produced good resolution and wide frequency range. Besides, the circuit function using low voltage supply and has wide frequency range DCO. This method reduced the silicon area of the DCO core by 50% and lowering power consumption by 67%. The ring DCO scheme also consumed smaller area, power efficient and wide frequency range combine with fine resolution. Pei-Ying et al. (2013) developed 3G-DCO design BIB001 . It achieved low jitter, consume low power and low design area. The work done in  produced the highest tuning range and is possible to obtain quadrature signals. Finally, the DCO combine with DAC and VCO scheme show fascinating results by improving linearity while decreasing the area and power usage. We can conclude that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The DCO is recognized as one of the modules that can give direct impact to the ADPLL performance. ADPLL needs low voltage and low power consumption, small chip area, highly portable, wide frequency range, and high resolution of DCO designs. The considerations to these DCO parameters are vital in improving APDLL performance. 2018  2017 BIB003 2017 BIB004 2017 BIB005 Ring DCOs 