Hardware Decoders for Polar Codes: An Overview <s> A. Fast BP-Based Decoders <s> A 1.48mm 2 1024-bit belief propagation polar decoder is designed in 65nm CMOS. A unidirectional processing reduces the memory size to 45Kb, and simplifies the processing element. A double-column 1024-parallel architecture enables a 4.68Gb/s throughput. A bit-splitting latch-based register file accommodates logic in memory for an 85% density. The architecture and circuit techniques reduce the power to 478mW for an efficiency of 15.5pJ/b/iteration at 1.0V. At 475mV, the efficiency is improved to 3.6pJ/b/iteration for a throughput of 780Mb/s. <s> BIB001 </s> Hardware Decoders for Polar Codes: An Overview <s> A. Fast BP-Based Decoders <s> Capacity-achieving polar codes have received significant attention in past few years. These codes can be decoded using either the successive-cancellation (SC) approach or the belief propagation (BP) approach. Several VLSI architectures of SC polar decoders have been reported in the literature. However, SC decoders suffer from long latency and low throughput due to their sequential decoding nature. On the other hand, although the BP decoders can be operated in an inherently parallel manner with high throughput, the functional units in these decoders are underutilized. In this paper, we exploit various architecture transformation techniques to further improve hardware performance of polar BP decoders. First, we propose an overlapped-scheduling approach at iteration level to reduce the overall decoding latency. Second, we propose codeword-level overlap to further improve hardware utilization efficiency. Third, we show that the above two overlapping approaches can be unified into a general framework into a joint overlapping approach. Fourth, we exploit the folding technique to design low-complexity polar BP decoders, and present two types of folded architectures. Synthesis results show that the proposed two (1024, 512) polar BP decoder designs can achieve 1.50 and 2.43 times reduction in hardware complexity, respectively. In addition, the proposed two designs can also achieve 7.4 and 2.5 times improvement in hardware efficiency, respectively. <s> BIB002
From Fig. 1a , the graph of polar codes of length N consists of log 2 N columns, each with 2N incident edges. A BP decoder traverses the graph column-by-column and each time 2N soft messages at the corresponding edges are updated. If the graph is traversed in a round-trip manner, a singlecolumn decoder takes 2 log 2 N − 1 clock cycles to complete an iteration. A double-column architecture was proposed in BIB001 where the operations of two adjacent columns are merged in one clock cycle, effectively reducing in half the latency per iteration. Although the critical path was shown to increase by 14% compared to that of the single-column architecture, the decoding throughput was improved by more than 40%. The graph can also be traversed uni-directionally, e.g., only activating columns from right to left. Under this schedule, data dependency is relaxed. Taking Fig. 1a for example, the messages updated by the left-most column c 0 of the current iteration are not used by the right-most column c 2 of the next iteration. Hence, the operations of these two columns can be simultaneously executed and one clock cycle is saved. More generally, an iteration-level overlapping schedule was proposed in BIB002 . By increasing the hardware complexity to compute 1 2 log 2 N columns simultaneously, the latency of a uni-directional BP decoder is reduced from J log 2 N clock cycles to 2J + log 2 N − 2, where J denotes the number of iterations.