DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> INTRODUCTION <s> This brief presents a frequency estimation algorithm (FEA) for an all-digital phase-locked loop (ADPLL) instead of the traditional binary frequency-searching algorithm. Based on the proposed FEA and a new fast-lock scheme, a fast-lock engine is designed to improve the lock-in time of an ADPLL design with two referenced clock cycles. An implementation of the proposed ADPLL design is realized by utilizing United Microelectronics Corporation (UMC) 0.18-μm 1P6M CMOS technology with a core area of 300 × 250 μm2, consisting of an acceptable input reference clock ranging from 220 kHz to 8 MHz. The ADPLL design has a frequency range of 28-446 MHz with an 8.8-ps digitally controlled oscillator resolution. Moreover, the peak-to-peak jitter of the ADPLL achieves 70 ps, respectively. <s> BIB001 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> INTRODUCTION <s> A jitter and power analysis on a digitally controlled oscillator (DCO) is presented in this brief. By analyzing variable capacitance components on each switching node of the DCO, a simple jitter and power model was derived in a closed form. The proposed mathematical analysis can be effectively used for the accurate and faster estimation of the DCO jitter and power consumption; thus, the overall DCO design time can be significantly reduced. In order to validate our proposed mathematical modeling, the DCO has been designed and fabricated using a 0.13-μm 1.2-V CMOS process. The fabricated chip presents the root-mean-square and peak-to-peak jitters of 8.9 and 70 ps, respectively, at the output frequency of 600 MHz, under the operation range of 179-656 MHz with a 2.8-ps resolution, which clearly shows that our proposed modeling is well matched with the experimental results. <s> BIB002 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> INTRODUCTION <s> A digital phase-locked loop (DPLL) employs a linear proportional path, a double integral path, bandwidth and tuning range tracking; and a novel delta-sigma digital to analog converter to achieve low jitter, wide operating range and low power. The proposed proportional path decouples the detector quantization error and oscillator noise bandwidth tradeoff and helps maximize bandwidth to suppress digitally controlled oscillator (DCO) phase noise in a power efficient manner. A double integral path alleviates the tradeoff between DCO tuning range and its frequency quantization error. The high resolution of the DCO was maintained over a wide range of sampling clock frequencies by using a delta-sigma digital to analog converter and a continuously tunable switched-RC filter. Bandwidth and tuning range tracking are employed to achieve low jitter over the entire operating range. The prototype DPLL, fabricated in a 90 nm CMOS process, operates from 0.7 GHz to 3.5 GHz. At 2.5 GHz, the proposed DPLL consumes only 1.6 mW power from a 1 V supply and achieves 1.6 ps and 11.6 ps of long-term r.m.s and peak jitter, respectively. <s> BIB003 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> INTRODUCTION <s> This paper presents an all-digital impulse radio ultra-wideband (IR-UWB) transmitter. All functional blocks in the transmitter are implemented with digital standard cells and automatically place-and-routed by design tools. The center frequency and the bandwidth of the UWB pulses are digitally tuned to compensate for variations, or target different applications. This paper also proposes a calibration scheme and modeling of a cell-based digitally controlled oscillator (DCO), which takes systematic mismatch from automatic place-and-route into account. The transmitter is fabricated in a 65 nm CMOS process, and occupies a core area of 0.032 mm2. The transmitter operates in the 3.1-5.0 GHz UWB band with leakage power of 170 μW and active energy consumption ranges from 8 pJ/pulse to 16 pJ/pulse, which combine to a total minimum energy/pulse of 12 pJ/pulse at 50 Mb/s. <s> BIB004 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> INTRODUCTION <s> We propose a new multirate architecture of an all-digital PLL (ADPLL) featuring phase/frequency modulation capability. While the ADPLL approach has already proven its benefits of power dissipation and cost reduction through the discrete-time operation and full RF-SoC integration in nanoscale CMOS, the coarse discretization of the phase detector function tends to keep it from reaching the ultimate of the RF performance potential. The proposed ADPLL features an arbitrarily high data rate modulation that is independent from the reference frequency. It is also made substantially free from injection pulling and ill-shaped quantization noise of the TDC by means of dithering with dynamic adjustment of differential pair mismatches as well as frequency translation of the feedback clock. Low power techniques, such as speculative clock retiming and asynchronous counter are used. The presented ADPLL is implemented in 65 nm CMOS as part of a single-chip GSM/EDGE RF-SoC. It occupies 0.35 mm2 and consumes 32 mA of current at 1.2 V supply in the low frequency band. The measured results show a virtually spur-free operation. <s> BIB005 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> INTRODUCTION <s> A digital ΔΣ fractional-N frequency synthesizer for 4G communication standards is presented which is able to achieve wide loop bandwidth while producing low fractional spurs. The loop adopts a fractional-N divider based on a phase interpolator, allowing to shrink the TDC dynamic range and to improve its linearity. A dynamic-element matching algorithm is employed to further improve TDC linearity and an original correlation algorithm is used to correct for the phase interpolator mismatches. Both digital algorithms operate in background and they are demonstrated to be concurrently effective in reducing in-band fractional spurs below -57 dBc. The circuit is fully integrated in a 65 nm CMOS process and it synthesizes a carrier in the 3.0-3.6 GHz range from a 40 MHz crystal reference with 40 Hz resolution. It achieves -104-dBc/Hz phase noise at 400-kHz offset and a 3.2-MHz maximum loop bandwidth. The synthesizer dissipates 80 mW and occupies 0.4 mm2. <s> BIB006 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> INTRODUCTION <s> This paper proposes an oppositely coupled varactor pair and reports the measured results for applying to a test digitally controlled oscillator (DCO). The pair exploits the differences between the accumulation region capacitance and inversion region capacitance of pMOS varactors. The novel varactor pairs provide much smaller switchable capacitances than those of other approaches, and hence, the test DCO for verifying the property of the pair achieves the high-frequency resolution. The pairs and test DCO are implemented in a 0.18-μm CMOS process. The switchable discrete capacitance of 32 aF is obtained by using the novel varactor pairs, and the test DCO has a frequency resolution of about 110 kHz at 5.8 GHz. Furthermore, ΔC of 4-aF and 14-kHz frequency resolution can be obtained through the dithering processes. The test DCO achieves a low phase noise of -117.6 dBc/Hz at 1-MHz offset from 5.8 GHz. <s> BIB007 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> INTRODUCTION <s> All-digital phase-locked loops (ADPLL) are inherently multirate systems with time-varying behavior. In support of this statement linear time-variant (LTV) models of ADPLL are presented that capture spectral aliasing effects that are not captured by linear time-invariant (LTI) models. It is analytically shown that the latter are subset of the former. The high-speed ΣΔ modulator that improves the frequency resolution of the digitally-controlled oscillator (DCO) is included, too. It realizes fractional resampling and interpolation of the tuning data of the DCO. The noise transfer from all three operating clock domains of the ADPLL (reference, ΣΔ, and DCO) to its output phase is accurately predicted and design metrics are derived with regard to its folded close-in and far-out phase noise performance. The analytical results are validated via simulations using measured event-driven modeling techniques for a CMOS RF ADPLL. <s> BIB008 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> INTRODUCTION <s> An improved architecture of polar transmitter (TX) is presented. The proposed architecture is digitally-intensive and mainly composed of an all-digital PLL (ADPLL) for phase modulation, a 1-bit low-pass delta sigma ΔΣ modulator for envelop modulation, and a H-bridge class-D power amplifier (PA) for differential signaling. The ΔΣ modulator is clocked using the phase modulated RF carrier to ensure phase synchronization between the amplitude and phase path, and to guarantee the PA is switching at zero crossings of the output current. An on-chip pre-filter is used to reduce the parasitic capacitance from packages at the switch stage output. The high over sampling ratio of the ΔΣ modulator move quantization noise far away from the carrier frequency, ensuring good in-band performance and relax filter requirements. The on-chip filter also acts as impedance matching and differential to single-ended conversion. The measured digital transmitter consumes 58 mW from a 1-V supply at 6.8 dBm output power. <s> BIB009 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> INTRODUCTION <s> A Bulk Acoustic Wave (BAW) resonator based 2.4-GHz low power receiver is presented in this work. The intrinsic high quality factor (Q) of the BAW resonator (around 400 at 2.4-GHz) is exploited to provide channel selection at RF and in the frequency synthesis. A novel way of addressing multiple channels (arbitrary frequency) using integer dividers and a BAW digitally controlled oscillator (DCO) and thus avoiding the need for a PLL is proposed in this work. To the best of our knowledge, this work is the first one to report a multi-channel (arbitrary frequency) receiver whose frequency synthesis depends solely on the low phase noise BAW DCO and does not include a PLL. A BAW pseudo-lattice with frequency and bandwidth tuning is proposed which significantly improves the rejection of unwanted signals in the channel filter. A quadrature sub-sampling mixer is used to down-convert the selected channel to baseband. The receiver is designed and integrated in a 0.18- μm CMOS process. With Q-boosting, the channel filter provides bandwidth down-to 1-MHz. For a BFSK modulated signal, the receiver exhibits a sensitivity of -78 \mathchar "702D dBm at a rate of 268-kbps for a BER of 10-3 . The total power consumption of the receiver is 5.94-mA from a 1.8-V power supply. <s> BIB010 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> INTRODUCTION <s> For an all-digital phase-locked loop, the frequency range supported is often segmented, and this could cause significant jitter when the operating condition (such as the supply voltage and/or the temperature) changes. To address this issue, we present a scheme, called smooth code-jumping, that can stitch together the segmented frequency profile of a digitally controlled oscillator (DCO) into a continuous range, and thereby reduce the jitter significantly. This scheme incorporates a new mirror-DCO-based calibration scheme to take into account process variations. We validate this scheme by test chips in 0.18-μm CMOS technology. Measurement results show that, when operating at 1 GHz, the rms jitter is 4.3 ps (0.43%UI) and the peak-to-peak jitter is 35.6 ps (3.56%UI), respectively. <s> BIB011 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> INTRODUCTION <s> An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13- μm CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches is essential for wider bandwidth operations. Moreover, sub-gate TDC resolution can be achieved with the proposed DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) which reduces 1/f noise is also proposed to enhance noise performance. The 2 MHz BW ADPLL which occupies 0.42 mm2 consumes 12 mA and its measured jitter is 4 psrms at 2.4 GHz. <s> BIB012 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> INTRODUCTION <s> A reference-less half-rate digital clock and data recovery (CDR) circuit employing a phase-rotating phase-locked loop (PRPLL) as phase interpolator is presented. By implementing the proportional control in phase domain within the PRPLL, the proposed CDR decouples jitter transfer (JTRAN) bandwidth from jitter tolerance (JTOL) corner frequency, eliminates jitter peaking, and removes JTRAN dependence on bang-bang phase detector gain. Fabricated in a 90 nm CMOS process, the prototype CDR achieves error-free operation (BER <; 10-12) with PRBS data sequences ranging from PRBS7 to PRBS31. At 5 Gb/s, it consumes 13.1 mW power and achieves a recovered clock long-term jitter of 5.0 ps rms/44.0 ps pp when operating with PRBS31 input data. The measured JTRAN bandwidth is 2 MHz and JTOL corner frequency is 16 MHz. The CDR is tolerant to 110 mV pp of sinusoidal noise on the DCO supply voltage at the worst case noise frequency of 7 MHz. At 2.5 GHz, the PRPLL consumes 2.9 mW and achieves -134 dBc/Hz phase noise at 1 MHz frequency offset. The differential and integral non-linearity of its digital-to-phase transfer characteristic are within ±0.2 LSB and ±0.4 LSB, respectively. <s> BIB013 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> INTRODUCTION <s> We present the first millimeter-wave digitally controlled oscillator (DCO) in a 28-nm CMOS technology. This DCO is developed as an integral part of all-digital phase-locked loop for automotive radar applications. The DCO achieves a tuning range of 3.6 GHz (39.3–42.9 GHz) with a fine frequency resolution less than 1 MHz and phase noise of −99.5 dBc/Hz at 1-MHz offset at 39.3 GHz. The DCO occupies 0.08 mm2 and consumes 10.5 mW. Impacts on DCO design from closely filled dummies to meet extremely stringent local density rules in the 28-nm CMOS process, which has not been investigated before, are also discussed. <s> BIB014
The modern communication systems for clock and data recovery (CDR) or frequency synthesis are widely use phase-locked loops (PLLs) BIB002 BIB010  BIB003 BIB008 . Electronic devices such as televisions, radio, cellular phones, computers and radio highly rely on PLL performances to operate efficiently. PLLs have been broadly studied due to massive range of applications. PLLs regularly developed on analog based design BIB004 BIB013 BIB011 . The main drawbacks of analog PLL are substrate-induced noise and the digital switch noise coupled with power through the power supply BIB009 . Moreover, the changes over CMOS process parameter required analog PLL to be redesign as it highly sensitive to parameter change BIB005 BIB012 BIB006 . Extensive studies have been done to improve the jitter performance however analog PLL outcome usually long lock-in time and increase design complexity. Therefore, ADPLL is used to replace the typical analog PLL for faster lock-in time, better stability, testability and portability over different process parameters. Figure 1 shows ADPLL block diagram that consists of functional blocks including phase detector (TDC), low pass filter, digital to analog converter (DAC), voltagecontrolled oscillator (VCO), and a multi-modulus divider  BIB001 . A phase comparator or phase detector is a logic circuit, frequency mixer, or analog multiplier that generates voltage signal makes up the difference in phase between two signal inputs. A low pass filter is a filter that passes signal with a frequency lower than a certain cut-off frequency. It eliminates signals with frequencies higher than the cut-off frequency. Digital controlled oscillator (DCO) plays an important role in ADPLL. DCO used in numerous applications including measuring temperature variations in oscillator frequency [15] . The DCO function similar with voltage-controlled oscillator (VCO) and DCO is used to overcome tuning stability limitations occur in the VCO BIB007 . DCO has identical delay stages, which each stage measures input delay or phase difference. The measurements usually form in a rough tuning block for larger frequency range. Better tuning block means the better is the time resolution BIB002 , BIB007 . Variable delays are major pull back in typical DCO design that required large number of power and jitter optimization iterations to enhance the ADPLL performance. Modern solutions employ a time to digital converter (TDC) BIB014 to measure the time difference between the edges of the oscillator and reference signal, thus obtaining the phase error. The phase error is then processed by a Control Algorithm. The typical control is a lowpass filter, called loop filter in the PLL terminology. A possible solution for the control is a digital accumulator (integration in the discrete domain), which integrates the frequency error signal, thus computing the control word for the DCO  . The design proposed in  is based on the ring topology and consists of four log-domain current-mode integrators. Using this implementation, the frequency can be tuned using the bias currents. The bias currents are obtained using a binary decoder and a current division network. The binary decoder role is to generate the control signals for the switches inside a current division cell. A 10-bit control word was used to generate 1024 control signals which in turn conducted to 1024 current values and 1024 distinct frequencies. The paper will first discuss the basic concept of DCO in Section 2.0. Next, the various DCO schemes for ADPLL is presented in Section 3.0. Finally, Section 4.0 presents the performance comparison of the various DCO schemes followed by conclusion section.