Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> IEEE Design & Test <s> We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)configure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms. <s> BIB001 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> IEEE Design & Test <s> A mixed-signal very large scale integration (VLSI) chip for large scale emulation of spiking neural networks is presented. The chip contains 2400 silicon neurons with fully programmable and reconfigurable synaptic connectivity. Each neuron implements a discrete-time model of a single-compartment cell. The model allows for analog membrane dynamics and an arbitrary number of synaptic connections, each with tunable conductance and reversal potential. The array of silicon neurons functions as an address-event (AE) transceiver, with incoming and outgoing spikes communicated over an asynchronous event-driven digital bus. Address encoding and conflict resolution of spiking events are implemented via a randomized arbitration scheme that ensures balanced servicing of event requests across the array. Routing of events is implemented externally using dynamically programmable random-access memory that stores a postsynaptic address, the conductance, and the reversal potential of each synaptic connection. Here, we describe the silicon neuron circuits, present experimental data characterizing the 3 mm times 3 mm chip fabricated in 0.5-mum complementary metal-oxide-semiconductor (CMOS) technology, and demonstrate its utility by configuring the hardware to emulate a model of attractor dynamics and waves of neural activity during sleep in rat hippocampus <s> BIB002 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> IEEE Design & Test <s> We present a model of spike-driven synaptic plasticity inspired by experimental observations and motivated by the desire to build an electronic hardware device that can learn to classify complex stimuli in a semisupervised fashion. During training, patterns of activity are sequentially imposed on the input neurons, and an additional instructor signal drives the output neurons toward the desired activity. The network is made of integrate-and-fire neurons with constant leak and a floor. The synapses are bistable, and they are modified by the arrival of presynaptic spikes. The sign of the change is determined by both the depolarization and the state of a variable that integrates the postsynaptic action potentials. Following the training phase, the instructor signal is removed, and the output neurons are driven purely by the activity of the input neurons weighted by the plastic synapses. In the absence of stimulation, the synapses preserve their internal state indefinitely. Memories are also very robust to the disruptive action of spontaneous activity. A network of 2000 input neurons is shown to be able to classify correctly a large number (thousands) of highly overlapping patterns (300 classes of preprocessed Latex characters, 30 patterns per class, and a subset of the NIST characters data set) and to generalize with performances that are better than or comparable to those of artificial neural networks. Finally we show that the synaptic dynamics is compatible with many of the experimental observations on the induction of long-term modifications (spike-timing-dependent plasticity and its dependence on both the postsynaptic depolarization and the frequency of pre- and postsynaptic neurons). <s> BIB003 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> IEEE Design & Test <s> Neuromorphic engineering (NE) is an emerging research field that has been attempting to identify neural types of computational principles, by implementing biophysically realistic models of neural systems in Very Large Scale Integration (VLSI) technology. Remarkable progress has been made recently, and complex artificial neural sensory-motor systems can be built using this technology. Today, however, NE stands before a large conceptual challenge that must be met before there will be significant progress toward an age of genuinely intelligent neuromorphic machines. The challenge is to bridge the gap from reactive systems to ones that are cognitive in quality. In this paper, we describe recent advancements in NE, and present examples of neuromorphic circuits that can be used as tools to address this challenge. Specifically, we show how VLSI networks of spiking neurons with spike-based plasticity mechanisms and soft winner-take-all architectures represent important building blocks useful for implementing artificial neural systems able to exhibit basic cognitive abilities. <s> BIB004 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> IEEE Design & Test <s> This paper introduces a novel design of an artificial neural network tailored for wafer-scale integration. The presented VLSI implementation includes continuous-time analog neurons with up to 16 k inputs. A novel interconnection and routing scheme allows the mapping of a multitude of network models derived from biology on the VLSI neural network while maintaining a high resource usage. A single 20 cm wafer contains about 60 million synapses. The implemented neurons are highly accelerated compared to biological real time. The power consumption of the dense interconnection network providing the necessary communication bandwidth is a critical aspect of the system integration. A novel asynchronous low-voltage signaling scheme is presented that makes the wafer-scale approach feasible by limiting the total power consumption while simultaneously providing a flexible, programmable network topology. <s> BIB005 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> IEEE Design & Test <s> This paper describes CAVIAR, a massively parallel hardware implementation of a spike-based sensing-processing-learning-actuating system inspired by the physiology of the nervous system. CAVIAR uses the asynchronous address-event representation (AER) communication framework and was developed in the context of a European Union funded project. It has four custom mixed-signal AER chips, five custom digital AER interface components, 45 k neurons (spiking cells), up to 5 M synapses, performs 12 G synaptic operations per second, and achieves millisecond object recognition and tracking latencies. <s> BIB006 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> IEEE Design & Test <s> Abstract Complex tasks often require the memory of recent events, the knowledge about the context in which they occur, and the goals we intend to reach. All this information is stored in our mental states. Given a set of mental states, reinforcement learning (RL) algorithms predict the optimal policy that maximizes future reward. RL algorithms assign a value to each already-known state so that discovering the optimal policy reduces to selecting the action leading to the state with the highest value. But how does the brain create representations of these mental states in the first place? We propose a mechanism for the creation of mental states that contain information about the temporal statistics of the events in a particular context. We suggest that the mental states are represented by stable patterns of reverberating activity, which are attractors of the neural dynamics. These representations are built from neurons that are selective to specific combinations of external events (e.g. sensory stimuli) and pre-existent mental states. Consistent with this notion, we find that neurons in the amygdala and in orbitofrontal cortex (OFC) often exhibit this form of mixed selectivity. We propose that activating different mixed selectivity neurons in a fixed temporal order modifies synaptic connections so that conjunctions of events and mental states merge into a single pattern of reverberating activity. This process corresponds to the birth of a new, different mental state that encodes a different temporal context. The concretion process depends on temporal contiguity, i.e. on the probability that a combination of an event and mental states follows or precedes the events and states that define a certain context. The information contained in the context thereby allows an animal to assign unambiguously a value to the events that initially appeared in different situations with different meanings. <s> BIB007 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> IEEE Design & Test <s> The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal?oxide?semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73?728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior. <s> BIB008 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> IEEE Design & Test <s> The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker - Spiking Neural Network architecture - is a massively parallel computer system designed to provide a cost-effective and flexible simulator for neuroscience experiments. It can model up to a billion neurons and a trillion synapses in biological real time. The basic building block is the SpiNNaker Chip Multiprocessor (CMP), which is a custom-designed globally asynchronous locally synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a lightweight, packet-switched asynchronous communications infrastructure. In this paper, we review the design requirements for its very demanding target application, the SpiNNaker micro-architecture and its implementation issues. We also evaluate the SpiNNaker CMP, which contains 100 million transistors in a 102-mm2 die, provides a peak performance of 3.96 GIPS, and has a peak power consumption of 1 W when all processor cores operate at the nominal frequency of 180 MHz. SpiNNaker chips are fully operational and meet their power and performance requirements. <s> BIB009 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> IEEE Design & Test <s> Several analog and digital brain-inspired elec- tronic systems have been recently proposed as dedicated solutions for fast simulations of spiking neural networks. While these architectures are useful for exploring the computational properties of large-scale models of the nervous system, the challenge of building low-power compact physical artifacts that can behave intelligently in the real world and exhibit cognitive abilities still remains open. In this paper, we propose a set of neuromorphic engineering solutions to address this challenge. In particular, we review neuromorphic circuits for emulating neural and synaptic dynamics in real time and discuss the role of biophysically realistic temporal dynamics in hardware neural processing architectures; we review the challenges of realizing spike-based plasticity mechanisms in real physical systems and present examples of analog electronic circuits that implement them; we describe the computational properties of recurrent neural networks and show how neuromorphic winner-take-all circuits can implement working-memory and decision-making mechanisms. We validate the neuromorphic approach proposed with experimental results obtained from our own circuits and systems, and argue how the circuits and networks presented in this work represent a useful set of components for efficiently and elegantly implementing neuro- morphic cognition. <s> BIB010 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> IEEE Design & Test <s> In this paper, we describe the design of Neurogrid, a neuromorphic system for simulating large-scale neural models in real time. Neuromorphic systems realize the function of biological neural systems by emulating their structure. Designers of such systems face three major design choices: 1) whether to emulate the four neural elementsVaxonal arbor, synapse, dendritic tree, and somaVwith dedicated or shared electronic circuits; 2) whether to implement these electronic circuits in an analog or digital manner; and 3) whether to interconnect arrays of these silicon neurons with a mesh or a tree network. The choices we made were: 1) we emulated all neural elements except the soma with shared electronic circuits; this choice maximized the number of synaptic connections; 2) we realizedallelectroniccircuitsexcept those foraxonal arbors in an analog manner; this choice maximized energy efficiency; and <s> BIB011 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> IEEE Design & Test <s> ): – requirements throughout surface waters of the N-limited North Pacific. Recent isotopic analysis of skeleton material from deep-sea corals near Hawaii also exhibit a decreasing trend over this time period, which has been interpreted as a signal of increasing N inputs from N2 fixation (36). However, because isotopic and stoichiometric signals of denitrification are transported from the anoxic zone into the subtropical gyre (37), the reported coral trends may originate partly from the OMZ. Any remaining signal attributable to N2 fixation would imply that the ecological niche of diazotrophs in the central gyre is uncoupled from the major N loss in the OMZ (38), and that a substantial imbalance of the Pacific N budget has persisted over the 20th century. <s> BIB012 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> IEEE Design & Test <s> Deep neural networks such as Convolutional Networks (ConvNets) and Deep Belief Networks (DBNs) represent the state-of-the-art for many machine learning and computer vision classification problems. To overcome the large computational cost of deep networks, spiking deep networks have recently been proposed, given the specialized hardware now available for spiking neural networks (SNNs). However, this has come at the cost of performance losses due to the conversion from analog neural networks (ANNs) without a notion of time, to sparsely firing, event-driven SNNs. Here we analyze the effects of converting deep ANNs into SNNs with respect to the choice of parameters for spiking neurons such as firing rates and thresholds. We present a set of optimization techniques to minimize performance loss in the conversion process for ConvNets and fully connected deep networks. These techniques yield networks that outperform all previous SNNs on the MNIST database to date, and many networks here are close to maximum performance after only 20 ms of simulated time. The techniques include using rectified linear units (ReLUs) with zero bias during training, and using a new weight normalization method to help regulate firing rates. Our method for converting an ANN into an SNN enables low-latency classification with high accuracies already after the first output spike, and compared with previous SNN approaches it yields improved performance without increased training time. The presented analysis and optimization techniques boost the value of spiking deep networks as an attractive framework for neuromorphic computing platforms aimed at fast and efficient pattern recognition. <s> BIB013 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> IEEE Design & Test <s> The application of biologically inspired methods in design and control has a long tradition in robotics. Unlike previous approaches in this direction, the emerging field of neurorobotics not only mimics biological mechanisms at a relatively high level of abstraction but employs highly realistic simulations of actual biological nervous systems. Even today, carrying out these simulations efficiently at appropriate timescales is challenging. Neuromorphic chip designs specially tailored to this task therefore offer an interesting perspective for neurorobotics. Unlike Von Neumann CPUs, these chips cannot be simply programmed with a standard programming language. Like real brains, their functionality is determined by the structure of neural connectivity and synaptic efficacies. Enabling higher cognitive functions for neurorobotics consequently requires the application of neurobiological learning algorithms to adjust synaptic weights in a biologically plausible way. In this paper, we therefore investigate how to program neuromorphic chips by means of learning. First, we provide an overview over selected neuromorphic chip designs and analyze them in terms of neural computation, communication systems and software infrastructure. On the theoretical side, we review neurobiological learning techniques. Based on this overview, we then examine on-die implementations of these learning algorithms on the considered neuromorphic chips. A final discussion puts the findings of this work into context and highlights how neuromorphic hardware can potentially advance the field of autonomous robot systems. The paper thus gives an in-depth overview of neuromorphic implementations of basic mechanisms of synaptic plasticity which are required to realize advanced cognitive capabilities with spiking neural networks. <s> BIB014 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s> IEEE Design & Test <s> Implementing compact, low-power artificial neural processing systems with real-time on-line learning abilities is still an open challenge. In this paper we present a full-custom mixed-signal VLSI device with neuromorphic learning circuits that emulate the biophysics of real spiking neurons and dynamic synapses for exploring the properties of computational neuroscience models and for building brain-inspired computing systems. The proposed architecture allows the on-chip configuration of a wide range of network connectivities, including recurrent and deep networks, with short-term and long-term plasticity. The device comprises 128 K analog synapse and 256 neuron circuits with biologically plausible dynamics and bi-stable spike-based plasticity mechanisms that endow it with on-line learning abilities. In addition to the analog circuits, the device comprises also asynchronous digital logic circuits for setting different synapse and neuron properties as well as different network configurations. This prototype device, fabricated using a 180 nm 1P6M CMOS process, occupies an area of 51.4 mm(2), and consumes approximately 4 mW for typical experiments, for example involving attractor networks. Here we describe the details of the overall architecture and of the individual circuits and present experimental results that showcase its potential. By supporting a wide range of cortical-like computational modules comprising plasticity mechanisms, this device will enable the realization of intelligent autonomous systems with on-line learning capabilities. <s> BIB015
Similarly to the classical neural networks, SNNs can be feedforward or recurrent. In a feedforward SNN, spike signals flow in only one direction, from input to output, one layer at a time, as depicted in Figure 7a . Addition of feedback loops allows the spike signals to flow in both directions and forms the recurrent neural network (RNN) shown in Figure 7b . Feedback adds some new properties in these networks such as associative memory BIB010 and context-dependent pattern classification, i.e., speech recognition BIB007 , as compared to the feedforward neural networks which are mainly used for complex pattern classification. RNNs that perform a WTA computation are believed to play a central role in cortical processing. They can perform powerful computations, including nonlinear selection, signal restoration, and state-dependent processing BIB004 . In its simplest abstract form, a WTA network consists of a group of interacting neurons which compete with each other for activation. Neurons that receive the strongest input signal will suppress the activation of other neurons to win the competition. However, a variation that allows the activation of more than one neuron also exists, namely the soft WTA network. Recently, spiking deep networks have also been proposed, aiming to overcome the large computational cost of the current state-of-the-art deep networks, such as convolutional and deep belief networks. Training these spiking deep networks is challenging because, instead of applying spikebased rules, a conversion from a conventional ANN, fully trained using backpropagation, into a spiking ANN is required. This conversion comes at a cost of performance losses BIB013 . There are numerous mixed-signal VLSI implementations of SNNs BIB002 , BIB001 . These generalpurpose computational networks consist of analog neurons that emulate the biophysics of real spiking neurons, synapses with STDP learning mechanisms, and the asynchronous AER communication protocol. The latter enables the configuration of a wide range of network topologies, including feedforward and recurrent networks. Additionally, due to their ability to simulate spike-based algorithms in real time, these VLSI networks may be interfaced to neuromorphic AER sensors, constructing VLSI sensory systems BIB006 . Six large-scale neuromorphic systems capable of simulating SNNs with a large number of neurons and synapses are presented below. Four of them are mixed-signal designs, in the sense that the circuits for neurons and synapses are analog, whereas the control of the analog circuit parameters, the network connectivity, and the multichip connectivity are based on asynchronous digital logic circuits. The remaining two are fully digital implementations. A more extensive review of these platforms can be found in BIB014 . The FACETS project BIB005 aims to develop a large-scale neuromorphic system, capable of implementing most of the neural systems modeled in computational neuroscience. To this end, a mixed-signal hardware neural network architecture consisting of analog neurons and a digital two-layer bus communication scheme was integrated on a wafer. The central element of this architecture is an analog neural network chip (HICANN), containing a total of 131072 synapses and up to 512 conductance-based adaptive exponential I&F neurons, which can be grouped together to form neurons with up to 14336 synapses. An important aspect of this type of neuron model is its operation at accelerated biological time. The acceleration factor ranges from 10 3 up to 10 5 as compared to the biological real time (BRT). Its synapses support both STP and LTP based on the STDP protocol mechanisms, whereas the synaptic weights are stored locally using 4-b SRAM cells. Following the AER paradigm, the digital communication scheme allows the integration of 384 HICANN chips on a single wafer. The main drawback of this wafer-scale system is the power consumption of 1 KW, which is mainly attributed to the acceleration scheme. The Neurogrid project BIB011 implements a mixed-signal neuromorphic hardware platform which serves as a brain simulation tool for neuroscientists. It uses analog computation to emulate ion-channel activity and a digital communication scheme to support synaptic connections. Its central processing element is called neurocore and contains 65536 quadratic I&F neurons which operate in BRT and use energy-efficient subthreshold operation. Neurogrid consists of 16 neurocores, yielding a total of 1048576 neurons and up to six billion synapses, which is much higher than in the FACETS project. Digital communication between neurocores is achieved by employing an external FPGA and a bank of SRAMs. Unlike the fully connected network of the HICANN chip, with separate circuits for every single synapse, all synapses of a neurocore neuron share only four synaptic population circuits, also feeding its neuron's neighbors. Although this results in a more compact implementation with considerably larger numbers of synapses per neuron, it also imposes a limitation as it precludes synaptic plasticity. It should be mentioned that the individual weights of the synapses are stored in a 1-b dedicated RAM. Finally, the overall system consumes only 5 W. The HRL SyNAPSE project BIB008 developed a mixed-signal fully integrated neuromorphic chip which is scalable and can be configured to implement various large-scale neural network topologies. It uses analog neurons and, instead of the AER protocol, the synaptic time multiplexing (STM) paradigm is applied. STM is used both as a communication protocol and for configuring the network topology. The chip contains 576 nodes, each of which emulates a neuron with 128 synapses. As a result, the maximum number of neurons is 576 and the corresponding number of synaptic connections is 73728. Contrary to the two previous architectures, a more basic leaky I&F neuron model was designed. The neuron operates in BRT and has very low power consumption. Each node contains only a single synaptic circuit but, due to STM, this circuit can compute multiple (up to 128) logical synapses, provided that it is able to operate at much higher speeds than the neurons. The corresponding synaptic weights can be stored in memristor arrays. Furthermore, the synapses support STDP but, compared to the HICANN chip, only a limited number of different STDP types is supported. Similarly to neurogrid, the overall power consumption of the whole neuromorphic chip is as low as 130 mW. The ROLLS neuromorphic processor BIB015 is also a mixed-signal VLSI architecture which can be used as an experimental platform for exploring the properties of computational neuroscience, as well as for developing brain-inspired largescale neuromorphic systems. Once again, the synapse and neuron circuits are implemented in the analog domain and are combined with digital circuits, such as latches and asynchronous digital AER logic blocks. The ROLLS neuromorphic processor operates in real time, consumes approximately 4 mW and contains, in total, 256 neurons and 131072 synapses. An adaptive exponential I&F neuron model similar to the one used in the HICANN chip is also employed here. By default, each neuron is connected to a specific set of 512 synapses. Half of them are learning synapses, modeling the LTP mechanisms, and the other half are STP synapses with programmable synaptic weights. LTP is implemented based on the bistable spike-driven plasticity rule BIB003 . Additionally, a control circuit is used to enable allocation of multiple sets of synapses to the neurons by disconnecting and sacrificing the unused neurons. Moreover, there are 512 extra virtual synapses for modeling all types of synapses that have shared weights and time constants. SpiNNaker BIB009 is a massively parallel, fully digital multiprocessor architecture for modeling and simulating large-scale SNNs. It can model neural networks up to a billion neurons and a trillion synapses with computations performed in BRT. The main processing building block is the SpiNNaker chip multiprocessor (CMP), which contains 18 ARM microprocessors and two routers. One of the routers handles the communication between the microprocessors and the peripherals, while the other handles the communication between microprocessors of different CMPs. Each of the microprocessors is capable of simulating up to 1000 spiking neurons and around 1000 synapses. However, out of the 18 microprocessors, only 16 are available for emulating neurons, as the rest are used for monitoring and fault tolerance purposes. The architecture allows for an integration of up to 65536 CMPs, with each CMP consuming 1 W. The fact that ARM microprocessors are used makes it possible to implement arbitrary neuron models and learning rules, a big advantage when compared to the analog neuromorphic chips previously analyzed. Furthermore, the synaptic weights are 16-b quantities stored in a tightly coupled memory (TCM) or SDRAM and the asynchronous AER protocol is used to model the massive interconnectivity of SNNs. IBM TrueNorth BIB012 is also a fully digital neuromorphic chip. It is fabricated in Samsung's 28-nm CMOS process technology and is well-suited for many applications that use complex low-power neural networks in real time, such as classification and multiobject detection tasks. It is assembled from 4096 parallel and distributed neurosynaptic cores, interconnected in an on-chip mesh network that integrates one million programmable spiking neurons and 256 million configurable synapses. The digital neurons in the neurosynaptic cores are an implementation of the standard leaky I&F neuron model. Each core has allocated 100 kb onchip SRAM memory in order to store synaptic and neuron parameters, as well as a router. The router passes spike packets between adjacent cores and delivers them to target cores, asynchronously. Although TrueNorth is a flexible architecture that leverages advances in packaging, 3-D integration, and novel devices, synaptic plasticity mechanisms are not supported. Table 1 summarizes the most important features of the aforementioned six neuromorphic platforms. Measurements related to power are not from the same benchmark so they cannot be compared directly. Specifically, for the HICANN chip, there are no power data available in the literature. Also, the fact that, in some cases, the number of neurons and synapses varies is because the supported neural network topologies are not fixed, i.e., they can be reconfigured.