Survey of Memory Management Techniques for HPC and Cloud Computing <s> K. PROGRAMMING MODELS <s> A lot of effort from academia and industry has been invested in exploring the suitability of low-power embedded technologies for HPC. Although state-of-the-art embedded systems-on-chip (SoCs) inherently contain GPUs that could be used for HPC, their performance and energy capabilities have never been evaluated. Two reasons contribute to the above. Primarily, embedded GPUs until now, have not supported 64-bit floating point arithmetic - a requirement for HPC. Secondly, embedded GPUs did not provide support for parallel programming languages such as OpenCL and CUDA. However, the situation is changing, and the latest GPUs integrated in embedded SoCs do support 64-bit floating point precision and parallel programming models. In this paper, we analyze performance and energy advantages of embedded GPUs for HPC. In particular, we analyze ARM Mali-T604 GPU - the first embedded GPUs with OpenCL Full Profile support. We identify, implement and evaluate software optimization techniques for efficient utilization of the ARM Mali GPU Compute Architecture. Our results show that, HPC benchmarks running on the ARM Mali-T604 GPU integrated into Exynos 5250 SoC, on average, achieve speed-up of 8.7X over a single Cortex-A15 core, while consuming only 32% of the energy. Overall results show that embedded GPUs have performance and energy qualities that make them candidates for future HPC systems. <s> BIB001 </s> Survey of Memory Management Techniques for HPC and Cloud Computing <s> K. PROGRAMMING MODELS <s> Future exascale systems will require very aggressive memory systems simultaneously delivering huge storage capacities and multi-TB/s bandwidths. To achieve the bandwidth targets, in-package, die-stacked memory technologies will likely be necessary. However, these integrated memories do not provide enough capacity to achieve the overall per-node memory size requirements. As a result, conventional off-package memory (e.g., DIMMs) will still be needed. This creates a "two-level memory" (TLM) organization where a portion of the machine's memory space provides high bandwidth, and the remainder provides capacity at a lower level of performance. Effective use of such a heterogeneous memory organization may require the co-design of the software applications along with the advancements in memory architecture. In this paper, we explore the efficacy of programmer-driven approaches to managing a TLM system, using three Exascale proxy applications as case studies. <s> BIB002
Being aware of the OpenCL performance portability issue, OpenCL software optimisation techniques, including memory allocation and mapping, for efficient execution HPC workload on embedded systems-on-chip (SoC) ARM Mali GPU Compute Architecture was proposed in BIB001 . The programmer effort required to manage NUMA-like twolevel memory organisation manually is described in BIB002 . The application programmer is encouraged to invoke the TLM-malloc API for the subset of data structures and memory objects that are important. For the remaining memory objects (including the function call stack, the code segments, and other automatic memory items) a simple OS-based mechanism is assumed. Recent research showed that programmer-driven memory management is the quickest way to reach the target bandwidth for the Exascale architecture. The high performance is achieved only through manual code optimisation and tuning and can not be reached by using only auto configurable memory systems. The main goal in optimising program models for HPC is to provide optimal performance for all applications in various workflows without any user intervention requires, such as application changes based on the knowledge of the low-level details of the hardware. Surveyed research on Memory Management (MM) techniques was summarised with respect to the functionality objectives (Table 1) , the memory methodology (Table 2 ) and the evaluated outcome ( Table 3 ). The overall taxonomy is presented in the Figure 13 . 