IMPLEMENTATION METHOD ON MEDICAL IMAGE COMPRESSION SYSTEM: A REVIEW <s> Figure 7 <s> Motion estimation is a very computational demanding operation during video compression process in standards such as MPEG4, thus special hardware architectures are required to achieve real-time compression performance. The present work focuses on the development of a reconfigurable systolic-based architecture implementing the Full Search Block Matching Algorithm (FBMA) which is highly computing-intensive and requires a large bandwidth to obtain real-time performance. The architecture comprises a smart memory scheme to reduce the number of accesses to data memory and Router elements to handle data movement among different structures inside the same architecture, adding the possibility of chaining interconnection of multiple processing blocks. Every Processing Element (PE) in the array includes a double ALU in order to search multiple macroblocks in parallel. The functionality has been extended to support operations involved in some other low-level image algorithms. Results show that a peak performance in the order of 9 GOPS can be achieved. <s> BIB001 </s> IMPLEMENTATION METHOD ON MEDICAL IMAGE COMPRESSION SYSTEM: A REVIEW <s> Figure 7 <s> Matrix computations are very important in image processing applications. Processing large images or matrices is computationally intensive, power hungry and requires a large amount of memory. This paper discusses the hardware implementation of a factorisation based approach for Haar wavelet transform (HWT) on reconfigurable hardware using distributed arithmetic (DA) principles. The proposed architectures can be integrated into a multiresolution based system for automatic detection and segmentation of tumour in medical images. Two factorisation methodologies are presented and their impact on FPGA implementation is addressed in terms of different resources required and performance achieved. <s> BIB002 </s> IMPLEMENTATION METHOD ON MEDICAL IMAGE COMPRESSION SYSTEM: A REVIEW <s> Figure 7 <s> ABSTRACT The evolution of computer and Internet has brought demand for powerful and high speed data processing, but in such complex environment fewer methods can provide perfect solution. To handle above addressed issue, parallel computing is proposed as a solution to the contradiction. This paper provides solution for the addressed issues of demand for high speed data processing. This paper demonstrates an effective design for the Matrix Multiplication using Systolic Architecture on Reconfigurable Systems (RS) like Field Programmable Gate Arrays (FPGAs). Here, the systolic architecture increases the computing speed by combining the concept of parallel processing and pipelining into a single concept. Here, the RTL code is written for matrix multiplication with systolic architecture and matrix multiplication without systolic architecture in Verilog HDL, compiled and simulated by using Modelsim XE III 6.4b, Synthesized by using Xilinx ISE 9.2i and targeted to the device xc3s500e-5-ft256 and then finally the designs are compared to each other to evaluate the performance of proposed architecture. The proposed Matrix Multiplication with systolic architecture is enhances the speed of matrix multiplication by twice of conventional method. <s> BIB003 </s> IMPLEMENTATION METHOD ON MEDICAL IMAGE COMPRESSION SYSTEM: A REVIEW <s> Figure 7 <s> In this paper we present FPGA implementation of Artificial Neural Networks for image compression. Image compression is a process which minimizes the size of an image file to an unacceptable level without degrading the quality of the image. The main components of an artificial neuron are adders and multipliers. In order to implement neural network, large number of adders and multipliers are required. The main constraint in the implementation of neural network is the area occupied by the multipliers. In order to overcome this area we propose the use of constant coefficient multiplier like distributed arithmetic (DA) based multiplier. The area efficiency is obtained by use of adders and shifters in Distributed arithmetic based multiplier architecture. The distributed arithmetic based multiplier is made use to implement 4∶4∶2∶2∶4 and 16∶16∶8∶8∶16 artificial neural network architecture for image compression. These architectures are implemented on FPGA and area efficiency is obtained. <s> BIB004
Basic block diagram of LUT-based DA BIB004 In addition, DA can also be used to compute sum of product and the implementation of DA-based multiplier exploits the LUT architecture. This design was targeted on Xilinx Virtex-2 pro and the result of using DA architecture has shown speed (throughput) increment by 25%. According to BIB002 , DA provides an efficient method of computing vectors or matrix multiplication by means of bit level rearrangement of the multiplyaccumulate process. This process distributes arithmetic operations rather than grouping them as multipliers would normally do. Implementation of FPGAs using DA architecture will speed up the efficiency of mechanization, which unfortunately will become slower, particularly when deadline with large transformation because of its bit serial nature. However, some modification such as portioning and bit pairing can significantly increase its performance. Figure 8 illustrates the proposed architecture for 1-D HWT (N=8) based on the DA principle. BIB002 On the other hand, systolic array (SA) design techniques are an array of processing elements (PE), called cells. Each cell is connected to a small number of their nearest neighbours in a mesh-like topology. Each cell performs a sequence of operation on the data that flows between them BIB003 . PE at each step takes input data from one or more neighbours (Left and Top), processes it and, in the next step, output results in the opposite direction (Right and Bottom). Figure 9 illustrates, the proposed two-dimensional systolic architecture for 3 by 3 matrices. The proposed architecture was designed for matrix multiplication and targeted for FPGAs devices. The parallel processing and pipelining were introduced into the proposed systolic array to enhance the speed and reduce the complexity of the matrix multiplier. The 2-D processor array and a smart schema for communication and data storage were proposed by Saldana and Arias BIB001 as shown in Figure 10 . The purpose of this architecture is to allow process chaining that can be replicated inside the same FPGAs several times in order to process different algorithms independently. Each PE has been specially designed to support the operations involved in ME. In addition, to provide more capacity to the architecture, the PE's functionality has been extended to support most window-based operation in image processing; multiplication, addition, subtraction, accumulation, maximum, minimum and absolute value. This research had also implemented the Handle-C, DK4 and synthesis technology (XST) tools.