Multi-Channel Neural Recording Implants: A Review <s> Systematic Technique <s> A highly sensitive CMOS chopper amplifier for low-frequency applications is described. It is realized with a second-order low-pass selective amplifier using a continuous-time filtering technique. The circuit has been integrated in a 3-/spl mu/m p-well CMOS technology. The chopper amplifier DC grain is 38 dB with a 200-Hz bandwidth. The equivalent input noise is 63 nV//spl radic/Hz and free from 1/f noise. The input offset is below 5 /spl mu/V for a tuning error less than 1%. The amplifier consumes only 34 /spl mu/W. <s> BIB001 </s> Multi-Channel Neural Recording Implants: A Review <s> Systematic Technique <s> These Ecole polytechnique federale de Lausanne EPFL, n° 802 (1989) Reference doi:10.5075/epfl-thesis-802Print copy in library catalog Record created on 2005-03-16, modified on 2016-08-08 <s> BIB002 </s> Multi-Channel Neural Recording Implants: A Review <s> Systematic Technique <s> In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input. <s> BIB003 </s> Multi-Channel Neural Recording Implants: A Review <s> Systematic Technique <s> A low-noise CMOS instrumentation amplifier intended for low-frequency thermoelectric microsensor applications is presented that achieves submicrovolt offset and noise. Key to its performance is the chopper modulation technique combined with a bandpass filter and a matching on-chip oscillator. No external components or trimming are required. The achievable offset performance depends on the bandpass filter Q and the oscillator-to-bandpass filter matching accuracy. Constraints are derived for an optimum Q and a given matching accuracy. The improvement of common-mode rejection ratio (CMRR) in chopper amplifiers is discussed. The amplifier features a total gain of 77/spl plusmn/0.3 dB and a bandwidth of approximately 600 Hz. The measured low-frequency input noise is 8.5 nV//spl radic/Hz and the input offset is 600 nV. The measured low-frequency CMRR is better than 150 dB. The circuit has been implemented in a standard 1-/spl mu/m single-poly CMOS process. <s> BIB004 </s> Multi-Channel Neural Recording Implants: A Review <s> Systematic Technique <s> A low-noise chopper-modulated CMOS instrumentation amplifier intended for low-frequency thermoelectric micro-sensors is presented, that achieves sub-microvolt offset and noise. Key to its performance is a delayed chopping scheme combined with a first order low-pass filter. The achievable reduction of residual offset due to charge injection spikes of the input modulator has been analyzed and experimentally verified. Compared to a similar design with a second order bandpass-filter [1], matching requirements have been relaxed by more than one order of magnitude and the capacitor area could be substantially reduced. The chopping clock does not need to be matched to any particular circuit parameter and can be set within a certain range. The amplifier features a gain of 70, a low-frequency input noise of 8.5 nV/√Hz, sub-microvolt offset and a minimum dc CMRR of 144 dB. <s> BIB005 </s> Multi-Channel Neural Recording Implants: A Review <s> Systematic Technique <s> The conventional signal demodulator of a chopper amplifier can be substituted by track-and-hold (T/H) and averaging functions. This arrangement provides offset cancellation without requiring low-pass filters and can ignore the residual offset generated by input spikes. A noise analysis shows that this T/H demodulator degrades the white noise signal-to-noise ratio (SNR), although degradation can be minimized by using maximum duty cycle and minimum amplifier bandwidth. <s> BIB006 </s> Multi-Channel Neural Recording Implants: A Review <s> Systematic Technique <s> Offset and 1/f noise have been major enemies for analog IC designers since the enormous increase of the market for digital applications forced them to develop analog front ends in standard CMOS technology. Because static techniques like trimming cannot reduce 1/f noise, solutions had to be found in dynamic offset cancellation. The current work presents an improvement of the chopper amplifier concept, called the nested chopper amplifier. It is shown that with this architecture the residual offset is reduced to <100 nV, while retaining minimal thermal noise in the signal band. <s> BIB007 </s> Multi-Channel Neural Recording Implants: A Review <s> Systematic Technique <s> A low-cost temperature sensor with on-chip sigma-delta ADC and digital bus interface was realized in a 0.5 μm CMOS process. Substrate pnp transistors are used for temperature sensing and for generating the ADC's reference voltage. To obtain a high initial accuracy in the readout circuitry, chopper amplifiers and dynamic element matching are used. High linearity is obtained by using second-order curvature correction. With these measures, the sensor's temperature error is dominated by spread on the base-emitter voltage of the pnp transistors. This is trimmed after packaging by comparing the sensor's output with the die temperature measured using an extra on-chip calibration transistor. Compared to traditional calibration techniques, this procedure is much faster and therefore reduces production costs. The sensor is accurate to within ±0.5 °C (3σ) from -50 °C to 120 °C. <s> BIB008 </s> Multi-Channel Neural Recording Implants: A Review <s> Systematic Technique <s> This paper describes a temperature-to-frequency converter (TFC) implemented in a standard CMOS process. Its output frequency is determined by the phase-shift of an electrothermal filter, which consists of a heater and a tempera- ture sensor realized in the substrate of a standard CMOS chip. The filter's phase-shift is determined by the geometry of the thermal path between the heater and the sensor, and by the temperature-dependent rate at which heat diffuses through the substrate. The resulting temperature-dependent phase-shift is quite well-defined, since filter geometry is defined by lithography, while the thermal diffusivity of the high-purity lightly-doped silicon substrate is essentially constant. The filter was used as the frequency-determining component of a frequency-locked loop (FLL), whose output frequency is then a well-defined function of temperature. Using this approach, a TFC with an inaccuracy of 0.5 C( 3 ) over the industrial temperature range ( 40 Ct o 105 C) has been realized in a standard 0.7- m CMOS process. Index Terms—Chopper modulation, electrothermal integrated circuit, frequency-locked-loop (FLL), temperature sensors. <s> BIB009 </s> Multi-Channel Neural Recording Implants: A Review <s> Systematic Technique <s> A crucial and important part of a medical diagnostics system is the monitoring of the biopotential signals. This paper describes a complete low-power EEG acquisition ASIC that is suitable for miniaturized ambulatory EEG measurement systems. The aim is not only to improve the patients' comfort but also to extend the device applications. <s> BIB010 </s> Multi-Channel Neural Recording Implants: A Review <s> Systematic Technique <s> Significant progress has been made in systems that interpret the electrical signals of the brain in order to control an actuator. One version of these systems senses neuronal extracellular action potentials with an array of up to 100 miniature probes inserted into the cortex. The impedance of each probe is high, so environmental electrical noise is readily coupled to the neuronal signal. To minimize this noise, an amplifier is placed close to each probe. Thus, the need has arisen for many amplifiers to be placed near the cortex. Commercially available integrated circuits do not satisfy the area, power and noise requirements of this application, so researchers have designed custom integrated-circuit amplifiers. This paper presents a comprehensive survey of the neural amplifiers described in publications prior to 2008. Methods to achieve high input impedance, low noise and a large time-constant high-pass filter are reviewed. A tutorial on the biological, electrochemical, mechanical and electromagnetic phenomena that influence amplifier design is provided. Areas for additional research, including sub-nanoampere electrolysis and chronic cortical heating, are discussed. Unresolved design concerns, including teraohm circuitry, electrical overstress and component failure, are identified. <s> BIB011 </s> Multi-Channel Neural Recording Implants: A Review <s> Systematic Technique <s> This paper presents a chopper instrumentation amplifier for interfacing precision thermistor bridges. For high CMRR and DC gain, the amplifier employs a three-stage current-feedback topology with nested-Miller compensation. By chopping both the input and intermediate stages of the amplifier, a 1 mHz 1/f noise corner was achieved at an input-referred noise power spectral density (PSD) of 15 nV/?Hz. To reduce chopper ripple, the amplifier employs a continuous-time AC-coupled ripple reduction loop. Due to its continuous-time nature, the loop causes no noise folding to DC and hence offers improved noise performance over auto-zeroed amplifiers. The loop reduces chopper ripple by more than 60 dB, to levels below the amplifier's own input-referred noise. Furthermore, a maximum input referred offset of 5 ? V and a CMRR greater than 120 dB were measured at a supply current of 230 ?A at 5 V. <s> BIB012 </s> Multi-Channel Neural Recording Implants: A Review <s> Systematic Technique <s> This paper presents a low-power SoC that performs EEG acquisition and feature extraction required for continuous detection of seizure onset in epilepsy patients. The SoC corresponds to one EEG channel, and, depending on the patient, up to 18 channels may be worn to detect seizures as part of a chronic treatment system. The SoC integrates an instrumentation amplifier, ADC, and digital processor that streams features-vectors to a central device where seizure detection is performed via a machine-learning classifier. The instrumentation-amplifier uses chopper-stabilization in a topology that achieves high input-impedance and rejects large electrode-offsets while operating at 1 V; the ADC employs power-gating for low energy-per-conversion while using static-biasing for comparator precision; the EEG feature extraction processor employs low-power hardware whose parameters are determined through validation via patient data. The integration of sensing and local processing lowers system power by 14x by reducing the rate of wireless EEG data transmission. Feature vectors are derived at a rate of 0.5 Hz, and the complete one-channel SoC operates from a 1 V supply, consuming 9 μJ per feature vector. <s> BIB013 </s> Multi-Channel Neural Recording Implants: A Review <s> Systematic Technique <s> Nonhuman primate and human studies have suggested that populations of neurons in the posterior parietal cortex (PPC) may represent high-level aspects of action planning that can be used to control external devices as part of a brain-machine interface. However, there is no direct neuron-recording evidence that human PPC is involved in action planning, and the suitability of these signals for neuroprosthetic control has not been tested. We recorded neural population activity with arrays of microelectrodes implanted in the PPC of a tetraplegic subject. Motor imagery could be decoded from these neural populations, including imagined goals, trajectories, and types of movement. These findings indicate that the PPC of humans represents high-level, cognitive aspects of action and that the PPC can be a rich source for cognitive control signals for neural prosthetics that assist paralyzed patients. <s> BIB014 </s> Multi-Channel Neural Recording Implants: A Review <s> Systematic Technique <s> We review integrated circuits for low-frequency noise and offset rejection as a motivation for the presented digitally-assisted neural amplifier design methodology. Conventional AC-coupled neural amplifiers inherently reject input DC offset but have key limitations in area, linearity, DC drift, and spectral accuracy. Their chopper stabilization reduces low-frequency intrinsic noise at the cost of degraded area, input impedance and design complexity. DC-coupled implementations with digital high-pass filtering yield improved area, linearity, drift, and spectral accuracy and are inherently suitable for simple chopper stabilization. As a design example, a 56-channel 0.13 μm CMOS intracranial EEG interface is presented. DC offset of up to ±50 mV is rejected by a digital low-pass filter and a 16-bit delta-sigma DAC feeding back into the folding node of a folded-cascode LNA with CMRR of 65 dB. A bank of seven column-parallel fully differential SAR ADCs with ENOB of 6.6 are freely moving ratsshared among 56 channels resulting in 0.018 mm ::: 2 ::: effective channel area. Compensation-free direct input chopping yields integrated input-referred noise of 4.2 μV ::: rms ::: over the bandwidth of 1 Hz to 1 kHz. The 8.7 mm ::: 2 ::: chip dissipating 1.07 mW has been validated in vivo in online intracranial EEG monitoring in freely moving rats. <s> BIB015
The neural signal contains important information in the low frequency range (i.e., less than f c ). In this frequency range, the flicker noise is dominant and, to reduce its effects, the chopper stabilization (CHS) technique is usually used BIB003  . The CHS technique operates as follows. Utilizing up-modulation by the first chopper, CHS transposes the neural signal to a higher chopping frequency ( f ch ) where the 1/f noise is not available. In the next step, the amplifier amplifies the signal while adding its 1/f noise and offset. The second chopping modulates up the offset and 1/f noise to f ch while the signal is demodulated back to the baseband. A LPF extracts the original signal with a much higher SNR. CHS can be used in both AC and DC-coupled amplifiers. Examples of utilizing this technique for DC-coupled amplifiers are shown in BIB010 BIB015  . However, in this section, we will further explore the CNF topology of Figure 3a . This is because this topology is more appropriate for multi-channel neural recordings and is more commonly used. In practice, implementing the CHS technique is challenging. The fact that the chopping switches are not ideal, as well as the amplifier, which has offset, limited gain and bandwidth, creates challenges in the design process. Utilizing the CHS technique in a designed LNA with the CFN topology of Figure 3a for the same capacitor size does not reduce the noise at low frequencies, but rather it increases it. The reason for this is explained in  . Figure 7a shows the amplifier utilized in  with the input and output chopper switches and the IRN of OTA. The input chopper switches, accompanied by the OTA input parasitic capacitance (such as the switched capacitor circuits), can be modeled as a resistor, with a value that can be calculated as where C in is the OTA input parasitic capacitance and f ch is the chopping frequency. The total noise of the neural amplifier, when transferring the OTA noise to the input of the neural amplifier by considering the effect of the resistor and other capacitors, could be presented as This equation shows that reducing the total IRN of the amplifier requires a huge C I capacitor. The capacitance value of the C I in  and BIB013 are reported as 300 pF and 1 nF, respectively. These large capacitors increase the area and also decrease the input impedance of the neural amplifier. The latter factor reduces the CMRR and also increases the effect of the main interferences on the system BIB011 . To improve the input impedance of this neural amplifier, an input impedance boosting circuit is utilized in  BIB013 as shown in Figure 7b . The operation of this circuit is such that a larger portion of the input capacitor current is provided by the output of the OTA through positive feedback. This technique increases the input impedance in  from 400 MΩ to 2 GΩ at 1 Hz. Two other challenges regarding the chopper amplifiers are reducing the output ripple and their residual offsets  BIB012 . The offset voltage of the OTA causes the ripple. When the offset voltage becomes amplified after up modulation, it can even have an amplitude that is greater than biopotential signals; therefore, it can limit the amplifier's output headroom. The amplifier designed in BIB012 senses the ripple in the output using a ripple reduction loop (RRL), and compensates for the ripple by applying it to the input through a feedback. Note that since RRL is implemented in analog and works continuously, it increases the power consumption significantly. The residual output offset is mainly due to the non-idealities of the CMOS switches in the input chopper BIB003 . Clock feedthrough and charge injection creates spikes in the input of the OTA and they are amplified and presented in the output of the OTA. Then, these spikes are down modulated with the output chopper and increase the DC at the output, which is called the residual output offset. The authors in BIB013 have compensated for the residual offset by embedding the circuit, called DC servo loop (DSL) in the feedback path. DSL takes samples from the output and provides almost equal current, but in the opposite direction to the offset current by utilizing a G m − C filter and applying it to the input of the chopper. The main drawback of this circuit is that it requires a huge off-chip capacitor (greater than 10 µF) to decrease the low-cutoff frequency to the appropriate value. To reduce the power consumption while removing the ripples in BIB012 and to avoid huge off-chip capacitor in BIB013 , a new mechanism called a digitally-assisted calibration loops is proposed in  that removes both the ripple and the offset. This mechanism provides a digital implementation of both RRL and DSL. There are also more examples in the literature that utilize techniques to reduce the charge injection [79] . Three examples of these techniques that are employed in the chopper amplifiers are nested chopping, spike filtering, and the use of delayed modulation or a dead-band. Figure 8a shows the schematic of the nested chopper amplifier BIB007  BIB008 BIB009 . As illustrated in the figure, this architecture utilizes a pair of internal and external choppers, where the frequency of the internal chopper should be chosen to be greater than 1/f noise corner frequency ( f C ). The frequency of the external chopper ( f chL ), which is a relatively low frequency, can be optimized for the input signal efficiently. With this technique, BIB007 has achieved 100 nV offset, with f chH = 2 KHz and f chL = 15.6 HZ. A spike filtering technique is another approach for reducing the residual offset. As explained earlier, the charge injection in the MOS switches of the input chopper creates spikes in the output of the amplifier, which eventually appears in the output of the second chopper as the residual offset in the frequency spectrum. Therefore, we can assume that these spikes have odd harmonics in the frequency domain BIB002 . By filtering these spikes, the residual offset can be reduced significantly. Figure 8b shows the schematic of this technique used in BIB001 BIB004 . Unlike the previous method, where a filter is used to reduce the residual offset in the frequency domain, in the delayed modulation or dead-band technique, the residual offset is mitigated in the time domain. Figure 9a shows the schematic of the delayed modulation technique. As shown in the figure, this technique utilizes a modulator M, amplifier A 1 , and demodulator D. In BIB005 , an amplifier is used followed by a LPF to shape the spikes and the second chopper with a constant delay is used (as shown in Figure 9b ) to demodulate the spikes. This causes the average of the signal to be zero which is extracted by a LPF. Another method, which is called dead-band or guard-band, that has a relatively simpler implementation, is shown in Figure 9c . In this method, there is no modulation when there is spike in the output signal. This technique is used in BIB006  . Another approach to implementing the CHS technique in the AC-coupled CFN topology, as shown in Figure 10a , is to use a chopper in front of the input coupling capacitors   . In this figure, there are two feedback loops that determine the midband gain and high pass corner of the amplifier. However the main drawback of this architecture is its low input impedance, which is calculated as where f ch is the chopping frequency and f sig is signal frequency. Increasing the f ch causes a more relaxed implementation of LPF on the one hand, and on the other hand, it reduces the input impedance according to Equation BIB014 . The input impedance is reported to be about 8 MΩ in  . In order to improve the low impedance of the design in   , a positive feedback loop (PFL) shown in Figure 10b is proposed in  . This circuit takes samples from the output and then provides a large portion of the current of the input coupling capacitors. The measurement results show that the input impedance increases from 6 MΩ to 30 MΩ. Note that due to the presence of parasitic input capacitances, the boost factor and the original input-impedance are lower than the expected (100 and 8 MΩ, respectively). Finally, at the end of this section, we analyze BIB015 , as a sample of the DC-coupled neural amplifier. Figure 11 shows the block diagram of this amplifier, which has 56 channels. In this architecture, a digital DSL is used in each channel to remove the input DC offset (caused by recording electrodes). In addition, CHS is used to reduce the 1/ f noise of the LNA. Avoiding huge capacitors in the DC coupled architecture due to utilizing a digital DSL reduces the chip area. However, due to utilizing CHS at a much higher bandwidth (10 Hz-5 KHz) than f C ( 100 Hz, flicker noise corner frequency), it does not present a good noise reduction performance. The reported IRN and NEF are 5.4 µV rms and 7, respectively, with a offset voltage of 50 mV. 