DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> BASIC CONCEPT OF DCO <s> An energy-efficient 915MHz FSK transceiver for wireless body sensor network (BSN) applications is implemented in 0.18um CMOS technology with 0.7V supply. A transceiver architecture based on injection-locked frequency divider (ILFD) is proposed for the low energy consumption. In the receiver, through the ILFD in the signal path, the received FSK signal is converted to amplitude-modulated signal which is applied to the following envelope detector. In the transmitter, the ILFD is used as digitally-controlled oscillator (DCO) which replaces the frequency synthesizer to eliminate the crystal oscillator (XO). The receiver and transmitter consume 420uW and 700uW, respectively, at −10dBm output power with a data rate of 5Mb/s, corresponding to energy consumption of 84pJ per received bit and 140pJ per transmitted bit. <s> BIB001 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> BASIC CONCEPT OF DCO <s> An all-digital phase-locked loop (ADPLL) with all components working with time interval or period signals is demonstrated. The ADPLL consists mainly of a free-running ring oscillator (FRO), a time to digital converter (TDC), a digitally controlled oscillator (DCO), a digital divider and a digital loop filter. In the proposed architecture, the TDC and DCO have an equal time resolution from the common FRO. The digital divider keeps the loop gain constant when the frequency multiplication factor changes. As a result, the ADPLL is inherently stable regardless of the variations of the process, supply voltage and temperature (PVT). The ADPLL is fabricated in 0.13 ?m CMOS process. Measurement results show that it works well over wide operation conditions, with the input frequencies ranging from 37.5 KHz to 25 MHz, frequency multiplication factors from 10 to 255, output frequencies from 10 MHz to 500 MHz, and supply voltages from 0.6 V to 1.6 V. <s> BIB002 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> BASIC CONCEPT OF DCO <s> A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) is presented. The time-windowed TDC uses a two-step structure with an inverter- and a Vernier-delay time-quantizer to improve time resolution, which results in low phase noise. Time-windowed operation is implemented in the TDC, in which a single-shot pulse-based operation is used for low power consumption. The test chip implemented in 90-nm CMOS technology exhibits in-band phase noise of , where the loop-bandwidth is set to 500 kHz with a 40-MHz reference signal, and out-band noise of at a 1-MHz offset frequency. The chip core occupies 0.37 and the measured power consumption is 8.1 mA from a 1.2-V power supply. <s> BIB003 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> BASIC CONCEPT OF DCO <s> This paper presents an all-digital impulse radio ultra-wideband (IR-UWB) transmitter. All functional blocks in the transmitter are implemented with digital standard cells and automatically place-and-routed by design tools. The center frequency and the bandwidth of the UWB pulses are digitally tuned to compensate for variations, or target different applications. This paper also proposes a calibration scheme and modeling of a cell-based digitally controlled oscillator (DCO), which takes systematic mismatch from automatic place-and-route into account. The transmitter is fabricated in a 65 nm CMOS process, and occupies a core area of 0.032 mm2. The transmitter operates in the 3.1-5.0 GHz UWB band with leakage power of 170 μW and active energy consumption ranges from 8 pJ/pulse to 16 pJ/pulse, which combine to a total minimum energy/pulse of 12 pJ/pulse at 50 Mb/s. <s> BIB004 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> BASIC CONCEPT OF DCO <s> This paper describes the design and implementation of an all-digital clock and data recovery circuit (ADCDR) for multigigabit/s operation. The proposed digitally-controlled oscillator (DCO) incorporating a supply-controlled ring oscillator with a digitally-controlled resistor (DCR) generates wide-frequency-range multiphase clocks with fine resolution. With an adaptive proportional gain controller (APGC) which continuously adjusts a proportional gain, the proposed ADCDR recovers data with a low-jitter clock and tracks large input jitter rapidly, resulting in enhanced jitter performance. A digital frequency-acquisition loop with a proportional control greatly reduces acquisition time. Fabricated in a 0.13-μm CMOS process with a 1.2-V supply, the ADCDR occupies 0.074 mm2 and operates from 1.0 Gb/s to 4.0 Gb/s with a bit error rate of less than 10-14. At a 3.0-Gb/s 231 - 1 PRBS, the measured jitter in the recovered clock is 3.59 psrms and 29.4 pspp, and the power consumption is 11.4 mW. <s> BIB005 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> BASIC CONCEPT OF DCO <s> This paper introduces a ΔΣ fractional-N digital PLL based on a single-bit TDC. A digital-to-time converter, placed in the feedback path, cancels out the quantization noise introduced by the dithering of the frequency divider modulus and permits to achieve low noise at low power. The PLL is implemented in a standard 65-nm CMOS process. It achieves - 102-dBc/Hz phase noise at 50-kHz offset and a total absolute jitter below 560 fsrms (integrated from 3 kHz to 30 MHz), even in the worst-case of a -42-dBc in-band fractional spur. The synthesizer tuning range spans from 2.92 GHz to 4.05 GHz with 70-Hz resolution. The total power consumption is 4.5 mW, which leads to the best jitter-power trade-off obtained with a fractional-N synthesizer. The synthesizer demonstrates the capability of frequency modulation up to 1.25-Mb/s data rate. <s> BIB006 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> BASIC CONCEPT OF DCO <s> This brief presents a built-in self-calibration (BISC) circuit to correct nonmonotonic responses in a digitally controlled oscillator (DCO) with a cascading structure. Generally speaking, a cascading DCO structure has the advantages of low power consumption and a small chip area. Nevertheless, when a subfrequency band is changed, an overlap region between subfrequency bands causes a large phase error and cycle-to-cycle jitter in an output clock. The proposed BISC circuit can reduce this problem; thus, it is very suitable for a low-power all-digital phase-locked loop design in system-on-a-chip applications. The proposed DCO, implemented with a standard performance 65-nm complementary metal-oxide-semiconductor process, can output frequency ranges from 47.8 to 538.7 MHz. The total power consumption of the DCO with a calibration circuit is 0.142 mW at 58.7 MHz and 0.205 mW at 481.6 MHz. <s> BIB007 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> BASIC CONCEPT OF DCO <s> This paper proposes an oppositely coupled varactor pair and reports the measured results for applying to a test digitally controlled oscillator (DCO). The pair exploits the differences between the accumulation region capacitance and inversion region capacitance of pMOS varactors. The novel varactor pairs provide much smaller switchable capacitances than those of other approaches, and hence, the test DCO for verifying the property of the pair achieves the high-frequency resolution. The pairs and test DCO are implemented in a 0.18-μm CMOS process. The switchable discrete capacitance of 32 aF is obtained by using the novel varactor pairs, and the test DCO has a frequency resolution of about 110 kHz at 5.8 GHz. Furthermore, ΔC of 4-aF and 14-kHz frequency resolution can be obtained through the dithering processes. The test DCO achieves a low phase noise of -117.6 dBc/Hz at 1-MHz offset from 5.8 GHz. <s> BIB008 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> BASIC CONCEPT OF DCO <s> An energy-efficient crystal-less double-FSK transceiver for wireless body-area-network (WBAN) sensor nodes is implemented in 0.18-μm CMOS technology with a 1-V supply. The injection-locking digitally controlled oscillator (IL-DCO) replaces the crystal oscillator (XO), which leads to significantly reduce the energy consumption and system cost. With the proposed calibration method using an injection-locking detector (IL-detector), the frequency drift of DCO can be calibrated within 100-kHz accuracy over 100° temperature variation. For the full satisfaction to the WBAN requirements, such as wide range of quality of service in terms of data rate, bit error rate, and network coexistence, we adopt a scalable double-FSK modulation scheme with divider-based transmitter by a power-efficient switching modulator. As a result, the fabricated crystal-less double-FSK WBAN compatible sensor node transceiver consumes 1 and 2 mW in calibrating and transmitting modes, respectively, at a data rate of up to 10 Mb/s, providing an 80 MHz reference source with 100-kHz accuracy by auto-calibrated DCO. <s> BIB009 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> BASIC CONCEPT OF DCO <s> This brief presents a low-power small-area digitally controlled oscillator (DCO). The coarse-fine architecture with binary-weighted delay stages is applied for the delay range and resolution optimization. The coarse-tuning stage of the DCO uses the interlaced hysteresis delay cell, which is power and area efficient, as compared with conventional delay cells. The glitch protection synchronous circuit makes the DCO easily controllable without generating glitches. A demonstrative all-digital phase-locked loop using the DCO is fabricated in a 90-nm CMOS process with an active area of 0.0086 mm2. The measured output frequency range is 180-530 MHz at the supply of 1 V. The power consumption are 466 and 357 μW at 480- and 200-MHz output, respectively. <s> BIB010 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> BASIC CONCEPT OF DCO <s> The recently proposed NAND-based digitally controlled delay-lines (DCDL) present a glitching problem which may limit their employ in many applications. This paper presents a glitch-free NAND-based DCDL which overcame this limitation by opening the employ of NAND-based DCDLs in a wide range of applications. The proposed NAND-based DCDL maintains the same resolution and minimum delay of previously proposed NAND-based DCDL. The theoretical demonstration of the glitch-free operation of proposed DCDL is also derived in the paper. Following this analysis, three driving circuits for the delay control-bits are also proposed. Proposed DCDLs have been designed in a 90-nm CMOS technology and compared, in this technology, to the state-of-the-art. Simulation results show that novel circuits result in the lowest resolution, with a little worsening of the minimum delay with respect to the previously proposed DCDL with the lowest delay. Simulations also confirm the correctness of developed glitching model and sizing strategy. As example application, proposed DCDL is used to realize an All-digital spread-spectrum clock generator (SSCG). The employ of proposed DCDL in this circuit allows to reduce the peak-to-peak absolute output jitter of more than the 40% with respect to a SSCG using three-state inverter based DCDLs. <s> BIB011 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> BASIC CONCEPT OF DCO <s> Two new millimeter-wave digitally controlled oscillators (DCOs) that achieve a tuning range >10% and fine frequency resolution 1 MHz simultaneously are described. Switched metal capacitors distributed across a passive resonator tune the oscillation frequency. To obtain sub-MHz frequency resolution, tuning step attenuation techniques exploiting an inductor and a transformer are proposed. Two 60-GHz implementations, a fine-resolution inductor-based DCO (L-DCO) and a transformer-coupled DCO (T-DCO), are demonstrated in 90-nm CMOS. The phase noise of both DCOs is lower than -90.5 dBc/Hz at 1-MHz offset across 56-62 GHz. The T-DCO achieves a fine frequency tuning step of 2.5 MHz, whereas the L-DCO tuning step is over one order of magnitude finer at 160 kHz. The L-DCO and T-DCO consume 10 and 12 mA, respectively, from a 1.2-V supply. The size of each DCO core is 0.4 ×0.4 mm2. <s> BIB012 </s> DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW <s> BASIC CONCEPT OF DCO <s> This paper presents a two-point modulator architecture which is immune to the nonlinear effect of the digitally-controlled oscillator (DCO). By utilizing a 1 bit ΔΣ modulation with embedded finite-impulse response (FIR) filtering the high-pass modulation path does not suffer from the DCO gain nonlinearity, thus requiring absolute gain calibration only. The digital FIR filter in the high-pass modulation path not only suppresses quantization noise but also reduces noise coupling with time-interleaved switching of partitioned capacitors. A hybrid FIR filtering method is also employed for the low-pass modulation path to enhance the linearity of the fractional-N phase-locked loop (PLL). A 1.8 GHz two-point modulator based on a semi-digital PLL is implemented in 65 nm CMOS consuming 6.9 mW from a 1 V supply. At the divide-by-2 output frequency of 913.2 MHz, the error-vector magnitude (EVM) values of 1.79% and 1.63% are achieved with 1.08 Mb/s and 270 kb/s GMSK modulation respectively. When the 1.08 Mb/s GFSK modulation is performed with the same PLL parameters, the EVM value of 1.96% is achieved. <s> BIB013
A standard DCO design can be divided into two main techniques. The first uses fixed capacitance loading to change the driving strength dynamically while the second tune the capacitance loading by using shunt capacitance technique BIB001 . Both method results in reasonable frequency operating range and produce good linear frequency when power dissipation does not been taken into consideration. In a DCO design, there is trade-off between the maximum frequency and the operating range for a DCO can achieve. By adding more capacitance load will increase the operating range causes higher power consumption and a lower maximum frequency. Figure 2 shows basic DCO cell. A functional DCO produces an oscillation period of TDCO BIB001 . With reference to the digital input word; d, TDCO can be written as: DCO transfer equation can also derive TDCO period of oscillation that linear proportional to d along with an offset. Thus, the oscillation period can be rewritten as: BIB001 where d is digital control bits (DCB), Tstep is the period of the quantization step, and Toffset is a constant offset period. Figure 2 show the conventional driving strengthcontrolled DCO. Calculating the constant delay of each cell is shown as follows: where W is width of transistor, C1 and C2 are the total capacitances at the drain M1 and M1' and R1 and R2 are the equivalent resistances of M1 and M1' respectively which mainly consist source to body and drain to body capacitances. Assume the driving strength is the same; this standard cell can obtain delay tuning range by using the equation as follow: Base on the Equation (5), the width of the transistor M1 needs to be increased in order to achieve a good linear tuning range. If the R1 is decrease, the delay tuning range value will be smaller. By increasing the capacitance load, the tuning range will increase as well keeping the linear response. But this will decrease maximum frequency and will increase the power consumption of the DCO. The DCO evaluated by its power consumption, speed, chip area, frequency range, supply voltage and resolution [15] , BIB001 BIB009 BIB010 . Low power dissipation requires reducing DCO power consumption to meet the low power demands in system on chip (SoC) design BIB004 , BIB009 BIB010 . For ADPLL, 50% of the total power contributed by DCO which is a major disadvantage. Therefore, power saving a major concern in many electronic devices. DCO requires multiple-phase clock or high frequency BIB005 BIB013 [25] . The attributes of frequency generation cause difficulty to the DCOs to operate at wide frequency range BIB006 . Voltage supply is the voltage used by the circuit to operate BIB011 BIB007 . Reducing it will save power. Finally, to get fine tuning, it is important for the oscillator to have high resolution. Figure 3 shows a simplified schematic of DCO used varactor pairs technique BIB008 , BIB002 BIB003 BIB012 . There are two independent varactor banks in the DCO. The first is fine tuning bank and the other is coarse tuning bank. The fine-tuning bank comprise and utilize unit weighted encoding of the proposed varactor pairs. On the other hand, the coarse tuning bank utilizes binary-weighted encoding. It also consists of the conventional pMOS varactors. 5-bit fine tuning bank and 8-bit course tuning bank can be controlled by the DCO. Fine-tuning frequency control word (FFCW) controls each pair of varactors. In addition, the DCO can also be designed with lesser number of pairs. Figure 3 shows that there are five pMOS pairs are used for simple operation. FCWROW controls the row while the FCW controls the untied unit varactor pair.