Survey of Memory Management Techniques for HPC and Cloud Computing <s> E. POLICIES <s> In parallel architectures that have a Non-Uniform Memory Access (NUMA) behavior, the mapping of memory pages to NUMA nodes influences the performance of parallel applications. In order to improve traditional data mapping policies, two basic strategies can be employed: optimizing locality or balance of memory accesses. In a locality-based policy, memory pages are mapped to nodes that access the page the most. In a balance-based policy, memory pages are mapped such that the number of memory accesses resolved by each memory controller is similar. In this paper, we perform an in-depth exploration of these data mapping policies on the performance of parallel applications. We introduce metrics that describe their memory access behavior and evaluate their suitability for data mapping. We also present new mapping policies that focus on locality, balance or both. These policies were evaluated on three different NUMA architectures with applications from the NAS-OMP and PARSEC benchmark suites. Results show that the performance improvements of each policy depend on the characteristics of the applications and machines. Choosing the wrong policy can actually hurt the performance compared to the default first-touch mapping. Compared to traditional mapping policies and to policies that only focus on either locality or balance, taking into account both locality and balance results in the highest improvements. Furthermore, it avoids the performance reduction caused by the wrong data mapping. <s> BIB001 </s> Survey of Memory Management Techniques for HPC and Cloud Computing <s> E. POLICIES <s> DRAM technology faces density and power challenges to increase capacity because of limitations of physical cell design. To overcome these limitations, system designers are exploring alternative solutions that combine DRAM and emerging NVRAM technologies. Previous work on heterogeneous memories focuses, mainly, on two system designs: PCache, a hierarchical, inclusive memory system, and HRank, a flat, non-inclusive memory system. We demonstrate that neither of these designs can universally achieve high performance and energy efficiency across a suite of HPC workloads. In this work, we investigate the impact of a number of multi-level memory designs on the performance, power, and energy consumption of applications. To achieve this goal and overcome the limited number of available tools to study heterogeneous memories, we created HMsim, an infrastructure that enables n-level, heterogeneous memory studies by leveraging existing memory simulators. We, then, propose HpMC, a new memory controller design that combines the best aspects of existing management policies to improve performance and energy. Our energy-aware memory management system dynamically switches between PCache and HRank based on the temporal locality of applications. Our results show that HpMC reduces energy consumption from 13% to 45% compared to PCache and HRank, while providing the same bandwidth and higher capacity than a conventional DRAM system. <s> BIB002 </s> Survey of Memory Management Techniques for HPC and Cloud Computing <s> E. POLICIES <s> System reliability is a first-class concern as technology continues to shrink, resulting in increased vulnerability to traditional sources of errors such as single event upsets. By tracking access counts and the Architectural Vulnerability Factor (AVF), application data can be partitioned into groups based on how frequently it is accessed (its "hotness") and its likelihood to cause program execution error (its "risk"). This is particularly useful for memory systems which exhibit heterogeneity in their performance and reliability such as Heterogeneous Memory Architectures – with a typical configuration combining slow, highly reliable memory with faster, less reliable memory. This work demonstrates that current state of the art, performance-focused data placement techniques affect reliability adversely. It shows that page risk is not necessarily correlated with its hotness; this makes it possible to identify pages that are both hot and low risk, enabling page placement strategies that can find a good balance of performance and reliability. This work explores heuristics to identify and monitor both hotness and risk at run-time, and further proposes static, dynamic, and program annotation-based reliability-aware data placement techniques. This enables an architect to choose among available memories with diverse performance and reliability characteristics. The proposed heuristic-based reliability-aware data placement improves reliability by a factor of 1.6x compared to performance-focused static placement while limiting the performance degradation to 1%. A dynamic reliability-aware migration scheme, which does not require prior knowledge about the application, improves reliability by a factor of 1.5x on average while limiting the performance loss to 4.9%. Finally, program annotation-based data placement improves the reliability by 1.3x at a performance cost of 1.1%. <s> BIB003
In BIB001 it was noticed that significant performance improvements could be achieved with data mapping in NUMA architectures. Generally, locality-based policies improve performance more than policies that are based on memory balance. A mixed policy was proposed to address the trade-off between optimising locality and balancing memory controllers. In BIB003 it was demonstrated that the performance-focused data placement technique might result in lower overall reliability. The static, dynamic, and program annotation-based reliability-aware data placement techniques were proposed. The reliability-aware data placement approach analyses memory pages for their hotness (e.g., how 'active' the page is currently in the cache) and vulnerability at runtime. To avoid prior profiling, the reliabilityaware dynamic migration schemes were developed. The co-designed hardware-software mechanism HpMC BIB002 implements a policy switching engine based on the temporal locality of applications and several new components that extend a single-level memory controller to facilitate switching policies and migrating pages. The periodical analysis of the temporal locality guides the switch between a hierarchical inclusive memory system PCache and a flat exclusive memory system HRank to deliver high performance and energy efficiency. Traditional performance-enhancing mechanisms rely on increasing the locality of memory accesses. In addition to the locality-based techniques, recent studies have also proposed to consider several factors when performing memory mapping, such as balance and reliability, to avoid overloading and guarantee fault tolerance. A brief taxonomy of the proposed policies is presented in Figure 6 . Taking all factors into account while performing the mapping can result in more significant improvements than when relying on a single metric only. However, it makes policy computationally expensive and error-prone. Besides, most of the current techniques consider a single application. Since real HPC systems execute several applications at the same time, the mapping decisions can conflict between them.