Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s>  <s> We present an analog integrated circuit containing a matched pair of silicon cochleae and an address event interface. Each section of the cochlea, modeled by a second-order low-pass filter, is followed by a simplified inner hair cell circuit and a spiking neuron circuit. When the neuron spikes, an address event is generated on the asynchronous data bus. Measurements with pure tones played from different positions are presented. <s> BIB001 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s>  <s> Neurobiological processing systems are remarkable computational devices. They use slow, stochastic, and inhomogeneous computing elements and yet they outperform today's most powerful computers at tasks such as vision, audition, and motor control, tasks that we perform nearly every moment that we are awake without much conscious thought or concern. Despite the vast amount of resources dedicated to the research and development of computing, information, and communication technologies, today's fastest and largest computers are still not able to match biological systems at robustly accomplishing real-world tasks. While the specific algorithms and representations that biological brains use are still largely unknown, it is clear that instead of Boolean logic, precise digital representations, and synchronous operations, nervous systems use hybrid analog/digital components, distributed representations, massively parallel mechanisms, combine communications with memory and computation, and make extensive use of adaptation, self-organization, and learning. On the other hand, as with many successful man-made systems, it is clear that biological brains have been co-designed with the body to operate under a specific range of conditions and assumptions about the world. ::: ::: Understanding the computational principles used by the brain and how they are physically embodied is crucial for developing novel computing paradigms and guiding a new generation of technologies that can combine the strengths of industrial-scale electronics with the computational performance of brains. <s> BIB002 </s> Toward Silicon-Based Cognitive Neuromorphic ICs—A Survey <s>  <s> Neuromorphic silicoN NeuroNs: state of the art Complementary metal-oxide-semiconductor (CMOS) transistors are commonly used in very-large-scale-integration (VLSI) digital circuits as a basic binary switch that turns on or off as the transistor gate voltage crosses some threshold. Carver Mead first noted that CMOS transistor circuits operating below this threshold in current mode have strikingly similar sigmoidal current– voltage relationships as do neuronal ion channels and consume little power; hence they are ideal analogs of neuronal function (Mead, 1989). This unique device physics led to the advent of “neuromorphic” silicon neurons (SiNs) which allow neuronal spiking dynamics to be directly emulated on analog VLSI chips without the need for digital software simulation (Mahowald and Douglas, 1991). In the inaugural issue of this Journal, Indiveri et al. (2011) review the current state of the art in CMOS-based neuromorphic neuron circuit designs that have evolved over the past two decades. The comprehensive appraisal delineates and compares the latest SiN design techniques as applied to varying types of spiking neuron models ranging from realistic conductancebased Hodgkin–Huxley models to simple yet versatile integrate-and-fire models. The timely and much needed compendium is a tour de force that will certainly provide a valuable guidepost for future SiN designs and applications. <s> BIB003
To mimic the operation of neural computing systems, neuromorphic engineering (NE) was introduced by Mead in the late 1980s  as the research field that uses electronic neural networks whose architectures and operations are based on those of biological nervous systems BIB002 . Mead's initial contribution to the evolution of NE can be distinguished in two parts. First, he observed that despite the advantages of digital computers in terms of precision and noise-free computation, the principles of the physics of neural computation are analog, rather than digital. For example, to compensate for the lack of parallelism, which is a key feature of the brain, computers have to run instructions faster, albeit at the cost of energy. Therefore, Mead was the first in the NE area to exploit the analog properties of transistors, rather than simply operating them as on-off switches BIB002 . His second observation regarding the common physical characteristics between protein channel in neurons and analog neuromorphic circuits resulted in the exploitation of the low power that transistors consume when operating below their threshold voltage. Specifically, he noticed that neuronal ion channels have a sigmoid Editor's notes: This Tutorial describes the building blocks of neuromorphic VLSI systems and the way they are engineered. From learning mechanisms through the gap between reactive and cognitive systems, all major aspects are covered. -Jörg Henkel, Karlsruhe, Institute of Technology input-output characteristic similar to the one that output current and input voltage have in complementary metal-oxide-semiconductor (CMOS) transistors operating in subthreshold BIB003 . The ultimate goal of NE is to demonstrate cognitive systems using hardware neural processing architectures integrated with physical bodies, e.g., humanoid robots BIB002 . Therefore, real-time response is a fundamental requirement. However, simulating large networks of neurobiological systems with digital computers proves to be unrealistic in terms of time. For example, the Blue Gene rack, a 2048-processor computer, needs 1 h and 20 min to simulate 1 s of neural activity in a relatively complex scenario entailing eight million neurons and four billion synapses. Similar time limitations are also observed when graphic processing units (GPUs) and field-programmable gate arrays (FPGAs) are used for simulating complex networks. These observations resulted in the advent of analog VLSI implementations of silicon neurons (SiNs) which lie between biological neurons and digital computers, in terms of area and power, as shown in Figure 1 BIB003 , and which can emulate brain computation mechanisms in real time. To date, neuromorphic silicon architectures have been used for implementing silicon retinas  and cochleas BIB001 , SiNs and synapses, and networks of SiNs and synapses. In this survey paper, we focus on presenting the general concepts of NE VLSI implementations and analyzing their building blocks. To this end, we first describe the basic structures of hardware models of spiking neurons, ranging from conductance-based and integrate-and-fire (I&F) structures to a mixture thereof. Next, we address plastic synapses and long-term weight storage mechanisms, as well as spike-based learning algorithms. Then, we discuss the asynchronous address-event-representation (AER) protocol, which is used to transmit spikes across chip boundaries and which contains both analog and digital components for local computation (on-chip) and long distance communication (offchip), respectively. Combination of the above neuromorphic components results into single-chip or multichip spiking neural networks (SNNs), such as recurrent and winner take all (WTA) architectures. These neural networks have been proposed for performing a number of tasks, such as pattern recognition, working memory, and decision making. Finally, we discuss challenges on bridging the gap between reactive and cognitive systems, we present existing frontiers in NE, and we investigate potential solutions to emerging issues.