IMPLEMENTATION METHOD ON MEDICAL IMAGE COMPRESSION SYSTEM: A REVIEW <s> Figure 10 <s> Motion estimation is a very computational demanding operation during video compression process in standards such as MPEG4, thus special hardware architectures are required to achieve real-time compression performance. The present work focuses on the development of a reconfigurable systolic-based architecture implementing the Full Search Block Matching Algorithm (FBMA) which is highly computing-intensive and requires a large bandwidth to obtain real-time performance. The architecture comprises a smart memory scheme to reduce the number of accesses to data memory and Router elements to handle data movement among different structures inside the same architecture, adding the possibility of chaining interconnection of multiple processing blocks. Every Processing Element (PE) in the array includes a double ALU in order to search multiple macroblocks in parallel. The functionality has been extended to support operations involved in some other low-level image algorithms. Results show that a peak performance in the order of 9 GOPS can be achieved. <s> BIB001 </s> IMPLEMENTATION METHOD ON MEDICAL IMAGE COMPRESSION SYSTEM: A REVIEW <s> Figure 10 <s> Matrix computations are very important in image processing applications. Processing large images or matrices is computationally intensive, power hungry and requires a large amount of memory. This paper discusses the hardware implementation of a factorisation based approach for Haar wavelet transform (HWT) on reconfigurable hardware using distributed arithmetic (DA) principles. The proposed architectures can be integrated into a multiresolution based system for automatic detection and segmentation of tumour in medical images. Two factorisation methodologies are presented and their impact on FPGA implementation is addressed in terms of different resources required and performance achieved. <s> BIB002 </s> IMPLEMENTATION METHOD ON MEDICAL IMAGE COMPRESSION SYSTEM: A REVIEW <s> Figure 10 <s> Medical image compression is necessary to store the huge database in Medical Centres and medical data transfer for the purpose of diagnosis. This paper attempts to improve the higher peak signal to noise ratio (PSNR) by using the system error compensation (SEC) method. The SEC design is based on quantization and curvelet transform (CT) decomposes the system error (E) to six scales. Only the scale 1 and scale 6 are constructed to error compensation. The simulation results are shown that the proposed method can improve 40.48 %, 9.69 % both in terms of bit rate and PSNR when compared to the conventional method. <s> BIB003
The proposed architecture BIB001 Referring to the current research trends regarding hardware implementation BIB003 - BIB001 , most of the researcher's tendency to explore in term of throughput (speed) and PSNR, instead of power consumption and maximum frequency. These because of researchers concentrate on the quality of images and the possible time to process an architecture on the selected hardware. Ultimately, SA and DA architectures frequently used for the hardware implementation. More importantly, DA was the efficiency of mechanization, which is in contrast with the multiply-accumulate (MAC) structure. Important to realize a characteristic of FPGAs, when dealing with large transformation it's become slower as a nature of bit serial hardware. In order increased its performance, some modification such as portioning and bit pairing were applied BIB002 . Table 1 shows the summary of DA and SA implementation. 