Hardware Decoders for Polar Codes: An Overview <s> A. Exact LLR-Based SCL Decoding <s> We describe a successive-cancellation list decoder for polar codes, which is a generalization of the classic successive-cancellation decoder of Arikan. In the proposed list decoder, up to L decoding paths are considered concurrently at each decoding stage. Simulation results show that the resulting performance is very close to that of a maximum-likelihood decoder, even for moderate values of L. Thus it appears that the proposed list decoder bridges the gap between successive-cancellation and maximum-likelihood decoding of polar codes. The specific list-decoding algorithm that achieves this performance doubles the number of decoding paths at each decoding step, and then uses a pruning procedure to discard all but the L “best” paths. In order to implement this algorithm, we introduce a natural pruning criterion that can be easily evaluated. Nevertheless, straightforward implementation still requires O(L · n2) time, which is in stark contrast with the O(n log n) complexity of the original successive-cancellation decoder. We utilize the structure of polar codes to overcome this problem. Specifically, we devise an efficient, numerically stable, implementation taking only O(L · n log n) time and O(L · n) space. <s> BIB001 </s> Hardware Decoders for Polar Codes: An Overview <s> A. Exact LLR-Based SCL Decoding <s> This brief presents a hardware architecture and algorithmic improvements for list successive cancellation (SC) decoding of polar codes. More specifically, we show how to completely avoid copying of the likelihoods, which is algorithmically the most cumbersome part of list SC decoding. The hardware architecture was synthesized for a blocklength of N = 1024 bits and list sizes L = 2, 4 using a UMC 90 nm VLSI technology. The resulting decoder can achieve a coded throughput of 181 Mb/s at a frequency of 459 MHz. <s> BIB002 </s> Hardware Decoders for Polar Codes: An Overview <s> A. Exact LLR-Based SCL Decoding <s> Long polar codes achieve the capacity of binary-input discrete memoryless channels when decoded with a successive cancelation (SC) algorithm. For polar codes with short or moderate length, the decoding performance of the SC algorithm is inferior, and the cyclic redundancy check (CRC) aided successive cancelation list (SCL) algorithm achieves significantly improved performance. In this paper, we propose an efficient list decoder architecture for the CRC aided SCL algorithm. Three list decoders with list size L = 2, 4 and 8, respectively, are implemented with a 90nm CMOS technology. Compared to list decoders with L = 2 and 4 in the literature, the proposed list decoders achieve 1.42 and 2.84 times, respectively, higher hardware efficiency. The implementation with list size L = 8 demonstrates that our decoder architecture works for large list sizes. <s> BIB003 </s> Hardware Decoders for Polar Codes: An Overview <s> A. Exact LLR-Based SCL Decoding <s> Successive cancellation list (SCL) decoding algorithm is a powerful method that can help polar codes achieve excellent error-correcting performance. However, the current SCL algorithm and decoders are based on likelihood or log-likelihood forms, which render high hardware complexity. In this paper, we propose a log-likelihood-ratio (LLR)-based SCL (LLR-SCL) decoding algorithm, which only needs half the computation and storage complexity than the conventional one. Then, based on the proposed algorithm, we develop low-complexity VLSI architectures for LLR-SCL decoders. Analysis results show that the proposed LLR-SCL decoder achieves 50% reduction in hardware and 98% improvement in hardware efficiency. <s> BIB004 </s> Hardware Decoders for Polar Codes: An Overview <s> A. Exact LLR-Based SCL Decoding <s> We present an LLR-based implementation of the successive cancellation list (SCL) decoder. To this end, we associate each decoding path with a metric which (i) is a monotone function of the path’s likelihood and (ii) can be computed efﬁciently from the channel LLRs. The LLR-based formulation leads to a more efﬁcient hardware implementation of the decoder compared to the known log-likelihood based implementation. Synthesis results for an SCL decoder with block-length of N = 1024 and list sizes of L = 2 and L = 4 conﬁrm that the LLR-based decoder has considerable area and operating frequency advantages in the orders of 50% and 30%, respectively. <s> BIB005
The original description of SCL decoding was made using channel likelihoods BIB001 . While such a high-level description is valid, these likelihoods can become very small during the decoding process, resulting in numerical precision problems and inefficient hardware implementations. The first hardware implementations of SCL decoding used log-likelihoods to partially overcome these problems BIB002 , BIB003 . An equivalent, but much more efficient, description of SCL decoding in terms of LLRs and an LLR-based path metric was presented in BIB005 , BIB004 . LLR-based SCL decoding leads to the most efficient exact 1 hardware implementation of SCL decoding BIB005 .