A Survey on ESD protection design in different RF circuits <s> Figure 3 (a) Proposed ESD protection design A and (b) proposed ESD protection design B. <s> A diode string as an electrostatic discharge (ESD) protection structure for RF ICs is attractive because of its reduced total parasitic capacitance. This letter reports a comprehensive RF characterization of diodes for RF ESD protection, including S-parameters, parasitic capacitance, and resistance. It is found that a two- or three-diode string may be an optimal RF ESD protection solution due to the balanced overall performance, including ESD protection level, total size, and ESD-induced parasitic effects, etc. An optimized two-diode string for 5 kV ESD protection features a 108.5 fF parasitic capacitance at 2.4 GHz, and is 3680 /spl mu/m/sup 2/ in size. The design was implemented in a commercial 0.35-/spl mu/m BiCMOS technology. <s> BIB001 </s> A Survey on ESD protection design in different RF circuits <s> Figure 3 (a) Proposed ESD protection design A and (b) proposed ESD protection design B. <s> Grounded-gate NMOS (GGNMOS) plays a more important role in electrostatic discharge (ESD) protection because of its simple structure and low trigger voltage. Various GGNMOS based on 90nm, 65nm and 40nm CMOS process are compared to investigate its ESD characteristic changes with process advancing. Results show that the key parameters, including channel width and length, have great influence on its ESD metrics. <s> BIB002 </s> A Survey on ESD protection design in different RF circuits <s> Figure 3 (a) Proposed ESD protection design A and (b) proposed ESD protection design B. <s> On-chip electrostatic discharge (ESD) protection device with large dimension can sustain high-ESD current, but the parasitic capacitance of the ESD protection device will increase the difficulty of impedance matching and degrade the bandwidth for broadband radio frequency (RF) applications. The traditional distributed ESD protection circuit can achieve good impedance matching, but it has a worse ESD robustness because of larger resistance caused by the input inductor. In this paper, a new distributed ESD protection structure with the stacked diodes with embedded silicon-controlled rectifier is proposed to attain good ESD robustness without degrading the RF performance. The proposed ESD protection circuit has been successfully verified in a 40-nm, 2.5-V CMOS process to sustain a human-metal model of 5 kV. The proposed ESD protection circuit is suitable to protect the broadband RF circuits in advanced nanoscale CMOS technology. <s> BIB003
To reduce the inductance used in LN, another additional capacitor (CS) can be added to attach in parallel with ESD protection diode. In other words, the parasitic capacitance of ESD protection diodes (C Diodes) is increased by adding the parallel capacitor (CS). It is better to add the supplement capacitor rather than rising the diode size, because the additional capacitor provides the simply capacitance, while increasing diode size lowers the parasitic resistance, which produces the lower parasitic impedance and higher insertion loss. In ESD series -connected diode strings and protection diodes are used. As diodes are increased more and more the total extra noise figure of the diode string ESD protection is increased BIB001 . GGNMOS has low set off voltage and straightforward structure, therefore GGNMOS and GGNMOS triggered ESD protection devices are broadly used in ESD guard field. The impact of W on trigger voltage and holding voltage is mainly considered as well as the impact of L on holding voltage when designing GGNMOS under 40nm process BIB002 . Examination on various ESD protection strategies dedicated to 3.3V RF applications (2GHz) in a 0.18mm CMOS process by C. Richier, compares different ESD protection devices and shows that a appropriate ESD performance target for RF applications (200fF max, 2kV HBM) can be reached with a diode network method. The optimization of the diodes is then a key point. A compromise has created between the ESD performance, the voltage drop during ESD and the parasitic capacitance. Poly as well as shallow trench isolation (STI) bounded diodes have been studied and it appears clearly that a solution based on poly bounded diodes is the best choice ( Fig. 4) . Different ESD protection strategies are offered and evaluated in terms of ESD performance but also in terms of parasitic capacitance. Poly and STI bounded diodes have been examined and poly diodes were found to have the best trade-off for the safety of RF applications (Fig. 5 ) [12] . Chen BIB003 proposed a new distributed ESD protection structure with the stacked diodes with embedded silicon-controlled rectifier to achieve good ESD robustness without degrading the RF performance. The proposed ESD protection circuit was confirmed in a 40nm, 2.5-V CMOS process to sustain a humanmetal model of 5 kV (Fig. 6 ). The proposed ESD protection circuit is suitable to guard the broad band RF circuits in superior nano scale CMOS technology. This newly proposed protection circuit has achieved lower turn-ON resistance, good ESD robustness, and required RF performance.