Performances of OpenFlow-Based Software- Defined Networks: An overview <s> C. Hardware-Based Enhancements <s> OpenFlow switching enables flexible management of enterprise network switches and experiments on regular network traffic. We present in this paper a complementary design to OpenFlow's existing reference designs. We apply network processor based acceleration cards to perform OpenFlow switching. We describe the design options and report our experiment results that show a 20% reduction on packet delay and the comparable packet forwarding throughput compared to conventional designs. <s> BIB001 </s> Performances of OpenFlow-Based Software- Defined Networks: An overview <s> C. Hardware-Based Enhancements <s> Commodity switches are becoming increasingly important as they are the basic building blocks for the enterprise and data center networks. With the availability of all-in-one switching ASICs, these switches almost universally adopt single switching ASIC design. However, such design also brings two major limitations, i.e, limited forwarding table for flow-based forwarding scheme such as Openflow and shallow buffer for bursty traffic pattern. In this paper, we propose to use CPU in the switches to handle not only control plane but also data plane traffic. We show that this design can provide large forwarding table for flow-based forwarding scheme and deep packet buffer for bursty traffic. We build such a prototype switch on ServerSwitch platform. In our evaluation, we show that our prototype can achieve over 90% traffic offloading ratio, absorb large traffic bursts without a single packet drop, and can be easily programmed to detect and defend low-rate burst attacks. <s> BIB002 </s> Performances of OpenFlow-Based Software- Defined Networks: An overview <s> C. Hardware-Based Enhancements <s> The data plane is in a continuous state of flux. Every few months, researchers publish the design of a new high-performance queueing or scheduling scheme that runs inside the network fabric. Many such schemes have been queen for a day, only to be surpassed soon after as methods --- or evaluation metrics --- evolve. The lesson, in our view: there will never be a conclusive victor to govern queue management and scheduling inside network hardware. We provide quantitative evidence by demonstrating bidirectional cyclic preferences among three popular contemporary AQM and scheduling configurations. We argue that the way forward requires carefully extending Software-Defined Networking to control the fast-path scheduling and queueing behavior of a switch. To this end, we propose adding a small FPGA to switches. We have synthesized, placed, and routed hardware implementations of CoDel and RED. These schemes require only a few thousand FPGA "slices" to run at 10 Gbps or more --- a minuscule fraction of current low-end FPGAs --- demonstrating the feasibility and economy of our approach. <s> BIB003
An OpenFlow switch makes generally two important decisions: queue-management and scheduling operations. The first concerns how long can the queue grow? and the second consists on deciding which packet should be sent next when an outgoing link is free. An interesting work in BIB003 treats these two questions. The authors propose to extend SDN's flexibility to cover queuing and scheduling decisions made in the data plane, this by adding a small FPGA to the fast path of a hardware switch, with simple interface to the switch's packet queues. This solution allows queuing and scheduling to be reconfigured by the network operator, and it adjusts queuing and scheduling behavior with application objectives. As a result they achieve both high performance and flexibility to the data plane. At least two studies have proposed additional ways to take profit of a CPU being connected to the switch. Authors in BIB002 attempt to increase the size of both forwarding table and packet buffer, by proposing some modifications to the current OpenFlow switch design. The main idea focuses on combining ASIC and CPU processing. In their solution, the switch is not a dummy component; it swaps the flows, monitors the queues and it decides the traffic redirection. They propose to use CPU as a traffic co-processor in switches to address the limited size of forwarding table and packet buffer. This makes the network devices more programmable and offer more network functions. A prototype is developed and a 3.9Gb/s throughput is achieved. In the same direction, Luo et al in BIB001 implement network processor based acceleration cards to perform OpenFlow switching. They show a 20 percent reduction on packet delay compared to conventional designs. From the previous studies, we see that various parameters may influence the performance of an OpenFlow-enabled switch, including the processing time in the modern all-in-one ASIC, lookup table delay, queue-management and scheduling operations. The proposed enhancements lead to better performances of OpenFlow switches, and they encourage the enterprises to use them in production networks. In the next section, we present performance studies of Openflow controllers.