Multi-Channel Neural Recording Implants: A Review <s> Analog to Digital Converters <s> Small area and power efficient analog-to-digital converters are needed to accommodate implantable multichannel sensors. This paper concerns the design and implementation of an ultra-low-power 8-bit successive approximation analog-to-digital converter (ADC). A new topology is proposed which improves the conventional architectures by replacing the successive approximation register and the digital-to-analog converter by a switchedopamp switched-capacitor circuit which dissipates very low power. The sampling frequency of the proposed ADC is 30 kSps and within an input range of 600 mV. Implemented in a 0.18-?m CMOS process with a 1.8 V voltage supply, the ADC achieves a power dissipation of 7.4 ?W and occupies an area of 0.04 mm2. <s> BIB001 </s> Multi-Channel Neural Recording Implants: A Review <s> Analog to Digital Converters <s> This paper describes a neurostimulation IC for use in advanced closed-loop neurostimulation applications, such as deep brain stimulation (DBS) for treatment and research of neurological disorders including Parkinson's disease. This system senses and filters neural activity with eight pre-amplifiers, a 200 kS/s 8-bit log ADC and digital filters and incorporates 64 programmable current-stimulation channels. The entire device, implemented in 0.18 μm CMOS, occupies 2.7 mm2 and consumes 89 μW in normal operation mode and 271 μW in configuration mode from a 1.8 V supply. <s> BIB002 </s> Multi-Channel Neural Recording Implants: A Review <s> Analog to Digital Converters <s> The 0.35µm CMOS active probe and stimulator enables responsive neural stimulation of the brain cortex. It monitors extracellular neural activity on 256 sites in the brain and generates 64 event-triggered current-mode neural stimuli. Each 0.035mm2 fully differential neural recording channel includes a 8-bit single slope ADC. Each 0.02mm2 neural stimulation channel reuses an OTA for both current sampling and current sourcing. The 13.5mW prototype is flip-chip bonded with a 64-shank Utah electrode array and validated in spatial recording of epileptic neural activity in the mouse hippocampus. <s> BIB003 </s> Multi-Channel Neural Recording Implants: A Review <s> Analog to Digital Converters <s> A system-on-chip (SoC) neural recording interface with 64 channels, 64 16-tap programmable mixed-signal FIR filters and a fully integrated 915 MHz OOK/FSK PLL-based wireless transmitter is presented. Each recording channel has a fully differential amplifier with 54 dB gain and utilizes a tunable low-distortion subthreshold MOS-resistor to reject DC offsets with an input-referred noise of 6.5 μV and a CMRR of 75 dB. Each channel contains a modified 8-bit SAR ADC with an ENOB of 7.8-bits and can provide analog-digital multiplication by modifying the the sampling phase of the ADC. It is used in conjunction with 12-bit digital adders and registers to implement 64 programmable transposed FIR filters. The 915 MHz FSK/OOK transmitter offers data rates up to 1.5 Mbps and a maximum output power of 0 dBm. The 4×3 mm2 chip fabricated in a 0.13 μm CMOS process dissipates 5.03 mW from a 1.2 V supply. Experimental measurements characterize the electrical performance of the wireless SoC. In vivo measurement results from freely moving rats are also presented. <s> BIB004 </s> Multi-Channel Neural Recording Implants: A Review <s> Analog to Digital Converters <s> This paper describes a low-power configurable neural recording system capable of capturing and digitizing both neural action-potential (AP) and fast-ripple (FR) signals. It demonstrates the functionality of epileptic seizure detection through FR recording. This system features a fixed-gain, variable-bandwidth (BW) front-end circuit and a sigma-delta ADC with scalable bandwidth and power consumption. The ADC employs a 2nd-order single-bit sigma-delta modulator (SDM) followed by a low-power decimation filter. Direct impulse-response implementation of a sinc3 filter and 8-cycle data pipelining in an IIR filter are proposed for the decimation filter design to improve the power and area efficiency. In measurements, the front end exhibits 39.6-dB DC gain, 0.8 Hz to 5.2 kHz of BW, 5.86-μVrms input-referred noise, and 2.4-μW power consumption in AP mode, while showing 38.5-dB DC gain, 250 to 486 Hz of BW, 2.48-μVrms noise, and 4.5- μW power consumption in FR mode. The noise efficiency factor (NEF) is 2.93 and 7.6 for the AP and FR modes, respectively. At 77-dB dynamic range (DR), the ADC has a peak SNR and SNDR of 75.9 dB and 67 dB, respectively, while consuming 2.75-mW power in AP mode. It achieves 78-dB DR, 76.2-dB peak SNR, 73.2-dB peak SNDR, and 588-μW power consumption in FR mode. Both analog and digital power supply voltages are 2.8 V. The chip is fabricated in a standard 0.6-μm CMOS process. The die size is 11.25 mm2. <s> BIB005 </s> Multi-Channel Neural Recording Implants: A Review <s> Analog to Digital Converters <s> We report the design and implementation of an Analog-to-Information Converter (AIC) based on Compressed Sensing (CS). The system is realized in a CMOS $180~{\rm nm}$ technology and targets the acquisition of bio-signals with Nyquist frequency up to $100~{\rm kHz}$ . To maximize performance and reduce hardware complexity, we co-design hardware together with acquisition and reconstruction algorithms. The resulting AIC outperforms previously proposed solutions mainly thanks to two key features. First, we adopt a novel method to deal with saturations in the computation of CS measurements. This allows no loss in performance even when 60% of measurements saturate. Second, the system is able to adapt itself to the energy distribution of the input by exploiting the so-called rakeness to maximize the amount of information contained in the measurements. <s> BIB006 </s> Multi-Channel Neural Recording Implants: A Review <s> Analog to Digital Converters <s> We review integrated circuits for low-frequency noise and offset rejection as a motivation for the presented digitally-assisted neural amplifier design methodology. Conventional AC-coupled neural amplifiers inherently reject input DC offset but have key limitations in area, linearity, DC drift, and spectral accuracy. Their chopper stabilization reduces low-frequency intrinsic noise at the cost of degraded area, input impedance and design complexity. DC-coupled implementations with digital high-pass filtering yield improved area, linearity, drift, and spectral accuracy and are inherently suitable for simple chopper stabilization. As a design example, a 56-channel 0.13 μm CMOS intracranial EEG interface is presented. DC offset of up to ±50 mV is rejected by a digital low-pass filter and a 16-bit delta-sigma DAC feeding back into the folding node of a folded-cascode LNA with CMRR of 65 dB. A bank of seven column-parallel fully differential SAR ADCs with ENOB of 6.6 are freely moving ratsshared among 56 channels resulting in 0.018 mm ::: 2 ::: effective channel area. Compensation-free direct input chopping yields integrated input-referred noise of 4.2 μV ::: rms ::: over the bandwidth of 1 Hz to 1 kHz. The 8.7 mm ::: 2 ::: chip dissipating 1.07 mW has been validated in vivo in online intracranial EEG monitoring in freely moving rats. <s> BIB007 </s> Multi-Channel Neural Recording Implants: A Review <s> Analog to Digital Converters <s> A multi-channel ADC structure is presented, which is dedicated to the digitization of multi-channel ECoG signals. The ADC is designed to decompose the signals on all the channels into one shared common baseline component and channel-specific differential components containing channel activities. The baseline component is digitized using a low-resolution ADC (BL-ADC), and the differential channel activities are converted to digital using a time-multiplexed sub-ADC. Designed to benefit from the spatial redundancy that exists in the common baseline signal, the proposed structure exhibits low power consumption and small silicon area. Another advantage of the proposed ADC scheme is the reduction achieved in the extent of the output digital data. This is because of sharing the common baseline data among all the channels. Fully-integrated version of the 8-channel ADC was designed in a 0.18-µm CMOS process, occupying about 0.015 mm2 of silicon area. Operating at a supply voltage of 1.8 V, sampling frequency of 1 kS/s for BL-ADC and 8 kS/s for the time-shared sub-ADC, the entire circuit dissipates 0.82µW. <s> BIB008 </s> Multi-Channel Neural Recording Implants: A Review <s> Analog to Digital Converters <s> A dual-mode, reconfigurable ADC for neural recording application is presented in this paper. In order to quantize the extracellular action potential (EAP or spike) of neural signal, the proposed ADC works as a 10 bits successive approximation register (SAR) ADC in the normal mode to process all the raw data. In other side, to reduce dynamic power, the ADC is designed to configure as a single-slope (SS) ADC in compression mode, and only essential parts of spike waveforms are processed. Fabricated in a 0.18 µm CMOS process, the proposed ADC consumes 2.83 μW in SAR mode and 24.71 μW in SS mode at supply voltage of 1.8 V, respectively. In SAR mode, the achieved SNDR and SFDR are 60.5 dB and 75.5 dB when a Nyquist frequency input signal is received @ the sampling rate of 25 kS/s. While in SS mode, the achieved SNDR and SFDR are 57.7 dB and 60.8 dB. <s> BIB009
The amplified neural signals are converted to digital by an ADC as shown in Figure 1 , before transmitting it out of the body. This is because the digital data is very tolerant of noise and other interferers, compared to analog signals. As the neural signals have very low bandwidth and require low power consumption for implant applications, successive approximation architecture analog to digital converters (SAR ADCs) are one of the best options. This ADC utilizes digital to analog converter (DAC) and successive approximation register (SAR) blocks. Most of the neural recording systems utilize an 8 to 10 bit resolution SAR ADC BIB008 , however in  , the resolution of the ADC is adaptively configured by the activity of the input neural signal, to save the power and compress the data. Figure 12 shows a SAR ADC which uses charge redistribution between the capacitors. Also, two sub DACs are utilized to decrease the total amount of capacitance and consequently reduces the total area BIB007 BIB004 BIB006 . This ADC is suitable for neural recording architectures shown in Figure 1a ,c which use one or several ADCs for all of the channels. Due to their large area and high-power consumption, this ADC is not suitable for the architecture shown in Figure 1b where each channel uses one ADC. For this purpose, the authors in BIB001 propose an improved SAR ADC shown in Figure 13a . The output bits of this ADC are extracted in serial. In addition, this structure exploits binary search algorithm as shown in Figure 13b . Although, in general, SAR ADC is a common architecture used in neural recording implants, the use of other ADC architecture is sometimes presented in the literature. For example, a logarithmic pipeline ADC with 8 bit resolution is used in BIB002 . The logarithmic encoding is used to represent the high dynamic range with a short word length. Another neural recording system with 256 channels is shown in BIB003 . In order to reduce the area and power consumption, an 8 bit resolution single slope ADC is used for each channel. The ramp generator and counter are shared between all channels in this architecture. The authors in BIB009 introduce a 10-bit resolution dual mode SAR and single-slope ADC for neural recording application. In the normal mode, the ADC works as a SAR ADC to quantize the extracellular action potential. In the compression mode, to reduce the dynamic power, the ADC is configured to single-slope and it processes just essential parts of spike waveforms. Sigma-Delta modulators are also utilized in neural recording applications due to the low-frequency bandwidth of neural signals  BIB005 . Sigma-Delta modulators operate based on oversampling data conversion. Therefore, although this data converters can be low power, they can increase the power consumption in the subsequent circuits especially in the wireless transmitter due to increasing the output data rate of Σ∆ modulators much higher than Nyquist-rate ADCs. However, as mentioned earlier, the charge redistributed SAR ADC is the best data converter option for multi-channel neural recording implants.