By Adam Taylor

So far on our Zynq development Journey of Discovery, we have yet to look at the Zynq SoC’s Gigabit Ethernet capabilites, which allow your application to be network enabled. Gigabit Ethernet provides very fast, flexible communications but Ethernet communications are a little more complicated than a simple RS-232 link. It’s nothing to be scared of, once you understand the topic and I think you will understand after the next few blog posts in this series.

There are two Gigabit Ethernet Controllers in the Zynq SoC’s PS (Processor System). Each of these controllers can be configured and used independently. The Gigabit Ethernet Controller, once correctly configured, implements a MAC—Media Access Controller—which forms part of the data link layer in the 7-layer OSI model. A MAC operates as a subsection of the data link layer in the OSI model. Over the next few blog posts in this series, we will be looking more at the MAC and then progressing on to TCP/IP and higher protocol levels. Therefore, I think a quick refresher on the OSI model is due.

acThe Open Systems Interconnection (OSI) 7-layer model uses an abstract model to describe how protocols function at different layers in the protocol stack.

Layer One: Physical Layer—describes the physical interconnection. Layer Two: Data Link Layer—describes the means for transferring data over the physical layer (Physical Addressing). Layer Three: Network Layer—describes the means to transfer data between different networks (Logical Addressing). Layer Four: Transport Layer—provides transfer of data between end users. Layer Five: Session Layer—controls the connections between end users. Layer Six: Presentation layer—transforms data presentation between higher level and low-level layers. Layer Seven: Application Layer—interfaces to the final application where the data transferred is used or gathered for another transfer.

It is worth noting at this point that not all levels of the model are required to be present within a particular implementation of the protocol.

The physical layer is implemented with an external PHY device. The Zynq SoC interfaces to a PHY device using one of two approaches depending upon your system design. The first choice is to connect the PHY to the Zynq SoC’s MIO using an RGMII interface. Alternatively, you can connect the Zynq SoC to the Phy using the EMIO via a GMII/MII interface. On the MicroZed board, the PHY is a Marvel Alaska 88E1512 device connected to a combined RJ45/USB connector.

To ensure that a PHY can be used across the maximum number of applications and to ensure design reuse, a standard interface has been developed called the Media Independent Interface which is the “MII” in the names RGMII, GMII, and MII above. “RG” means “Reduced Gigabit” while “G” is simply “Gigabit.” These are adaptations of the MII standard for higher data rates and, in some cases, a reduced number of signal pins.

Having looked at how the Zynq Gigabit Ethernet Controller interfaces with the network and the external world, we will now examine how the Zynq SoC’s internal Ethernet controller interfaces with the PS. A simple register interface provides control and status while high-speed transfers for bidirectional Gigabit data communications requires DMA (Direct Memory Accesses) between a system’s memory and the Ethernet controler.

In the next blog we will look at configuring the MAC with the help of a Xilinx example. We can then go forward to create more network-enabled designs.

Now, you can have convenient, low-cost Kindle access to the first year of Adam Taylor’s MicroZed Chronicles for a mere $7.50. Click here.

Please see the previous entries in this MicroZed Chronicles series by Adam Taylor:

Adam Taylor’s MicroZed Chronicles Part 76: Constraints for Relatively Placed Macros

Adam Taylor’s MicroZed Chronicles, Part 75: Placement Constraints – Pblocks

Adam Taylor’s MicroZed Chronicles, Part 73: Physical Constraints

Adam Taylor’s MicroZed Chronicles, Part 73: Working with other Zynq-Based Boards

Adam Taylor’s MicroZed Chronicles, Part 72: Multi-cycle Constraints

Adam Taylor’s MicroZed Chronicles, Part 70: Constraints—Clock Relationships and Avoiding Metastability

Adam Taylor’s MicroZed Chronicles, Part 70: Constraints—Introduction to timing and defining a clock

Adam Taylor’s MicroZed Chronicles Part 69: Zynq SoC Constraints Overview

Adam Taylor’s MicroZed Chronicles Part 68: AXI DMA Part 3, the Software

Adam Taylor’s MicroZed Chronicles Part 67: AXI DMA II

Adam Taylor’s MicroZed Chronicles Part 66: AXI DMA

Adam Taylor’s MicroZed Chronicles Part 65: Profiling Zynq Applications II

Adam Taylor’s MicroZed Chronicles Part 64: Profiling Zynq Applications

Adam Taylor’s MicroZed Chronicles Part 63: Debugging Zynq Applications

Adam Taylor’s MicroZed Chronicles Part 62: Answers to a question on the Zynq XADC

Adam Taylor’s MicroZed Chronicles Part 61: PicoBlaze Part Six

Adam Taylor’s MicroZed Chronicles Part 60: The Zynq and the PicoBlaze Part 5—controlling a CCD

Adam Taylor’s MicroZed Chronicles Part 59: The Zynq and the PicoBlaze Part 4

Adam Taylor’s MicroZed Chronicles Part 58: The Zynq and the PicoBlaze Part 3

Adam Taylor’s MicroZed Chronicles Part 57: The Zynq and the PicoBlaze Part Two

Adam Taylor’s MicroZed Chronicles Part 56: The Zynq and the PicoBlaze

Adam Taylor’s MicroZed Chronicles Part 55: Linux on the Zynq SoC

Adam Taylor’s MicroZed Chronicles Part 54: Peta Linux SDK for the Zynq SoC

Adam Taylor’s MicroZed Chronicles Part 53: Linux and SMP

Adam Taylor’s MicroZed Chronicles Part 52: One year and 151,000 views later. Big, Big Bonus PDF!

Adam Taylor’s MicroZed Chronicles Part 51: Interrupts and AMP

Adam Taylor’s MicroZed Chronicles Part 50: AMP and the Zynq SoC’s OCM (On-Chip Memory)

Adam Taylor’s MicroZed Chronicles Part 49: Using the Zynq SoC’s On-Chip Memory for AMP Communications

Adam Taylor’s MicroZed Chronicles Part 48: Bare-Metal AMP (Asymmetric Multiprocessing)

Adam Taylor’s MicroZed Chronicles Part 47: AMP—Asymmetric Multiprocessing on the Zynq SoC

Adam Taylor’s MicroZed Chronicles Part 46: Using both of the Zynq SoC’s ARM Cortex-A9 Cores

Adam Taylor’s MicroZed Chronicles Part 44: MicroZed Operating Systems—FreeRTOS

Adam Taylor’s MicroZed Chronicles Part 43: XADC Alarms and Interrupts

Adam Taylor’s MicroZed Chronicles MicroZed Part 42: MicroZed Operating Systems Part 4

Adam Taylor’s MicroZed Chronicles MicroZed Part 41: MicroZed Operating Systems Part 3

Adam Taylor’s MicroZed Chronicles MicroZed Part 40: MicroZed Operating Systems Part Two

Adam Taylor’s MicroZed Chronicles MicroZed Part 39: MicroZed Operating Systems Part One

Adam Taylor’s MicroZed Chronicles MicroZed Part 38 – Answering a question on Interrupts

Adam Taylor’s MicroZed Chronicles Part 37: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 8

Adam Taylor’s MicroZed Chronicles Part 36: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 7

Adam Taylor’s MicroZed Chronicles Part 35: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 6

Adam Taylor’s MicroZed Chronicles Part 34: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 5

Adam Taylor’s MicroZed Chronicles Part 33: Driving Adafruit RGB NeoPixel LED arrays with the Zynq SoC

Adam Taylor’s MicroZed Chronicles Part 32: Driving Adafruit RGB NeoPixel LED arrays

Adam Taylor’s MicroZed Chronicles Part 31: Systems of Modules, Driving RGB NeoPixel LED arrays

Adam Taylor’s MicroZed Chronicles Part 30: The MicroZed I/O Carrier Card

Zynq DMA Part Two – Adam Taylor’s MicroZed Chronicles Part 29

The Zynq PS/PL, Part Eight: Zynq DMA – Adam Taylor’s MicroZed Chronicles Part 28

The Zynq PS/PL, Part Seven: Adam Taylor’s MicroZed Chronicles Part 27

The Zynq PS/PL, Part Six: Adam Taylor’s MicroZed Chronicles Part 26

The Zynq PS/PL, Part Five: Adam Taylor’s MicroZed Chronicles Part 25

The Zynq PS/PL, Part Four: Adam Taylor’s MicroZed Chronicles Part 24

The Zynq PS/PL, Part Three: Adam Taylor’s MicroZed Chronicles Part 23

The Zynq PS/PL, Part Two: Adam Taylor’s MicroZed Chronicles Part 22

The Zynq PS/PL, Part One: Adam Taylor’s MicroZed Chronicles Part 21

Introduction to the Zynq Triple Timer Counter Part Four: Adam Taylor’s MicroZed Chronicles Part 20

Introduction to the Zynq Triple Timer Counter Part Three: Adam Taylor’s MicroZed Chronicles Part 19

Introduction to the Zynq Triple Timer Counter Part Two: Adam Taylor’s MicroZed Chronicles Part 18

Introduction to the Zynq Triple Timer Counter Part One: Adam Taylor’s MicroZed Chronicles Part 17

The Zynq SoC’s Private Watchdog: Adam Taylor’s MicroZed Chronicles Part 16

Implementing the Zynq SoC’s Private Timer: Adam Taylor’s MicroZed Chronicles Part 15

MicroZed Timers, Clocks and Watchdogs: Adam Taylor’s MicroZed Chronicles Part 14

More About MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 13

MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 12

Using the MicroZed Button for Input: Adam Taylor’s MicroZed Chronicles Part 11

Driving the Zynq SoC's GPIO: Adam Taylor’s MicroZed Chronicles Part 10

Meet the Zynq MIO: Adam Taylor’s MicroZed Chronicles Part 9

MicroZed XADC Software: Adam Taylor’s MicroZed Chronicles Part 8

Getting the XADC Running on the MicroZed: Adam Taylor’s MicroZed Chronicles Part 7

A Boot Loader for MicroZed. Adam Taylor’s MicroZed Chronicles, Part 6

Figuring out the MicroZed Boot Loader – Adam Taylor’s MicroZed Chronicles, Part 5

Running your programs on the MicroZed – Adam Taylor’s MicroZed Chronicles, Part 4

Zynq and MicroZed say “Hello World”-- Adam Taylor’s MicroZed Chronicles, Part 3

Adam Taylor’s MicroZed Chronicles: Setting the SW Scene

Bringing up the Avnet MicroZed with Vivado