Publications | VLSI CAD LAB Skip to main content VLSI CAD LAB University of California, Santa Barbara Home People Research Publications Contact Publications Search Show only items where Author anyAikyo, TAitken, JAnderson, BBrewer, FChai, DChang, Ya-Ting Chang, Shih-Chieh Chang, Chih-Wei Chang, DChen, L HChen, Fen Chen, BChen, Sao-Jie Chen, ZChen, Kuang-Chien Cheng, Kwang-Ting Cheng, David ICheng, Chung-Kuan Divecha, RDutta, RFan, Hongbing Feng, K DFunabiki, NGatlin, DGrygiel, SHa, HHellebrand, SHenson, W KHsiao, Ming-Fu Hu, Bo Jiang, Hailin Jiang, Yi-Min Jozwiak, LKane, TKasprowicz, DKinser, EKondratyev, AKontra, RKozhaya, JKrstic, AKuh, E SKumar, MKuo, Yu-Min Kuzmicz, WLee, Bill Lee, Tien-Chien Li, Di-an Li, XLi, Jeong-Tyng Lin, Chih-Chang Lin, Yi-Wei Lin, Shen Liu, Qinghua Long, S ILuba, TMacchiarulo, Luca Maire, FMakedon, Fillia Malvi, RMaly, Wojciech Maly, Wojciech Marek-Sadowska, Malgorzata Marek-Sadowska, MMatheron, CMehta, Vishal Merek-Sadowska, Malgorzata Mittl, SMocuta, DModi, Nilesh Mukherjee, Arindam Nandakumar, V SNassif, S RNewmark, DNowicka, MParthasarathy, GParthasarathy, Ganapathy Pedram, MPerkowski, MPfitzner, APikus, Fedor GQiu, Xiang Rajski, Janusz Ran, Yajun Rieger, Michael LSarrafzadeh, MShen, NShinosky, MShu, Shih-Min Singh, PSingh, Vivek KSingh, Amit Singh, NSu, Yu-Shih Suaris, PSudhakar, RSwift, ATarng, Tom Tsan-Kuo Todri, Aida Tompson, RTorres, Andres Tsai, Kun-Han Tsai, Chien-Chung Tsai, Chung-Kuan Tseng, Kenneth Tsukiyama, Shuji Van Ginneken, L P P PVittal, Ashok Wang, Deborah CWang, Da-Chung Wang, Kai-Ping Wang, Zhi Wang, Yun Wang, Yanfeng Wang, Kai Wang, Zhiyuan Watanabe, Yosinori Weng, Shih-Hung Wong, C KWoo, Nam-Sung Wu, Yu-Liang Wuu, Jen-Yi Xiao, Tong Yang, Sherry Yeh, Chao-Yang Zeng, Yue Zhan, Yaping Zhang, Jin S Type anyConference PaperJournal Article Term any Year any2012201120102009200820072006200520042003200220012000199919981997199619951994199319921991199019891987198519841983 Keyword any0.25 micron0.5 micron0.5 mum130 nm180 nm2-D FPGAs2-layer channel-routing problem2.5 V2D array2D FPGA2D FPGA routing2D interval packing problem3-D geometry transistor3D architectural blocks3D design space exploration3D hybrid architecture3D integration3D junctionless VeSFET3D multicore architectures3D multicore processor3D network-on-chip architecture500 MHz625 MHz65 nm715 MHz90 nmabutmentaccuracyActel 2active areaadd-a-wire-and-remove-a-wire operationaddersadditionadvanced VLSI circuitsaggressoraggressor alignmentalgebraic factorizationalgorithmalgorithmsalternative functionalternative wirealternative wire identificationalternative wiresanalysis toolanalytic placementAND gatesAND/XOR canonical networksAND/XOR representationsannealing refinement stageapplication specific integrated circuitsapplication-specified integrated circuitsapproximation accuracyarbitrary fixed switch box topologyarchitectural level routingarchitecture resourcesarea improvementarea optimizationarea overheadarea-optimization heuristicarithmetic functionsarray sizearray type architecturesarray-type FPGAASICASIC designASICsassymetrical bidirectional currentsATPGATPG guided logic optimizationATPG-based logic synthesisautomatic placeautomatic synthesisautomatic test pattern generationautomatic testingautomatic-test-pattern-generated setsback-mappingback-mapping processbasic arithmetic operationsbasic logic blockBDDBDD-based techniquesBDD-type structuresBDDsbin-packing heuristicbinary decision diagrambinary decision diagramsblock-based statistical static timing analysisBoolean algebraBoolean coverBoolean equationsBoolean formulationBoolean functionBoolean function classesBoolean functionsBoolean functions classificationBoolean logicBoolean logic optimizationBoolean matchingBoolean networkBoolean network functional symmetriesBoolean networksboolean optimizationBoolean optimization methodBoolean satisfiabilityboundary scan testingbounding box placersBSIM3v3 modelbuffer areabuffer area minimisationbuffer circuitsbuffer delay changebuffer delay modelbuffer insertionbuffer resizingbuffer widthbuffered clock treesbuilt-in self testbuilt-in-self-testC-SBGT algorithmcache blockCADcandidate wirescanonical formscapacitancecapacitive coupling-induced crosstalk noisecapacitive coupling-induced delaycapacitive couplingscapacitive loadingcapacitively coupled linescapacitor switchingcarrier velocity saturationCD thresholdcell based designcell classcell interconnect layoutscell layout-performance relationshipscell level routingcell librarycell power noise estimationcell-level interconnect patterncellular arrayschannel densitychipchip manufacturabilitychip performancechip performance optimizationcircuit analysis computingcircuit blockscircuit CADcircuit clocking frequencycircuit clusteringcircuit complexitycircuit component delayscircuit delaycircuit delayscircuit depth optimizationcircuit designcircuit design methodologycircuit diagnosiscircuit elementscircuit functional propertycircuit layoutcircuit layout CADcircuit mappability predictioncircuit modelcircuit noisecircuit operationcircuit optimisationcircuit optimizationcircuit parameterscircuit partitioningcircuit performancecircuit performance optimizationcircuit placement algorithmcircuit reliabilitycircuit rewiringcircuit simulationcircuit sizescircuit stabilitycircuit structurescircuit techniquescircuit testabilitycircuit testingcircuit timingcircuit timing informationcircuit timing propertycircuit timing-informationclock buffersclock gatingclock jitterclock mesh distribution networksclock netsclock networkclock network optimizationclock network sizingclock path delayclock period constraintsclock routingclock skewclock skew optimizationclock topologiesclock topologyclockingclocking componentsclocksclosed-form crosstalk delay metricsclosed-form crosstalk noise metricsclosed-form estimation formulasclosed-form formulasclusteringclustering netlistclustering-based placementCMOS circuitsCMOS digital integrated circuitsCMOS gatesCMOS integrated circuitsCMOS logic circuitsCMOS static cellsCMOS technologyCMOS VLSI circuitscoarse meshcofactor pair compatibilitycombinational circuitcombinational circuitscombinational logiccombinational logic functionscombinational logic restructuringcombinational logic restructuring techniquecombinatorial circuitscomplementary metal-oxide-semiconductor-based homogeneous 3D NoCcompletely specified functionscomplex logic transformationscomplexitycomputabilitycomputation-intensive combinational circuitscomputational complexityconductance circuit simulation techniquecongestion minimization techniquesconnection flexibilityconstant bounded mapping ratiosconstant insertionconstant-delay modelconstrained region graphconstraint-driven routingcontrol sequencecontrollabilityconventional clock tree synthesisconvergentcopper contactcorrelation methodscost function optimizationcost functionscost-free scancoupled circuitscoupled clock networkscoupled noisecoupled noise integralcoupled noise reductioncoupling capacitancecoupling directioncoupling effectscoupling jittercoupling locationcover pattern processingcritical netcrossing distribution problemcrosstalkcrosstalk amplitudecrosstalk aware static timing analysiscrosstalk aware two-pin net routercrosstalk computationcrosstalk couplingcrosstalk delay effectscrosstalk effectcrosstalk induced critical paths identificationcrosstalk induced delaycrosstalk minimizationcrosstalk modelingCrosstalk noisecrosstalk noise analysiscrosstalk noise analysis methodcrosstalk noise dependencycrosstalk noise modelingcrosstalk pulse widthcrosstalk reductioncrosstalk violations removalcrosstalk-induced delaycube diagram bundlescurrent densitiescurrent densitycustom designed transistor level macrosdata structuredatapath circuitdatapath circuitsdatapath combinational circuitsdc current densitiesDC voltage-transfer characteristicsdecapdecap areadecap configurationdecap distributiondecap paddingdecayingdecaying effectdecoupling capacitancedecoupling capacitance insertiondecoupling capacitor effectivenessdeep sub-micron technologiesdeep submicron chip designdeep submicron digital circuitsdeep submicron integrated circuit designdeep submicron technologiesdeep submicron technologydeep-submicron circuitsdelaydelay analysisdelay budgetingdelay calculation methoddelay circuitsdelay constrained power optimizationdelay defect sizedelay equalizationdelay estimationdelay expressionsdelay fault diagnosisdelay fault identificationdelay fault testingdelay modeldelay modelsdelay optimizationdelay overheaddelay testingdelay upper boundsdelay variationdelay window propagationdelay-defect diagnosisdelay-defect-size estimationsdelay-fault diagnosisdelaysdesign complexitydesign for manufacturedesign for testabilitydesign mappability estimationdesign methodologydesign reliabilitydesign specificationsdesign timingdesign timing failuresdesign-for-reliability toolsdesign-for-testabilitydesign-timing failuresdetailed routingdeterministic algorithmsdeterministic patternsdeterministic routingDFTDFT overheaddiagnosis algorithmdiagnostic resolutiondiagnostic test patternsdielectric breakdowndiffusion contactsdigital arithmeticdigital circuit crosstalkdigital circuit optimizationdigital circuitsdigital integrated circuitsdigital MOS circuitsdigital VLSI circuit designdirect mappingdirected acyclic graphdirected graphsdiscrete gate resizingdiscrete-size cell librarydistributed parameter networksdistributed RC coupling networkdistributed RC coupling treesdivide and conquer methodsdivide-and-conquerdivisiondoglegsdon't caresDonath methoddouble-gate transistor-array-based layoutDragon routability-driven placerDRAM chipsdriver circuitsdriver sizedriving capabilitiesDWPdynamic noise marginsdynamic power dissipationdynamic transient currentdynamically reconfigurable FPGAsearthingECL encoder chipECO-Mapedge separabilityefficiencyefficient algorithmefficient ordering heuristicelectric noise measurementelectrical constraintselectrical propertyelectromigrationelectromigration constraintselectromigration phenomenaelectronic deviceselectronic engineering computingelectrostatic dischargeelement proximityempirical measureenergy consumptionengineering changeengineering change ordersengineering changesepitaxial source-drainequivalence classesequivalent circuitsequivalent resistanceserror correctionestimate-then-eliminate strategiesestimation theoryestimation-less placementevaluation machineexpansion-based placerexponent computationexternal don't caresextra variablefailing pattern analysisfailure analysisfailure analyzerfailure log processingfailure logsfailure mechanismsfan-out optimizationfanout treesfar-end couplingfast design convergencefast design mappability estimationfast physical verification toolfast placer implementationfast placer implementation frameworkfast postplacement optimizationfast timing verificationfast turn-around timesfault clusteringfault clustering analysisfault coveragefault detectionfault diagnosisfault locationfault multiplicityfault simulationFF reduction algorithmfield effect integrated circuitsfield effect transistor circuitsfield effect transistorsfield programmable gate arrayfield programmable gate arraysfine grain 3D integrated regular microprocessor blocksfine granularity clustering-based placementfine-granularity clustering algorithmFinFETfinite state machinesfinite-state machinesfirst-order Taylor expansionfixed metal masksfixed point arithmeticfixed polarityFixed Polarity Reed-Muller formfixed polarity Reed-Muller formsfixed-point additionfixed-polarity AND/XOR canonical networks minimisationflip-flopflip-flop minimizationflip-flopsflipflop minimizationfloorplanningforce directed placementforce directed schedulingformal verificationfour-variable functionsFPGAFPGA designFPGA placementFPGA routingFPGA routing architectureFPGA structuresFPGA-based designFPIFPI frameworkfree-scan flip-flopsFSMFSM decomposition theoryfull-scan designfunction representationfunctional correlation analysisfunctional equivalencefunctional flexibilityfunctional irredundant path sensitization criteriafunctional logicfunctional scan chain testingfunctional scan pathsfunctional symmetriesfunctional symmetryfunctional symmetry based rewiringGA approachgain controlGain-based technology mappinggate arraysgate delaygate delay calculationgate delaysgate sizinggate-level Boolean networksgate-level modelgate-level timing calculationgate-sizing algorithmgate-sizing methodgate-to-drain capacitancesgate-to-source capacitancesgated blocksgeneral cell layoutsgeneral skew constraintsgeneral-purpose fabricgeneralised Reed-Muller formGeneralized Reed-Mullergeneralized Reed-Muller formsgenetic algorithmsglobal netsglobal placementglobal power supply noiseglobal route mappingglobal routingglobal routing channel densityglobal routing techniqueglobal to detailed routing mappinggraph based analysisgraph domaingraph modelsgraph partitioninggraph theorygreedy 2-D routergreedy channel routergreedy coupling heuristicsgreedy routing architecturesgrid segmentsgrid sizingground bounceground bounce controlground grid networksground mesh sizing problemground node potentialsground noisegroup compatibilityH treeH-treehardware costheterogeneous 3D chipheuristicheuristic algorithmheuristic approachheuristic methodologyheuristic switch-level modelhierarchical FPGAshierarchical techniquehierarchical test set structurehigh diagnostic resolutionhigh fault coveragehigh level synthesishigh performance arithmetic circuitshigh speed test pattern generatorhigh throughput circuitshigh-density regular circuitshigh-density transistor arrayshigh-speed integrated circuitshigh-throughput circuit generationhighly periodic layouthold logichold logic designhold time defect diagnosishold time fault diagnosishold time violationshorizontal connectionshot carriershot-carrier effecthotspot detection toolhotspot pattern identificationHSPICE simulationHSPICE simulationshybrid methodologyI/O padsIC designIC layoutIC manufacturabilityIC testingidle blocksimplicit algorithmimplicit white space allocationimproved performancein-place optimizationincompletely specified functionsincompletely specified multiple output functionsincremental cell movement schemeincremental circuit restructuringincremental logic restructuringindividual wire length predictionindustrial applicationsindustrial designsinfrared voltage drop effectsinner loopsinput negationinput permutationinput switching conditionsinput switching dependency captureinput vectorsinsulated gate field effect transistorsinsulatorsinteger linear programminginteger programmingintegrated circuitintegrated circuit designintegrated circuit fabricationintegrated circuit interconnectionsintegrated circuit layoutintegrated circuit manufactureintegrated circuit manufacturingintegrated circuit measurementintegrated circuit modellingintegrated circuit noiseintegrated circuit packagingintegrated circuit reliabilityintegrated circuit technologyintegrated circuit testingintegrated circuitsintegrated design flowintegrated logic circuitsintegrationintellectual property blocksinter clock crosstalkinter-block connectionsinter-clock crosstalkintercell routingintercell white spaceinterconnect coupling noiseinterconnect delaysinterconnect insensitive driver modelinterconnect length predictioninterconnect predictioninterconnect resource-aware placementinterconnect structureinterconnect-related failure modesinterconnected IP coresinterconnectioninterconnection complexityinterconnectionsinterconnectsinterference suppressioninternal nodesintra-block connectionsintracell routingintrinsic delayIR dropIR drop noiseIR drop waveformsISCASiterationiterative methoditerative methodsiterative updatingjitterjitter characteristicslarge CMOS designslarge networkslarge scale integrationlarge scan designslarge-scale meshlarge-scale networklatch count minimizationlatcheslatencylatency penaltieslayoutlayout aspect ratiolayout effectslayout friendly structureslayout friendly synthesized structureslayout generatorlayout object printabilitylayout stylelayout techniqueslayout-driven hot-carrier degradationlayout-driven synthesisleakage currentsleakage powerleakage power reductionleakage power savinglearning (artificial intelligence)level-induced jitterlinear circuit elementslinear equationslinear modellinear network analysislinear program sequencelinear programminglinear programming approachlinear programming-based techniquelinear time complexitylinear time-varying driver modellinear-region modellinear-time algorithmlinearized pseudo-symmetric binary decision diagramliteral minimizationlithographic hotspot detectionlithographylocal netslocal power supply voltagelocal truncation errorlocally optimal switch box routinglogic arrayslogic assignmentslogic CADlogic circuitslogic contractionlogic designlogic effortlogic functionlogic gateslogic minimizationlogic minimization techniqueslogic optimizationlogic optimization techniqueslogic partitioninglogic perturbationlogic representationlogic restructuringlogic restructuring techniqueslogic simulationlogic stagelogic synthesislogic synthesis algorithmslogic testinglogic verificationlong wireslong-term reliabilitylongest delaylook-up tableslookup-table-typelow complexitylow energy network-on-chip fabriclow granularity pipelininglow-cost BIST schemelow-overhead scan design methodologylow-overhead scan path designlow-power buffered clock tree designlow-power electronicslower bound complexitylower levelslower-bound time complexityLTV modelM1-M2 via maskmachine learningmandatory assignmentsmanufacturing defectsmanufacturing process variationsmappabilitymappingmapping propertiesmapping ratiomapping solutionsmask costmasksmaximum IR-drop constraintsMCNCMCNC benchmarkMCNC benchmarksMCNC circuitsmemory array macrosmesh topologymetal gatemetal layersmetal masksmetric of dynamic binatenessmicroprocessormicroprocessor chipsmiddle-of-line PC-to-CA dielectric reliabilitymiddle-of-line poly gate-to-diffusion contact reliability issuesmin-max delay modelminimisationminimisation of switching netsminimization algorithmsminimizeminimizing inter clock coupling jitterminimum area sequential budgetingminimum number of blocksminmax delay modelmodeling graphmodern chip designsMOL PC-CA shortsMOL PC-to-CA dielectric reliabilitymonolithic integrated circuitsMonte Carlo methodsMOS integrated circuitsMOS transistorsMOSFETmulti-level combinational circuitsmulti-pin net listsmulticore processormulticore processorsmulticore systemmulticore systemsmultigrid-based techniquemultilevel Boolean network optimizermultilevel combinational networksmultilevel expansion-based VLSI placementmultilevel fixed point additionmultilevel logic synthesismultilevel logic synthesis methodmultilevel networksmultipin netmultiple candidate signalsmultiple clock tree routingmultiple fault diagnosismultiple gating schedulesmultiple power gatingmultiple-error diagnosismultiple-fault diagnosismultiple-valued decomposersmultiple-valued relationsmultiple-valued relations decompositionmultiplexermultiplicationmultipliersmultiplying circuitsmultiprocessing systemsmultiterminal networksmultivalued logicmultivalued logic circuitsmutual contractionmutually capacitively coupled signalsn-bit addern-detectionn-detection testnanometer technologynanotechnologynatural representationsnear-driver coupling locationnear-end coupling directionnear-receiver couplingnet absorptionnet absorption algorithmnet orderingnet partitioningnet rangenet slacknet weighting delaysnetlistnetlist clusternetlist structurenets intersectionnetwork optimizationnetwork parameternetwork routingnetwork synthesisnetwork topologynetwork-on-chipNoCNoC communication fabricnoisenoise delay faultsnoise eliminationnoise estimationnoise faultnoise faultsnoise signalsnoise sourcesnoise waveformnoise waveform widthnoise-constrained layout synthesisnoise-on-signal propagationnoniterative layout techniquenoniterative synthesis techniquenonlinear programmingnonlinear programming problemnonlinear resistive devicenonlinear transfer characteristics approximationnonrobust propagation conditionsnonrobust testnonrobust test patternsNP hard problemNP-complete problemnumerical iterationsOBDD minimizationoff-seton-chip power supplyon-chip power-supply network optimizationon-chip switchingon-setone-step routerOPC-free IC designOPC-free interconnect manufacturing processoptical proximity correctionoptical proximity correction free processoptimal algorithmoptimal detailed routingoptimal entire-chip routingoptimal polarityoptimal selectionoptimal solutionoptimisationoptimizationoptimization cost functionoptimization speed increaseoptimization techniquesoptimize sequential circuitsOR gatesorder graphordered binary decision diagrams minimizationoutput negationoverall circuit functionalityoverall device areapackagingparallel metal tracksparameter variationsparametric yieldpartial correspondencepartial-scan designpartial-scan designspartition based placementpartitioning approachpartner patternspass transistor logicpassing patternspath delaypath delay constraintspattern classificationpattern matchingpattern matching-based toolspeak coupled noise voltage boundpeak crosstalk noisepeak crosstalk noise amplitudepeak noise occurring timeperformance deteriorationperformance improvementperformance lossperformance optimizationperformance optimization algorithmsperformance optimization issuespermutation equivalent LUTsperturbation techniquesperturbation theoryphase locked loopsphoto-lithographiyphotolithographyphysical designphysical layoutphysical synthesispiecewise-linear functionspiecewise-linear techniquespin assignmentpin assignment algorithmpin densitypin reorderingpipeline arithmeticpipeline processingpipelined interconnectpipelining techniquesPITIAplacement algorithm efficiencyplacement efficiencyplacement flowplacement programsplacement quality lossplacement stabilitypolynomial time mapping solutionspolysilicon control gatepositionspost-layout designpost-layout physical distancepostlayout logic restructuringpotential slack budgetingpower aware computingpower consumptionpower deliverypower densitypower dissipationpower dropspower estimationpower gated ICpower gatingpower gating configurationpower gating designspower gating schedulingpower gridpower grid analysispower grid networkspower grid noisepower grid optimisationpower gridspower ground networkspower integrated circuitspower mesh granularitypower minimizationpower noisepower noise reductionpower optimizationpower reductionpower saving techniquespower sizing problempower supplypower supply circuitspower supply networkpower supply noisepower supply noise aware workload assignmentpower supply variationspower supply voltage variationspower timingpower-gated chipspower-gated ICpower-gatingpower-gating aware floorplanningpower-gating techniquepower/ground IR-dropspower/ground mesh area optimizationpower/ground network synthesispower/ground noise reductionpower/ground supply network optimizationpre-layout physical connectivity predictionpredictable detailed routingprefabricated logic blocksprime number based segmentationprobabilistic modelprobabilityprobability-basedprobability-based techniqueprocess speedupprocess variationprocess variationsprocessor coresprogram GUD-MVprogrammable cellprogrammable logic arraysprogrammable logic devicesprogrammable SRAMsprogrammable via mask customized interconnectsproximity effect (lithography)pseudocellsPTLPTL mappingpulse widthquadratic placement techniquequadratic programmingracesRAMFIRErandom pattern resistant faultsrandom-access storagerapid layout pattern classificationrapid signal transitionsRC circuitsRC interconnectsreasoning schemereceiver sizerecognizing strings of patternsreconfigurable architecturereduced delay errorreduced ordered binary decision diagramredundancyredundancy additionredundancy detection algorithmredundancy removalredundancy removal processredundancy-addition-and-removalredundant alternative wireredundant faultsredundant wiresReed-Muller codesReed-Muller formsregular fabricregular fabricsregular segmentationregular segmentedreliabilityreliability analysisreliability constraintsreliability optimizationreliability problemsRent exponentRent ruleRent's rulerepeater chainrepeater chainsresistance-inductance-capacitance power-supply networkresistive capacitively coupled linesresistive VLSI interconnectionsretimingrewiringrewiring enginerewiring techniquerise timeRLC circuitsRLC networkROBDD size minimisationRoth-Karp decompositionrough partition representationroutabilityroutability problemroute strategyrouter cost functionsroutingrouting algorithmrouting architecturerouting congestionrouting flexibilityrouting lengthrouting problemrouting resource usagerule-based postprocessorrun timeruntime enhancement techniquesSATSAT logicsaturation-region modelscalabilityscalingscan chainscan designscan encoded test pattern generationscan orderscan overhead reductionscan pathscan pathsscan synthesisscan-based BIST schemeschedulingSDF delay informationsea-of-gates designssearch space reductionseed-growth clustering algorithmsegmented prefabricated wiressemi-individual wire-length predictionsequence of linear programssequence of linear programs solutionsequential benchmark circuitssequential circuitsequential circuitssequential circuits optimizationsequential circuits partitioningsequential circuits pipeliningsequential delay budgetingsequential elementssequential fault simulationsequential linear programmingsequential machinessequential permissible functionsseries-parallel functionsshapesshort path activation conditionshort-channel MOSFETshort-channel MOSFET behaviorshort-channel MOSFET modelsignal alignmentsignal arrival timessignal functionalitysignal orderingsignal propagationsignal routingsignal timingsignal transition correlationsignal transition timessignal transitionssignature of variablessignaturessignatures setsimpler fault simulationsimulated annealingsimulated annealing based placementsimulation resultssimulation-based methodsimulation-based techniquesimulation-based techniquessingle processorsingle stuck-at fault testabilitysingle-delay-fault diagnosissingle-fault-based diagnostic algorithmsingle-pass techniquesingle-via-mask fabricsize 32 nmsize 45 nmskew-retiming equivalenceslack assignment algorithmsleep transistorsleep transistorssleep-transistor sizeslower-than-nominal clock frequenciesspare cellsspare-recycled cellsSPARSE routabilityspecial net routingspecification changespecified timing constraintsspeedupSPICESPICE-like integration approachsquare rootSRAM arraysSRAM based FPGAsSRAM cellsSRAM chipsSRAM functional stress failuresSRAM read operationSRAM registersSRAM stabilitySRAM yield lossstandard cell designstandard cell global placementstandard cell implementationstandard cell librariesstandard cell placement toolstandard cellsstandard-cell based designstandard-cell designstandard-cell placement problemstandard-cell- based designsstar testSTAR-ATPGSTAR-ATPG algorithmSTAR-BISTstate traversal approachstate variable dependenciesstate-variable dependenciesstatic CMOS combinational circuitsstatic timing analysisstatic timing optimizationstatistical Monte-Carlo circuit simulationsstatistical static timing analysis flowstatistical timing modelSteiner tree heuristicsstepwise constant conductancesstepwise equivalent conductance modelstepwise equivalent conductance timing simulatorstress linerstrongly unspecified datastrongly unspecified multiple-valued functionsstructural metricsstructured ASICstuck-at faultssubject functionsubmicron technologiessuboptimal power supply network designsubtractionsummation of wire lengthssuper gate extractionsuper-regular layout stylesuper-regular transistor arrangementsupergate structuressupply noise aware workload assignment methodsupply voltage levelsupport vector machinesSWECswitch boxswitch box connection topologyswitch numberswitch-level timing analysisswitchesswitches per switch boxswitchingswitching activities estimationswitching circuitswitching circuitsswitching currentsswitching directionsswitching frequencyswitching networksswitching theoryswitching timessymmetric variablessymmetric variables detectionsymmetrysynchronous circuitssynchronous digital systemssynthesized modulessystem performancesystem-on-chipsystem-on-chip designtable lookuptarget TLU table lookup architecturetarget wiretechnology mappingtechnology parameterstechnology remappingtelescopic unittelescopic unitstemplatestemporofunctional crosstalk noise analysistest generatortest modetest point insertiontest vectorstest-mode point insertion techniquetestabilitytesting setthin Boolean functionsthin-oxide decapthree-dimensional integrated circuitsthree-input lookup table cellsthrough silicon viasthroughputthroughput-intensive designtime division multiplexingtime intervaltime phasestime steptime-domain analysistime-multiplexed computationtime-multiplexed routing resourcestime-varying current sourcestime-varying networkstime-varying switching-current modeltimed Boolean logictimingtiming analysistiming awaretiming aware sequential budgetingtiming circuitstiming closuretiming constrainttiming constraintstiming critical netstiming defect diagnosistiming driven layout synthesistiming driven placementtiming errorstiming estimationtiming failurestiming faultstiming jittertiming optimizationtiming relationstiming windowtiming window propagationtiming windowstiming-aware automatic test pattern generation setstiming-aware multiple-delay-fault diagnosistiming-aware power noise reductiontiming-driven partial scan designtiming-driven placementtop leveltopological analysistopologytotal areatotal number minimisationtotal wire length guided placerstotally symmetric functionstrack numbertrade-off curvetransfer functionstransformations of function graphstransient analysistransistor circuitstransistor current modeltransistor footprinttransistor masktransistor sizestransistor sizingtransistor-level high-density regular circuitstransistorstransistors threshold voltagetransition densitytrees (mathematics)trial-and-error redundancy testingtwin gate vertical slit FETtwo dimensional FPGAstwo pole transfer functiontwo-dimensional field programmable gate arraytwo-dimensional FPGAtwo-level form specified functionstwo-level hotspot pattern classification methodologytwo-level representationtwo-phase clocking schemetwo-pin connectiontwo-pin net liststwo-sided routingtwo-step technology mapping algorithmTWPuncorrelated power noiseunified logic/physical synthesis schemeuniform RLC poweruniversal logic blocksuniversal logic gateunknown input correspondenceupper bound delay constraintsuser specified constraintsuser-specified control sequencevariable-latency design stylevariable-latency designsVCGA-based designverifying equivalencevertical connectionsvertical slit device architecturevertical slit field effect transistor circuitsvertical slit field effect transistorsvertical slit transistor based integrated circuitvery fine granular pipeliningvery large scale integrated circuitvery large scale integrationVeSFETVeSFET circuitsVeSFET technologyvia configurable gate arrayvia configurable regular fabricvia configurable routing architecturevia-configurable functional cellvia-configurable functional cellsvia-configurable gate arrayvia-configurable inverter arraysvia-configurable logic blockvia-configurable regular fabric architecturevia-configurable regular fabric designvia-configurable routing architecturesvia-decomposable flip-flopvictim driver modelingvictim switching waveformvirtual voltage levelVLSIVLSI circuitVLSI circuit designVLSI designVLSI design implementationVLSI design processVLSI interconnectionsVLSI layout designVLSI manufacturing technologyVLSI placementVLSI realizationvoltage dropvoltage drop aware power grid optimizationvoltage regulatorswake-up orderwake-up time constraintwave pipeliningwave steered circuitswave steered FSMswave steeringwave steering techniquewave-steered design methodologywaveform analysiswhite-space allocationwhite-space allocation schemewire lengthwire length prediction based clusteringwire orderingwire redundancy checkingwire sizingwire spacingwire widthwire width optimizationwire-length predictionwiringwiring segmentationworst delay estimationworst-case crosstalk noiseXerox general cell benchmarkXilinx 4000 style architectureXilinx architectureXilinx-4000-like routing architectureXilinx-like routing architecturesXilinx-like routing modelYADD structuresYADDsyet another decision diagramYet Another Decision Diagrams Found 18 results Author Title Type Year Filters: Author is Shih-Chieh Chang [Clear All Filters] Conference Paper A. Todri, Marek-Sadowska, M., and Chang, S. - C., “Analysis and optimization of power-gated ICs with multiple power gating configurations”, in Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on, 2007, pp. 783 -790. S. - C. Chang, Marek-Sadowska, M., and Cheng, K. - T., “An efficient algorithm for local don't care sets calculation”, in DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, 1995, pp. 663–667. Y. - S. Su, Wang, D. - C., Chang, S. - C., and Marek-Sadowska, M., “An Efficient Mechanism for Performance Optimization of Variable-Latency Designs”, in Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, 2007, pp. 976 -981. A. Todri, Chang, S. - C., and Marek-Sadowska, M., “Electromigration and voltage drop aware power grid optimization for power gated ICs”, in Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on, 2007, pp. 391 -394. Y. - M. Kuo, Chang, Y. - T., Chang, S. - C., and Marek-Sadowska, M., “Engineering change using spare cells with constant insertion”, in ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, 2007, pp. 544–547. S. - C. Chang, Van Ginneken, L. P. P. P., and Marek-Sadowska, M., “Fast Boolean optimization by rewiring”, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 262 -269. S. - C. Chang, Cheng, K. - T., Woo, N. - S., and Marek-Sadowska, M., “Layout Driven Logic Synthesis for FPGAs”, in Design Automation, 1994. 31st Conference on, 1994, pp. 308 - 313. S. - C. Chang, Cheng, D. I., and Marek-Sadowska, M., “Minimizing ROBDD size of incompletely specified multiple output functions”, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 620 -624. S. - C. Chang and Marek-Sadowska, M., “Perturb And Simplify: Multi-level Boolean Network Optimizer”, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 2 -5. S. - C. Chang and Marek-Sadowska, M., “Perturb and simplify: optimizing circuits with external don't cares”, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 402 -406. S. - C. Chang and Marek-Sadowska, M., “Technology mapping and circuit depth optimization for field programmable gate arrays”, in Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993, 1993, pp. 3.5.1 -3.5.4. S. - C. Chang and Marek-Sadowska, M., “Technology mapping via transformations of function graphs”, in Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings., IEEE 1992 International Conference on, 1992, pp. 159 -162. S. - H. Weng, Kuo, Y. - M., Chang, S. - C., and Marek-Sadowska, M., “Timing analysis considering IR drop waveforms in power gating designs”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 532 -537. Journal Article S. - C. Chang, Van Ginneken, L. P. P. P., and Marek-Sadowska, M., “Circuit optimization by rewiring”, Computers, IEEE Transactions on, vol. 48, pp. 962 -970, 1999. Y. - S. Su, Wang, D. - C., Chang, S. - C., and Marek-Sadowska, M., “Performance Optimization Using Variable-Latency Design Style”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 1874 -1883, 2011. S. - C. Chang, Marek-Sadowska, M., and Cheng, K. - T., “Perturb and simplify: multilevel Boolean network optimizer”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 1494 -1504, 1996. S. - C. Chang, Cheng, K. - T., Woo, N. - S., and Marek-Sadowska, M., “Postlayout logic restructuring using alternative wires”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 587 -596, 1997. Y. - M. Kuo, Chang, Y. - T., Chang, S. - C., and Marek-Sadowska, M., “Spare Cells With Constant Insertion for Engineering Change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 456 -460, 2009. Electrical and Computer Engineering, Harold Frank Hall, University of California, Santa Barbara, CA - 93106. Log In