COMMUNICATION UNIT, INTEGRATED CIRCUIT AND METHOD FOR CLOCK DISTRIBUTION AND SYNCHRONIZATION
FIG1 illustrates a block diagram of a known radar unit that cascades two radar TRx chips
In some examples, a systematic error between the synchronized data and clock signals, which can be due to process variations, for example, can be tolerated and may be compensated through a higher level phase calibration. After such process impact calibration, the MCU may be configured to add a dedicated systematic phase offset on each receiver channel at, say, the start-up of the respective master and slave devices, whose value may be found during a calibration process to align all phases of all signals (e.g. intermediate frequency (IF) signals) coming from all receivers. For optimal operation of distributed radar systems, it is important that the signals (such as LO 140, MS clock signal 142 and RFS 166 from FIG1) are synchronous across all receiver circuits on different devices. This means that, after calibration of the phase difference between all receiver channels in all master and slave devices, the voltage supply Vcc, temperature and aging variation between all devices distributed within the PCB should not change the initial clock alignment, for example after a one-time calibration operation is performed at radar module level.
block diagram
166
RFS signal
164
MCU clock interface
160
MCU
142
clock signal
168
circuit
165
this clock signal
140
signal
110
master device
114
receive antennas
120
slave device slave devices
['1. A communication unit (400, 500) comprising: a plurality of cascaded devices that comprise at least one master device (510) and at least one slave device (520) configured in a master-slave arrangement; wherein the communication unit (400, 500) is  characterized in that : the at least one master device (510) comprises: a clock generation circuit configured to output a system clock signal; a modulator circuit (562) coupled to the clock generation circuit and configured to receive the system clock signal and a frame start signal and embed the frame start signal into the system clock signal to produce a modulated embedded master-slave clock signal (584); and transmit the modulated embedded master-slave clock signal (584) to the at least one slave device to synchronise the system clock signal and the frame start signal between the at least one master device (510) and at least one slave device (520).']