CONSERVATIVE RASTERIZATION
FIG3B is a schematic diagram showing a second part of the conservative rasterization hardware from the pipeline of FIG2A in more detail
Having calculated outer coverage results, On,i, for a pixel i and each edge n, the results for the different edges are combined using an AND gate 308 (block 408) as shown in FIG3B. This generates a single outer coverage result Oi for the pixel i and if it is zero it indicates that the primitive does not intersect any part of the square pixel area. Conservative rasterization does not permit false negatives for outer coverage results, although a small number of false positives for outer coverage results are permitted. The false positives that are obtained may be removed using a bounding box, as described below. Having calculated inner coverage results, In,i, for a pixel i and each edge n, the results for the different edges are combined using an AND gate 310 (block 410) as shown in FIG3B. This generates a single inner coverage result Ii for the pixel i and if it is zero it indicates that the primitive does not fully cover the square pixel area. The inner coverage is performed precisely and there are no inherent false positives.
schematic diagram
310
gate
306
gate gates
304
gate
302
hardware elements hardware element
308
gate
['2. The graphics processing pipeline according to claim 1, wherein the edge test calculation hardware (302) comprises one or more hardware arrangements (500, 520) each arranged to perform an edge test using a sum-of-products, each hardware arrangement comprising: a microtile component hardware element (502) comprising hardware logic arranged to calculate a first output using the sum-of-products and coordinates of a microtile within a tile in the rendering space; a plurality of pixel component hardware elements (504, 524), each comprising hardware logic arranged to calculate one of a plurality of second outputs using the sum-of-products and coordinates for different pixel corners defined relative to an origin of the microtile; a plurality of adders arranged to generate a plurality of output results for the sum-of-products in parallel by combining, for each output result, a different combination of the first output and one of the plurality of second outputs.']