ARRAY SUBSTRATE, DISPLAY PANEL, AND DISPLAY DEVICE
FIG2 is an exemplary block diagram illustrating a display panel provided by another embodiment of the present disclosure and a display device provided by yet another embodiment of the present disclosure
For example, FIG2 is an exemplary block diagram illustrating a display panel provided by another embodiment of the present disclosure and a display device provided by yet another embodiment of the present disclosure. For example, as illustrated in FIG2, the display panel can include an array substrate. It should be understood that, for other indispensible components (e.g., opposed substrate, a LC layer and the like) for the display panel, conventional components can be adopted, which should be appreciated by those skilled art in the art, no further descriptions will be given herein and it shall not be constructed as limitations to the embodiments of the present disclosure. The display panel achieves an improvement in the aperture ratio. For example, as illustrated in FIG2, the display device can include the display panel or the array substrate described above. It should be understood that, other indispensible components (e.g., a controlling device, an image data encoding/decoding device, a row scanning driver, a column scanning driver, a clock circuit and the like) for the display device are also included in the display device, which should be appreciated by those skilled art in the art, no further descriptions will be given herein and it shall not be constructed as limitations to the embodiments of the present disclosure. The display device achieves an improvement in the aperture ratio.
exemplary block diagram
210
data line
100
array substrate
260
common electrode line
232
second sub-pixel
255
second electrode portion
3
andFig.
200
array substrate
['3. The array substrate according to claim 2, wherein the three sub-pixels comprise a first sub-pixel adjacent to the first gate line, a third sub-pixel adjacent to the second gate line, and a second sub-pixel located between the first sub-pixel and the second sub-pixel, the first sub-pixel is electrically connected to the first gate line and the first data line, the third sub-pixel is electrically connected to the second gate line and the first data line, and the second sub-pixel is electrically connected to the first gate line and the second data line, or is electrically connected to the second gate line and the second data line.', '11. The array substrate according to claim 10, wherein the first driving sub-electrode comprises a first electrode portion and a second electrode portion which extend along different directions, and the first electrode portion and the second electrode portion are intersected with the rubbing alignment direction, respectively.', '14. The array substrate according to claim 11, further comprising a common electrode line, wherein the common electrode line is non-transparent and is disposed between adjacent two of the sub-pixels.']