COMMUNICATION UNIT, INTEGRATED CIRCUIT AND METHOD FOR CLOCK DISTRIBUTION AND SYNCHRONIZATION
FIG7 illustrates an example flowchart of the steps associated with synchronization across multiple master device(s)-slave device(s), according to example embodiments of the invention
Referring now to FIG7 an example flowchart 700 of the steps associated with synchronization across multiple master device(s)-slave device(s) is illustrated, according to example embodiments of the invention. The flowchart starts at 702, with a start-up of at least the master device and/or a MCU. At 704, the reference phase locked loop (PLL) of the radar unit is initiated. In some examples, at 704, a clock signal is sent to master device(s) and slave device(s) and the MCU. In one example at 706, a main PLL is initiated and a waveform generator of a master device controls its VCO to output a LO signal with a fixed frequency that is proportional to a chirp start frequency, fstart_master.
flowchart
704
At
712
At
710
At
706
In one example at
708
at
702
flowchart starts at
716
flowchart ends at
714
At
700
example flowchart
['1. A communication unit (400, 500) comprising: a plurality of cascaded devices that comprise at least one master device (510) and at least one slave device (520) configured in a master-slave arrangement; wherein the communication unit (400, 500) is  characterized in that : the at least one master device (510) comprises: a clock generation circuit configured to output a system clock signal; a modulator circuit (562) coupled to the clock generation circuit and configured to receive the system clock signal and a frame start signal and embed the frame start signal into the system clock signal to produce a modulated embedded master-slave clock signal (584); and transmit the modulated embedded master-slave clock signal (584) to the at least one slave device to synchronise the system clock signal and the frame start signal between the at least one master device (510) and at least one slave device (520).']