GUARANTEED DATA COMPRESSION
FIG13B is a schematic diagram of a hardware implementation of the method of FIG13A
An adjustment value is then determined (block 1204) based on the input n-bit number, N, and, as described below, this may be implemented using a number of AND and OR gates in the look-up logic unit 1224. These AND and OR logic gates (or alternative logic arrangement that is functionally equivalent) compare a plurality of pre-determined subsets of the bits of N with pre-determined values in fixed-function circuitry and based on the outcome of the comparisons, determine an adjustment value which is then added to the replicated value (from block 1302 and replication hardware unit 1322) in the increment/decrement unit 1226 (block 1306). The value of the adjustment value is either zero, one, or minus one. In some examples, i.e. for some combinations of values of n and m (where n<m), the adjustment value is always zero and hence both the increment/decrement unit 1226 and the look-up logic unit 1224 can be omitted from FIG13B.
schematic diagram
1226
increment/decrement unit
1204
block
1302
block
1224
unit
1322
replication hardware unit
['1. A method of mapping an input n-bit number to an output m-bit number, where n and m are integers and n>m, the method comprising: truncating, in a truncation hardware unit (1222), the input n-bit number from n-bits to m-bits to form an intermediate m-bit number (1202); in a look-up logic hardware unit (1224): (i) comparing pre-determined subsets of the bits of the input n-bit number with pre-determined values in fixed-function circuitry, and (ii) setting an adjustment value in dependence on the results of the comparisons; and adding, in an increment/decrement hardware unit (1226), the adjustment value to the intermediate m-bit number to generate the output m-bit number (1206).', '3. A method of mapping an input n-bit number to an output m-bit number, where n and m are integers and n<m, the method comprising: appending, in a replication hardware unit (1322), (m-n) most significant bits of the input n-bit number to the input n-bit number to form an intermediate m-bit number (1302); in a look-up logic hardware unit (1224): (i) comparing pre-determined subsets of the bits of the input n-bit number with pre-determined values in fixed-function circuitry, and (ii) setting an adjustment value in dependence on the results of the comparisons; and adding, in an increment/decrement hardware unit (1226), the adjustment value to the intermediate m-bit number to generate the output m-bit number (1306).']