EMBEDDED NETWORK ON CHIP ACCESSIBLE TO PROGRAMMABLE LOGIC FABRIC OF PROGRAMMABLE LOGIC DEVICE IN MULTI-DIMENSIONAL DIE SYSTEMS
FIG2 is a block diagram of a package including the programmable logic device where a fabric die is vertically stacked with a base die, in accordance with an embodiment
One example of the programmable logic device 12 is shown in FIG2, but any suitable programmable logic device may be used. In the example of FIG2, the programmable logic device 12 includes a fabric die 22 and a base die 24 that are connected to one another via microbumps 26. Although the fabric die 22 and base die 24 appear in a one-to-one relationship in FIG2, other relationships may be used. For example, a single base die 24 may attach to several fabric die 22, or several base die 24 may attach to a single fabric die 22, or several base die 24 may attach to several fabric die 22 (e.g., in an interleaved pattern along the x- and/or y-direction). Peripheral circuitry 28 may be attached to, embedded within, and/or disposed on top of the base die 24, and heat spreaders 30 may be used to reduce an accumulation of heat on the programmable logic device 12. The heat spreaders 30 may appear above, as pictured, and/or below the package (e.g., as a double-sided heat sink). The base die 24 may attach to a package substrate 32 via C4 bumps 34. In the example of FIG2, two pairs of fabric die 22 and base die 24 are shown communicatively connected to one another via a silicon bridge 36 (e.g., an embedded multi-die interconnect bridge (EMIB)) and microbumps 38 at a silicon bridge interface 39.
block diagram
24
base die
28
peripheral circuitry
14
design software
12
programmable logic device
30
heat spreaders
38
microbumps
22
fabric die
18
bitstream
39
silicon bridge interface
2
sector integrated circuit die. CLAUSE
20
configuration program
34
via C4 bumps
26
microbumps
21
CLAUSE
36
silicon bridge
32
package substrate
['7. A programmable logic device comprising: a plurality of regions of programmable logic fabric disposed in a first integrated circuit die, wherein the plurality of regions comprises a first set of programmable logic elements controlled by a respective set of configuration memory cells; network on chip (NOC) circuitry disposed in a second integrated circuit die, wherein the NOC circuitry is connected to at least one of the plurality of regions of programmable logic fabric via a physical connection, wherein the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die via the physical connection.']