LIQUID CRYSTAL DISPLAY PANEL AND DEVICE
FIG3 is a schematic illustrative drawing of a liquid crystal display panel according to the present disclosure 
FIG3 is a schematic illustrative drawing of a liquid crystal display panel according to the present disclosure. As shown in FIG3, the liquid crystal display panel of the present disclosure comprises a data line 11, a scanning line 12, a first common line 21, and a second common line 22. The liquid crystal display panel further comprises a main-pixel portion 201 and a sub-pixel portion 202. The present disclosure further provides a liquid display device, which comprises a back-light module and a liquid crystal display panel, as shown in FIG3, the liquid crystal display panel comprises a data line 11, a scanning line 12, a first common line 21, and a second common line 22. The liquid crystal display panel further comprises a main-pixel portion 201 and a sub-pixel portion 202.
schematic
201
main-pixel portion
202
sub-pixel portion
12
line
203
first pixel electrode
11
data line
22
second common line
204
second pixel electrode
21
common line
['1. A liquid crystal display panel, comprising a data line, a scanning line, a first common line, a second common line, a main-pixel portion, and a sub-pixel portion; the first common line being for supplying a common voltage, the second common line being for making a voltage of the sub-pixel portion equal to a fixed value and a voltage of the main-pixel portion is different from the voltage of the sub-pixel portion when the liquid crystal display panel is aligned; the voltage of the sub-pixel portion is obtained by a voltage inputted according to the second common line; wherein the main-pixel portion comprises a first thin film transistor and a first pixel electrode, the first thin film transistor comprises a first gate electrode, a first source electrode, and a first drain electrode, the first gate electrode is connected to the scanning line, the source electrode is connected to the data line, and the first drain electrode is connected to the first pixel electrode; and wherein the sub-pixel portion comprises a second thin film transistor, a third thin film transistor, and a second pixel electrode, the second thin film transistor comprises a second gate electrode, a second source electrode, and a second drain electrode, the third thin film transistor comprises a third gate electrode, a third source electrode, and a third drain electrode, the second gate electrode and the third gate electrode are connected to the scanning line, the second source electrode is connected to the data line, the second drain electrode is connected to the third drain electrode, the third drain electrode is connected to the second pixel electrode, and the third source electrode is connected to the second common line.']