CONTROL APPARATUS, SYSTEM PROGRAM, AND CONTROL METHOD
FIG3 is a schematic diagram showing an example of a hardware configuration of a computation unit constituting the control apparatus according to the present embodiment
Referring to FIG3, the computation unit 13 includes a processor 100, a chipset 102, a main memory 104, a nonvolatile memory 106, a system timer 108, a PLC system bus controller 120, a field network controller 140, and a USB connector 110. The chip set 102 is connected to other components through various buses. Although FIG3 illustrates one processor 100 for convenience of description, a plurality of processors 100 may be provided or a plurality of cores may be mounted in one processor 100. The performance and configuration of the processor 100 may be determined according to required computing resources.
schematic diagram
142
DMA control circuit
130
PLC system bus connector
100
processor processors
126
buffer memory
104
main memory
20
ms operation per
144
field network control circuit
146
buffer memory
102
chipset
108
system timer
106
nonvolatile memory
140
field network controller
110
USB connector
124
system bus control circuit
120
PLC system bus controller
13
computation unit
['1. A control apparatus (1) for controlling a control object, comprising: a processor (100); a first program (240) which is repeatedly executed by the processor and has a highest execution priority; a second program having a lower execution priority than the first program; a third program having a lower execution priority than the second program; and a scheduler program which manages programs executed by the processor, wherein the second program includes a notification command (224) for outputting a start notification (270) according to start of execution in the processor and outputting an end notification (272) according to completion of execution in the processor, and the scheduler program (212) includes a command (2120) for causing the processor to execute the second and third programs such that execution of the first program is not obstructed, and a command (2122) for determining an execution state of the second program in each predetermined monitoring cycle (262) on the basis of the start notification and the end notification from the second program; characterized by  a fourth program (242) having a higher execution priority than the second program, wherein the scheduler program includes a command (2124) for temporarily interrupting execution of the fourth program when the execution state of the second program does not satisfy predetermined settings, the command for determining the execution state includes a command for determining an execution state of the third program in the monitoring cycle, and the scheduler program includes a command (2124) for temporarily interrupting execution of the second program when the execution state of the third program does not satisfy predetermined settings.']