PROCESSOR INSTRUCTION SUPPORT TO DEFEAT SIDE-CHANNEL ATTACKS
FIG12B is an expanded view of part of the processor core in FIG12A according to embodiments of the invention
FIG12B is an expanded view of part of the processor core in FIG12A according to embodiments of the invention. FIG12B includes an L1 data cache 1206A part of the L1 cache 1204, as well as more detail regarding the vector unit 1210 and the vector registers 1214. Specifically, the vector unit 1210 is a 16-wide vector processing unit (VPU) (see the 16-wide ALU 1228), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit 1220, numeric conversion with numeric convert units 1222A-B, and replication with replication unit 1224 on the memory input. Write mask registers 1226 allow predicating resulting vector writes.
expanded view
1204
cache
1226
input. Write mask registers
1228
ALU
1210
vector unit
1214
vector registers
1224
1220
inputs with swizzle unit
1208
scalar unit
1202
interconnect network
1212
scalar registers
1206
cache
1200
instruction decoder
['3. The apparatus of any one of claims 1-2, further comprising: a cache, an entry in the cache including a second flag that, when set, identifies an entry that, upon eviction, causes the first flag in the first register to be cleared and the second flag in the entry to be cleared.']