SHIFT REGISTER, DRIVING METHOD THEREFOR, GATE DRIVER DEVICE, AND DISPLAY DEVICE
FIG2 is an exemplary block diagram of a shift register according to an embodiment of the present disclosure
FIG2 illustrates an exemplary block diagram of a shift register 100 according to an embodiment of the present disclosure. The shift register 100 includes an input circuit 110, a hold circuit 120, an output selection circuit 130, a first output circuit 140, a second output circuit 150, and a third output circuit 160.
exemplary block diagram
160
third output circuit
130
output selection circuit
100
shift register shift registers
2
March
140
first output circuit
110
input circuit
150
second output circuit
120
hold circuit
['1. A shift register comprising an input circuit, a hold circuit, an output selection circuit, a first output circuit, a second output circuit, and a third output circuit; wherein the input circuit is configured to control a voltage of a first node and a voltage of a second node based on a start signal from an input terminal, a first clock signal from a first clock signal terminal, and a first voltage from a first voltage terminal; the hold circuit is configured to hold the voltage of the first node and the voltage of the second node as well as an output signal of the first output circuit and an output signal of the second output circuit; the output selection circuit is configured to select the first output circuit and/or the second output circuit to output a scanning signal, and control a voltage of a third node and/or a voltage of a fourth node based on the voltage of the second node; the first output circuit is configured to output a first output signal from a first output terminal based on the voltage of the first node and the voltage of the third node; the second output circuit is configured to output a second output signal from a second output terminal based on the voltage of the first node and the voltage of the fourth node; and the third output circuit is configured to output a third output signal from a third output terminal based on a second clock signal and the voltage of the second node.']