HALF-BRIDGE DRIVER CIRCUIT, RELATED INTEGRATED CIRCUIT AND SYSTEM
FIG8 shows an embodiment of a digital processing circuit of the half-bridge driver of FIG7, wherein the digital processing circuit comprises a synchronization circuit  FIG9 shows an embodiment of the synchronization circuit of the digital processing circuit of FIG8
For example, FIG8 shows an embodiment of the processing circuit 208. Generally, the signals CS10, CS20 and CS30 may be provided at output as digital signals, e.g. via the communication interface 210. Conversely, in the embodiment shown in FIG8, the processing circuit 208 comprises three digital-to-analog converters 216 (and optionally respective driver circuits 218), in order to generate analog signal CS10, CS20 and CS30, each indicative of the amplitude of a respective phase current, wherein the analog signals CS10, CS20 and CS30 are provided to respective pins of the driver circuit 22a. In various embodiments, the number of output signals (CS10, CS20 and CS30) corresponds thus to the number of phases of the motor to be driven. Moreover, when using analog output signals, the number of digital-to-analog converters 216 (and respective driver circuits 218) corresponds to the number of output signals.  FIG9 shows an embodiment of the block of/the steps performed by the synchronization circuit 220. For example, FIG9 shows that the digital processing circuit 214 may comprise three hardware or software modules, wherein: Specifically, FIG9 shows the blocks of the synchronization circuit 220 configured to generate a single control signal T for one motor phase by monitoring a respective control signal IN (e.g. the control signal for the high side switch), and the same blocks may be repeated also for the other motor phases. Generally, in case of a fixed switching duration TPWM the value/signal CPWM may also be set, e.g. via the interface 210 (see also FIG9). In various embodiments, instead of monitoring a high side control signal (e.g. IN1, IN3 and IN5 for the example considered), each synchronization circuit 220 shown in FIG9 may monitor a low side control signals (e.g. IN2, IN4 and IN6 for the example considered).
embodiment
236
control circuit
210
interface
214
processing circuit
216
converters
218
respective driver circuits
230
digital comparator circuit comparators
8
equation
220
synchronization circuit synchronization circuits
208
circuit
206
differential amplifiers differential amplifier
228
circuit
232
counter
226
sample circuit
234
comparator comparators
224
counter counters
212
converter converters
['1. A half-bridge driver circuit (22a) comprising: - two input terminals for receiving a high side control signal ( IN 1 ) and a low side control signal ( IN 2 ), wherein said high side control signal ( IN 1 ) is a center aligned pulse-width-modulated signal having a given switching period ( T PWM ) and a given switch-on duration ( T ON ) ,  and said low side control signal ( IN 2 ) corresponds to an inverted version of said high side control signal ( IN 1 ) with a first delay ( T ONDT ) between a falling edge of said low side control signal ( IN 2 ) and a following rising edge of said high side control signal ( IN 1 ) and with a second delay ( T OFFDT ) between a falling edge of said high side control signal ( IN 1 ) and a following rising edge of said low side control signal ( IN 2 ); - two output terminals for providing a high side drive signal ( DRV 1 ) for a high side switch (SW 1 ) and a low side drive signal ( DRV 2 ) for a low side switch (SW 2 ) ; - a high side driver circuit (200 1 ) configured to generate said high side drive signal ( DRV 1 ) as a function of said high side control signal ( IN 1 ) ,  and a low side driver circuit (200 2 ) configured to generate said low side drive signal ( DRV 2 ) as a function of said low side control signal ( IN 2 ); - two measurement terminals ( CS1P, CS1N ) configured to be connected to the terminals of a shunt resistor (RS 1 ); and - an amplifier (206 1 ) configured to amplify the signal applied to said two measurement terminals ( CS1P, CS1N ) ,  thereby generating a measurement signal ( CS ) indicative of the current flowing through said shunt resistor (RS 1 ); wherein said half-bridge driver circuit (22a)  comprises: - an analog-to-digital converter (212); - a processing circuit (214) configured to selectively acquire a digital sample of said measurement signal ( CS ) via said analog-to-digital converter (212) in response to a trigger signal ( T1 ); - a synchronization circuit (220) configured to generate said trigger signal ( T1 ) by: - determining via a first digital counter (224) a first value ( C1 ) indicative of said switch-on duration ( T ON ) of said high side control signal ( IN 1 ) by monitoring the rising and falling edges either of said high side control signal ( IN 1 ) or of said low side control signal ( IN 1 ); - determining a second value ( CPWM ) indicative of said switching period ( T PWM ) of said high side control signal ( IN 1 ); - computing a third value  (C3)  indicative of the first count value ( CNT1 ) of said first digital counter (224) when a next switching period of said high side control signal ( IN 1 ) starts as a function of said first value ( C1 ) and said second value ( CPWM ); - comparing said third value ( C3 ) with said first count value ( CNT1 ) of said first digital counter (224), thereby generating a third signal ( ST ) when the next switching period of said high side control signal ( IN 1 ) starts; - starting a second digital counter (232) in response to said third signal ( ST ); - comparing the count value ( CNT2 ) of said second digital counter (232) with a reference value ( REF ), thereby generating a fourth signal ( T ); and - generating said trigger signal ( T1 ) as a  function of said fourth signal ( T ).', '5. The half-bridge driver circuit (22a) according to Claim 4, wherein said third value  (C3)  is computed  according to the following equation:  C 3 = C 1 + CPWM − C 1 − C ONDT + C OFFDT / 2  where C1 is said first value ( C1 ) , CPWM  is said second value ( C1 ) , C3  is said third value ( C3 ) ,  and  C ONDT  and  C OFFDT  are indicative of said first delay ( T ONDT ) and said second delay ( T OFFDT ) ,  respectively, wherein the value  C ONDT  and  C OFFDT  are preferably programmable via a communication interface (210) of said half-bridge driver circuit (22a).']