COMMUNICATION UNIT, INTEGRATED CIRCUIT AND METHOD FOR CLOCK DISTRIBUTION AND SYNCHRONIZATION
FIG5 illustrates an example diagram of a radar unit that cascades multiple chips in a Master Slave synchronization approach, according to example embodiments of the invention
Referring now to FIG5, an example block diagram of a communication unit 500 having a master-slave architecture is illustrated. In this example, the master-slave architecture is illustrated as a radar unit 505 that includes a master device 510 and one or multiple slave devices 520, 523. One slave device 520 is shown for clarity purposes only, with the potential for other similar slave devices shown as 523. The reference clocks are generated on master device 510 using the reference PLL clock signal (clk2) 582, tied to an external crystal oscillator 552, and sent to RFS modulator 560. Under, say, a SPI command from the MCU 414, the digital controller 516 of the master device 510 provides a chirp start (RFS_in) signal 580 to the RFS modulator circuit 560, which is configured to embed (e.g. encapsulates) the chirp start (RFS_in) signal 580 into the master-slave clock signal (clk2) 582 received from reference PLL 550. In this example, the embedded chirp start (RFS_in) signal 580 takes a form of differential master-slave clock signal (MS_clkdiff) 584, which is then used by all the master device(s) 510 and slave devices 520 of the system. In FIG5, the RFS modulator circuit 560 may be an LVDS transmitter and the differential master-slave clock signal (MS_clkdiff) 584 may take a form of an LVDS signal, MSclk n & MSclk_p. In a master device, at 1002, the master device (say master device 510 from FIG5) starts, for example when a signal is provided by XTAL inputs, a start master digital controller starts and, in some LDVS examples, a startup sequence causes a number of termination loads in the system to be determined such that a LVDS TX current can be set. At 1004, a reference PLL is started, such that a master-slave clock signal is sent to the RFS modulator. In some examples, this results in a LVDS TX_RX (clk2) signal being generated (from FIG5), such that the master-slave clock signal (MSclk_n, Msclk_p) is sent to each master device and slave device. In addition, in some examples, the master-slave clock signal is also sent to the MCU. Furthermore, in some examples, the master-slave clock signal is also sent to the main PLL (i.e. as clk1 from FIG5) inside the master device.
diagram
587
splitter
522
transmitter circuit
562
RFS modulator
598
single integrated circuit separate integrated circuits datavalidS
516
digital controller
512
transmitter circuit transmitter circuits
550
reference PLL
585
respective RFS master modulator
588
clock signal
532
flip-flop
580
signal
514
slave receiver circuits
500
communication unit
505
radar unit
564
demodulator demodulators
544
serial interface
526
digital controller
594
rfsSync_S
507
RF splitter
570
time engines
584
signal
515
LO_out path received high-frequency LO signal
560
circuit circuits
510
master device
518
LO_out path/pin
['1. A communication unit (400, 500) comprising: a plurality of cascaded devices that comprise at least one master device (510) and at least one slave device (520) configured in a master-slave arrangement; wherein the communication unit (400, 500) is  characterized in that : the at least one master device (510) comprises: a clock generation circuit configured to output a system clock signal; a modulator circuit (562) coupled to the clock generation circuit and configured to receive the system clock signal and a frame start signal and embed the frame start signal into the system clock signal to produce a modulated embedded master-slave clock signal (584); and transmit the modulated embedded master-slave clock signal (584) to the at least one slave device to synchronise the system clock signal and the frame start signal between the at least one master device (510) and at least one slave device (520).', '8. The communication unit (400, 500) of Claim 3 wherein the at least two complementary driver circuits are supplied with a current source (k*I, (1-k)*I) controlled by complementary bias voltages wherein the controlled complementary bias voltages are configured to provide embedded frame start amplitudes (Amax, Amin) on the modulated embedded master-slave clock signal (584) of an amplitude level that is expected by each RFS demodulator of a number of slave device(s) and master device(s).', '9. The communication unit (400, 500) of any of preceding Claims 6 to 8 wherein the RFS modulator 562 is terminated by a 100 ohms differential resistor (T).', '10. The communication unit (400, 500) of any preceding Claim wherein the at least one master device comprises a digital controller (516) coupled to the modulator circuit (565) and configured to re-sample a re-created frame start signal (rfs_outM 586) using the re-created system clock signal (585).', '11. The communication unit (400, 500) of any preceding Claim wherein the communication unit is a radar unit (400) and the frame start signal (590, 586) is a chirp start signal.']