TRANSMISSION WAVE BEAM DETERMINATION METHOD, TRANSMISSION END AND RECEPTION END
FIG14 is still yet another schematic view showing the receiving end device according to some embodiments of the present disclosure   FIG13 is yet another schematic view showing the transmitting end device according to some embodiments of the present disclosure
The present disclosure further provides in some embodiments a receiving end device which, as shown in FIG14, includes a processor 1400, a transceiver 1410, a memory 1420, a user interface 1430 and a bus interface. The processor 1400 is configured to read a program stored in the memory 1420, so as to: receive through the transceiver 1410 and measure beam training signals for N number of transmission beams from a transmitting end device, select Q number of transmission beams from the N number of transmission beams in accordance with a measurement result, and divide the Q number of transmission beams into G number of transmission beam groups, N, Q and G being each a positive integer; and transmit through the transceiver 1410 identification information about the Q number of transmission beams and group information about each transmission beam in the Q number of transmission beams to the transmitting end device, so as to enable the transmitting end device to determine that a signal is capable of being transmitted simultaneously to the receiving end device via transmission beams in the Q number of transmission beams belonging to different transmission beam groups. The transceiver 1410 is configured to receive and transmit data under the control of the processor 1400. In FIG14, bus architecture may include a number of buses and bridges connected to each other, so as to connect various circuits for one or more processors 1400 and one or more memories 1420. In addition, as is known in the art, the bus architecture may be used to connect any other circuits, such as a circuit for a peripheral device, a circuit for a voltage stabilizer and a power management circuit. The bus interface may be provided, and the transceiver 1410 may consist of a plurality of elements, i.e., a transmitter and a receiver for communication with any other devices over a transmission medium. With respect to different UEs, the user interface 1430 may also be provided for devices which are to be arranged inside or outside the UE, and these devices may include but not limited to a keypad, a display, a speaker, a microphone and a joystick. The processor 1400 may take charge of managing the bus architecture as well as general processings. The memory 1420 may store therein data for the operation of the processor 1400.  The present disclosure further provides in some embodiments a transmitting end device which, as shown in FIG13, includes a processor 1300, a transceiver 1310, a memory 1320, a user interface 1330 and a bus interface. The processor 1300 is configured to read a program stored in the memory 1320, so as to: transmit through the transceiver 1310 beam training signals for N number of transmission beams to a receiving end device, N being a positive integer; receive through the transceiver 1310 identification information about Q number of transmission beams in the N number of transmission beams and group information about each transmission beam in the Q number of transmission beams from the receiving end device, the Q number of transmission beams including G number of transmission beam groups, the G number of transmission beam groups being acquired by the receiving end device in accordance with a measurement result, the measurement result being a measurement result acquired after the receiving end device has received and measured the beam training signals from the transmitting end device, Q and G being each a positive integer; and determine that a signal is capable of being transmitted simultaneously to the receiving end device via transmission beams in the Q number of transmission beams belonging to different transmission beam groups. The transceiver 1310 is configured to receive and transmit data under the control of the processor 1300. In FIG13, bus architecture may include a number of buses and bridges connected to each other, so as to connect various circuits for one or more processors 1300 and one or more memories 1320. In addition, as is known in the art, the bus architecture may be used to connect any other circuits, such as a circuit for a peripheral device, a circuit for a voltage stabilizer and a power management circuit. The bus interface may be provided, and the transceiver 1310 may consist of a plurality of elements, i.e., a transmitter and a receiver for communication with any other devices over a transmission medium. With respect to different UEs, the user interface 1330 may also be provided for devices which are to be arranged inside or outside the UE, and these devices may include but not limited to a keypad, a display, a speaker, a microphone and a joystick. The processor 1300 may take charge of managing the bus architecture as well as general processings. The memory 1320 may store therein data for the operation of the processor 1300.
schematic view
1300
processor processors
14
andFIG.
1400
processor processors
1310
transceiver
1410
transceiver
1420
memory memories
['2. The transmission beam determination method according to claim 1, wherein the G number of transmission beam groups correspond to G number of transceiver unit groups of the receiving end device respectively.', '33. A transmitting end device, comprising a processor, a transceiver, a memory, a user interface and a bus interface, wherein the processor is configured to read a program stored in the memory, so as to implement the transmission beam determination method according to any one of claims 1 to']