PROCESSOR AND INSTRUCTION SCHEDULING METHOD
FIG13A is a schematic structural diagram of a processor according to another embodiment of this application
In an example, as shown in FIG13A, the processor 30 includes a decoding unit 31 and four processing units 32. The decoding unit 31 includes an instruction decoder 311 and X program counters 312. Each processing unit 32 includes a data path 321 and X groups of data registers 322. Each group of data registers 322 includes at least one data register. Quantities of data registers included in different groups of data registers 322 may be the same or may be different.
schematic structural diagram
30
processor
3
PC
2
decoding result
4
is
31
decoding unit
32
processing unit processing units
['1. A processor, wherein the processor supports X-channel interleaved multi-threading IMT, the processor comprises a decoding unit and a processing unit, and X is an integer greater than 1; the decoding unit is configured to: obtain one instruction from each of Z predefined threads in each cyclic period, decode the Z obtained instructions to obtain Z decoding results, and send the Z decoding results to the processing unit, wherein each cyclic period comprises X sending periods, one decoding result is sent to the processing unit in each sending period, a decoding result of the Z decoding results may be repeatedly sent by the decoding unit in a plurality of sending periods, 1 ≤ Z < X or Z = X, and Z is an integer; and the processing unit is configured to execute the instruction based on the decoding result.']