ARRAY SUBSTRATE, DISPLAY SCREEN, AND ELECTRONIC DEVICE
FIG14 is a schematic structural diagram illustrating partial structure of the array substrate of FIG13
The display circuit layer 32 includes the gate 3231 of the TFT 323, the gate insulation layer 326, the semiconductor layer 3234 of the TFT 323, the first end 3232 of the TFT 323, the second end 3233 of the TFT 323, and the first planarization layer 325. The display circuit layer 32 further includes the data line 322 coupled with the first end 3232 of the TFT 323 and the gate line 321 (not illustrated in FIG14) coupled with the gate 3231 of the TFT 323. The recognition circuit layer 33 includes the cathode 3312 of the photoelectric sensor 331, the photosensitive layer 3313 of the photoelectric sensor 331, and the anode 3311 of the photoelectric sensor 331. The recognition circuit layer 33 further includes the multiple output wires 333. The multiple output wires 333 are coupled with the cathodes 3312 of the multiple photoelectric sensors 331 respectively. The display circuit layer 32 further includes the multiple input wires 332 (not illustrated in FIG14). The multiple input wires 332 are coupled with the anodes 3311 of the multiple photoelectric sensors 331 respectively.
schematic structural diagram
331
photoelectric sensors photoelectric sensor
3234
semiconductor layer
3231
gate
3232
first end
3312
cathodes cathode
325
first planarization layer
323
TFT
3313
photosensitive layer photosensitive layers
334
insulation layer
326
gate insulation layer
31
first base material
3233
second end second ends
3311
anodes anode
33
recognition circuit layer
3
array substrate
322
multiple data lines
333
multiple output wires
32
display circuit layer
['1. An array substrate (3), comprising a first base material (31), and a display circuit layer (32) and a recognition circuit layer (33) laminated on the first base material; the display circuit layer comprising a plurality of gate lines (321), a plurality of data lines (322), and a plurality of thin-film transistors, TFT (323), projections of the plurality of gate lines on the first base material and projections of the plurality of data lines on the first base material defining a plurality of sub-pixel projection areas (320), and each of projections of the plurality of TFTs on the first base material falling into a corresponding area of the plurality of sub-pixel projection areas; and the recognition circuit layer comprising a plurality of photoelectric sensors (331), projections of the plurality of photoelectric sensors on the first base material falling into a corresponding area of the sub-pixel projection areas, and the photoelectric sensor being configured to sense target lights carrying user fingerprint information.', '3. The array substrate of claim 2, wherein each of the plurality of photoelectric sensors comprises a cathode (3312), a photosensitive layer (3313), and an anode (3311) sequentially laminated, and wherein the cathode is located on one side of the photosensitive layer towards the first base material; and the anode is located on one side of the photosensitive layer away from the cathode, and the anode is made of a transparent conductive material.', '7. The array substrate of claim 6, wherein the cathodes of the plurality of photoelectric sensors are located on one side of the first planarization layer away from the first base material, and wherein the recognition circuit layer further comprises an insulation layer (326), the insulation layer is located on the one side of the first planarization layer away from the first base material and covers the cathodes of the plurality of photoelectric sensors, the insulation layer has a plurality of second through-holes (3341) and a plurality of third through-holes (3342), the plurality of second through-holes are aligned with the cathodes of the plurality of photoelectric sensors respectively, and the plurality of third through-holes communicate with the plurality of first through-holes respectively; the photosensitive layers of the plurality of photoelectric sensors are partially or wholly filled in the plurality of second through-holes respectively and are in contact with the cathodes of the plurality of photoelectric sensors; the anodes of the plurality of photoelectric sensors are located on one side of the insulation layer away from the first planarization layer and covers the photosensitive layers of the plurality of photoelectric sensors respectively; and the plurality of pixel electrodes are located on the one side of the insulation layer away from the first planarization layer and are coupled to the plurality of TFTs via the plurality of third through-holes and the plurality of first through-holes respectively.']