DOWNLINK CONTROL CHANNEL DETECTION METHOD, TERMINAL, AND BASE STATION
FIG5 is a schematic diagram illustrating modules of a base station, in accordance with an embodiment of the present disclosure  FIG6 is a block diagram of a base station, in accordance with an embodiment of the present disclosure 
As shown in FIG5, in the embodiment of the present disclosure, the base station 500 may implement the functions of the fifth and sixth embodiments as follows: the base station allocates a corresponding downlink control channel for a terminal; the base station transmits the first auxiliary information to the terminal, based on time-domain duration of a control resource set of the downlink control channel; the base station transmits second auxiliary information to the terminal, based on resource mapping mode from REG of control resource set to CCE, and achieves the same effects. Specifically, the base station 500 includes the following functional modules:  To better achieve foregoing objectives, as shown in FIG6, the fourth embodiment of the present disclosure further provides a base station. The base station includes a processor 600; a memory 620 coupled with the processor 600 via a bus interface, a transceiver 610 coupled with the processor 600 via a bus interface. The memory 620 is configured to store program and data, which may be used when the processor performs operations. The transceiver 610 may be configured to transmit data information or pilots, and receive an uplink control channel. Specifically, when the processor 600 calls and executes programs and data in the memory 620, the processor 600 is configured to read programs from the memory 620, and implements the following functions: allocates a corresponding downlink control channel for a terminal. In FIG6, the bus architecture may include any index of interconnected buses and bridges. Specifically, one or more processors demonstrated with processor 600 are coupled with various circuits of memory, which is demonstrated with memory 620. The bus architecture may also link various other circuits, such as, peripherals, voltage regulators, and power management circuits, as is known in the art. Thus, in the application, no further description is provided. The bus interface provides an interface. The transceiver 610 may be composed of multiple components, that is, including a transmitter and a receiver, which provide a unit for communicating with various other devices via the transmitting medium. The processor 600 is in charge of managing bus architecture and general processing. The memory 620 may store data used when the processor 600 performs operations.
block diagram, schematic diagram
620
memory
600
processor
500
base station
530
second transmitting module
610
transceiver
510
allocating module
520
first transmitting module
['39. A Base Station (BS), comprising: an allocating module, configured to allocate a corresponding downlink control channel for a terminal; a first transmitting module, configured to transmit first auxiliary information to the terminal, based on a time-domain duration of a Control Resource Set (CORESET) of the downlink control channel; and, a second transmitting module, configured to transmit second auxiliary information to the terminal, based on a resource mapping mode from a Resource Element Group (REG) of the control resource set to a Control Channel Element (CCE).', '43. A terminal, comprising a processor, a memory, and a computer program stored in the memory, wherein the computer program is executable by the processor, when the computer program is executed by the processor, the processor is caused to perform a downlink control channel detection method according to any of claims 1 to']