SHIFT REGISTER, DRIVING METHOD THEREFOR, GATE DRIVER DEVICE, AND DISPLAY DEVICE
FIG5 is an exemplary block diagram of a gate drive device according to an embodiment of the present disclosure
FIG5 illustrates an exemplary block diagram of a gate drive device 500 according to an embodiment of the present disclosure. The gate drive device 500 includes a plurality of cascaded shift registers 100 as mentioned above. An input terminal STV of a first-stage shift register is inputted with a scan enable signal. An input terminal STV of each of the shift registers at stages other than the first stage is coupled to a third output terminal OUTPUT_N of a previous-stage shift register, the first clock signal terminal CLK1 of each of the shift registers at stages other than the first stage is coupled to a second clock signal terminal CLK2 of the previous-stage shift register, and the second clock signal terminal CLK2 of each of the shift registers at stages other than the first stage is coupled to the first clock signal terminal CLK1 of the previous-stage shift register. As shown in FIG5, in the first-stage shift register, an input terminal STV is inputted with a scan enable signal. The first clock signal terminal CLK1 is coupled to a first clock signal Clock1. The second clock signal terminal CLK2 is coupled to a second clock signal Clock2. A first output signal OUTPUT_L_1 is outputted from the first output terminal OUTPUT_L. A second output signal OUTPUT_R_1 is outputted from the second output terminal OUTPUT_R. A third output signal 0UTPUT_N_1 is outputted from the third output terminal OUTPUT_N.
exemplary block diagram
500
gate drive device
['12. A gate drive device comprising a plurality of cascaded shift registers according to any one of claims 1-8; wherein an input terminal of a first-stage shift register is inputted with a scan enable signal; and an input terminal of each of the shift registers at stages other than the first stage is coupled to a third output terminal of a previous-stage shift register, the first clock signal terminal of each of the shift registers at stages other than the first stage is coupled to a second clock signal terminal of the previous-stage shift register, and the second clock signal terminal of each of the shift registers at stages other than the first stage is coupled to the first clock signal terminal of the previous-stage shift register.']