INTELLIGENT TRANSPORT SYSTEM TECHNOLOGY CO-EXISTENCE METHOD AND ARRANGEMENT
FIG6 is a schematic drawing of parts of yet another embodiment of a node for communication within a cooperative intelligent transport system  FIG8 is a schematic drawing of an embodiment of a road side unit comprising a node for communication within a cooperative intelligent transport system
FIG6 is a schematic block diagram illustrating yet another example of a node 100 for communication within a cooperative intelligent transport system, based on combination of both processor(s) 310-1, 310-2 and hardware circuitry 330-1, 330-2 in connection with suitable memory unit(s) 320. The node 100 comprises one or more processors 310-1, 310-2, memory 320 including storage for software and data, and one or more units of hardware circuitry 330-1, 330-2 such as ASICs and/or FPGAs. The overall functionality is thus partitioned between programmed software (SW) for execution on one or more processors 310-1, 310-2, and one or more pre-configured or possibly reconfigurable hardware circuits 330-1, 330-2 such as ASICs and/or FPGAs. The actual hardware-software partitioning can be decided by a system designer based on a number of factors including processing speed, cost of implementation and other requirements.  FIG8 is a schematic block diagram illustrating an example of a road side unit 20 comprising a node 100 according to any of the embodiments. With reference to the different embodiments mentioned above, either of, or both, of the node receiving the first ITS message and the node transmitting the first ITS message may be a road side unit.
schematic
100
node
320
memory
20
RSUs
40
OBU
['3. The node according to claim 2,  characterised in that  said node comprises a processor (110) and a memory (120), said memory (120) comprising instructions executable by the processor (110), whereby the processor is operative to identify said technology status of said another node.']