METHOD AND DEVICE FOR DETERMINING PREAMBLE SEQUENCE OF PHYSICAL RANDOM ACCESS CHANNEL
FIG5 is a schematic structural diagram of a network-side device according to some embodiments of the application 
FIG5 is a schematic structural diagram of a network-side device according to embodiments of the application, and as illustrated, the device includes: Here in FIG5, the bus architecture can include any number of any number of interconnecting buses and bridges to particularly link together various circuits including one or more processors represented by the processor 500, and one or more memories represented by the memory 520. The bus architecture can further link together various other circuits, e.g., a peripheral device, a manostat, a power management circuit, etc., all of which are well known in the art, so a further description thereof will be omitted in this context. The bus interface serves as an interface. The transceiver 510 can be a number of elements, e.g., a transmitter and a receiver, which are units for communication with various other devices over a transmission medium. The processor 500 is responsible for managing the bus architecture and performing normal processes, and the memory 520 can store data for use by the processor 500 in performing the operations.
schematic structural diagram
402
anda sequence determining module
500
processor
510
transceiver
401
520
memory
['11. A device for determining a preamble sequence on a Physical Random Access Channel (PRACH), the device comprising: a processor configured to read and execute program in a memory to: determine instances of time at which respective preamble sub-sequences are detected in a detection window; and determine preamble sub-sequences belonging to a same preamble sequence according to the  instances of time at which the respective preamble sub-sequences are detected in a current stage, and the instances of time at which the respective preamble sub-sequences are detected in a previous stage; and a transceiver configured to transmit and receive data under the control of the processor is configured to: receive the respective preamble sub-sequences in the previous stage; and receive the respective preamble sub-sequences in the current stage.']