ARRAY BASED FORWARD ERROR CORRECTION FOR OPTICAL TRANSMISSION
FIG1C is a block diagram of an illustrative receiver in the illustrative optical communication system of FIG1A
FIG1C is a block diagram illustrating components of example receiver 106 of optical communication system 100. As shown, receiver 106 comprises optical interface 122, demodulator circuitry 124, deinterleaver circuitry 126, FEC decoder circuitry 128, and output interface 130. Optical interface 122 is configured to receive data transmitted over optical link 106. The demodulator circuitry 124 is configured to demodulate data received over optical link 106. The demodulated data is provided to deinterleaver circuitry 126, which is configured to reverse or undo the re-arrangement of the data performed by the interleaver 116. The FEC decoder circuitry 128 is configured to decode the de-interleaved data and provide the decoded data to output interface 130.
block diagram
24
embodiment
128
FEC decoder circuitry
116
interleaver circuitry
130
output interface
126
deinterleaver circuitry
20
embodiment
118
modulator circuitry
0
between
102
data
115
memory
124
demodulator circuitry
106
link
114
encoder circuitry
['1. An apparatus for performing forward error correction of data to be transmitted over an optical communications channel, the apparatus comprising: an input interface; a preprocessor comprising circuitry coupled to the input interface and configured to: organize data bits received from the input interface into an arrangement having a plurality of blocks organized into rows and columns, the plurality of blocks further organized into a plurality of strands of blocks including a first strand of blocks, the first strand of blocks comprising: a back portion comprising a first row of the plurality of blocks, and a front portion comprising blocks from at least two different columns in at least two different rows other than the first row of blocks; and an encoder comprising circuitry configured to encode at least some of the data bits in the arrangement using a first error correcting code at least in part by: accessing first data bits in the front portion of the first strand of blocks; accessing second data bits in the back portion of the first strand of blocks; and generating first parity bits by applying the first error correcting code to the first data bits and the second data bits.', '12. The apparatus of one of claims 1 to 11, further comprising a memory configured to store the arrangement.']