ICE: a scalable, low-cost FPGA-based telescope signal processing and
  networking system
  We present an overview of the 'ICE' hardware and software framework that
implements large arrays of interconnected FPGA-based data acquisition, signal
processing and networking nodes economically. The system was conceived for
application to radio, millimeter and sub-millimeter telescope readout systems
that have requirements beyond typical off-the-shelf processing systems, such as
careful control of interference signals produced by the digital electronics,
and clocking of all elements in the system from a single precise
observatory-derived oscillator. A new generation of telescopes operating at
these frequency bands and designed with a vastly increased emphasis on digital
signal processing to support their detector multiplexing technology or
high-bandwidth correlators---data rates exceeding a terabyte per second---are
becoming common. The ICE system is built around a custom FPGA motherboard that
makes use of an Xilinx Kintex-7 FPGA and ARM-based co-processor. The system is
specialized for specific applications through software, firmware, and custom
mezzanine daughter boards that interface to the FPGA through the
industry-standard FMC specifications. For high density applications, the
motherboards are packaged in 16-slot crates with ICE backplanes that implement
a low-cost passive full-mesh network between the motherboards in a crate, allow
high bandwidth interconnection between crates, and enable data offload to a
computer cluster. A Python-based control software library automatically detects
and operates the hardware in the array. Examples of specific telescope
applications of the ICE framework are presented, namely the
frequency-multiplexed bolometer readout systems used for the SPT and Simons
Array and the digitizer, F-engine, and networking engine for the CHIME and
HIRAX radio interferometers.
