Architecture of 60 GHz OFDM Baseband Transmitter
For the development of the 60 GHz OFDM baseband processor, first a complete MATLAB model was developed. The simulation of different realizations of the wireless channel is the basis for the parameter optimization. Subsequently the MATLAB model was converted into a VHDL code and implemented on a high-performance FPGA platform. The block diagram shows the structure of the developed baseband transmitter. A 32-bit-wide data bus with a clock frequency of 125 MHz is used to stream data from the MAC. After buffering und scrambling, data is passed to the Reed Solomon encoder or a second buffer stage, which synchronizes the data to the 200 MHz clock domain. The same buffer is used for the signal field, which is generated in parallel and not RS-encoded. The next module is the convolutional coder. To reach the maximum throughput of 4 Gbps, data is processed with up to 24 parallel encoding streams. This is due to the implemented Viterbi decoder, which operates at a clock frequency of 200 MHz, providing a data throughput of 200 Mbps per stream. The system uses a single memory-based block interleaver, providing a throughput of 6.4 Gbps with 200 MHz clocking. Up to here, the data interfaces between the modules are always 32-bit wide. After interleaving, the data is reformatted to form 8 streams with 1-4 bit depending on the modulation scheme. Eight parallel mappers are used. Within the pilot insertion stage, mapped data symbols are transferred to the 270 MHz clock domain. A cyclic prefix is added by the IFFT module and the computed OFDM symbol is output to the DACs. The preamble is pre-calculated during implementation time and stored in a memory. This is accessible from MAC-layer through a memory-mapped interface and therefore configurable.