he National Science Foundation through the following awards:
Papers and Theses on the Hardware Mechanisms Investigated To Date ...
Performance, Energy, and Memory-Subsystem ModelingWith embedded processor technology moving towards faster and smaller processors and systems on a chip, it becomes increasingly difficult to accurately evaluate real-time performance and power consumption. This research describes an evaluation method using an embedded architecture software emulator that models several embedded microprocessor architectures, including the Motorola M-CORE, the Texas Instruments C6000 DSP, and the Digital/Intel StrongARM.
Details can be found in the following papers and student theses:
Highly Integrated, Heterogeneous Systems-on-Chip
(note: this section is cross-listed with the Circuit Integrity page)It is clear from the decades-long trends of miniaturization and integration that future systems-on-chip will combine all technologies currently found in modern embedded systems -- including digital, analog and MEMS components. We are working to develop interfaces, models, and basic understanding to make this integration possible. Current (published) work focuses on integrating digital signal processing with MEMS sensors, and developing high-level power models for (digital) SoC components such as cores, memories, I/O controllers, and busses. Other work includes topologies and protocols for networks-on-chip and related issues in circuit integrity.
Details can be found in the following papers:
Issues in Digital Signal Processors
Flexibility in Hardware Implementation of VLIW DSPsExtended Split-Issue is a technique that enables a designer of VLIW microprocessors (examples of VLIW processors include Intel's Itanium processor; Transmeta's Crusoe; and most high-end digital signal processors, such as those from Texas Instruments, Motorola, Analog Devices, and Agere Systems) to overcome the most significant drawback of VLIW architectures--namely, that of cross-compatibility--without sacrificing performance.
The term 'VLIW' stands for 'very long instruction word' and refers to a class of processor architectures popular in modern energy-efficient yet high-performance systems. VLIW architectures take much of the dynamic decision-making logic out of hardware and move it instead into the compiler. The degree to which VLIW specifies the required hardware sets it apart from other architectures and enables the development of high-performance processors that are efficient in their die area and power consumption, relative to other architecture means of achieving high performance. The trade-off is that code written for a VLIW processor cannot easily be run on another VLIW processor with a different hardware configuration. Among other things, this sharply limits the designer's ability to offer multiple processor implementations--for instance, to offer multiple designs at different cost-performance price points such as a DSP with one hardware multiplier, or two hardware multipliers, or none at all using software emulation. Such cross-compatibility enabled the long-lived success of both IBM's System/360 and Intel's x86 architecture families.
The Extended Split-Issue mechanism can be applied to any processor design that uses VLIW, especially "NUAL" VLIWs, in which the compiler has intimate knowledge of the processor pipeline organization. The mechanism allows any hardware implementation to emulate the configuration expected by the compiler, thereby providing cross-compatibility between dissimilar processor implementations. By enabling VLIW code to run on any processor implementation, even if that implementation is not compatible with the code, Extended Split-Issue provides de facto cross-compatibility in the VLIW domain, thus solving a problem that has been open since VLIW was introduced three decades ago.
Details can be found in the following papers:
Memory Systems for Digital Signal ProcessorsToday's digital signal processors (DSPs), unlike general-purpose processors, use a non-uniform addressing model in which the primary components of the