pped I/O
I/O mapped I/O – in this technique memory device and I/O devices are arranged separately. Read and write lines are also separate for read and write operation. (Refer to Figure 4.4).
Figure 4.4: I/O Mapped I/O
Commands are of four types and they are as follows:
Control – It is used to activated the I/O devices and instruct the device about action to be performed.
Test – It used to test various status conditions related to the I/O devices.
Read – It is the command which instruct I/O module to obtain data from I/O device and place it in an internal buffer.
Write – It is the command which instruct ` module to take data from data bus and subsequently transfer it to the I/O device.
Figure 4.5: Flowchart for Programmed I/O
4.4.2 Interrupt ââ‚¬” Driven I/O
The problem with programmed I/O is that CPU has to wait for long time, till instruction gets executed. An alternative is for the CPU to issue an I/O command to a module and then go to do the some other useful work; the I/O module will interrupt the CPU to request service when it is ready to execute the data. (Refer to Figure 4.6). This technique improved performance of the CPU of skipping CPU waiting time till the I/O operation performs.
Figure 4.6: Interrupt Driven I/O
4.4.3 Direct Memory Access (DMA)
DMA uses special I/O CPU that take control of an I/O operation to move large block of data. This technique adds additional module on system bus.
When CPU needs to read or write data, it issues command to the DMA module, by sending following information:
Whether a read and write is requested, using read, or write control line between the CPU and DMA module.
The address of I/O module involved, communicated on the data line.
The starting location is in memory to read from or write to, communicated on the lines and stored by the DMA module in its address registers.
The number of words to be read or written, again communicated via the data lines and stored in the data count register. The CPU then continues with other work.
DMA Data Transfer Modes
There are three typed of data transfer modes and they are as follows:
Block Transfer Mode – In this transfer mode DMA controller takes control of system bus through system bus. It transfers blocks of data. This system is used in very high speed secondary memory and latest microprocessors. While data is transferring CPU does some internal operation that does not require system bus interaction.
Cycle Stealing – In this case instead of transferring entire block of data, it transfers only word by word. DMA forces CPU to pause running operation for a short time. Cycle is stole only when CPU is using some work that does not require system bus.
Interleaved – Interleaved is same as block transfer modem, only difference is it takes control of system bus, when CPU is not using it.
There are two types of configuration and they are as follows: In first type, it allows DMA, I/O and all types of modules to share the same system bus. In the second type, direct path should be established between the DMA and I/O module without any intervention of the system bus.
4.5 Intel 8237A DMA Controller
The Intel 8237A DMA controller interfaces to 8086 CPU family (Refer to Figure ââ‚¬¦.). Configuration of Intel 8237A is as follows:
Four Independent I/O channels.
27 registers, out of these seven are for system wide registers and five for each I/O channel.
Out of five registers, four are 16 bit and one is 6 bits. They are as follows:
6 bit is mode register
DMA based address
DMA current address
DMA operation will flow from following steps and they are as follows:
The peripheral device will request for the service, so DREQ (DMA Request) line will be activated.
The DMA will put high on its HRQ (Hold Request), signaling the CPU through its HOLD pin that it needs to use the buses.
CPU will finish the present bus cycle and respond to the DMA request by putting high on its HDLA (hold acknowledge), thus telling the 8237 DMA that it can go ahead and use the bus performs its task. HOLD must remain active high as long as DMA performing task.
DMA will activate DACK (DMA ack