IW' stands for 'very long instruction word' and refers to a class of processor architectures popular in modern energy-efficient yet high-performance systems. VLIW architectures take much of the dynamic decision-making logic out of hardware and move it instead into the compiler. The degree to which VLIW specifies the required hardware sets it apart from other architectures and enables the development of high-performance processors that are efficient in their die area and power consumption, relative to other architecture means of achieving high performance. The trade-off is that code written for a VLIW processor cannot easily be run on another VLIW processor with a different hardware configuration. Among other things, this sharply limits the designer's ability to offer multiple processor implementations--for instance, to offer multiple designs at different cost-performance price points such as a DSP with one hardware multiplier, or two hardware multipliers, or none at all using software emulation. Such cross-compatibility enabled the long-lived success of both IBM's System/360 and Intel's x86 architecture families.
The Extended Split-Issue mechanism can be applied to any processor design that uses VLIW, especially "NUAL" VLIWs, in which the compiler has intimate knowledge of the processor pipeline organization. The mechanism allows any hardware implementation to emulate the configuration expected by the compiler, thereby providing cross-compatibility between dissimilar processor implementations. By enabling VLIW code to run on any processor implementation, even if that implementation is not compatible with the code, Extended Split-Issue provides de facto cross-compatibility in the VLIW domain, thus solving a problem that has been open since VLIW was introduced three decades ago.
Details can be found in the following papers:
Memory Systems for Digital Signal ProcessorsToday's digital signal processors (DSPs), unlike general-purpose processors, use a non-uniform addressing model in which the primary components of the memory system--the DRAM and dual tagless SRAMs--are referenced through completely separate segments of the address space. The recent trend of programming DSPs in high-level languages instead of assembly code has exposed this memory model as a potential weakness, as the model makes for a poor compiler target. In many of today's high-performance DSPs this non-uniform model is being replaced by a uniform model--a transparent organization like that of most general-purpose systems, in which all memory structures share the same address space as the DRAM system.
In such an architecture, one must replace the DSP's traditional tagless SRAMs with something resembling a general-purpose cache. This study investigates an alternative on-chip data cache design for a high-performance DSP, the Texas Instruments 'C6000 VLIW DSP. Rather than simply adding tags to the large on-chip SRAM structure, we take advantage of the relatively regular memory access behavior of most DSP applications and replace the tagless SRAM with a near-traditional cache that uses a very small number of wide blocks. We find that one can achieve nearly the same performance as a tagless SRAM while using a much smaller footprint.
Details can be found in the following paper:
Low-Power Embedded SystemsThis study presents the modeling of embedded systems with SimBed, an execution-driven simulation testbed that measures the execution behavior and power consumption of embedded applications and RTOSs by executing them on an accurate architectural model of a microcontroller with simulated real-time stimuli. We briefly describe the simulation environment and present a study that compares three RTOSs: uC/OS-II, a popular public-domain embedded real-time operating system; Echidna, a sophisticated, industrial-strength (commercial) RTOS; and NOS, a bare-bones multi-rate task scheduler reminiscent of typical "roll-your-own" RTOSs found in many commercial embedded systems. The microcontroller simulated in this study is the Motorola M-CORE processor: a low-power, 32-bit CPU 