ould be better. The consumer S/PDIF interface, with a 75-ohm ±5% impedance spec, is probably acceptable.
Once the transmitter/transport and the receiver have the proper impedance, the cable needs to be impedance-matched. While several companies have recently introduced mechanically superb and financially extravagant cables, impedance matching in itself does not need to be expensive. The television industry has been producing impedance-matched cables and connectors for use up to 900MHz; even good-quality cables are reasonably priced. While shielding of AES transmission pairs is a good idea, the isolation requirements are well below that of analog cables. Hence, two digital transmission cables with the same characteristic impedance will have the same effect on the jitter, whether they cost $3 or $300.
It's clear that jitter performance of an AES/EBU or S/PDIF transmission link is highly dependent on hardware implementation. This includes the transmitter (a CD transport), the interface cable, and the input receiver in the digital processor. Of the three, the receiver is, at least conceptually, clearly the most difficult one to design and manufacture. Although a low-jitter transmitter and interface isn't, in theory, that difficult to design, bad cables and transmitters/transports abound in the real world.
Measuring transport & interface jitter
The designer of low-jitter circuits faces a great obstacle: the lack of commercially available instruments for measuring jitter. Without a way of measuring jitter, how can we know how our transmitters, interfaces, and input receivers are performing? The solution is to design and build your own jitter analyzer. This is, however, no small task; many pitfalls await the courageous adventurer.
Clock jitter can be measured in three ways, each with its advantages and disadvantages. First, we can measure jitter using a reference clock running at a different frequency from the clock we want to measure. This is the method used in reciprocal counters. The reference clock is compared to the measured clock. To be of any use, the counter must resolve time within a reference clock period. The instrument's quality is based on the accuracy of this time resolution. Moreover, crosstalk between the reference and measured clocks must be avoided. This method will work with non-periodic signals such as those carried by the AES/EBU or S/PDIF interface signal.
Another method uses a reference clock running at the same frequency as the measured clock. This technique can measure the jitter degradation caused by a circuit, or measure the intrinsic jitter and jitter attenuation characteristics of a phase-locked loop (PLL) such as is found in input receiver circuits. The recovered clock is compared to the reference clock with a relatively simple circuit. The reference clock must be of extraordinary accuracy. UltraAnalog uses this technique to measure the performance of its low-jitter AES 20 input receiver.
Finally, clock jitter can be measured with a low-jitter PLL. The incoming clock is sent to a PLL with very low intrinsic jitter and a very low jitter attenuation cutoff frequency. The low-jitter clock is compared with the incoming clock; a simple circuit separates the jitter component in the incoming clock and outputs the jitter in analog form.
The PLL's jitter attenuation cutoff frequency must be very low. Below the attenuation cutoff frequency, the PLL follows the incoming clock and its jitter, passing the incoming jitter to the recovered clock. The recovered clock will thus have the same jitter as the incoming clock; no measurement can be made by comparing the two clocks. By replacing the simple phase comparator described in the second method with a more sophisticated cascaded track-and-hold circuit, this technique can measure non-periodic signals such as the digital interface signal.
This is the method used in the custom jitter analysis instrument built by UltraAnalog, shown in block form in fig.7. An AES/EBU or S/PDIF signal is input to the analyzer, and the analyzer's output is the jitter component of the me