d of data transfer modes and they are as follows:
Block Transfer Mode – In this transfer mode DMA controller takes control of system bus through system bus. It transfers blocks of data. This system is used in very high speed secondary memory and latest microprocessors. While data is transferring CPU does some internal operation that does not require system bus interaction.
Cycle Stealing – In this case instead of transferring entire block of data, it transfers only word by word. DMA forces CPU to pause running operation for a short time. Cycle is stole only when CPU is using some work that does not require system bus.
Interleaved – Interleaved is same as block transfer modem, only difference is it takes control of system bus, when CPU is not using it.
There are two types of configuration and they are as follows: In first type, it allows DMA, I/O and all types of modules to share the same system bus. In the second type, direct path should be established between the DMA and I/O module without any intervention of the system bus.
4.5 Intel 8237A DMA Controller
The Intel 8237A DMA controller interfaces to 8086 CPU family (Refer to Figure ââ‚¬¦.). Configuration of Intel 8237A is as follows:
Four Independent I/O channels.
27 registers, out of these seven are for system wide registers and five for each I/O channel.
Out of five registers, four are 16 bit and one is 6 bits. They are as follows:
6 bit is mode register
DMA based address
DMA current address
DMA operation will flow from following steps and they are as follows:
The peripheral device will request for the service, so DREQ (DMA Request) line will be activated.
The DMA will put high on its HRQ (Hold Request), signaling the CPU through its HOLD pin that it needs to use the buses.
CPU will finish the present bus cycle and respond to the DMA request by putting high on its HDLA (hold acknowledge), thus telling the 8237 DMA that it can go ahead and use the bus performs its task. HOLD must remain active high as long as DMA performing task.
DMA will activate DACK (DMA acknowledge), which tell the peripheral device that it will start to transfer the data.
DMA starts to transfer the data from memory to peripheral by putting the address of the first byte of the block on the address bus and activating MEMR, thereby reading the byte from memory into the data bus; it then activate IOW to write it to the peripheral. The DMA decrements the counter and increments the address pointer and repeats this process until the count reaches and task is finished.
After the DMA has finished its job, it will deactivate HRQ, signaling the CU that it can regain control over its buses.
4.6 Chapter Review Questions
Which of the following are I/O techniques?
Ans: A and C
Which the following line is used to identify location of I/O device?
Which of the following components are included in I/O device interface?
Ans: B and C
The system bus consists of _______________.
Ans: A, B and C
Which of the following is not function of I/O module?
Providing time and control signals
Communicating with CPU
Communication with I/O devices
None of these
The peripheral device will request for the service, which generated______ signal.
None of these
Intel 8237A DMA Controller consists of ______ I/O channels.
Which of the following DMA mode stops CPU from accessing system bus?
Block Transfer Mode
None of these
Intel 8237A DMA Controller consists of ____ number of registers?
10. MMU stands for ——————–
Memory Mixture unit
Memory Management Unit
Memory measurement Unit
None of these
2. A and C
In the chapter, I/O Organisation, you learnt about:
I/O modules and its function.
I/O module structure.
Different types of I/O techniques.
Intel 8237A DMA Controller..
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