ctions in an embedded system, thus maximizing the performance and predictability of real-time applications. This project is targeted to design and build a simulator, a prototype processor, and an experimental RTOS to demonstrate these claims.
Our research goal is to improve the performance, predictability, energy consumption, and reliability of embedded systems at little to no increase in cost. Our prior investigations in RTOS technology and processor architectures have led us to several orthogonal hardware mechanisms that one can add to any processor architecture, either microcontroller or DSP. These mechanisms enable an RTOS to provide a virtual machine environment in an embedded system with near-zero overhead.
We have performed initial measurements of the effectiveness of our scheme; we have built a complete embedded-system simulator that simulates both the embedded microcontroller and the RTOS. This enables us to gather a large amount of information on the behavior of real-time systems and allows us to measure the effect of changes to the system architecture that require modifications to both hardware and software. Other measurement techniques do not allow such flexibility; software simulators that execute applications directly on an emulated processor neglect operating system activity, and systems that attach logic probes to real hardware obtain accurate measurements but do not allow modifications to the processor architecture.
Need for Experimentation
This type of research requires experimental software systems. One cannot obtain these measurements without actually building prototype systems; the variables are so numerous and their interactions so complex that realistic mathematical analysis is incredibly difficult, and when the system is simplified to the point that the analysis is feasible, the results are no longer realistic. Accurate simulation of systems is the preferred method for obtaining measurements of low-level behavior where the operating system meets the hardware.
This project is supported by the National Science Foundation through the following awards:
Papers and Theses on the Hardware Mechanisms Investigated To Date ...
Performance, Energy, and Memory-Subsystem ModelingWith embedded processor technology moving towards faster and smaller processors and systems on a chip, it becomes increasingly difficult to accurately evaluate real-time performance and power consumption. This research describes an evaluation method using an embedded architecture software emulator that models several embedded microprocessor architectures, including the Motorola M-CORE, the Texas Instruments C6000 DSP, and the Digital/Intel StrongARM.
Details can be found in the following papers and student theses:
Highly Integrated, Heterogeneous Systems-on-Chip
(note: this section is cross-listed with the Circuit Integrity page)It is clear from the decades-long trends of miniaturization and integration that future systems-on-chip will combine all technologies currently found in modern embedded systems -- including digital, analog and MEMS components. We are working to develop interfaces, models, and basic understanding to make this integration possible. Current (published) work focuses on integrating digital signal processing with MEMS sensors, and developing high-level power models for (digital) SoC components such as cores, memories, I/O controllers, and busses. Other work includes topologies and protocols for networks-on-chip and related issues in circuit integrity.
Details can be found in the following papers:
Issues in Digital Signal Processors
Flexibility in Hardware Implementation of VLIW DSPsExtended Split-Issue is a technique that enables a designer of VLIW microprocessors (examples of VLIW processors include Intel's Itanium processor; Transmeta's Crusoe; and most high-end digital signal processors, such as those from Texas Instruments, Motorola, Analog Devices, and Agere Systems) to overcome the most significant drawback of VLIW architectures--namely, that of cross-compatibility--without sacrificing performance.
The term 'VL