At the International Solid State Circuits Conference today, IBM, Sony, and Toshiba took the wraps off their long-awaited Cell processor. Back in 2001, the three companies decided to form an alliance to create the processor that would power the upcoming Sony PlayStation 3. Last year, they let it be known that the Cell would have other uses, such as powering new workstations.
Our CPU Editor Jon "Hannibal" Stokes was on hand for the presentation today and took copious notes. The result is a two-part series on the architecture of the Cell processor. Part I covers the SIMD processing units that handle much of the processor's workload in usual Hannibal style, with plenty of diagrams to illustrate how IBM has addressed the problems of proximity communication with the Cell.
The Cell processor consists of a general-purpose POWERPC processor core connected to eight special-purpose DSP cores. These DSP cores, which IBM calls "synergistic processing elements" (SPE), but I'm going to call "SIMD processing elements" (SPE) because "synergy" is a dumb word, are really the heart of the entire Cell concept. IBM introduced the basic architecture of the SPE today, and they're going to introduce the overall architecture of the complete Cell system in a session tomorrow morning.
The Cell looks impressive: nine processor cores with clock speeds starting at 4GHz. It can process 256 billion calculations per second, and has 234 million transistors fabbed on a 90nm process. Plans call for a switch to a 65nm process by year end. Test production of the processors will begin later in the year, and the final versions will appear not only in the PS3 early next year, but also in high-end graphics and animation workstations. Dig in to Hannibal's coverage!