Jitter & the Digital Interface Page 3
Moreover, calculations show that jitter caused by interface band-limiting is correlated with the signal. In fact, frequency analysis, both theoretical and measured on equipment, shows the jitter spectrum to exhibit lines corresponding to the signal frequency and to interference or beating between the signal and the sampling frequency. These beat frequencies themselves modulate the signal frequency inside the converter to produce artifacts. For example, a 4kHz signal causes a jitter spectral line at 100Hz by beating with the 44.1kHz sampling frequency. The 100Hz component in turn causes jitter at 3.9kHz and 4.1kHz to appear on the reconstructed signal's spectrum (footnote 7).
This somewhat simplistic demonstration of the generation of jitter by bandwidth limitations is intended more to give a physical understanding of the problem than to yield an exact numerical value. For a more refined computation, one must know which digital interface signal edges actually contribute to the jitter, and which do not. The Crystal CS8412 and the UltraAnalog AES 20 receivers, for instance, use only half of the edges to regenerate the master clock. The Yamaha YM3623B receiver uses only the edges located in that portion of the signal called the preamble. The definition of digital interface jitter must then be modified to exclude the edges ignored by the receiver.
Another great contributor to interface jitter is the mismatch between transmission cable and receiver impedance. A 10' cable represents a round-trip delay of about 30ns (30,000ps), and any impedance mismatch adds an attenuated echo signal with the same 30ns delay. It doesn't take three pages of math to realize that this causes quite a mess. In that respect, one may regret the loose impedance (110 ohms ±20%) specification recommended by the AES/EBU standard. Equipment manufacturers should attempt to be as close to 110 ohms impedance as possible for their transports, processors, cables, etc. A tolerance of 5% is a good starting point; 3% would be better. The consumer S/PDIF interface, with a 75-ohm ±5% impedance spec, is probably acceptable.
Once the transmitter/transport and the receiver have the proper impedance, the cable needs to be impedance-matched. While several companies have recently introduced mechanically superb and financially extravagant cables, impedance matching in itself does not need to be expensive. The television industry has been producing impedance-matched cables and connectors for use up to 900MHz; even good-quality cables are reasonably priced. While shielding of AES transmission pairs is a good idea, the isolation requirements are well below that of analog cables. Hence, two digital transmission cables with the same characteristic impedance will have the same effect on the jitter, whether they cost $3 or $300.
It's clear that jitter performance of an AES/EBU or S/PDIF transmission link is highly dependent on hardware implementation. This includes the transmitter (a CD transport), the interface cable, and the input receiver in the digital processor. Of the three, the receiver is, at least conceptually, clearly the most difficult one to design and manufacture. Although a low-jitter transmitter and interface isn't, in theory, that difficult to design, bad cables and transmitters/transports abound in the real world.
Measuring transport & interface jitter
The designer of low-jitter circuits faces a great obstacle: the lack of commercially available instruments for measuring jitter. Without a way of measuring jitter, how can we know how our transmitters, interfaces, and input receivers are performing? The solution is to design and build your own jitter analyzer. This is, however, no small task; many pitfalls await the courageous adventurer.
Clock jitter can be measured in three ways, each with its advantages and disadvantages. First, we can measure jitter using a reference clock running at a different frequency from the clock we want to measure. This is the method used in reciprocal counters. The reference clock is compared to th