To keep througput close to 1/cycle when there is a multi-cycle stage that sends a command to a far module then gets answer(10 clocks per send or receive), could separating it in two(send + receive) and putting idle stages(18x1 clocks) between them solve the problem? For example, with just a single stage that takes 20 clocks, it has throughput of 0.05 instructions per cycle. When idle stages are added, incoming instructions should randezvous with incoming answers from distant module at last stage and it should keep throughput at 1 instruction per cycle. So answer is received from bottom stage instead of same stage of sending. Is there a more elegant way than this? I'm writing a cpu-design and simulation game that drag-n-dropped-connected modules communicate and pass instructions from fetch to retire, but they all have multiple layers of communications that slow throughput and I need to keep a high throughput without giving simplicity away(for gamers) and doing it right (idle stages are right or not?)If a pipeline stage is a combinatorial logic, than it could have communication with other circuits than its own(not just flowing data to next stage)(fetch wired to memory controller/cache, decode wired to decoder instead of accepting decoder module as a whole pipeline stage)
Pipeline depth with idle stages
cpu pipelines