Why are instruction decoding and register read are combined in single stage of a 5-stage MIPS-pipeline, even though they serve two different operation?
Why Instruction Decode and Register Read are in the same stage of MIPS pipeline
computer architecture;cpu pipelines
Instruction Decode and Register Read are done in parallel on that stage in order to prevent needing to wait on either to complete.  There's no reason not to do this since they are both known at that point in time for the MIPS-Pipeline, and since they will most likely be needed for the next step (Execution Cycle).By no reason, I mean that you would effectively be using more power while separating them (as mentioned in the comments below).  You would also be adding a whole extra stage in that case, as the stage before (Instruction Fetch) is what actually gets the information for ID and RR, and adding it to the stage after would not work because that stage requires both.  Thus the only way to do it would be to add the stage in-between the ID stage and EX stage, which would add a whole extra cycle to every operation, which would obviously result in slow downs overall.If you're interested in reading more about this, I'd recommend this textbook I'm using for a class (Computer Architecture: A Quantitative Approach by John Hennessy and David Patterson).  It's got a pretty handy reference for MIPS especially from what I've read so far and it's where I pulled this information from.