In Vol. 1 Issue 1, Jan. 1958 of the magazine Communications of the ACM, Dr. Saul Gorn discusses the advantages of the computer architecture of Edvac to that of Eniac.He states that the Edvac had a three-plus-one address word structure, and that the tendencies of his time period were to use one-address hardware and three-plus-zero address pseudo-codes. He then goes on to say that for the future he imagines using variable instruction-word-length machines.My questions: What is a three-plus-one address word structure? What is a one-address hardware and three-plus-zero address pseudo code? What do these terms mean exactly? I understand what a word is, but not to an extent that would allow me to understand these terms contextually.Link to this issue of CACM: here. I believe an ACM membership is required to access the magazine. This question refers to Dr. Saul Gorn's Letter to the Editor.
Address Word Structure
computer architecture
The EDVAC employed a 44 bit word with a 4 bit op code and 4 10 bit address fields.While the use of the fields varied a lot, the ADD instruction was typical. The memory location in field 1 was added to the memory location in field 2 and the result placed into the memory location in field 3. Execution of code then continued at the location addressed by field 4.Thus we can summarize C = A + B; GOTO DAs for simulation with pseudo codes, we can deduce that for the Accumulator + One address machines popular at the time, the C = A + B would be simulated with three instructions and the GOTO part would be omitted. Thus three-plus-zero. It might look something like (stylized not actual code):; ADD A,B,CLD Acc, AADD Acc, BST Acc, CFor more on EDVAC please see:https://babel.hathitrust.org/cgi/pt?id=mdp.39015002095639;view=1up;seq=87