In modern computer architecture, pipeline has stage that access memory for normal data and instruction in parallel.But datas and instructions are usually in same memory, and their access address is different.But how pipelined cpu can access them in parallel? Are the memory has   two address port for read data and instruction respectively?If they are in separate memory, they can be accessed simultaneously. But what if there are only one memory for them? one of them is just stalled?
how one memory can be accessed simultaneously in instruction fetch and data read?
computer architecture;memory hardware;cpu pipelines