I have attached the problem belowConsider a 512-KByte cache with 64-word cachelines (a cacheline is also known as a cache block, each word is 4-Bytes). This cache uses write-back scheme, and the address is 32 bitswide.Let's try to start doing the first row. To find the Cachline index, I would have to know the number of cachelines in the cache. I don't know that. The problem doesn't provide any information about the cache that is being used. It's going to be a Miss since at the beginning the cache is empty. It wasn't modified because the request is to read. For the tag, I would have to know what's the bit size of the address , but in this case it's in hex. What's data?. what is caused replace? what is write-back to Memory?. It would be nice if someone can do the first two rows for me and go through every step in this process. I would do the other ones. I would like the first two rows to be done because there are two different types of request, read and write. I need orientation. It would be good as well if someone can point out the resources to understand this question.Thanks!!!I have updated the threadIn previous computations, I got that cache offset is 8 bits, cache index is 11 bits and the tag is 13 bits. I converted 0x128 to binary and got 0b100101000. This implies that the cacheline index is 1. The requested address is 0x28 and the tag is 0x0, however; I still can't understand what data, caused replace and write-back to memoery means.
Direct Mapped, Cache Transactions
computer architecture;cpu cache