LOOP:LW    R1,0(R2)     ADDI  R1,R1,#1     SW    R1,0(R2)     ADDI  R2,R2,#4     SUB   R4,R3,R2     BNEZ  R4, LOOPIf we want to move an instruction into a branch delay slot what will be that instruction and the schedule of the instructions?In the solution they have brought SW R1,0(R2) into the branch delay slot like this:LOOP:LW    R1,0(R2)     ADDI  R2,R2,#4     SUB   R4,R3,R2     ADDI  R1,R1,#1     BNEZ  R4, LOOP     SW    R1,0(R2)But according to me it will change the meaning of the program since R2 will be incremented by 4 before storing the word. Can anyone clear this?
Computer architecture pipelining
computer architecture;cpu pipelines