What I am doing:I've been reading there about front-side busses (FSB) and their cycles per second (MHz) vs. bandwidth (Millions of Transactions per second or MT/s).What I've understood:FSB's MHz is the actual speed it does per cycle, however, the speed per second depends on how many cycles it does per secondWhat I need:Can we by some way say that the CPU multiplier amount is the same amount of cycles it does per second that we can tell that if the FSB is 800MHz and the multiplier is x4, it's capable of transferring up to *(800*4)MT/s*?Why I assumed that?Because of Wikipedia telling me that: In computing, the clock multiplier (or CPU multiplier or bus/core ratio) measures the ratio of an internal CPU clock rate to the externally supplied clock. A CPU with a 10x multiplier will thus see 10 internal cycles (produced by PLL-based frequency multiplier circuitry) for every external clock cycle
Is the front-side bus multiplier the same as how many transfers it does per second?
computer architecture
No.  You're not cancelling your units correctly.The wikipedia article is talking about something else.  (The cycles/sec of the front-side bus vs. the cycles/sec of the processor.)The Transfers (or Transactions) per second is given by:$$ \frac{\mathrm{Transactions}}{\mathrm{cycle}} \times \frac{\mathrm{cycles}}{\mathrm{second}} = \frac{\mathrm{Transactions}}{\mathrm{second}}.  $$MHz is millions of cycles per second (cycles/second), not speed per cycle.The calculation you do in your section what I need. is correct:  If the front-side bus is running at 800 million cycles/sec, and can do 4 transfers per cycle, then it can do 800M * 4 = 3200M transfers/second.