Basically, and as an simple method, we can access cache with Physical Address which is from the TLB.But, as an another method, we can access cache with Virtual Address. But, in this case, if the cache is not fully flushed between context switch(other process's datas can be exist in cahce), there is an aliasing problem. Same memory can be directed from the different virtual address.But in my text book, including these problem, many can be solved by virtually indexed physically tagged. I think this still can make an aliasing problem.Am I wrong?
cache virtually indexed physically tagged
computer architecture;cpu cache