I'm trying to understand in a general sense how L1/L2 (and now L3 caches) are updated and how the updates are propagated in a multi-core x86/x86-64 CPU to the other cores and eventually RAM.Assuming an 4 core CPU and 2 pairs of L1/L2 caches, where pairs of cores share a common L1/L2 pair and there's an interconnect between the 2 L1/L2 pairs. And the cache lines are 64-bit wide.So we have:Core-0/Core-1 on (L1/L2)-0Core-2/Core-3 on (L1/L2)-1(L1/L2)-0 is connected to (L1/L2)-1Let's say there is a thread T0 running on Core-0 that is writing to a 64-bit integer variable called X, and there's another thread T1 on Core-3 continually reading variable X's value - Please ignore the logical race conditions for a moment.Question:Assuming X has been cached in Core-0's L1. When T0 writes a new value to X, Is the following sequence of events correct?X's value is pushed from register to L1-0X's value is pushed from L1-0 to L2-0X's value is pushed from L2-0 to L2-1X's value is pushed from L2-1 to L1-1X's value is pushed from L1-0 to RAMNote: Steps 2 and 4 may happen concurrently.
Understanding memory update propagation in x86/x86-64 CPU L1/L2/L3 caches and RAM
architecture;memory;caching;cpu