I'm a bit new to the practical use of memristors in general, but I'm starting to see it as a (3D stacked) grid of components that could be treated as transistors or flip-flops on demand (which may be completely wrong, I'm not sure). It seems like the usual Von Neumann architecture wouldn't be ideal at all (of course you could emulate it, but it doesn't seem like a good idea). Does anyone know of any models that are better suited? I'm trying to get my brain to move past a model that would create variable cores that scale with size as the program runs in the memristive space (I've been poisoned by the current models) and more of one where the core and memory is combined (no independent TLB/cache/RAM).Edit: As to what I mean by memristive grid -- So, lets say you have a 3 dimensional hypercube with nodes at each discrete x,y,z coordinate. Each one of these nodes is addressable. When you address a node, you can tell it to become a bit of memory or a gate (just like an FPGA gate). After you tell all of the nodes what they are, you can then perform computation in the hypercube using the landscape of memory and gates that you designed. It's kinda like a processor with bits of memory sitting right next to the transistors, but you can reconfigure it as you go (under a nanosecond for each reconfiguration), possibly after each instruction that you execute in the landscape.Edit: One of the things that got me interested in thinking about this problem is the idea that you can calculate Hilbert integers for a space filling curve and transpose the hypercube into a linear space using reflected binary codes -- it might lead into some interesting memory arrangements when you try to optimize the clustering of memristive memory and computation.
What is the the optimal computational model for memristive style CMOS?
computability;machine models