Electrical property comparison and charge transmission in p-type double gate and single gate junctionless accumulation transistor fabricated by AFM nanolithography
1 Department of Physics, Faculty of Science, Universiti Putra Malaysia, Serdang, Selangor 43400, Malaysia
2 School of Materials and Mineral Resources Engineering, Universiti Sains Malaysia, Nibong Tebal, Penang, 14300, Malaysia
3 Functional Devices Laboratory, Institute of Advanced Technology, Universiti Putra Malaysia, Serdang, Selangor 43400, Malaysia
4 Department of Chemistry, Islamic Azad University, Behbahan Branch University Street, Behbahan, 6361713198, Iran
Nanoscale Research Letters 2012, 7:381 doi:10.1186/1556-276X-7-381Published: 11 July 2012
The junctionless nanowire transistor is a promising alternative for a new generation of nanotransistors. In this letter the atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer. The etching process was developed and optimized in the present work compared to our previous works. The output, transfer characteristics and drain conductance of both structures were compared. The trend for both devices found to be the same but differences in subthreshold swing, ‘on/off’ ratio, and threshold voltage were observed. The devices are ‘on’ state when performing as the pinch off devices. The positive gate voltage shows pinch off effect, while the negative gate voltage was unable to make a significant effect on drain current. The charge transmission in devices is also investigated in simple model according to a junctionless transistor principal.