Copper Pillar Technology and Challenges
Instructor: John Briar
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|Course Dates | Location||Cost||Pay Via Credit Card|
|December 16-17, 2013 (Mon.-Tues.) | Penang, Malaysia||$1,295||Add To Shopping Cart|
|Pay Via Purchase Order/Check|
|Please fax the printable registration form for public courses to (505) 858-9813 to Complete Your Order.|
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Refund Policy: If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.
The drive to reduce costs in semiconductor and integrated circuits remains a key challenge for the industry. For example, many of today’s ICs use expensive gold wiring. As a result, the industry is pushing to use copper wires and copper pillar bumping in an increasing array of applications. This has created a number of challenges related to the bonding and packaging of these components. Copper Pillar Technology and Challenges is a 2-day course that offers detailed instruction on the technology issues associated with today’s semiconductor packages. We place special emphasis on current issues like bond formation, bumping, and package design and manufacturing processes. This course is a must for every manager, engineer, and technician working in semiconductor packaging, using semiconductor components in high performance applications or non-standard packaging configurations, or supplying packaging tools to the industry.
By focusing on current issues in packaging technology, participants will learn why advances in the industry are occurring along certain lines and not others. Our instructors work hard to explain semiconductor packaging without delving heavily into the complex physics and materials science that normally accompany this discipline.
What Will I Learn By Taking This Class?
Participants learn basic but powerful aspects about the semiconductor packaging. This skill-building series is divided into four segments:
- Basic Semiconductor Copper Pillar Bumping Metallurgy: Participants will study the manufacturing techniques used to create these packages.
- Wafer Design Rules and Pillar Design: The course presents design concepts needed at the wafer and package level to ensure a successful package design. The Back-End-of-Line (BEOL) materials interact with the copper pillar and the copper pillar interacts with the package substrate. These interfaces need to be properly designed to ensure a reliable, cost-effective solution.
- Common Package Types: Participants will learn about the various package types on which on can use copper pillar bumping. This includes both molded packages like Ball Grid Arrays and Quad Flat No-Lead packages, as well as direct chip attach packages such as chip scale packages and package-on-package configurations.
- Reliability and Environmental Tests: The last part of the class brings together the basic principles and selected alloy systems to analyze the results of reliability testing, interpret the observed failure modes to identify root causes, and predict behavior for materials or process changes implemented to lower costs and/or improve reliability. The course covers moisture tests, thermomechanical tests, electromigration, and failure analysis methodology.
- At the end of the course, participants will understand the various types of copper pillar bumping techniques and technologies.
- They will also know about the manufacturing techniques involved in creating these packages.
- Participants should be able to predict and identify potential reliability problems and the environmental testing that can identify and bring these problems to the surface. They should also know how to interpret failure analysis results.
- Participants will gain methods to apply these principles to process and material changes to lower cost and produce increased reliability for IC packaging.
- Participants will be able to make decisions about how to construct and evaluate new packaging designs and technologies.
- The participant will see several case studies associated with Copper Pillar Bumping.
- Copper Pillar Metallurgy
- Types and advantages/disadvantages (This would include copper pillar solder bumping, thermal copper pillar bumping, and thin-film thermoelectric technologies)
- Reliability considerations (This would include a discussion on FIT rates, the Arrhenius equation, HAST testing for copper oxidation and degration, voltage-bias tests, autoclave tests, temperature cycling, electromigration, and failure analysis techniques)
- Cost considerations (This would include a discussion on material costs, processing costs, impacts on package size, die size, interposer technologies, and other factors that affect the cost)
- Wafer design rules and pillar design
- Coplanarity (This includes a discussion of wafer flatness, and the techniques necessary to maintain flatness with the assembly/bumping equipment)
- Shapes and sizes (This includes factors like copper pillar height, total height, row-to-row pitch, bond pad width, trace pitch, etc.)
- Common package types and cost
- BGA, Leaded packages (QFN, etc.)
- Direct chip attach (This includes chip scale packages, and package-on-package configurations like bare die, molded, flip chip, and flip stack technologies)
- Package reliability
- Underfill (This includes a discussion on both reworkable and non-reworkable underfills. It also includes a discussion on flex tests and drop tests)
- Overmold, glob top (This includes a discussion on selection of appropriate polymers/thermosets for chip protection)
- Case Studies
By using a combination of instruction by lecture, classroom exercises, and question/answer sessions, participants will learn practical information on semiconductor packaging and the operation of this industry. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. We use instructors who are internationally recognized experts in their fields that have years of experience (both current and relevant) in this field.
More than twenty years experience in electronics and manufacturing with duties including, President, Chief Technologist, and Director of Engineering focusing on new product, new process, and new market development in the area of Integrated Circuit (IC) packaging and test.
Part of the core start-up team that established the world leading IC packaging factories at STATS/Chippac in Singapore, Amkor Electronics in the Philippines, and Amkor/Anam Electronics in Korea.
Direct hands on development of all types of IC packaging technologies including wafer RDL and bumping, WLCSP, flip chip packaging, LGA/BGA large die stack packages with up to 16 die, and multiple die stack leadframe packages.
Wrote and awarded numerous U.S., Singapore, and other international patents and inventions relating to IC packaging. Published and presented a variety of technical papers worldwide and recognized expert in packaging.