val all_slots_assoc_comp (#vcfg:_) (ssm: slot_state_map vcfg) (ss: seq (slot_id vcfg))
  : b:bool{b <==> all_slots_assoc ssm ss}
val all_slots_assoc_comp (#vcfg:_) (ssm: slot_state_map vcfg) (ss: seq (slot_id vcfg))
  : b:bool{b <==> all_slots_assoc ssm ss}
let all_slots_assoc_comp (#vcfg:_) (ssm: slot_state_map vcfg) (ss: seq (slot_id vcfg))
  : b:bool{b <==> all_slots_assoc ssm ss}
  = not (exists_elems_with_prop_comp (fun s -> not (is_assoc ssm s)) ss)
module Zeta.Intermediate.Logs

open FStar.Classical
open Zeta.SeqIdx
/
Zeta.SeqIdx.fsti.checked prims.fst.checked FStar.Pervasives.fsti.checked FStar.Classical.Sugar.fsti.checked FStar.Classical.fsti.checked
Zeta.Intermediate.Logs.fst

    ssm: Zeta.Intermediate.SlotKeyRel.slot_state_map vcfg ->
    ss: FStar.Seq.Base.seq (Zeta.Intermediate.VerifierConfig.slot_id vcfg)
  -> b: Prims.bool{b <==> Zeta.Intermediate.Logs.all_slots_assoc ssm ss}
Zeta.Intermediate.VerifierConfig.verifier_config Zeta.Intermediate.SlotKeyRel.slot_state_map FStar.Seq.Base.seq Zeta.Intermediate.VerifierConfig.slot_id Prims.op_Negation Zeta.SeqIdx.exists_elems_with_prop_comp Zeta.Intermediate.SlotKeyRel.is_assoc Prims.bool Prims.l_iff Prims.b2t Zeta.Intermediate.Logs.all_slots_assoc
let all_slots_assoc_comp (#vcfg: _) (ssm: slot_state_map vcfg) (ss: seq (slot_id vcfg))
    : b: bool{b <==> all_slots_assoc ssm ss} =
  
not (exists_elems_with_prop_comp (fun s -> not (is_assoc ssm s)) ss)