Logic Designer - Auto
The Logic Design/Synthesis Auto tool (SYN) automatically designs, minimizes and simulates digital logic functions and state machines. The size of a circuit that can be synthesized is relatively small compared to the circuits that can simulated in the Logic Design Draw and Logic Simulator tools.
SYN will start to search for a circuit solution of any size, but because the number of circuit permutations grows exponentially as a function of the number of parts and the number of part inputs, the time to find a large-circuit solution may take hours, days, or years.
The number of permutations is reduced by numerous filters within Logic Design Auto, some of which depend on user input. Refer to Section 3 "Part Defaults - Faster Solutions", and Section 4 "Options".
The Input Specification window contains the Design Specification for the logic or state machine. Data can be typed in, pasted, loaded from a file (File/Open or Examples menus), or a file can be dragged-and-dropped onto the Input window. File data must be in standard ASCII text format.
There are two modes of operation - Hardware (HW) and Software (SW). While both modes perform functional simulations of candidate circuits, the HW mode performs additional timing checks including flip-flop setup/hold times, race conditions and spike/glitch detection which are generally not applicable to software solutions.
Output formats include Boolean equations, gate-level logic schematics, truth tables and timing diagrams.
All logic types and configurations are supported:
Automatic Design - SYN searches for one or more digital circuits that provide the transfer function specified by the input/output signal waveforms. In general, the first circuit solution found will be the simplest solution possible.
Because of this, SYN provides both automated design and minimization. For example, if the truth table of a Boolean equation is specified as an input to SYN, the first solution found will be the minimized form of the Boolean equation.
CAUTION: Except for very simple
Boolean expressions, SYN is much slower than the Boolean Equation tool
(BEQ) since the SYN search time increases exponentially with the number
of variables and the number of parts. In general BEQ should be
used for large combinational functions.
SYN has been optimized for its default and-or PARTS; other gate types, such as nand or nor, generally take much more time to find solutions.
Simulation - Simulates each logic circuit and displays its functional operation including the effects of glitches and flip-flop setup/hold violations.
Design & Simulation features:
- 10 part types: and, or, nand, nor, xor, xnor logic gates and D flip-flops
- 2 to 10 inputs per logic gate
- Flip-flop state initialization
- Optional spike/glitch filters
- 0 1 x r f logic states
- clock/data signal types
Minimization - Refer to the Overview (Help menu) for a comparison of Boolean (BEQ) vs. Logic Design Auto/Synthesis (SYN) minimization
The following example is from file "2-input AND Default.txt" which can be loaded using the SYN Examples menu:
A 0101; 'input #1
B 0011; 'input #2
C 0001; 'circuit output
A and B are inputs, C is the output signal that the circuit must generate. C is specified as the logical 'AND' of A and B.
Circuit synthesis is started by clicking the "Go" button.
The circuit found is shown in the Output Circuits / Timing window if Logic Circuit is checked.
Similarly, the corresponding Boolean equation is displayed in the Output Circuits / Timing window if Boolean Eqn is checked.
The truth table or waveform of the circuit is also shown unless the Timing Format is "Off".
The files in the Examples\Synthesis directory demonstrate the flexibility of SYN as well as usage of its Advanced Options. For example:
"Adder with OR2.txt" generates a fairly large (14 part) combinational circuit.
"DFF Edge-Triggered.txt" synthesizes an edge-triggered D-flip-flop using Nand gates.
"Serial Input 32-bit.txt" illustrates a relatively complex sequential circuit specification.
ADVANCED FEATURES and OPTIONS
1. INPUT SPECIFICATION SECTIONS
There are four sections of a Design Specification, three of which are optional.
|IN_OUT_SIGNALS||Required - A list of the Input signals & the Output signal. The Output signal must be last in the list. At least one item, the output signal, must be specified.|
|PARTS||Optional - Part types to be tried during the design synthesis|
|OPTIONS||Optional - Used to control and/or speed up the design synthesis|
|END_OF_SPEC||Optional - Indicates the end of the design specification|
The Input Specification can also contain comments. Refer to the COMMENTS section below for comment syntax.
2. INPUT SPECIFICATION - IN_OUT_SIGNALS
This section specifies the truth table or waveforms of the function to be synthesized. One or more input signals (signal name and truth table/waveform) are followed by an output signal. Each name-truth table/waveform pair must be terminated with a semi-colon ";"
Names can be any word from 1-32 characters long with the following exceptions:
a. SIM/SYN section names (IN_OUT_SIGNALS, PARTS, NETLIST, OPTIONS, END_OF_SPEC) are not allowed as signal names.
b. Names consisting only of numbers, such as "123", are not allowed; this avoids Signal Name and Netlist number confusion.
c. The following characters not allowed in a name: space tab ; : " or character(s) beginning a comment: // -- ' # .
Name Groups - Input Signals Only
An Input signal name group can be used to generate from 1 to 4 numbered names and bit-patterns. The logic states of the bit-patterns must be specified in hexadecimal format, that is characters 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F (decimal values of 0-15).
Name groups are defined by adding "(n:m)" to the end of the input-signal name, where 'n' is the starting bit and 'm' is the last bit of the group.
A(0:3) 4 D A 3 1 0;
This will generate signals A(0), A(1), A(2), A(3), each with unique logic 0/1 bit patterns.
Note that the smallest group number, A(0), is the least-significant hexadecimal bit; and that only Logic 0, Logic 1 and Logic x states are supported. If an 'x' is specified, all four signals will be an 'x' for that bit/tic time.
If the Timing Format "Expand Hex" box is checked, the Output display will show the four signals separately:
A(0) 0 1 0 1 1 0;
A(1) 0 0 1 1 0 0;
A(2) 1 1 0 0 0 0;
A(3) 0 1 1 0 0 0;
Example file "Decode IR.txt" can be run as an example of a Name Group and Hexadecimal bit patterns.
Combinational vs. Sequential logic
Synthesis results normally include a line that says "COMBINATIONAL logic" or "SEQUENTIAL logic". If the input signals and the comparison word/output signal indicate that memory (D flip-flops or gate latches) is needed in the circuit, "SEQUENTIAL logic" is displayed. If memory is not required, "COMBINATIONAL logic" is displayed which means that D flip-flops and gate latches are not needed. For example:
Input 1 0 0 0 ;
Input 2 0 1 1 ;
Comparison word 0 1 0 ;
Since the second and third input pairs are identical (0 1, 0 1) but the comparison word result is different (1, 0), a combinational solution is not possible and memory is required ("SEQUENTIAL logic").
Note that if the comparison word has no '1's or '0's, the digital logic type cannot be determined and the "COMBINATIONAL logic / SEQUENTIAL logic" display is inhibited.
Logic States - Signals
(9) logic states are supported for un-grouped signals/comparison words. The following table lists two or more characters that represent each state:
|Logic 0||0 _||logic 0|
|Logic 1||1 =||logic 1|
|Logic X||x X|| Input Signal: unknown (0 or 1)
Comparison Word: Don't care
|Rising||r R /||logic 0 to logic 1 transition|
|Falling||f F \||logic 1 to logic 0 transition|
|Spike High||h H||glitch/spike high: logic 0 to 1 to 0|
|Spike Low||l L||glitch/spike low: logic 1 to 0 to 1|
|Spike Unknown||u U||glitch/spike unknown: (high or low)|
|Oscillation||o O ~||logic 0/1 oscillation|
The following rising/falling sequences are NOT allowed: 0f, 1r, xr, xf, rx, fx, rf, fr. In addition, a signal waveform cannot begin or end with 'r' or 'f'.
Logic States - Signal Groups
For Input-signal Groups, logic states are specified in Hexadecimal (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F) or an 'x'/'X" for don't care bits. R/F/H/L/U/O states are not supported.
If the Expand Hex option is checked, Input-signal Groups are shown as Logic 0/1/x's.
|Logic 0/1/x||0-F, X||Grouped logic 0/1/x's|
|Logic 0||0 _||Expand - logic 0|
|Logic 1||1 =||Expand - logic 1|
|Logic X||x||Expand - Input Signal: unknown (0 or 1)|
For a clock-type signal (signal:clk), only Logic 0 and Logic 1 states are allowed.
Input Signal Types - data clk
signal:data can connect to any pin EXCEPT a flip-flop clock pin
signal:clk can ONLY connect to a flip-flop clock pin
Note: These types are not applicable to the Output signal
When Timing waveforms are displayed in the Output Circuits/Timing window, the Signal Probe box is also displayed.
By clicking on any signal waveform in the Output section, the logic state of the signal is shown on a tic-by-tic basis. All states are supported: 0, 1, x (unkown), rising, falling, oscillation, etc.
For signal groups - such as A(0:3) - the hexadecimal value is converted to decimal. If a group has more than 4 bits - such as A(0:3) A(4:7) - the decimal value of the entire group - A(0:7) - is calculated.
If the entire group is negative (the most-significant bit - A(7) - is a '1') for a signed-number application, both the positive unsigned value and negative signed values are displayed. Refer to the following example:
| Decimal |
|1||19||37||122||140 [-116]||175 [-81]|
NOTE: If more than one circuit solution is generated, the Signal Probe is only active for the waveform of the last solution.
3. INPUT SPECIFICATION - PARTS
This section is optional.
There are 10 primitive part types supported
Logic gates: inv and or xor nand nor xnor
D flip-flops: dff dff_c dff_cp
The inv (inverter) parts have (1) input while and, or, xor, nand, nor, xnor gates have (2) inputs.
The and, or, xor, nand, nor, xnor gates can also have from 3 to 10 inputs by appending the number of inputs to the part name - for example, and3, or4, nand5, nor10.
The dff is a D flip-flop with only a D and Clock input. The dff_c is a dff plus a /Clear input. The dff_cp is a dff plus /Clear and /Preset inputs.
Although dff_cp has additional functionality (both preset and clear), it is NOT recommended for most Synthesis applications. This is because dff_cp parts take much longer to synthesize than dff_c parts, which in turn take much longer to synthesize than dff parts.
Refer to Logic Parts Data for part descriptions and function tables.
Part Defaults - Faster Solutions
If the PARTS section is excluded or specifies no parts, the default parts assigned are inv, and, or, dff.
- dff will be assigned only for sequential designs.
- inv parts are always assigned unless specified as "inv=0".
The default parts assigned by SYN will be selected to minimize the time to find one or more solutions. For Combinational or Synchronous logic, and-or parts are generally much faster that nand, nor, xor or xnor. For Sequential logic, dff parts are faster than dff_c or dff_cp parts.
Part quantities can be specified to constrain the design. For example, to limit the design to a maximum of two dff parts, specify dff=0-2 or dff<3 or dff=2. In general, the last format (dff=2) is NOT recommended since any solution with just (1) dff will be missed. That is, it is recommended to start at 0 or to use the "<" operator.
4. INPUT SPECIFICATION - OPTIONS
This section is optional. If this section is excluded or specifies no options, the default options (indicated below with *) are used.
OPTIONS can be used to control the output of SYN. For example:
SOLUTION_First stops synthesis after the first solution is found
WAVEFORM_0 is equivalent to Timing Format Off
OPTIONS can also be used to control and in some cases reduce the synthesis time.
FF_ALL_SYNC causes all D flip-flops to be clocked by :clk type signals. This also means that :clk type signals can only connect to clock (C) inputs of D flip-flops which generally reduces the time to find solutions.
Combinational or Sequential Options
|NO_AND_OR_Order1||and-gates and or-gates can interconnect in any order|
|NO_GLITches2||HW mode - All signals in the circuit solution must be glitch-free|
|SW mode - Not applicable|
|NO_OUTPUT_GLITch||HW mode - The Output signal of the circuit must be glitch-free|
|SW mode - Not applicable|
|SOLUTION_First||Stop search after finding the FIRST solution|
|SOLUTION_Simple||Find only the SIMPLEST solution(s) for each set of parts|
|SOLUTION_Equiv||Same as SOLUTION_Simple with an additional number of parts (such as inv) allowed|
|SOLUTION_All||Find ALL solutions (limit of 10)|
|WAVEFORM_0||Timing Format Off|
|WAVEFORM_1||Timing Format 01x|
|WAVEFORM_2||Timing Format _=x|
|WAVEFORM_33||Timing Format Graphic|
Sequential (memory) Options
|FF_2IN_SYNC||2-input D flip-flop parts are clocked by a :clk signal|
|FF_3IN_SYNC||3-input D flip-flop parts are clocked by a :clk signal|
|FF_4IN_SYNC||4-input D flip-flop parts are clocked by a :clk signal|
|FF_ALL_SYNC||All D flip-flop parts are clocked by a :clk signal|
|GATE_LATch_allwd4||Cross-coupled gate circuits are allowed|
|NO_FF_INItialize5||1-4 flip-flops - All combinations of flip-flop 0/1 starting states must meet the Compare word.
If any combination fails, the candidate solution is rejected.
Note: If all combinations work, the solution is shown at the last initialization state (all '0's).|
5+ flip-flops - All flip-flops are initialized to an 'x'.
|OUT_DEDicated||The OUTPUT signal of the circuit is NOT fed back to inputs|
|OUT_SYNChronous||The OUTPUT signal is from a D flip-flop clocked by :clk|
1. Option NO_AND_OR_Order - If both and-gates and or-gates are assigned, the default solution(s)
will be and-gates driving or-gates but not vice versa. For
example, "(A and C) or (B and C)" has two and-gates driving an
or-gate. If NO_AND_OR_Order is specified, a simpler
solution, "(A or B) and C" which has one or-gate and one and-gate, can
also be found. In general the NO_AND_OR_Order option is NOT
recommended since it will result in longer synthesis times.
2. Lower-case letters are not required, NO_GLIT = NO_GLITches etc.
3. Default option
4. Option GATE_LATch_allwd - In general GATE_LATch_allwd is NOT recommended since it will result in longer synthesis times. Note that cross-coupled gate circuits are automatically allowed if there are no dff parts. If GATE_LATch_allwd is NOT specified and PARTS do include dff(s), all feedback paths must include a DFF 'D' pin. That is, memory circuits using only gates will NOT be synthesized.
5. Option NO_FF_INItialize - Normally (without the NO_FF_INItialize option), flip-flops are initialized using one of two methods, depending on the number of flip-flops being used:
For 1-4 flip-flops, all combinations of flip-flop 0/1 starting states are tried, stopping at the first combination that meets the Compare word. For example if there are two flip-flops, they are started at 0 0, then 0 1, then 1 0, and then 1 1. If no combination works, the solution is rejected.
For 5+ flip-flops, all flip-flops are normally initialized to a '0'.
When NO_FF_INItialize is specified, the Comparison word typically should be an 'x' until one or more positive clock edges occur. This option only applies to D flip-flops. Gate latches are never initialized.
5. INPUT SPECIFICATION - END_OF_SPEC
This section is optional. If this section is excluded SYN will consider all text in the Input Specification window to be part of the specification. If END_OF_SPEC is included, any text after it will be ignored.
Comments begin with "//" or "--" or " ' " or "#" and extend to the end of the line.
|in signals||0-10||input signals to logic circuit|
|output / comparison word||1||circuit output|
|parts||0-31||total parts per circuit|
The Search box can be used to highlight signal names, numbers or text in the Output window. To search, enter the text to be found and then press the Enter key. This will highlight up to 100 instances of the Search text.
To clear all highlighting, delete all text in the Search box and press Enter.
8. OUTPUT OPTIONS
Input Signals - IN_OUT_SIGNALS are re-drawn in the Output window
without circuit synthesis. This can be used to reformat
IN_OUT_SIGNALS or to obtain a waveform printout. The default
Timing Format for Input Signals is Graphic.
Boolean Eqn - The Boolean equation of the solution is displayed.
! && || - If this box is NOT checked, Boolean equation Not And Or operators are displayed as "not", "and" and "or". If this box IS checked, Boolean equation Not And Or operators are displayed as "!" "&&" and "||"
Netlist - The Parts and the Netlist of the Logic Circuit are
displayed. This text can be copied to the Simulation tool to
evaluate and/or modify the Logic Circuit.
Logic Circuit - The Logic Circuit is graphically displayed.
Note: To save logic circuit graphics, select the "Save as type" as Rich Text Format(*.rtf).
For a Copy/Paste save, paste to an .rtf file with Courier New font.
Timing Format - Timing waveform outputs can be turned Off or formatted in one of three formats:
Off - No waveforms displayed (except for the Input Signals option)
01x - Logic 0, 1, x format
_=x - Logic 0 (underscore), Logic 1 (equal), x format
Graphic - Graphical format of 0, 1, x, rising and falling states including glitches/spikes.
Note: To save graphic waveforms, select the "Save as type" as Rich Text Format(*.rtf).
For a Copy/Paste save, paste to an .rtf file with Courier New font.
Input Spec - The timing format is controlled by WAVEFORM_0|1|2|3 Options in the Input Specification. If there is no WAVEFORM_n Option in the Input Spec, the default Timing Format is Graphic.
Expand Hex - Name groups with hexadecimal bit-patterns are expanded to separate name/bit-pattern lines.