VHDL includes few built-in types, but offers a number of additional types through extension packages. Two of the most widely used types are the std_logic and std_ulogic. The difference between them is that the former is resolved, while the latter isn’t.
Before we go on to investigate what it means that a type is resolved, let’s first look at the traits that the two types share in common.
Bit and boolean are part of the standard package,