The United States Department of Defense as part of its Very High-Speed Integrated Circuit (VHSIC) program developed VHSIC HDL (VHDL) in 1982. It is based on programming language ada. The development of VHDL was originated by IBM, Texas Instruments and Intermetrics in 1983. The result contributed by many participating Electronics Design Automation (EDA) groups. It includes many hardware specific constructs. This language has constructs that enable to express the concurrent or sequential behaviour of digital system with or without timing, it also allows interconnecting component. Very High-Speed Integrated Circuit (VHSIC) HDL (VHDL) is a programming language for describing the behavior of digital systems. This language has constructs that enable to express the concurrent or sequential behavior of digital system with or without timing, it also allows interconnecting component. VHDL is one of a few HDLs in widespread use today. VHDL is recognized as a standard HDL by the Institute of Electrical and Electronics Engineers (IEEE Standard 1076, ratified in 1987). VHDL has many features appropriate for describing the behavior of electronic components ranging from simple logic gates to complete microprocessors and custom chips. VHDL allows the behavior of complex electronic circuits to be captured into a design system for automatic circuit synthesis or for system simulation. One of the most important applications of VHDL is to capture the performance specification for a circuit, in the form of what is commonly referred to as a test bench.
Features of VHDL :
(1) World wide Popularity.
(2) VHDL supports different types of modeling.
(3) Also VHDL can be used at different complexity levels-from single transistor up to complete systems and everything remains in the same simulation environment.
(4) The language supports flexible design methodologies top down, bottom up or mixed.
(5) The language can be used as communication medium between different CAD and CAE tools.
(6) The language supports hierarchy that is digital system can be modeled as a set of interconnected components or subcomponents.
(7) It supports both synchronous and asynchronous timing models.
(8) Test benches can be written using the same language to test other VHDL models