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Physical verification is a process whereby an integrated circuit layout -LRB- IC layout -RRB- design is checked via EDA software tools to see if it meets certain criteria .. integrated circuit layout. integrated circuit layout. Verification involves design rule check -LRB- DRC -RRB- , layout versus schematic -LRB- LVS -RRB- , electrical rule check -LRB- ERC -RRB- , XOR -LRB- exclusive OR -RRB- , and antenna checks .. design rule check. design rule check. layout versus schematic. layout versus schematic