Soyuz is still in service as a set of satellites.
The DLX -LRB- pronounced `` Deluxe '' -RRB- is a RISC processor architecture designed by John L. Hennessy and David A. Patterson , the principal designers of the Stanford MIPS and the Berkeley RISC designs -LRB- respectively -RRB- , the two benchmark examples of RISC design -LRB- named after the Berkeley design -RRB- .. John L. Hennessy. John L. Hennessy. David A. Patterson. David A. Patterson ( scientist ). RISC. Reduced instruction set computer. processor. Central processing unit. architecture. Computer architecture. Stanford MIPS. Stanford MIPS. Berkeley RISC. Berkeley RISC. The DLX is essentially a cleaned up -LRB- and modernized -RRB- simplified MIPS CPU .. The DLX has a simple 32-bit load / store architecture , somewhat unlike the modern MIPS CPU .. architecture. Computer architecture. As the DLX was intended primarily for teaching purposes , the DLX design is widely used in university-level computer architecture courses .. architecture. Computer architecture. university. university. There are two known implementations  : ASPIDA and VAMP .. ASPIDA project resulted in a core with many nice features  : open source , supports Wishbone , asynchronous design , supports multiple ISA 's , ASIC proven .. Wishbone. Wishbone ( computer bus ). VAMP is a DLX-variant that was mathematically verified as part of Verisoft project .. It was specified with PVS , implemented in Verilog , and runs on a Xilinx FPGA .. A full stack from compiler to kernel to TCP / IP was built on it .