Datasets:

nchen909

/

devign-processed

like 0

static int mss4_decode_frame(AVCodecContext *avctx, void *data, int *got_frame, AVPacket *avpkt) { const uint8_t *buf = avpkt->data; int buf_size = avpkt->size; MSS4Context *c = avctx->priv_data; GetBitContext gb; GetByteContext bc; uint8_t *dst[3]; int width, height, quality, frame_type; int x, y, i, mb_width, mb_height, blk_type; int ret; if (buf_size < HEADER_SIZE) { av_log(avctx, AV_LOG_ERROR, "Frame should have at least %d bytes, got %d instead\n", HEADER_SIZE, buf_size); return AVERROR_INVALIDDATA; } bytestream2_init(&bc, buf, buf_size); width = bytestream2_get_be16(&bc); height = bytestream2_get_be16(&bc); bytestream2_skip(&bc, 2); quality = bytestream2_get_byte(&bc); frame_type = bytestream2_get_byte(&bc); if (width > avctx->width || height != avctx->height) { av_log(avctx, AV_LOG_ERROR, "Invalid frame dimensions %dx%d\n", width, height); return AVERROR_INVALIDDATA; } if (quality < 1 || quality > 100) { av_log(avctx, AV_LOG_ERROR, "Invalid quality setting %d\n", quality); return AVERROR_INVALIDDATA; } if ((frame_type & ~3) || frame_type == 3) { av_log(avctx, AV_LOG_ERROR, "Invalid frame type %d\n", frame_type); return AVERROR_INVALIDDATA; } if (frame_type != SKIP_FRAME && !bytestream2_get_bytes_left(&bc)) { av_log(avctx, AV_LOG_ERROR, "Empty frame found but it is not a skip frame.\n"); return AVERROR_INVALIDDATA; } if ((ret = ff_reget_buffer(avctx, c->pic)) < 0) return ret; c->pic->key_frame = (frame_type == INTRA_FRAME); c->pic->pict_type = (frame_type == INTRA_FRAME) ? AV_PICTURE_TYPE_I : AV_PICTURE_TYPE_P; if (frame_type == SKIP_FRAME) { *got_frame = 1; if ((ret = av_frame_ref(data, c->pic)) < 0) return ret; return buf_size; } if (c->quality != quality) { c->quality = quality; for (i = 0; i < 2; i++) ff_mss34_gen_quant_mat(c->quant_mat[i], quality, !i); } init_get_bits8(&gb, buf + HEADER_SIZE, (buf_size - HEADER_SIZE)); mb_width = FFALIGN(width, 16) >> 4; mb_height = FFALIGN(height, 16) >> 4; dst[0] = c->pic->data[0]; dst[1] = c->pic->data[1]; dst[2] = c->pic->data[2]; memset(c->prev_vec, 0, sizeof(c->prev_vec)); for (y = 0; y < mb_height; y++) { memset(c->dc_cache, 0, sizeof(c->dc_cache)); for (x = 0; x < mb_width; x++) { blk_type = decode012(&gb); switch (blk_type) { case DCT_BLOCK: if (mss4_decode_dct_block(c, &gb, dst, x, y) < 0) { av_log(avctx, AV_LOG_ERROR, "Error decoding DCT block %d,%d\n", x, y); return AVERROR_INVALIDDATA; } break; case IMAGE_BLOCK: if (mss4_decode_image_block(c, &gb, dst, x, y) < 0) { av_log(avctx, AV_LOG_ERROR, "Error decoding VQ block %d,%d\n", x, y); return AVERROR_INVALIDDATA; } break; case SKIP_BLOCK: if (frame_type == INTRA_FRAME) { av_log(avctx, AV_LOG_ERROR, "Skip block in intra frame\n"); return AVERROR_INVALIDDATA; } break; } if (blk_type != DCT_BLOCK) mss4_update_dc_cache(c, x); } dst[0] += c->pic->linesize[0] * 16; dst[1] += c->pic->linesize[1] * 16; dst[2] += c->pic->linesize[2] * 16; } if ((ret = av_frame_ref(data, c->pic)) < 0) return ret; *got_frame = 1; return buf_size; }

static void guest_phys_blocks_region_add(MemoryListener *listener, MemoryRegionSection *section) { GuestPhysListener *g; uint64_t section_size; hwaddr target_start, target_end; uint8_t *host_addr; GuestPhysBlock *predecessor; /* we only care about RAM */ if (!memory_region_is_ram(section->mr) || memory_region_is_skip_dump(section->mr)) { return; } g = container_of(listener, GuestPhysListener, listener); section_size = int128_get64(section->size); target_start = section->offset_within_address_space; target_end = target_start + section_size; host_addr = memory_region_get_ram_ptr(section->mr) + section->offset_within_region; predecessor = NULL; /* find continuity in guest physical address space */ if (!QTAILQ_EMPTY(&g->list->head)) { hwaddr predecessor_size; predecessor = QTAILQ_LAST(&g->list->head, GuestPhysBlockHead); predecessor_size = predecessor->target_end - predecessor->target_start; /* the memory API guarantees monotonically increasing traversal */ g_assert(predecessor->target_end <= target_start); /* we want continuity in both guest-physical and host-virtual memory */ if (predecessor->target_end < target_start || predecessor->host_addr + predecessor_size != host_addr) { predecessor = NULL; } } if (predecessor == NULL) { /* isolated mapping, allocate it and add it to the list */ GuestPhysBlock *block = g_malloc0(sizeof *block); block->target_start = target_start; block->target_end = target_end; block->host_addr = host_addr; block->mr = section->mr; memory_region_ref(section->mr); QTAILQ_INSERT_TAIL(&g->list->head, block, next); ++g->list->num; } else { /* expand predecessor until @target_end; predecessor's start doesn't * change */ predecessor->target_end = target_end; } #ifdef DEBUG_GUEST_PHYS_REGION_ADD fprintf(stderr, "%s: target_start=" TARGET_FMT_plx " target_end=" TARGET_FMT_plx ": %s (count: %u)\n", __FUNCTION__, target_start, target_end, predecessor ? "joined" : "added", g->list->num); #endif }

InputEvent *replay_read_input_event(void) { InputEvent evt; KeyValue keyValue; InputKeyEvent key; key.key = &keyValue; InputBtnEvent btn; InputMoveEvent rel; InputMoveEvent abs; evt.type = replay_get_dword(); switch (evt.type) { case INPUT_EVENT_KIND_KEY: evt.u.key = &key; evt.u.key->key->type = replay_get_dword(); switch (evt.u.key->key->type) { case KEY_VALUE_KIND_NUMBER: evt.u.key->key->u.number = replay_get_qword(); evt.u.key->down = replay_get_byte(); break; case KEY_VALUE_KIND_QCODE: evt.u.key->key->u.qcode = (QKeyCode)replay_get_dword(); evt.u.key->down = replay_get_byte(); break; case KEY_VALUE_KIND__MAX: /* keep gcc happy */ break; } break; case INPUT_EVENT_KIND_BTN: evt.u.btn = &btn; evt.u.btn->button = (InputButton)replay_get_dword(); evt.u.btn->down = replay_get_byte(); break; case INPUT_EVENT_KIND_REL: evt.u.rel = &rel; evt.u.rel->axis = (InputAxis)replay_get_dword(); evt.u.rel->value = replay_get_qword(); break; case INPUT_EVENT_KIND_ABS: evt.u.abs = &abs; evt.u.abs->axis = (InputAxis)replay_get_dword(); evt.u.abs->value = replay_get_qword(); break; case INPUT_EVENT_KIND__MAX: /* keep gcc happy */ break; } return qapi_clone_InputEvent(&evt); }

build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm, unsigned facs, unsigned dsdt) { AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt)); fadt->firmware_ctrl = cpu_to_le32(facs); /* FACS address to be filled by Guest linker */ bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, ACPI_BUILD_TABLE_FILE, table_data, &fadt->firmware_ctrl, sizeof fadt->firmware_ctrl); fadt->dsdt = cpu_to_le32(dsdt); /* DSDT address to be filled by Guest linker */ bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, ACPI_BUILD_TABLE_FILE, table_data, &fadt->dsdt, sizeof fadt->dsdt); fadt_setup(fadt, pm); build_header(linker, table_data, (void *)fadt, "FACP", sizeof(*fadt), 1, NULL); }

vpc_co_pwritev(BlockDriverState *bs, uint64_t offset, uint64_t bytes, QEMUIOVector *qiov, int flags) { BDRVVPCState *s = bs->opaque; int64_t image_offset; int64_t n_bytes; int64_t bytes_done = 0; int ret; VHDFooter *footer = (VHDFooter *) s->footer_buf; QEMUIOVector local_qiov; if (be32_to_cpu(footer->type) == VHD_FIXED) { return bdrv_co_pwritev(bs->file->bs, offset, bytes, qiov, 0); } qemu_co_mutex_lock(&s->lock); qemu_iovec_init(&local_qiov, qiov->niov); while (bytes > 0) { image_offset = get_image_offset(bs, offset, true); n_bytes = MIN(bytes, s->block_size - (offset % s->block_size)); if (image_offset == -1) { image_offset = alloc_block(bs, offset); if (image_offset < 0) { ret = image_offset; goto fail; } } qemu_iovec_reset(&local_qiov); qemu_iovec_concat(&local_qiov, qiov, bytes_done, n_bytes); ret = bdrv_co_pwritev(bs->file->bs, image_offset, n_bytes, &local_qiov, 0); if (ret < 0) { goto fail; } bytes -= n_bytes; offset += n_bytes; bytes_done += n_bytes; } ret = 0; fail: qemu_iovec_destroy(&local_qiov); qemu_co_mutex_unlock(&s->lock); return ret; }

static int debugcon_parse(const char *devname) { QemuOpts *opts; if (!qemu_chr_new("debugcon", devname, NULL)) { exit(1); } opts = qemu_opts_create(qemu_find_opts("device"), "debugcon", 1, NULL); if (!opts) { fprintf(stderr, "qemu: already have a debugcon device\n"); exit(1); } qemu_opt_set(opts, "driver", "isa-debugcon", &error_abort); qemu_opt_set(opts, "chardev", "debugcon", &error_abort); return 0; }

static void qemu_rbd_parse_filename(const char *filename, QDict *options, Error **errp) { const char *start; char *p, *buf, *keypairs; char *found_str; size_t max_keypair_size; Error *local_err = NULL; if (!strstart(filename, "rbd:", &start)) { error_setg(errp, "File name must start with 'rbd:'"); return; } max_keypair_size = strlen(start) + 1; buf = g_strdup(start); keypairs = g_malloc0(max_keypair_size); p = buf; found_str = qemu_rbd_next_tok(RBD_MAX_POOL_NAME_SIZE, p, '/', "pool name", &p, &local_err); if (local_err) { goto done; } if (!p) { error_setg(errp, "Pool name is required"); goto done; } qemu_rbd_unescape(found_str); qdict_put(options, "pool", qstring_from_str(found_str)); if (strchr(p, '@')) { found_str = qemu_rbd_next_tok(RBD_MAX_IMAGE_NAME_SIZE, p, '@', "object name", &p, &local_err); if (local_err) { goto done; } qemu_rbd_unescape(found_str); qdict_put(options, "image", qstring_from_str(found_str)); found_str = qemu_rbd_next_tok(RBD_MAX_SNAP_NAME_SIZE, p, ':', "snap name", &p, &local_err); if (local_err) { goto done; } qemu_rbd_unescape(found_str); qdict_put(options, "snapshot", qstring_from_str(found_str)); } else { found_str = qemu_rbd_next_tok(RBD_MAX_IMAGE_NAME_SIZE, p, ':', "object name", &p, &local_err); if (local_err) { goto done; } qemu_rbd_unescape(found_str); qdict_put(options, "image", qstring_from_str(found_str)); } if (!p) { goto done; } found_str = qemu_rbd_next_tok(RBD_MAX_CONF_NAME_SIZE, p, '\0', "configuration", &p, &local_err); if (local_err) { goto done; } p = found_str; /* The following are essentially all key/value pairs, and we treat * 'id' and 'conf' a bit special. Key/value pairs may be in any order. */ while (p) { char *name, *value; name = qemu_rbd_next_tok(RBD_MAX_CONF_NAME_SIZE, p, '=', "conf option name", &p, &local_err); if (local_err) { break; } if (!p) { error_setg(errp, "conf option %s has no value", name); break; } qemu_rbd_unescape(name); value = qemu_rbd_next_tok(RBD_MAX_CONF_VAL_SIZE, p, ':', "conf option value", &p, &local_err); if (local_err) { break; } qemu_rbd_unescape(value); if (!strcmp(name, "conf")) { qdict_put(options, "conf", qstring_from_str(value)); } else if (!strcmp(name, "id")) { qdict_put(options, "user" , qstring_from_str(value)); } else { /* FIXME: This is pretty ugly, and not the right way to do this. * These should be contained in a structure, and then * passed explicitly as individual key/value pairs to * rados. Consider this legacy code that needs to be * updated. */ char *tmp = g_malloc0(max_keypair_size); /* only use a delimiter if it is not the first keypair found */ /* These are sets of unknown key/value pairs we'll pass along * to ceph */ if (keypairs[0]) { snprintf(tmp, max_keypair_size, ":%s=%s", name, value); pstrcat(keypairs, max_keypair_size, tmp); } else { snprintf(keypairs, max_keypair_size, "%s=%s", name, value); } g_free(tmp); } } if (keypairs[0]) { qdict_put(options, "keyvalue-pairs", qstring_from_str(keypairs)); } done: if (local_err) { error_propagate(errp, local_err); } g_free(buf); g_free(keypairs); return; }

static void register_multipage(MemoryRegionSection *section) { target_phys_addr_t start_addr = section->offset_within_address_space; ram_addr_t size = section->size; target_phys_addr_t addr; uint16_t section_index = phys_section_add(section); assert(size); addr = start_addr; phys_page_set(addr >> TARGET_PAGE_BITS, size >> TARGET_PAGE_BITS, section_index); }

static int gdb_breakpoint_insert(CPUState *env, target_ulong addr, target_ulong len, int type) { switch (type) { case GDB_BREAKPOINT_SW: case GDB_BREAKPOINT_HW: return cpu_breakpoint_insert(env, addr, BP_GDB, NULL); #ifndef CONFIG_USER_ONLY case GDB_WATCHPOINT_WRITE: case GDB_WATCHPOINT_READ: case GDB_WATCHPOINT_ACCESS: return cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type], NULL); #endif default: return -ENOSYS; } }

ResampleContext *ff_audio_resample_init(AVAudioResampleContext *avr) { ResampleContext *c; int out_rate = avr->out_sample_rate; int in_rate = avr->in_sample_rate; double factor = FFMIN(out_rate * avr->cutoff / in_rate, 1.0); int phase_count = 1 << avr->phase_shift; int felem_size; if (avr->internal_sample_fmt != AV_SAMPLE_FMT_S16P && avr->internal_sample_fmt != AV_SAMPLE_FMT_S32P && avr->internal_sample_fmt != AV_SAMPLE_FMT_FLTP && avr->internal_sample_fmt != AV_SAMPLE_FMT_DBLP) { av_log(avr, AV_LOG_ERROR, "Unsupported internal format for " "resampling: %s\n", av_get_sample_fmt_name(avr->internal_sample_fmt)); return NULL; } c = av_mallocz(sizeof(*c)); if (!c) return NULL; c->avr = avr; c->phase_shift = avr->phase_shift; c->phase_mask = phase_count - 1; c->linear = avr->linear_interp; c->factor = factor; c->filter_length = FFMAX((int)ceil(avr->filter_size / factor), 1); c->filter_type = avr->filter_type; c->kaiser_beta = avr->kaiser_beta; switch (avr->internal_sample_fmt) { case AV_SAMPLE_FMT_DBLP: c->resample_one = resample_one_dbl; c->resample_nearest = resample_nearest_dbl; c->set_filter = set_filter_dbl; break; case AV_SAMPLE_FMT_FLTP: c->resample_one = resample_one_flt; c->resample_nearest = resample_nearest_flt; c->set_filter = set_filter_flt; break; case AV_SAMPLE_FMT_S32P: c->resample_one = resample_one_s32; c->resample_nearest = resample_nearest_s32; c->set_filter = set_filter_s32; break; case AV_SAMPLE_FMT_S16P: c->resample_one = resample_one_s16; c->resample_nearest = resample_nearest_s16; c->set_filter = set_filter_s16; break; } felem_size = av_get_bytes_per_sample(avr->internal_sample_fmt); c->filter_bank = av_mallocz(c->filter_length * (phase_count + 1) * felem_size); if (!c->filter_bank) goto error; if (build_filter(c) < 0) goto error; memcpy(&c->filter_bank[(c->filter_length * phase_count + 1) * felem_size], c->filter_bank, (c->filter_length - 1) * felem_size); memcpy(&c->filter_bank[c->filter_length * phase_count * felem_size], &c->filter_bank[(c->filter_length - 1) * felem_size], felem_size); c->compensation_distance = 0; if (!av_reduce(&c->src_incr, &c->dst_incr, out_rate, in_rate * (int64_t)phase_count, INT32_MAX / 2)) goto error; c->ideal_dst_incr = c->dst_incr; c->padding_size = (c->filter_length - 1) / 2; c->index = -phase_count * ((c->filter_length - 1) / 2); c->frac = 0; /* allocate internal buffer */ c->buffer = ff_audio_data_alloc(avr->resample_channels, 0, avr->internal_sample_fmt, "resample buffer"); if (!c->buffer) goto error; av_log(avr, AV_LOG_DEBUG, "resample: %s from %d Hz to %d Hz\n", av_get_sample_fmt_name(avr->internal_sample_fmt), avr->in_sample_rate, avr->out_sample_rate); return c; error: ff_audio_data_free(&c->buffer); av_free(c->filter_bank); av_free(c); return NULL; }

static inline void stl_phys_internal(target_phys_addr_t addr, uint32_t val, enum device_endian endian) { uint8_t *ptr; MemoryRegionSection *section; section = phys_page_find(addr >> TARGET_PAGE_BITS); if (!memory_region_is_ram(section->mr) || section->readonly) { addr = memory_region_section_addr(section, addr); if (memory_region_is_ram(section->mr)) { section = &phys_sections[phys_section_rom]; } #if defined(TARGET_WORDS_BIGENDIAN) if (endian == DEVICE_LITTLE_ENDIAN) { val = bswap32(val); } #else if (endian == DEVICE_BIG_ENDIAN) { val = bswap32(val); } #endif io_mem_write(section->mr, addr, val, 4); } else { unsigned long addr1; addr1 = (memory_region_get_ram_addr(section->mr) & TARGET_PAGE_MASK) + memory_region_section_addr(section, addr); /* RAM case */ ptr = qemu_get_ram_ptr(addr1); switch (endian) { case DEVICE_LITTLE_ENDIAN: stl_le_p(ptr, val); break; case DEVICE_BIG_ENDIAN: stl_be_p(ptr, val); break; default: stl_p(ptr, val); break; } invalidate_and_set_dirty(addr1, 4); } }

static int usb_hub_handle_control(USBDevice *dev, int request, int value, int index, int length, uint8_t *data) { USBHubState *s = (USBHubState *)dev; int ret; ret = usb_desc_handle_control(dev, request, value, index, length, data); if (ret >= 0) { return ret; } switch(request) { case DeviceRequest | USB_REQ_GET_STATUS: data[0] = (1 << USB_DEVICE_SELF_POWERED) | (dev->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP); data[1] = 0x00; ret = 2; break; case DeviceOutRequest | USB_REQ_CLEAR_FEATURE: if (value == USB_DEVICE_REMOTE_WAKEUP) { dev->remote_wakeup = 0; } else { goto fail; } ret = 0; break; case EndpointOutRequest | USB_REQ_CLEAR_FEATURE: if (value == 0 && index != 0x81) { /* clear ep halt */ goto fail; } ret = 0; break; case DeviceOutRequest | USB_REQ_SET_FEATURE: if (value == USB_DEVICE_REMOTE_WAKEUP) { dev->remote_wakeup = 1; } else { goto fail; } ret = 0; break; case DeviceRequest | USB_REQ_GET_CONFIGURATION: data[0] = 1; ret = 1; break; case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: ret = 0; break; case DeviceRequest | USB_REQ_GET_INTERFACE: data[0] = 0; ret = 1; break; case DeviceOutRequest | USB_REQ_SET_INTERFACE: ret = 0; break; /* usb specific requests */ case GetHubStatus: data[0] = 0; data[1] = 0; data[2] = 0; data[3] = 0; ret = 4; break; case GetPortStatus: { unsigned int n = index - 1; USBHubPort *port; if (n >= NUM_PORTS) { goto fail; } port = &s->ports[n]; data[0] = port->wPortStatus; data[1] = port->wPortStatus >> 8; data[2] = port->wPortChange; data[3] = port->wPortChange >> 8; ret = 4; } break; case SetHubFeature: case ClearHubFeature: if (value == 0 || value == 1) { } else { goto fail; } ret = 0; break; case SetPortFeature: { unsigned int n = index - 1; USBHubPort *port; USBDevice *dev; if (n >= NUM_PORTS) { goto fail; } port = &s->ports[n]; dev = port->port.dev; switch(value) { case PORT_SUSPEND: port->wPortStatus |= PORT_STAT_SUSPEND; break; case PORT_RESET: if (dev) { usb_send_msg(dev, USB_MSG_RESET); port->wPortChange |= PORT_STAT_C_RESET; /* set enable bit */ port->wPortStatus |= PORT_STAT_ENABLE; } break; case PORT_POWER: break; default: goto fail; } ret = 0; } break; case ClearPortFeature: { unsigned int n = index - 1; USBHubPort *port; if (n >= NUM_PORTS) { goto fail; } port = &s->ports[n]; switch(value) { case PORT_ENABLE: port->wPortStatus &= ~PORT_STAT_ENABLE; break; case PORT_C_ENABLE: port->wPortChange &= ~PORT_STAT_C_ENABLE; break; case PORT_SUSPEND: port->wPortStatus &= ~PORT_STAT_SUSPEND; break; case PORT_C_SUSPEND: port->wPortChange &= ~PORT_STAT_C_SUSPEND; break; case PORT_C_CONNECTION: port->wPortChange &= ~PORT_STAT_C_CONNECTION; break; case PORT_C_OVERCURRENT: port->wPortChange &= ~PORT_STAT_C_OVERCURRENT; break; case PORT_C_RESET: port->wPortChange &= ~PORT_STAT_C_RESET; break; default: goto fail; } ret = 0; } break; case GetHubDescriptor: { unsigned int n, limit, var_hub_size = 0; memcpy(data, qemu_hub_hub_descriptor, sizeof(qemu_hub_hub_descriptor)); data[2] = NUM_PORTS; /* fill DeviceRemovable bits */ limit = ((NUM_PORTS + 1 + 7) / 8) + 7; for (n = 7; n < limit; n++) { data[n] = 0x00; var_hub_size++; } /* fill PortPwrCtrlMask bits */ limit = limit + ((NUM_PORTS + 7) / 8); for (;n < limit; n++) { data[n] = 0xff; var_hub_size++; } ret = sizeof(qemu_hub_hub_descriptor) + var_hub_size; data[0] = ret; break; } default: fail: ret = USB_RET_STALL; break; } return ret; }

void nbd_client_close(BlockDriverState *bs) { NbdClientSession *client = nbd_get_client_session(bs); struct nbd_request request = { .type = NBD_CMD_DISC, .from = 0, .len = 0 }; if (client->ioc == NULL) { return; } nbd_send_request(client->ioc, &request); nbd_teardown_connection(bs); }

static int handle_tsch(S390CPU *cpu) { CPUS390XState *env = &cpu->env; CPUState *cs = CPU(cpu); struct kvm_run *run = cs->kvm_run; int ret; cpu_synchronize_state(cs); ret = ioinst_handle_tsch(env, env->regs[1], run->s390_tsch.ipb); if (ret >= 0) { /* Success; set condition code. */ setcc(cpu, ret); ret = 0; } else if (ret < -1) { /* * Failure. * If an I/O interrupt had been dequeued, we have to reinject it. */ if (run->s390_tsch.dequeued) { uint16_t subchannel_id = run->s390_tsch.subchannel_id; uint16_t subchannel_nr = run->s390_tsch.subchannel_nr; uint32_t io_int_parm = run->s390_tsch.io_int_parm; uint32_t io_int_word = run->s390_tsch.io_int_word; uint32_t type = ((subchannel_id & 0xff00) << 24) | ((subchannel_id & 0x00060) << 22) | (subchannel_nr << 16); kvm_s390_interrupt_internal(cpu, type, ((uint32_t)subchannel_id << 16) | subchannel_nr, ((uint64_t)io_int_parm << 32) | io_int_word, 1); } ret = 0; } return ret; }

static int read_password(char *buf, int buf_size) { uint8_t ch; int i, ret; printf("password: "); fflush(stdout); term_init(); i = 0; for(;;) { ret = read(0, &ch, 1); if (ret == -1) { if (errno == EAGAIN || errno == EINTR) { continue; } else { break; } } else if (ret == 0) { ret = -1; break; } else { if (ch == '\r') { ret = 0; break; } if (i < (buf_size - 1)) buf[i++] = ch; } } term_exit(); buf[i] = '\0'; printf("\n"); return ret; }

static uint64_t exynos4210_rtc_read(void *opaque, target_phys_addr_t offset, unsigned size) { uint32_t value = 0; Exynos4210RTCState *s = (Exynos4210RTCState *)opaque; switch (offset) { case INTP: value = s->reg_intp; break; case RTCCON: value = s->reg_rtccon; break; case TICCNT: value = s->reg_ticcnt; break; case RTCALM: value = s->reg_rtcalm; break; case ALMSEC: value = s->reg_almsec; break; case ALMMIN: value = s->reg_almmin; break; case ALMHOUR: value = s->reg_almhour; break; case ALMDAY: value = s->reg_almday; break; case ALMMON: value = s->reg_almmon; break; case ALMYEAR: value = s->reg_almyear; break; case BCDSEC: value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_sec); break; case BCDMIN: value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_min); break; case BCDHOUR: value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_hour); break; case BCDDAYWEEK: value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_wday); break; case BCDDAY: value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mday); break; case BCDMON: value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mon + 1); break; case BCDYEAR: value = BCD3DIGITS(s->current_tm.tm_year); break; case CURTICNT: s->reg_curticcnt = ptimer_get_count(s->ptimer); value = s->reg_curticcnt; break; default: fprintf(stderr, "[exynos4210.rtc: bad read offset " TARGET_FMT_plx "]\n", offset); break; } return value; }

static int read_tfra(MOVContext *mov, AVIOContext *f) { MOVFragmentIndex* index = NULL; int version, fieldlength, i, j, err; int64_t pos = avio_tell(f); uint32_t size = avio_rb32(f); if (avio_rb32(f) != MKBETAG('t', 'f', 'r', 'a')) { return -1; } av_log(mov->fc, AV_LOG_VERBOSE, "found tfra\n"); index = av_mallocz(sizeof(MOVFragmentIndex)); if (!index) { return AVERROR(ENOMEM); } mov->fragment_index_count++; if ((err = av_reallocp(&mov->fragment_index_data, mov->fragment_index_count * sizeof(MOVFragmentIndex*))) < 0) { av_freep(&index); return err; } mov->fragment_index_data[mov->fragment_index_count - 1] = index; version = avio_r8(f); avio_rb24(f); index->track_id = avio_rb32(f); fieldlength = avio_rb32(f); index->item_count = avio_rb32(f); index->items = av_mallocz( index->item_count * sizeof(MOVFragmentIndexItem)); if (!index->items) { return AVERROR(ENOMEM); } for (i = 0; i < index->item_count; i++) { int64_t time, offset; if (version == 1) { time = avio_rb64(f); offset = avio_rb64(f); } else { time = avio_rb32(f); offset = avio_rb32(f); } index->items[i].time = time; index->items[i].moof_offset = offset; for (j = 0; j < ((fieldlength >> 4) & 3) + 1; j++) avio_r8(f); for (j = 0; j < ((fieldlength >> 2) & 3) + 1; j++) avio_r8(f); for (j = 0; j < ((fieldlength >> 0) & 3) + 1; j++) avio_r8(f); } avio_seek(f, pos + size, SEEK_SET); return 0; }

void ff_h264_direct_ref_list_init(H264Context * const h){ MpegEncContext * const s = &h->s; Picture * const ref1 = &h->ref_list[1][0]; Picture * const cur = s->current_picture_ptr; int list, j, field; int sidx= (s->picture_structure&1)^1; int ref1sidx = (ref1->f.reference&1)^1; for(list=0; list<2; list++){ cur->ref_count[sidx][list] = h->ref_count[list]; for(j=0; j<h->ref_count[list]; j++) cur->ref_poc[sidx][list][j] = 4 * h->ref_list[list][j].frame_num + (h->ref_list[list][j].f.reference & 3); } if(s->picture_structure == PICT_FRAME){ memcpy(cur->ref_count[1], cur->ref_count[0], sizeof(cur->ref_count[0])); memcpy(cur->ref_poc [1], cur->ref_poc [0], sizeof(cur->ref_poc [0])); } cur->mbaff= FRAME_MBAFF; h->col_fieldoff= 0; if(s->picture_structure == PICT_FRAME){ int cur_poc = s->current_picture_ptr->poc; int *col_poc = h->ref_list[1]->field_poc; h->col_parity= (FFABS(col_poc[0] - cur_poc) >= FFABS(col_poc[1] - cur_poc)); ref1sidx=sidx= h->col_parity; } else if (!(s->picture_structure & h->ref_list[1][0].f.reference) && !h->ref_list[1][0].mbaff) { // FL -> FL & differ parity h->col_fieldoff = 2 * h->ref_list[1][0].f.reference - 3; } if (cur->f.pict_type != AV_PICTURE_TYPE_B || h->direct_spatial_mv_pred) return; for(list=0; list<2; list++){ fill_colmap(h, h->map_col_to_list0, list, sidx, ref1sidx, 0); if(FRAME_MBAFF) for(field=0; field<2; field++) fill_colmap(h, h->map_col_to_list0_field[field], list, field, field, 1); } }

static int make_ydt24_entry(int p1, int p2, int16_t *ydt) { int lo, hi; lo = ydt[p1]; hi = ydt[p2]; return (lo + (hi << 8) + (hi << 16)) << 1; }

static uint64_t fw_cfg_comb_read(void *opaque, hwaddr addr, unsigned size) { return fw_cfg_read(opaque); }

static int xan_decode_frame(AVCodecContext *avctx, void *data, int *data_size, AVPacket *avpkt) { const uint8_t *buf = avpkt->data; int ret, buf_size = avpkt->size; XanContext *s = avctx->priv_data; if (avctx->codec->id == CODEC_ID_XAN_WC3) { const uint8_t *buf_end = buf + buf_size; int tag = 0; while (buf_end - buf > 8 && tag != VGA__TAG) { unsigned *tmpptr; uint32_t new_pal; int size; int i; tag = bytestream_get_le32(&buf); size = bytestream_get_be32(&buf); size = FFMIN(size, buf_end - buf); switch (tag) { case PALT_TAG: if (size < PALETTE_SIZE) if (s->palettes_count >= PALETTES_MAX) tmpptr = av_realloc(s->palettes, (s->palettes_count + 1) * AVPALETTE_SIZE); if (!tmpptr) return AVERROR(ENOMEM); s->palettes = tmpptr; tmpptr += s->palettes_count * AVPALETTE_COUNT; for (i = 0; i < PALETTE_COUNT; i++) { #if RUNTIME_GAMMA int r = gamma_corr(*buf++); int g = gamma_corr(*buf++); int b = gamma_corr(*buf++); #else int r = gamma_lookup[*buf++]; int g = gamma_lookup[*buf++]; int b = gamma_lookup[*buf++]; #endif *tmpptr++ = (r << 16) | (g << 8) | b; } s->palettes_count++; break; case SHOT_TAG: if (size < 4) new_pal = bytestream_get_le32(&buf); if (new_pal < s->palettes_count) { s->cur_palette = new_pal; } else av_log(avctx, AV_LOG_ERROR, "Invalid palette selected\n"); break; case VGA__TAG: break; default: buf += size; break; } } buf_size = buf_end - buf; } if ((ret = avctx->get_buffer(avctx, &s->current_frame))) { av_log(s->avctx, AV_LOG_ERROR, "get_buffer() failed\n"); return ret; } s->current_frame.reference = 3; if (!s->frame_size) s->frame_size = s->current_frame.linesize[0] * s->avctx->height; memcpy(s->current_frame.data[1], s->palettes + s->cur_palette * AVPALETTE_COUNT, AVPALETTE_SIZE); s->buf = buf; s->size = buf_size; if (xan_wc3_decode_frame(s) < 0) /* release the last frame if it is allocated */ if (s->last_frame.data[0]) avctx->release_buffer(avctx, &s->last_frame); *data_size = sizeof(AVFrame); *(AVFrame*)data = s->current_frame; /* shuffle frames */ FFSWAP(AVFrame, s->current_frame, s->last_frame); /* always report that the buffer was completely consumed */ return buf_size; }

void do_405_check_sat (void) { if (!likely(((T1 ^ T2) >> 31) || !((T0 ^ T2) >> 31))) { /* Saturate result */ if (T2 >> 31) { T0 = INT32_MIN; } else { T0 = INT32_MAX; } } }

void *grow_array(void *array, int elem_size, int *size, int new_size) { if (new_size >= INT_MAX / elem_size) { av_log(NULL, AV_LOG_ERROR, "Array too big.\n"); exit(1); } if (*size < new_size) { uint8_t *tmp = av_realloc(array, new_size*elem_size); if (!tmp) { av_log(NULL, AV_LOG_ERROR, "Could not alloc buffer.\n"); exit(1); } memset(tmp + *size*elem_size, 0, (new_size-*size) * elem_size); *size = new_size; return tmp; } return array; }

static int select_input_file(uint8_t *no_packet) { int64_t ipts_min = INT64_MAX; int i, file_index = -1; for (i = 0; i < nb_input_streams; i++) { InputStream *ist = input_streams[i]; int64_t ipts = ist->pts; if (ist->discard || no_packet[ist->file_index]) continue; if (!input_files[ist->file_index]->eof_reached) { if (ipts < ipts_min) { ipts_min = ipts; file_index = ist->file_index; } } } return file_index; }

static target_ulong get_psr(void) { helper_compute_psr(); #if !defined (TARGET_SPARC64) return env->version | (env->psr & PSR_ICC) | (env->psref? PSR_EF : 0) | (env->psrpil << 8) | (env->psrs? PSR_S : 0) | (env->psrps? PSR_PS : 0) | (env->psret? PSR_ET : 0) | env->cwp; #else return env->version | (env->psr & PSR_ICC) | (env->psref? PSR_EF : 0) | (env->psrpil << 8) | (env->psrs? PSR_S : 0) | (env->psrps? PSR_PS : 0) | env->cwp; #endif }

void qpci_iounmap(QPCIDevice *dev, void *data) { /* FIXME */ }

int rom_add_file(const char *file, const char *fw_dir, hwaddr addr, int32_t bootindex, bool option_rom, MemoryRegion *mr) { MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); Rom *rom; int rc, fd = -1; char devpath[100]; rom = g_malloc0(sizeof(*rom)); rom->name = g_strdup(file); rom->path = qemu_find_file(QEMU_FILE_TYPE_BIOS, rom->name); if (rom->path == NULL) { rom->path = g_strdup(file); fd = open(rom->path, O_RDONLY | O_BINARY); if (fd == -1) { fprintf(stderr, "Could not open option rom '%s': %s\n", rom->path, strerror(errno)); goto err; rom->fw_dir = g_strdup(fw_dir); rom->fw_file = g_strdup(file); rom->addr = addr; rom->romsize = lseek(fd, 0, SEEK_END); if (rom->romsize == -1) { fprintf(stderr, "rom: file %-20s: get size error: %s\n", rom->name, strerror(errno)); goto err; rom->datasize = rom->romsize; rom->data = g_malloc0(rom->datasize); lseek(fd, 0, SEEK_SET); rc = read(fd, rom->data, rom->datasize); if (rc != rom->datasize) { fprintf(stderr, "rom: file %-20s: read error: rc=%d (expected %zd)\n", rom->name, rc, rom->datasize); goto err; close(fd); rom_insert(rom); if (rom->fw_file && fw_cfg) { const char *basename; char fw_file_name[FW_CFG_MAX_FILE_PATH]; void *data; basename = strrchr(rom->fw_file, '/'); if (basename) { basename++; } else { basename = rom->fw_file; snprintf(fw_file_name, sizeof(fw_file_name), "%s/%s", rom->fw_dir, basename); snprintf(devpath, sizeof(devpath), "/rom@%s", fw_file_name); if ((!option_rom || mc->option_rom_has_mr) && mc->rom_file_has_mr) { data = rom_set_mr(rom, OBJECT(fw_cfg), devpath); } else { data = rom->data; fw_cfg_add_file(fw_cfg, fw_file_name, data, rom->romsize); } else { if (mr) { rom->mr = mr; snprintf(devpath, sizeof(devpath), "/rom@%s", file); } else { snprintf(devpath, sizeof(devpath), "/rom@" TARGET_FMT_plx, addr); add_boot_device_path(bootindex, NULL, devpath); return 0; err: if (fd != -1) close(fd); g_free(rom->data); g_free(rom->path); g_free(rom->name); g_free(rom); return -1;

static inline int find_pte (CPUState *env, mmu_ctx_t *ctx, int h, int rw) { #if defined(TARGET_PPC64) if (env->mmu_model == POWERPC_MMU_64B || env->mmu_model == POWERPC_MMU_64BRIDGE) return find_pte64(ctx, h, rw); #endif return find_pte32(ctx, h, rw); }

static void vfio_probe_nvidia_bar5_quirk(VFIOPCIDevice *vdev, int nr) { VFIOQuirk *quirk; VFIONvidiaBAR5Quirk *bar5; VFIOConfigWindowQuirk *window; if (!vfio_pci_is(vdev, PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID) || !vdev->has_vga || nr != 5) { return; } quirk = g_malloc0(sizeof(*quirk)); quirk->mem = g_malloc0(sizeof(MemoryRegion) * 4); quirk->nr_mem = 4; bar5 = quirk->data = g_malloc0(sizeof(*bar5) + (sizeof(VFIOConfigWindowMatch) * 2)); window = &bar5->window; window->vdev = vdev; window->address_offset = 0x8; window->data_offset = 0xc; window->nr_matches = 2; window->matches[0].match = 0x1800; window->matches[0].mask = PCI_CONFIG_SPACE_SIZE - 1; window->matches[1].match = 0x88000; window->matches[1].mask = PCIE_CONFIG_SPACE_SIZE - 1; window->bar = nr; window->addr_mem = bar5->addr_mem = &quirk->mem[0]; window->data_mem = bar5->data_mem = &quirk->mem[1]; memory_region_init_io(window->addr_mem, OBJECT(vdev), &vfio_generic_window_address_quirk, window, "vfio-nvidia-bar5-window-address-quirk", 4); memory_region_add_subregion_overlap(&vdev->bars[nr].region.mem, window->address_offset, window->addr_mem, 1); memory_region_set_enabled(window->addr_mem, false); memory_region_init_io(window->data_mem, OBJECT(vdev), &vfio_generic_window_data_quirk, window, "vfio-nvidia-bar5-window-data-quirk", 4); memory_region_add_subregion_overlap(&vdev->bars[nr].region.mem, window->data_offset, window->data_mem, 1); memory_region_set_enabled(window->data_mem, false); memory_region_init_io(&quirk->mem[2], OBJECT(vdev), &vfio_nvidia_bar5_quirk_master, bar5, "vfio-nvidia-bar5-master-quirk", 4); memory_region_add_subregion_overlap(&vdev->bars[nr].region.mem, 0, &quirk->mem[2], 1); memory_region_init_io(&quirk->mem[3], OBJECT(vdev), &vfio_nvidia_bar5_quirk_enable, bar5, "vfio-nvidia-bar5-enable-quirk", 4); memory_region_add_subregion_overlap(&vdev->bars[nr].region.mem, 4, &quirk->mem[3], 1); QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); trace_vfio_quirk_nvidia_bar5_probe(vdev->vbasedev.name); }

static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem, hwaddr base, qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) { PXA2xxI2SState *s = (PXA2xxI2SState *) g_malloc0(sizeof(PXA2xxI2SState)); s->irq = irq; s->rx_dma = rx_dma; s->tx_dma = tx_dma; s->data_req = pxa2xx_i2s_data_req; pxa2xx_i2s_reset(s); memory_region_init_io(&s->iomem, NULL, &pxa2xx_i2s_ops, s, "pxa2xx-i2s", 0x100000); memory_region_add_subregion(sysmem, base, &s->iomem); vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s); return s; }

static void unimp_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = unimp_realize; dc->props = unimp_properties; }

int ff_get_qtpalette(int codec_id, AVIOContext *pb, uint32_t *palette) { int tmp, bit_depth, color_table_id, greyscale, i; avio_seek(pb, 82, SEEK_CUR); /* Get the bit depth and greyscale state */ tmp = avio_rb16(pb); bit_depth = tmp & 0x1F; greyscale = tmp & 0x20; /* Get the color table ID */ color_table_id = avio_rb16(pb); /* Do not create a greyscale palette for Cinepak */ if (greyscale && codec_id == AV_CODEC_ID_CINEPAK) return 0; /* If the depth is 1, 2, 4, or 8 bpp, file is palettized. */ if ((bit_depth == 1 || bit_depth == 2 || bit_depth == 4 || bit_depth == 8)) { int color_count, color_start, color_end; uint32_t a, r, g, b; /* Ignore the greyscale bit for 1-bit video and sample * descriptions containing a color table. */ if (greyscale && bit_depth > 1 && color_table_id) { int color_index, color_dec; /* compute the greyscale palette */ color_count = 1 << bit_depth; color_index = 255; color_dec = 256 / (color_count - 1); for (i = 0; i < color_count; i++) { r = g = b = color_index; palette[i] = (0xFFU << 24) | (r << 16) | (g << 8) | (b); color_index -= color_dec; if (color_index < 0) color_index = 0; } } else if (color_table_id) { /* The color table ID is non-zero. Interpret this as * being -1, which means use the default Macintosh * color table */ const uint8_t *color_table; color_count = 1 << bit_depth; if (bit_depth == 1) color_table = ff_qt_default_palette_2; else if (bit_depth == 2) color_table = ff_qt_default_palette_4; else if (bit_depth == 4) color_table = ff_qt_default_palette_16; else color_table = ff_qt_default_palette_256; for (i = 0; i < color_count; i++) { r = color_table[i * 3 + 0]; g = color_table[i * 3 + 1]; b = color_table[i * 3 + 2]; palette[i] = (0xFFU << 24) | (r << 16) | (g << 8) | (b); } } else { /* The color table ID is 0; the color table is in the sample * description */ color_start = avio_rb32(pb); avio_rb16(pb); /* color table flags */ color_end = avio_rb16(pb); if ((color_start <= 255) && (color_end <= 255)) { for (i = color_start; i <= color_end; i++) { /* each A, R, G, or B component is 16 bits; * only use the top 8 bits */ a = avio_r8(pb); avio_r8(pb); r = avio_r8(pb); avio_r8(pb); g = avio_r8(pb); avio_r8(pb); b = avio_r8(pb); avio_r8(pb); palette[i] = (a << 24 ) | (r << 16) | (g << 8) | (b); } } } return 1; } return 0; }

AVCodecParserContext *av_parser_init(int codec_id) { AVCodecParserContext *s = NULL; AVCodecParser *parser; int ret; if(codec_id == AV_CODEC_ID_NONE) return NULL; for(parser = av_first_parser; parser != NULL; parser = parser->next) { if (parser->codec_ids[0] == codec_id || parser->codec_ids[1] == codec_id || parser->codec_ids[2] == codec_id || parser->codec_ids[3] == codec_id || parser->codec_ids[4] == codec_id) goto found; } return NULL; found: s = av_mallocz(sizeof(AVCodecParserContext)); if (!s) goto err_out; s->parser = parser; s->priv_data = av_mallocz(parser->priv_data_size); if (!s->priv_data) goto err_out; s->fetch_timestamp=1; s->pict_type = AV_PICTURE_TYPE_I; if (parser->parser_init) { if (ff_lock_avcodec(NULL) < 0) goto err_out; ret = parser->parser_init(s); ff_unlock_avcodec(); if (ret != 0) goto err_out; } s->key_frame = -1; s->convergence_duration = 0; s->dts_sync_point = INT_MIN; s->dts_ref_dts_delta = INT_MIN; s->pts_dts_delta = INT_MIN; return s; err_out: if (s) av_freep(&s->priv_data); av_free(s); return NULL; }

static int ra288_decode_frame(AVCodecContext * avctx, void *data, int *got_frame_ptr, AVPacket *avpkt) { AVFrame *frame = data; const uint8_t *buf = avpkt->data; int buf_size = avpkt->size; float *out; int i, ret; RA288Context *ractx = avctx->priv_data; GetBitContext gb; if (buf_size < avctx->block_align) { av_log(avctx, AV_LOG_ERROR, "Error! Input buffer is too small [%d<%d]\n", buf_size, avctx->block_align); return AVERROR_INVALIDDATA; } /* get output buffer */ frame->nb_samples = RA288_BLOCK_SIZE * RA288_BLOCKS_PER_FRAME; if ((ret = ff_get_buffer(avctx, frame, 0)) < 0) return ret; out = (float *)frame->data[0]; init_get_bits8(&gb, buf, avctx->block_align); for (i=0; i < RA288_BLOCKS_PER_FRAME; i++) { float gain = amptable[get_bits(&gb, 3)]; int cb_coef = get_bits(&gb, 6 + (i&1)); decode(ractx, gain, cb_coef); memcpy(out, &ractx->sp_hist[70 + 36], RA288_BLOCK_SIZE * sizeof(*out)); out += RA288_BLOCK_SIZE; if ((i & 7) == 3) { backward_filter(ractx, ractx->sp_hist, ractx->sp_rec, syn_window, ractx->sp_lpc, syn_bw_tab, 36, 40, 35, 70); backward_filter(ractx, ractx->gain_hist, ractx->gain_rec, gain_window, ractx->gain_lpc, gain_bw_tab, 10, 8, 20, 28); } } *got_frame_ptr = 1; return avctx->block_align; }

int avcodec_check_dimensions(void *av_log_ctx, unsigned int w, unsigned int h){ if((int)w>0 && (int)h>0 && (w+128)*(uint64_t)(h+128) < INT_MAX/4) return 0; av_log(av_log_ctx, AV_LOG_ERROR, "picture size invalid (%ux%u)\n", w, h); return -1; }

static int find_unused_picture(MpegEncContext *s, int shared) { int i; if (shared) { for (i = 0; i < MAX_PICTURE_COUNT; i++) { if (s->picture[i].f.data[0] == NULL) return i; } } else { for (i = 0; i < MAX_PICTURE_COUNT; i++) { if (pic_is_unused(s, &s->picture[i])) return i; } } return AVERROR_INVALIDDATA; }

static int av_always_inline mlp_thd_probe(AVProbeData *p, uint32_t sync) { const uint8_t *buf, *last_buf = p->buf, *end = p->buf + p->buf_size; int frames = 0, valid = 0, size = 0; for (buf = p->buf; buf + 8 <= end; buf++) { if (AV_RB32(buf + 4) == sync) { frames++; if (last_buf + size == buf) { valid++; } last_buf = buf; size = (AV_RB16(buf) & 0xfff) * 2; } else if (buf - last_buf == size) { size += (AV_RB16(buf) & 0xfff) * 2; } } if (valid >= 100) return AVPROBE_SCORE_MAX; return 0; }

void gic_complete_irq(GICState *s, int cpu, int irq) { int update = 0; int cm = 1 << cpu; DPRINTF("EOI %d\n", irq); if (irq >= s->num_irq) { /* This handles two cases: * 1. If software writes the ID of a spurious interrupt [ie 1023] * to the GICC_EOIR, the GIC ignores that write. * 2. If software writes the number of a non-existent interrupt * this must be a subcase of "value written does not match the last * valid interrupt value read from the Interrupt Acknowledge * register" and so this is UNPREDICTABLE. We choose to ignore it. */ return; } if (s->running_irq[cpu] == 1023) return; /* No active IRQ. */ if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) { /* Mark level triggered interrupts as pending if they are still raised. */ if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm) && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) { DPRINTF("Set %d pending mask %x\n", irq, cm); GIC_SET_PENDING(irq, cm); update = 1; } } if (irq != s->running_irq[cpu]) { /* Complete an IRQ that is not currently running. */ int tmp = s->running_irq[cpu]; while (s->last_active[tmp][cpu] != 1023) { if (s->last_active[tmp][cpu] == irq) { s->last_active[tmp][cpu] = s->last_active[irq][cpu]; break; } tmp = s->last_active[tmp][cpu]; } if (update) { gic_update(s); } } else { /* Complete the current running IRQ. */ gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]); } }

static void core_commit(MemoryListener *listener) { PhysPageMap info = cur_map; cur_map = next_map; phys_sections_clear(&info); }

static int ppc_hash32_pte_update_flags(struct mmu_ctx_hash32 *ctx, target_ulong *pte1p, int ret, int rwx) { int store = 0; /* Update page flags */ if (!(*pte1p & HPTE32_R_R)) { /* Update accessed flag */ *pte1p |= HPTE32_R_R; store = 1; } if (!(*pte1p & HPTE32_R_C)) { if (rwx == 1 && ret == 0) { /* Update changed flag */ *pte1p |= HPTE32_R_C; store = 1; } else { /* Force page fault for first write access */ ctx->prot &= ~PAGE_WRITE; } } return store; }

static int raw_eject(BlockDriverState *bs, int eject_flag) { BDRVRawState *s = bs->opaque; switch(s->type) { case FTYPE_CD: if (eject_flag) { if (ioctl (s->fd, CDROMEJECT, NULL) < 0) perror("CDROMEJECT"); } else { if (ioctl (s->fd, CDROMCLOSETRAY, NULL) < 0) perror("CDROMEJECT"); } break; case FTYPE_FD: { int fd; if (s->fd >= 0) { close(s->fd); s->fd = -1; raw_close_fd_pool(s); } fd = open(bs->filename, s->fd_open_flags | O_NONBLOCK); if (fd >= 0) { if (ioctl(fd, FDEJECT, 0) < 0) perror("FDEJECT"); close(fd); } } break; default: return -ENOTSUP; } return 0; }

static void usage(void) { const struct qemu_argument *arginfo; int maxarglen; int maxenvlen; printf("usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n" "Linux CPU emulator (compiled for " TARGET_ARCH " emulation)\n" "\n" "Options and associated environment variables:\n" "\n"); maxarglen = maxenvlen = 0; for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { if (strlen(arginfo->env) > maxenvlen) { maxenvlen = strlen(arginfo->env); } if (strlen(arginfo->argv) > maxarglen) { maxarglen = strlen(arginfo->argv); } } printf("%-*s%-*sDescription\n", maxarglen+3, "Argument", maxenvlen+1, "Env-variable"); for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) { if (arginfo->has_arg) { printf("-%s %-*s %-*s %s\n", arginfo->argv, (int)(maxarglen-strlen(arginfo->argv)), arginfo->example, maxenvlen, arginfo->env, arginfo->help); } else { printf("-%-*s %-*s %s\n", maxarglen+1, arginfo->argv, maxenvlen, arginfo->env, arginfo->help); } } printf("\n" "Defaults:\n" "QEMU_LD_PREFIX = %s\n" "QEMU_STACK_SIZE = %ld byte\n", interp_prefix, guest_stack_size); printf("\n" "You can use -E and -U options or the QEMU_SET_ENV and\n" "QEMU_UNSET_ENV environment variables to set and unset\n" "environment variables for the target process.\n" "It is possible to provide several variables by separating them\n" "by commas in getsubopt(3) style. Additionally it is possible to\n" "provide the -E and -U options multiple times.\n" "The following lines are equivalent:\n" " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n" " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n" " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n" "Note that if you provide several changes to a single variable\n" "the last change will stay in effect.\n"); exit(1); }

static void qemu_rbd_complete_aio(RADOSCB *rcb) { RBDAIOCB *acb = rcb->acb; int64_t r; r = rcb->ret; if (acb->cmd == RBD_AIO_WRITE || acb->cmd == RBD_AIO_DISCARD) { if (r < 0) { acb->ret = r; acb->error = 1; } else if (!acb->error) { acb->ret = rcb->size; } } else { if (r < 0) { memset(rcb->buf, 0, rcb->size); acb->ret = r; acb->error = 1; } else if (r < rcb->size) { memset(rcb->buf + r, 0, rcb->size - r); if (!acb->error) { acb->ret = rcb->size; } } else if (!acb->error) { acb->ret = r; } } /* Note that acb->bh can be NULL in case where the aio was cancelled */ acb->bh = qemu_bh_new(rbd_aio_bh_cb, acb); qemu_bh_schedule(acb->bh); g_free(rcb); }

static gboolean gd_window_key_event(GtkWidget *widget, GdkEventKey *key, void *opaque) { GtkDisplayState *s = opaque; GtkAccelGroupEntry *entries; guint n_entries = 0; gboolean propagate_accel = TRUE; gboolean handled = FALSE; entries = gtk_accel_group_query(s->accel_group, key->keyval, key->state, &n_entries); if (n_entries) { const char *quark = g_quark_to_string(entries[0].accel_path_quark); if (gd_is_grab_active(s) && strstart(quark, "<QEMU>/File/", NULL)) { propagate_accel = FALSE; } } if (!handled && propagate_accel) { handled = gtk_window_activate_key(GTK_WINDOW(widget), key); } if (handled) { gtk_release_modifiers(s); } else { handled = gtk_window_propagate_key_event(GTK_WINDOW(widget), key); } return handled; }

static av_always_inline void hl_decode_mb_predict_luma(H264Context *h, int mb_type, int is_h264, int simple, int transform_bypass, int pixel_shift, int *block_offset, int linesize, uint8_t *dest_y, int p) { void (*idct_add)(uint8_t *dst, int16_t *block, int stride); void (*idct_dc_add)(uint8_t *dst, int16_t *block, int stride); int i; int qscale = p == 0 ? h->qscale : h->chroma_qp[p - 1]; block_offset += 16 * p; if (IS_INTRA4x4(mb_type)) { if (IS_8x8DCT(mb_type)) { if (transform_bypass) { idct_dc_add = idct_add = h->h264dsp.h264_add_pixels8_clear; } else { idct_dc_add = h->h264dsp.h264_idct8_dc_add; idct_add = h->h264dsp.h264_idct8_add; } for (i = 0; i < 16; i += 4) { uint8_t *const ptr = dest_y + block_offset[i]; const int dir = h->intra4x4_pred_mode_cache[scan8[i]]; if (transform_bypass && h->sps.profile_idc == 244 && dir <= 1) { h->hpc.pred8x8l_add[dir](ptr, h->mb + (i * 16 + p * 256 << pixel_shift), linesize); } else { const int nnz = h->non_zero_count_cache[scan8[i + p * 16]]; h->hpc.pred8x8l[dir](ptr, (h->topleft_samples_available << i) & 0x8000, (h->topright_samples_available << i) & 0x4000, linesize); if (nnz) { if (nnz == 1 && dctcoef_get(h->mb, pixel_shift, i * 16 + p * 256)) idct_dc_add(ptr, h->mb + (i * 16 + p * 256 << pixel_shift), linesize); else idct_add(ptr, h->mb + (i * 16 + p * 256 << pixel_shift), linesize); } } } } else { if (transform_bypass) { idct_dc_add = idct_add = h->h264dsp.h264_add_pixels4_clear; } else { idct_dc_add = h->h264dsp.h264_idct_dc_add; idct_add = h->h264dsp.h264_idct_add; } for (i = 0; i < 16; i++) { uint8_t *const ptr = dest_y + block_offset[i]; const int dir = h->intra4x4_pred_mode_cache[scan8[i]]; if (transform_bypass && h->sps.profile_idc == 244 && dir <= 1) { h->hpc.pred4x4_add[dir](ptr, h->mb + (i * 16 + p * 256 << pixel_shift), linesize); } else { uint8_t *topright; int nnz, tr; uint64_t tr_high; if (dir == DIAG_DOWN_LEFT_PRED || dir == VERT_LEFT_PRED) { const int topright_avail = (h->topright_samples_available << i) & 0x8000; av_assert2(h->mb_y || linesize <= block_offset[i]); if (!topright_avail) { if (pixel_shift) { tr_high = ((uint16_t *)ptr)[3 - linesize / 2] * 0x0001000100010001ULL; topright = (uint8_t *)&tr_high; } else { tr = ptr[3 - linesize] * 0x01010101u; topright = (uint8_t *)&tr; } } else topright = ptr + (4 << pixel_shift) - linesize; } else topright = NULL; h->hpc.pred4x4[dir](ptr, topright, linesize); nnz = h->non_zero_count_cache[scan8[i + p * 16]]; if (nnz) { if (is_h264) { if (nnz == 1 && dctcoef_get(h->mb, pixel_shift, i * 16 + p * 256)) idct_dc_add(ptr, h->mb + (i * 16 + p * 256 << pixel_shift), linesize); else idct_add(ptr, h->mb + (i * 16 + p * 256 << pixel_shift), linesize); } else if (CONFIG_SVQ3_DECODER) ff_svq3_add_idct_c(ptr, h->mb + i * 16 + p * 256, linesize, qscale, 0); } } } } } else { h->hpc.pred16x16[h->intra16x16_pred_mode](dest_y, linesize); if (is_h264) { if (h->non_zero_count_cache[scan8[LUMA_DC_BLOCK_INDEX + p]]) { if (!transform_bypass) h->h264dsp.h264_luma_dc_dequant_idct(h->mb + (p * 256 << pixel_shift), h->mb_luma_dc[p], h->dequant4_coeff[p][qscale][0]); else { static const uint8_t dc_mapping[16] = { 0 * 16, 1 * 16, 4 * 16, 5 * 16, 2 * 16, 3 * 16, 6 * 16, 7 * 16, 8 * 16, 9 * 16, 12 * 16, 13 * 16, 10 * 16, 11 * 16, 14 * 16, 15 * 16 }; for (i = 0; i < 16; i++) dctcoef_set(h->mb + (p * 256 << pixel_shift), pixel_shift, dc_mapping[i], dctcoef_get(h->mb_luma_dc[p], pixel_shift, i)); } } } else if (CONFIG_SVQ3_DECODER) ff_svq3_luma_dc_dequant_idct_c(h->mb + p * 256, h->mb_luma_dc[p], qscale); } }

static void mcf_fec_do_tx(mcf_fec_state *s) { uint32_t addr; mcf_fec_bd bd; int frame_size; int len; uint8_t frame[FEC_MAX_FRAME_SIZE]; uint8_t *ptr; DPRINTF("do_tx\n"); ptr = frame; frame_size = 0; addr = s->tx_descriptor; while (1) { mcf_fec_read_bd(&bd, addr); DPRINTF("tx_bd %x flags %04x len %d data %08x\n", addr, bd.flags, bd.length, bd.data); if ((bd.flags & FEC_BD_R) == 0) { /* Run out of descriptors to transmit. */ break; } len = bd.length; if (frame_size + len > FEC_MAX_FRAME_SIZE) { len = FEC_MAX_FRAME_SIZE - frame_size; s->eir |= FEC_INT_BABT; } cpu_physical_memory_read(bd.data, ptr, len); ptr += len; frame_size += len; if (bd.flags & FEC_BD_L) { /* Last buffer in frame. */ DPRINTF("Sending packet\n"); qemu_send_packet(qemu_get_queue(s->nic), frame, len); ptr = frame; frame_size = 0; s->eir |= FEC_INT_TXF; } s->eir |= FEC_INT_TXB; bd.flags &= ~FEC_BD_R; /* Write back the modified descriptor. */ mcf_fec_write_bd(&bd, addr); /* Advance to the next descriptor. */ if ((bd.flags & FEC_BD_W) != 0) { addr = s->etdsr; } else { addr += 8; } } s->tx_descriptor = addr; }

static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr, uint32_t val) { PCIBonitoState *s = opaque; uint32_t pciaddr; uint16_t status; DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x \n", addr, val); assert((addr&0x3)==0); pciaddr = bonito_sbridge_pciaddr(s, addr); if (pciaddr == 0xffffffff) { return; } /* set the pci address in s->config_reg */ s->pcihost->config_reg = (pciaddr) | (1u << 31); pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 4); /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ status = pci_get_word(s->dev.config + PCI_STATUS); status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); pci_set_word(s->dev.config + PCI_STATUS, status); }

void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0, DriveInfo *hd1, qemu_irq irq) { int i; DriveInfo *dinfo; for(i = 0; i < 2; i++) { dinfo = i == 0 ? hd0 : hd1; ide_init1(bus, i); if (dinfo) { if (ide_init_drive(&bus->ifs[i], dinfo->bdrv, dinfo->media_cd ? IDE_CD : IDE_HD, NULL, *dinfo->serial ? dinfo->serial : NULL) < 0) { error_report("Can't set up IDE drive %s", dinfo->id); exit(1); } bdrv_attach_dev_nofail(dinfo->bdrv, &bus->ifs[i]); } else { ide_reset(&bus->ifs[i]); } } bus->irq = irq; bus->dma = &ide_dma_nop; }

static void pxa2xx_ssp_write(void *opaque, hwaddr addr, uint64_t value64, unsigned size) { PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; uint32_t value = value64; switch (addr) { case SSCR0: s->sscr[0] = value & 0xc7ffffff; s->enable = value & SSCR0_SSE; if (value & SSCR0_MOD) printf("%s: Attempt to use network mode\n", __FUNCTION__); if (s->enable && SSCR0_DSS(value) < 4) printf("%s: Wrong data size: %i bits\n", __FUNCTION__, SSCR0_DSS(value)); if (!(value & SSCR0_SSE)) { s->sssr = 0; s->ssitr = 0; s->rx_level = 0; } pxa2xx_ssp_fifo_update(s); break; case SSCR1: s->sscr[1] = value; if (value & (SSCR1_LBM | SSCR1_EFWR)) printf("%s: Attempt to use SSP test mode\n", __FUNCTION__); pxa2xx_ssp_fifo_update(s); break; case SSPSP: s->sspsp = value; break; case SSTO: s->ssto = value; break; case SSITR: s->ssitr = value & SSITR_INT; pxa2xx_ssp_int_update(s); break; case SSSR: s->sssr &= ~(value & SSSR_RW); pxa2xx_ssp_int_update(s); break; case SSDR: if (SSCR0_UWIRE(s->sscr[0])) { if (s->sscr[1] & SSCR1_MWDS) value &= 0xffff; else value &= 0xff; } else /* Note how 32bits overflow does no harm here */ value &= (1 << SSCR0_DSS(s->sscr[0])) - 1; /* Data goes from here to the Tx FIFO and is shifted out from * there directly to the slave, no need to buffer it. */ if (s->enable) { uint32_t readval; readval = ssi_transfer(s->bus, value); if (s->rx_level < 0x10) { s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval; } else { s->sssr |= SSSR_ROR; } } pxa2xx_ssp_fifo_update(s); break; case SSTSA: s->sstsa = value; break; case SSRSA: s->ssrsa = value; break; case SSACD: s->ssacd = value; break; default: printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr); break; } }

static int pci_ne2000_init(PCIDevice *pci_dev) { PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev); NE2000State *s; uint8_t *pci_conf; pci_conf = d->dev.config; pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8029); pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); /* TODO: RST# value should be 0. PCI spec 6.2.4 */ pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0 pci_register_bar(&d->dev, 0, 0x100, PCI_BASE_ADDRESS_SPACE_IO, ne2000_map); s = &d->ne2000; s->irq = d->dev.irq[0]; qemu_macaddr_default_if_unset(&s->c.macaddr); ne2000_reset(s); s->nic = qemu_new_nic(&net_ne2000_info, &s->c, pci_dev->qdev.info->name, pci_dev->qdev.id, s); qemu_format_nic_info_str(&s->nic->nc, s->c.macaddr.a); if (!pci_dev->qdev.hotplugged) { static int loaded = 0; if (!loaded) { rom_add_option("pxe-ne2k_pci.rom", -1); loaded = 1; } } add_boot_device_path(s->c.bootindex, &pci_dev->qdev, "/ethernet-phy@0"); return 0; }

static void inc_refcounts(BlockDriverState *bs, uint16_t *refcount_table, int refcount_table_size, int64_t offset, int64_t size) { BDRVQcowState *s = bs->opaque; int64_t start, last, cluster_offset; int k; if (size <= 0) return; start = offset & ~(s->cluster_size - 1); last = (offset + size - 1) & ~(s->cluster_size - 1); for(cluster_offset = start; cluster_offset <= last; cluster_offset += s->cluster_size) { k = cluster_offset >> s->cluster_bits; if (k < 0 || k >= refcount_table_size) { fprintf(stderr, "ERROR: invalid cluster offset=0x%" PRIx64 "\n", cluster_offset); } else { if (++refcount_table[k] == 0) { fprintf(stderr, "ERROR: overflow cluster offset=0x%" PRIx64 "\n", cluster_offset); } } } }

static int pte_check_hash32(struct mmu_ctx_hash32 *ctx, target_ulong pte0, target_ulong pte1, int h, int rw, int type) { target_ulong mmask; int access, ret, pp; ret = -1; /* Check validity and table match */ if ((pte0 & HPTE32_V_VALID) && (h == !!(pte0 & HPTE32_V_SECONDARY))) { /* Check vsid & api */ mmask = PTE_CHECK_MASK; pp = pte1 & HPTE32_R_PP; if (HPTE32_V_COMPARE(pte0, ctx->ptem)) { if (ctx->raddr != (hwaddr)-1ULL) { /* all matches should have equal RPN, WIMG & PP */ if ((ctx->raddr & mmask) != (pte1 & mmask)) { qemu_log("Bad RPN/WIMG/PP\n"); return -3; } } /* Compute access rights */ access = ppc_hash32_pp_check(ctx->key, pp, ctx->nx); /* Keep the matching PTE informations */ ctx->raddr = pte1; ctx->prot = access; ret = ppc_hash32_check_prot(ctx->prot, rw, type); if (ret == 0) { /* Access granted */ LOG_MMU("PTE access granted !\n"); } else { /* Access right violation */ LOG_MMU("PTE access rejected\n"); } } } return ret; }

static int aio_read_f(int argc, char **argv) { int nr_iov, c; struct aio_ctx *ctx = calloc(1, sizeof(struct aio_ctx)); while ((c = getopt(argc, argv, "CP:qv")) != EOF) { switch (c) { case 'C': ctx->Cflag = 1; break; case 'P': ctx->Pflag = 1; ctx->pattern = parse_pattern(optarg); if (ctx->pattern < 0) { free(ctx); return 0; } break; case 'q': ctx->qflag = 1; break; case 'v': ctx->vflag = 1; break; default: free(ctx); return command_usage(&aio_read_cmd); } } if (optind > argc - 2) { free(ctx); return command_usage(&aio_read_cmd); } ctx->offset = cvtnum(argv[optind]); if (ctx->offset < 0) { printf("non-numeric length argument -- %s\n", argv[optind]); free(ctx); return 0; } optind++; if (ctx->offset & 0x1ff) { printf("offset %" PRId64 " is not sector aligned\n", ctx->offset); free(ctx); return 0; } nr_iov = argc - optind; ctx->buf = create_iovec(&ctx->qiov, &argv[optind], nr_iov, 0xab); if (ctx->buf == NULL) { free(ctx); return 0; } gettimeofday(&ctx->t1, NULL); bdrv_aio_readv(bs, ctx->offset >> 9, &ctx->qiov, ctx->qiov.size >> 9, aio_read_done, ctx); return 0; }

static void scsi_free_request(SCSIRequest *req) { SCSIDiskReq *r = DO_UPCAST(SCSIDiskReq, req, req); qemu_vfree(r->iov.iov_base); }

void ff_mjpeg_encode_picture_header(AVCodecContext *avctx, PutBitContext *pb, ScanTable *intra_scantable, uint16_t intra_matrix[64]) { int chroma_h_shift, chroma_v_shift; const int lossless = avctx->codec_id != AV_CODEC_ID_MJPEG; int hsample[3], vsample[3]; av_pix_fmt_get_chroma_sub_sample(avctx->pix_fmt, &chroma_h_shift, &chroma_v_shift); if (avctx->codec->id == AV_CODEC_ID_LJPEG && avctx->pix_fmt == AV_PIX_FMT_BGR24) { vsample[0] = hsample[0] = vsample[1] = hsample[1] = vsample[2] = hsample[2] = 1; } else { vsample[0] = 2; vsample[1] = 2 >> chroma_v_shift; vsample[2] = 2 >> chroma_v_shift; hsample[0] = 2; hsample[1] = 2 >> chroma_h_shift; hsample[2] = 2 >> chroma_h_shift; } put_marker(pb, SOI); jpeg_put_comments(avctx, pb); jpeg_table_header(pb, intra_scantable, intra_matrix); switch (avctx->codec_id) { case AV_CODEC_ID_MJPEG: put_marker(pb, SOF0 ); break; case AV_CODEC_ID_LJPEG: put_marker(pb, SOF3 ); break; default: assert(0); } put_bits(pb, 16, 17); if (lossless && avctx->pix_fmt == AV_PIX_FMT_BGR24) put_bits(pb, 8, 9); /* 9 bits/component RCT */ else put_bits(pb, 8, 8); /* 8 bits/component */ put_bits(pb, 16, avctx->height); put_bits(pb, 16, avctx->width); put_bits(pb, 8, 3); /* 3 components */ /* Y component */ put_bits(pb, 8, 1); /* component number */ put_bits(pb, 4, hsample[0]); /* H factor */ put_bits(pb, 4, vsample[0]); /* V factor */ put_bits(pb, 8, 0); /* select matrix */ /* Cb component */ put_bits(pb, 8, 2); /* component number */ put_bits(pb, 4, hsample[1]); /* H factor */ put_bits(pb, 4, vsample[1]); /* V factor */ put_bits(pb, 8, 0); /* select matrix */ /* Cr component */ put_bits(pb, 8, 3); /* component number */ put_bits(pb, 4, hsample[2]); /* H factor */ put_bits(pb, 4, vsample[2]); /* V factor */ put_bits(pb, 8, 0); /* select matrix */ /* scan header */ put_marker(pb, SOS); put_bits(pb, 16, 12); /* length */ put_bits(pb, 8, 3); /* 3 components */ /* Y component */ put_bits(pb, 8, 1); /* index */ put_bits(pb, 4, 0); /* DC huffman table index */ put_bits(pb, 4, 0); /* AC huffman table index */ /* Cb component */ put_bits(pb, 8, 2); /* index */ put_bits(pb, 4, 1); /* DC huffman table index */ put_bits(pb, 4, lossless ? 0 : 1); /* AC huffman table index */ /* Cr component */ put_bits(pb, 8, 3); /* index */ put_bits(pb, 4, 1); /* DC huffman table index */ put_bits(pb, 4, lossless ? 0 : 1); /* AC huffman table index */ put_bits(pb, 8, lossless ? avctx->prediction_method + 1 : 0); /* Ss (not used) */ switch (avctx->codec_id) { case AV_CODEC_ID_MJPEG: put_bits(pb, 8, 63); break; /* Se (not used) */ case AV_CODEC_ID_LJPEG: put_bits(pb, 8, 0); break; /* not used */ default: assert(0); } put_bits(pb, 8, 0); /* Ah/Al (not used) */ }

int qemu_paio_error(struct qemu_paiocb *aiocb) { ssize_t ret = qemu_paio_return(aiocb); if (ret < 0) ret = -ret; else ret = 0; return ret; }

static void arm_gic_common_reset(DeviceState *dev) { GICState *s = ARM_GIC_COMMON(dev); int i; memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); for (i = 0 ; i < s->num_cpu; i++) { if (s->revision == REV_11MPCORE) { s->priority_mask[i] = 0xf0; } else { s->priority_mask[i] = 0; } s->current_pending[i] = 1023; s->running_irq[i] = 1023; s->running_priority[i] = 0x100; s->cpu_enabled[i] = false; } for (i = 0; i < GIC_NR_SGIS; i++) { GIC_SET_ENABLED(i, ALL_CPU_MASK); GIC_SET_EDGE_TRIGGER(i); } if (s->num_cpu == 1) { /* For uniprocessor GICs all interrupts always target the sole CPU */ for (i = 0; i < GIC_MAXIRQ; i++) { s->irq_target[i] = 1; } } s->ctlr = 0; }

static int guess_disk_lchs(BlockDriverState *bs, int *pcylinders, int *pheads, int *psectors) { uint8_t buf[BDRV_SECTOR_SIZE]; int i, heads, sectors, cylinders; struct partition *p; uint32_t nr_sects; uint64_t nb_sectors; bdrv_get_geometry(bs, &nb_sectors); /** * The function will be invoked during startup not only in sync I/O mode, * but also in async I/O mode. So the I/O throttling function has to * be disabled temporarily here, not permanently. */ if (bdrv_read_unthrottled(bs, 0, buf, 1) < 0) { return -1; } /* test msdos magic */ if (buf[510] != 0x55 || buf[511] != 0xaa) { return -1; } for (i = 0; i < 4; i++) { p = ((struct partition *)(buf + 0x1be)) + i; nr_sects = le32_to_cpu(p->nr_sects); if (nr_sects && p->end_head) { /* We make the assumption that the partition terminates on a cylinder boundary */ heads = p->end_head + 1; sectors = p->end_sector & 63; if (sectors == 0) { continue; } cylinders = nb_sectors / (heads * sectors); if (cylinders < 1 || cylinders > 16383) { continue; } *pheads = heads; *psectors = sectors; *pcylinders = cylinders; trace_hd_geometry_lchs_guess(bs, cylinders, heads, sectors); return 0; } } return -1; }

static mode_t v9mode_to_mode(uint32_t mode, V9fsString *extension) { mode_t ret; ret = mode & 0777; if (mode & P9_STAT_MODE_DIR) { ret |= S_IFDIR; } if (mode & P9_STAT_MODE_SYMLINK) { ret |= S_IFLNK; } if (mode & P9_STAT_MODE_SOCKET) { ret |= S_IFSOCK; } if (mode & P9_STAT_MODE_NAMED_PIPE) { ret |= S_IFIFO; } if (mode & P9_STAT_MODE_DEVICE) { if (extension && extension->data[0] == 'c') { ret |= S_IFCHR; } else { ret |= S_IFBLK; } } if (!(ret&~0777)) { ret |= S_IFREG; } if (mode & P9_STAT_MODE_SETUID) { ret |= S_ISUID; } if (mode & P9_STAT_MODE_SETGID) { ret |= S_ISGID; } if (mode & P9_STAT_MODE_SETVTX) { ret |= S_ISVTX; } return ret; }

int kvm_cpu_exec(CPUState *cpu) { struct kvm_run *run = cpu->kvm_run; int ret, run_ret; DPRINTF("kvm_cpu_exec()\n"); if (kvm_arch_process_async_events(cpu)) { cpu->exit_request = 0; return EXCP_HLT; } do { MemTxAttrs attrs; if (cpu->kvm_vcpu_dirty) { kvm_arch_put_registers(cpu, KVM_PUT_RUNTIME_STATE); cpu->kvm_vcpu_dirty = false; } kvm_arch_pre_run(cpu, run); if (cpu->exit_request) { DPRINTF("interrupt exit requested\n"); /* * KVM requires us to reenter the kernel after IO exits to complete * instruction emulation. This self-signal will ensure that we * leave ASAP again. */ qemu_cpu_kick_self(); } qemu_mutex_unlock_iothread(); run_ret = kvm_vcpu_ioctl(cpu, KVM_RUN, 0); qemu_mutex_lock_iothread(); attrs = kvm_arch_post_run(cpu, run); if (run_ret < 0) { if (run_ret == -EINTR || run_ret == -EAGAIN) { DPRINTF("io window exit\n"); ret = EXCP_INTERRUPT; break; } fprintf(stderr, "error: kvm run failed %s\n", strerror(-run_ret)); #ifdef TARGET_PPC if (run_ret == -EBUSY) { fprintf(stderr, "This is probably because your SMT is enabled.\n" "VCPU can only run on primary threads with all " "secondary threads offline.\n"); } #endif ret = -1; break; } trace_kvm_run_exit(cpu->cpu_index, run->exit_reason); switch (run->exit_reason) { case KVM_EXIT_IO: DPRINTF("handle_io\n"); kvm_handle_io(run->io.port, attrs, (uint8_t *)run + run->io.data_offset, run->io.direction, run->io.size, run->io.count); ret = 0; break; case KVM_EXIT_MMIO: DPRINTF("handle_mmio\n"); address_space_rw(&address_space_memory, run->mmio.phys_addr, attrs, run->mmio.data, run->mmio.len, run->mmio.is_write); ret = 0; break; case KVM_EXIT_IRQ_WINDOW_OPEN: DPRINTF("irq_window_open\n"); ret = EXCP_INTERRUPT; break; case KVM_EXIT_SHUTDOWN: DPRINTF("shutdown\n"); qemu_system_reset_request(); ret = EXCP_INTERRUPT; break; case KVM_EXIT_UNKNOWN: fprintf(stderr, "KVM: unknown exit, hardware reason %" PRIx64 "\n", (uint64_t)run->hw.hardware_exit_reason); ret = -1; break; case KVM_EXIT_INTERNAL_ERROR: ret = kvm_handle_internal_error(cpu, run); break; case KVM_EXIT_SYSTEM_EVENT: switch (run->system_event.type) { case KVM_SYSTEM_EVENT_SHUTDOWN: qemu_system_shutdown_request(); ret = EXCP_INTERRUPT; break; case KVM_SYSTEM_EVENT_RESET: qemu_system_reset_request(); ret = EXCP_INTERRUPT; break; default: DPRINTF("kvm_arch_handle_exit\n"); ret = kvm_arch_handle_exit(cpu, run); break; } break; default: DPRINTF("kvm_arch_handle_exit\n"); ret = kvm_arch_handle_exit(cpu, run); break; } } while (ret == 0); if (ret < 0) { cpu_dump_state(cpu, stderr, fprintf, CPU_DUMP_CODE); vm_stop(RUN_STATE_INTERNAL_ERROR); } cpu->exit_request = 0; return ret; }

void HELPER(crypto_aese)(CPUARMState *env, uint32_t rd, uint32_t rm, uint32_t decrypt) { static uint8_t const sbox[][256] = { { /* S-box for encryption */ 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 }, { /* S-box for decryption */ 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb, 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25, 0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92, 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84, 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, 0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73, 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e, 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef, 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d } }; static uint8_t const shift[][16] = { /* ShiftRows permutation vector for encryption */ { 0, 5, 10, 15, 4, 9, 14, 3, 8, 13, 2, 7, 12, 1, 6, 11 }, /* ShiftRows permutation vector for decryption */ { 0, 13, 10, 7, 4, 1, 14, 11, 8, 5, 2, 15, 12, 9, 6, 3 }, }; union AES_STATE rk = { .l = { float64_val(env->vfp.regs[rm]), float64_val(env->vfp.regs[rm + 1]) } }; union AES_STATE st = { .l = { float64_val(env->vfp.regs[rd]), float64_val(env->vfp.regs[rd + 1]) } }; int i; assert(decrypt < 2); /* xor state vector with round key */ rk.l[0] ^= st.l[0]; rk.l[1] ^= st.l[1]; /* combine ShiftRows operation and sbox substitution */ for (i = 0; i < 16; i++) { st.bytes[i] = sbox[decrypt][rk.bytes[shift[decrypt][i]]]; } env->vfp.regs[rd] = make_float64(st.l[0]); env->vfp.regs[rd + 1] = make_float64(st.l[1]); }

Visitor *string_output_get_visitor(StringOutputVisitor *sov) { return &sov->visitor; }

static void spr_write_tbl (DisasContext *ctx, int sprn, int gprn) { if (use_icount) { gen_io_start(); } gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); if (use_icount) { gen_io_end(); gen_stop_exception(ctx); } }

static int mig_save_device_dirty(QEMUFile *f, BlkMigDevState *bmds, int is_async) { BlkMigBlock *blk; BlockDriverState *bs = blk_bs(bmds->blk); int64_t total_sectors = bmds->total_sectors; int64_t sector; int nr_sectors; int ret = -EIO; for (sector = bmds->cur_dirty; sector < bmds->total_sectors;) { blk_mig_lock(); if (bmds_aio_inflight(bmds, sector)) { blk_mig_unlock(); blk_drain(bmds->blk); } else { blk_mig_unlock(); } if (bdrv_get_dirty(bs, bmds->dirty_bitmap, sector)) { if (total_sectors - sector < BDRV_SECTORS_PER_DIRTY_CHUNK) { nr_sectors = total_sectors - sector; } else { nr_sectors = BDRV_SECTORS_PER_DIRTY_CHUNK; } bdrv_reset_dirty_bitmap(bmds->dirty_bitmap, sector, nr_sectors); blk = g_new(BlkMigBlock, 1); blk->buf = g_malloc(BLOCK_SIZE); blk->bmds = bmds; blk->sector = sector; blk->nr_sectors = nr_sectors; if (is_async) { blk->iov.iov_base = blk->buf; blk->iov.iov_len = nr_sectors * BDRV_SECTOR_SIZE; qemu_iovec_init_external(&blk->qiov, &blk->iov, 1); blk->aiocb = blk_aio_preadv(bmds->blk, sector * BDRV_SECTOR_SIZE, &blk->qiov, 0, blk_mig_read_cb, blk); blk_mig_lock(); block_mig_state.submitted++; bmds_set_aio_inflight(bmds, sector, nr_sectors, 1); blk_mig_unlock(); } else { ret = blk_pread(bmds->blk, sector * BDRV_SECTOR_SIZE, blk->buf, nr_sectors * BDRV_SECTOR_SIZE); if (ret < 0) { goto error; } blk_send(f, blk); g_free(blk->buf); g_free(blk); } sector += nr_sectors; bmds->cur_dirty = sector; break; } sector += BDRV_SECTORS_PER_DIRTY_CHUNK; bmds->cur_dirty = sector; } return (bmds->cur_dirty >= bmds->total_sectors); error: DPRINTF("Error reading sector %" PRId64 "\n", sector); g_free(blk->buf); g_free(blk); return ret; }

static int kvm_get_xcrs(X86CPU *cpu) { CPUX86State *env = &cpu->env; int i, ret; struct kvm_xcrs xcrs; if (!kvm_has_xcrs()) { return 0; } ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs); if (ret < 0) { return ret; } for (i = 0; i < xcrs.nr_xcrs; i++) { /* Only support xcr0 now */ if (xcrs.xcrs[i].xcr == 0) { env->xcr0 = xcrs.xcrs[i].value; break; } } return 0; }

uint64_t timer_expire_time_ns(QEMUTimer *ts) { return timer_pending(ts) ? ts->expire_time : -1; }

static int default_fdset_dup_fd_add(int64_t fdset_id, int dup_fd) { return -1; }

static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) { const char *rn = "invalid"; if (sel != 0) check_insn(env, ctx, ISA_MIPS32); switch (reg) { case 0: switch (sel) { case 0: gen_op_mfc0_index(); rn = "Index"; break; case 1: check_mips_mt(env, ctx); gen_op_mfc0_mvpcontrol(); rn = "MVPControl"; break; case 2: check_mips_mt(env, ctx); gen_op_mfc0_mvpconf0(); rn = "MVPConf0"; break; case 3: check_mips_mt(env, ctx); gen_op_mfc0_mvpconf1(); rn = "MVPConf1"; break; default: goto die; } break; case 1: switch (sel) { case 0: gen_op_mfc0_random(); rn = "Random"; break; case 1: check_mips_mt(env, ctx); gen_op_mfc0_vpecontrol(); rn = "VPEControl"; break; case 2: check_mips_mt(env, ctx); gen_op_mfc0_vpeconf0(); rn = "VPEConf0"; break; case 3: check_mips_mt(env, ctx); gen_op_mfc0_vpeconf1(); rn = "VPEConf1"; break; case 4: check_mips_mt(env, ctx); gen_op_mfc0_yqmask(); rn = "YQMask"; break; case 5: check_mips_mt(env, ctx); gen_op_mfc0_vpeschedule(); rn = "VPESchedule"; break; case 6: check_mips_mt(env, ctx); gen_op_mfc0_vpeschefback(); rn = "VPEScheFBack"; break; case 7: check_mips_mt(env, ctx); gen_op_mfc0_vpeopt(); rn = "VPEOpt"; break; default: goto die; } break; case 2: switch (sel) { case 0: gen_op_mfc0_entrylo0(); rn = "EntryLo0"; break; case 1: check_mips_mt(env, ctx); gen_op_mfc0_tcstatus(); rn = "TCStatus"; break; case 2: check_mips_mt(env, ctx); gen_op_mfc0_tcbind(); rn = "TCBind"; break; case 3: check_mips_mt(env, ctx); gen_op_mfc0_tcrestart(); rn = "TCRestart"; break; case 4: check_mips_mt(env, ctx); gen_op_mfc0_tchalt(); rn = "TCHalt"; break; case 5: check_mips_mt(env, ctx); gen_op_mfc0_tccontext(); rn = "TCContext"; break; case 6: check_mips_mt(env, ctx); gen_op_mfc0_tcschedule(); rn = "TCSchedule"; break; case 7: check_mips_mt(env, ctx); gen_op_mfc0_tcschefback(); rn = "TCScheFBack"; break; default: goto die; } break; case 3: switch (sel) { case 0: gen_op_mfc0_entrylo1(); rn = "EntryLo1"; break; default: goto die; } break; case 4: switch (sel) { case 0: gen_op_mfc0_context(); rn = "Context"; break; case 1: // gen_op_mfc0_contextconfig(); /* SmartMIPS ASE */ rn = "ContextConfig"; // break; default: goto die; } break; case 5: switch (sel) { case 0: gen_op_mfc0_pagemask(); rn = "PageMask"; break; case 1: check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_pagegrain(); rn = "PageGrain"; break; default: goto die; } break; case 6: switch (sel) { case 0: gen_op_mfc0_wired(); rn = "Wired"; break; case 1: check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_srsconf0(); rn = "SRSConf0"; break; case 2: check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_srsconf1(); rn = "SRSConf1"; break; case 3: check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_srsconf2(); rn = "SRSConf2"; break; case 4: check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_srsconf3(); rn = "SRSConf3"; break; case 5: check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_srsconf4(); rn = "SRSConf4"; break; default: goto die; } break; case 7: switch (sel) { case 0: check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_hwrena(); rn = "HWREna"; break; default: goto die; } break; case 8: switch (sel) { case 0: gen_op_mfc0_badvaddr(); rn = "BadVaddr"; break; default: goto die; } break; case 9: switch (sel) { case 0: gen_op_mfc0_count(); rn = "Count"; break; /* 6,7 are implementation dependent */ default: goto die; } break; case 10: switch (sel) { case 0: gen_op_mfc0_entryhi(); rn = "EntryHi"; break; default: goto die; } break; case 11: switch (sel) { case 0: gen_op_mfc0_compare(); rn = "Compare"; break; /* 6,7 are implementation dependent */ default: goto die; } break; case 12: switch (sel) { case 0: gen_op_mfc0_status(); rn = "Status"; break; case 1: check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_intctl(); rn = "IntCtl"; break; case 2: check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_srsctl(); rn = "SRSCtl"; break; case 3: check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_srsmap(); rn = "SRSMap"; break; default: goto die; } break; case 13: switch (sel) { case 0: gen_op_mfc0_cause(); rn = "Cause"; break; default: goto die; } break; case 14: switch (sel) { case 0: gen_op_mfc0_epc(); rn = "EPC"; break; default: goto die; } break; case 15: switch (sel) { case 0: gen_op_mfc0_prid(); rn = "PRid"; break; case 1: check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_ebase(); rn = "EBase"; break; default: goto die; } break; case 16: switch (sel) { case 0: gen_op_mfc0_config0(); rn = "Config"; break; case 1: gen_op_mfc0_config1(); rn = "Config1"; break; case 2: gen_op_mfc0_config2(); rn = "Config2"; break; case 3: gen_op_mfc0_config3(); rn = "Config3"; break; /* 4,5 are reserved */ /* 6,7 are implementation dependent */ case 6: gen_op_mfc0_config6(); rn = "Config6"; break; case 7: gen_op_mfc0_config7(); rn = "Config7"; break; default: goto die; } break; case 17: switch (sel) { case 0: gen_op_mfc0_lladdr(); rn = "LLAddr"; break; default: goto die; } break; case 18: switch (sel) { case 0 ... 7: gen_op_mfc0_watchlo(sel); rn = "WatchLo"; break; default: goto die; } break; case 19: switch (sel) { case 0 ...7: gen_op_mfc0_watchhi(sel); rn = "WatchHi"; break; default: goto die; } break; case 20: switch (sel) { case 0: #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) check_insn(env, ctx, ISA_MIPS3); gen_op_mfc0_xcontext(); rn = "XContext"; break; #endif default: goto die; } break; case 21: /* Officially reserved, but sel 0 is used for R1x000 framemask */ switch (sel) { case 0: gen_op_mfc0_framemask(); rn = "Framemask"; break; default: goto die; } break; case 22: /* ignored */ rn = "'Diagnostic"; /* implementation dependent */ break; case 23: switch (sel) { case 0: gen_op_mfc0_debug(); /* EJTAG support */ rn = "Debug"; break; case 1: // gen_op_mfc0_tracecontrol(); /* PDtrace support */ rn = "TraceControl"; // break; case 2: // gen_op_mfc0_tracecontrol2(); /* PDtrace support */ rn = "TraceControl2"; // break; case 3: // gen_op_mfc0_usertracedata(); /* PDtrace support */ rn = "UserTraceData"; // break; case 4: // gen_op_mfc0_debug(); /* PDtrace support */ rn = "TraceBPC"; // break; default: goto die; } break; case 24: switch (sel) { case 0: gen_op_mfc0_depc(); /* EJTAG support */ rn = "DEPC"; break; default: goto die; } break; case 25: switch (sel) { case 0: gen_op_mfc0_performance0(); rn = "Performance0"; break; case 1: // gen_op_mfc0_performance1(); rn = "Performance1"; // break; case 2: // gen_op_mfc0_performance2(); rn = "Performance2"; // break; case 3: // gen_op_mfc0_performance3(); rn = "Performance3"; // break; case 4: // gen_op_mfc0_performance4(); rn = "Performance4"; // break; case 5: // gen_op_mfc0_performance5(); rn = "Performance5"; // break; case 6: // gen_op_mfc0_performance6(); rn = "Performance6"; // break; case 7: // gen_op_mfc0_performance7(); rn = "Performance7"; // break; default: goto die; } break; case 26: rn = "ECC"; break; case 27: switch (sel) { /* ignored */ case 0 ... 3: rn = "CacheErr"; break; default: goto die; } break; case 28: switch (sel) { case 0: case 2: case 4: case 6: gen_op_mfc0_taglo(); rn = "TagLo"; break; case 1: case 3: case 5: case 7: gen_op_mfc0_datalo(); rn = "DataLo"; break; default: goto die; } break; case 29: switch (sel) { case 0: case 2: case 4: case 6: gen_op_mfc0_taghi(); rn = "TagHi"; break; case 1: case 3: case 5: case 7: gen_op_mfc0_datahi(); rn = "DataHi"; break; default: goto die; } break; case 30: switch (sel) { case 0: gen_op_mfc0_errorepc(); rn = "ErrorEPC"; break; default: goto die; } break; case 31: switch (sel) { case 0: gen_op_mfc0_desave(); /* EJTAG support */ rn = "DESAVE"; break; default: goto die; } break; default: goto die; } #if defined MIPS_DEBUG_DISAS if (loglevel & CPU_LOG_TB_IN_ASM) { fprintf(logfile, "mfc0 %s (reg %d sel %d)\n", rn, reg, sel); } #endif return; die: #if defined MIPS_DEBUG_DISAS if (loglevel & CPU_LOG_TB_IN_ASM) { fprintf(logfile, "mfc0 %s (reg %d sel %d)\n", rn, reg, sel); } #endif generate_exception(ctx, EXCP_RI); }

intptr_t (*checkasm_check_func(intptr_t (*func)(), const char *name, ...))() { char name_buf[256]; intptr_t (*ref)() = func; CheckasmFuncVersion *v; int name_length; va_list arg; va_start(arg, name); name_length = vsnprintf(name_buf, sizeof(name_buf), name, arg); va_end(arg); if (!func || name_length <= 0 || name_length >= sizeof(name_buf)) return NULL; state.current_func = get_func(name_buf, name_length); v = &state.current_func->versions; if (v->func) { CheckasmFuncVersion *prev; do { /* Only test functions that haven't already been tested */ if (v->func == func) return NULL; if (v->ok) ref = v->func; prev = v; } while ((v = v->next)); v = prev->next = checkasm_malloc(sizeof(CheckasmFuncVersion)); } v->func = func; v->ok = 1; v->cpu = state.cpu_flag; state.current_func_ver = v; if (state.cpu_flag) state.num_checked++; return ref; }

static hwaddr vfio_container_granularity(VFIOContainer *container) { return (hwaddr)1 << ctz64(container->iova_pgsizes); }

void apic_init_reset(DeviceState *dev) { APICCommonState *s = APIC_COMMON(dev); APICCommonClass *info = APIC_COMMON_GET_CLASS(s); int i; if (!s) { return; } s->tpr = 0; s->spurious_vec = 0xff; s->log_dest = 0; s->dest_mode = 0xf; memset(s->isr, 0, sizeof(s->isr)); memset(s->tmr, 0, sizeof(s->tmr)); memset(s->irr, 0, sizeof(s->irr)); for (i = 0; i < APIC_LVT_NB; i++) { s->lvt[i] = APIC_LVT_MASKED; } s->esr = 0; memset(s->icr, 0, sizeof(s->icr)); s->divide_conf = 0; s->count_shift = 0; s->initial_count = 0; s->initial_count_load_time = 0; s->next_time = 0; s->wait_for_sipi = !cpu_is_bsp(s->cpu); if (s->timer) { timer_del(s->timer); } s->timer_expiry = -1; if (info->reset) { info->reset(s); } }

static void gen_msa(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode = ctx->opcode; check_insn(ctx, ASE_MSA); check_msa_access(ctx); switch (MASK_MSA_MINOR(opcode)) { case OPC_MSA_I8_00: case OPC_MSA_I8_01: case OPC_MSA_I8_02: gen_msa_i8(env, ctx); break; case OPC_MSA_I5_06: case OPC_MSA_I5_07: gen_msa_i5(env, ctx); break; case OPC_MSA_BIT_09: case OPC_MSA_BIT_0A: gen_msa_bit(env, ctx); break; case OPC_MSA_3R_0D: case OPC_MSA_3R_0E: case OPC_MSA_3R_0F: case OPC_MSA_3R_10: case OPC_MSA_3R_11: case OPC_MSA_3R_12: case OPC_MSA_3R_13: case OPC_MSA_3R_14: case OPC_MSA_3R_15: gen_msa_3r(env, ctx); break; case OPC_MSA_ELM: gen_msa_elm(env, ctx); break; case OPC_MSA_3RF_1A: case OPC_MSA_3RF_1B: case OPC_MSA_3RF_1C: gen_msa_3rf(env, ctx); break; case OPC_MSA_VEC: gen_msa_vec(env, ctx); break; case OPC_LD_B: case OPC_LD_H: case OPC_LD_W: case OPC_LD_D: case OPC_ST_B: case OPC_ST_H: case OPC_ST_W: case OPC_ST_D: { int32_t s10 = sextract32(ctx->opcode, 16, 10); uint8_t rs = (ctx->opcode >> 11) & 0x1f; uint8_t wd = (ctx->opcode >> 6) & 0x1f; uint8_t df = (ctx->opcode >> 0) & 0x3; TCGv_i32 tdf = tcg_const_i32(df); TCGv_i32 twd = tcg_const_i32(wd); TCGv_i32 trs = tcg_const_i32(rs); TCGv_i32 ts10 = tcg_const_i32(s10); switch (MASK_MSA_MINOR(opcode)) { case OPC_LD_B: case OPC_LD_H: case OPC_LD_W: case OPC_LD_D: save_cpu_state(ctx, 1); gen_helper_msa_ld_df(cpu_env, tdf, twd, trs, ts10); break; case OPC_ST_B: case OPC_ST_H: case OPC_ST_W: case OPC_ST_D: save_cpu_state(ctx, 1); gen_helper_msa_st_df(cpu_env, tdf, twd, trs, ts10); break; } tcg_temp_free_i32(twd); tcg_temp_free_i32(tdf); tcg_temp_free_i32(trs); tcg_temp_free_i32(ts10); } break; default: MIPS_INVAL("MSA instruction"); generate_exception(ctx, EXCP_RI); break; } }

int bdrv_snapshot_load_tmp(BlockDriverState *bs, const char *snapshot_name) { BlockDriver *drv = bs->drv; if (!drv) { return -ENOMEDIUM; } if (!bs->read_only) { return -EINVAL; } if (drv->bdrv_snapshot_load_tmp) { return drv->bdrv_snapshot_load_tmp(bs, snapshot_name); } return -ENOTSUP; }

static void io_watch_poll_finalize(GSource *source) { IOWatchPoll *iwp = io_watch_poll_from_source(source); g_source_destroy(iwp->src); g_source_unref(iwp->src); iwp->src = NULL; }

static void omap_pin_cfg_init(MemoryRegion *system_memory, target_phys_addr_t base, struct omap_mpu_state_s *mpu) { memory_region_init_io(&mpu->pin_cfg_iomem, &omap_pin_cfg_ops, mpu, "omap-pin-cfg", 0x800); memory_region_add_subregion(system_memory, base, &mpu->pin_cfg_iomem); omap_pin_cfg_reset(mpu); }

void cpu_x86_inject_mce(CPUState *cenv, int bank, uint64_t status, uint64_t mcg_status, uint64_t addr, uint64_t misc, int broadcast) { unsigned bank_num = cenv->mcg_cap & 0xff; CPUState *env; int flag = 0; if (bank >= bank_num || !(status & MCI_STATUS_VAL)) { return; } if (broadcast) { if (!cpu_x86_support_mca_broadcast(cenv)) { fprintf(stderr, "Current CPU does not support broadcast\n"); return; } } if (kvm_enabled()) { if (broadcast) { flag |= MCE_BROADCAST; } kvm_inject_x86_mce(cenv, bank, status, mcg_status, addr, misc, flag); } else { qemu_inject_x86_mce(cenv, bank, status, mcg_status, addr, misc); if (broadcast) { for (env = first_cpu; env != NULL; env = env->next_cpu) { if (cenv == env) { continue; } qemu_inject_x86_mce(env, 1, MCI_STATUS_VAL | MCI_STATUS_UC, MCG_STATUS_MCIP | MCG_STATUS_RIPV, 0, 0); } } } }

static void psy_3gpp_analyze(FFPsyContext *ctx, int channel, const float *coefs, const FFPsyWindowInfo *wi) { AacPsyContext *pctx = (AacPsyContext*) ctx->model_priv_data; AacPsyChannel *pch = &pctx->ch[channel]; int start = 0; int i, w, g; const int num_bands = ctx->num_bands[wi->num_windows == 8]; const uint8_t* band_sizes = ctx->bands[wi->num_windows == 8]; AacPsyCoeffs *coeffs = &pctx->psy_coef[wi->num_windows == 8]; //calculate energies, initial thresholds and related values - 5.4.2 "Threshold Calculation" for (w = 0; w < wi->num_windows*16; w += 16) { for (g = 0; g < num_bands; g++) { AacPsyBand *band = &pch->band[w+g]; band->energy = 0.0f; for (i = 0; i < band_sizes[g]; i++) band->energy += coefs[start+i] * coefs[start+i]; band->thr = band->energy * 0.001258925f; start += band_sizes[g]; ctx->psy_bands[channel*PSY_MAX_BANDS+w+g].energy = band->energy; } } //modify thresholds - spread, threshold in quiet - 5.4.3 "Spreaded Energy Calculation" for (w = 0; w < wi->num_windows*16; w += 16) { AacPsyBand *band = &pch->band[w]; for (g = 1; g < num_bands; g++) band[g].thr = FFMAX(band[g].thr, band[g-1].thr * coeffs->spread_hi [g]); for (g = num_bands - 2; g >= 0; g--) band[g].thr = FFMAX(band[g].thr, band[g+1].thr * coeffs->spread_low[g]); for (g = 0; g < num_bands; g++) { band[g].thr_quiet = band[g].thr = FFMAX(band[g].thr, coeffs->ath[g]); if (!(wi->window_type[0] == LONG_STOP_SEQUENCE || (wi->window_type[1] == LONG_START_SEQUENCE && !w))) band[g].thr = FFMAX(PSY_3GPP_RPEMIN*band[g].thr, FFMIN(band[g].thr, PSY_3GPP_RPELEV*pch->prev_band[w+g].thr_quiet)); ctx->psy_bands[channel*PSY_MAX_BANDS+w+g].threshold = band[g].thr; } } memcpy(pch->prev_band, pch->band, sizeof(pch->band)); }

static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value) { int channel = addr >> DBDMA_CHANNEL_SHIFT; DBDMA_channel *ch = (DBDMA_channel *)opaque + channel; int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2; DBDMA_DPRINTF("writel 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value); DBDMA_DPRINTF("channel 0x%x reg 0x%x\n", (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg); /* cmdptr cannot be modified if channel is RUN or ACTIVE */ if (reg == DBDMA_CMDPTR_LO && (ch->regs[DBDMA_STATUS] & cpu_to_be32(RUN | ACTIVE))) return; ch->regs[reg] = value; switch(reg) { case DBDMA_CONTROL: dbdma_control_write(ch); break; case DBDMA_CMDPTR_LO: /* 16-byte aligned */ ch->regs[DBDMA_CMDPTR_LO] &= cpu_to_be32(~0xf); dbdma_cmdptr_load(ch); break; case DBDMA_STATUS: case DBDMA_INTR_SEL: case DBDMA_BRANCH_SEL: case DBDMA_WAIT_SEL: /* nothing to do */ break; case DBDMA_XFER_MODE: case DBDMA_CMDPTR_HI: case DBDMA_DATA2PTR_HI: case DBDMA_DATA2PTR_LO: case DBDMA_ADDRESS_HI: case DBDMA_BRANCH_ADDR_HI: case DBDMA_RES1: case DBDMA_RES2: case DBDMA_RES3: case DBDMA_RES4: /* unused */ break; } }

static uint64_t omap_os_timer_read(void *opaque, target_phys_addr_t addr, unsigned size) { struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; int offset = addr & OMAP_MPUI_REG_MASK; if (size != 4) { return omap_badwidth_read32(opaque, addr); } switch (offset) { case 0x00: /* TVR */ return s->timer.reset_val; case 0x04: /* TCR */ return omap_timer_read(&s->timer); case 0x08: /* CR */ return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; default: break; } OMAP_BAD_REG(addr); return 0; }

static uint64_t ahci_mem_read(void *opaque, target_phys_addr_t addr, unsigned size) { AHCIState *s = opaque; uint32_t val = 0; if (addr < AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR) { switch (addr) { case HOST_CAP: val = s->control_regs.cap; break; case HOST_CTL: val = s->control_regs.ghc; break; case HOST_IRQ_STAT: val = s->control_regs.irqstatus; break; case HOST_PORTS_IMPL: val = s->control_regs.impl; break; case HOST_VERSION: val = s->control_regs.version; break; } DPRINTF(-1, "(addr 0x%08X), val 0x%08X\n", (unsigned) addr, val); } else if ((addr >= AHCI_PORT_REGS_START_ADDR) && (addr < (AHCI_PORT_REGS_START_ADDR + (s->ports * AHCI_PORT_ADDR_OFFSET_LEN)))) { val = ahci_port_read(s, (addr - AHCI_PORT_REGS_START_ADDR) >> 7, addr & AHCI_PORT_ADDR_OFFSET_MASK); } return val; }

static inline uint16_t get_hwc_color(SM501State *state, int crt, int index) { uint32_t color_reg = 0; uint16_t color_565 = 0; if (index == 0) { return 0; } switch (index) { case 1: case 2: color_reg = crt ? state->dc_crt_hwc_color_1_2 : state->dc_panel_hwc_color_1_2; break; case 3: color_reg = crt ? state->dc_crt_hwc_color_3 : state->dc_panel_hwc_color_3; break; default: printf("invalid hw cursor color.\n"); abort(); } switch (index) { case 1: case 3: color_565 = (uint16_t)(color_reg & 0xFFFF); break; case 2: color_565 = (uint16_t)((color_reg >> 16) & 0xFFFF); break; } return color_565; }

mlt_compensate_output(COOKContext *q, float *decode_buffer, cook_gains *gains, float *previous_buffer, int16_t *out, int chan) { int j; cook_imlt(q, decode_buffer, q->mono_mdct_output); gain_compensate(q, gains, previous_buffer); /* Clip and convert floats to 16 bits. */ for (j = 0; j < q->samples_per_channel; j++) { out[chan + q->nb_channels * j] = av_clip(lrintf(q->mono_mdct_output[j]), -32768, 32767); } }

int main(int argc, char **argv){ int in_sample_rate, out_sample_rate, ch ,i, flush_count; uint64_t in_ch_layout, out_ch_layout; enum AVSampleFormat in_sample_fmt, out_sample_fmt; uint8_t array_in[SAMPLES*8*8]; uint8_t array_mid[SAMPLES*8*8*3]; uint8_t array_out[SAMPLES*8*8+100]; uint8_t *ain[SWR_CH_MAX]; uint8_t *aout[SWR_CH_MAX]; uint8_t *amid[SWR_CH_MAX]; int flush_i=0; int mode; int num_tests = 10000; uint32_t seed = 0; uint32_t rand_seed = 0; int remaining_tests[FF_ARRAY_ELEMS(rates) * FF_ARRAY_ELEMS(layouts) * FF_ARRAY_ELEMS(formats) * FF_ARRAY_ELEMS(layouts) * FF_ARRAY_ELEMS(formats)]; int max_tests = FF_ARRAY_ELEMS(remaining_tests); int test; int specific_test= -1; struct SwrContext * forw_ctx= NULL; struct SwrContext *backw_ctx= NULL; if (argc > 1) { if (!strcmp(argv[1], "-h") || !strcmp(argv[1], "--help")) { av_log(NULL, AV_LOG_INFO, "Usage: swresample-test [<num_tests>[ <test>]] \n" "num_tests Default is %d\n", num_tests); return 0; } num_tests = strtol(argv[1], NULL, 0); if(num_tests < 0) { num_tests = -num_tests; rand_seed = time(0); } if(num_tests<= 0 || num_tests>max_tests) num_tests = max_tests; if(argc > 2) { specific_test = strtol(argv[1], NULL, 0); } } for(i=0; i<max_tests; i++) remaining_tests[i] = i; for(test=0; test<num_tests; test++){ unsigned r; uint_rand(seed); r = (seed * (uint64_t)(max_tests - test)) >>32; FFSWAP(int, remaining_tests[r], remaining_tests[max_tests - test - 1]); } qsort(remaining_tests + max_tests - num_tests, num_tests, sizeof(remaining_tests[0]), (void*)cmp); in_sample_rate=16000; for(test=0; test<num_tests; test++){ char in_layout_string[256]; char out_layout_string[256]; unsigned vector= remaining_tests[max_tests - test - 1]; int in_ch_count; int out_count, mid_count, out_ch_count; in_ch_layout = layouts[vector % FF_ARRAY_ELEMS(layouts)]; vector /= FF_ARRAY_ELEMS(layouts); out_ch_layout = layouts[vector % FF_ARRAY_ELEMS(layouts)]; vector /= FF_ARRAY_ELEMS(layouts); in_sample_fmt = formats[vector % FF_ARRAY_ELEMS(formats)]; vector /= FF_ARRAY_ELEMS(formats); out_sample_fmt = formats[vector % FF_ARRAY_ELEMS(formats)]; vector /= FF_ARRAY_ELEMS(formats); out_sample_rate = rates [vector % FF_ARRAY_ELEMS(rates )]; vector /= FF_ARRAY_ELEMS(rates); av_assert0(!vector); if(specific_test == 0){ if(out_sample_rate != in_sample_rate || in_ch_layout != out_ch_layout) continue; } in_ch_count= av_get_channel_layout_nb_channels(in_ch_layout); out_ch_count= av_get_channel_layout_nb_channels(out_ch_layout); av_get_channel_layout_string( in_layout_string, sizeof( in_layout_string), in_ch_count, in_ch_layout); av_get_channel_layout_string(out_layout_string, sizeof(out_layout_string), out_ch_count, out_ch_layout); fprintf(stderr, "TEST: %s->%s, rate:%5d->%5d, fmt:%s->%s\n", in_layout_string, out_layout_string, in_sample_rate, out_sample_rate, av_get_sample_fmt_name(in_sample_fmt), av_get_sample_fmt_name(out_sample_fmt)); forw_ctx = swr_alloc_set_opts(forw_ctx, out_ch_layout, out_sample_fmt, out_sample_rate, in_ch_layout, in_sample_fmt, in_sample_rate, 0, 0); backw_ctx = swr_alloc_set_opts(backw_ctx, in_ch_layout, in_sample_fmt, in_sample_rate, out_ch_layout, out_sample_fmt, out_sample_rate, 0, 0); if(swr_init( forw_ctx) < 0) fprintf(stderr, "swr_init(->) failed\n"); if(swr_init(backw_ctx) < 0) fprintf(stderr, "swr_init(<-) failed\n"); if(!forw_ctx) fprintf(stderr, "Failed to init forw_cts\n"); if(!backw_ctx) fprintf(stderr, "Failed to init backw_ctx\n"); //FIXME test planar setup_array(ain , array_in , in_sample_fmt, SAMPLES); setup_array(amid, array_mid, out_sample_fmt, 3*SAMPLES); setup_array(aout, array_out, in_sample_fmt , SAMPLES); #if 0 for(ch=0; ch<in_ch_count; ch++){ for(i=0; i<SAMPLES; i++) set(ain, ch, i, in_ch_count, in_sample_fmt, sin(i*i*3/SAMPLES)); } #else audiogen(ain, in_sample_fmt, in_ch_count, SAMPLES/6+1, SAMPLES); #endif mode = uint_rand(rand_seed) % 3; if(mode==0 /*|| out_sample_rate == in_sample_rate*/) { mid_count= swr_convert(forw_ctx, amid, 3*SAMPLES, (const uint8_t **)ain, SAMPLES); } else if(mode==1){ mid_count= swr_convert(forw_ctx, amid, 0, (const uint8_t **)ain, SAMPLES); mid_count+=swr_convert(forw_ctx, amid, 3*SAMPLES, (const uint8_t **)ain, 0); } else { int tmp_count; mid_count= swr_convert(forw_ctx, amid, 0, (const uint8_t **)ain, 1); av_assert0(mid_count==0); shift(ain, 1, in_ch_count, in_sample_fmt); mid_count+=swr_convert(forw_ctx, amid, 3*SAMPLES, (const uint8_t **)ain, 0); shift(amid, mid_count, out_ch_count, out_sample_fmt); tmp_count = mid_count; mid_count+=swr_convert(forw_ctx, amid, 2, (const uint8_t **)ain, 2); shift(amid, mid_count-tmp_count, out_ch_count, out_sample_fmt); tmp_count = mid_count; shift(ain, 2, in_ch_count, in_sample_fmt); mid_count+=swr_convert(forw_ctx, amid, 1, (const uint8_t **)ain, SAMPLES-3); shift(amid, mid_count-tmp_count, out_ch_count, out_sample_fmt); tmp_count = mid_count; shift(ain, -3, in_ch_count, in_sample_fmt); mid_count+=swr_convert(forw_ctx, amid, 3*SAMPLES, (const uint8_t **)ain, 0); shift(amid, -tmp_count, out_ch_count, out_sample_fmt); } out_count= swr_convert(backw_ctx,aout, SAMPLES, (const uint8_t **)amid, mid_count); for(ch=0; ch<in_ch_count; ch++){ double sse, maxdiff=0; double sum_a= 0; double sum_b= 0; double sum_aa= 0; double sum_bb= 0; double sum_ab= 0; for(i=0; i<out_count; i++){ double a= get(ain , ch, i, in_ch_count, in_sample_fmt); double b= get(aout, ch, i, in_ch_count, in_sample_fmt); sum_a += a; sum_b += b; sum_aa+= a*a; sum_bb+= b*b; sum_ab+= a*b; maxdiff= FFMAX(maxdiff, FFABS(a-b)); } sse= sum_aa + sum_bb - 2*sum_ab; if(sse < 0 && sse > -0.00001) sse=0; //fix rounding error fprintf(stderr, "[e:%f c:%f max:%f] len:%5d\n", sqrt(sse/out_count), sum_ab/(sqrt(sum_aa*sum_bb)), maxdiff, out_count); } flush_i++; flush_i%=21; flush_count = swr_convert(backw_ctx,aout, flush_i, 0, 0); shift(aout, flush_i, in_ch_count, in_sample_fmt); flush_count+= swr_convert(backw_ctx,aout, SAMPLES-flush_i, 0, 0); shift(aout, -flush_i, in_ch_count, in_sample_fmt); if(flush_count){ for(ch=0; ch<in_ch_count; ch++){ double sse, maxdiff=0; double sum_a= 0; double sum_b= 0; double sum_aa= 0; double sum_bb= 0; double sum_ab= 0; for(i=0; i<flush_count; i++){ double a= get(ain , ch, i+out_count, in_ch_count, in_sample_fmt); double b= get(aout, ch, i, in_ch_count, in_sample_fmt); sum_a += a; sum_b += b; sum_aa+= a*a; sum_bb+= b*b; sum_ab+= a*b; maxdiff= FFMAX(maxdiff, FFABS(a-b)); } sse= sum_aa + sum_bb - 2*sum_ab; if(sse < 0 && sse > -0.00001) sse=0; //fix rounding error fprintf(stderr, "[e:%f c:%f max:%f] len:%5d F:%3d\n", sqrt(sse/flush_count), sum_ab/(sqrt(sum_aa*sum_bb)), maxdiff, flush_count, flush_i); } } fprintf(stderr, "\n"); } return 0; }

void MPV_decode_mb_internal(MpegEncContext *s, DCTELEM block[12][64], int is_mpeg12) { const int mb_xy = s->mb_y * s->mb_stride + s->mb_x; if(CONFIG_MPEG_XVMC_DECODER && s->avctx->xvmc_acceleration){ ff_xvmc_decode_mb(s);//xvmc uses pblocks return; } if(s->avctx->debug&FF_DEBUG_DCT_COEFF) { /* save DCT coefficients */ int i,j; DCTELEM *dct = &s->current_picture.f.dct_coeff[mb_xy * 64 * 6]; av_log(s->avctx, AV_LOG_DEBUG, "DCT coeffs of MB at %dx%d:\n", s->mb_x, s->mb_y); for(i=0; i<6; i++){ for(j=0; j<64; j++){ *dct++ = block[i][s->dsp.idct_permutation[j]]; av_log(s->avctx, AV_LOG_DEBUG, "%5d", dct[-1]); } av_log(s->avctx, AV_LOG_DEBUG, "\n"); } } s->current_picture.f.qscale_table[mb_xy] = s->qscale; /* update DC predictors for P macroblocks */ if (!s->mb_intra) { if (!is_mpeg12 && (s->h263_pred || s->h263_aic)) { if(s->mbintra_table[mb_xy]) ff_clean_intra_table_entries(s); } else { s->last_dc[0] = s->last_dc[1] = s->last_dc[2] = 128 << s->intra_dc_precision; } } else if (!is_mpeg12 && (s->h263_pred || s->h263_aic)) s->mbintra_table[mb_xy]=1; if ((s->flags&CODEC_FLAG_PSNR) || !(s->encoding && (s->intra_only || s->pict_type==AV_PICTURE_TYPE_B) && s->avctx->mb_decision != FF_MB_DECISION_RD)) { //FIXME precalc uint8_t *dest_y, *dest_cb, *dest_cr; int dct_linesize, dct_offset; op_pixels_func (*op_pix)[4]; qpel_mc_func (*op_qpix)[16]; const int linesize = s->current_picture.f.linesize[0]; //not s->linesize as this would be wrong for field pics const int uvlinesize = s->current_picture.f.linesize[1]; const int readable= s->pict_type != AV_PICTURE_TYPE_B || s->encoding || s->avctx->draw_horiz_band; const int block_size = 8; /* avoid copy if macroblock skipped in last frame too */ /* skip only during decoding as we might trash the buffers during encoding a bit */ if(!s->encoding){ uint8_t *mbskip_ptr = &s->mbskip_table[mb_xy]; if (s->mb_skipped) { s->mb_skipped= 0; assert(s->pict_type!=AV_PICTURE_TYPE_I); *mbskip_ptr = 1; } else if(!s->current_picture.f.reference) { *mbskip_ptr = 1; } else{ *mbskip_ptr = 0; /* not skipped */ } } dct_linesize = linesize << s->interlaced_dct; dct_offset = s->interlaced_dct ? linesize : linesize * block_size; if(readable){ dest_y= s->dest[0]; dest_cb= s->dest[1]; dest_cr= s->dest[2]; }else{ dest_y = s->b_scratchpad; dest_cb= s->b_scratchpad+16*linesize; dest_cr= s->b_scratchpad+32*linesize; } if (!s->mb_intra) { /* motion handling */ /* decoding or more than one mb_type (MC was already done otherwise) */ if(!s->encoding){ if(HAVE_THREADS && s->avctx->active_thread_type&FF_THREAD_FRAME) { if (s->mv_dir & MV_DIR_FORWARD) { ff_thread_await_progress(&s->last_picture_ptr->f, ff_MPV_lowest_referenced_row(s, 0), 0); } if (s->mv_dir & MV_DIR_BACKWARD) { ff_thread_await_progress(&s->next_picture_ptr->f, ff_MPV_lowest_referenced_row(s, 1), 0); } } op_qpix= s->me.qpel_put; if ((!s->no_rounding) || s->pict_type==AV_PICTURE_TYPE_B){ op_pix = s->dsp.put_pixels_tab; }else{ op_pix = s->dsp.put_no_rnd_pixels_tab; } if (s->mv_dir & MV_DIR_FORWARD) { MPV_motion(s, dest_y, dest_cb, dest_cr, 0, s->last_picture.f.data, op_pix, op_qpix); op_pix = s->dsp.avg_pixels_tab; op_qpix= s->me.qpel_avg; } if (s->mv_dir & MV_DIR_BACKWARD) { MPV_motion(s, dest_y, dest_cb, dest_cr, 1, s->next_picture.f.data, op_pix, op_qpix); } } /* skip dequant / idct if we are really late ;) */ if(s->avctx->skip_idct){ if( (s->avctx->skip_idct >= AVDISCARD_NONREF && s->pict_type == AV_PICTURE_TYPE_B) ||(s->avctx->skip_idct >= AVDISCARD_NONKEY && s->pict_type != AV_PICTURE_TYPE_I) || s->avctx->skip_idct >= AVDISCARD_ALL) goto skip_idct; } /* add dct residue */ if(s->encoding || !( s->msmpeg4_version || s->codec_id==CODEC_ID_MPEG1VIDEO || s->codec_id==CODEC_ID_MPEG2VIDEO || (s->codec_id==CODEC_ID_MPEG4 && !s->mpeg_quant))){ add_dequant_dct(s, block[0], 0, dest_y , dct_linesize, s->qscale); add_dequant_dct(s, block[1], 1, dest_y + block_size, dct_linesize, s->qscale); add_dequant_dct(s, block[2], 2, dest_y + dct_offset , dct_linesize, s->qscale); add_dequant_dct(s, block[3], 3, dest_y + dct_offset + block_size, dct_linesize, s->qscale); if(!CONFIG_GRAY || !(s->flags&CODEC_FLAG_GRAY)){ if (s->chroma_y_shift){ add_dequant_dct(s, block[4], 4, dest_cb, uvlinesize, s->chroma_qscale); add_dequant_dct(s, block[5], 5, dest_cr, uvlinesize, s->chroma_qscale); }else{ dct_linesize >>= 1; dct_offset >>=1; add_dequant_dct(s, block[4], 4, dest_cb, dct_linesize, s->chroma_qscale); add_dequant_dct(s, block[5], 5, dest_cr, dct_linesize, s->chroma_qscale); add_dequant_dct(s, block[6], 6, dest_cb + dct_offset, dct_linesize, s->chroma_qscale); add_dequant_dct(s, block[7], 7, dest_cr + dct_offset, dct_linesize, s->chroma_qscale); } } } else if(is_mpeg12 || (s->codec_id != CODEC_ID_WMV2)){ add_dct(s, block[0], 0, dest_y , dct_linesize); add_dct(s, block[1], 1, dest_y + block_size, dct_linesize); add_dct(s, block[2], 2, dest_y + dct_offset , dct_linesize); add_dct(s, block[3], 3, dest_y + dct_offset + block_size, dct_linesize); if(!CONFIG_GRAY || !(s->flags&CODEC_FLAG_GRAY)){ if(s->chroma_y_shift){//Chroma420 add_dct(s, block[4], 4, dest_cb, uvlinesize); add_dct(s, block[5], 5, dest_cr, uvlinesize); }else{ //chroma422 dct_linesize = uvlinesize << s->interlaced_dct; dct_offset = s->interlaced_dct ? uvlinesize : uvlinesize*block_size; add_dct(s, block[4], 4, dest_cb, dct_linesize); add_dct(s, block[5], 5, dest_cr, dct_linesize); add_dct(s, block[6], 6, dest_cb+dct_offset, dct_linesize); add_dct(s, block[7], 7, dest_cr+dct_offset, dct_linesize); if(!s->chroma_x_shift){//Chroma444 add_dct(s, block[8], 8, dest_cb+block_size, dct_linesize); add_dct(s, block[9], 9, dest_cr+block_size, dct_linesize); add_dct(s, block[10], 10, dest_cb+block_size+dct_offset, dct_linesize); add_dct(s, block[11], 11, dest_cr+block_size+dct_offset, dct_linesize); } } }//fi gray } else if (CONFIG_WMV2_DECODER || CONFIG_WMV2_ENCODER) { ff_wmv2_add_mb(s, block, dest_y, dest_cb, dest_cr); } } else { /* dct only in intra block */ if(s->encoding || !(s->codec_id==CODEC_ID_MPEG1VIDEO || s->codec_id==CODEC_ID_MPEG2VIDEO)){ put_dct(s, block[0], 0, dest_y , dct_linesize, s->qscale); put_dct(s, block[1], 1, dest_y + block_size, dct_linesize, s->qscale); put_dct(s, block[2], 2, dest_y + dct_offset , dct_linesize, s->qscale); put_dct(s, block[3], 3, dest_y + dct_offset + block_size, dct_linesize, s->qscale); if(!CONFIG_GRAY || !(s->flags&CODEC_FLAG_GRAY)){ if(s->chroma_y_shift){ put_dct(s, block[4], 4, dest_cb, uvlinesize, s->chroma_qscale); put_dct(s, block[5], 5, dest_cr, uvlinesize, s->chroma_qscale); }else{ dct_offset >>=1; dct_linesize >>=1; put_dct(s, block[4], 4, dest_cb, dct_linesize, s->chroma_qscale); put_dct(s, block[5], 5, dest_cr, dct_linesize, s->chroma_qscale); put_dct(s, block[6], 6, dest_cb + dct_offset, dct_linesize, s->chroma_qscale); put_dct(s, block[7], 7, dest_cr + dct_offset, dct_linesize, s->chroma_qscale); } } }else{ s->dsp.idct_put(dest_y , dct_linesize, block[0]); s->dsp.idct_put(dest_y + block_size, dct_linesize, block[1]); s->dsp.idct_put(dest_y + dct_offset , dct_linesize, block[2]); s->dsp.idct_put(dest_y + dct_offset + block_size, dct_linesize, block[3]); if(!CONFIG_GRAY || !(s->flags&CODEC_FLAG_GRAY)){ if(s->chroma_y_shift){ s->dsp.idct_put(dest_cb, uvlinesize, block[4]); s->dsp.idct_put(dest_cr, uvlinesize, block[5]); }else{ dct_linesize = uvlinesize << s->interlaced_dct; dct_offset = s->interlaced_dct? uvlinesize : uvlinesize*block_size; s->dsp.idct_put(dest_cb, dct_linesize, block[4]); s->dsp.idct_put(dest_cr, dct_linesize, block[5]); s->dsp.idct_put(dest_cb + dct_offset, dct_linesize, block[6]); s->dsp.idct_put(dest_cr + dct_offset, dct_linesize, block[7]); if(!s->chroma_x_shift){//Chroma444 s->dsp.idct_put(dest_cb + block_size, dct_linesize, block[8]); s->dsp.idct_put(dest_cr + block_size, dct_linesize, block[9]); s->dsp.idct_put(dest_cb + block_size + dct_offset, dct_linesize, block[10]); s->dsp.idct_put(dest_cr + block_size + dct_offset, dct_linesize, block[11]); } } }//gray } } skip_idct: if(!readable){ s->dsp.put_pixels_tab[0][0](s->dest[0], dest_y , linesize,16); s->dsp.put_pixels_tab[s->chroma_x_shift][0](s->dest[1], dest_cb, uvlinesize,16 >> s->chroma_y_shift); s->dsp.put_pixels_tab[s->chroma_x_shift][0](s->dest[2], dest_cr, uvlinesize,16 >> s->chroma_y_shift); } } }

int ff_h264_decode_ref_pic_marking(H264Context *h, GetBitContext *gb, int first_slice) { int i, ret; MMCO mmco_temp[MAX_MMCO_COUNT], *mmco = mmco_temp; int mmco_index = 0; if (h->nal_unit_type == NAL_IDR_SLICE) { // FIXME fields skip_bits1(gb); // broken_link if (get_bits1(gb)) { mmco[0].opcode = MMCO_LONG; mmco[0].long_arg = 0; mmco_index = 1; } } else { if (get_bits1(gb)) { // adaptive_ref_pic_marking_mode_flag for (i = 0; i < MAX_MMCO_COUNT; i++) { MMCOOpcode opcode = get_ue_golomb_31(gb); mmco[i].opcode = opcode; if (opcode == MMCO_SHORT2UNUSED || opcode == MMCO_SHORT2LONG) { mmco[i].short_pic_num = (h->curr_pic_num - get_ue_golomb(gb) - 1) & (h->max_pic_num - 1); #if 0 if (mmco[i].short_pic_num >= h->short_ref_count || !h->short_ref[mmco[i].short_pic_num]) { av_log(s->avctx, AV_LOG_ERROR, "illegal short ref in memory management control " "operation %d\n", mmco); return -1; } #endif } if (opcode == MMCO_SHORT2LONG || opcode == MMCO_LONG2UNUSED || opcode == MMCO_LONG || opcode == MMCO_SET_MAX_LONG) { unsigned int long_arg = get_ue_golomb_31(gb); if (long_arg >= 32 || (long_arg >= 16 && !(opcode == MMCO_SET_MAX_LONG && long_arg == 16) && !(opcode == MMCO_LONG2UNUSED && FIELD_PICTURE(h)))) { av_log(h->avctx, AV_LOG_ERROR, "illegal long ref in memory management control " "operation %d\n", opcode); return -1; } mmco[i].long_arg = long_arg; } if (opcode > (unsigned) MMCO_LONG) { av_log(h->avctx, AV_LOG_ERROR, "illegal memory management control operation %d\n", opcode); return -1; } if (opcode == MMCO_END) break; } mmco_index = i; } else { if (first_slice) { ret = ff_generate_sliding_window_mmcos(h, first_slice); if (ret < 0 && h->avctx->err_recognition & AV_EF_EXPLODE) return ret; } mmco_index = -1; } } if (first_slice && mmco_index != -1) { memcpy(h->mmco, mmco_temp, sizeof(h->mmco)); h->mmco_index = mmco_index; } else if (!first_slice && mmco_index >= 0 && (mmco_index != h->mmco_index || check_opcodes(h->mmco, mmco_temp, mmco_index))) { av_log(h->avctx, AV_LOG_ERROR, "Inconsistent MMCO state between slices [%d, %d]\n", mmco_index, h->mmco_index); return AVERROR_INVALIDDATA; } return 0; }

static int init_input_stream(int ist_index, char *error, int error_len) { int i; InputStream *ist = input_streams[ist_index]; if (ist->decoding_needed) { AVCodec *codec = ist->dec; if (!codec) { snprintf(error, error_len, "Decoder (codec id %d) not found for input stream #%d:%d", ist->st->codec->codec_id, ist->file_index, ist->st->index); return AVERROR(EINVAL); } /* update requested sample format for the decoder based on the corresponding encoder sample format */ for (i = 0; i < nb_output_streams; i++) { OutputStream *ost = output_streams[i]; if (ost->source_index == ist_index) { update_sample_fmt(ist->st->codec, codec, ost->st->codec); break; } } if (codec->type == AVMEDIA_TYPE_VIDEO && codec->capabilities & CODEC_CAP_DR1) { ist->st->codec->get_buffer = codec_get_buffer; ist->st->codec->release_buffer = codec_release_buffer; ist->st->codec->opaque = &ist->buffer_pool; } if (!av_dict_get(ist->opts, "threads", NULL, 0)) av_dict_set(&ist->opts, "threads", "auto", 0); if (avcodec_open2(ist->st->codec, codec, &ist->opts) < 0) { snprintf(error, error_len, "Error while opening decoder for input stream #%d:%d", ist->file_index, ist->st->index); return AVERROR(EINVAL); } assert_codec_experimental(ist->st->codec, 0); assert_avoptions(ist->opts); } ist->last_dts = ist->st->avg_frame_rate.num ? - ist->st->codec->has_b_frames * AV_TIME_BASE / av_q2d(ist->st->avg_frame_rate) : 0; ist->next_dts = AV_NOPTS_VALUE; init_pts_correction(&ist->pts_ctx); ist->is_start = 1; return 0; }

build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) { Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa); tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT); tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length)); bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1, false /* high memory */); /* log area start address to be filled by Guest linker */ bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, ACPI_BUILD_TPMLOG_FILE, &tcpa->log_area_start_address, sizeof(tcpa->log_area_start_address)); build_header(linker, table_data, (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL); }

static CharDriverState *qemu_chr_open_udp_fd(int fd) { CharDriverState *chr = NULL; NetCharDriver *s = NULL; chr = g_malloc0(sizeof(CharDriverState)); s = g_malloc0(sizeof(NetCharDriver)); s->fd = fd; s->chan = io_channel_from_socket(s->fd); s->bufcnt = 0; s->bufptr = 0; chr->opaque = s; chr->chr_write = udp_chr_write; chr->chr_update_read_handler = udp_chr_update_read_handler; chr->chr_close = udp_chr_close; /* be isn't opened until we get a connection */ chr->explicit_be_open = true; return chr; }

static int get_pix_fmt_score(enum AVPixelFormat dst_pix_fmt, enum AVPixelFormat src_pix_fmt, unsigned *lossp, unsigned consider) { const AVPixFmtDescriptor *src_desc = av_pix_fmt_desc_get(src_pix_fmt); const AVPixFmtDescriptor *dst_desc = av_pix_fmt_desc_get(dst_pix_fmt); int src_color, dst_color; int src_min_depth, src_max_depth, dst_min_depth, dst_max_depth; int ret, loss, i, nb_components; int score = INT_MAX - 1; if (dst_pix_fmt >= AV_PIX_FMT_NB || dst_pix_fmt <= AV_PIX_FMT_NONE) return ~0; /* compute loss */ *lossp = loss = 0; if (dst_pix_fmt == src_pix_fmt) return INT_MAX; if ((ret = get_pix_fmt_depth(&src_min_depth, &src_max_depth, src_pix_fmt)) < 0) return ret; if ((ret = get_pix_fmt_depth(&dst_min_depth, &dst_max_depth, dst_pix_fmt)) < 0) return ret; src_color = get_color_type(src_desc); dst_color = get_color_type(dst_desc); if (dst_pix_fmt == AV_PIX_FMT_PAL8) nb_components = FFMIN(src_desc->nb_components, 4); else nb_components = FFMIN(src_desc->nb_components, dst_desc->nb_components); for (i = 0; i < nb_components; i++) { int depth_minus1 = (dst_pix_fmt == AV_PIX_FMT_PAL8) ? 7/nb_components : (dst_desc->comp[i].depth - 1); if (src_desc->comp[i].depth - 1 > depth_minus1 && (consider & FF_LOSS_DEPTH)) { loss |= FF_LOSS_DEPTH; score -= 65536 >> depth_minus1; } } if (consider & FF_LOSS_RESOLUTION) { if (dst_desc->log2_chroma_w > src_desc->log2_chroma_w) { loss |= FF_LOSS_RESOLUTION; score -= 256 << dst_desc->log2_chroma_w; } if (dst_desc->log2_chroma_h > src_desc->log2_chroma_h) { loss |= FF_LOSS_RESOLUTION; score -= 256 << dst_desc->log2_chroma_h; } // don't favor 422 over 420 if downsampling is needed, because 420 has much better support on the decoder side if (dst_desc->log2_chroma_w == 1 && src_desc->log2_chroma_w == 0 && dst_desc->log2_chroma_h == 1 && src_desc->log2_chroma_h == 0 ) { score += 512; } } if(consider & FF_LOSS_COLORSPACE) switch(dst_color) { case FF_COLOR_RGB: if (src_color != FF_COLOR_RGB && src_color != FF_COLOR_GRAY) loss |= FF_LOSS_COLORSPACE; break; case FF_COLOR_GRAY: if (src_color != FF_COLOR_GRAY) loss |= FF_LOSS_COLORSPACE; break; case FF_COLOR_YUV: if (src_color != FF_COLOR_YUV) loss |= FF_LOSS_COLORSPACE; break; case FF_COLOR_YUV_JPEG: if (src_color != FF_COLOR_YUV_JPEG && src_color != FF_COLOR_YUV && src_color != FF_COLOR_GRAY) loss |= FF_LOSS_COLORSPACE; break; default: /* fail safe test */ if (src_color != dst_color) loss |= FF_LOSS_COLORSPACE; break; } if(loss & FF_LOSS_COLORSPACE) score -= (nb_components * 65536) >> FFMIN(dst_desc->comp[0].depth - 1, src_desc->comp[0].depth - 1); if (dst_color == FF_COLOR_GRAY && src_color != FF_COLOR_GRAY && (consider & FF_LOSS_CHROMA)) { loss |= FF_LOSS_CHROMA; score -= 2 * 65536; } if (!pixdesc_has_alpha(dst_desc) && (pixdesc_has_alpha(src_desc) && (consider & FF_LOSS_ALPHA))) { loss |= FF_LOSS_ALPHA; score -= 65536; } if (dst_pix_fmt == AV_PIX_FMT_PAL8 && (consider & FF_LOSS_COLORQUANT) && (src_pix_fmt != AV_PIX_FMT_PAL8 && (src_color != FF_COLOR_GRAY || (pixdesc_has_alpha(src_desc) && (consider & FF_LOSS_ALPHA))))) { loss |= FF_LOSS_COLORQUANT; score -= 65536; } *lossp = loss; return score; }

static void pc_init1(ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, int pci_enabled, const char *cpu_model) { char *filename; int ret, linux_boot, i; ram_addr_t ram_addr, bios_offset, option_rom_offset; ram_addr_t below_4g_mem_size, above_4g_mem_size = 0; int bios_size, isa_bios_size, oprom_area_size; PCIBus *pci_bus; int piix3_devfn = -1; CPUState *env; qemu_irq *cpu_irq; qemu_irq *i8259; int index; BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; BlockDriverState *fd[MAX_FD]; int using_vga = cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled; if (ram_size >= 0xe0000000 ) { above_4g_mem_size = ram_size - 0xe0000000; below_4g_mem_size = 0xe0000000; } else { below_4g_mem_size = ram_size; } linux_boot = (kernel_filename != NULL); /* init CPUs */ if (cpu_model == NULL) { #ifdef TARGET_X86_64 cpu_model = "qemu64"; #else cpu_model = "qemu32"; #endif } for(i = 0; i < smp_cpus; i++) { env = cpu_init(cpu_model); if (!env) { fprintf(stderr, "Unable to find x86 CPU definition\n"); exit(1); } if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { env->cpuid_apic_id = env->cpu_index; apic_init(env); } qemu_register_reset(main_cpu_reset, 0, env); } vmport_init(); /* allocate RAM */ ram_addr = qemu_ram_alloc(0xa0000); cpu_register_physical_memory(0, 0xa0000, ram_addr); /* Allocate, even though we won't register, so we don't break the * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000), * and some bios areas, which will be registered later */ ram_addr = qemu_ram_alloc(0x100000 - 0xa0000); ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000); cpu_register_physical_memory(0x100000, below_4g_mem_size - 0x100000, ram_addr); /* above 4giga memory allocation */ if (above_4g_mem_size > 0) { #if TARGET_PHYS_ADDR_BITS == 32 hw_error("To much RAM for 32-bit physical address"); #else ram_addr = qemu_ram_alloc(above_4g_mem_size); cpu_register_physical_memory(0x100000000ULL, above_4g_mem_size, ram_addr); #endif } /* BIOS load */ if (bios_name == NULL) bios_name = BIOS_FILENAME; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); if (filename) { bios_size = get_image_size(filename); } else { bios_size = -1; } if (bios_size <= 0 || (bios_size % 65536) != 0) { goto bios_error; } bios_offset = qemu_ram_alloc(bios_size); ret = load_image(filename, qemu_get_ram_ptr(bios_offset)); if (ret != bios_size) { bios_error: fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name); exit(1); } if (filename) { qemu_free(filename); } /* map the last 128KB of the BIOS in ISA space */ isa_bios_size = bios_size; if (isa_bios_size > (128 * 1024)) isa_bios_size = 128 * 1024; cpu_register_physical_memory(0x100000 - isa_bios_size, isa_bios_size, (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); option_rom_offset = qemu_ram_alloc(0x20000); oprom_area_size = 0; cpu_register_physical_memory(0xc0000, 0x20000, option_rom_offset); if (using_vga) { const char *vgabios_filename; /* VGA BIOS load */ if (cirrus_vga_enabled) { vgabios_filename = VGABIOS_CIRRUS_FILENAME; } else { vgabios_filename = VGABIOS_FILENAME; } oprom_area_size = load_option_rom(vgabios_filename, 0xc0000, 0xe0000); } /* Although video roms can grow larger than 0x8000, the area between * 0xc0000 - 0xc8000 is reserved for them. It means we won't be looking * for any other kind of option rom inside this area */ if (oprom_area_size < 0x8000) oprom_area_size = 0x8000; if (linux_boot) { load_linux(0xc0000 + oprom_area_size, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); oprom_area_size += 2048; } for (i = 0; i < nb_option_roms; i++) { oprom_area_size += load_option_rom(option_rom[i], 0xc0000 + oprom_area_size, 0xe0000); } /* map all the bios at the top of memory */ cpu_register_physical_memory((uint32_t)(-bios_size), bios_size, bios_offset | IO_MEM_ROM); bochs_bios_init(); cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1); i8259 = i8259_init(cpu_irq[0]); ferr_irq = i8259[13]; if (pci_enabled) { pci_bus = i440fx_init(&i440fx_state, i8259); piix3_devfn = piix3_init(pci_bus, -1); } else { pci_bus = NULL; } /* init basic PC hardware */ register_ioport_write(0x80, 1, 1, ioport80_write, NULL); register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); if (cirrus_vga_enabled) { if (pci_enabled) { pci_cirrus_vga_init(pci_bus); } else { isa_cirrus_vga_init(); } } else if (vmsvga_enabled) { if (pci_enabled) pci_vmsvga_init(pci_bus); else fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__); } else if (std_vga_enabled) { if (pci_enabled) { pci_vga_init(pci_bus, 0, 0); } else { isa_vga_init(); } } rtc_state = rtc_init(0x70, i8259[8], 2000); qemu_register_boot_set(pc_boot_set, rtc_state); register_ioport_read(0x92, 1, 1, ioport92_read, NULL); register_ioport_write(0x92, 1, 1, ioport92_write, NULL); if (pci_enabled) { ioapic = ioapic_init(); } pit = pit_init(0x40, i8259[0]); pcspk_init(pit); if (!no_hpet) { hpet_init(i8259); } if (pci_enabled) { pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic); } for(i = 0; i < MAX_SERIAL_PORTS; i++) { if (serial_hds[i]) { serial_init(serial_io[i], i8259[serial_irq[i]], 115200, serial_hds[i]); } } for(i = 0; i < MAX_PARALLEL_PORTS; i++) { if (parallel_hds[i]) { parallel_init(parallel_io[i], i8259[parallel_irq[i]], parallel_hds[i]); } } watchdog_pc_init(pci_bus); for(i = 0; i < nb_nics; i++) { NICInfo *nd = &nd_table[i]; if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) pc_init_ne2k_isa(nd, i8259); else pci_nic_init(pci_bus, nd, -1, "ne2k_pci"); } qemu_system_hot_add_init(); if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { fprintf(stderr, "qemu: too many IDE bus\n"); exit(1); } for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); if (index != -1) hd[i] = drives_table[index].bdrv; else hd[i] = NULL; } if (pci_enabled) { pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259); } else { for(i = 0; i < MAX_IDE_BUS; i++) { isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]); } } i8042_init(i8259[1], i8259[12], 0x60); DMA_init(0); #ifdef HAS_AUDIO audio_init(pci_enabled ? pci_bus : NULL, i8259); #endif for(i = 0; i < MAX_FD; i++) { index = drive_get_index(IF_FLOPPY, 0, i); if (index != -1) fd[i] = drives_table[index].bdrv; else fd[i] = NULL; } floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd); cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd); if (pci_enabled && usb_enabled) { usb_uhci_piix3_init(pci_bus, piix3_devfn + 2); } if (pci_enabled && acpi_enabled) { uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ i2c_bus *smbus; /* TODO: Populate SPD eeprom data. */ smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]); for (i = 0; i < 8; i++) { DeviceState *eeprom; eeprom = qdev_create((BusState *)smbus, "smbus-eeprom"); qdev_set_prop_int(eeprom, "address", 0x50 + i); qdev_set_prop_ptr(eeprom, "data", eeprom_buf + (i * 256)); qdev_init(eeprom); } } if (i440fx_state) { i440fx_init_memory_mappings(i440fx_state); } if (pci_enabled) { int max_bus; int bus; max_bus = drive_get_max_bus(IF_SCSI); for (bus = 0; bus <= max_bus; bus++) { pci_create_simple(pci_bus, -1, "lsi53c895a"); } } /* Add virtio block devices */ if (pci_enabled) { int index; int unit_id = 0; while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) { pci_create_simple(pci_bus, -1, "virtio-blk-pci"); unit_id++; } } /* Add virtio balloon device */ if (pci_enabled && !no_virtio_balloon) { pci_create_simple(pci_bus, -1, "virtio-balloon-pci"); } /* Add virtio console devices */ if (pci_enabled) { for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) { if (virtcon_hds[i]) { pci_create_simple(pci_bus, -1, "virtio-console-pci"); } } } }

static ssize_t v9fs_synth_lgetxattr(FsContext *ctx, V9fsPath *path, const char *name, void *value, size_t size) { errno = ENOTSUP; return -1; }

static void aw_emac_cleanup(NetClientState *nc) { AwEmacState *s = qemu_get_nic_opaque(nc); s->nic = NULL; }

static void virtio_net_set_features(VirtIODevice *vdev, uint32_t features) { VirtIONet *n = VIRTIO_NET(vdev); int i; virtio_net_set_multiqueue(n, !!(features & (1 << VIRTIO_NET_F_MQ)), !!(features & (1 << VIRTIO_NET_F_CTRL_VQ))); virtio_net_set_mrg_rx_bufs(n, !!(features & (1 << VIRTIO_NET_F_MRG_RXBUF))); if (n->has_vnet_hdr) { tap_set_offload(qemu_get_subqueue(n->nic, 0)->peer, (features >> VIRTIO_NET_F_GUEST_CSUM) & 1, (features >> VIRTIO_NET_F_GUEST_TSO4) & 1, (features >> VIRTIO_NET_F_GUEST_TSO6) & 1, (features >> VIRTIO_NET_F_GUEST_ECN) & 1, (features >> VIRTIO_NET_F_GUEST_UFO) & 1); } for (i = 0; i < n->max_queues; i++) { NetClientState *nc = qemu_get_subqueue(n->nic, i); if (!nc->peer || nc->peer->info->type != NET_CLIENT_OPTIONS_KIND_TAP) { continue; } if (!tap_get_vhost_net(nc->peer)) { continue; } vhost_net_ack_features(tap_get_vhost_net(nc->peer), features); } }

void qemu_del_nic(NICState *nic) { int i, queues = nic->conf->queues; /* If this is a peer NIC and peer has already been deleted, free it now. */ if (nic->peer_deleted) { for (i = 0; i < queues; i++) { qemu_free_net_client(qemu_get_subqueue(nic, i)->peer); } } for (i = queues - 1; i >= 0; i--) { NetClientState *nc = qemu_get_subqueue(nic, i); qemu_cleanup_net_client(nc); qemu_free_net_client(nc); } }

static int vfio_initfn(PCIDevice *pdev) { VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); VFIODevice *vbasedev_iter; VFIOGroup *group; char path[PATH_MAX], iommu_group_path[PATH_MAX], *group_name; ssize_t len; struct stat st; int groupid; int ret; /* Check that the host device exists */ snprintf(path, sizeof(path), "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/", vdev->host.domain, vdev->host.bus, vdev->host.slot, vdev->host.function); if (stat(path, &st) < 0) { error_report("vfio: error: no such host device: %s", path); return -errno; } vdev->vbasedev.ops = &vfio_pci_ops; vdev->vbasedev.type = VFIO_DEVICE_TYPE_PCI; vdev->vbasedev.name = g_strdup_printf("%04x:%02x:%02x.%01x", vdev->host.domain, vdev->host.bus, vdev->host.slot, vdev->host.function); strncat(path, "iommu_group", sizeof(path) - strlen(path) - 1); len = readlink(path, iommu_group_path, sizeof(path)); if (len <= 0 || len >= sizeof(path)) { error_report("vfio: error no iommu_group for device"); return len < 0 ? -errno : -ENAMETOOLONG; } iommu_group_path[len] = 0; group_name = basename(iommu_group_path); if (sscanf(group_name, "%d", &groupid) != 1) { error_report("vfio: error reading %s: %m", path); return -errno; } trace_vfio_initfn(vdev->vbasedev.name, groupid); group = vfio_get_group(groupid, pci_device_iommu_address_space(pdev)); if (!group) { error_report("vfio: failed to get group %d", groupid); return -ENOENT; } snprintf(path, sizeof(path), "%04x:%02x:%02x.%01x", vdev->host.domain, vdev->host.bus, vdev->host.slot, vdev->host.function); QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { if (strcmp(vbasedev_iter->name, vdev->vbasedev.name) == 0) { error_report("vfio: error: device %s is already attached", path); vfio_put_group(group); return -EBUSY; } } ret = vfio_get_device(group, path, &vdev->vbasedev); if (ret) { error_report("vfio: failed to get device %s", path); vfio_put_group(group); return ret; } ret = vfio_populate_device(vdev); if (ret) { return ret; } /* Get a copy of config space */ ret = pread(vdev->vbasedev.fd, vdev->pdev.config, MIN(pci_config_size(&vdev->pdev), vdev->config_size), vdev->config_offset); if (ret < (int)MIN(pci_config_size(&vdev->pdev), vdev->config_size)) { ret = ret < 0 ? -errno : -EFAULT; error_report("vfio: Failed to read device config space"); return ret; } /* vfio emulates a lot for us, but some bits need extra love */ vdev->emulated_config_bits = g_malloc0(vdev->config_size); /* QEMU can choose to expose the ROM or not */ memset(vdev->emulated_config_bits + PCI_ROM_ADDRESS, 0xff, 4); /* * The PCI spec reserves vendor ID 0xffff as an invalid value. The * device ID is managed by the vendor and need only be a 16-bit value. * Allow any 16-bit value for subsystem so they can be hidden or changed. */ if (vdev->vendor_id != PCI_ANY_ID) { if (vdev->vendor_id >= 0xffff) { error_report("vfio: Invalid PCI vendor ID provided"); return -EINVAL; } vfio_add_emulated_word(vdev, PCI_VENDOR_ID, vdev->vendor_id, ~0); trace_vfio_pci_emulated_vendor_id(vdev->vbasedev.name, vdev->vendor_id); } else { vdev->vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); } if (vdev->device_id != PCI_ANY_ID) { if (vdev->device_id > 0xffff) { error_report("vfio: Invalid PCI device ID provided"); return -EINVAL; } vfio_add_emulated_word(vdev, PCI_DEVICE_ID, vdev->device_id, ~0); trace_vfio_pci_emulated_device_id(vdev->vbasedev.name, vdev->device_id); } else { vdev->device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); } if (vdev->sub_vendor_id != PCI_ANY_ID) { if (vdev->sub_vendor_id > 0xffff) { error_report("vfio: Invalid PCI subsystem vendor ID provided"); return -EINVAL; } vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_VENDOR_ID, vdev->sub_vendor_id, ~0); trace_vfio_pci_emulated_sub_vendor_id(vdev->vbasedev.name, vdev->sub_vendor_id); } if (vdev->sub_device_id != PCI_ANY_ID) { if (vdev->sub_device_id > 0xffff) { error_report("vfio: Invalid PCI subsystem device ID provided"); return -EINVAL; } vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_ID, vdev->sub_device_id, ~0); trace_vfio_pci_emulated_sub_device_id(vdev->vbasedev.name, vdev->sub_device_id); } /* QEMU can change multi-function devices to single function, or reverse */ vdev->emulated_config_bits[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_MULTI_FUNCTION; /* Restore or clear multifunction, this is always controlled by QEMU */ if (vdev->pdev.cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { vdev->pdev.config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; } else { vdev->pdev.config[PCI_HEADER_TYPE] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION; } /* * Clear host resource mapping info. If we choose not to register a * BAR, such as might be the case with the option ROM, we can get * confusing, unwritable, residual addresses from the host here. */ memset(&vdev->pdev.config[PCI_BASE_ADDRESS_0], 0, 24); memset(&vdev->pdev.config[PCI_ROM_ADDRESS], 0, 4); vfio_pci_size_rom(vdev); ret = vfio_msix_early_setup(vdev); if (ret) { return ret; } vfio_map_bars(vdev); ret = vfio_add_capabilities(vdev); if (ret) { goto out_teardown; } /* QEMU emulates all of MSI & MSIX */ if (pdev->cap_present & QEMU_PCI_CAP_MSIX) { memset(vdev->emulated_config_bits + pdev->msix_cap, 0xff, MSIX_CAP_LENGTH); } if (pdev->cap_present & QEMU_PCI_CAP_MSI) { memset(vdev->emulated_config_bits + pdev->msi_cap, 0xff, vdev->msi_cap_size); } if (vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1)) { vdev->intx.mmap_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, vfio_intx_mmap_enable, vdev); pci_device_set_intx_routing_notifier(&vdev->pdev, vfio_intx_update); ret = vfio_intx_enable(vdev); if (ret) { goto out_teardown; } } vfio_register_err_notifier(vdev); vfio_register_req_notifier(vdev); vfio_setup_resetfn_quirk(vdev); return 0; out_teardown: pci_device_set_intx_routing_notifier(&vdev->pdev, NULL); vfio_teardown_msi(vdev); vfio_unregister_bars(vdev); return ret; }

static void absolute_mouse_grab(void) { int mouse_x, mouse_y; if (SDL_GetAppState() & SDL_APPINPUTFOCUS) { SDL_GetMouseState(&mouse_x, &mouse_y); if (mouse_x > 0 && mouse_x < real_screen->w - 1 && mouse_y > 0 && mouse_y < real_screen->h - 1) { sdl_grab_start(); } } }

int socket_dgram(SocketAddress *remote, SocketAddress *local, Error **errp) { int fd; switch (remote->type) { case SOCKET_ADDRESS_KIND_INET: fd = inet_dgram_saddr(remote->u.inet, local ? local->u.inet : NULL, errp); break; default: error_setg(errp, "socket type unsupported for datagram"); fd = -1; } return fd; }

static int update_wrap_reference(AVFormatContext *s, AVStream *st, int stream_index) { if (s->correct_ts_overflow && st->pts_wrap_bits < 63 && st->pts_wrap_reference == AV_NOPTS_VALUE && st->first_dts != AV_NOPTS_VALUE) { int i; // reference time stamp should be 60 s before first time stamp int64_t pts_wrap_reference = st->first_dts - av_rescale(60, st->time_base.den, st->time_base.num); // if first time stamp is not more than 1/8 and 60s before the wrap point, subtract rather than add wrap offset int pts_wrap_behavior = (st->first_dts < (1LL<<st->pts_wrap_bits) - (1LL<<st->pts_wrap_bits-3)) || (st->first_dts < (1LL<<st->pts_wrap_bits) - av_rescale(60, st->time_base.den, st->time_base.num)) ? AV_PTS_WRAP_ADD_OFFSET : AV_PTS_WRAP_SUB_OFFSET; AVProgram *first_program = av_find_program_from_stream(s, NULL, stream_index); if (!first_program) { int default_stream_index = av_find_default_stream_index(s); if (s->streams[default_stream_index]->pts_wrap_reference == AV_NOPTS_VALUE) { for (i=0; i<s->nb_streams; i++) { s->streams[i]->pts_wrap_reference = pts_wrap_reference; s->streams[i]->pts_wrap_behavior = pts_wrap_behavior; } } else { st->pts_wrap_reference = s->streams[default_stream_index]->pts_wrap_reference; st->pts_wrap_behavior = s->streams[default_stream_index]->pts_wrap_behavior; } } else { AVProgram *program = first_program; while (program) { if (program->pts_wrap_reference != AV_NOPTS_VALUE) { pts_wrap_reference = program->pts_wrap_reference; pts_wrap_behavior = program->pts_wrap_behavior; break; } program = av_find_program_from_stream(s, program, stream_index); } // update every program with differing pts_wrap_reference program = first_program; while(program) { if (program->pts_wrap_reference != pts_wrap_reference) { for (i=0; i<program->nb_stream_indexes; i++) { s->streams[program->stream_index[i]]->pts_wrap_reference = pts_wrap_reference; s->streams[program->stream_index[i]]->pts_wrap_behavior = pts_wrap_behavior; } program->pts_wrap_reference = pts_wrap_reference; program->pts_wrap_behavior = pts_wrap_behavior; } program = av_find_program_from_stream(s, program, stream_index); } } return 1; } return 0; }

uint64_t HELPER(diag)(CPUS390XState *env, uint32_t num, uint64_t mem, uint64_t code) { uint64_t r; switch (num) { case 0x500: /* KVM hypercall */ r = s390_virtio_hypercall(env); break; case 0x44: /* yield */ r = 0; break; case 0x308: /* ipl */ r = 0; break; default: r = -1; break; } if (r) { program_interrupt(env, PGM_OPERATION, ILEN_LATER_INC); } return r; }

static uint64_t get_cluster_offset(BlockDriverState *bs, VmdkExtent *extent, VmdkMetaData *m_data, uint64_t offset, int allocate) { unsigned int l1_index, l2_offset, l2_index; int min_index, i, j; uint32_t min_count, *l2_table, tmp = 0; uint64_t cluster_offset; if (m_data) m_data->valid = 0; l1_index = (offset >> 9) / extent->l1_entry_sectors; if (l1_index >= extent->l1_size) { return 0; } l2_offset = extent->l1_table[l1_index]; if (!l2_offset) { return 0; } for (i = 0; i < L2_CACHE_SIZE; i++) { if (l2_offset == extent->l2_cache_offsets[i]) { /* increment the hit count */ if (++extent->l2_cache_counts[i] == 0xffffffff) { for (j = 0; j < L2_CACHE_SIZE; j++) { extent->l2_cache_counts[j] >>= 1; } } l2_table = extent->l2_cache + (i * extent->l2_size); goto found; } } /* not found: load a new entry in the least used one */ min_index = 0; min_count = 0xffffffff; for (i = 0; i < L2_CACHE_SIZE; i++) { if (extent->l2_cache_counts[i] < min_count) { min_count = extent->l2_cache_counts[i]; min_index = i; } } l2_table = extent->l2_cache + (min_index * extent->l2_size); if (bdrv_pread( extent->file, (int64_t)l2_offset * 512, l2_table, extent->l2_size * sizeof(uint32_t) ) != extent->l2_size * sizeof(uint32_t)) { return 0; } extent->l2_cache_offsets[min_index] = l2_offset; extent->l2_cache_counts[min_index] = 1; found: l2_index = ((offset >> 9) / extent->cluster_sectors) % extent->l2_size; cluster_offset = le32_to_cpu(l2_table[l2_index]); if (!cluster_offset) { if (!allocate) return 0; // Avoid the L2 tables update for the images that have snapshots. cluster_offset = bdrv_getlength(extent->file); bdrv_truncate( extent->file, cluster_offset + (extent->cluster_sectors << 9) ); cluster_offset >>= 9; tmp = cpu_to_le32(cluster_offset); l2_table[l2_index] = tmp; /* First of all we write grain itself, to avoid race condition * that may to corrupt the image. * This problem may occur because of insufficient space on host disk * or inappropriate VM shutdown. */ if (get_whole_cluster( bs, extent, cluster_offset, offset, allocate) == -1) return 0; if (m_data) { m_data->offset = tmp; m_data->l1_index = l1_index; m_data->l2_index = l2_index; m_data->l2_offset = l2_offset; m_data->valid = 1; } } cluster_offset <<= 9; return cluster_offset; }