Q:

How do IBMs lis and ori instructions work?

I want to know how do lis and ori instructions work? There is a description IBM description which i cannot understand well. Could someone explain to me what is the result on this example:
lis r1, 0x0028      
ori r1, r1, 0x776F  

A:

lis is defined here ( http://www-01.ibm.com/support/knowledgecenter/api/content/nl/en-us/ssw_aix_53/com.ibm.aix.aixassem/doc/alangref/fixed_point_load.htm#idx175 )

Extended Mnemonic lis rx, value => Equivalent to addis rx, 0, value. aka Load Immediate Shifted

addis is then defined as:

Calculates an address from a concatenated offset and a base address and loads the result in a general-purpose register.

The "Load Immediate Shifted" operation is described on this page ( http://www.ibm.com/developerworks/library/l-ppc/ ):

Conveniently, lis (meaning "load immediate shifted") will load directly into the high 16 bits of the GPR. Then all that's left to do is add in the lower bits.

So lis r1, 0x0028 is addis r1, 0, 0x0028, in English: Set the upper 16 bits of the contents of register r1 to 0x0028.  (And zero the other bits, because we added 0x28 << 16 to 0.)
I think ori's definition is straight-forward:

Logically ORs the lower 16 bits of the contents of a general-purpose register with a 16-bit unsigned integer and stores the result in another general-purpose register.

In your example, ori r1, r1, 0x776F:
In English: Get the lower 16-bits of whatever is in register r1 and OR them with 0x776F ( 1110111 01101111 ) then store it back in r1.

So those two instructions form 0x0028776F in register r1, with no dependency on the previous contents.
The low 16 bits are zero after addis, so ORing into them just sets them to ori's immediate.
A 2-instruction sequence like this (special instruction to set high bits, then addi or ori to set the low bits) is typical of RISC ISAs for constructing arbitrary 32-bit constants; a 32-bit instruction word doesn't have room for a whole 32-bit immediate.

