Q:

how to nor two vectors in dataflow verilog?

I am using ModelSim and implementing an ALU. This is the assignment part:
assign {cout,dst} = (op_i == add ) ? scr0+scr1+cin:
                    (op_i == sub ) ? scr1-scr0:
                    (op_i == shift_l) ? {scr0[15:0],cin}:
                    (op_i == shift_r) ? {scr0[0],cin,scr0[15:1]}:
                    (op_i == ar_shift_r) ? {scr0[0],scr0[15],scr0[15:1]}:
                    (op_i == par) ? { ^scr0,scr0[15:0] } :
                    (op_i == rotate)? {scr0[14:0],scr0[15]}:
                    (op_i == Nor ) ?  (scr1 ~| scr0) :
                    17'h00000;

The last Nor is giving me an error. If I try oring instead of noring then it works. But the ~| is showing unexpected ~| error.

A:

In SystemVerilog, the ~| operator is the unary NOR. It NORs together all bits of a vector, which is why it's also called a NOR reduce. There is a bitwise exclusive NOR operator, ~^ or ^~, but no NOR.
If you want to implement a bitwise NOR, then you have to perform a bitwise OR followed by a bitwise negation:
~(scr1 | scr0)

