Q:

Makefile: the sequence of executing the makefile

Makefile:
foo: 
    @echo hello

%: force
    @echo foo

force:
    @echo force

If I typed `make foo', the output is:
force
foo
hello

So why not  hello
However, If I changed to this:
foo: 
    @echo hello

%:
    @echo foo

force:
    @echo force

It only outputs hello 

A:

The reason is because make has to track back through dependencies to make you a foo.
When you type make foo, make thinks you are asking it to make a file called foo. So as foo does not exist (assumption) it tries to work out how to make a foo. You made a wildcard rule % can be anything and since there is no better option make will try to use this rule to make a foo. To make foo now there is a dependency force, which needs to be executed before we can go about making foo. As a file force does not exist make determines it needs to execute the target to make force.
So we have reached the point where stuff starts to happen in terms of output. force executes which echos force, then the wildcard rule executes, which echos foo finally make believes its ready to create foo and the command is only to echo hello. 
So it is actually in reverse order, from outermost dependency first to final target last.
When you take away force as a dependency of the wildcard rule then the wildcard rule will determine there is nothing to do to create force and so will not execute its body (echoing foo), but as hello does not exist it will execute the body of your foo target.
If you include something to make a file force in the force target (e.g. touch force) you will see now that foo and hello print, but not force.
You can see the steps make takes if you pass the flag --debug=a (all) to make on the command line.

