Q:

Error when executing make

I am trying to create a makefile for my project, but i seem to run into some errors, as I am testing new things. My file structure is as such: 
~/main   #root project folder
    ~/main/include   #header files (mostly class headers)
    ~/main/src       #source files
    ~/main/src/obj   #object files
    Makefile

(Makefile is in the root project folder)
Makefile:
CC=g++

IDIR=include
SDIR=src
ODIR=src/obj

DEPS=$(IDIR)/%.h
OBJS=$(ODIR)/%.o
SRCS=$(SDIR)/%.cpp

CFLAGS=-Wall -std=c++11 -I$(IDIR)

$(OBJS): $(SRCS) $(DEPS)
    $(CC) -c -o $@ $< $(CFLAGS)

all: $(OBJS)
    gcc -o run $^ $(CFLAGS)

.PHONY: clean

clean:
    rm -f $(OBJS)

For testing purposes I have a single main.cpp in src folder and a random header file in include folder. The error I am getting when running the simple make command is the following:
make: *** No rule to make target `src/obj/%.o', needed by `all'.  Stop.

EDIT : With the help of the guys below i came up with the solution
CC=g++

IDIR=include
SDIR=src
ODIR=src/obj

CFLAGS=-Wall -std=c++11 -I$(IDIR)

_DEPS = yo.h
DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))

_OBJ = main.o
OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))

_SRC = main.cpp
SRC = $(patsubst %,$(SDIR)/%,$(_SRC))

$(ODIR)/%.o: $(SRC) $(DEPS)
    $(CC) -c -o $@ $< $(CFLAGS)

all: $(OBJ)
    $(CC) -o run $^ $(CFLAGS) $(LIBS)

.PHONY: clean

clean:
    rm -f $(OBJS)

A:

There is a difference in using % in your two cases. When you write:
$(ODIR)/%.o : $(SDIR)/%.cpp $(IDIR)/%.h

that will do pattern substitution, and create a bunch of rules like:
$(ODIR)/foo.o : $(SDIR)/foo.cpp $(SDIR)/foo.h

So it's fine there, although you should use the % explicitly there so it's clear to see what the rule is doing.
But when you use it here:
all : $(ODIR)/%.o

That is literally looking for the target $(ODIR)/%.o for which you don't have a rule. There's no substitution. And you don't have a rule to make that target - hence the error. What you meant to do was have all depend on all the actual objects, for which you'll want to use the wildcard function:
SOURCES = $(wildcard $(SDIR)/*.cpp)
OBJECTS = $(SOURCES:$(SDIR)/%.cpp=$(ODIR)/%.o)

all : $(OBJECTS)
    gcc -o run $^ $(CFLAGS)

