1. Field of the Invention
Embodiments of the invention relate to memory devices, and more particularly, in one or more embodiments, to flash memory devices.
2. Description of the Related Art
Flash memory devices are non-volatile memory devices which store information on a semiconductor in a way that needs no power to maintain the information stored therein. Among flash memory devices, NAND flash memory devices have been widely used as mass-storage devices because of their high storage densities and low costs. In some applications, a NAND flash memory device serves as a solid state disk (SSD), replacing or supplementing a hard disk.
Referring to FIG. 1, a conventional NAND flash memory device includes a plurality of memory blocks. The illustrated flash memory device 10 includes first to N-th memory blocks 100. Each of the memory blocks 100 includes a plurality of memory cells arranged in a matrix form.
FIG. 2A illustrates one of the memory blocks 100 of the NAND flash memory device 10 of FIG. 1. The illustrated memory block 100 includes first to m-th bit lines BL0-BLm and first to n-th word lines WL0-WLn. In some arrangements, m can be 32,767 or 65,535, and n can be 32 or 64. The bit lines BL0-BLm extend parallel to one another in a column direction. The word lines WL0-WLn extend parallel to one another in a row direction perpendicular to the column direction. The memory block 100 also includes upper and lower bit line select transistors 120a, 120b for selecting the one memory block 100 among the plurality of memory blocks of FIG. 1 by coupling the one memory block 100 to bit lines extending outside the memory block 100.
Each bit line includes a string of memory cells 110. For example, the second bit line BL1 includes memory cells 110 connected in series. Each of the memory cells 100 includes a floating gate transistor. The floating gate transistors of the memory cells 100 are coupled to one another in series source to drain. The control gates of the floating gate transistors of memory cells 110 in the same row are coupled to the same word line. Each of the memory cells 110 stores a charge (or a lack of charge), wherein the amount of stored charge can be used to represent, for example, one or more states, and wherein the one or more states can represent one or more digits (e.g., bits) of data. The memory cell can be either a single-level cell (SLC) or a multi-level cell (MLC). In one arrangement, the amounts of charge stored in the memory cells 110 may be detected by sensing currents flowing through the floating gate transistors of the memory cells 110. In another arrangement, the amounts of charge stored in the memory cells 110 may be detected by sensing the threshold voltage values of the floating gate transistors of the memory cells 110.
FIG. 2B illustrates a cross-section of the floating gate transistors of the memory cells 110 in the second bit line BL1. The floating gate transistors are formed on a substrate 201. Each of the floating gate transistors includes a source region 210 (which is a drain region for a neighboring transistor), a drain region 212 (which is a source region for a neighboring transistor), a doped channel region 214, a first dielectric (e.g., a tunnel oxide) 216, a floating gate 218, a second dielectric (e.g., a gate oxide, wherein the tunnel and gate oxide can be formed of the same or different material) 220, and a control gate 222. The tunnel oxide 216 is formed on the channel region 214 to insulate the floating gate 218 from the channel region 214. The gate dielectric 220 physically and electrically separates the floating gate 218 from the control gate 222. The control gate 222 is coupled to an appropriate word line, e.g., word line WL1. Electrons can be trapped on the floating gate 218 and be used to store data.
Referring now to FIGS. 1 and 2C, a conventional method of writing data on a memory block will be described. FIG. 2C schematically illustrates the memory block 100 of FIG. 2A, and only shows memory cells, bit lines, and word lines. However, it will be understood that the memory block 100 can include other components as described above with respect to FIGS. 2A and 2B.
During a write operation of the NAND flash memory device 10 (FIG. 1), data is typically written on a set of memory cells on a single word line. Such a set of memory cells can be referred to as a “page.” In one arrangement, a page may include all memory cells on a word line. In other arrangements, a page may be formed by every other memory cells on a single word line. In certain arrangements, a page may be formed by every fourth memory cells on a single word line. It will be understood that a page may be formed by any suitable selected number of memory cells on a word line.
On the other hand, an erase operation of the NAND flash memory device 10 (FIG. 1) is typically performed on a block-by-block basis. In other words, a page or memory cells cannot be selectively erased.
Likewise, when changing data values in some of memory cells in a memory block, the data values in the memory cells cannot be selectively changed. Instead, the entire memory block is erased and re-written (or programmed) with changed data values. For this process, data values stored in the entire memory block are copied to another memory block. For example, when some of data values in the I-th memory block are to be modified, the data values in the entire I-th memory block are copied to an unused memory block, for example, the J-th memory block. Subsequently, the data values in the entire I-th memory block are erased, and then updated data including unmodified and modified data values is written onto the erased I-th memory block.