1. Technical Field
The present invention relates to design verification, and more specifically, to semiconductor device design verification.
2. Related Art
In a semiconductor device design, a design structure (i.e., a structure in the design) and the same structure in actuality (i.e., after being fabricated according to the design) are always not identical. More specifically, the design structure and the same structure in actuality may have different shapes, sizes, and/or positions on the wafer. For example, in the design, a metal line can be on top of and in direct physical contact with a via, while, in actuality, the metal line can be misaligned with the via such that the metal line is not in direct physical contact with the via. When this happens (i.e., in actuality, the metal line is not in direct physical contact with the via), the entire chip that contains the metal line and the via can be defective and may have to be discarded.
As a result, there is a need for a method for identifying potential defects in a design (called a design verification process) due to structures in actuality and the same structure in design not having the same shapes, sizes, or positions on the wafer.