This invention relates to a CMOS inverter circuit and more particularly to a CMOS inverter including a compensation circuit which compensates the inverter's low-to-high or high-to-low dynamic input threshold for a range of Vcc.
A conventional CMOS inverter 10 is shown in FIG. 1. Inverter 10 includes a pMOS transistor 12 and a nMOS transistor 14. A gate 12g of pMOS transistor 12 is coupled to a gate 14g of nMOS transistor 14. A first flow electrode 12s of transistor 12 is coupled to VCC and a first flow electrode 14s of transistor 14 is coupled to ground. A second flow electrode 12d of transistor 12 is coupled to a second flow electrode 14d of transistor 14. The switching threshold of inverter 10 is dependent on the relative size of transistors 12 and 14 and the supply voltage Vcc. The higher the ratio of pMOS to nMOS, the higher the input threshold. If we assume for a typical circuit that the input threshold is Vcc/2 and that Vcc is allowed to vary from 2.7 to 3.6 volts, the input threshold could then vary from 1.35 to 1.8 volts. This is undesirable, for example, if the input of inverter 10 is a clock pulse specified to ramp from 2.7 to 0 volts with a 2.5 ns slew rate and the design requires the propagation time of the clock signal to be independent of Vcc.
Accordingly, it would be desirable to provide a CMOS inverter including circuitry which could control the switching threshold as Vcc varies in order to maintain a substantially constant input threshold.