As an integrated circuit pattern has become a very narrow pattern, forming a circuit pattern of the narrower dimension than halves of the exposure wavelengths has to study in lithography technology field, where an integrated circuit pattern formed on the mask is printed onto a semiconductor wafer with ultra violet exposure light.
For example, a reference of “Photo mask gijutu no hanashi', Kougyouchousakai K. K. pp. 236-240, 1996” discloses as follows: Optical Proximity Correction technology prevents the decline of a printing accuracy to a semiconductor wafer of an integrated circuit pattern, and accuracy of integrated circuit pattern is possible to increase by correcting of circuit pattern formed on the mask.
Japanese Patent Publication No. 2710967 invented by this inventor discloses a phase shift technology which is improved resolution of printing the integrated circuit pattern on a semiconductor wafer. This is using a dark line of light interference of transmitted light by a phase difference of light set on the mask.
Japanese Patent Publication No. 2634037 discloses an exposure technology, which is improved resolution of printing the integrated circuit pattern on a semiconductor wafer. This technique uses an off-axis illumination of exposure light limited on the mask illumination.
Japanese Patent Laid-Open No. 10-303114 discloses a liquid immersion exposure equipment which does not lead to deterioration of the image performance for fine pattern by filling the room between the reduced projection lens and wafer with liquid.
Japanese Patent Publication No. 3120474 invented by this inventor discloses a projection exposure method using a phase shift mask, which is formed by overlapping an opaque pattern substrate and a phase shifter pattern substrate.
Related Japanese Patent Documents                (1) Japanese Patent Publication No. 2710967        (2) Japanese Patent Publication No. 2634037        (3) Japanese Patent Laid-Open No. 10-303114        (4) Japanese Patent Publication No. 3120474        
Other References
M. Hoga et al, ‘Photo the mask gijutu no hanashi’, Kougyou Chousakai K K, pp. 235-240, Aug. 20, 1996
The subject which invention tries to solve.
A semiconductor integrated circuit device has been becoming more higher integration without stopping. Minimum pattern size of semiconductor circuit of large volume production device has become narrower than 100 nm pattern.
The reduced projection exposure method has formed circuit patterns. This exposure method cannot cope with progress of integrated circuit device any more, because shorting of exposure light wavelength and enlarging of numerical aperture of projection lens have become very difficult. The technique until now cannot be taken any more. Using the above mentioned phase shift technique, it is said to cope with pattern size to the half of exposure wavelength, but it is very difficult for narrower pattern.
The exposure technology disclosed in Japanese Patent Publication No. 3120474 had problems of both increasing printed pattern deformation and miss-matching of forming a narrow pattern. This reason is a phase shift mask fabricated by overlapping an opaque pattern and a phase shift pattern.
A liquid immersion exposure equipment disclosed in Japanese Patent Laid-Open No. 10-303114 had problems of both generating of bubbles in liquid and changing of liquid temperature during exposure. And it has practical problems of photosensitive resist material and developer material.
A reduced projection exposure equipment is repeating exposure steps after changing position between projection lens and wafer surface. Then, solid material of immersion method cannot change position between a projection lens and a wafer surface, instead of liquid material.
An object of the present invention is to provide a reduced projection exposure method, which is possible to manufacture a semiconductor integrated circuits device whose circuit pattern size is less than half of exposure wavelength.
Another objective of this invention is to provide an exposure method, which is possible to printing a very narrow pattern on a semiconductor wafer, by both increasing numerical aperture of projection lens and reducing optical phase difference between ideal wave-front and actual wave-front.
Another objective of this invention is to provide a reduced projection exposure equipment for printing circuit pattern on the mask to semiconductor wafer. And another objective of this invention is to provide a mask for a semiconductor fabrication process.
Another objective of this invention is to provide a high efficient semiconductor fabrication technology by lowering investment of both development and fabrication of a semiconductor device.
Another objective of this invention is to provide a forming method of very narrow pattern which pattern size is narrower than exposure wavelength, by overcoming surface roughness of both an insulator film and a conductor film on a semiconductor wafer.
Another objective of this invention is to provide a method of forming a circuit pattern whose pattern size is narrower than exposure wavelength, by solving problems of both micro bubbles and liquid temperature in the liquid immersion exposure.
Another objective of this invention is to provide a circuit design method of reduced cost for a new fine circuit development.
Another objective of this invention is to provide a exposure method of reduced mask fabrication cost, by using an opaque mask instead of a phase-shift mask.
The above-mentioned objects and other objects of the present invention, and new features thereof will be apparent from the description of the present specification and attached drawings.