Wafer-level packaging is the technology of packaging one or more electronic modules as part of a wafer, in contrast to the conventional method of slicing the wafer into individual circuits and then packaging them. Reconstructed wafers, including high density electronic devices, are typically formed by fabricating a silicon wafer with embedded electronic modules (e.g., chip scale components) using a molding process. Most embedded chip scale components, referred to as electronic modules, include various circuitry contained within a housing and electrical contacts along one surface or another of the housing. During the molding process, the desired chip scale components (i.e., dies) are typically oriented on a mounting surface with the electrical contacts facing upward or downward relative to the mounting surface.
Integrated ultra-high density (iUHD) manufacturing and packaging processes are reconstructed wafer-level packaging processes that allow for miniaturization of electronic components. Such processes typically involve placement of individual dies face down on a mounting surface, such as an adhesive film, prior to a molding process. A cavity wafer can be created by patterning and etching a standard silicon (Si) wafer. The one or more cavities formed in the wafer can be configured to accept buried components. The cavity wafer can have a plurality of fillports, which can be distributed in each of the cavities. The cavity wafer can be placed over the dies and low coefficient of thermal expansion (CTE) encapsulant can be injected into the cavities through the fillports to surround the die. Following encapsulation, the adhesive film can be removed to reveal a planar surface on the reconstructed wafer. Multilayer interconnect can then be fabricated on both sides of the core using standard wafer fabrication techniques.
FIG. 1 shows one embodiment of a molding process for wafer-level packaging 10 using a conventional custom cavity wafer. One or more dies 17 can be placed on a film 11. A cavity wafer 12 can be placed over the dies. The cavity wafer can have one or more frontside cavities 13, 14, 15. A piston 18 forces down the upper part (the film 11, the dies 17, and the cavity wafer 12) of the package into a liquid encapsulant 16. Before the molding process starts, a molding chamber (not shown) where the molding process is performed can be evacuated. As pressure is applied by the piston 18, the encapsulant 16 can flow through fillports 131, 132, 133 of the cavities 13, 14, 15. The liquid encapsulant 16 can reach the cavities and surround the dies 17. Gaskets 19 can serve as mechanical stops to avoid applying too much pressure, e.g., to the level that the dies contact the walls of the wafer cavities. It can be desirable to leave space between the dies and the walls of the wafer cavity of at least about 50 μm to allow the encapsulant 16 to flow between the dies and the walls of the wafer cavity and surround the dies completely. Spacing less than about 50 μm can, in some embodiments, be too narrow to allow particles of the encapsulant 16 to flow without restriction. Once the mold has been pressurized, heat can be applied to the wafer-level packaging to cure the liquid encapsulant 16. When the liquid encapsulant 16 is cured, the film 11 can be removed, along with excess encapsulant.
FIGS. 2A-2D illustrate a cross-sectional view of conventional custom cavity wafer design. A standard silicon (Si) wafer, shown in FIG. 2A, can be etched to form fillports and cavities, as shown in FIGS. 2B and 2C. After encapsulant flows through the fillports, the encapsulant can fill the fillports and the cavities as shown in FIG. 2D.
Due to a CTE mismatch between the encapsulant and the silicon wafer, bowing of the wafer can occur when heat is applied to cure the encapsulant 16. In order to control the amount of wafer bow, backside cavities can be etched in some embodiments, as shown in FIG. 2C. These backside cavities can create oppositely-directed bowing forces that can balance those created on the frontside of the wafer.
A group of dies can form a module in which the dies are electrically connected by the iUHD process, as shown in FIG. 2E. Conventionally, cavities are created for each module 21, 22 by etching into the wafer 20, as shown in FIG. 2F. The layout of each module can vary and a custom cavity wafer can be required for each module design.
In the conventional approach, since separate cavities are formed for each module, large gaps are formed between modules that consume valuable real-estate of the wafer. In addition, cavity wafer design that is specific to module design prevents fabrication of the cavity wafer until a corresponding module design is complete. This limitation creates issues with production schedules because each cavity wafer is essentially a custom component.