The present invention relates to the fabrication of integrated circuits. More particularly, the invention provides a technique, including a method and apparatus, for modifying the profile of high-aspect-ratio trenches on a substrate to fill those trenches with void-free dielectric material.
Semiconductor device geometries continue to decrease in size, providing more devices per fabricated wafer and faster devices. Currently, some devices are being fabricated with less than 0.25 xcexcm spacing between features; in some cases there is as little as 0.18 xcexcm spacing between device features. The space between features often takes the form of a trench.
If the height of the features remains constant, reducing the spacing between features increases the aspect ratio of trenches between the features. The aspect ratio of a trench is the ratio of the height of a trench to the width of a trench. For example, a trench that is 2 xcexcm deep and has a 1 xcexcm gap has an aspect ratio of 2:1. Two examples of such trenches that frequently have high aspect ratios are isolation trenches and the trenches formed by adjacent conductive traces on a substrate. Isolation trenches are formed in a substrate between features, such as transistors, and conductive traces are typically formed by patterning a layer of metal or other conductor.
Material, such as doped or undoped silicon oxide glass, is often deposited in the trenches. The deposited material may serve several purposes, including protecting the substrate or conductive lines from physical or chemical damage, electrically insulating one side of the trench from the other, and providing a surface to build subsequent features on. One way to deposit trench-filling material is by chemical vapor deposition (CVD), where gases react or are decomposed to form a film, or layer, on the substrate.
FIGS. 1(a) through 1(c) illustrate that a void may form as a trench with a narrow gap is filled. In conventional CVD processes the gap may become pinched off as material accumulates on the upper edges of the trench as the trench fills. This forms an overhang 4 that may eventually merge, leaving behind a void 5 in the deposited material. Such a void may cause yield or reliability problems.
One method for keeping a gap open so that a trench may be filled is to use a plasma process that sputter etches some of the deposited material away as a layer is being formed. Using a plasma etch during deposition keeps gaps open because the rate of plasma sputter etching is dependant on the surface angle of the material being etched, and is higher at the corners of the trenches.
FIG. 2 shows that the rate of etching 6 in a plasma sputtering system varies as the surface angle, or angle from the horizontal plane of the substrate. In the example shown in FIG. 2, the maximum etching rate 7 occurs at 45 degrees to the horizontal, which represents the etching rate at a corner, or edge, of a trench. FIG. 2 shows that the etching rate at a corner of a trench is about 4 times greater than at a horizontal surface (also known as the xe2x80x9cfieldxe2x80x9d) for the conditions represented in FIG. 2. The difference between the angular etching rate and the deposition rate 8 in a deposition/etch process allows formation of a facet 9, rather than an overhang, at the edge of a trench, as shown in FIG. 3. It is generally desired, after an initial thin layer of material has been deposited, that the etching rate equal the deposition rate at the trench corners, resulting in no net deposition or etching in this region. Balancing the rate of deposition with the rate of etching should keep the trench open without exposing the underlying corner.
Simply filling a trench by plasma etching during a deposition process appears to be an attractive way to fill a narrow, high-aspect ratio trench in a void-free manner; however, the solution is not that simple. First, etching a layer as it is being deposited reduces the net deposition rate, thus increasing process time and associated cost. Second, the difference between keeping the gaps open and etching into the material forming the edge of the trench can be slight. Etching into the material forming the edge of the trench is undesirable because it erodes the edge, which can affect device performance and because it can contaminate the processing chamber and substrate. Sealing, or lining, the edge of the narrowly spaced gaps so that the trench edge won""t be exposed by the plasma etching is difficult and tricky. Only a very thin lining layer can be deposited before the gap starts pinching shut. A thin lining layer does not provide much margin for error when etching to keep the trench open. It is especially difficult to uniformly process large wafers because it is generally more difficult to maintain the required process control over a larger area.
It is typical for a process to have some variation, or xe2x80x9crun-outxe2x80x9d, across the surface of the wafer, and it is challenging to fill narrow trenches in a gap-free manner as the size of typical wafers continues to increase. The combined effects of shrinking device geometries and increasing wafer size makes it even more important to understand the gap-filling process so that additional process controls may be applied. Conventional deposition methods have not addressed the subtle nature of some parameters that affect the gap-filling process. Thus, it is desirable to provide a deposition process with greater control over the process parameters to fill narrow gaps in an efficient, void-free manner.
The present invention recognizes that it is possible to modify the profile of a trench during a deposition process to fill that trench in a gap fill manner. The trench profile modification can lower the aspect ratio of the trench, thus making it easier to efficiently fill the trench in a gap-free manner. The trench may be etched into a silicon substrate, such as the type of trench used for shallow-trench isolation (STI), may be formed by a patterned metallization layer, or may be another type of trench.
The trench profile is modified during a deposition process in a high-density plasma CVD (HDP-CVD) system. The HDP-CVD system was modified in various ways to provide additional control over the deposition process, particularly with respect to how the plasma heats a substrate. It was determined that the profile of a trench may be modified by the heating the backside of the substrate, by controlling the thermal coupling between the substrate and a supporting structure, by altering the configuration of the plasma, or by a combination of these methods. These methods and combinations of methods provides degrees of process control that allow the efficient deposition of void-free material in narrow gaps.
In a specific embodiment, the backside of a substrate is heated during the deposition process while the front side of the substrate is heated by the plasma formed in the HDP-CVD system chamber. Heating the backside of the substrate changes the temperature profile of the wafer, resulting in a hotter wafer surface, which alters the deposition characteristics. In another embodiment, the substrate is not chucked to the wafer support structure. By not chucking the substrate, less heat is transferred from the surface of the substrate to the wafer support structure, and the surface of the wafer, which is heated by the plasma, becomes hotter than it would if the substrate were chucked. Thus, not chucking the substrate also alters the deposition characteristics.
In another embodiment, the amount of radio frequency (RF) power provided to a top coil relative to the amount of RF power provided to a side coil is adjusted to control the plasma characteristics. The surface of the substrate is heated by the plasma, so controlling the plasma characteristics may also be used to control the surface temperature of the substrate and hence the deposition characteristics.
These and other embodiments of the present invention, as well as its advantages and features are described in more detail in conjunction with the text below and attached figures.