This application claims the priority of Korean patent application Serial No.99-55682 filed on Dec. 8, 1999.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing thereof, and more particularly to a semiconductor device having ferroelectric memories fit for a highly integrated semiconductor device and a method of manufacturing thereof.
2. Description of the Related Art
As well known, the recent trend to fabricate a semiconductor device is towards to a high degree of integration accompanied with a development of material, and improvements of equipments and process techniques and progress of design techniques used for fabricating it. As the semiconductor device is highly integrated, circuit elements manufactured respectively such as a capacitor, a transistor, and a resistor are integrated in one chip. Furthermore, the device in which the circuit elements are organically combined each other, such as a memory, is integrated in one chip.
Moreover, as electronic industries are developed, it is required of the memory that is driven at lower voltage than the conventional memory and has a high speed of data process. Therefore, to satisfy the requirement, a large number of memories are developed and used commercially or being developed.
The ferroelectrics memory among the memories being developed is expected to substitute for DRAM in the future and is in the progress of development and research since it has advantages that a driving voltage is low, a speed of data process is fast, and durability as well as reliance is high.
The ferroelectrics memory uses ferroelectric material having a perovskite structure such as PbTiO3[BT], (Pb, La)TiO3[PLT], Pb(Zr, Ti)O3[PZT], (Pb, La)(Zr, Ti)O3 as a capacitor dielectric film, and write and read data by the spontaneous polarization of the ferroelectrics.
That is, when the ferroelectrics is interposed between both electrodes and voltages having different electric potential are applied to each electrode, the ferroelectrics is polarized to a specific direction spontaneously. Read and write of data are performed by using the polarization direction.
For example, when the voltage of 5V is applied to an upper electrode and the voltage of 0V is applied to a lower electrode, the ferroelectrics interposed between both electrodes is polarized to the positive potential, thereby writing data xe2x80x9c1xe2x80x9d. Conversely, when 0V is applied to the upper electrode and 5V is applied to the lower electrode, the ferroelectrics is polarized to the-negative potential, thereby writing data xe2x80x9c0xe2x80x9d.
In case of data read, when 5V is applied to the upper electrode and 0V is applied to the lower electrode, the output voltage is compared with the reference voltage. If the output voltage is greater than the reference voltage, data xe2x80x9c1xe2x80x9d is read out. On the contrary, if the output voltage is smaller than the reference voltage, data xe2x80x9c0xe2x80x9d is read out. Herein, the output voltage is changed according to the direction of spontaneous polarization of the ferroelectrics.
As described above, the ferroelectrics memory is not affected by leakage current since it writes and reads data using the spontaneous polarization instead of a quantity of electric charges stored in capacitor.
However, although the ferroelectrics memory has the advantages as mentioned above, DRAM is generally incorporated in the semiconductor device to write and read data. The structure of semiconductor device having a memory like the above will be explained as following.
Although it is not shown in figures, a logic circuit area and a memory area are formed on the same plane of a semiconductor substrate with a predetermined area(for example, area ratio 1:1).
As described above, when the logic circuit area and the memory area are formed on the same plane, the utilization efficiency of the semiconductor substrate, namely the degree of integration becomes lowered. However such a construction prevents the capacitor from misoperating by a leakage current in spite of the disadvantage.
In more detail, the memory has a plurality of unit cells respectively consisting of one transistor and one capacitor and writes data by charging electric charges in the capacitor to correspond to the drive of the transistor. In reading the written data, the memory compares the voltage generated by charges stored in the capacitor with a predetermined reference voltage and determines whether the data stored in the capacitor is xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
For example, when DC voltage is applied to the capacitor, the memory compares the voltage outputted from the capacitor with the reference voltage, and reads out as data xe2x80x9c1xe2x80x9d if the output voltage is greater than the reference voltage. On the contrary, if the output voltage is smaller than the reference voltage, the memory reads out data as data xe2x80x9c0xe2x80x9d.
And, when the memory is formed on the upper portion of a logic circuit area to improve a degree of integration, electric charges stored in the capacitor may be lost by the leakage current in the capacitor of unit cells in memory.
For instance, electric charges stored in the capacitor may be lost by the leakage current generated when the transistor connected to the capacitor is off or at impurity diffusion area connected to the capacitor.
As explained above, when electric charges stored in loss of electric charges is great, the output voltage is lowered than the reference voltage. As a result, data xe2x80x9c1xe2x80x9d is read in the capacitor in which data xe2x80x9c1xe2x80x9d is stored.
Accordingly, until a recent date, there has been a problem that logic circuit area and memory should be formed on the same plane of the semiconductor device to assure reliance thereof, which inevitably results in decrease of integration degree.
Therefore, an object of the invention is to provide a semiconductor device having the ferroelectrics memory fit for the highly integrated semiconductor device and a method of manufacturing thereof.
In order to achieve the object, the semiconductor device according to the present invention comprises: a semiconductor substrate; a logic circuit area formed on the semiconductor substrate, the logic circuit area includes transistors for driving bit lines; and a ferroelectrics memory area laminated on the logic circuit area and including a transistor area and a capacitor area.
And also, the semiconductor device further comprises interconnection wirings formed on the logic circuit area and electrically connected to the transistors; bit lines formed on the upper part of the interconnection wirings, and electrically connected to the interconnection wirings; a silicon film formed on the upper side of the bit lines and defining a cell forming area; a transistor area formed on the silicon film and comprising a gate electrode, a source and a drain; and a capacitor formed on each transistor and electrically connected to the source of the transistor.
The method of fabricating a semiconductor device according to the present invention comprises steps of forming logic circuit area having interconnection wiring connected to bit line driving transistor on semiconductor substrate; forming bit line electrically connected to the interconnection wiring over the interconnection wiring; forming silicon film connected to the bit line over the bit line and restricting cell forming area; forming transistor consisting of gate electrode, source electrode, and drain electrode on the silicon film; and forming capacitor electrically connected to the source electrode over the transistor.
Moreover, another method of fabricating a semiconductor device according to the present invention comprises steps of forming a logic circuit area including interconnection wirings connected to bit line driving transistors on a semiconductor substrate; forming a first layer intermediate insulating film on the entire surface for exposing the upper side of the interconnection wirings; forming bit lines electrically connected the interconnection wirings on the first layer intermediate insulating film; forming a second layer intermediate insulating film on the entire surface after forming the bit lines for exposing the a part of the bit lines; defining a cell forming area by selectively patterning the second layer intermediate insulating film; forming a silicon film on a part of the defined cell forming area, the silicon film is connected to the bit lines; forming a gate insulating film and a gate electrode on the silicon film; forming a source electrode and a drain electrode on the silicon film situated under the both sides of the gate electrode; forming a lower electrode for a capacitor on the entire surface to expose the source electrode; and forming a dielectric film and an upper electrode on the lower electrode.