The present invention relates generally to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package and a method for manufacturing the same that exhibits a reduced electric resistance and an increased junction force.
These days, the semiconductor industry is actively engaged in developing more cost efficient ways of manufacturing semiconductor products that exhibit high reliability. Light weight, miniaturization, high speed operation, multi-functionality, and high performance features are also being actively developed by the semiconductor industry. In achieving these desired features, semiconductor package forming techniques are considered as one promising aspect in this rapidly developing and important technology in the semiconductor industry.
The semiconductor package forming techniques are designed to produce semiconductor chips that have their circuit patterns protected therein from outside circumstances. Further, semiconductor package forming techniques are designed to produce semiconductor packages that mount easily to a substrate so that the operational reliability of the semiconductor chips can be secured. The semiconductor package forming techniques include processes, such as, semiconductor chip attaching processes, wire bonding processes, molding processes and trimming/forming processes. The semiconductor package forming techniques can be either conducted at the chip level or the wafer level.
Recently, techniques for forming semiconductor packages by stacking at least two semiconductor chips or packages have gained much interest in achieving many of the above desired features. These stack package techniques have been developed to accomplish miniaturization, high capacity and high mounting efficiency in semiconductor packages. The stack package techniques promise to provide a semiconductor product that can realize a memory capacity greater than semiconductor products made from more conventional integration processes partly because mounting area utilization efficiency can be improved.
In stack packages, electrical connections are formed using metal wires, bumps or through-electrodes between semiconductor chips or packages and a substrate or between semiconductor chips or packages. Of particular note are stack packages that use through-electrodes in semiconductor chips or packages in which electrical degradation of the resultant stack packages can be avoided or minimized. As a consequence of using through-electrodes in stack packages, the resultant operation speed can be increased and the size of the stack package can be miniaturized. Accordingly, interest in further developing these types of stack packages has been grown.
However, stack packages that use through-electrodes are not without problems. In particular, because through-electrodes of upper and lower semiconductor chips or packages are joined with each other by different kind of metals such as solders, then increases in electric resistance and in electrical reliability degradation problems are likely to occur due to such things as deterioration brought about by substantial brittleness.
Further regarding stack packages that use through-electrodes, electrical and physical connections formed have small junction areas. As a consequence, these connections are likely to break or fail due to external forces such as external physical shocks. As a result, these types of stack packages that use through-electrodes are prone to suffering degradation to their reliability. It is known that the junction reliability of the stack packages can be improved by using adhesive tapes or filler materials. However, using adhesive tapes or filler materials necessarily results in additional processes that consequently increase the fabrication cost and/or the manufacturing time needed to assure that these semiconductor package products do not suffer post-manufacture deteriorate.
Moreover, because the junction areas of stack packages that incorporate through-electrodes are small, the electric resistance across these small junction areas increases. Accordingly, these semiconductor products cannot be used in high-performance electronic products that require high signal transmitting speeds.