The technology of SOI devices has resulted in significant improvements for integrated circuit application. In particular, high voltage devices have been designed where both the dielectric isolation and availability of a wide range of semiconductor thicknesses are desirable. Previous methods of forming SOI devices have included the direct silicon bonding technique, such as discussed by Lasky, Applied Physics Letters, Volume 48, No. 1, 6 Jan. 1986, pages 78-80. In this method, two silicon wafers are joined together to form a strong bond and then one of the wafers is thinned to the desired thickness.
One common approach to such thinning involves a mechanical grinding and polishing technique. This technique, however, has not resulted in SOI layers of a thickness less than 2-3 microns.
An etching technique for thinning a device is shown in the prior art by Maszara et al, Journal of Applied Physics, Volume 64, No. 10, 1988, page 4943 et seq. The conventional direct silicon bonding and thinning technique involves the process shown in FIG. 1. Herein, FIG. 1A shows a silicon wafer, referred to as the substrate, which has been oxidized with a silicon oxide layer, while FIG. 1B shows another silicon wafer referred to as the device wafer, which has been first formed with an etch stopping p+layer by either ion-implantation or epitaxial growth, and then a further epitaxially grown layer of either p-type or n-type is formed thereon. Subsequently, as seen in FIG. 1C, the two starting wafers are bonded together by placing the p-type or n-type layer of the device wafer onto the oxide layer of the substrate wafer. Then, as seen in FIG. 1D, the device wafer is etched to the p+ layer. Finally, as seen in FIG. 1E, the p+ layer is again etched away to leave a p-type or n-type device layer on the oxide layer on the silicon substrate.
This conventional technique involves numerous steps of epitaxial growth, etching, and implanting dopants. With this technique it is difficult to obtain SOI layer thicknesses less than about 1 micron.