1. Field of the Invention
The present invention relates to a counter control method in a microcomputer including a plurality of counters.
2. Description of the Prior Art
FIG. 4 is a block diagram illustrating the start/stop operation for counters included in a microcomputer of this type.
A clock signal (count pulse) transmitted on a signal line 1 from a clock generator (not shown) is input to one terminal of the switching means 4 and 5, which respectively control start/stop operations for the counters 2 and 3. Those counters 2 and 3 are adapted respectively to be different, for example, in their set counts and issue respectively onto signal lines 6 and 7, terminal count signals indicative of the ends of their countings up to the respective set counts.
FIG. 5 is a view of the address configuration of a register for illustrating a prior counter control system. This address configuration is based upon the like configuration of a control register described in the technical sheet of the 8/16 bit 1 chip microcomputer MSM66301 issued from Oki Electric Industry Co., Ltd. As the figure shows, the register has 8 bit information stored therein at its address (a). the bit 0 thereamong including switching information 4S allocated thereto for driving the switching means 4 which serves to start/stop the counter 2. In addition, the register has 8 bit information stored therein at its address (b) in the same manner, the bit 0 thereamong including switching information 5S for driving the switching means 5 which serves to start/stop the counter 3.
In succession, operation of this prior example will be described. The switching means 4 and 5 are closed once the switching information 4S and 5S of a logic level "1" are written in the register at the bits 0 of the respective addresses (a) and (b), for thereby starting the countings by the counters 2 and 3. They are opened once the switching information 4S and 5S of a logic level "0" is written in the register at the bits 0, for thereby stopping the countings by the counters 2 and 3. A central processing unit (operation control means) is assumed here to have a data bit length of 8 bits which are accessible all at one time.
When the central processing unit is needs to start both the counters 2 and 3, for example, using software, it writes data "xxxxxxxl" in the register at the address (a) of FIG. 5. As a result, the switching means 4 of FIG. 4 is closed to thereby start the counting by the counter 2. In succession, the central processing unit writes data "xxxxxxx1" in the same manner at the address (b). Thereupon, the switching means 5 is closed to thereby start the counting by the counter 3. The central processing unit is adapted in such a manner to twice write the data in the register at the addresses (a) and (b) for starting those two counters 2 and 3. That is, the central processing unit starts those two counters by accessing the register twice.
In the prior counter control system, as described above, the need of starting a plurality of counters produced during the associated processing requires a plurality of accesses for writing the information serving to start those counters in the register. In particular, when the object to be controlled requires a higher processing speed, it is needed to control a relative time difference between terminal count signals from the respective counters. Upon this control of the relative time difference, it is necessary to take into consideration not only a difference between the set counts of the counters 2 and 3 but a relative time difference between the first writing (writing of the information for starting the counter 2) and the second writing (that for starting the counter 3). The prior counter control system thus suffers from problems of, for example, complicating the control software to make demonstration of the real time property thereof (that to recognize the time when the central processing unit accesses the register within the whole very short processing time) difficult. So, in order to operate the control object at a very high processing speed, the time difference between the starts of the counters 2 and 3 is subtracted from the absolute time of the start of the counter 3. Hereby, the counters 2 and 3 are operated apparently so as to be simultaneously started. However, provided the event speed of the control object responsive to the terminal count signal is made very high, prior control software is unsatisfactory to operate that control object.