The incorporation of increasing numbers of discrete devices into progressively smaller integrated circuits remains an important challenge in the manufacture of Very Large Scale Integration (VLSI) structures. For example, the implementation of complementary metal-oxide semiconductor (CMOS) technology into integrated circuits usually involves imparting a prescribed set of manufacturing attributes to the integrated circuit, such as selected dopant concentrations, channel lengths, interconnect dimensions, contact shapes, or other pertinent attributes, which collectively permit the integrated circuit to provide a desired function.
Many of the desired features in VLSI structures may be formed using photolithographic methods. Briefly, and in general terms, a photolithographic mask (or reticle) is formed that includes a desired pattern corresponding to a particular masking step for the structure. The pattern generally includes optically transparent areas and optically attenuating areas that are suitably arranged on an optically transparent supporting substrate. The mask may then be positioned proximate to an illumination system and a layer of an illumination-sensitive photoresist material applied to a semiconductor wafer. The illumination system projects illumination radiation through the optically transmissive portions of the mask and onto the photoresist material, which suitably changes the properties of the photoresist material. Subsequent development of the exposed photoresist material thus permits the selective differentiation between exposed and non-exposed areas in the photoresist material so that the desired pattern may be subsequently formed on the semiconductor wafer.
When a wavelength of the illumination radiation is greater than a minimum feature size expressed on the mask, various optical effects may adversely affect the quality of features formed on a semiconductor structure. For example, a mask used to form a memory device array may include patterns having different orientations, such as a first set of generally horizontal features in an array portion of the memory device, and a second set of generally vertical and/or mixed features in a peripheral logic region. Although the illumination system may permit the first set of features to be accurately resolved at a first focal distance, undesired optical aberrations (including, for example, astigmatism) in the illumination system generally permit the second set of resolvable features to be accurately resolved only at a second focal distance that is different from the first focal distance. In one commonly employed method, a focal distance is selected for the illumination system that is intermediate between the first focal distance and the second focal distance so that the first set and the second set of features are projected from the mask and onto the wafer to yield a device pattern on the wafer having a correspondingly intermediate pattern resolution. As device features continue to decrease in size, however, the foregoing optical compensation method may be unable to generate device patterns at an acceptable resolution level.
Therefore, there presently exists an urgent need in the art for optical compensation methods, systems, and devices applicable to sub-resolution photolithography that permit aggressive reductions in device feature size.