1. Field of the Invention
The present invention relates to an exposure method used in the semiconductor process, more particularly to an exposure method which can correct the variation of the after-etch-inspection critical dimension (AEICD).
2. Description of the Prior Art
Lithography process is an important step in the transfer of the circuit pattern onto the substrate. After the photoresist is exposed to a patterned light beam and developed and after the substrate is etched, the substrate not covered by the photoresist is removed. In this way, the pattern can be transferred onto the substrate.
However, during the etching process, including wet etching and dry etching, due to the loading effect, the etching rate of the die region near the periphery of the wafer is different from the etching rate of the die region near the center of the wafer. Therefore, the after-etch-inspection critical dimension (AEICD) will vary in the die region located in different positions of the wafer. Accordingly, in the semi-conductor field, one of the challenges is to improve the AEICD uniformity.