1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly, to structures of a MOS (Metal Oxide Semiconductor) type LDD (Lightly Doped Drain) structure transistor and other MOS type transistors and a manufacturing method thereof.
2. Description of the Background Art
The basic structure of a MOS type field effect transistor comprises a source supplying carriers and a drain drawing carriers provided on both sides of a so-called MOS capacitor which has a silicon substrate and a metal electrode disposed thereabove with a thin oxide film provided therebetween. As the metal electrode on the oxide film has a function for controlling conductance between the source and the drain, it is referred to as a transfer gate electrode. As materials for the transfer gate electrode, impurity-doped polysilicon, and metal silicide formed by applying heat treatment in inert gas to refractory metal such as tungsten deposited on polysilicon are often employed.
When the voltage of the transfer gate electrode (gate voltage) is lower than the threshold voltage V.sub.th required for inverting conductivity type of the area adjacent to the silicon substrate surface between a source and a drain (channel), the source/drain are isolated by a pn junction and current does not flow. When a gate voltage higher than Vth is applied, the conductivity type of the channel surface is inverted, a layer of the same conductivity type as that of the source/drain is formed in this area, and current flows between the source and the drain.
If variations in impurity concentration distribution at the boundary of the source/drain and the channel are great, the electric field strength in the area is high. Carriers get energy due to the electric field, and so-called hot carriers are produced. The carriers are then injected into the transfer gate insulating film, sometimes to form an interface state at an interface region of the transfer gate insulating film and a semiconductor substrate, or sometimes to be trapped into the transfer gate insulating film. Thus, threshold voltage and transconductance of the MOS transistor are degraded during operation. This is the MOS transistor degradation phenomenon due to hot carriers. Avalanche voltage also falls due to the hot carriers. Therefore, the electric field strength is reduced by lowering the n-type impurity concentration in the vicinity of the source/drain to attain a small variation in the concentration distribution. In a MOS type LDD structure transistor, this suppresses the MOS transistor degradation due to the hot carriers and increases avalanche voltage of the source and the drain.
One of conventional manufacturing methods of MOS type LDD structure transistors is illustrated in FIGS. 1A to 1F. First in this method, a transfer gate oxide film 3 is formed in an element forming region surrounded by an element isolation insulating film 2 on a P-type semiconductor substrate 1 by so-called LOCOS (Local Oxidation of Silicon) method (FIG. 1A). Next, for controlling the threshold voltage, p-type impurity such as boron ion is directed all over the semiconductor substrate 1 to form ion-implanted regions 4 (FIG. 1B). Subsequently, a polysilicon film is deposited all over the transfer gate oxide film 3 by the low pressure CVD (Chemical Vapor Deposition) method to form a transfer gate electrode 5 by the photolithography technique and the reactive ion etching technique (FIG. 1C). Alternatively, as the transfer gate electrode 5, a two-layer film of refractory metal such as tungsten, molybdenum and titanium or silicidized version thereof, and polysilicon can be used in place of the polysilicon. Phosphorus ions are doped into the transfer gate electrode 5 to increase its conductivity. In this case, the transfer gate electrode 5 becomes n-type, which is the same as that of the channel or the source/drain. Accordingly, even when a gate voltage is not applied to the transfer gate electrode 5, the p-type channel surface is in such a state as a positive gate voltage is effectively applied because of the difference between work functions of the n-type transfer gate electrode 5 and the p-type channel surface.
This is described as follows according to the band theory. First, with no n type transfer gate electrode 5 on the channel surface, bands of the transfer gate electrode 5, transfer gate oxide film 3 and the p type semiconductor substrate 1 appear as shown in FIG. 1G. When a transfer gate electrode 5 is formed on the channel surface with a transfer gate oxide film 3 provided therebetween, the bands change as shown in FIG. 1H. The change of bands occurs because the Fermi level E.sub.FG of the transfer gate electrode 5 and the Fermi level E.sub.FS of the semiconductor substrate 1 become equal to produce balanced conditions and the band in the vicinity of the surface of the semiconductor substrate 1 is bent downwards under the effect of the electric field by the transfer gate electrode 5. After forming the transfer gate 5, as shown in FIG. 1H, free electrons are induced in the vicinity of the surface of the semiconductor substrate 1. Accordingly, the transfer gate electrode 5 is in a condition in which positive potential is effectively applied thereto.
Also, the n-type impurity doped in the transfer gate electrode 5 may diffuse into the p-type channel surface due to thermal treatment thereafter. V.sub.th falls because of these reasons, and it is possible to happen that an inverted layer is already produced in the channel in some cases. The ion-implanted regions 4 described above are for overcoming the effect of impurity ion doped into the transfer gate electrode 5 by implanting p-type impurity in advance to surely obtain desired V.sub.th.
Next, with the gate electrode 5 as a mask, n-type impurity such as phosphorus ion and arsenic ion is implanted vertically into the semiconductor substrate 1 surface to form n-type ion-implanted layers 6 (FIG. 1D). Subsequently, an insulating film of silicon dioxide or the like is deposited all over the surface of the semiconductor substrate 1 by the low pressure CVD method or the atmospheric pressure CVD method, to which anisotropic etching is applied to form sidewall spacers 7 (FIG. 1E). Next, using the transfer gate electrode 5 and the sidewall spacer 7 as masks, n-type impurity such as phosphorus ion and arsenic ion is vertically directed to the surface of the semiconductor substrate 1 to form n-type ion-implanted layers 8 of higher concentration than that of the ion-implanted layers 6 (FIG. 1F). Thus, after heat treatment for activating the implanted impurity ion, a MOS type LDD structure transistor is completed.
While a p-type semiconductor substrate is employed in the above described conventional embodiment, a substrate having a p-well, or a p-type impurity-implanted region, at least near the substrate surface can also be employed. Furthermore, as a substrate, an n-type semiconductor substrate or a substrate having n-well, an n-type impurity-implanted region, at least near the surface may be employed. In this case, a transfer gate electrode 5 is p-type, ion-implanted regions 4 for controlling a threshold voltage are n-type, and p-type ion-implanted layers 6 and 8 are formed as a source region and a drain region.
As the embodiment above is based on ion-implantation only in a direction perpendicular to the surface of the semiconductor substrate 1, the ion-implanted regions 4 for controlling the threshold voltage must be formed before forming the transfer gate electrode 5. On the other hand, as for a method of forming respective ion-implanted layers after forming a transfer gate electrode 5 by applying the oblique ion implantation method, reference is made to Japanese Patent Laying-Open No. 61-226968. As illustrated in FIGS. 2A-2D, in the method of manufacturing a MOS type semiconductor device described in the gazette, using a field oxide film 12 and a gate 14 formed on a p-type semiconductor substrate 11 as masks, n-type regions 18 are formed by implanting phosphorus ions with acceleration voltage of 20 keV (FIG. 2A). Subsequently, by directing boron ions using the gate electrode 14 as a mask at the angle of incidence of 30.degree. and with acceleration voltage of 30 keV, p-type regions 19a are formed (FIG. 2B). Upon performing similar oblique ion implantation from the opposite side, the p-type regions 19a and 19b are formed entirely surrounding the side and the bottom of the n-type regions 18 (FIG. 2C).
Next, the photoresist 20 is formed around the gate 14, and using the same as a mask, arsenic ions are implanted at high concentration to form n-type regions 21 as the source/drain (FIG. 2D).
Finally, a silicon oxide film 22 is deposited all over the surface by the CVD method, contact holes are formed at predetermined positions in the respective regions of gate, source and drain by the reactive ion etching method or the like, and aluminum is deposited by the sputtering method or the CVD method and patterned, then an n-channel MOS type semiconductor device is completed.
As described above, according to the conventional embodiment, the p-type regions 19a and 19b are formed by oblique ion implantation, and respective ion-implanted layers are formed after forming the gate electrode 14.
Among the above-described conventional manufacturing methods of semiconductor devices, in the first conventional embodiment, by vertically implanting ions all over the surface of the semiconductor substrate 1 before forming the transfer gate electrode 5, the ion implanted regions 4, or a diffusion layer for controlling the threshold voltage, is formed. Accordingly, the p-type impurity ion concentration distribution is almost uniform all over the channel region as shown by the broken line in the graph of FIG. 3. This tendency does not change greatly after the step of thermal diffusion, and the distribution is shown by the double dashed line in FIG. 3. As the threshold voltage is determined corresponding to an almost average value of the channel potential over the channel region, upon setting a predetermined threshold voltage, the average value of the concentration distribution of the ion-implanted regions 4 to be formed is determined accordingly. In the first conventional example, the concentration distribution of the ion-implanted regions 4 in the vicinity of the channel region, or the distribution of the channel potential becomes almost uniform, and the channel potential in the vicinity of the source region and the drain region becomes a relatively low value almost the same as the potential in the center area of the channel. Accordingly, a sufficient potential barrier is not formed in the vicinity of the source/drain regions on both ends of the channel region. Thus, the extension of the depletion layer toward the semiconductor substrate in the vicinity of the source and drain increases. As the device is highly integrated, and as the length of the transfer gate electrode, or the effective channel length becomes shorter, an electrical short between the source and the drain occurs more easily because of the extension of the depletion layer, and the punchthrough breakdown voltage between the source and the drain falls. If the concentration of the ion in the channel region is increased to restrain the extension of the depletion layer, the threshold voltage becomes higher than a desired value.
Also, the so-called ALPEN (Alpha Particle Source/Drain Penetration) effect, wherein .alpha.-particles irradiated by the radioactive isotope such as uranium or thorium in the resin molded package pass through the source/drain regions, becomes more apt to happen. Because of this ALPEN effect, if the .alpha.-ray hits a memory cell, for example, a so-called soft error in which information of a memory is broken to cause a malfunction occurs. In conditions of information "H" where electrons are not collected in capacitor of a memory cell, if the .alpha.-particles hit this memory cell, electron-hole pairs are produced because of current effect by the .alpha.-particle's energy, and the electrons are collected in a depletion layer so that the condition of information "L" is attained. When the .alpha.-particles pass through the source/drain, electron-hole pairs are produced along the path of the .alpha.-particles. The electron-hole pairs are separated by the electric field of the depletion layer between the source or the drain and the semiconductor substrate, and a new transient depletion layer is produced along the path of the .alpha.-particles. The phenomenon that a transient depletion layer is produced along the path of the .alpha.-particles is referred to as a funneling phenomenon. During operation of a transistor, if a transient depletion layer due to the funneling phenomenon is produced between the depletion layers in the vicinity of the source/drain, a transient punchthrough occurs between the source and the drain, which causes a soft error in a new mode ("L.fwdarw.H" soft error).
As described above, in a manufacturing method like the first conventional example, as the device is highly integrated, the source/drain breakdown voltage falls and the soft error becomes more apt to happen, and there is a problem that the initial characteristic and the long term reliability confidence of the device is degraded.
The p-type regions 19a, 19b formed in the second embodiment serve as barriers for preventing a punch through at both ends of the channel region. However, these p-type regions 19a, 19b are formed independently of control of the threshold voltage of the channel region. Accordingly, in addition to increasing the number of steps, it also affects the predetermined threshold voltage.