This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-066734, filed Mar. 10, 2000; No. 2000-087403, filed Mar. 27, 2000; and No. 2000-087417, filed Mar. 27, 2000, the entire contents of all of which are incorporated herein by reference.
The present invention relates to a semiconductor device having a ferroelectric capacitor and a method for manufacturing the ferroelectric capacitor.
Ferroelectric substances have a hysteresis characteristic between applied electric fields and the amount of electric polarization; thus, polarization remains even if a voltage applied between opposite ends of the ferroelectric substance is returned to zero. That is, the ferroelectric substance is characterized in that electric polarization generated when electric fields are applied remains even after the application of electric fields has been stopped and in that the direction of the polarization is reversed when electric fields of a certain intensity or more are applied in a direction opposite to that of the above electric fields.
Memory which consists of series connected memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor inbetween the two terminals, hereafter named xe2x80x9cSeries connected TC unit type ferroelectric RAMxe2x80x9d is gathering the industry""s attention. In these Series connected TC unit type ferroelectric RAMs, the cell area per memory cell is reduced based on the non-volatile characteristic of ferroelectric substances, by connecting opposite ends of a ferroelectric capacitor (C) between a source and a drain of a cell transistor (T) to constitute a unit cell and connecting a plurality of such unit cells in series.
These Series connected TC unit type ferroelectric RAMs are known, for example, from xe2x80x9cHigh-Density Chain Ferroelectric Random Access Memory (CFRAM)xe2x80x9d, VLSI Circuit Symposium, 1997, p.83-84, xe2x80x9cA Sub-40 ns Random-Access Chain FRAM Architecture with 7 ns Cell-Plate-Line Drivexe2x80x9d, ISSCC Tech. Digest Papers, pp.102-103, Feb 1999, and xe2x80x9cFerro Electric RAMxe2x80x9d, D. Takashima et al., JSSCC, pp.787-792, May 1998xe2x80x9d.
FIG. 1 shows an equivalent circuit of the Series connected TC unit type ferroelectric RAMs described in these documents. In this figure, eight transistors T0 to T7 are connected in series, and ferroelectric capacitors are each connected between a source and a drain of a corresponding one of the transistors to constitute a cell array block. The cell array block has one end connected to a bit line BL via a selection gate transistor ST1 and the other end connected to a plate line PL via a selection gate transistor ST2 (or directly).
The transistors T0 to T7 have their gates connected to word lines WL0 to WL7, respectively, and the selection gate transistors ST1 and ST2 have their gates connected to selection gate lines BS1 and BS2, respectively. Specifically, the word lines WL0 to WL7 and the selection gate lines BS1 and BS2 are configured by continuously forming corresponding gate electrodes between a plurality of other cell array blocks (not shown).
The Series connected TC unit type ferroelectric RAMs are advantageous in that the unit cell area can be reduced by sharing a diffusion layer of the adjacent transistor within the cell array block; theoretically, these memories can achieve 4F2 (F denotes a minimum size). Further, the area occupied by peripheral circuits can be reduced compared to ordinary ferroelectric memories, thereby reducing the chip size and costs.
The Series connected TC unit type ferroelectric RAMs also have an excellent characteristic that the plate line PL connected to the other end can be formed of the diffusion layer formed outside the cell array and thus has low resistance, whereby drivers are not required to have high performance. The Series connected TC unit type ferroelectric RAMs can thus operate faster than ordinary ferroelectric memories.
As described above, the Series connected TC unit type ferroelectric RAMs have various characteristics, but also have problems.
That is, for memory cells of a capacitor on plug (COP) structure in which, for example, a tungsten plug (W plug) is formed on a source and a drain diffusion layer of a transistor as a contact plug with a ferroelectric capacitor formed on the W plug, a barrier metal must be interposed between the W plug and the ferroelectric capacitor to prevent oxidation of the W plug, but no metal has been found suitable to be such a barrier metal.
Thus, an upper and a lower electrode of the ferroelectric capacitor are connected to the source and drain diffusion layers of the transistor by separately forming metal wiring.
FIGS. 2A to 2E show a conventional method for manufacturing a ferroelectric capacitor for a series connected TC unit type ferroelecric RAM, in the order of steps.
First, as shown in FIG. 2A, a lower electrode 12, a ferroelectric film 13, and an upper electrode 14 are sequentially deposited on an interlayer insulating film 11 provided on a semiconductor substrate.
Then, as shown in FIG. 2B, an etching mask 15 having a predetermined pattern shape is formed and used to etch the upper electrode 14.
Then, the mask 15 is removed and a new etching mask 16 having a predetermined pattern shape is subsequently formed as shown in FIG. 2C. In this case, the mask 16 is shaped so as to continuously cover the two upper electrodes 14. The mask 16 us used to etch the remaining part of the ferroelectric film 13 and lower electrode 12.
Then, as shown in FIG. 2D, an interlayer insulating film 17 is deposited on the entire top surface, wiring grooves 18 and contact holes 19 for the two upper electrodes 14 are formed in the interlayer insulating film 17, and a wiring groove 20 and a contact hole 21 for the lower electrode 12 are further formed.
Subsequently, contact plugs/wires 22 are formed so as to fill the wiring grooves 18 and 20 and the contact holes 19 and 21. The contact plugs/wires 22 are connected to a source and a drain diffusion layers of a transistor (not shown).
In this conventional method, when the contact hole 21 for the lower electrode 12 is formed, the interlayer insulated layer 17 and the ferroelectric film 13 must be etched. An etching rate for the ferroelectric film is low, about one tenths (for example, 50 nm/sec.) of that for the interlayer insulating film, thus requiring a large amount of time to form the deep contact hole 21 for the lower electrode 12. Consequently, when the contact holes 19 for the upper electrodes 14 are formed, relatively large parts of the upper electrodes 14 are removed as shown in FIG. 2D, thereby disadvantageously degrading capacitor characteristics or inducing capacitor leakage.
Furthermore, it has been found that since the contact hole 21 for the lower electrode 12 penetrates the ferroelectric film 13, an etching gas may damage the ferroelectric film to degrade polarization.
The present invention has been made in view of the foregoing. An object of the invention is to provide a semiconductor device, a semiconductor storage device and a method of manufacturing the same, in which the degradation of capacitor characteristics or the capacitor leakage is prevented when a part of the upper electrode is etched in the process of making contact holes and in which the damage to the ferroelectric film is reduced to prevent the deterioration of the ferroelectric capacitor, which would otherwise occur due to polarization.
According to the present invention, there is provided a semiconductor device comprising a first interlayer insulating film formed on a semiconductor substrate, a lower electrode formed on the first interlayer insulating film, a pair of ferroelectric films formed on the lower electrode separately from each other, and a pair of upper electrode formed on the pair of ferroelectric films, wherein the lower electrode, the pair of ferroelectric films, and the pair of upper electrodes constitute a pair of ferroelectric capacitors and portions of the lower electrode which are located under the pair of ferroelectric films are thicker than the other portions of the lower electrode.
According to the present invention, there is provided a method for manufacturing a semiconductor device comprising sequentially forming a lower electrode, a ferroelectric film, and an upper electrode on a first interlayer insulating film formed on a semiconductor substrate, forming a first mask on the upper electrode, using the first mask to sequentially etch the upper electrode and the ferroelectric film to leave on the lower electrode a pair of laminated structure comprising the ferroelectric film and the upper electrode, forming a second mask having such a pattern shape that continuously covers at least the pair of laminated structure, using the second mask to etch the lower electrode to thereby leave portions of the lower electrode in which the pair of laminated structures comprising the ferroelectric film and the upper electrode are formed.
According to the present invention, there is provide a semiconductor device comprising an interlayer insulating film formed on a semiconductor substrate, a lower electrode formed on the interlayer insulating film, a pair of ferroelectric films formed on the lower electrode separately from each other and each having a recess portion, and a pair of upper electrodes formed so as to fill recess portions of the pair of ferroelectric films, wherein the lower electrode, the pair of ferroelectric films, and the pair of upper electrode constitute a pair of ferroelectric capacitors.
According to the present invention, there is provided a method for manufacturing a semiconductor device comprising forming a lower electrode on a first interlayer insulating film formed on a semiconductor substrate, leaving the lower electrode only at selected portions of the first interlayer insulating film, while removing the other portions, forming a second interlayer insulating film on the entire top surface including a surface of the lower electrode and then executing a flattening process to expose the lower electrode, forming a third interlayer insulating film on the entire top surface and then forming two openings in the third interlayer insulating film so as to lead to the surface of the lower electrode, sequentially forming a ferroelectric film and an upper electrode on the entire top surface including interiors of the two openings, and executing a flattening process to leave laminated structures in the two openings, the laminated structures comprising the ferroelectric film and the upper electrode.
According to the present invention, there is provided a method for manufacturing a semiconductor device comprising forming a lower electrode on a first interlayer insulating film formed on a semiconductor substrate, leaving the lower electrode only at selected portions of the first interlayer insulating film, while removing the other portions, forming a second interlayer insulating film on the entire top surface including a surface of the lower electrode and then executing a flattening process, forming two openings in the second interlayer insulating film so as to lead to the surface of the lower electrode, sequentially forming a ferroelectric film and an upper electrode on the entire top surface including interiors of the two openings, and leaving laminated structures only in the two openings, the laminated structures comprising the ferroelectric film and the upper electrode.
According to the present invention, there is provided a method for manufacturing a semiconductor device comprising forming a first interlayer insulating film on a second interlayer insulating film formed on a semiconductor substrate, forming a first opening in the first interlayer insulating film, depositing a lower electrode on the entire top surface, executing a flattening process to expose the first interlayer insulating film, while leaving the lower electrode in the first opening, forming a third interlayer insulating film on the entire top surface, forming a pair of second openings in the third interlayer insulating film so as to lead to a surface of the lower electrode, sequentially forming a ferroelectric film and an upper electrode on the entire top surface including interiors of the pair of second openings, and flattening the ferroelectric film and the upper electrode to leave the ferroelectric film and the upper electrode in the pair of second openings.
According to the present invention, there is provide a semiconductor device comprising a first interlayer insulating film formed on a semiconductor substrate, a first lower electrode formed on the first interlayer insulating film, a pair of second lower electrodes formed on the first lower electrode separately from each other and each having a recess portion, a pair of ferroelectric films formed so as to fill recess portions of the pair of second lower electrodes and each having a recess portion, and a pair of upper electrodes formed so as to fill recess portions of the pair of ferroelectric films, wherein the first lower electrode, the pair of second lower electrodes, the pair of ferroelectric films, and the pair of upper electrode constitute a pair of ferroelectric capacitors.
According to the present invention, there is provided a method for manufacturing a semiconductor device comprising forming a first interlayer insulating film on a second interlayer insulating film formed on a semiconductor substrate, forming a first opening in the first interlayer insulating film, forming a first lower electrode on the entire top surface, executing a flattening process to expose the first interlayer insulating film, while leaving the first lower electrode in the first opening, forming a third interlayer insulating film on the entire top surface, forming a pair of second openings in the third interlayer insulating film so as to lead to a surface of the lower electrode, sequentially forming a second lower electrode, a ferroelectric film, and an upper electrode on the entire top surface including interiors of the pair of second openings, and flattening the second lower electrode, the ferroelectric film, and the upper electrode to leave the second lower electrode, the ferroelectric film, and the upper electrode in the pair of second openings.
According to the present invention, there is provided a method for manufacturing a semiconductor device comprising forming a first lower electrode on a first interlayer insulating film formed on a semiconductor substrate, leaving the first lower electrode only at selected portions of the first interlayer insulating film, while removing the other portions, forming a second interlayer insulating film on the entire top surface including a surface of the first lower electrode and then executing a flattening process to expose the first lower electrode, forming a third interlayer insulating film on the entire top surface and then forming two openings in the third interlayer insulating film so as to lead to the surface of the lower electrode, sequentially forming a second lower electrode, a ferroelectric film, and an upper electrode on the entire top surface including interiors of the two openings, executing a flattening process to leave laminated structures in the two openings, the laminated structures comprising the second lower electrode, the ferroelectric film, and the upper electrode.
According to the present invention, there is provided a method for manufacturing a semiconductor device comprising forming a first lower electrode on a first interlayer insulating film formed on a semiconductor substrate, leaving the first lower electrode only at selected portions of the first interlayer insulating film, while removing the other portions, forming a second interlayer insulating film on the entire top surface including a surface of the first lower electrode and then executing a flattening process, forming two openings in the second interlayer insulating film so as to lead to the surface of the first lower electrode, sequentially forming a second lower electrode, a ferroelectric film, and an upper electrode on the entire top surface including interiors of the two openings, and executing one of an etchback process and flattening etching process to leaving laminated structures only in the two openings, the laminated structures composing the second lower substrate, the ferroelectric film, and the upper electrode.
According to the present invention, there is provide a semiconductor storage device comprising a semiconductor substrate, a plurality of transistors formed on the semiconductor substrate, a first interlayer insulating film formed so as to cover the plurality of transistors, and a plurality of ferroelectric capacitors each comprising a laminated structure of a lower electrode, a ferroelectric film, and an upper electrode sequentially formed on the first interlayer insulating film, wherein the plurality of ferroelectric capacitors constitute sets each comprising two of these ferroelectric capacitors, the lower electrode is shared by the one set of ferroelectric capacitors, the upper electrode is individually separated between the one set of ferroelectric capacitors, and a space between the upper electrodes of the one set of ferroelectric capacitors is smaller than a space between the upper electrodes of the one set of ferroelectric capacitors and the upper electrodes of an adjacent set of ferroelectric capacitors.
More specifically, the one set of ferroelectric capacitors have their peripheries formed into inclined surfaces extending continuously from a top surface of the upper electrode to a bottom surface of the lower electrode and having no step, and the individual upper electrodes of the one set of ferroelectric capacitors are separated by a generally V-shaped groove.
Thus, the upper electrodes of the ferroelectric capacitors are not spaced at equal intervals, and the space between the upper electrodes of one set of ferroelectric capacitors on the shared lower electrode is smaller than the space between the upper electrodes of one set of ferroelectric capacitors and the upper electrodes of the adjacent set of ferroelectric capacitors, thereby reducing the unit cell area.
According to the present invention, the semiconductor substrate preferably partitioned into a plurality of element forming areas each having the plurality of transistor formed therein, adjacent ones of the plurality of transistors share a diffusion area and are arranged in a row, and the ferroelectric capacitors are connected in parallel with the transistors to constitute a cell array block.
In this case, gate electrodes of the transistors extended in a direction crossing a transistor arranging direction of the cell array block constitute a word line, and the space between the upper electrodes of the one set of ferroelectric capacitors is smaller than the width of the word line.
When the upper electrodes are separated by the space smaller than the width of the word line, the upper electrodes have larger areas to provide excellent characteristics even if the ferroelectric capacitors are arranged at a very small pitch. Specifically, the word line width is equal to a minimum dimension according to design rules.
Furthermore, according to the present invention, there is provide a semiconductor storage device comprising a semiconductor substrate, a plurality of transistors formed on the semiconductor substrate, a first interlayer insulating film formed so as to cover the plurality of transistors, and a plurality of ferroelectric capacitors each comprising a laminated structure of a lower electrode, a ferroelectric film, and an upper electrode sequentially formed on the first interlayer insulating film, wherein the plurality of ferroelectric capacitors constitute sets each comprising two of these ferroelectric capacitors, the lower electrode is shared by the one set of ferroelectric capacitors, the upper electrode is individually separated between the one set of ferroelectric capacitors and has a space, the one set of ferroelectric capacitors have peripheries thereof formed into inclined surfaces extending continuously from a top surface of the upper electrode to a bottom surface of the lower electrode and having no step, and the individual upper electrodes of the one set of ferroelectric capacitors are separated by a generally V-shaped groove.
According to the present invention, there is provided a method for manufacturing semiconductor storage device comprising forming a plurality of transistors in and on a semiconductor substrate, forming an interlayer insulating film on the entire top surface, forming a lower-electrode material film, a ferroelectric film, and an upper-electrode material film on the interlayer insulating film to constitute a plurality of ferroelectric capacitors, forming an etching mask on each upper-electrode forming area of the upper-electrode material film, using the etching mask to separate the upper electrodes of the plurality of ferroelectric capacitors, while separating, in order to allow the lower electrode to be shared by one set of plurality of ferroelectric capacitors, the lower electrode between the adjacent ferroelectric capacitors of the set.
According to the present invention, there is provide a method for manufacturing a semiconductor storage device comprising forming an isolation film in a semiconductor substrate and partitioning the semiconductor substrate into a plurality of element forming areas, forming a plurality of transistors in each of the plurality of element forming areas, the transistors each having a first and a second diffusion regions in such a manner that the transistor is adjacent, at one side, to the first diffusion region, which is shared by the adjacent transistor on this side, while the transistor is adjacent, at the other side, to the second diffusion region, which is shared by the adjacent transistor on this side, forming a first interlayer insulating film on the entire top surface, burying a contact plug in the first interlayer insulating film, the contact plug being connected to each of the first diffusion areas of the plurality of transistors, sequentially forming a lower-electrode material film, a ferroelectric film, and an upper-electrode material film on the first interlayer insulating film to constitute a plurality of ferroelectric capacitors, forming an etching mask on each upper-electrode forming area of the upper-electrode material film, using the etching mask and etching to separate upper electrodes of each of the ferroelectric capacitor while separating the adjacent pairs of ferroelectric capacitors in such a manner that the pair of ferroelectric capacitors share the lower electrode connected to the contact plug, forming a second interlayer insulating film so as to cover all of the top surface, and a step of forming a wiring layer on the second interlayer insulating film, for connecting the upper electrode of the ferroelectric capacitor to the second diffusion region of the corresponding transistor.
According to the present invention, there is provide a method for manufacturing a semiconductor storage device comprising forming a plurality of transistors in a semiconductor substrate, the transistors each having a first and a second diffusion regions in such a manner that the transistor is adjacent, at one side, to the first diffusion region, which is shared by the adjacent transistor on this side, while the transistor is adjacent, at the other side, to the second diffusion region, which is shared by the adjacent transistor on this side, forming a first interlayer insulating film on the entire top surface, forming an opening leading to a surface of the first diffusion region of each of the plurality of transistors and forming a plug electrode in the opening, sequentially forming a lower-electrode material film, a ferroelectric film, and an upper-electrode material film on the first interlayer insulating film so as to contact with the plug electrode, forming a mask pattern for etching the upper-electrode material film so that a pair of upper electrodes are located on the plug electrode, using the mask pattern to etch the upper-electrode material film, the ferroelectric film, and the lower-electrode material film to thereby form a pair of upper electrodes, a ferroelectric film, and a lower electrode on the plug electrode, forming a second interlayer insulating film on the entire top surface, and forming a wiring layer for connecting the second diffusion regions of the plurality of transistors and the upper electrodes together.
According to the present invention, there is provide a method for manufacturing a semiconductor storage device comprising forming a plurality of transistors in a semiconductor substrate, the transistors each having a first and a second diffusion regions in such a manner that the transistor is adjacent, at one side, to the first diffusion region, which is shared by the adjacent transistor on this side, while the transistor is adjacent, at the other side, to the second diffusion region, which is shared by the adjacent transistor on this side, forming a first interlayer insulating film on the entire top surface, forming a first opening leading to a surface of the first diffusion region of each of the plurality of transistors and forming a plug electrode in the opening, sequentially forming a lower-electrode material film, a ferroelectric film, and an upper-electrode material film on the first interlayer insulating film so as to contact with the plug electrode, forming a mask pattern for etching the upper-electrode material film, using the mask pattern to etch the upper-electrode material film to form a pair of upper electrodes, forming a side wall insulating film on side walls of the pair of upper electrodes and arranging, on the plug electrode, a portion of the side wall insulating film located between the pair of upper electrodes, using the mask pattern and the side wall insulating film to sequentially etch the ferroelectric film and the lower-electrode material film to form a pair of ferroelectric films and a lower electrode on the plug electrode, forming a second interlayer insulating film on the entire top surface, and forming a wiring layer for connecting the second diffusion regions of the plurality of transistors and the upper electrodes together.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.