1. Field of the Invention
The present disclosure relates generally to memory fault testing, and more specifically to a system and method for identifying address-swap faults in multiport memories.
2. Description of the Related Art
An address “mis-decode” fault occurs when an address applied to a memory accesses a different memory location, that is, a location that is not the addressed location. An address-swap occurs when a first address ends up accessing a location of a second address, and the second address ends up accessing a location of the first address. Address mis-decode faults occur due to various defects on the address bus, such as stuck-at faults, shorts and opens. Address-swap faults occur, however, when there is an inversion fault, or when two bits of an address bus are swapped due to a design implementation error or because of faulty wiring. Defects such as shorts and opens can result in inversion faults. An inversion fault occurs when defects in a circuit result in a logic net flipping to the opposite value (e.g., actual value on a logic net is logic “1” but is flipped or inverted to a logic “0” and vice-versa).
Bit-swap faults and inversion faults were not considered an interesting class of faults for logic circuits because they are implicitly detected by conventional and existing test routines employing common fault models such as the stuck-at fault model. Bit-swap and inversion faults are undetectable for single-port memories. Such faults were considered inconsequential for single-port memories since as long as a data value is correctly stored using an address value (even if at a different location) and is correctly read out using the same address value, the single-port memory operates as intended. Bit-swap and inversion faults, however, may cause chip failure for multiport memory devices and further may be undetectable. In the case of multiport memory devices, a fault at one port causes read and/or write errors at other ports and vice-versa. Conventional test procedures or routines were unable to detect such address-swap faults in multiport memory devices.