The present invention relates generally to communication systems. More particularly, the present system relates to the cell or packet switching, assembly and disassembly associated with cell or packet switched networks.
Various systems have been adopted to carry digitally-encoded signals for communication applications, such as, telephone, video, and data services. These systems are often connection-oriented transmission systems, such as, asynchronous transfer mode (ATM) systems, frame relay systems, X.25 systems, or other transmission systems. Connection-oriented systems (e.g., ATM systems) have been employed in private and public communication systems or networks (e.g., wide area networks (WANs)) to transfer packetized signals (e.g., data cells or protocol data units) across communication lines, such as, telephone lines, cables, optical fibers, air waves, satellite links, or other communication media. Cell based networks transfer data units of a constant length, while packet based networks transfer data units of variable length. Therefore, the term packet used herein refers to variable sized data units, as in IP networks or frames as well as in Ethernet or token ring networks.
Generally, ATM systems are comprised of nodes or elements which communicate information in cells between each other to ultimately transfer information from a source to a destination. The node or element can be an ATM switch, a port or edge device, computer equipment, communication device, or any apparatus for relaying information. Each of the data cells communicated in an ATM system contains headers identifying the connection and also contains a payload providing the information being transmitted and received. During the transfer of the cells throughout the network to the destination, the headers may be changed to indicate the path that the cell is following to reach the receiving equipment.
ATM systems are typically coupled to telephones, modems, other networks, or other communication devices through a port or edge device. The port or edge device receives data cells from the ATM system and transforms these into data units and provides the data units to the systems coupled thereto. Additionally, the edge device receives data units from the systems coupled thereto and provides data cells representative of the data units to the ATM system. Thus, the edge device can provide translation and routing functions, such as adaptation, segmentation, and reassembly operations to interface the systems coupled to it to the ATM system. The edge device often must adapt the data cells of the ATM system to the formats of the systems coupled thereto. The edge device can be an adapting network interface card, an adapting switch, an adapting concentrator, an ATM desktop device, a router access multiplexer, or other interface device.
ATM systems generally include the capability of distinguishing between cell generating, cell terminating, and cell switching elements in the ATM network. The generation or segmentation of data packets into cells on the data source side of an ATM network as well as the reassembly of cells into data packets on the data destination side of an ATM network can be performed by a segmentation and reassembly (SAR) device. U.S. Pat. No. 5,768,275, issued on Jun. 16, 1998, to Lincoln et al., entitled xe2x80x9cController for ATM Segmentation and Reassembly,xe2x80x9d the disclosure of which is incorporated herein by reference, discloses one such SAR device.
Conventional SAR devices segment packets received from an attached processor (as a source of communication) into cells. Such SAR devices also reassemble received cells and forward them to the attached processor (as a destination for communication). The content of the cells is stored in buffers. The SAR device has a pool of free buffers in a free buffer queue. When a data packet is received by the SAR device from one of the input ports, the SAR device reads a free buffer and buffer descriptor from a free buffer pool. The SAR device writes the data packet information into the free buffer and writes the buffer descriptor to a reassembly status queue. The processor (as a destination of the communication) reads the buffer descriptor from the reassembly status queue, processes the data contained in the buffer, and writes the buffer and buffer descriptor back to the free buffer pool.
For data transmission, the processor (as a source of communication) writes communication data to buffers and writes their corresponding buffer descriptor to the transmit queue. The SAR device segments the buffers, transmits the cells, and then returns the buffers to the processor by writing the buffer descriptors to a segmentation status queue. The processor reads the buffer descriptor and makes the corresponding buffers available for future transmission.
Conventionally, the switching of cells in an ATM system is performed by an ATM switch. An ATM switch routes cells from any of its input ports to any of its output ports. Furthermore, the ATM switch modifies the header information of each cell to indicate the path that the cell is following to reach its destination. Conventional ATM systems do not integrate cell generating, cell terminating, and cell switching operations into one element in the ATM network.
Thus, there is a need for the integration of segmentation, reassembly, and switching functions into one device or element in the ATM system. Further, there is a need to combine the operations of cell generation or termination and cell switching. Even further, there is a need for a node in the ATM network to be able to perform as a communication source, destination, and switch. Even further, there is a need for a node at the interface between ATM networks and packet based networks to perform switching between any combination of packet and cell ports, segmenting of packets into cells, and reassembling cells into packets.
One embodiment of the invention relates to a communication system for communication of data packet or cells associated with a packet or cell switched network. The system includes a plurality of ports and a switching segmentation and reassembly device. The ports communicate data packets or cells to and from at least one communication source (e.g. an attached processor) and at least one destination. The switching segmentation and reassembly device routes data packets or cells to and from the ports and the at least one destination. The switching segmentation and reassembly device further switches data packets or cells between ports.
Another embodiment of the invention relates to a communication apparatus for communication of data packets or cells associated with a packet or cell switched network to a plurality of ports. The apparatus includes an interface, a memory, and a segmentation and reassembly block. The interface couples the plurality of ports to the communication apparatus. The memory stores the content of data packets received from the plurality of ports and information on virtual channels to the plurality of ports. The segmentation and reassembly block assembles data packets, processes data from memory, writes the buffer descriptor corresponding to the received data packet to memory for future transmission, segments data packets, and transmits data packets to the corresponding destination port.
Another embodiment of the invention relates to a method for communication of data packets or cells associated with a packet or cell switched network in a communication system from a source physical device to a destination physical device. The method includes receiving a data packet or cell including a header and payload from the physical device; assigning the data packet or cell received to a connection identifier; making necessary changes to data packet or cell header; segmenting received packets into cells; reassembling received cells into packets; and communicating data packet or cells to the destination physical device as indicated by the connection identifier.