This application claims the priority benefit of Taiwan application serial no. 89115392, filed Aug. 1, 2000.
1. Field of Invention
The present invention relates to a multi-level capping layer applicable to a semiconductor process. More particularly, the present invention relates to a multi-film capping layer applicable to a self-aligned silicide (salicide) process.
2. Description of Related Art
Conventionally, a self-aligned silicide (salicide) process is usually performed to form a metal silicide layer, such as titanium silicide layer, on a source/drain region and gate polysilicon layer of a gate transistor, so as to reduce the resistance of the gate transistor. The metal silicide layer formed as such results an increased electrical conduction in the gate transistor, and thus an operation speed of a semiconductor device is improved.
However, as the size of the semiconductor device has gradually reduced according to the design rule, a sheet resistance of the metal silicide increases. This is known as a narrow line width effect. It was known that the sub-micron process of below 0.15 micron is possibly an ultimate limitation for using the titanium silicide layer. To follow a trend for an increased integration of the semiconductor device, another metal layer, such as cobalt (Co) layer which produce a lower sheet resistance regardless of size reduction of the device, is selected for forming the metal silicide layer.
FIG. 1A is a schematic, cross-sectional diagram illustrating a metal layer formed on a gate transistor without a capping layer. A semiconductor substrate 100 is provided having shallow trench isolations 102 (STI) formed therein. The STI 102 define an active region (not shown) for forming a gate transistor 104, which gate transistor 104 comprising a source/drain region 106, a gate oxide layer 108, a polysilicon layer 110, and a gate spacer 112, as shown in FIG. 1A. A metal layer, such as the Co layer 114 is formed to cover a profile including the gate transistor 104 and the surface of the substrate 100. This allows performing a self-aligned silicide (salicide) process including a rapid thermal process (RTP) which forms a cobalt silicide layer on the conductive regions of the gate transistor 104.
A chemical reaction between Co and Si occurs during the salicide process, and the reaction can simply be shown by the chemical equation below:
Co+Sixe2x86x92Co2Sixe2x86x92CoSixxe2x86x92CoSi2
Since the CoSix intermediate species is chemically very reactive in an ambient environment, a top portion of the Co layer 114 is consumed by the surrounding, while the rest of the Co layer 114 reacts with the silicon layer during the salicide process. This causes an increase in the sheet resistance (Rsh) of the cobalt silicide layer, and thus an increase in the overall resistance of the device. As a result, the device suffers a reduced operation speed.
One common solution to the problem stated above involves forming a titanium (Ti) layer 116 on the Co layer 114. FIG. 1B is a schematic, cross-sectional diagram illustrating a conventional capping layer formed on a gate transistor for a salicide process. The Ti layer 116 is formed directly on the Co layer 114 by sputtering so as to protect the Co layer 114 from being consumed by oxygen in the surroundings. Thus, this yields a more uniform Co layer 114 than the case without formation of the Ti layer 116. But, the Ti layer 116 itself produces other problems in terms of consumption of the Co layer 114. For example, a Coxe2x80x94Ti reaction occurs when the RTP is performed to consume the Co layer 114. This causes a thinning of the CoSi2 layer that results an increase in the Rsh.
FIG. 1C is a schematic, cross-sectional diagram illustrating another conventional capping layer formed on a gate transistor for a salicide process, which capping layer is made of a titanium nitride (TiN). The TiN layer 118 does not consume cobalt and thus resolves the problem of Co thinning. However, a cobalt oxide is formed when a rapid thermal process is performed, since oxygen or moisture coming from a fabrication environment will diffuse into annular nanopipes surrounding columnar TiN grains and trapped therein. The cobalt oxide formed as such is hard to be removed in a cleaning step after the salicide is formed. If the cobalt oxide is not completely removed, a portion of the cobalt oxide can remain on the gate spacer. This produces a bridge issue or filament issue at which a trace of cobalt oxide undesirably connects up the gate polysilicon layer and the source/drain region, thus leading to a short circuiting.
The invention provides a multi-film capping layer which is applicable to a self-aligned silicide (salicide) process. The multi-film capping layer is a combination of different layers, each having a unique characteristics which works together to achieve a low resistance environment in a resultant device.
As embodied and broadly described herein, the invention provides a multi-film capping layer comprising of a cobalt (Co) layer, a barrier layer, and a stuffing layer. The multi-film capping layer is formed to cover a profile including a gate transistor which is constructed on a substrate. The Co layer is formed on substrate and covers the gate transistor so as to form a salicide layer on conductive regions of the gate transistor. The barrier layer is formed on the Co layer, while the stuffing layer is formed on the barrier layer, so that the barrier layer isolates the Co layer from the stuffing layer.
Accordingly, the multi-film capping layer has several advantages over the conventional capping layer for the salicide process. First of all, the sheet resistance (Rsh) of the salicide layer is significantly reduced, since the barrier layer formed above the Co layer solves the problem of Co thinning. The addition of the stuffing layer further prevents entry of oxygen or moisture to the salicide layer, thus no Co-oxide is formed when RTP is performed. Without formation of the Co-oxide, the invention is free from the bridging issue and the filament issue.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.