1. Field of the Invention
The present invention relates to a method of manufacturing heterojunction transistors with self-aligned contacts, and more particularly to a method of manufacturing mesa-type heterojunction bipolar transistors with self-aligned emitter and base metal contacts.
2. Discussion of the Background
A conventional method for manufacturing a vertical heterojunction bipolar transistor (HBT) is shown in FIGS. 1A-1C. In FIG. 1A, a n-type AlGaAs emitter layer 4, a p-type GaAs base layer 3 and a n-type GaAs collector layer 2 are formed on a semi-insulating substrate 1. Typically, all three layers are grown in one step by a method such as organometallic vapor phase epitaxy (OMVPE) or molecular beam epitaxy (MBE). A masking material 5 is deposited on emitter layer 4 and patterned using standard photolithographic techniques. The emitter layer 4 is then etched using masking layer 5 as a mask to provide the structure shown in FIG. 1B. Masking layer 5 is then removed and electrodes 6 and 7 are deposited using standard photolithographic techniques to provide the base and emitter contacts, respectively, as shown in FIG. 1C. The resulting device does not have self-aligned base and emitter contacts, and has a further disadvantage in that the emitter layer must be etched to expose the base layer. This can be a difficult process when very thin base layers (approximately 200 angstroms) are used or if it is desired to avoid the removal of any base material in order to optimize performance.
A second HBT according to the prior art is shown in FIG. 2. In manufacturing this structure, the base layer 3 is patterned after deposition, and then emitter layer 4 is grown by an overgrowth epitaxy technique to provide a planar surface. Regions 10 and 11 are formed by implantation of impurities such as Be, to provide a base contact via base electrode 6. Emitter contact 7 and collector contact 8 complete the structure. This device requires implantation to contact the base region and the base and emitter contacts are not self-aligned.
A prior art process having self-aligned features is disclosed in U.S. Pat. No. 4,731,340 to Chang et al. A photoresist layer is deposited on an AlGaAs layer used to form the emitter region. Apertures are etched through both the photoresist layer and the AlGaAs layer to expose the base region. Base metallization is deposited over the structure to provide self-aligned base metal contacts. The photoresist layer with the metal deposited thereon is subsequently removed to expose the emitter region. The emitter contact metal is defined by another photoresist mask and a subsequent metal deposition provides the emitter metal contact. While the process of '340 provides self-aligned base contacts, two separate photomasking and metal deposition steps are required as well as a complex combination of etching through both the photoresist layer and the AlGaAs layer. Moreover, the base contacts are aligned with the photoresist, and not the emitter layer.
A further method of forming an HBT according to the prior art is disclosed by Plumpton et al in U.S. Pat. No. 4,868,633. In FIGS. 5A and 6A-6C of '633, a pedestal comprised of layers 238, 240, 242 is selectively grown on a n+/n GaAs collector 234/236 on a GaAs substrate 132 masked by WSi:Zn layer 246. The growth of the layer pedestal avoids any deposition or growth on a WSi:Zn mask in one embodiment, or polycrystalline growth or deposition on a silicon dioxide mask in the second embodiment. The layer pedestal includes both base and emitter layers (or base and collector layers in the second embodiment) and does not require any penetration of the emitter layer (either by doping or etching) to contact the base, but the subsequently formed contacts must include photolithographic tolerances and hence be non-self-aligned as shown in FIG. 5A. This structure has a characteristic of self-aligned base metal in that the extrinsic base is WSi:Zn which has a significantly lower resistance than heavily doped GaAs and is thus significantly improved. However, a significant reduction of base-collector capacitance (or emitter-base capacitance in the second embodiment), largely determined by the approximate distance between the outside edges of the base metal 254 in FIG. 5A, which is also a characteristic of self-aligned base metal, is not achieved since this distance is increased by these photolithographic tolerances. This increase in capacitance lowers the performance of the transistor and the large number of process steps increases the complexity and cost.