1. Field of the Invention
The present invention relates to a semiconductor integrated device, and more particularly, to semiconductor integrated device including a Fin Field effect transistor (hereinafter abbreviated as FinFET) device and protecting structures.
2. Description of the Prior Art
Conventional planar metal-oxide-semiconductor (MOS) transistor has difficulty when scaling down to 65 nm and below. Therefore the non-planar transistor technology such as Fin Field effect transistor (FinFET) technology that allows smaller size and higher performance is developed to replace the planar MOS transistor.
The FinFET device is conventionally formed by: First a silicon layer of a substrate is patterned to form fin structures (not shown) by a proper etching process. Then, an insulating layer surrounding lower portions of the fin structures is formed and followed by forming a gate covering a portion of the insulating layer and top portions of the fin structures. Next, dopants are introduced and annealing treatments are performed to form source/drain in the fin structures not covered by the gate. Since the manufacturing processes of the FinFET device are similar to the traditional logic device processes, it provides superior process compatibility. Furthermore, when the FinFET device is formed on the SOI substrate, traditional shallow trench isolation (STI) is no longer in need. More important, since the FinFET device increases the overlapping area between the gate and the fin structures, the channel region is more effectively controlled. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect, and the current between the source and the drain is increased.
However, the FinFET device still faces many problems. For example, because the fin structures are long and slim plate-like structures, they are susceptible to physical or electrical impacts. The long and slim fin structures are even damaged upon those impacts. Therefore, a strong and sufficient protecting structure is always in need for the FinFET device.