The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1, a partial functional block diagram of a single port of a network device is shown. A physical layer (PHY) module 102 for the port is connected to a physical media 104. For example, the network device may be an Ethernet device, the physical media 104 may include optical fiber and the PHY module 102 may be 1000BASE-X compliant. In another example, the physical media 104 may include twisted pairs of cable while the PHY module may be 1000BASE-T compliant.
The PHY module 102 includes a receiver module 110 that receives data over the physical media 104. The data received over the physical media 104 includes an embedded clock, which is recovered by a clock recovery module 112. The clock recovery module 112 provides the recovered clock (RX_CLK) to the receiver module 110. RX_CLK is also output from the PHY module 102. The receiver module 110 uses RX_CLK to latch data received over the physical media 104. The latched data is transmitted to a physical medium attachment module 114.
The physical medium attachment module 114 transmits data to and receives data from a physical coding module 116. The physical coding module 116 transmits data to and receives data from a media access control (MAC) module 118 external to the PHY module 102. The PHY module 102 includes a transmitter module 120 that transmits data over the physical media 104 from the physical medium attachment module 114. The transmitter module 120 transmits data using a transmit clock, TX_CLK, received from outside the PHY module 102.