1. Technical Field
The present invention is directed to a mask read-only-memory (mask ROM) and a method for manufacturing same. More particularly, the present invention is directed to a method for manufacturing a mask ROM using self-alignment techniques.
2. Background of the Prior Art
The structure of a conventional mask ROM is shown in FIGS. 1, 2, and 3, where FIG. 1 is a top view of the mask ROM, and FIGS. 2, 3 are cross-sectional views taken along lines II--II and III--III respectively. Mask ROM 1 includes a P type semiconductor substrate 10, a plurality of N.sup.+ bit lines 12 formed on substrate 10 by implantation, a gate oxide layer 14 formed on the substrate 10 and the bit lines 12, and a plurality of word lines 16 formed on the gate oxide layer 14.
The mask ROM is used to store predetermined data which need not be changed. Each bit of the data is stored in a corresponding memory cell of the mask ROM, each of which comprises a metal-oxide-semiconductor (MOS) transistor with its channel being located under a word line between two bit lines. Predetermined memory cells are implanted with P type impurities, such as Boron, so that their threshold voltage is raised. As a result, they become non-conducting (or inactive) at normal operating voltages. Therefore, the data bits can be programmed by the state of conduction of the MOS transistors. For example, a conductive MOS transistor lci can be used to represent "0", while a non-conductive MOS transistor, which has been made non-conducting and hence inactive by the implantation of impurities in its gate region, can be used to represent "1".
In the conventional implantation process for programming, a photoresist layer 20 is initially coated on the mask ROM 1. Openings 22 are then formed in the photoresist layer 20 over the cells to be programmed by lithography techniques. Boron ions are implanted through the opening 22 to form a P.sup.+ doped region 18 in the channel region in the MOS transistor being programmed. Therefore, when a normal voltage is placed on the word line 16, the bit lines 12 will not become conductive.
With the reduction in the scale of semiconductor integrated circuits, the width of the word lines 16 are becoming smaller. However, the amount of reduction in the width of the opening 22 is limited by factors in lithography processes used, such as difficulties in making the patterned mask 20 register correctly. As a result, misalignment of the opening 22 is a problem which has inhibited the development of smaller circuits. The misalignment problem plus lateral diffusion of the impurities induces counterdoping of the bit lines 12, which increases the bit line resistance, increases bit line capacitance, and lowers breakdown voltage. High bit line resistance and high bit line capacitance will slow down the speed of the circuit. Low breakdown voltage will result in circuit malfunctions. In the worst condition, adjacent memory cells will be mistakenly doped, which results in errors of data.