1. Technical Field
The present invention relates to an active matrix type TFT array substrate on which a thin film transistor (hereinafter referred to as TFT) is mounted to serve as a switching element, to a liquid crystal display using the TFT array substrate, and to a manufacturing method of them.
2. Background Art
Researches and developments of liquid crystal display to serve as a flat panel display in substitution for CRT have been popularly carried out. In particular, making use of its feature of small power consumption and small thickness, several liquid crystal displays have been heretofore put into practical use to serve as a display for ultra small size television or for notebook type personal computer driven by battery. As a drive method of the liquid crystal display, an active matrix type TFT array is principally used in which TFT is used as a switching element from the viewpoint of high display quality.
To achieve small power consumption in the liquid crystal display, it is effective to increase an effective display area of picture element section of the liquid crystal panel, i.e., to enhance aperture ratio of picture element. As a TFT array effective for achieving a liquid crystal panel of a high aperture ratio, for example, the Japanese Patent Publication (examined) Nos. 2521752 and 2598420 and the Japanese Laid-Open Patent Publication (unexamined) No. 163528/1992, etc. disclose a structure. In this structure, after forming a TFT comprising a scanning electrode, a signal electrode and a semiconductor layer, an interlayer insulating film composed of a transparent resin is formed to coat the TFT, and a picture element electrode is formed on the uppermost layer.
A high aperture ratio is achieved in the mentioned structure principally by following two reasons. In the first place, as the picture element electrode is formed on the interlayer insulating film of transparent resin of which surface is flattened, it is possible to prevent a deficient display (domain phenomenon) caused by irregular orientation of liquid crystal molecules occurring at the step portion of the picture element electrode of the conventional structure, whereby it becomes possible to increase an effective display area. In the second place, by forming the picture element electrode on the relatively thick interlayer insulating film of 0.3 xcexcm to 2 xcexcm in thickness, no electric short circuit takes place between the scanning line or signal line located at the lower layer of the interlayer insulating film and the picture element electrode located on the upper layer, and therefore it becomes possible to form the picture element electrode in wider area to overlap those lines.
A manufacturing process of the mentioned known TFT array of high aperture ratio is hereinafter described. First, a TFT comprising gate electrode, gate insulating film, semiconductor layer, source electrode, and drain electrode is formed on a transparent insulating substrate such as glass substrate. Then, an interlayer insulating film composed of a transparent resin of which surface is flattened so as not to produce any step caused by the TFT is formed, and a contact hole is formed at required portions. Finally, a picture element electrode composed of a transparent conductive film such as ITO is formed, thus a TFT array being completed. The picture element electrode is electrically connected to the drain electrode on the lower layer through the contact hole formed in the interlayer insulating film.
As described in the Japanese Laid-Open Patent Publications (unexamined) Nos. 127553/1997 and 152625/1997, methods for forming a contact hole in the interlayer insulating film are classified into one method in which a photosensitive transparent resin (having a photosensitivity) is used, and into another method in which non-photosensitive transparent resin (having no photosensitivity) is used. In the case of using a photosensitive transparent resin, a required contact hole is formed by a photomechanical process, without using any resist, in which exposure and development are performed using a mask pattern of the contact hole after application and baking of the resin. On the other hand, in the case of using a non-photosensitive transparent resin, after applying and baking the resin, a resist is applied. Then, after forming a contact pattern by photomechanical process, a dry etching is performed using a gas containing at least one of CF4, CF3 or SF6, and finally by removing the resist, a required contact hole is achieved.
On the mentioned TFT array substrate, terminals electrically connected to each of the date line, the source lines, etc. are arranged on the periphery of the image display section, whereby a terminal region for connecting each terminal to an external terminal is formed. FIG. 18 is a partially top view showing an active matrix type TFT array substrate of high aperture ratio according to the prior art. In the drawing, reference numeral 1 indicates a glass substrate being a transparent insulating film, numeral 2 indicates a gate line formed on the glass substrate 1, and numeral 3 indicates a source line crossing over the gate line 2. Numeral 4 is a gate terminal electrically connected to the gate line 2, and numeral 5 is a source terminal electrically connected to the source line 3. Numeral 6 is an interlayer insulating film composed of a photosensitive transparent resin formed to cover the entire gate line 2 and source line 3 and end portions of the image display section side of the gate terminal 4 and the source terminal 5. Numeral 7 is a guard resistance, numeral 8 is a contact hole of the terminal section, and numeral 9 is a contact hole of the guard resistance section. Numeral 14 is a short ring which is formed to prevent an electrostatic destruction of the TFT at the time of manufacturing thereof, and connects electrically respective terminals to each other through the guard resistance 7.
In the active matrix type substrate of above arrangement, at the end portions on the image display section side of the gate terminal 4 and the source terminal 5, a metallic wiring on the lower layer such as gate line 2, source line 3, etc. and a transparent conductive film on the upper layer are connected to each other through the contact hole 8 formed in the interlayer insulating film 6. On the other hand, since the interlayer insulating film 6 is not formed at the end portion on the guard resistance 7 side of each terminal and at the guard resistance section 7, a photomechanical process is separately required to form, for example, the contact hole 9 in the guard resistance section.
A transparent conductive film such as ITO is used as a picture element electrode and an upper conductive film of the gate terminal 4 and the source terminal 5, and this ITO is formed by forming a film on the entire substrate and patterning the film. However, there is a difference in the manner of crystal growth and in etching speed between the ITO formed on the interlayer insulating film 6 which is an organic film and the ITO formed on the glass substrate 1 or on an inorganic film. For example, etching speed of the ITO formed on the organic film is faster than that of the ITO formed on the inorganic film by 2 to 5 times. In the actual manufacturing process, from the viewpoint of patterning precision of the picture element electrode, it is necessary to set an etching time to that for the image display section in which the ITO is formed on the interlayer insulating film 6 composed of an organic film. Accordingly, in the terminal region on the guard resistance 7 side where the interlayer insulating film 6 is not formed, there arises a problem that the ITO remains not etched between the adjacent two gate terminals 4, and between two source terminals 5. The ITO left not etched brings about a deficient leak between respective terminals.
To reduce this deficient leak, it was necessary to perform a first etching on the etching condition (at an etching time) applied to the ITO formed on the organic film of faster etching speed, and perform a second etching at an etching time applied to the ITO formed on the glass substrate or on the inorganic film, while protecting the ITO on the organic film with a resist. In this manner, since it is necessary for resist pattern and etching to be performed twice, there is a disadvantage that the manufacturing process becomes unavoidably complicated.
The Japanese Laid-Open Patent Publication (unexamined) No. 90397/1997 discloses a method for etching an ITO film in which by causing an interlayer insulating film to remain between the terminals in assembly region, short circuit between the terminals can be prevented and etching process is performed once.
In the conventional liquid crystal display of above arrangement to achieve a TFT array of high aperture ratio, any interlayer insulating film is not formed in the assembly region for electrical connection between an external substrate provided on the outside of the display region of the TFT array substrate and each electrode line. Therefore, in the step of forming the picture element electrode on the interlayer insulating film, it is essential to perform twice the photomechanical process and the etching process, whereby there arise problems such that manufacturing process becomes complicated, and throughput is lowered while cost being increased.
Moreover, to leave the interlayer insulating film between the terminals, there is a further problem that irregularity due to the interlayer insulating film increases a connection resistance at the time of connecting the terminals to the external substrate.
Generally, the electrical connection between the picture element electrode of the TFT array of above structure and the drain electrode is achieved through the contact hole formed in the interlayer insulating film. In this case, to reduce the connection resistance between the picture element electrode and the drain electrode, after forming the contact hole by dry etching using CF4+O2, SF6+O2 or other fluorine gas+O2, an ashing process is performed using O2 gas to remove residue from the contact hole.
However, as the surface of the interlayer insulating film is also etched in the ashing process using the O2 gas, irregularity is formed on the surface of the interlayer insulating film. It was found that such a surface condition of the interlayer insulating film gives an influence on the etching characteristic (adaptability to etching) of the ITO film formed on the interlayer insulating film.
For example, after the etching process using CF4+O2, SE6+O2 or other fluorine gas+O2, the surface of the interlayer insulating film is smooth. When forming an ITO film on the interlayer insulating film of such a smooth condition, etching speed of the ITO film on the interlayer insulating film is almost the same as that of ITO film on the transparent insulating substrate. Thus the ITO film can be patterned by one etching process. Actually, in the case of performing an etching process at an optimum etching speed of the ITO film on the transparent insulating substrate, a side etching amount of ITO pattern on the interlayer insulating film is 1 xcexcm or less on one side, thus a desirable ITO pattern is obtained.
However, when performing the ashing process using O2 gas after the etching process using CF4+O2, SF6+O2 or other fluorine gas+O2, irregularity is produced on the surface of the interlayer insulating film. When forming an ITO film on the interlayer insulating film of such an irregular surface condition, etching speed of the ITO film on the interlayer insulating film is faster than that of the ITO film on the transparent insulating substrate by 5 times. Therefore, it is impossible to pattern the ITO film by just one etching process. Actually, in the case of performing an etching process at an optimum etching speed of the ITO film on the transparent insulating substrate, a side etching amount of ITO pattern on the interlayer insulating film is 3 xcexcm or more on one side, thus the ITO pattern is formed into an extremely tapered configuration.
As discussed above, in the case of performing the ashing process with O2 gas to reduce the connection resistance between the picture element electrode and the drain electrode, there arises a problem that it is impossible to pattern the ITO film by just one etching process. On the other hand, in the case of not performing any ashing process with O2 gas, there arises another problem that the ITO film on the interlayer insulating film and the ITO film on the transparent insulating substrate can be certainly patterned by just one etching process, but connection resistance between the picture element electrode and the drain electrode is increased.
The present invention was made to solve the above-discussed problems, and has an object of providing a TFT array substrate of high aperture ratio capable of being manufactured in smaller number of processes than that in the prior arts and capable of preventing a leak between terminals due to residue produced by etching ITO. A manufacturing method of the TFT array substrate and a liquid crystal display using the TFT array substrate are also provided.
Another object of the invention is to provide a manufacturing method of a TFT array substrate of high aperture ratio in smaller number of processes than that in the prior arts, without any photomechanical process conventionally required at the time of forming a contact hole at the opposite end of the image display section side of each terminal and a contact hole of guard resistance section, and in which a contact hole of the drain electrode portion in the image display section and a contact hole of each terminal section and guard resistance section can be simultaneously formed on an interlayer insulating film, by providing the interlayer insulating film not only on the image display section of the substrate but also on the peripheral edge section of the substrate including the guard resistance and a short ring for preventing the electrostatic destruction of the TFT at the time of manufacture, at least from opposite end of the image display section side of each terminal in terminal region.
A further object of the invention is to provide a manufacturing method in which pattern formation of a transparent conductive film can be performed by just one resist pattern formation and etching, without leaving any transparent conductive film between terminals, in spite of performing an etching on the etching conditions applied to the transparent conductive film formed on the interlayer insulating film, by providing an interlayer insulating film between terminals in terminal region so that width of the interlayer insulating film is smaller than the distance between the terminals, and in which it is possible to prevent a deficient leak between terminals due to residue produced by etching the transparent conductive film.
A yet further object of the invention is to provide a manufacturing method in which coverage of the transparent conduct film becomes insufficient, due to existence of a sharp step of an insulating film of which section is not tapered between one terminal and another, and which can prevent deficient leak between the terminals, by providing the insulating film wider and thicker than the terminals on a lower layer of each terminal in terminal region.
A still further object of the invention is to provide a manufacturing method of a liquid crystal display in which connection resistance between picture element electrode and drain electrode can be lowered and stabilized, and at the time of forming the picture element electrode, an ITO film can be patterned by just one etching process without occurring any short circuit between the terminals in assembly region.
A further object of the invention is to provide a manufacturing method of a liquid crystal display of high performance and high aperture ratio at a reasonable cost, in which, for manufacturing the liquid crystal display achieving an improvement in aperture ratio by the steps of forming an interlayer insulating film composed of a transparent resin on electrode lines and on a TFT, flattening a surface of the interlayer insulating resin, and forming a picture element electrode on the uppermost layer, any residue on the bottom portion of a contact hole is exactly removed by optimizing dry etching condition for forming the contact hole to which the picture element electrode and a drain electrode formed on the interlayer insulating film are electrically connected, connection resistance between the picture element electrode and the drain electrode can be reduced by achieving a condition that there is no irregularity on the surface of the interlayer insulating film at the time of forming an ITO film forming the picture element electrode after forming the contact hole, and the ITO film on the interlayer insulating film and the ITO film on the transparent insulating substrate exposed between the terminals in the assembly region can be patterned into a desirable configuration without short circuit between the terminals in one etching process.
A TFT array substrate according to the present invention comprises: a plurality of gate lines provided with a gate electrode and formed on a transparent insulating substrate; a plurality of source lines provided with a source electrode and crossing over the gate lines; a semiconductor layer provided on the gate electrode through a gate insulating film; a thin film transistor comprised of the source electrode and the drain electrode connected to the semiconductor layer; an interlayer insulating film formed on the substrate, and of which surface is flattened so as not to produce any step due to the thin film transistor; a picture element electrode composed of a transparent conductive film provided in a wide spread manner on the interlayer insulating film and connected to the drain electrode through a contact hole formed on the interlayer insulating film; and a terminal region in which terminals electrically connected to each of the gate lines and the source lines are arranged on the periphery of an image display section of the substrate to connect each terminal to an external terminal; wherein the interlayer insulating film is provided not only on the image display section side but also on a peripheral edge portion including at least an opposite end of the image display section side of each terminal in the terminal region.
It is preferable that the interlayer insulating film is provided between respective terminals in the terminal region so that width of the interlayer insulating film is smaller than a distance between the terminals.
It is preferable that the interlayer insulating film which is thick and of which section is not tapered is provided between respective terminals in the terminal region so that width of the interlayer insulating film is smaller than the distance between the terminals.
It is preferable that an insulating film which is thick and of which section is not tapered is provided on a lower layer of each terminal in the terminal region so that width of the insulating film is larger than that of the terminals.
It is preferable that the interlayer insulating film is provided on the entire surface of the terminal region.
It is preferable that the interlayer insulating film is composed of a photosensitive resin.
A liquid crystal display according to the invention comprises a liquid crystal arranged between any of the mentioned TFT array substrates and an opposite electrode substrate having a transparent electrode, a color filter, etc.
A manufacturing method of a TFT array substrate according to the invention comprises: a first step of forming lines such as gate lines, source lines and a thin film transistor on a transparent insulating substrate; a second step of forming an interlayer insulating film not only on an image display section of the substrate but also on a peripheral edge section of the substrate, including a guard resistance and a short ring for preventing electrostatic destruction of the thin film transistor at the time of manufacture, at least from opposite end of the image display section side of terminals in a terminal region; a third step of forming contact holes respectively for a drain electrode section, a terminal section and a guard resistance section on the interlayer insulating film; and a fourth step of forming a transparent conductive film such as ITO on the substrate, and forming a picture element electrode, each terminal and the guard resistance by resist patterning and etching.
It is preferable that in the second step, an organic film is used as the interlayer insulating film.
It is preferable that in the second step, a photosensitive resin is used as the interlayer insulating film.
It is preferable that in the fourth step, a resist pattern for each terminal is formed wider than a desired pattern on the interlayer insulating film, and an etching is performed on the etching condition applied to the transparent conductive film formed on a transparent insulating substrate or on an inorganic film.
A manufacturing method of a liquid crystal display according to the invention in which two transparent insulating substrates, at least on either of which an electrode is formed, are adhered facing to each other and a liquid crystal is held between the two transparent insulating substrates comprises: a step of forming a scanning electrode, a scanning electrode line and a scanning electrode line terminal on either of the two transparent insulating substrates; a step of forming an insulating film on the scanning electrode, scanning electrode line and scanning electrode line terminal; a step of forming a semiconductor layer on the scanning electrode through the insulating film; a step of forming a first electrode, a first electrode line and a first electrode line terminal and a second electrode on the semiconductor layer; a step of forming a passivation film on the first electrode, first electrode line, first electrode line terminal and second electrode; a step of forming a contact hole on the second electrode and forming an interlayer insulating film having an aperture in an assembly region in which the scanning electrode line terminal and the first electrode line terminal are formed, by applying a transparent resin having a photosensitivity to the passivation film and by exposure and development thereof; a step of etching the passivation film and the insulating film exposed through the contact hole and the aperture by dry etching using the interlayer insulating film as a mask; and a step of forming a transparent conductive film on the interlayer insulating film, in the contact hole, on the transparent insulating substrates exposed through the aperture, on the scanning electrode line terminal and on the first electrode line terminal, and forming a picture element electrode electrically connected to the second electrode through the contact hole and forming a transparent conductive film pattern on the scanning electrode line terminal and on the first electrode line terminal by patterning in just one etching process; in which surface of the interlayer insulating film after the etching process by dry etching is smooth.
Another manufacturing method of a liquid crystal display according to the invention in which two transparent insulating substrates, at least on either of which an electrode is formed, are adhered facing to each other and a liquid crystal is held between the two transparent insulating substrates comprises: a step of forming a scanning electrode, a scanning electrode line and a scanning electrode line terminal on either of the two transparent insulating substrates; a step of forming an insulating film on the scanning electrode, scanning electrode line and scanning electrode line terminal; a step of forming a semiconductor layer on the scanning electrode through the insulating film; a step of removing the insulating film in an assembly region in which the scanning electrode line terminal and a first electrode line terminal are formed; a step of forming the first electrode, a first electrode line and a first electrode line terminal and a second electrode on the semiconductor layer; a step of forming a passivation film on the first electrode, on the first electrode line, first electrode line terminal and second electrode; a step of forming a contact hole on the second electrode and forming an interlayer insulating film having an aperture in an assembly region in which the scanning electrode line terminal and the first electrode line terminal are formed, by applying a transparent resin having a photosensitivity to the passivation film and by exposure and development thereof; a step of etching the passivation film exposed through the contact hole and the aperture by dry etching using the interlayer insulating film as a mask; and a step of forming a transparent conductive film on the interlayer insulating film, in the contact hole, on the transparent insulating substrates exposed through the aperture, on the scanning electrode line terminal and on the first electrode line terminal, and forming a picture element electrode electrically connected to the second electrode through the contact hole and forming a transparent conductive film pattern on the scanning electrode line terminal and on the first electrode line terminal by patterning in just one etching process; in which surface of the interlayer insulating film after the etching process by dry etching is smooth.
A further manufacturing method of a liquid crystal display according to the invention in which two transparent insulating substrates, at least on either of which an electrode is formed, are adhered facing to each other and a liquid crystal is held between the two transparent insulating substrates comprises: a step of forming a scanning electrode, a scanning electrode line and a scanning electrode line terminal on either of the two transparent insulating substrates; a step of forming an insulating film on the scanning electrode, scanning electrode line and scanning electrode line terminal; a step of forming a semiconductor layer on the scanning electrode through the insulating film; a step of forming a first electrode, a first electrode line and a first electrode line terminal and a second electrode on the semiconductor layer; a step of forming a passivation film on the first electrode, first electrode line, first electrode line terminal and second electrode; a step of forming a contact hole on the second electrode and forming an interlayer insulating film having an aperture in an assembly region in which the scanning electrode line terminal and the first electrode line terminal are formed, by applying a transparent resin having a photosensitivity to the passivation film and by exposure and development thereof; a step of forming a resist by applying a photo-resist and patterning the photo-resist into the same configuration as the interlayer insulating film; a step of removing the resist after etching the passivation film and the insulating film exposed through the contact hole and the aperture by dry etching using the resist as a mask; and a step of forming a transparent conductive film on the interlayer insulating film, in the contact hole, on the transparent insulating substrates exposed through the aperture, on the scanning electrode line terminal and on the first electrode line terminal, and forming a picture element electrode electrically connected to the second electrode through the contact hole and a transparent conductive film pattern on the scanning electrode line terminal and on the first electrode line terminal by patterning in just one etching process.
A still further manufacturing method of a liquid crystal display according to the invention in which two transparent insulating substrates, at least on either of which an electrode is formed, are adhered facing to each other and a liquid crystal is held between the two transparent insulating substrates comprises: a step of forming a scanning electrode, a scanning electrode line and a scanning electrode line terminal on either of the two transparent insulating substrates; a step of forming an insulating film on the scanning electrode, scanning electrode line and scanning electrode line terminal; a step of forming a semiconductor layer on the scanning electrode through the insulating film; a step of forming a first electrode, a first electrode line and a first electrode line terminal and a second electrode on the semiconductor layer; a step of forming a passivation film on the first electrode, first electrode line, first electrode line terminal and second electrode; a step of forming an interlayer insulating film by applying a transparent resin having no photosensitivity to the passivation film; a step of forming a resist, and removing the resist after forming a contact hole on the second electrode and an aperture in an assembly region in which the scanning electrode line terminal and the first electrode line terminal are formed, by etching the interlayer insulating film, passivation film and insulating film by dry etching; and a step of forming a transparent conductive film on the interlayer insulating film, in the contact hole, on the transparent insulating substrates exposed through the aperture, on the scanning electrode line terminal and on the first electrode line terminal, and forming a picture element electrode electrically connected to the second electrode through the contact hole and forming a transparent conductive film pattern on the scanning electrode line terminal and on the first electrode line terminal by patterning in just one etching process.
It is preferable that the insulating film in the assembly region in which the scanning electrode line terminal and the first electrode line terminal are formed is removed after forming the semiconductor layer and before forming the first electrode, the first electrode line, the first electrode line terminals and the second electrode.
It is preferable that in the etching process by dry etching using the inter layer insulating film as a mask, an ashing process using O2 gas and a second etching process using CF4+O2, SF6+O2 or other fluorine gas+O2 gas are performed, after completing a first etching process using CF4+O2, SF6+O2 or other fluorine gas+O2 gas.
It is preferable that in the second etching process using CF4+O2, SF6+O2 or other fluorine gas+O2 gas, the etching process is performed in a shorter time or by setting a flow ratio of O2 gas to be higher or by setting a power to be smaller than that in the first etching process using CF4+O2, SF6+O2 or other fluorine gas+O2 gas, or by combining at least two of these process conditions.
It is preferable that in etching process conditions by dry etching after forming the resist on the interlayer insulating film, after the etching process using CF4+O2, SF6+O2 or other fluorine gas+O2 gas, an ashing process using O2 is performed.
It is preferable that in the etching process using the interlayer insulating film or the resist as a mask, the second etching process using CF4+O2, SF6+O2 or other fluorine gas+O2 gas is performed by setting a flow ratio of O2 gas to be higher than that in the first etching process, after completing the first etching process using CF4+O2, SF6+O2 or other fluorine gas +O2 gas.