A typical data storage system stores and retrieves data for external hosts. FIG. 1 shows a high-level block diagram of a conventional data storage system 20. The data storage system 20 includes front-end circuitry 22, a cache 24, back-end circuitry 26 and a set of disk drives 28-A, 28-B (collectively, disk drives 28). The cache 24 operates as a buffer for data exchanged between external hosts 30 and the disk drives 28. The front-end circuitry 22 operates as an interface between the hosts 30 and the cache 24. Similarly, the back-end circuitry 26 operates as an interface between the cache 24 and the disk drives 28.
FIG. 1 further shows a particular implementation 32 of the data storage system 20. In the implementation 32, the front-end circuitry 22 includes multiple front-end circuit boards 34. Each front-end circuit board 34 includes a pair of front-end directors 36-A, 36-B. Each front-end director 36 (e.g., the front-end director 36-A of the front-end circuit board 34-1) is interconnected between a particular host 30 (e.g., the host 30-A) and a set of M buses 38 that lead to the cache 24 (M being a positive integer), and operates as an interface between that particular host 30 and the cache 24.
Similarly, the back-end circuitry 26 includes multiple back-end circuit boards 40. Each back-end circuit board 40 includes a pair of back-end directors 42-A, 42-B. Each back-end director 42 is interconnected between a particular disk drive 28 and the M buses 38 leading to the cache 24, and operates as an interface between that disk drive 28 and the cache 24.
Each disk drive 28 has multiple connections 44, 46 to the cache 24. For example, the disk drive 28-A has a first connection 44-A that leads to the cache 24 through the back-end director 42-A of the back-end circuit board 40-1, and a second connection 46-A that leads to the cache 24 through another back-end director of another back-end circuit board 40 (e.g., a back-end director of the back-end circuit board 40-2). An explanation of how the implementation 32 of the data storage system 20 retrieves a block of data (e.g., 512 bytes) for a host 30 will now be provided.
Suppose that the host 30-A submits, to the front-end director 36-A of the front-end circuit board 34-1, a request for a block of data stored on the disk drive 28-A. In response to the request, the front-end director 36-A looks for the block in the cache 24. If the front-end director 36-A finds the block in the cache 24 (i.e., a cache hit), the front-end director 36-A simply transfers a copy of the block from the cache 24 through one of the M buses 38 to the host 30-A. This operation is called a cached read since the front-end director 36-A was able to read a cached block (a block previously existing in the cache 24) on its first attempt.
However, if the front-end director 36-A does not find the block in the cache 24 (i.e., a cache miss), the front-end director 36-A performs a non-cached read operation. Here, the front-end director 36-A places a read message in the cache 24 through one of the M buses 38. The read message directs the back-end director 42-A of the back-end circuit board 40-1 to copy the block from the disk drive 28-A to the cache 24. The back-end director 42-A, which periodically polls the cache 24 for such messages, eventually detects the read message from the front-end director 36-A. In response to such detection, the back-end director 42-A transfers a copy of the block from the disk drive 28-A through one of the M buses 38 to the cache 24. The back-end director 42-A then places a notification message into the cache 24 through one of the M buses 38. The notification message notifies the front-end director 36-A that the requested block now resides in the cache 24. The front-end director 36-A, which periodically polls the cache 24 for such notification messages and for the requested block, eventually detects the notification message or the presence of the requested block in the cache 24. In response to such detection, the front-end director 36-A transfers the copy of the block from the cache 24 through one of the buses 38 to the host 30-A.
As described above, the non-cached read operation requires more time to fulfill than the above-described cached read operation. In particular, the extra step of putting the data block into the cache 24, and then reading the data block from the cache 24 takes unnecessary time and adds to the latency of the overall operation, thus reducing performance.
It should be understood that the implementation 32 of the data storage system 20 can handle a subsequent request from a host 30 for the block of data by simply transferring the copy of the block residing in the cache 24 to the host 30 (i.e., a cache hit) without having to re-read the block from a disk drive 28. Such operation significantly reduces the block retrieval latency particularly since retrieval time for a block of data from a disk drive is typically an order of magnitude higher than retrieval time for a block of data from cache memory.
It should be further understood that the redundant features of the data storage system implementation 32 (e.g., the redundant front-end directors 36, the redundant back-end directors 42, the M buses 38, the multiple disk drive connections 44, 46, etc.) provide fault-tolerant and load balancing capabilities for the data storage system implementation 32. For example, if the back-end director 42-A fails and is thus unable to retrieve a data block from the disk drive 28-A in response to a request from the host 30-A, another back-end director 42 (e.g., a back-end director 42 residing on the circuit board 40-2) can respond to the request by retrieving the requested block through a redundant path to the disk drive 28-A (see the connection 46-A of FIG. 1).
Unfortunately, there are deficiencies to the above-described conventional implementation 32 of the data storage system 20 of FIG. 1. For example, for transactions requiring many non-cached read operations such as media streaming, there is a heavy amount of traffic through the connection infrastructure between the front-end directors 36 and the back-end directors 38 (i.e., the cache 24 and the M buses 38). For such non-cached read operations, the exchanging of data blocks, read messages and notification messages, as well as the polling for such messages tends to clog this connection infrastructure.
Additionally, there are delays associated with using the M buses 38. In particular, each director 36, 42 must arbitrate for use of the buses 38. A bus controller (not shown) typically grants the directors 36, 42 access to the buses 38 in accordance with a fair arbitration scheme (e.g., a round-robin arbitration) to guarantee that none of the directors 36, 42 becomes starved for bus access. Accordingly, some directors 36, 42 may have to wait until it is their turn to use the buses 38, and such waiting is a source of latency. Particularly, in times of heavy traffic, some directors 36, 42 may have to wait extended amounts of time before obtaining access to the cache 24 through one of the buses 38 thus significantly increasing data retrieval latencies.
In contrast to the above-described conventional data storage system implementation 32, the invention is directed to techniques for accessing data within a data storage system having a circuit board that includes both a front-end circuit for interfacing with a host and a back-end circuit for interfacing with a storage device. To move data between the host and the storage device, an exchange of data between the front-end circuit and the back-end circuit can occur within the circuit board thus circumventing the cache of the data storage system. Such operation not only reduces traffic through the cache, but also shortens data transfer latency.
In one arrangement, a data storage system includes a cache, a first front-end circuit that operates as an interface between the cache and a first host, a second front-end circuit that operates as an interface between the cache and a second host, a first storage device (e.g., a disk drive, tape drive, CDROM drive, etc.), a second storage device, a first back-end circuit that operates as an interface between the cache and the first storage device, and a second back-end circuit that operates as an interface between the cache and the second storage device. The first front-end circuit and the first back-end circuit reside on a first circuit board. Similarly, the second front-end circuit and the second back-end circuit reside on a second circuit board. Accordingly, data transfer between the first host and the first storage device can occur through the first front-end circuit and the first back-end circuit (both of which are on the first circuit board) and circumvent the cache. Likewise, data transfer between the second host and the second storage device can occur through the second front-end circuit and the second back-end circuit (both of which are on the second circuit board) and circumvent the cache. Such data transfers decrease traffic through the cache and reduce data retrieval latencies for non-cached read operations as well as lighten the load on the structure to increase performance of operations not able to use this mechanism.
In one arrangement, the data storage system further includes a buffer circuit that (i) is interconnected between the first front-end circuit and the first back-end circuit and (ii) resides on the first circuit board. The buffer circuit provides a direct data pathway between the first front-end circuit and the first back-end circuit that circumvents the cache. The buffer circuit is capable of retaining copies of data elements (e.g., blocks of data) transferred from the first storage device to the first host for possible subsequent access by the first host or another host. Accordingly, a host (e.g., the first host) can acquire the data element from the buffer circuit without requiring first back-end circuit to re-transfer another copy of the data element from the first storage device.
In one arrangement, the buffer circuit includes multi-ported random access memory (RAM). The multi-ported RAM includes memory locations, a first port coupled to the first front-end circuit, and a second port coupled to the first back-end circuit. The first port enables the first front-end circuit to access the memory locations. The second port enables the first back-end circuit to access the memory locations. The multiple ports prevent accesses of the first front-end circuit and the first back-end circuit from interfering with each other through a single port.
In one arrangement, data can travel to multiple locations within the data storage system at substantially the same time. For example, the first back-end circuit can simultaneously place data from a read operation (e.g., a bicast disk read) in the cache (through a bypass) and the buffer circuit. As another example, the first back-end circuit can provide data directly to the cache and the first front-end circuit at substantially the same time (another bicast operation).
In another arrangement, the data storage system operates in a traditional manner in some situations. That is, the cache provides a data pathway between the first front-end circuit and the second back-end circuit, and the second storage device stores another data element. Here, the first front-end circuit and the second back-end circuit are configured to respond to a request, from the first host, for the other data element resulting in a cache miss by transferring a copy of the other data element from the second storage device to the first host through the data pathway between the first front-end circuit and the second back-end circuit. Accordingly, in situations that require use of a front-end circuit and a back-end circuit on different circuit boards, the data element can be transferred through the cache in a traditional manner.
In one arrangement, the multi-ported RAM further includes a third port coupled to the cache. The third port enables circuitry other than the first front-end circuit and the first back-end circuit to move data elements between the memory locations and the cache. The availability of the third port enables data exchanges between the buffer circuit and the cache, and prevents such data exchanges from interfering with accesses by the first front-end circuit and the first back-end circuit through a single port.
The features of the invention, as described above, may be employed in data storage systems, devices and methods, as well as in other computer-related mechanisms such as those manufactured by EMC Corporation of Hopkinton, Mass.