The present invention relates to devices used on reconfigurable chips for loading data or configuration. Reconfigurable chips typically load data and configuration from an off-chip memory. Especially when reconfigurable chips are used for reconfigurable computing, the loading of the data and configuration from the off-chip memory can take a significant amount of time, slowing the operation of the reconfigurable chip.
It is desired to have an improved loading plane for use on a reconfigurable chip.
One embodiment of the present invention comprises a loading plane which includes a number of background bit storage units associated with foreground bit storage units. At least one of the background units receives a data bit from off-chip memory. This unit can selectively supply the background data bit to a foreground unit. Additionally, at least one additional background unit receives a data bit from an on-chip source, the additional background unit also adapted to selectively supply the background data bit to the foreground unit.
In this way, both data from off-chip and data derived on-chip can be provided to the foreground unit. In a preferred embodiment, the above units are combined into a register block. This register block is preferably within a data path unit. By having background units, the system can operate on the current data loaded in the foreground, while still loading data for the next operation into the background. By having an additional background unit able to load from on-chip, additional flexibility is gained in the operation of the reconfigurable chip.