Most devices today, which may be integrated circuit (IC) devices or embedded core devices within an IC, include an IEEE standard 1149.1 (JTAG) Test Access Port (TAP) architecture to access target circuits within the devices. The TAP includes an interface which comprises a test data input (TDI) signal, a test clock (TCK) signal, a test mode select (TMS) signal, a test data output (TDO) signal and an optional test reset signal. Devices also use other IEEE standards that are based on the IEEE 1149.1 TAP such as but not limited to IEEE 1149.4, IEEE 1149.6, IEEE 1149.7, IEEE P1149.8.1, IEEE 1532, and IEEE P1687. The TAP is used to control various activities in the device such as but not limited too, device to device boundary scan testing, device testing, device debugging, and device programming.
FIG. 1 illustrates an example implementation of a TAP within a device 102. The TAP includes a TAP state machine (TSM) 104, an instruction register 106, two or more data registers 108, a data register control (DRC) router, multiplexers 112 and 114, a falling TCK edge operated TDO register (R) 116, and TDO buffer 118. The TSM operates in response to the TCK and TMS input signals to; (1) place the TAP is a Test Logic Reset state, (2) place the TAP in a Run Test/Idle state, (3) perform a scan operation to the instruction register from TDI to TDO, or (4) to perform scan operation to a selected data register from TDI to TDO.
During instruction scan operations, the TSM outputs a bus of instruction register control (IRC) signals to the instruction register, a select (SEL) signal to multiplexer 114, and an enable (ENA) signal to TDO buffer 118. In response to an instruction scan operation, the instruction register inputs data from TDI and outputs data to TDO via multiplexer 114, R 116, and TDO buffer 118.
During data scan operations, the TSM outputs a bus of data register control (DRC) signals 120 to a selected data register via DRC router 110, the SEL signal to multiplexer 114, the ENA signal to TDO buffer 118. In response to a data scan operation, the selected data register inputs data from TDI and outputs data to TDO via multiplexer 112 and multiplexer 114, R 116, and TDO buffer 118.
In the FIG. 1 example, a data register is selected for access by data register enable (DRE) signals output from the instruction register. The DRE signals are set by the instruction loaded into the instruction register. The DRE signals are input to the DRC router to couple the DRC signal outputs 120 from the TSM to the DRC signal inputs 122,124 of the selected data register. The DRE signals also control multiplexer 112 to couple the output of the selected data register to the TDO signal via multiplexer 114, R 116 and TDO buffer 118.
FIG. 2 illustrates the state diagram of the TSM 104 which is well known in the art. The state diagram has a Test Logic Reset state 202, Run Test/Idle state 204, data register scanning states 206 (Capture-DR, Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR) and instruction register scanning states 208 (Capture-IR, Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and Update-IR). State transitions occur in response to the TMS signal on the rising edge of the TCK signal. The data scanning states are entered via the Select-DR state 210 and the instruction scanning states are entered via the Select-IR state 212.
In the Capture-DR state the selected data register captures data from its parallel inputs. In the Shift-DR state the selected data register shifts data from TDI to TDO. In the Pause-DR state the selected data register pauses shifting. In the Update-DR state the selected data register updates data to its parallel outputs.
In the Capture-IR state the instruction register captures data from its parallel inputs. In the Shift-IR state the instruction register shifts data from TDI to TDO. In the Pause-IR state the instruction register pauses shifting. In the Update-IR state the instruction register updates data to its parallel outputs.
FIG. 3 illustrates two known types of DRC signal output groups 302, 304 of the TSM DRC signal bus 120. DRC output group 302, comprising ClockDR, ShiftDR and UpdateDR signals, is used to control scan access to asynchronous data registers 108. In this disclosure asynchronous data registers are registers comprising scan cells that do not have the ability to hold their present state when no capture, shift or update operations are taking place. Thus they must be timed by a gated clock input (i.e. ClockDR). The ClockDR signal is a gated TCK clock signal that is active in the Capture-DR and Shift-DR TSM states of FIG. 2. The ShiftDR signal controls the selected data register to capture data in the Capture-DR state and shift data in the Shift-DR state. The UpdateDR signal is a gated clock output that is active in the Update-DR state to update data from the parallel outputs of the selected data register.
DRC output group 304, comprising a Capture signal, a Shift signal and an Update signal, is used to control scan access to synchronous data registers 108. In this disclosure synchronous data registers are registers comprising scan cells that do have the ability to hold their present state when no capture, shift or update operations are taking place. Thus they can be timed by a free running clock (i.e. TCK). The Capture signal is set when the TSM is in the Capture-DR state of FIG. 2 to cause the data register to capture data from its parallel inputs on the rising edge of the free running TCK signal. The Shift signal is set when the TSM is in the Shift-DR state of FIG. 2 to cause the data register to shift data on the rising edge of the free running TCK signal. The Update signal is set when the TSM is in the Update-DR state of FIG. 2 to cause the data register to update data to its parallel outputs on the falling edge of the free running TCK signal.
While not shown, the IRC signals from TSM 104 may use similar groups of signals for performing capture, shift and update operations on asynchronous or synchronous types of instruction registers 106.
FIG. 4 illustrates the DRC router 110 in more detail. In this example, the DRC router 110 is used to couple the DRC bus signals 120 of TSM 104 to four types of data registers, (1) an asynchronous capture, shift and update (CSU) data register 410, (2) an asynchronous capture and shift (CS) data register 412, (3) a synchronous capture, shift and update (CSU) data register 414 and (4) a synchronous capture and shift (CS) data register 416. As will be shown in example FIGS. 9 and 10, the CSU data registers 410 and 414 include an update register that is coupled to the parallel outputs of the shift register of the data register. As will be shown in example FIGS. 13 and 14, the CS data registers 412 and 416 only include a shift register with parallel outputs.
When scan access to data register 410 is required, a first instruction is scanned into the instruction register 106 to output DRE control signals that enable routing circuit 402 to; (1) couple the ClockDR signal of bus 120 to the ClockDR signal input of data register 410, (2) couple the ShiftDR signal of bus 120 to the ShiftDR signal input of data register 410, (3) couple the UpdateDR signal of bus 120 to the UpdateDR signal input of data register 410
When scan access to data register 412 is required, a second instruction is scanned into the instruction register 106 to output DRE control signals that enable routing circuit 404 to; (1) couple the ClockDR signal of bus 120 to the ClockDR signal input of data register 412 and (2) couple the ShiftDR signal of bus 120 to the ShiftDR signal input of data register 412.
When scan access to data register 414 is required, a third instruction is scanned into the instruction register 106 to output DRE control signals that enable routing circuit 406 to; (1) couple the Capture signal of bus 120 to the Capture signal input of data register 414, (2) couple the Shift signal of bus 120 to the Shift signal input of data register 414, (3) couple the Update signal of bus 120 to the Update signal input of data register 414. Data register 414 is clocked by the free running TCK signal.
When scan access to data register 416 is required, a fourth instruction is scanned into the instruction register 106 to output DRE control signals that enable routing circuit 408 to; (1) couple the Capture signal of bus 120 to the Capture signal input of data register 416 and (2) couple the Shift signal of bus 120 to the Shift signal input of data register 416. Data register 416 is clocked by the free running TCK signal.
Routing circuits 402-408 that are not enabled by the current instruction in the instruction register will decouple their outputs from the DRC bus signals 120 and set their outputs to static desired states.
FIG. 5 illustrates a simplified view of a TAP within a device 502 that has a data register 108 that has been enabled for scan access by the DRE signals from instruction register (IR) 106. The simplified view of FIG. 5 and other Figures to follow does not show multiplexers 112 and 114, R 116, or TDO buffer 118 between the data register output and TDO, but they are assumed to exist. The data register 108 can be any type of data register or similar type circuit including but not limited too, an asynchronous CSU data register 410, an asynchronous CS data register, a synchronous CSU data register 414, a synchronous CS data register 416 or a test compression architecture having a compressed data input coupled to TDI and a compressed data output coupled to TDO.
FIG. 6 illustrates the scan access timing of accessing a CSU type data register 108. As seen, the scan access timing is controlled by the TSM 104 repeatedly transitioning through the Select-DR, Capture-DR, Shift-DR, Exit1-DR and Update-DR states of FIG. 2. The data register performs a data Capture operation (OP) on the rising edge of the TCK when the TSM is in the Capture-DR state. The data register performs a data Shift operation (OP) on the rising edge of the TCK when the TSM is in the Shift-DR state. The data register performs a data Update operation (OP) on the falling edge of the TCK when the TSM is in the Update-DR state.
FIG. 7 illustrates the scan access timing of accessing a CS type data register 108. As seen, the scan access timing is controlled by the TSM 104 repeatedly transitioning through the Select-DR, Capture-DR, Shift-DR, Exit1-DR and Update-DR states of FIG. 2. The data register performs a data Capture operation on the rising edge of the TCK when the TSM is in the Capture-DR state. The data register performs a data Shift operation on the rising edge of the TCK when the TSM is in the Shift-DR state. The data register does not perform a data Update operation on the falling edge of the TCK when the TSM is in the Update-DR state since it has no update register.
FIG. 8A is provided to illustrate that the data register 108 of FIG. 5 could be a test data register 802 coupled to circuitry to be tested, such as but not limited too combination logic and memories.
FIG. 8B is provided to illustrate that the data register 108 of FIG. 5 could be a debug data register 804 coupled to circuitry to be debugged, such as but not limited too microcontrollers and DSPs.
FIG. 8C is provided to illustrate that the data register 108 of FIG. 5 could be a programming data register 806 coupled to circuitry to be programmed, such as but not limited too FPGAs, CPLDs and memories (Flash/PROM) as described in IEEE standard 1532.
FIG. 8D is provided to illustrate that the data register 108 of FIG. 5 could be a Instrumentation data register 808 coupled to instrumentation circuitry embedded within a device, such as but not limited too instrumentation circuitry described in IEEE standard P1687.
FIG. 8E is provided to illustrate that the data register 108 of FIG. 5 could be an IC boundary register 810 coupled to the IC interconnects for the purpose of testing the IC interconnects as described in IEEE standards, 1149.1, 1149.4, 1149.6, and P1149.8.1 and shown in FIG. 8I.
FIG. 8F is provided to illustrate that the data register 108 of FIG. 5 could be an IC boundary register 812 of an IC coupled to the IC system logic for the purpose of testing the system logic as described in IEEE standard 1149.1 and shown in FIG. 8J.
FIG. 8G is provided to illustrate that the data register 108 of FIG. 5 could be a core wrapper boundary register 814 coupled to the core interconnects for the purpose of testing the core interconnects as described in IEEE standard 1500 and shown in FIG. 8I.
FIG. 8H is provided to illustrate that the data register 108 of FIG. 5 could be a core wrapper boundary register 816 coupled to the core system logic for the purpose of testing the system logic as described in IEEE standard 1500 and shown in FIG. 8J.
FIG. 8I illustrates how the IC boundary register 810 could be used to test the interconnects between two ICs according to IEEE 1149.1 and how the core wrapper boundary register 814 could be used to test the interconnects between two cores in an IC according to IEEE 1500.
FIG. 8J illustrates how the IC boundary registers 814 could be used to test the system logic of an IC according to IEEE 1149.1 and how the core wrapper boundary register 816 could be used to test the system logic of a core in an IC according to IEEE 1500.
FIG. 9 illustrates an example asynchronous CSU data register 902 coupled to TSM 104 via a routing circuit 906 located within DRC router 110 of FIG. 4. Data register 902 could be, but is not limited to being, the IEEE 1149.1 IC boundary register of FIGS. 8E and 8F or the IEEE 1500 core wrapper boundary register of FIG. 8G or 8H. When the routing circuit 906 is enabled by DRE inputs from the instruction register 106, the ClockDR, ShiftDR and UpdateDR signals from the TSM pass through the routing circuit to operate CSU scan cells 904 within data register 902.
FIG. 10 illustrates the CSU scan cell 904 which comprises a multiplexer 1002, a shift register FF 1004, an update register FF 1006 and optionally a multiplexer 1008. When the TSM is in the Capture-DR state of FIG. 2, multiplexer 1002 will be set by the ShiftDR signal to couple the scan cell's data input (DI) to FF 1004 to allow the DI to be captured into FF 1004 in response to a clock input on ClockDR. When the TSM is in the Shift-DR state of FIG. 2, multiplexer 1002 will be set by the ShiftDR signal to couple the TDI signal to FF 1004 to allow TDI data to be shifted into FF 1004 and TDO data to be shifted out of FF 1004 in response to clock inputs on ClockDR. When the TSM is in the Update-DR state of FIG. 2, FF 1006 will update (load) with the data output from FF 1004 in response to a clock input on UpdateDR and outputs the data on the scan cell's data output (DO). If the scan cell 904 does not include multiplexer 1008 the DO from update FF 1006 will pass directly to DO 1010. If the scan cell 904 includes multiplexer 1008 the DO from update FF 1006 will pass to DO 1012 via multiplexer 1008. When scan cell 904 includes the multiplexer 1008 it operates as an IEEE 1149.1 boundary scan cell which allows DO 1012 to be selectively driven by DI or by the output of update FF 1006 in response to a Mode signal input from the DRE bus. Including multiplexer 1008 supports boundary scan testing on the interconnects between devices as shown in FIG. 8I
FIG. 11 illustrates routing circuit 906 which comprises a gating circuit 1102, a gating circuitry 1104, a gating circuitry 1106 and optionally a clock multiplexer 1108 as shown in FIG. 12. When routing circuit 906 is enable by DRE signal inputs, the ClockDR signal from TSM 104 is routed to the ClockDR input of data register 902, the ShiftDR signal from TSM 104 is routed to the ShiftDR input of data register 902, and the UpdateDR signal from TSM 104 is routed to the UpdateDR input of data register 902. When the routing circuit 906 is disabled by DRE signal inputs, the gating circuits 1102-1106 isolate the TSM ClockDR, ShiftDR and UpdateDR outputs from the data register ClockDR, ShiftDR and UpdateDR inputs and sets the ClockDR, ShiftDR and UpdateDR inputs to the data register to static desired states. If clock multiplexer 1108 is included in the routing circuit 906, it will be controlled by a DRE input to select the ClockDR input to the data register 902 to be driven by either the ClockDR output of gating circuit 1102 during test mode or by a functional clock (FC) signal during non-test mode, i.e. during functional device operation mode.
The Gating circuits of FIG. 11 and following Figures of this disclosure can be any type of gating circuitry required to control the data register inputs to the appropriate signal levels during test and during functional operation modes.
FIG. 13 illustrates an example asynchronous CS data register 1302 coupled to TSM 104 via a routing circuit 1306 located within DRC router 110 of FIG. 4. When the routing circuit 1306 is enabled by DRE inputs from the instruction register 106, the ClockDR and ShiftDR signals from the TSM pass through the routing circuit to operate CS scan cells 1304 within data register 1302. Data register 1302 could be, but is not limited to being, the test data register of FIG. 8A for testing circuitry coupled to the DI input and DO output of the scan cells 1304. The FF 1404 of the scan cells 1304 is typically shared between functional and test operations.
FIG. 14 illustrates the CS scan cell 1304 which comprises a multiplexer 1402 and shift register FF 1404. When the TSM is in the Capture-DR state of FIG. 2, multiplexer 1402 will be set by the ShiftDR signal to couple the scan cell's data input (DI) to FF 1404 to allow the DI to be captured into FF 1404 in response to a clock input on ClockDR. When the TSM is in the Shift-DR state of FIG. 2, multiplexer 1402 will be set by the ShiftDR signal to couple the TDI signal to FF 1404 to allow TDI data to be shifted into FF 1404 and TDO data to be shifted out of FF 1404 in response to clock inputs on ClockDR. As seen the data output from FF 1404 is output on the scan cell's DO and TDO output.
FIG. 15 illustrates routing circuit 1306 which comprises a gating circuit 1502, a gating circuitry 1504 and optionally the previously describe clock multiplexer 1108 of FIG. 12. When routing circuit 1306 is enable by DRE signal inputs, the ClockDR signal from TSM 104 is routed to the ClockDR input of data register 1302 and the ShiftDR signal from TSM 104 is routed to the ShiftDR input of data register 1302. When the routing circuit 906 is disable by DRE signal inputs, the gating circuits 1502-1504 isolate the TSM ClockDR and ShiftDR outputs from the data register ClockDR and ShiftDR inputs and sets the ClockDR and ShiftDR inputs to the data register to static desired states. If clock multiplexer 1108 is included in the routing circuit 1306, it will be controlled by a DRE input to select the ClockDR input to the data register 902 to be driven by either the ClockDR output of gating circuit 1502 during test mode or by a FC during non-test mode.
FIG. 16 illustrates an example synchronous CSU data register 1602 coupled to TSM 104 via a routing circuit 1606 located within DRC router 110 of FIG. 4. Data register 1602 could be, but is not limited to being, the IEEE 1149.1 IC boundary register of FIGS. 8E and 8F or the IEEE 1500 core wrapper boundary register of FIGS. 8G and 8H. When the routing circuit 1606 is enable by DRE inputs from the instruction register 106, the Capture, Shift and Update signals from the TSM pass through the routing circuit to operate CSU scan cells 1604 within data register 1602.
FIG. 17 illustrates the CSU scan cell 1604 which comprises a multiplexer 1702, a shift register FF 1704, a multiplexer 1706, an update register FF 1708 and optionally a multiplexer 1710. When the TSM is in the Capture-DR state of FIG. 2, multiplexer 1702 will be set by the Capture and Shift signals to couple the scan cell's data input (DI) to FF 1704 to allow the DI to be captured into FF 1704 in response to the free running TCK signal. When the TSM is in the Shift-DR state of FIG. 2, multiplexer 1702 will be set by the Capture and Shift signals to couple the TDI signal to FF 1704 to allow TDI data to be shifted into FF 1704 and TDO data to be shifted out of FF 1704 in response to the free running TCK signal. When the TSM is not in either the Capture-DR or Shift-DR state, multiplexer 1702 couples the output of FF 1704 to the input of FF 1704 causing FF 1704 to hold its present state in response to TCK inputs. When the TSM is in the Update-DR state of FIG. 2, FF 1708 will update (load) with the data output from FF 1704 in response to the free running TCK input and output the data on the scan cell's data output (DO). If the scan cell 1604 does not include multiplexer 1710 the DO from update FF 1708 will pass directly to DO 1714. If the scan cell 1604 includes multiplexer 1710 the DO from update FF 1708 will pass to DO 1712 via multiplexer 1710. When scan cell 1604 includes the multiplexer 1710 it operates as an IEEE 1149.1 or IEEE 1500 boundary scan cell which allows DO 1712 to be selectively driven by DI or by the output of update FF 1708 in response to a Mode signal input from the DRE bus. Including multiplexer 1710 supports boundary scan testing on the interconnects between devices as shown in FIG. 8I
FIG. 18 illustrates routing circuit 1606 which comprises a gating circuit 1802, a gating circuitry 1804 and a gating circuitry 1806. When routing circuit 1606 is enable by DRE signal inputs, the Capture signal from TSM 104 is routed to the Capture input of data register 1602, the Shift signal from TSM 104 is routed to the Shift input of data register 1602, and the Update signal from TSM 104 is routed to the Update input of data register 1602. When the routing circuit 1602 is disable by DRE signal inputs, the gating circuits 1802-1806 isolate the TSM Capture, Shift and Update outputs from the data register Capture, Shift and Update inputs and sets the Capture, Shift and Update inputs to the data register to static desired states.
As seen in FIG. 16, a clock multiplexer 1608 as shown in FIG. 16A can be included in the TCK path to the scan cells of data register 1602. If included, the clock multiplexer can be controlled by a DRE input to select the TCK input to the scan cells to be driven by either the TCK signal during test mode or by a FC during non-test mode.
FIG. 19 illustrates an example synchronous CS data register 1902 coupled to TSM 104 via a routing circuit 1906 located within DRC router 110 of FIG. 4. When the routing circuit 1906 is enable by DRE inputs from the instruction register 106, the Capture and Shift signals from the TSM pass through the routing circuit to operate CS scan cells 1904 within data register 1902. Data register 1902 could be, but is not limited to being, the test data register of FIG. 8A for testing circuitry coupled to the DI input and DO output of the scan cells 1904.
FIG. 20 illustrates the CS scan cell 1904 which comprises a multiplexer 2002 and shift register FF 2004. When the TSM is in the Capture-DR state of FIG. 2, multiplexer 2002 will be set by the Capture and Shift signals to couple the scan cell's data input (DI) to FF 2004 to allow the DI to be captured into FF 2004 in response to the free running TCK signal. When the TSM is in the Shift-DR state of FIG. 2, multiplexer 2002 will be set by the Capture and Shift signals to couple the TDI signal to FF 2004 to allow TDI data to be shifted into FF 2004 and TDO data to be shifted out of FF 2004 in response to the free running TCK signal. When the TSM is not in either the Capture-DR or Shift-DR state, multiplexer 2002 couples the output of FF 2004 to the input of FF 2004 causing FF 2004 to hold its present state in response to TCK inputs. As seen the data output from FF 2004 is output on the scan cell's DO and TDO output.
FIG. 21 illustrates routing circuit 1906 which comprises a gating circuit 2102 and gating circuitry 2104. When routing circuit 1906 is enable by DRE signal inputs, the Capture signal from TSM 104 is routed to the Capture input of data register 1902 and the Shift signal from TSM 104 is routed to the Shift input of data register 1902. When the routing circuit 1902 is disable by DRE signal inputs, the gating circuits 2102-2104 isolate the TSM Capture and Shift outputs from the data register Capture and Shift inputs and sets the Capture and Shift inputs to the data register to static desired states.
As seen in FIG. 19, clock multiplexer 1608 shown and described in regard to FIGS. 16 and 16A can be included in the TCK path to the scan cells of data register 1902 to allow the scan cells to be driven by either the TCK signal during test mode or by a FC during non-test mode.
FIG. 22 illustrates an example test compression architecture (TCA) 2202 within a device coupled to a TSM 104 via routing circuit 1306. TCA architectures are well known, such as but not limited to Mentor's TestKompress™ architecture. The example TCA comprises a decompressor circuit 2204, parallel scan paths 2206, and a compactor circuit 2208. Each scan path comprises scan cells as described in FIGS. 13 and 14. The TCA of FIG. 22, while significantly more complex in construction, can be operated in basically the same way as the asynchronous data register 1302 of FIG. 13 by coupling the TSM 104 to the TCA via routing circuit 1306. The decompressor circuit operates to input compressed test data from TDI and decompress the test data into individual stimulus data inputs to the scan paths. The compactor circuit operates to input individual outputs from the scan paths and compact them down to a compressed test data output signal on TDO.
When routing circuit 1306 is enabled by DRE inputs from the instruction register 106, the ClockDR and ShiftDR signals from the TSM pass through the routing circuit to operate the decompressor, scan paths and compactor circuits to perform capture and shift operations as described in regard to the data register 1302 of FIGS. 13, 14 and 15. When the TSM is in the Capture-DR state of FIG. 2, the ClockDR and ShiftDR signals are operated to perform a capture operation which loads response data from combinational logic associated with the scan paths and initializes the decompressor circuit 2204 to receive a stream of compressed test data from TDI. When the TSM is in the Shift-DR state of FIG. 2, the ClockDR and ShiftDR signals are operated to perform a shift operation which shifts stimulus data from the decompressor circuit into the scan paths and shifts response data from the scan paths into the compactor circuit. The response data input to the compactor circuit during the shift operation is compacted down to a single stream of compressed test data output on the TDO signal.
As seen in FIG. 22, clock multiplexer 1108 shown and described in regard to FIGS. 11 and 12 can be included in the ClockDR path to the scan cells of the scan paths 2206 to allow the scan cells to be driven by either the ClockDR signal during test mode or by a FC during non-test mode.
FIG. 23 illustrates another example test compression architecture (TCA) 2202 within a device coupled to a TSM 104 via routing circuit 1906. The example TCA comprises a decompressor circuit 2304, parallel scan paths 2306, and a compactor circuit 2308. Each scan path comprises scan cells as described in FIGS. 19 and 20. The TCA of FIG. 23, while significantly more complex in construction, can be operated in basically the same way as the synchronous data register 1902 of FIG. 19 by coupling the TSM 104 to the TCA via routing circuit 1306. The decompressor circuit operates to input compressed test data from TDI and decompress the test data into individual stimulus data inputs to the scan paths. The compactor circuit operates to input individual outputs from the scan paths and compact them down to a compressed test data output signal on TDO.
When routing circuit 1906 is enabled by DRE inputs from the instruction register 106, the Capture and Shift signals from the TSM pass through the routing circuit to operate the decompressor, scan paths and compactor circuits to perform capture and shift operations as described in regard to the data register 1902 of FIGS. 19, 20 and 21. When the TSM is in the Capture-DR state of FIG. 2, the Capture, Shift and TCK signals operate to perform a capture operation which loads response data from combinational logic associated with the scan paths and initializes the decompressor circuit 2304 to receive a stream of compressed test data from TDI. When the TSM is in the Shift-DR state of FIG. 2, the Capture, Shift and TCK signals operate to perform a shift operation which shifts stimulus data from the decompressor circuit into the scan paths and shifts response data from the scan paths into the compactor circuit. The response data input to the compactor circuit during the shift operation is compacted down to a single stream of compressed test data output on the TDO signal.
As seen in FIG. 23, clock multiplexer 1608 shown and described in regard to FIGS. 16 and 19 can be included in the TCK path to the scan cells of the scan paths 2306 to allow the scan cells to be driven by either the TCK signal during test mode or by a FC signal during non-test mode.