Embodiments of the present invention relate generally to semiconductor chip packaging, and more specifically to a collar structure placed around solder balls used to connect a semiconductor die to a semiconductor chip package substrate.
In a typical assembly of a semiconductor die or integrated circuit to a semiconductor chip package substrate, solder balls are attached to respective bond pads on the die. The semiconductor die is then placed onto the semiconductor chip package substrate. An anneal is performed to join the solder balls on the semiconductor die to respective bond pads on the semiconductor chip package substrate. Typically, there is a high degree of mismatch between the coefficients of thermal expansion (CTE) between the solder balls, the semiconductor die and the semiconductor chip package substrate. The mismatch of CTE results in the formation of large strains that cause thermal stresses to develop about the solder balls and the semiconductor die during thermal cycling. Thermal stresses become more prevalent with the use of low-k dielectrics in the semiconductor dies and lead-free solder balls. In particular, low-k dielectrics tend to be more porous, making them mechanically weak and more susceptible to the formation of thermal stresses resulting from CTE mismatch. Lead-free solder balls generally have a higher melting point than lead solder balls, which further exacerbates the CTE mismatch, and results in more thermal stress formations during thermal cycling.