1. Field
This invention relates generally to switched-capacitor circuits and more specifically to a switched-capacitor amplifier circuit that may be disposed on an integrated circuit.
2. Related Art
A switched-capacitor circuit is a circuit that provides signals that are discrete in time and continuous in voltage amplitude. Correlated double sampling (CDS) is a technique used with switched-capacitor circuits to measure small, slowly changing signals in the presence of large amounts of low frequency (1/f) noise and direct current (DC) input offset voltage. The CDS technique is a particular type of auto-zero technique, in which noise and a DC input offset voltage are sampled twice in each clock period. Switched-capacitor amplifiers often use the CDS technique to compensate for non-idealities of an operational amplifier (OpAmp) in the switched-capacitor circuit such as finite open-loop gain (hereinafter “OpAmp gain”) and DC input offset voltage. In a non-CDS amplifier, a gain error of an OpAmp is approximately inversely proportional to the OpAmp gain, i.e., gain error≈1/gain of the OpAmp. The CDS technique minimizes the gain error of the OpAmp. The CDS technique effectively makes the gain error of the OpAmp in a switched capacitor amplifier inversely proportional to a square of the gain of the OpAmp, i.e., gain error≈1/gain2.
In most switched-capacitor amplifiers that do not use the CDS technique, an output of an OpAmp is re-set to analog ground (AGND), which is defined as (VDD+VSS)/2, on each occasion that the switched-capacitor amplifier samples an input signal during a sampling time phase, or phase one. During an amplification time phase, or phase two, the output of the OpAmp goes from AGND to a voltage that represents the input differential voltage multiplied by a gain. Capacitors are charged or re-charged during each phase to change the output of the switched-capacitor amplifier to a new value that represents a present input differential voltage multiplied by a gain.
In a switched-capacitor amplifier that uses the CDS technique (hereinafter “CDS amplifier”), the output of the OpAmp is not re-set to AGND at each phase one. In a CDS amplifier, the output of the OpAmp remains at the voltage that it had in an immediately previous phase two, and the output of the OpAmp is not re-set to AGND. In a CDS amplifier, the input signal is assumed to change very slowly with respect to a sampling frequency. Therefore, in any clock phase, the value of an output signal does not vary much from a value that it had during an immediately previous clock phase. Consequently, the CDS amplifier can take advantage of the output voltage from a previous sample (which is stored in a capacitor), and can obtain a new value during the amplification phase more quickly than if the output were re-set to AGND. This is because the previous output level is close in value to a next output value. By using the CDS technique, a switched-capacitor amplifier requires less time to produce each new output value.
A rail-to-rail OpAmp can properly amplify an input differential signal even if the input common-mode voltage is near either of the rails, i.e., VDD or VSS, of a power supply. An input differential signal of an OpAmp comprises an input differential voltage plus an input common-mode voltage. A non-rail-to-rail input OpAmp (hereinafter “non-rail-to-rail OpAmp”) has a limited input common-mode range and can properly amplify only differential signals that have a common-mode voltage near AGND. In other words, a non-rail-to-rail OpAmp cannot properly amplify a differential signal that has a common-mode voltage near either rail because the non-rail-to-rail OpAmp has a limited common-mode range.
The known CDS amplifier 102 comprises a first sampling switch 106 with one terminal connected to a VIP input terminal 104 and another terminal connected to a first sampling capacitor 130, and a second sampling switch 107 with one terminal connected to a VIN input terminal 105 and another terminal connected to a second sampling capacitor 131. The known CDS amplifier 102 also comprises a first grounding switch 108 with one terminal connected to the first sampling capacitor 130 and another terminal connected to an AGND terminal 103, and a second grounding switch 109 with one terminal connected to the second sampling capacitor 131 and another terminal connected to the AGND terminal 103. Additionally, the known CDS amplifier 102 comprises a first gain capacitor 140 with one end connected to a VN input terminal 162 of the OpAmp 160 and another end connected to the AGND terminal 103 when switch 142 is closed and connected to an output terminal 164 of the OpAmp when switch 144 is closed. The known CDS amplifier 102 also comprises a second gain capacitor 141 with one end connected to the AGND terminal 103 and another end connected to a VP input terminal 163 of the OpAmp 160. The known CDS amplifier 102 further comprises a first CDS capacitor 150 with one end connected to the output terminal 164 of the OpAmp 160 and another end connected to the VN input terminal 162 of the OpAmp when switch 152 is closed, and connected to the AGND terminal 103 when switch 154 is closed. The known CDS amplifier 102 further comprises a second CDS capacitor 151 with one end connected to the AGND terminal 103 and another end connected to the VP input terminal 163 of the OpAmp 160 when switch 153 is closed and connected to the AGND terminal 103 when switch 155 is closed.
The following assumes that the known CDS amplifier 102 has started, i.e., it has operated in phase one and phase two long enough to set properly the output voltage VO, and the voltages at the VN input terminal 162 and at the VP input terminal 163 of the OpAmp 160 are near AGND. In phase one (the sampling phase), only the F1 switches are closed, which allows sampling capacitors 130 and 131 to sample the input signal. The input signal can be expressed as VI=V1+VCM, where Vi is an input differential voltage, Vi=VIP−VIN, and where VCM is an input common-mode voltage, VCM=(VIP+VIN)/2. In phase one, a right plate of gain capacitor 140 is coupled to the AGND terminal 103, CDS capacitor 150 closes the feedback loop around the OpAmp 160, and gain capacitor 140 stores any error voltage (due to OpAmp gain error and/or DC input offset voltage). In phase two (the amplification phase), only the F2 switches are closed, and the charges stored in sampling capacitors 130 and 131 are transferred to gain capacitors 140 and 141 to amplify the input differential voltage. The CDS capacitor 150 compensates for the gain error and/or the DC input offset voltage of the OpAmp 160 such that an output voltage VO of the OpAmp is not affected by these factors. However, disadvantageously, the output of the known CDS amplifier 102 is not immune to VCM. The known CDS amplifier 102 has gain errors when VCM is close to either rail of the power supply.
In phase one, the F1 switches are closed. The known CDS amplifier 102 may work properly when the input common-mode voltage is near AGND. For example, when the common-mode voltage of the input signal is at AGND, the output error may not be greater than one-half of a least significant bit (LSB) with 16-bit resolution, where LSB=VDD/2n, where n is number of bits of resolution (LSB=VDD/216 in this example). In other words, when the common-mode voltage of the input signal is at AGND, the CDS amplifier 102 amplifies the input signal with 16-bit resolution. However, when the common-mode voltage of the input signal is near VDD or VSS, the output error of the known CDS amplifier 102 may be disadvantageously in the range of one-half of a LSB when the number of bits of resolution is 12-bits or fewer. In other words, the resolution of the CDS amplifier 102 reduces from sixteen bits, to twelve or fewer bits, when the common-mode input voltage is close to the power supply rails.
The following assumes that the inputs of the OpAmp 160 are near AGND. In phase one, by coupling the CDS capacitor 150 between a VN input terminal 162 and a VO output terminal of the OpAmp 160, a VN input voltage of the OpAmp is forced to be near AGND. In phase two, gain capacitor 140 is coupled between the VO output terminal 164 of the OpAmp 160 and the VN input terminal 162 of the OpAmp.
As an example, in phase one, a charge is placed on each of the sampling capacitors 130 and 131 (a charge equivalent to +50 mV on sampling capacitor 130 and a charge equivalent to −50 mV on sampling capacitor 131, with respect to AGND). In the known CDS amplifier 102, in phase two, a left plate of sampling capacitor 130 is coupled to the AGND terminal 103, thereby discharging the left plate of the sampling capacitor 130 and leaving a charge equivalent to −50 mV on the right plate of sampling capacitor 130. As a result of the left plate of sampling capacitor 130 being coupled to the AGND terminal 103, a corresponding current flows through gain capacitor 140. Sampling capacitor 130 and gain capacitor 140 are connected in series; therefore, a current flowing in sampling capacitor 130 is a same current flowing in gain capacitor 140 because no current flows into or out of the OpAmp 160, which is assumed to be ideal, i.e., has infinite input impedance. Provided that phase two is of sufficient duration, enough current flows during phase two to transfer all the charge in sampling capacitor 130 to gain capacitor 140. In one embodiment, gain capacitor 140 is half the size of sampling capacitor 130. In such embodiment, at the end of phase two, the voltage across the gain capacitor 140 is twice the voltage that was across sampling capacitors 130 and 131. A ratio sampling capacitor 130/gain capacitor 140 defines a gain of the known CDS amplifier 102. At the end of phase two, if gain capacitor 140 is half the size of sampling capacitor 130, then the voltage gain is two (2). At the end of phase two, the voltage across gain capacitor 140 is twice the voltage that was seen across sampling capacitors 130 and 131 at the beginning of phase two, i.e., the right plate of gain capacitor 140 is at a potential of 200 mV with respect to AGND. In such embodiment, at the end of phase two, an output voltage of the known CDS amplifier 102 is two times the input differential voltage of 100 mV, that is, the output voltage is +200 mV with respect to AGND. A disadvantage of the known CDS amplifier 102 is that, during phase two, the input common-mode voltage VCM affects the input of the OpAmp 160.
The known CDS amplifier 102 does not work properly if the common-mode voltage is not near AGND. When the common-mode voltage is not near AGND, the differential voltage at the input of the OpAmp 160 alternates, or pulses, between approximately AGND (during the sampling phase, or phase one) and a second voltage other than AGND (during the amplification phase, or phase two). During the sampling phase, the input to the OpAmp 160 is maintained near AGND because of the feedback loop comprising gain capacitor 140. (During the sampling phase, the input differential signal, VIP and VIN, is not presented to the input of the OpAmp 160, but is being stored in sampling capacitors 130 and 131.) During the amplification phase, charge is transferred between sampling capacitor 130 and gain capacitor 140. As a result, a voltage, which, in general, is at a potential other than AGND, appears at the input of the OpAmp 160. If the common-mode voltage is above AGND, the second voltage is at a potential below AGND. If the common-mode voltage is below AGND, the second voltage is at a potential above AGND. Such pulsing occurs because switches 108 and 109 alternately couple one of the input signal (during phase one) and AGND (during phase two) to the OpAmp 160. The peak-to-peak level of the pulses is directly proportional to a difference between the input common-mode voltage and AGND. Therefore, the peak-to-peak level of the pulses is small when the input common-mode voltage is near AGND. However, when the common-mode voltage is near VDD or near VSS, such pulsing causes an error at the output of a non-rail-to-rail OpAmp. In the known switched-capacitor amplifier 102, when VIP and VIN are each near VSS, the value of a VP input voltage at the VP input terminal 163 of the OpAmp 160 disadvantageously swings from almost AGND to almost VDD when going from phase one to phase two. Similar disadvantageous behavior occurs for the value of the VN input voltage at the VN input terminal 162 of the OpAmp 160 because the feedback loop is closed by CDS capacitor 150.