The present invention concerns a semiconductor integrated circuit device and it particularly relates to a semiconductor integrated circuit device having a plurality of transistors formed over one identical diffusion layer.
In the semiconductor integrated circuit device, reduction in the circuit area directly leads to reduction in the manufacturing cost. Particularly, in a case of semiconductor memory devices, etc., when the area of a circuit portion that is used repetitively in an identical layout pattern can be reduced even at the slightest, a significant effect of decreasing the cost can be obtained.
A sense amplifier circuit is used repetitively as a circuit portion in a dynamic semiconductor memory device. In the dynamic semiconductor memory device, a plurality of sense amplifier circuits are coupled to a memory cell array in which memory cells are arranged in a matrix. FIG. 1 is a circuit diagram showing the configuration of one sense amplifier circuit in a general dynamic semiconductor memory device.
Referring to the constitutional elements of the sense amplifier circuit in FIG. 1, the sense amplifier circuit includes a first bit line BLT, a second bit line BLN, a sense amplifier SA, a precharge/balance device Q, an equalize signal input portion EQ, and a half power source voltage input portion HVC. The precharge/balance device Q includes a first transistor Q1 as a balance device, a second transistor Q2 as a first precharge device, and a third transistor Q3 as a second precharge device. As the most general sense amplifier SA, a simple flip-flop circuit is used.
The coupling relation for the constitutional elements in the sense amplifier circuit in FIG. 1 is to be described. One end of the sense amplifier SA is coupled to a first bit line BLT. The other end of the sense amplifier SA is coupled the second bit line BLN. One of the source and the drain of the first transistor Q1 is coupled to the first bit line BLT. The other of the source and the drain of the first transistor Q1 is coupled to the second bit line BLN. Gates of the respective first to third transistors Q1 to Q3 are coupled in common to the equalize signal input portion EQ. One of the source and the drain of the second transistor Q2 is coupled to the first bit line BLT. One of the source and the drain of the third transistor Q3 is coupled to the second bit line BLN. The other of the source and the drain of the respective second and third transistors Q2 and Q3 are coupled to the half power source voltage input portion HVC.
The operation of the sense amplifier circuit shown in FIG. 1 is to be described briefly. At first, the potential difference between the first and second bit lines BLT and BLN is decided depending on the state of a memory cell coupled to one of the bit lines thereof and selected by a word line.
The half power source voltage input portion HVC supplies a half power source voltage as one-half of a power source voltage VCC to the source-drain coupling portion of the second and third transistors Q2 and Q3. As a result, the second and third transistors Q2 and Q3 precharge the half power source voltage to the first and the second bit lines BLT and BLN. Since the second and third transistors Q2 and Q3 operate as two precharge devices, they are generally designed with an identical size of the gate width and in a symmetrical layout.
Finally, the sense amplifier SA amplifies the voltages of the first and second bit lines BLT and BLN to complementary potentials in accordance with the difference between the potentials and the half power source voltage respectively.
Then, the gates of the first, second, and third transistors Q1, Q2, and Q3 are provided an equalize signal from the equalize signal input portion, respectively. As a result, the source and the drain are conducted in each of the first, second, and third transistors Q1, Q2, and Q3, and the voltages of the first and second bit lines BLT and BLN become identical. While the same effect can be obtained only by the second and third transistors Q2 and Q3, if the first transistor is added, a potential is supplied to the first and second bit lines BLT and BLN and the potentials of the BLT and BLN can be equalized at a higher speed by the first transistor when it is intended to equalize the voltages between them. As described above, since the first transistor Q1 operates as a balance device, the gate width is generally designed to be longer than the gate width of the second or third transistor Q2 or Q3 so that a larger current flows at once.
FIG. 2A is a plan view showing a layout of a semiconductor integrated circuit portion that schematically illustrates the precharge/balance device Q shown in FIG. 1. FIG. 2B is a plan view showing another layout of a semiconductor integrated circuit portion that schematically illustrates the precharge/balance device Q in FIG. 1.
Each of the semiconductor integrated circuit portions in FIG. 2A and FIG. 2B includes first to third transistors Q1 to Q3 in the same manner as the precharge/balance device Q in FIG. 1. In the layout of FIG. 2A and FIG. 2B, the first bit line BLT, the second bit line BLN, the equalize signal input portion EQ, and the half power source voltage input portion HVC are drawn as contacts that can be coupled to respective wirings.
In the layout of FIG. 2A, the first, second, and third transistors Q1, Q2, and Q3 are formed over one identical diffusion layer 11. The first, second, and third transistors Q1, Q2, and Q3 have a gate in common, and the gate is coupled to the contact for the equalize signal input portion EQ. The first and second transistors Q1 and Q2 also have the source or the drain in common, and the source or the drain is coupled to the contact for first bit lines BLT. The first and third transistor Q1 and Q3 also have the source or the drain in common and the source or the drain is coupled to the contact for the second bit lines BLN. The second and third transistors Q2 and Q3 also have the source or the drain in common and the source or the drain is coupled to the contact for the half power source voltage input portion HVC. The second and third transistors Q2 and Q3 are arranged such that the directions of the respective gate width are arranged on one extension line. Further, the first transistor Q1 is arranged such that the direction of the gate width is different from the direction of the gate width of the second or third transistor Q2 or Q3.
In the layout of FIG. 2B, the layout of FIG. 2A is rotated by 90° and, further, the position of the contact for the equalize signal input portion EQ is changed to the top of the gate protrusion portion of the first transistor Q1. Either the layout of FIG. 2A or FIG. 2B has been generally used so far.
In connection with the above technique, Japanese Patent No. 3787500 contains disclosure regarding a write/read circuit. The write/read circuit evaluates at least one of bit lines (BL, BBL) in a DRAM memory. The write/read circuit includes at least two transistor pairs (T1/T2, T4/T5) and two transistors (T3/T6) for evaluation. The two transistor pairs (T1/T2, T4/T5) for evaluation have transistors of an identical channel type respectively. The two transistors (T3/T6) apply voltages (VDD; GND) to the transistor pairs (T1/T2, T4/T5). The transistors used in the transistor pairs (T1/T2, T4/T5) are vertical MOS transistors (T1, T2, T4, and T5). The vertical MOS transistors (T1, T2, T4, and T4) in each of the transistors pairs (T1/T2, T4/T5) and the transistors (T3, T6) used for applying the voltage (VDD; GND) have respective common source/drain regions (59, 63).
Further, Japanese Unexamined Patent Publication No. 2004-87074 discloses a semiconductor integrated circuit device. The semiconductor integrated circuit device includes a sense amplifier, a first precharge MOSFET, a selection switch MOSFET, a second precharge MOSFET, and a dynamic memory cell. The sense amplifier includes a CMOS latch circuit for amplifying and holding a pair of input/output node signals corresponding to an operation timing signal. The first precharge MOSFET includes a pair of transistors disposed to input/output nodes, put to an on-state in a precharge period, and supplying a precharge voltage to respective complementary bit line pairs of the input/output nodes. The selection switch MOSFET couples the input/output node and the complementary bit line pair corresponding to a selection signal. The second precharge MOSFET is disposed between the pair of complementary bit lines for short circuiting the same. The dynamic memory cell is disposed between one of the pair of complementary bit lines and a word line crossing the same and includes an address selection MOSFET and a memory capacitor. The semiconductor integrated circuit device has a feature of including a memory circuit in which the gate insulation film of the second precharge MOSFET is formed to a smaller thickness than that of the gate insulation film of the selection MOSFET.
Further, Japanese Unexamined Patent Publication No. 2005-340367 discloses a semiconductor integrated circuit device. The semiconductor integrated circuit device includes a sense amplifier, precharge MOSFETs including paired transistors, a selection switch MOSFET, a first equalize MOSFET, and a dynamic memory cell. The sense amplifier includes a CMOS latch circuits for amplifying and holding signals of a pair of input/output node signals corresponding to an operation timing signal. The paired precharge MOSFET are disposed to the pair of input/output nodes, put to an on state during a precharge period and supplies a precharge voltage to each of the input/output nodes. The selection switch MOSFET couples the pair of input/output nodes and the complementary bit line pair corresponding to a selection signal. The first equalize MOSFET is disposed between the pair of complementary bit lines for short circuiting the same during a precharge period. The dynamic memory cell is disposed between one of the pair of complementary bit lines and a word line crossing the same, and includes an address selection MOSFET and a memory capacitor. The gate insulation film of the selection switch MOSFET and the first equalize MOSFET is formed with a gate insulation film of a first thickness. The gate insulation film of the precharge MOSFET is formed with a gate insulation film of a second thickness which is smaller than the first thickness. A precharge signal corresponding to a power source voltage is supplied to the precharge MOSFET. The first equalize MOSFET and the selection switch MOSFET include a memory circuit which is supplied with an equalize signal corresponding to an elevated voltage defined to higher than the power source voltage and a selection signal.