1. Field of the Invention
The present invention relates to an isolation testing circuit and a testing circuit optimization method for executing an isolation test of a plurality of IPs incorporated into an LSI.
2. Description of the Related Art
The number of IPs incorporated into the LSI becomes huge nowadays pursuant to the larger scale of the LSI. In order to check functions of incorporated IPs, the isolation testing circuit for leading input/output terminals of respective IPs to external terminal of the LSI must be inserted. Since the input/output terminals of respective IPs are connected to share the external terminal of the LSI, the external terminal of the LSI and respective IPs are connected via enormous wirings. In this case, the related art concerned with the IP test is disclosed in Patent Reference 1(JP-A-2001-267510), and so forth.
FIG. 10 is a configurative view of LSI showing an isolation testing circuit configuration in the related art. In FIG. 10, a test input signal 1009 input from the external device via a test input terminal 1007 is connected to IP blocks 1001 to 1006 incorporated into the LSI via one wiring respectively. Also, test output signals 1017 to 1022 of respective IP blocks 1001 to 1006 are connected to a test output terminal 1015 via a test switching selector 1037 in such a manner that all wirings are converged into the test output terminal 1015. Such wirings are inserted as many as the number of the test input signals used in the isolation test.
However, according to the method in the related art, a large number of wirings that are extended from the external terminal to respective IPs in a one-to-multiple fashion and wirings that are converged into one location must be inserted. As a result, problems such as a routing complexity, a signal rounding, etc. were caused in a layout design of LSI, so that a floor plan of LSI often failed and an increase of a chip size and a delay of a development term were brought about.