As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have motivated circuit designers to look to novel structures to deliver improved performance. One avenue of inquiry is the development of three-dimensional designs, such as a fin-like field effect transistor (FinFET). A FinFET can be thought of as a typical planar device extruded out of a substrate and into the gate. A typical FinFET is fabricated on a thin “fin” (or fin structure) extending upwards from the body from the substrate, and may be formed by depositing fin material on the substrate, etching, non-fin areas of the substrate, or a combination thereof. The channel of the FET is formed in this vertical fin, and a gate is provided over (e.g., wrapping) the fin. Wrapping the gate around the fin increases the contact area between the channel region and the gate and allows the gate to control the channel from both sides. This may result in higher current flow, a reduction in short channel effect, and other advantages.
Because of the complexity inherent in FinFETs and other nonplanar devices, a number of techniques used in manufacturing planar transistors are not available in manufacturing nonplanar devices. As merely one example, buried insulator layers are used to isolate devices and to lower parasitic capacitance. However, many conventional techniques for forming a semiconductor substrate with a buried insulator layer are not well suited for use with FinFET devices. Therefore, while existing fabrication techniques have been generally adequate for planar devices, in order to continue to meet ever-increasing design requirements, further advances are needed.