Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device that includes a duty correction circuit for adjusting a duty ratio of a clock signal,
Description of Related Art
The type called DDR (Double Data Rate) is the mainstream of DRAM (Dynamic Random Access Memory), which is a typical semiconductor memory device. The DDR-type DRAM is designed to input or output data in synchronization with both rising and falling edges of the clock signal. Therefore, the duty ratio of the clock signal needs to be precisely kept at 50%. For that purpose, a duty correction circuit is frequently used (See Japanese Patent Application Laid-Open No. 2008-210436).
The duty correction circuit is usually incorporated into a DLL (Delay Locked Loop) circuit that controls the phase of the clock signal. The DLL circuit includes a delay line that delays the clock signal. The duty ratio of the clock signal that has passed through the delay line is detected by a duty cycle detector, and the results thereof are fed back to the duty correction circuit, which then adjust the duty ratio of the clock signal.
However, the delay line has a relatively large amount of inherent delay. Therefore, the loop length of a feedback loop consisting of the duty correction circuit and the duty cycle-detector is relatively long. This leads to a decrease in feedback responsiveness in duty-control. The problem is that it takes a long time to reach a desired duty ratio.