a) Field of the Invention
The present invention relates to manufacture of insulating films, and more particularly to a method of manufacturing semiconductor devices having planarized insulating films.
b) Description of the Related Art
Requests for high integration and high speed operation of semiconductor IC devices are increasing more and more. In order to highly integrate semiconductor elements and operate them at a high speed, it is necessary to layout a number of semiconductor elements in a small chip area and in some cases interconnect elements by multi-level wiring patterns by increasing the number of wiring layers. It is desired to narrow the width of each wiring pattern. However, a wiring pattern with a narrow width becomes higher than a wiring pattern with a broad width if both the wiring patterns should have the same resistance.
The surface of a chip having such multi-level wiring layers becomes extraordinarily irregular, so that not only the step coverage of a wiring layer formed thereover is degraded but also the precision of photolithography is lowered. Therefore, planarization technique plays a more important role in planarizing surfaces of underlie films such as an interlevel insulating film, prior to forming multi-level wiring layers thereon.
Reflow of glasses having a softening point lowered by additive impurities, such as phosphorous silicate glass (PSG), boron silicate glass (BSG), and boron phosphorous silicate glass (BPSG), is known as one of such insulating film planarization techniques. Glass reflow technique requires a relatively high temperature so that its use is restricted to some applications, and cannot be applied to semiconductor chips having wiring layers with low heat resistance such as Al or a highly precise impurity profile.
Lower temperature planarization technique has been desired. Silicon oxide film deposition technique by reacting tetraethoxy silane (TEOS) with ozone, can be used at a relatively low temperature and has a self-planarization function of reducing steps of the surface of an underlie layer. Although a region between convexities having a relatively narrow span can be efficiently filled with an ozone-TEOS oxide film, the planarization performance is lowered at a region between convexities having a wider span.
A spin-on-glass (SOG) silicon oxide film can be formed by spin-coating liquid phase silicon compound such as polysilazane at a room temperature and curing it. This method has a good planarization performance because of use of liquid phase silicon compound.
It is difficult to sufficiently planarize a stepped surface of a substrate by an ozone-TEOS oxide film, if convexities formed by a wiring pattern or other patterns have a broad span.
In forming a silicon oxide film through SOG, polysilazane is spin-coated on the surface of a substrate, and then is cured in an aqueous (water) vapor atmosphere to replace N atoms of silazane bonds in polymer with O atoms. During curing in an aqueous vapor atmosphere, water contents permeate into wiring patterns under the SOG film so that the patterns become easy to be corroded; In addition, rapid replacement of N atoms with O atoms generates heat. Although this heat does not corrode wiring patterns, the patterns may be destroyed and locally narrowed. A current density at a narrowed wiring pattern increases, and electromigration becomes likely to occur. If destruction is large, the wiring pattern may be broken away.