(1) Field of the Invention
The invention relates to a semiconductor-device design method, a semiconductor-device design program, and a semiconductor-device design apparatus, particularly those wherein change in capacitance due to a dummy pattern is taken into consideration.
(2) Description of the Related Art
At present, in the field of semiconductor devices, inserting a dummy pattern between wiring patterns is an essential technique for reducing difference in flatness of a chip surface and difference in thickness of wiring patterns, which differences are due to uneven wiring pattern density. Hence, there is a design tool for designing a semiconductor device with dummy patterns inserted.
For example, in aluminum wiring, when etching for forming wiring is carried out, side-wall protective films are formed on side-walls of wiring patterns. Uneven wiring pattern density would cause an undesired variance in the side-wall protective film thickness. The existing design tools avoid this problem by placing dummy patterns in sparse portions to populate the patterns as uniformly as possible.
In copper wiring, uneven wiring pattern density would cause dishing, that is, a phenomenon that the center of a wiring pattern is dented, in CMP (Chemical Mechanical Polishing). The existing design tools avoid this problem by placing dummy patterns in sparse portions to populate the patterns as uniformly as possible.
However, when a dummy pattern having no potential difference (being in a floating state) is inserted between wiring patterns, the physical distance between the wiring patterns becomes smaller by the width of the dummy pattern. Hence, the capacitance value between the wiring patterns changes.
FIG. 10 shows a flow of a process performed by a conventional design tool. The design tool is installed in a computer to perform the following process:
[Step S21] Process information about wiring structure such as wiring width, wiring distance, wiring height and dielectric constant of a wiring pattern in each wiring layer is received.
[Step S22] A capacitance value for each of wiring distances between the wiring patterns defined by the process information is calculated, and an RC rule file containing the calculated capacitance values is created. The RC rule file is stored in an RC rule database.
[Step S23] Referring to the RC rule file, capacitance values produced between wiring patterns of an intended semiconductor device defined by layout data stored in a layout database are calculated.
[Step S24] Using the calculated capacitance values, analysis of operation of a signal in the wiring patterns defined by the layout data is performed.
[Step S25] Whether the signal performs intended operation or not is determined. If the signal does not perform the intended operation, step S26 is taken. If it does, step S28 is taken.
[Step S26] The layout data is corrected in respect of the wiring patterns so that the signal will perform the intended operation. The layout data corrected in respect of the wiring patterns is stored in the layout database.
[Step S27] Whether the corrected layout data meets design rules such as a rule about processing dimension or not is checked.
[Step S28] Dummy patterns defined by data stored in a dummy rule database are inserted between the wiring patterns defined by the layout data.
[Step S29] Mask data is generated from the layout data, which covers dummy patterns inserted between wiring patterns.
In the case of the conventional design tool, the RC rule file does not reflect change in capacitance due to the inserted dummy patterns. The operation analysis is carried out using the capacitance values calculated referring to this RC rule file, and mask data about the wiring patterns with the dummy patterns inserted between is created. Thus, with the conventional design tool, there is a problem that a semiconductor device is designed without considering change in capacitance between wiring patterns due to an inserted dummy pattern.