The disclosure relates to a clock data recovery (CDR) circuit having a function of reproducing a clock signal from data having a clock signal embedded in a data row, and relates to, for example, a technique effective in a case of application to a data input interface circuit using a CDR circuit in which a specific data pattern is used for frequency lock.
In a display driving device that performs display driving of a liquid crystal display (LCD) or the like, the speeds required of a data input interface circuit have increased corresponding to increases in the high definition of the display. A CDR circuit can be used as part of a clock-embedded data input interface for high-speed transmission.
In one example, JP-A-2012-44446 discloses a clock data recovery circuit that generates and outputs a clock signal for extracting data from a data signal transmitted in a serial manner, and that includes a frequency-locked loop for locking the clock signal to a desired frequency using a predetermined reference clock signal, and a phase-locked loop for phase-synchronizing the clock signal with the data signal in the locked state of the clock signal. Frequency comparison of the reference clock signal with the clock signal is performed during an operation of the frequency-locked loop, a clock signal is generated having a frequency according to the comparison result, and the phases of the generated clock signal and data are synchronized by bringing the phase-locked loop into operation.