The threshold voltage (V.sub.t) tolerance on metal-oxide semiconducting field effect transistor (MOSFET) is an important design parameter in very large scale integrated circuits (VLSI). The threshold voltage (V.sub.t) is contributed to mainly by variations in insulator charge, gate oxide thickness, short channel effect, narrow channel effect and macroscopic doping tolerance. The statistical total is typically in the vicinity of 200 mV. As the dimensions of MOSFET devices are reduced, constant field scaling dictates that the doping level within the channel increase in inverse proportion to the device dimension. This means that the number of dopant atoms within the device channel decreases in proportion to the square of the device dimensions. Device operation, dependent upon a forbidden energy gap within the silicon, free of sub-bands, requires that the location of dopant impurity ions within the silicon lattice be completely statiscally random. As the number of dopant ions within a device decreases, statistical fluctuations in the random placement of dopant ions will increase from device to device. Since the threshold voltage (V.sub.t) of a MOSFET strongly depends on the doping, threshold voltage tolerance due to statistical dopant density fluctuation similarly increases.
It has been shown that for a scaled device design point with a width to length equivalency of 0.1 .mu.m, has an average number of 360 dopant ions within the channel. In a device with these dimensions, a one sigma threshold voltage (V.sub.t) tolerance is only 20 mV. In effect, as dimensions continue to decrease, threshold voltage (V.sub.t) tolerance in MOSFETs will not only become dominant, but will constitute a practical limit MOSFET dimensional scaling and device application. Also, in this environment, expanded applications for MOSFETs, e.g., in production drivers and clock drivers with uniform characteristics and delays, become especially difficult since circuit timing and delay times become critical as dimensions become smaller and the demand for circuit speeds increases.
One approach to overcoming statistical dopant density fluctuation is to provide a ground plane doping profile wherein a high doping region is buried beneath a near intrinsic layer at the device surface. Although this type of retrograde doping profile does reduce the sensitivity to the doping variations, it negatively increases the sensitivity to short channel effects.
A method to decrease the sensitivity to both doping fluctuations and channel length variations is to completely remove the impurity in the channel. This is accomplished by using intrinsic silicon on insulator (SOI) devices. However, the same requires both very thin silicon films of approximately 20 nanometers (nm) for device length of 0.1 .mu.m, and an alternative means of controlling the threshold voltage (V.sub.t) other than by impurity doping. In other words, a processing technology change would be required with a departure from conventional processing tools and steps, or changing the gate material from polysilicon to a metal.
Thus, what is needed is a method and structure for MOSFETs which reduce or eliminate the effects of statistical dopant fluctuations and channel length variations as the dimensions in these devices continue to scale down. Further, it is desirable to develop a method and structure for MOSFETs which can accord these benefits using conventional processing tools and process steps.