High density integrated circuits including monolithic circuits and ultra high-speed digital circuits are produced by forming a plurality of integrated circuits on semiconductor wafers. Prior to subdividing the semiconductor wafer into individual circuit chips, die or devices, each chip/die/device should be functionally tested to identify defective circuits. In testing integrated circuits, one objective is the attainment of an accurate representation of the circuit parameters and performance under operational conditions. Ideally, the apparatus and method should be conducive to high frequency/high speed testing, simple to fabricate, durable and require minimal packaging and fixturing for testing.
To ensure an accurate representation of individual element parameters and performance of the interconnected circuit elements, an effective probe system engages the contact elements of the IC chip to be tested, which lie in approximately the same plane, to ensure proper engagement therebetween for reliable and repeatable electrical test signal propagation. A planarized probe system with mirror-imaged contact elements ensures an acceptable level of engagement force between the probe system contact elements and the contact elements of the IC chips, one wherein physical damage to the contact pads and/or the underlying semiconductor substrate is minimized and deformation of the wafer probe elements is effectively eliminated.
A semiconductor wafer testing scheme typically used in the industry is exemplified in FIG. 1. Individual integrated circuits, i.e., chips, die or devices, are multiply formed on semiconductor wafers at the first stage. The individual integrated circuits are DC tested for electrical integrity at the second stage. The individual integrated circuits are then packaged in a usable configuration, e.g., mounted in flatpacks or dual in-line packages, in the third stage. The mounted integrated circuits are then performance tested in the final stage. Individual integrated circuits which are defective are rejected at either the second or final stage. Typically, approximately 60-80% of the integrated circuits are acceptable at the second stage and approximately 85% of the packaged integrated circuits are acceptable at the final stage.
It will be appreciated that the above-described wafer testing scheme has several inherent disadvantages. The greatest cost is incurred in packaging integrated circuits at the third stage. As a consequence, packaged integrated circuits rejected at the final stage represent a significant expense. The overall time period for the illustrated testing scheme may run up to twelve weeks. If final stage performance testing reveals that the integrated circuits are being fabricated in a defective manner, feedback to modify the wafer fabrication process at the first stage will be untimely, resulting in the fabrication of semiconductor wafers which must be discarded.
One prior art method employs a plurality of probe needles having tips which physically engage the terminal contact pads of the IC chips to be tested. Representative examples of such prior art are disclosed and illustrated in U.S. Pat. Nos. 4,382,228, 4,518,914, 4,523,144, 4,567,433 and 4,593,243. While needle probe systems are generally an effective means of determining the parameters of low density IC chips, there are several drawbacks which decrease their utility for testing high density IC chips.
First, to ensure that the plurality of needle tips lie in approximately the same plane, the probe needles may require mechanical finishing by sanding or filing to bring the needle tips within the required tolerance range, i.e., degree of planarization. As well as being a time consuming and expensive process, needle tip finishing may also result in damage to the probe assembly itself.
Needle-type probes physically engage contact pads of the IC chips and thus present a likelihood that damage may be sustained by the pads such as by gouging during initial engagement. Further, unevenly applied pressures exerted against the engaged needles and pads may result in contact pressures being transmitted through the pads to the underlying wafer structure, resulting in damage thereto.
Another problem with needle-type probe assemblies is the degree of care, both in terms of time and skill, which must be exercised to ensure that the needles are properly connected to the probe assembly. Additionally, lower limits as to the degree of miniaturization possible in probe needle systems limit the utility of needle-type probes for testing high density IC chips. Further, at high frequencies (1 MHz or greater) it is difficult to control the characteristic impedance between the needles and the line conductors connecting the needles to external test equipment.
Another method for compensating for nonplanarization between devices to be electrically interconnected is to form metallic conducting buttons on one of two arrays of registered contact pads, as disclosed in U.S. Pat. Nos. 4,453,795 and 4,125,310. The registered arrays of contact pads are electrically interconnected by being forced together under pressure. Deviations in planarity among the contact pads are compensated for by corresponding deformations of the metallic buttons and deformation of a compression pad.
One disadvantage of these interconnects is that the contact pads and resilient metallic buttons are formed on rigid substrates. Since the substrates are forced together under pressure by means of external pressure plates, excessive forces may be transmitted by the metallic buttons against the unbuttoned contact pads to cause damage thereto or to the underlying rigid substrate. Additionally, plastic deformation of the metallic buttons can result in electrical discontinuities at the deformation sites, which in a probe system would result in the loss of parameter and/or performance information.