1. Field of the Invention
The present invention relates to high voltage vertical power transistors that are circuits vertically fabricated in a silicon wafer whose rear surface is connected to a high voltage. The invention is directed to MOS-type vertical power transistors or insulated-gate bipolar transistors (IGBT's), and more particuLarly applies to Smart Power switches, that are circuits including on a same silicon chip vertical power components and logic circuits for controlling such components.
2. Discussion of the Related Art
Power transistors are designed to withstand a predetermined forward voltage (for example, 400 volts). The application of a higher voltage to the circuit by the external circuit causes a breakdown of the device that can damage it. For example, the switching of an inductive load generates an overvoltage with a determined quantity of energy to be dissipated. Such over-voltage is applied to the power switch that is off, or is in a transient off state. One of the solutions to protect the transistor is to provide a signal onto its control electrode to briefly bring the transistor in a conductive state during a period long enough to dissipate the excess energy.
It is therefore desirable to provide a device that goes to conduction state for a value slightly lower than the breakdown voltage of the power transistor(s) in order to, for example, trigger the conduction of the transistors before their breakdown threshold, thus avoiding damage.
In the following description, power MOS transistors are always referred to. However, it is clear that the whole description also applies to IGBT's whose structure is substantially identical, except for the fact that they include on the side of the rear surface a layer having a conductivity opposite to the conductivity of the layer forming the rear surface of a power MOS transistor.
In order to better illustrate the problem that the invention aims at solving, FIG. 1 represents a cross-sectional view of an exemplary conventional dual structure including a vertical diffused MOS (VDMOS) transistor TP, two cells of which are represented. Such transistor is combined with logic circuits, including an N-channel MOS transistor TL of which is illustrated. The vertical MOS transistor is comprised of a large number, for example 10,000, of identical cells.
The structure is fabricated in a substrate O of a first conductivity type, for example of the N-type. A cell of the power MOS transistor TP includes a well 1 (1-1, 1-2) formed by a P-type diffusion in the substrate. In each well 1-1, 1-2 is formed an N.sup.+ -type annular diffusion region that constitutes an element of the power transistor source. Diffusions 2 are interconnected through a conductive layer 3 that is, for example, made of aluminum. The surface peripheral areas of regions 1 form a channel region 4 of the power transistor. Additionally, each well 1 generally includes a deeper and more highly doped central portion 5 (5-1, 5-2).
Each cell of the power MOS transistor TP includes a gate 6, formed above the surface peripheral areas by a polycrystalline silicon layer. Gate 6 is separated from substrate 1 by an oxide layer 7. All the gates 6 are interconnected.
The rear surface 10 of substrate 1 includes an highly doped layer 11 of the first conductivity type which is coated with a drain metallization 12.
The MOS transistor TL of the logic portion also includes a P-type well 14 region formed in the substrate. Well 14 includes two N.sup.+ -type areas, the first area forming source 15 and the second area forming the drain 16 of transistor TL. Transistor TL includes a gate 18 formed by a polycrystalline silicon layer above the well region. Gate 18 is separated from well 14 by an oxide layer 19. The diffused areas forming source 15 and drain 16 are connected to a conductive line labeled 20, 21, respectively. The conductive lines 20, 21 are for example of aluminum.
Conventionally, a P.sup.+ -type area 23 connected to a conductive layer 24 is also provided in well 14. Area 23 and the conductive layer 24 connect well 14 to ground.
Under normal operation, the metallization of the rear surface 12 is connected to a positive voltage, and the front surface metallizations 3 of the power transistor are connected to a voltage that is negative with respect to the positive voltage, for example, a voltage close to the ground voltage.
The problem to be solved is to avoid a switching on, due to breakdown, of the power transistor cells, i.e. due to an avalanche phenomenon of the junction between substrate O and the P-type wells of the transistor cells (1-1, 1-2, 5-2) when the drain voltage increases while the transistor is off. Such a switching on is undesirable because it may cause heating of this junction where the avalanche is generated due to excessive flow of current, and this heating can be destructive. It should be also noted, in the case of the represented integrated circuit including a logic portion, that an avalanche breakdown may occur at the junction between the substrate and the wells of the logic component cells. Conventionally, the structure is designed so that this latter junction breaks down after the junction of the power transistor cells.
An avalanche diode, having a triggering threshold lower than the threshold of the active cells of the power MOS transistor can be conventionally used, for example as illustrated in FIG. 2 which represents the power transistor TP with its drain terminal D (12), source terminal S (3) and gate terminal G (6). Transistor TP includes a reverse conduction diode 30 which corresponds to the junction between P-type well 5 and the N-type substrate 0 of the transistor TP. The reverse breakdown of this diode corresponds to the avalanche breakdown of the power transistor cell TP. An avalanche diode 31 can be connected between the drain and the gate and can be such that an avalanche voltage of diode 31 plus a forward voltage drop of a series diode 32 is less than the breakdown voltage of the power transistor and is therefore turned on before the power transistor enters the avalanche mode. The series diode 32 is used to avoid the derivation of normal gate control signals. The circuit of FIG. 2 is represented by way of example only because various alternative circuits for the triggering of a main transistor occurring after the triggering of a detection avalanche diode are known. It should be noted that, in most of these circuits, as illustrated in FIG. 2, the cathode of the avalanche diode is connected to the drain of the power transistor. This cathode or drain corresponds to the common terminal 12 of FIG. 1.
A different approach is described in the U.S. Pat. No. 5,136,349 in which each individual cell of a power MOS transistor is specifically designed so as to include a central avalanche diode that goes to avalanche mode shortly before the cells of the power transistor. Such structure has two drawbacks. The first drawback is that a new design of all the cells of a power MOS transistor is required, whereas, normally, the manufacturers of power MOS transistors have already developed optimized cells. This new design involves a major task that does not take advantage of prior developments already made by manufacturers. The second drawback is that major adjustment tasks are required to design the shape of the avalanche diode so that its triggering threshold is adequately determined with respect to the avalanche threshold of the power transistor cells.