1. Technical Field
The present invention relates generally to Digital-to-Analog circuitry and, more specifically, to a method and apparatus for a coarse Digital-to-Analog Converter architecture for voltage interpolation.
2. Introduction
A coarse Digital-to-Analog Converter (DAC) architecture is commonly used in mixed-mode systems requiring monotonicity, wherein the DAC acts as an interface to convert a digital code to an analog signal. For high resolution resistor string DACs, the resistor string is typically placed in several rows whereby the resistors of one row align with resistors of another row to form columns. In this design, each resistor is connected to a switch network through a resistor tap, and a binary-to-unary decoder is used to select switches to be closed such that the sub-DAC voltage comes from the resistor taps connected to the selected switches. The output voltage from each row is then fed into a multiplexer, wherein the multiplexer produces the coarse DAC output voltages. Conventional coarse DAC designs attempt to extend the resolution of differential resistor string DACs by feeding the multiplexer output voltages into a voltage interpolation amplifier.
One such resistor string DAC design includes an M-bit coarse DAC combined with an N-bit interpolation amplifier to achieve M+N bit total resolution, wherein the coarse DAC is used to generate two DAC voltages with a voltage difference of 2N*VLSB, the voltage difference across one resistor in a string of resistors in the coarse DAC circuit. This design includes a resistor string comprising 2M resistors, with two sets of switches connected to each resistor tap. Accordingly, the number of switches is equal to twice the number of resistors. For input data K, the Kth tap is connected to low output voltage VOL and the K+1th tap is connected to high output voltage VOH. Due to the large number of switches, this design requires a significant amount of circuit real estate and generates a significant glitch when changing data.