1. Field of the Invention
The present invention relates to an integrated circuit having protection from electrostatic discharge (ESD).
2. Description of the Prior Art
The protection of integrated circuits from electrostatic discharge has been a significant design issue, especially as transistor electrode dimensions shrink below the 1.5 micron level. An excessively high ESD voltage conducted from a package terminal to the integrated circuit bond pad can easily damage input or output circuitry, unless protection techniques are adopted. It appears that the use of the lightly-doped drain (LDD) structure and silicided source/drain regions has increased ESD susceptibility, especially in output buffers that utilize n-channel field effect transistors. One recent study by C. Duvvury and C. Diaz, "Dynamic Gate Coupling of NMOS for Efficient Output ESD Protection" Proceedings of the IRPS (1992), indicates that improved ESD performance can be obtained using a field oxide capacitor to couple the gate of the output transistor to the bond pad; see FIG. 6 therein. In that technique, the output transistor is made to carry the ESD current. However, the field oxide capacitor undesirably increases the capacitive lead on the bond pad, requiring a larger output transistor.
A somewhat similar prior-art technique is shown in FIG. 1, wherein an output buffer 10 is connected to the bond pad 11. A protective n-channel transistor 13 is connected to the bond pad for conducting ESD current (I) to the power supply conductor (V.sub.SS). The ESD voltage is conducted to the gate of transistor 13 by capacitor 12, typically about 10 picofarads in one design. This conduction tends to allow transistor 13 to conduct by means of bipolar break-down action during an ESD event, allowing the current I to flow. The resistor 14, typically about 2 kilohms, causes the positive charge on the gate of transistor 13 to be conducted to V.sub.SS, thereby turning transistor 13 off after the ESD event has dissipated. In this manner, transistor 13 does not conduct during normal operation of the output buffer. However, the circuitry of FIG. 1 requires that the protective transistor be sufficiently large so as to be able to carry the relatively large ESD current. This requirement increases the area required to implement the output buffer. In addition, the transistor 13 presents an additional capacitive lead to the buffer 10, which again undesirably requires that the buffer have additional drive capability, and hence increased size.
In some cases, protection against positive ESD voltages is improved by the presence of a p-channel output transistor. In that case, the p-n junction of the drain electrode, which is connected to the bond pad, provides for clamping positive ESD voltages to a power supply conductor. However, some designs use only n-channel output transistors. For example, TTL output buffers typically use n-channel transistors for both the pull-up and pull-down devices. More recently, the Standard Computer Systems Interface (SCSI) chips have output buffers that typically use only n-channel transistors. It is therefore desirable to have an improved ESD protection technique that is effective with output buffers, and which mitigates certain problems associated with the prior-art techniques.