The development of semiconductor memory technology is essentially driven by the requirement for increasing the performance of the semiconductor memories in conjunction with miniaturization of the feature sizes. However, further miniaturization of the semiconductor memory concepts based on storage capacitors may be difficult due to the large quantity of charge that is required for writing to and reading from the storage capacitors, which leads to a high current demand. Therefore, thought is increasingly being given to new cell concepts that are distinguished by a significantly lower quantity of charge for the writing and reading operation. Semiconductor memories having a resistance memory element that exhibits a bipolar switching behavior are one such new promising circuit architecture.
In order to provide maximum density of memory units, it is desirable to provide a cell field consisting of a plurality of memory cells, which are conventionally arranged in a matrix consisting of column and row supply lines, called also word and bit lines, respectively. The actual memory cell is usually positioned at the crosspoints of the supply lines that are made of electrically conductive material. The word and bit lines are each electrically connected with the memory cell via an upper or top electrode and a lower or bottom electrode. To perform a change of the information content in a particular memory cell at the addressed crosspoint, or to recall the content of the memory cell, the corresponding word and bit lines are selected either with a write current or with a read current. To this end, the word and bit lines are controlled by appropriate control means.
There are several memory cells that are able to fit into such memory cell arrangement.
For example, RAM (Random Access Memory) comprises a plurality of memory cells that are each equipped with a capacitor that is connected with a so-called selection transistor. By selectively applying a voltage at the corresponding selection transistor via the word and bit lines, it is possible to store electric charge as an information unit (bit) in the capacitor during a write process and to recall it again during a read process via the selection transistor. A RAM memory device is a memory with random access, i.e., data can be stored under any particular address and can be read out again under this address later.
Another kind of semiconductor memory is DRAM (Dynamic Random Access Memory), which comprises in general only one single, correspondingly controlled capacitive element, e.g., a trench capacitor, with the capacitance of which one bit each can be stored as charge. This charge, however, remains for a relatively short time only in a DRAM memory cell, so that a so-called “refresh” must be performed regularly, wherein the information content is written in the memory cell again.
Since it is intended to accommodate as many memory cells as possible in a RAM memory device, one has been trying to realize them as simple as possible and on the smallest possible space, i.e., to scale them. The previously employed memory concepts (floating gate memories such as flash and DRAM) will, due to their functioning that is based on the storing of charges, presumably meet with physical scaling limits within foreseeable time. Furthermore, in the case of the flash memory concept, the high switching voltages and the limited number of read and write cycles, and in the case of the DRAM memory concept the limited duration of the storage of the charge state, constitute additional problems.
The CBRAM (conductive bridging RAM) memory cell, also known as a programmable metallization cell (“PMC”), may be switched between different electric resistance values by bipolar electric pulsing. In the simplest embodiment, such an element may be switched between a very high (off resistance) and a distinctly lower (on resistance) resistance value by applying short current or voltage pulses. The switching rates may be less than a microsecond. Very high ratios of the off resistance (R(off)) to the on resistance (R(on)) are achieved in the case of the CBRAM cells, due to the very high-resistance state of the solid electrolyte material in the non-programmed state. Typical values are R(off)/R(on)>106 given R(off)>1010′Ω and an active cell area <1 μm2. At the same time, this technology is usually characterized by low switching voltages of less than 100 mV for initiating the erase operation and less than 300 mV for the write operation.
In structural terms, a CBRAM cell is a resistance memory element comprising an inert cathode electrode, a reactive anode electrode and a solid state electrolyte arranged between the cathode and anode. The term “solid state electrolyte,” as referred to herein, includes all solid state materials in which at least some ions can move under the influence of an electric field.
The surfaces of the chalcogenide material, usually provided in a CBRAM cell are deposited by means of sputtering methods, have an amorphous structure and frequently contain superfluous chalcogenides that are poorly bound so that these weakly bound chalcogenide atoms are conglomerated like clusters and cannot be removed, which leads to the formation of Ag-chalcogenide conglomerates or protrusion defects in the Ag doping and electrode layer, which usually is made of Ag. In addition, the etch process of noble metals is difficult as no etch chemistry exists for etching silver, for example. It is, thus, difficult to obtain a homogeneous, planar anode for the CBRAM cells using silver. Current approach is to simultaneously deposit silver together with the other metallic material in a co-sputtering process. However, the planarization and the structuring of the anode has to be done using a physical process.