Experimentally validated three dimensional GCT wafer level simulations
In this paper we present a wafer level three-dimensional simulation model of the Gate Commutated Thyristor (GCT) under inductive switching conditions. The simulations are validated by extensive experimental measurements. To the authors' knowledge such a complex simulation domain has not been used so far. This method allows the in depth study of large area devices such as GCTs, Gate Turn Off Thyristors (GTOs) and Phase Control Thyristors (PCTs). The model captures complex phenomena, such as current filamentation including subsequent failure, which allow us to predict the Maximum Controllable turn-off Current (MCC) and the Safe Operating Area (SOA) previously impossible using 2D distributed models.
We present two implementations of a view-independent cell projection algorithm for off-the-shelf programmable graphics hardware. Both implementations perform all computations for the projection and scan conversion of a set of tetrahedra on the graphics hardware and are therefore compatible with many of the hardware-accelerated optimizations for polygonal graphics, e.g., OpenGL vertex arrays and display lists. Apart from our actual implementations, we discuss potential improvements on future, more flexible graphics hardware and applications to interactive volume visualization of unstructured meshes.