A fast and accurate statistical method that estimates at gate level the leakage power consumption of CMOS digital circuits is demonstrated. Means, variances and correlations of logic gate leakages are extracted at library characterization step, and used for subsequent circuit statistical computation. In this paper, the methodology is applied to an eleven thousand cells ST test IP. The circuit leakage analysis computation time is 400 times faster than a single fast-Spice corner analysis, while providing coherent results.
Due to the effects of the Moore's law, the process variations in current technologies are increasing and have a major impact on power and performance which results in parametric yield loss. Due to this, process variability and the difficulty of modeling accurately transistor behavior impede the dimensions scaling benefits. The Fully Depleted Silicon-On- Insulator (FDSOI) technology is one of the main contenders for deep submicron devices as they can operate at low voltage with superior energy efficiency compared with bulk CMOS. In this paper, we study the static energy on 28nm FDSOI devices to implement sub-threshold circuits. Study of delay vs. static power trade-off reveals the FDSOI robustness with respect to process variations.
Berzelius failed to make use of Faraday's electrochemical laws in his laborious determination of equivalent weights.