The Effect of SOA Enhancement on Device Ruggedness Under UIS for the LDMOSFET
This paper presents a unified study on the relationship between safe operating area (SOA) enhancement and unclamped inductive switching (UIS) behavior in an LDMOS. Popularized methods of SOA enhancement techniques are implemented, including a highly doped p+ bottom layer, n-adaptive layer, and drift extension. The effect that each enhancement has on SOA is first analyzed and shown, followed by the impact that it has on device ruggedness as measured through the UIS test. The energy absorbed during UIS, time in avalanche, and peak lattice temperature are each considered in evaluating ruggedness. Off-state breakdown voltages and on -resistances are also analyzed. The results indicate varying behavior during UIS, depending on each SOA enhancement technique used.
We present a physical, predictive and efficient model (BSIM3) for deep-submicrometer MOSFETs with emphasis on both digital and analog applications. BSIM3 can also be suitable for statistical modeling.