Circuit level interconnect reliability study using 3D circuit model
Integrated circuit (IC) reliability is gaining increasing concerns in IC technology with decreasing device size, and the impact of interconnect failure mechanisms on IC failure rate increases significantly with decreasing interconnect dimension and increasing number of interconnect levels. In this work, we attempt a first step in the study of interconnect electromigration reliability in integrated circuit using a complete 3D circuit model. 3D circuit model is necessary because all integrated circuits are 3D in their actual physical implementation, and 3D model is essential for the study of today interconnect reliability. As temperature and stress distributions in the interconnect are crucial to its reliability, we demonstrate our method through the computation of their distributions in a simple inverter circuit under typical normal operating condition, and the locations of the electromigration weak spots in the interconnect system are identified.
Surface reconstruction from point cloud is of great practical importance in computer graphics. Existing methods often realize reconstruction via a few phases with respective goals, whose integration may not give an optimal solution. In this paper, to avoid the inherent limitations of multi-phase processing in the prior art, we propose a unified framework that treats geometry and connectivity construction as one joint optimization problem. The framework is based on dictionary learning in which the dictionary consists of the vertices of the reconstructed triangular mesh and the sparse coding matrix encodes the connectivity of the mesh. The dictionary learning is formulated as a constrained e2,q-optimization (0