In this paper, we propose a novel approach to on-chip cooling by thermionic emission by using vertical superlattices fabricated directly into the silicon wafer as opposed to conventional planar additive deposition methods used by most other groups. The advantages of this method are (i) significantly lower fabrication costs and (ii) adequate number of superlattice layers translating to higher efficiency. Initial fabrication has been completed on micro-scale ‘superlattices’ and work on ‘nano’-superlattices for actual thermionic emission and on-chip cooling are on-going. Measurements of thermal conductivity have been proposed to be made on the completed devices using the 2ω method. Further work will lead to conclusive results from this approach.
A three-dimensional heat conduction model is presented, coupled with a frequency-domain thermoreflectance measuring bench. The combination of these tools makes it possible to determine the thermal properties of thin film materials deposited on thick substrates, for a wide range of thermal conductivity and diffusivity. We give an example of experimental determination of the properties of a gold layer, the results of which are compared to the literature. We then present a sensitivity study using simulations for a 200 nm thin layer of polylactic acid, deposited on a silicone substrate and covered by 100 nm of gold.
Berzelius failed to make use of Faraday's electrochemical laws in his laborious determination of equivalent weights.