Complexity Analysis of Reversible Logic Synthesis
Reversible logic circuit is a necessary construction for achieving ultra low power dissipation as well as for prominent post-CMOS computing technologies such as Quantum computing. Consequently automatic synthesis of a Boolean function using elementary reversible logic gates has received significant research attention in recent times, creating the domain of reversible logic synthesis. In this paper, we study the complexity of reversible logic synthesis. The problem is separately studied for bounded-ancilla and ancilla-free optimal synthesis approaches. The computational complexity for both cases are linked to known/presumed hard problems. Finally, experiments are performed with a shortest-path based reversible logic synthesis approach and a (0-1) ILP-based formulation.
We present a novel approach to the synchronization problem. It is a well-known fact that a problem of finding minimal (or: the shortest) synchronizing word (MSW) for a given synchronizing automaton is NP-complete. In this paper we present the genetic algorithm which tries, for a given automaton, to find possibly short word that synchronizes it. We use a modified version of a classical simple genetic algorithm (SGA).