The author addresses the effect on the performance of the DTTL (data transition tracking loop) symbol synchronizer of the signal transition variation due to signal transition density, data asymmetry, and sinusoidal modulation. It is shown that the combination of these factors will indeed affect the DTTL performance, e.g. clock jitter and cycle slippage rate, and that worst-case performance may result if the parameters are not well selected. Typical numerical results are shown. >
Bit synchronization in the presence of asymmetric channel noise has not appeared in the open literature. It is the purpose of this paper to study the tracking performance (clock jitter and cycle slip rate) of a popular digital clock synchronizer, the digital data transition tracking loop (DTTL), in the presence of asymmetric noise. Related parameters of interest, the transition density and data asymmetry, are also included. Acquisition performance (frequency acquisition time) is discussed in the absence of noise. A comparison of the DTTL and crossspectrum synchronization loop (CSSL) is also provided. Numerical results are Presented for the design of a bit synchronizer in this environment.
We prove that groups acting geometrically on delta-quasiconvex spaces contain no essential Baumslag-Solitar quotients as subgroups. This implies that they are translation discrete, meaning that the translation numbers of their nontorsion elements are bounded away from zero.