revision preference src: Instructions 4, 5, and 6 are independent of instructions 1, 2, and 3, but the processor cannot finish 4 until 3 is done, because 3 would then write the wrong value. <SEP> tgt: The instructions in the final three lines are independent of the first three instructions, but the processor cannot finish r1 ≔ m2048 until the preceding m1032 ≔ r1 is done (doing so otherwise would write a wrong value).