1. A method of test pattern generation for an integrated circuit (IC) design simulation system, comprising: merging at least two test vectors into a merged vector, wherein each test vector defines a set of test behaviors; and compiling and linking the merged vector to generate a merged test pattern able to perform each set of test behaviors independently, wherein each test vector comprises a test configuration; wherein merging the at least two test vectors into a merged vector comprises: comparing test configurations for similarity, and extracting configuration constituents comprising all test configurations into a common configuration; combining differences between each test vector and the common configuration into a behavior vector; and combining the common configuration and all behavior vectors into the merged vector using a predetermined format.