1. A method, executed by at least one processor of a computer, for speed-path debug comprising: receiving test failure information, the test failure information identifying one or more failing scan cells and a scan test pattern associated with the one or more failing scan cells; selecting a failing scan cell from the one or more failing scan cells; and identifying suspect speed paths for the failing scan cell based on X-simulation, the X-simulation comprising: identifying one or more transition supporting scan cells, the one or more transition supporting scan cells being supporting scan cells that make a transition at a first cycle capture of the two-cycle at-speed scan test pattern; changing values of the first cycle capture for the one or more transition supporting scan cells to “X” values; and propagating the “X” values.