1. A method of optimizing a model of a logic circuit in a simulation, comprising the steps of: providing a data flow graph (DFG) representing a logic circuit; identifying a mergeable cluster in said DFG; said mergeable cluster having inputs and an output; calculating an upper bound on a information content of said output; reducing bitwidths of data flow paths of said DFG responsively to said step of calculating; identifying further mergeable clusters in said DFG responsively to said step of reducing.