1. A method for placement of a plurality of cells of a user design on an integrated circuit (IC), the method comprising: building a set of timing constraints for placement of the plurality of cells on a plurality of sites on the IC; with a placer, sending the set of timing constraints to a satisfiability solver; with the placer, receiving a placement that satisfies the set of timing constraints for the plurality of cells from the satisfiability solver; and configuring the integrated circuit with configuration data that includes the placement that satisfies the set of timing constraints.