1. A computer-implemented method for design analysis comprising: modeling a semiconductor circuit, using a set of constraints for the semiconductor circuit wherein one or more constraints from the set of constraints is defined over one or more variables, as part of a test bench wherein the test bench is modeled as a random process; solving, using one or more processors, the set of constraints by generating random values for the one or more variables within the test bench to provide stimulus to the semiconductor circuit; using a subset of the one or more variables to determine a structure for a first constraint problem related to the semiconductor circuit; monitoring information content for the subset of the one or more variables related to the semiconductor circuit; evaluating changes in the information content for the subset of the one or more variables related to the semiconductor circuit; caching into problem storage, the first constraint problem along with the information content for the subset of the one or more variables related to the semiconductor circuit, based on the changes in the information content; iterating to a second constraint problem with a second subset of the set of constraints and a second subset of the one or more variables related to the semiconductor circuit; searching through the problem storage to identify a previously cached constraint problem which matches the second constraint problem related to the semiconductor circuit; retrieving from the problem storage a structure corresponding to the second constraint problem to be solved related to the semiconductor circuit; solving the second constraint problem related to the semiconductor circuit based on the structure that was retrieved; and generating a stimulus for the semiconductor circuit based on the solving of the second constraint problem.