1. A method of designing, including floorplanning functions for, an integrated circuit, comprising the steps of: designing an integrated circuit, including a plurality of interconnected functions, each function requiring a first area and a plurality of interconnected functions, each function requiring a first area and a plurality of I/O points, each I/O point requiring a second area; selecting a die having a die size, die area and die shape; performing a floorplanning process whereby portions of the die area are successively partitioned by a partitioning process into progressively smaller groups of two or more sub-partitions, each portion of the die area having a partition area and each sub-partition having a sub-partition area; assigning functions to the sub-partitions such that each assignment of functions to the sub-partitions results in a number of connections between interconnected functions crossing from one sub-partition area into another sub-partition area, said crossings of connections between the sub-partition areas being "partition boundary crossings"; and determining a partition cost factor (PCF) according to the equation: ##EQU8## where A.sub.f is a sum of the first areas of all d the functions assigned to all of the sub-partitions in a first group of sub-partitions, A.sub.f1 is a sum of the first areas of all of the functions assigned to a first sub-partition in the first group, A.sub.f2 is the sum of the areas of all of the functions assigned to a second sub-partition in the group, `m` is the number of sub-partitions in the first group, A.sub.f'm' is the sum of the areas of all of the functions assigned to the `m`.sup.th sub-partition in the first group, A.sub.p1 is the sub-partition area of the first sub-partition, A.sub.p2 is the sub-partition area of the second sub-partition, A.sub.p'm' is the sub-partition area of the `m`.sup.th sub-partition, A.sub.D is the partition area for the portion of the die areas which has been partitioned into the first group of sub-partitions, PBC is the number of partition boundary crossings, SF.sub.1 is a partition-balance scale factor, and SF.sub.2 is a partition boundary crossing scale factor; wherein said floorplanning process is based on the PCF resulting in a layout for the die of the integrated circuit.