1. A method to automatically synthesize a custom integrated circuit, comprising: receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; encoding architecture level knowledge in a data model to generate and pass new constraints for physical synthesis of a chip specification uniquely customized to the computer readable code; iteratively generating a custom architecture unique to the computer readable code; receiving a look-ahead cost function during architecture optimization consistent with cost observed later in the flow after detailed physical synthesis is performed, wherein the look-ahead cost function is generated from a prior iteration and supplied to a subsequent iteration through the data model; automatically translating information available at one optimization point into a constraint for another optimization point invoked at a different place in the design flow using the data model; applying pre and post fix tags to indicate if the grouping of cells in a hierarchy is a hard or soft constraint synthesizing a computer readable description of the chip specification into the custom integrated circuit for semiconductor fabrication; and performing iteratively physical synthesis of the chip specification and updates the data model of the chip specification in each iteration until the constraints are satisfied, wherein the information generated from a prior iteration is provide as feedback loops.