1. A computer-readable recording medium stores therein a verification support program that causes a computer to execute: receiving a hardware description of a sequential circuit to be verified and a timing specification that indicates a timing constraint in the hardware description; converting the hardware description into a control flow graph that expresses a flow of control in the sequential circuit; indentifying, from the control flow graph and as a combination of conditional branch descriptions having a hierarchical relation, conditional branch descriptions that are connected in parallel; extracting, from among combinations of conditional branch descriptions identified at the identifying, a combination having a potential to satisfy specified conditions; creating a simulation program that, at a timing satisfying the timing specification received at the receiving, causes the conditional branch descriptions included in the combination extracted at the extracting to satisfy the specified conditions; and outputting, as assertion information of the sequential circuit, the simulation program created at the creating.