1. A method, comprising: extracting multiple-patterning group assignment information of one or more layout patterns from a layout design, the layout design corresponding to a circuit design, and the one or more layout patterns corresponding to a node of the circuit design, wherein the circuit design is accessible in a form of a netlist file; determining, by a hardware processor, if the extracted multiple-patterning group assignment information is consistent with a set of multiple-patterning group assignment constraints of the node; and extracting the set of multiple-patterning group assignment constraints from a modified netlist file, the modified netlist file comprising a first portion having contents of the netlist file and a second portion having the set of multiple-patterning group assignment constraints.