1. A method of obtaining a physical design of an integrated circuit from a logical design, the method comprising: performing, with a processing device, a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget; computing power assertions; performing a re-synthesis using the timing constraints and the power assertions to obtain a new physical design; comparing the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design wherein the comparing includes determining a baseline quality of result (QOR) for the baseline physical design and a new QOR for the new physical design and using a difference between the baseline QOR and the new QOR as a measure of the degradation; reducing a weighting of the power assertions relative to the timing constraints based on the degradation; and iteratively executing the performing the re-synthesis, the comparing, and the reducing until the degradation is below a threshold value.