1. A method for designing an integrated circuit comprising: partitioning a design into a plurality of function blocks; designing a first one of said plurality of function blocks employing Verilog to produce a first block design; designing a second one of said plurality of function blocks employing SPICE to produce a second block design; converting said first block design to SPICE to produce a converted first block design; simulating operation of said converted first block design and said second block design; and translating said converted first block design to Verilog to produce a translated first block design.