1. A computer-implemented method for identifying the best process path in a semiconductor manufacturing process for processing a plurality of wafer lots, comprising: providing a plurality of operations in the semiconductor manufacturing process; providing a plurality of tools in at least one of the plurality of operations; providing a plurality of process paths; providing a plurality of lot yields corresponding to the plurality of wafer lots; setting the plurality of lot yields as responses; setting the plurality of operations as control factors; setting the plurality of tools as factor levels in response to at least one of the plurality of operations; determining at least one of the plurality of operations by using an analysis of variance method with the responses, control factors, and factor levels; determining a best tool for the one of the plurality of operations having the most influence by retrieving a maximum statistical characteristic; and outputting at least one best process path from the plurality of process paths, where in the at least one best process path includes the best tool.