1. A computer-supported, automated method for the verification of analog circuits ( 1 ), said method comprising the steps of: transforming of constants or variables (A1, x1), respectively, characterizing a first equation system for describing the properties of a circuit; transforming of constants or variables (A2, x2), respectively, characterizing a second equation system for describing the properties of a circuit; performing a circuit equivalence test by using the transformed quantities (z) obtained from transforming.