1. A processor with an instruction class controllable pipeline comprising: an adaptable decode stage that decodes in a first time period an instruction received from an instruction register, stores the decoded instruction in a decode register, and generates an instruction class indication that identifies the decoded instruction as a first class instruction or as a second class instruction; an adaptable execution stage that executes an identified first class instruction in a first class execution logic circuit or executes an identified second class instruction in a second class execution logic circuit in response to the instruction class indication, wherein the first class execution logic circuit has a worst-case signal propagation time that is less than or equal to a first class time period and the second class execution logic circuit has a worst-case signal propagation time that is greater than the first class time period and assigned to a second class time period; and an adaptable pipeline control unit responsive to the instruction class indication for an identified second class instruction to select the second class execution logic circuit and to hold the decoded instruction in the decode register until the first time period plus a second time period is equal to the second class time period, wherein stages of the class controllable pipeline advance at a rate that allows the identified second class instruction to complete operations in the adaptable execution stage.