1. A computer system comprising: a processor; a memory device; a cache connected to said processor and said memory device, having a plurality of cache blocks for storing memory blocks corresponding to addresses of said memory device; program instructions residing in said memory device and executed by said processor, for selecting an associativity level among a plurality of associativity levels to assign said addresses to said cache blocks according to a respective one of a plurality of mapping functions for a selected associativity level, said program instructions dynamically monitoring cache misses as the cache operates with different associativity levels, and the selected associativity level dynamically changing among the different associativity levels based on said cache misses; and application software containing the program instructions, the application software having procedures resulting in strides at particular association levels, and the known appropriate level being chosen to lessen memory latencies due to strides.