1. A method for optimizing a circuit design, the method comprising: evaluating, by computer, a first candidate gate from a library of gates as a replacement for a gate that is being optimized, wherein said evaluating involves computing one or more timing metrics based on the first candidate gate; responsive to rejecting the first candidate gate based on said evaluating, storing one or more parameter values of the first candidate gate; determining whether a second candidate gate from the library of gates degrades the one or more timing metrics by comparing one or more corresponding parameter values of the second candidate gate with the one or more stored parameter values; and rejecting the second candidate gate based on said determining.