1. A method, executed by at least one processor of a computer, for improving the manufacturing yield of integrated circuit comprising the steps: receiving a plurality of integrated circuit layout elements; constructing and allocating a plurality of position variables to a plurality of layout elements, wherein position variables represent locations of edges or points of the plurality of layout elements; constructing a constraint system using the positional variables, wherein the constraints represent relationships among edges or points of the plurality of layout elements; constructing a fabrication process compliance analysis undesirability function with inputs consisting of position variables; establishing an objective function composed of fabrication process compliance analysis undesirability function and weighted sum of plurality of position variables; solving an optimization problem of minimizing the objective function subject to the constraint system requirements; and generating new layout from the new position variable values.