1. A method of testing a circuit design, comprising: generating a simulation model of said circuit design, said circuit design comprising one or more source latches, one or more destination latches and a logic function connected between said source latches and said destination latches; generating a modified simulation model of said simulation model by inserting random skew between an output of each source latch and an input of said logic function only in asynchronous data paths between said source latches and said destination latches of said simulation model; and running said modified simulation model.