1. A computing system, comprising a multi-core processor that includes a plurality of processor cores, each of the plurality of processor cores comprising a predicate predictor, wherein at least one predicate predictor is configured to predict an output of a predicate instruction mapped to a corresponding processing core of the plurality of processing cores, wherein the predicate instruction is generated from a branch instruction that is included in a block of instructions, wherein the block of instructions includes a block address that determines which processing core of the plurality of processing cores are assigned to execute the branch instruction, wherein the prediction is based on information encoded in the branch instruction, and wherein the information encoded in the branch instruction represents at least a portion of a predicate path or an approximation of a predicate path.