1. A method for verifying a logical equivalence of a plurality of circuits, the method comprising: receiving one or more inputs at a threshold logic gate implementing a threshold function F=[W;T], where W is a set of input weights, W=(w 1 , w 2 ,. .. , w n ), X is a set of n binary inputs to said threshold logic gate, X={x 1 , x 2 ,. .. , x n }, and T is a threshold value of said threshold logic gate; recursively decomposing said threshold function F into a first function F 1 and a second function F 2 using cofactors of said threshold function F; generating a Boolean function representation of said threshold logic gate based on said recursive decomposition of said threshold function F; and verifying said logical equivalence of said threshold logic gate with one or more other logic circuits based on said generated Boolean function representation of said threshold logic gate, wherein said method is executed by one or more circuits in a computer.