1. A method for selectively optimizing a circuit design for physical implementation comprising: (a) generating a circuit routing solution, by a processor, in accordance with a plurality of constraints for parametric resources of the circuit design, said constraints being defined respectively by a plurality of corresponding constraint instances, each said constraint instance variably indicating a constraining limit and degree of resource consumption for at least one of said parametric resources; (b) selectively adjusting, by a processor, at least one of said constraints by an over-constraining amount; (c) preliminarily modifying, by a processor, said circuit routing solution by applying at least one routing action selected responsive to said constraint adjustment; (d) evaluating potential impact upon constraint compliance, by a processor, said evaluation including generating a relative cost measure for said preliminary modification of said circuit routing solution, based at least partially upon each of said constraint instances; (e) alternatively discarding or accepting, by a processor, said preliminary modification of said circuit routing solution responsive to said evaluation, whereby acceptance of said preliminary modification is conditioned upon measurable validation of favorable constraint compliance impact associated therewith; and, (f) optionally repeating (b)-(e) in recursive manner.