1. A method for executing a multithreaded algorithm to perform a static timing analysis of a chip, comprising: traversing the chip to identify a plurality of components within a logic circuit of the chip, each of the plurality of components including a plurality of nodes; defining a waveform graph for the plurality of nodes; generating a first and a second virtual graph from the waveform graph; assigning the first virtual graph for running an early mode propagation; assigning the second virtual graph for running a late mode propagation; processing the plurality of nodes in the first and the second virtual graphs independently using a first and a second thread to compute arrival time domain dataset values at each of the plurality of nodes; performing a timing check at end point nodes in each of the first and the second virtual graphs using the time domain dataset values to determine any timing violations within the chip circuit; and processing the plurality of nodes in the first and the second virtual graphs independently using a third and a fourth thread to compute required time domain dataset values at each of the plurality of nodes.