1. A computer-implemented method of performing physical synthesis in a chip design process using hierarchical wire-pin co-optimization, the method comprising: providing, using a processor implementing a unit level controller, an indication of candidate pins among a plurality of pins of a plurality of macros, the candidate pins being permitted to be moved and the plurality of macros being part of a unit that includes the unit level controller such that the unit is at a higher hierarchical level than the plurality of macros; providing, using the processor implementing the unit level controller, constraints on a range of movement of one or more of the plurality of pins; and performing macro-level physical synthesis at each of the plurality of macros based on the candidate pins and the constraints provided by the unit level controller to generate pin locations and timing results, wherein the chip design resulting from the physical synthesis is used to fabricate an integrated circuit or cause the integrated circuit to be fabricated.