1. A method for performing a hierarchical timing analysis and closure of an integrated circuit (IC) chip design component using load-sensitive feedback constraints, the method comprising: a) obtaining at least one original feedback constraint, a base load representation, and a sensitivity of said at least one original feedback constraint to said base load representation for one or more boundary pins of said component; b) performing an out-of-context timing analysis and closure of said component wherein an electrical parasitic of said one or more boundary pin is updated as part of said timing closure; c) obtaining an updated value of said load representation of said one or more boundary pin that accounts said electrical parasitic updates; d) computing an updated feedback constraint of said one or more boundary pin based on said one or more original feedback constraint, said base load representation, said sensitivity, and said updated value of the load representation; and e) employing said computed updated feedback assertion to perform a new timing analysis of said component as part of timing closure of the said chip design prior to chip manufacturing.