1. An encoding system including a processor and a memory for encoding an event time series, the system comprising: a processor, and a memory, the memory storing instructions to cause the processor to: compute, using said processor, an inter-arrival time between each of a plurality of input events and computes a sequence of events; transform, using said processor, each of the inter-arrival times between the plurality of input events into discrete time symbols by quantizing the time symbols between two events, each discrete time symbol representing one inter-arrival time of the computed inter-arrival times between two of the input events; and map, using said processor, the input events and the discrete time symbols using a dictionary to output a time gram, wherein the mapping introduces symbol sets and grammar rules to group the plurality of input events together that have a predetermined threshold inter-arrival time and also maps a sequence of events with the inter-arrival times for recognized out of sequence patterns between the inter-arrival times between the plurality of input events.