1. A method of partitioning portions of a circuit design for an electronic design automation process, comprising: generating one or more initial clusters of nodes from the circuit design by employing a computing system identify one or more critical paths in the circuit design that do not meet specified timing requirements, select one or more nodes in the critical paths that have timing violations, and grow the initial clusters of nodes from the selected nodes, wherein each initial cluster of nodes includes at least one node having a timing violation exceeding a threshold value and having a logical connection to at least another node in the initial cluster of nodes; employing a computing system to create one or more final clusters of nodes from the initial clusters of nodes based upon processing weight values for processing the final clusters of nodes according to the electronic design automation process; and employing a computing system to partition the circuit design according to the final clusters of nodes.