1. A computer-implemented method for performing formal verification of a circuit in view of low power design specification, the method comprising: receiving a request to perform formal verification of connectivity of a circuit representing an input/output ring of a system on chip, the formal verification based on a set of assertions associated with the circuit; receiving low power design specification for the circuit, the low power design specification describing power states for one or more power domains of the circuit; modifying the circuit design by introducing one or more isolation cells based on the low power design specification; generating combinational constraints based on the low power design specification, the combinational constraints representing valid power states of power domains of the circuit based on the low power design specification; performing formal verification of the modified circuit based on the set of assertions and the combinational constraints based on low power design specification; and determining whether the circuit has valid connectivity in view of the low power design specification based on the result of the formal verification.