1. A method of simulating the operation of an electronic logic circuit having a multiplicity of logic gates, said method comprising the steps of: (A) receiving and storing in a computer memory a netlist denoting said logic circuit's components and nodes interconnecting said components; each said component of said logic circuit having at least one input port and at least one output port, said nodes including circuit input nodes and circuit output nodes for said logic circuit; (B) receiving cell delay data representing signal delays associated with said components in said logic circuit; said delay data for each component representing signal delays from each input port to each output port of said component; (C) receiving and storing in said computer memory input signal waveforms for input signals applied to said circuit input nodes; (D) parsing said input signal waveforms into a sequence of variable length time periods in accordance with predefined criteria; (E) identifying a set of said logic circuit's nodes as watched nodes; (F) for each said time period, initially simulating operation of said logic circuit without determining when signal transitions on said circuit's nodes occur, said initial simulation step including assigning each signal on each node in said logic circuit an extended boolean value selected from the set consisting of stable signal values (0, 1, x and z), and non-stable signal values, said non-stable signal values including signal values (t0, t1, tx, tz) having a single transition during said time period, and a multiple transition signal value (mt) indicating more than one transition during said time period; said initial simulation stem including evaluating outputs of said logic circuit's components using predefined extended boolean truth tables wherein for each of at least a plurality of said predefined extended boolean truth tables, said each predefined extended logic table specifies at least stable output, having one of said stable signal values, corresponding to a set of input signals that include at least one input signal having one of said non-stable signal values and at least one input signal having one of said stable signal values; and (G) for each said time period, backtracking through said logic circuit for each respective watched node assigned a non-stable value so as to identify nodes that control said respective watched node and that were assigned non-stable signal values, and then performing event driven simulation of said logic circuit for signal transition events on said identified nodes; said steps F and G generating simulated waveforms representing signal values on said watched nodes over a defined period of time.