1. A method implemented by computer, for selecting representative paths for the analysis of the behavior of an integrated circuit according to a predefined analysis strategy, comprising the identification of the set of paths of said integrated circuit having logic gates and the construction of a list of the set of said paths, the method further comprising the following steps: the selection of several criteria related to the behavior of said integrated circuit, said several criteria being chosen from among the following types: topology, usage, sensitivity, environment, criticality; the determination of values of the selected criteria for each of said identified paths; the application of a correlation function so as to aggregate the set of said values of criteria in such a way as to define for each of said paths, an aggregation criterion value; and the selection of a subset of representative paths from among the list of the set of said paths, as a function of the value of the aggregation criterion of each of said paths and of the predefined analysis strategy.