1. In an ECAD system, a method of creating and validating a structural description of an electronic system from a higher level, behavior-oriented description thereof, comprising: entering on an ECAD system a specification for a design of desired behavior of an electronic system, including high-level timing goals, in a high-level, behavior-oriented language; on the ECAD system, iteratively simulating and changing the design of the electronic system at the behavioral-level until the desired behavior is obtained; on the ECAD system, displaying the design of at least a portion the electronic system as a plurality of graphical objects forming a schematic diagram and simultaneously displaying simulation data on the schematic diagram adjacent to graphical objects to which the simulation data applies; on the ECAD system, partitioning the design of the device into a number of architectural blocks and constraining the architectural choices to those which meet the high-level timing goals; and on the ECAD system, directing the various architectural blocks to logic synthesis programs, said logic synthesis programs also running in the ECAD system, thereby providing a netlist or gate-level description of the design.