1. A method for automatic design of an electronic circuit, comprising using a computer for performing steps of: generating a layout of said electronic circuit; generating abstract data at the substrate level associated to the layout of said electronic circuit; generating a grid of subdivision into meshes and nodes with respect to a view pertaining to said abstract data and applying it to a substrate; extracting, on the basis of said subdivision grid, a full electrical netlist pertaining to the substrate; performing an evaluation of the interactions between devices of said electronic circuit at the substrate level according to said full electrical netlist pertaining to the substrate; subdividing the devices of the electronic circuit according to a plurality of layers; applying said subdivision grid to each layer; for each layer, analyzing grid elements obtained from the subdivision operation; and calculating electrical parameters to be associated to said grid element according to a technology-configuration file pertaining to the analyzed grid element.