1. A method for verification of an integrated circuit design, the method comprising: independently executing a plurality of simulation runs in response to a plurality of coverage models to respectively generate a plurality of coverage data for a plurality of functional blocks within one or more integrated circuit designs; generating a target coverage model to selectively merge at least first coverage data associated with a first coverage model and at least second coverage data associated with a second coverage model; in response to the target coverage model and the plurality of simulation runs, selectively projecting the plurality of coverage data into a merged coverage data result associated with the target coverage model; and wherein one or more of the independent execution, the generating, and the selective projecting are automatically performed with a processor.