1. A method of reducing the number of hold violations in an integrated circuit, the method comprising: determining at least one segment of the circuit, wherein each segment is a connection between a plurality of circuit nodes; associating at least one timing path with each segment, wherein each timing path is a connection of circuit nodes, including a starting point node and an endpoint node, that covers one or more segments; determining a weight for each segment, wherein the weight is determined by a number of timing paths associated with the segment; ranking each segment based upon the determined weight associated with the segment; and employing at least one processor in inserting a delay buffer at least one of the segments based upon said ranking.