1. A system for address-event-representation network simulation comprising: a hardware structure comprised of a plurality of interconnected processing modules configured to simulate a plurality of interconnected nodes, wherein each node comprises: a source table configured to receive an input message and identify a weight associated with a source of the input message; state management logic configured to update a node state as a function of the identified weight, and generate an output signal responsive to the updated node state; and a target table configured to generate an output message in response to the output signal, identify a target to receive the output message, and transmit the output message.