1. A method for analyzing a design for an integrated circuit to identify violations of a specification window, the method comprising: generating a SPICE deck that defines the design; generating a pseudo-random sample set of input conditions; simulating the design to produce an output set of responses correlated to the sample set of input conditions; fitting a mathematical model to the output set, the model representing a behavior of the design; defining a set of desirability functions to an out-of-spec condition, the desirability functions are set based on an analysis of the output set; and searching the model using the desirability functions to identify a worst-case data point, wherein the method operations are executed on a processor.