1. A delay analysis apparatus comprising: a CPU; an extracting unit configured to extract a predetermined destination from among destinations obtained by testing a circuit, the destinations being sites at which a delay signal is captured in the circuit; a tracing unit configured to trace an output branch point on a path that leads to the predetermined destination, by tracing back from the predetermined destination; a determining unit configured to determine an estimated failure site in the circuit based on the traced output branch point; and an output unit configured to output a result of determination by the determining unit.