1. A computer implemented method for determining the failure rate of an integrated circuit, said method comprising: partitioning said circuit into a plurality of cells; computing a default failure in time (FIT) rate of each of said plurality of cells assuming a default input signal; identifying a plurality of overshoot cells that experience overshoots exceeding said default input signal during operation of said integrated circuit, wherein said plurality of overshoot cells are comprised in said plurality of cells; computing an exact FIT rate for each of said plurality of overshoot cells; and determining said failure rate of said integrated circuit based on said default FIT rate and said exact FIT rate.