1. A computer implemented front-end design methodology for designing an electronic design, the methodology comprising: storing a library of logic structures each having performance data for each of a plurality of different physical implementations of the logic structures; partitioning the electronic design into a number of partitions, at least one partition associated with at least one of the logic structures from the library; for each partition of the electronic design, modeling the performance of each of the plurality of physical implementations of the partition from the performance data of the logic structures included in the partition; and globally and locally optimizing the electronic design and the number of partitions using placement based wire load data to define a set of design constraints that enables the electronic design to be implemented to meet timing requirements associated with the electronic design in a single pass through a back-end process.