1. A computer-implemented method, comprising: receiving a program representative of a hardware design of one or more functions; producing a hardware representation of the hardware design by running the received program through a compilation process that comprises multiple stages, wherein the hardware representation of the hardware design is subject to one or more constraints, wherein said producing the hardware representation of the hardware design comprises: collecting information relating to characteristics of the hardware design throughout the compilation process, wherein the characteristics of the hardware design include timing path information of the hardware design, and wherein the hardware representation of the hardware design does not meet at least one of the one or more constraints; and performing, until the one or more constraints are met: automatically adjusting one or more stages of the compilation process prior to completion of the compilation process, based on the collected information via a programming interface, including automatically adjusting timing path implementation decisions, thereby adjusting the compilation process, including: producing a timing report resulting from the compilation process, wherein the timing report comprises one or more failed timing constraint paths; and adding one or more registers along at least one of the one or more failed timing constraint paths in response to receiving input instructions via the programming interface, in order to improve the timing paths; and performing said producing via the adjusted compilation process; wherein said automatically adjusting one or more stages of the compilation process comprises: comparing the timing report with a prior timing report obtained from a previous compilation process performed on the received program, said comparing comprising: parsing the one or more failed timing constraint paths in the timing report; and comparing timing delays comprised in the failed timing constraint paths to timing delays comprised in corresponding timing constraint paths in the prior timing report; and adjusting timing paths in the hardware design according to results of the comparison of the timing report with the prior timing report, wherein said adjusting comprises: finding a longest preexisting component delay from the failed timing constraint paths; and adding a register in a timing path corresponding to the found delay.