1. A method of implementing a circuit design for an integrated circuit (IC), comprising: on at least one programmed processor, performing operations including: processing a description of the circuit design having logic elements into a graph having nodes representing the logic elements and edges representing potential pairs of the logic elements; determining a packing of pairs of the nodes to divide the graph into selected nodes and unselected nodes and selected edges and unselected edges by performing iterations of: identifying an augmenting path in the graph between a pair of unselected nodes; and modifying the selected nodes and unselected nodes and the selected edges and unselected edges based on the augmenting path; and grouping the logic elements in the description into pairs of logic elements based on the packing of pairs of the nodes.