1. An integrated circuit, comprising: a path between a source register in a first clock domain and a destination register in a second clock domain; a buffer within the path, wherein the buffer is configured to propagate a buffer input data signal along the path responsive to a buffer enable signal being asserted; and circuitry configured to: determine that a predetermined number of clock cycles have occurred since the buffer received the buffer input data signal; and assert the buffer enable signal in response to determining that the predetermined number of clock cycles of have occurred.