1. A method of testing logic circuitry, comprising: performing a statistical timing analysis on a design of logic circuitry; performing a criticality analysis on said logic circuitry as a function of said statistical timing analysis so as to determine a criticality probability for each node; selecting a plurality of nodes of said logic circuitry as a function of said criticality analysis; selecting a plurality of timing paths as a function of said criticality probabilities of said plurality of nodes; and generating an at-speed structural test (ASST) pattern for each of said plurality of timing paths.