1. A method for conducting a parallel analysis on a circuit design represented by a timing graph formed by a plurality of interconnected nodes, the method comprising: using a computer, determining and updating unprocessed predecessor counts for said interconnected nodes; creating a globally shared work queue of ready to process independent nodes identified as those of said interconnected nodes whose said unprocessed predecessor counts reach zero; assigning said independent nodes from said work queue to at least two parallel computation processes, simultaneously performing node analysis computations thereof; and modifying said circuit design by updating values of said processed independent nodes obtained from said node analysis, said at least two parallel computation processes independently updating said globally shared work queue to process a new plurality of independent nodes.