1. A method of checking for power integrity in a preliminary design for a semiconductor integrated circuit having a power mesh including a power ring formed on a semiconductor die and defining a die size within the boundaries of the power ring, the method comprising the steps of: defining the power mesh for the integrated circuit; selecting applicable power integrity constraints; defining a preliminary floorplan of the design in terms of a plurality of rectangular clusters, each cluster corresponding to a functional block of the design and having a predetermined total current consumption; calculating a current density for each of the clusters based on its total current consumption; selecting a number of coefficients for analyzing power integrity of the design; and estimating a normalized voltage drop of the power mesh responsive to the defined floorplan by applying two-dimensional Fourier spatial analysis using the selected number of coefficients.