1. A system comprising: three or more processors running in lock-step; a controller adapted to receive signals from the processors and being further adapted to determine a majority value for the received signals and detect errors within the received signals; a memory module adapted to store a prior state of the processors; and a scrubbing module adapted to resynchronize the processors, at a predetermined time prior to any detection of errors within the received signals, by reconfiguring elements of the processors to the prior state, the resynchronization being in accordance with the majority value.