1. A method of placing arithmetic operators on a programmable integrated circuit device including a plurality of regions, said method comprising: determining, using a data processing system including a host interface and a memory interface, a placement of a first plurality of arithmetic operators of a data flow graph of multiply accumulate units (MACs) in a region of digital signal processing (DSP) circuitry of the programmable integrated circuit device and a second plurality of arithmetic operators of the data flow graph in a region of logic fabric of the programmable integrated circuit device, wherein the data flow graph of MACs includes four stages of arithmetic operators, wherein each arithmetic operator in the four stages is based in one of the region of DSP circuitry and the region of logic fabric; and determining, using the data processing system, a score related to the performance of the data flow graph.