1. A sequential logic cell comprising: four inverter circuits, each of the four inverter circuits comprising one p-type MOSFET having a gate, one n-type MOSFET having a gate, and one output, wherein the four inverter circuits are connected as a Dual Interlocked Cell (DICE), wherein for each inverter circuit, the gate of the p-type MOSFET is coupled to the output of a first of three remaining inverter circuits and the gate of the n-type MOSFET is coupled to the output of a second of the three remaining inverter circuits, wherein the first and second inverter circuits are different; wherein the DICE comprises four nets, wherein each of the inverter outputs is coupled to one of the four nets, wherein a first net and a second net comprise a voltage state, and wherein a third net and a fourth net comprise an inverse voltage state, and wherein each net comprises a p-type drain contact area and an n-type drain contact area; wherein each of the p-type contact areas and the n-type contact areas are placed along a line, wherein the line comprises a plurality of adjacent contact areas comprising a first contact area and a second contact area; wherein for each pair of adjacent contact areas, if a first adjacent contact area and a second adjacent contact area both comprise p-type drain contact areas or both comprise n-type drain contact areas, the first adjacent contact area and the second adjacent contact area are coupled to nets comprising opposite voltage states; and wherein for each pair of adjacent contact areas, if the first adjacent contact area and the second adjacent contact area comprise one p-type drain contact area and one n-type drain contact area, the first adjacent contact area and the second adjacent contact area are coupled to nets comprising similar voltage states.