1. A method of identifying trace-containment for a sequential circuitry design netlist by execution of instructions loaded into a computer system, the method comprising: identifying, by the execution of said instructions, a cut of the netlist comprising an input i; enumerating, by the execution of said instructions, a set of mismatch traces; deriving, by the execution of said instructions, a set of inputs ‘J’ from the mismatch traces for equivalence checking to detect trace containment; performing, by the execution of said instructions, time-bounded unfolding of a cofactored version of the cut reflecting sequential cofactor for the input i and temporal uncorrelation constraints for the set of inputs ‘J’; determining, by the execution of said instructions, whether there is trace containment; in response to detecting trace containment, recognizing a constraining relation over the set of inputs ‘J’; and seeking, by the execution of said instructions, to prove sequential equivalence of said cut subject to the constraining relation.