1. A method for measuring an effective gate channel length during a capacitance-voltage (C-V) method, said method comprising: providing a first device with a source/drain and a gate mounted on a substrate, wherein said gate being in a predetermined length L 1, a predetermined width W 1, and a predetermined height H 1, and said predetermined width being orthogonal to said predetermined length of said gate; applying a negative fixed voltage to said gate of said first device; measuring a first capacitance between said gate and said source/drain of said first device at said negative fixed voltage; applying a positive fixed voltage to said gate of said first device; measuring a second capacitance between said gate and said source/drain of said first device at said positive fixed voltage; using said measured first capacitance to determine a gate-to-drain overlap length of said first device; using said measured second capacitance to determine a gate etch bias length of said first device; and calculating said effective channel length from said gate-to-drain overlap length and said gate etch bias length.