1. A design rule checking system for checking compliance of an integrated circuit design with a plurality of design rules, said integrated circuit design comprising design data defining a plurality of elements in the integrated circuit, said design data comprising data specifying respective values for a set of geometric parameters descriptive of the geometry of one or more elements in the integrated circuit, said set of geometric parameters including at least a first geometric parameter, and said plurality of design rules comprising a plurality of first design rules specifying respective limit values for said first geometric parameter, and yield loss occurs when said integrated circuit is manufactured according to said integrated circuit design, said yield loss including systematic yield loss, the design rule checking system comprising: a conflict-detection unit for detecting conflict between at least two of said first design rules; a systematic-yield-loss modelling unit for applying, in respect of each of said at least two first design rules, a respective model indicating a relationship between the value of said first geometric parameter of said integrated circuit design and a corresponding value of systematic yield loss when the integrated circuit is manufactured, the systematic-yield-loss modelling unit including a calculation unit adapted to calculate, for different possible values of said first geometric parameter, a value of systematic yield loss according to each of said non-binary models; and a value-setting unit for selecting a value for said first geometric parameter by determining the lowest value of systematic yield loss calculated by said calculation unit for a value of said first geometric parameter that respects said conflicting first design rules and selecting the value of the first geometric parameter that corresponds to said lowest value of systematic yield loss, and for controlling said design data to set the first geometric parameter to said selected value.