1. A computer implemented system for instruction scheduling and resource management comprising: a scheduling module configured to order a sequence of instructions; a function unit based finite state automata table configured to store a plurality of function unit vectors, each having as no more used bits than there are issue ports for a microprocessor, and one or more function unit template assignments for each function unit vector; and one or more microprocessor resource management components configured to match the sequence of instructions with at least one of the plurality of function unit vectors, and to arrange the sequence of instructions in accordance with at least one of the function unit template assignments corresponding to the at least one of the plurality of function unit vectors and in cooperation with the scheduling module.