1. A processor comprising: at least one core; an interconnect that couples the at least one core and cache memory, the interconnect to operate at an interconnect frequency (f CL ); and a power management unit (PMU) including f CL logic to determine whether to adjust the f CL responsive to a Bayesian prediction value that is associated with scalability of a workload to be processed by the processor, wherein the Bayesian prediction value is determined based on one or more activity measures associated with the processor.