1. A semiconductor memory device, comprising: an array of memory cells arranged in rows and columns, said rows extending in a first direction and said columns extending in a second direction substantially perpendicular to said first direction; wherein said plurality of memory cells are organized into a plurality of memory cell cores each comprising a plurality of said memory cells, said memory cell cores being arranged in an array of rows and columns of memory cell cores extending in said first and second directions, respectively; and wherein each two adjacent columns of memory cores define a substantially columnar stripe therebetween, such that a plurality of said columnar stripes are defined throughout said array of memory cells; said memory device further comprising: a plurality of conductive column select lines extending in said second direction along said columnar stripes defined between adjacent columns of memory cell blocks; a plurality of conductive power straps extending in said second direction along said columnar stripes defined between adjacent columns of memory cell blocks; and a plurality of conductive control signal lines extending in said second direction along said columnar stripes defined between adjacent columns of memory cell blocks.