1. A method of simulating an integrated circuit (IC) design, the method comprising: accessing an optimized hierarchical netlist; determining a node order ranking of nodes in the optimized hierarchical netlist, a node order being proportional to a maximum value of a derivative ratio; partitioning circuits of the optimized hierarchical netlist with a static current driving scheme and a dynamic current driving scheme based on the node order ranking; building a hierarchical data structure based on the partitioning; merging intermediate node orders for optimization and re-partitioning the circuits based on at least one merged intermediate node order; performing solving and integration using the hierarchical data structure to generate an order-ranked hierarchy; performing analysis on the order-ranked hierarchy engine; and exporting simulation data of the IC design based on the analysis.