1. A back annotation apparatus including: a pre-layout simulation implementing part for detecting nodes of which the potential changes when a predetermined signal is applied to a logic circuit; a layout pattern verification implementing part for implementing a predetermined layout pattern verification for layout patterns of said logical circuit; a parasitic element extraction part connected to said pre-layout simulation implementing part which extracts parasitic elements from said nodes of which the potential changes; a net list generation part connected to said parasitic element extraction part for generating a net list which includes all the devices included in said layout pattern data and parasitic elements extracted in said parasitic element extraction part; and a post layout simulation implementing part connected to said net list generation part for implementing a post layout simulation by using said net list.