1. A semiconductor device design method performed by at least one processor, said method comprising: extracting, using a resistance and capacitance (RC) extraction tool, a first parasitic capacitance, the first parasitic capacitance being between a first set of electrical components, the first set of electrical components being positioned inside a defined region within a layout of a semiconductor device, the first parasitic capacitance being extracted by the RC extraction tool using a first extraction methodology; extracting, using the RC extraction tool, a second parasitic capacitance, the second parasitic capacitance being between a second set of electrical components, the second set of electrical components including one or more electrical components positioned outside the defined region, the second parasitic capacitance being extracted by the RC extraction tool using a second extraction methodology different from the first extraction methodology; and generating, using a netlist generator tool implemented by the processor, a netlist representation of the layout, the netlist including the extracted first parasitic capacitance and the extracted second parasitic capacitance, wherein the first extraction methodology uses a greater quantity of electrical components to extract the first parasitic capacitance than the second extraction methodology uses to extract the second parasitic capacitance, the first extraction methodology thereby being more accurate than the second extraction methodology.