1. A method for performing an analysis of at least one logic stage in a netlist, said logic stage having at least one driver, the method comprising: a) generating at least one look-up table for an output transient current, based on values of input and output voltages, using data available from a cell library; b) synthesizing analytically at least one current source model including a DC component and a plurality of parasitic capacitances, using said look-up table, said synthesizing said current source model including representing said DC component of said current source model using an analytical expression and curve-fitting said analytical expression to values of said output transient current available from said look-up table; c) simulating said logic stage using said current source model to model said driver; and d) obtaining characteristics of said simulated logic stage, wherein synthesizing said current source model further comprises computing values of said plurality of parasitic capacitances by curve-fitting said current source model to values of said output transient current available from said look-up table.