1. In a method for designing a circuit where design parameters for performance specifications are represented by posynomial expressions with constraints and solved with geometric programming, an improvement for simultaneously determining the boundaries for circuit elements in the floorplan of the circuit comprising: representing the boundaries for circuit elements in the floorplan of the circuit as posynomial expressions with constraints on circuit size; solving the posynomial expressions for the design parameters and floorplan boundaries on a digital computer using geometric programming; outputting the results in a format that can be used by a circuit designer in the fabrication of the circuit.