1. A method of forming an integrated circuit chip, comprising: (a) loading a multi-chip reticle into a photolithographic exposure tool, said multi-chip reticle having two or more separate chip images arranged in an array, each chip image of said two or more chip images having only one type of reticle image, wherein at least two of said two more chip images have different types of reticle images; after (a), then (b) coating a semiconductor substrate with a photoresist layer, loading said substrate into said photolithographic exposure tool, exposing said first photoresist layer using a first chip image of said two or more chip images; and after (b), either (c) removing said substrate from said photolithography tool, developing said first photoresist layer, processing said substrate, removing said first photoresist layer, coating said semiconductor substrate with a second photoresist layer, loading said substrate into said photolithographic exposure tool, exposing said second photoresist layer using a second chip image of said two or more chip images, said second chip image having only one and a different type of reticle image than said first chip image, removing said substrate, developing said second photoresist layer, further processing said substrate and removing said second photoresist layer or (d) exposing said first photoresist layer using a second chip image of said two or more chip images, said second chip image having only one and a different type of reticle image than said first chip image, removing said substrate, developing said first photoresist layer, processing said substrate and removing said first photoresist layer.