1. A memory device for electrical connection to a memory bus, the memory device comprising: a plurality of dynamic random access memory (“DRAM”) integrated circuits, each DRAM integrated circuit comprising a memory core of a plurality of cells and accessible at a first speed; and an interface integrated circuit electrically coupled to the plurality of DRAM integrated circuits for providing an interface between the DRAM integrated circuits and the memory bus at a second speed; wherein the interface integrated circuit is adapted for providing a predetermined electrical load on the memory bus independent of a number of the DRAM integrated circuits to which the interface integrated circuit is electrically coupled.