1. An image sensor device comprising: a silicon substrate having a plurality of CMOS circuit formed thereon; a pixel array having a plurality of rows and a plurality of columns formed within the substrate; a timing control logic block formed within the substrate; a row addressing circuit formed within the substrate and operatively connected to each the pixel array and the timing control circuit, the row addressing circuit having a row bus that provides address lines to each row in the pixel array; a column addressing circuit formed within the substrate; a pixel timing circuit formed within the substrate; a signal processing circuit contained within the substrate; and an interface circuit coupled to external computational means for provision of commands used by the sensor to generate address and control signals to the sensor device, the interface circuit being operatively coupled the timing control logic, the pixel timing circuit, the row addressing circuit and the column addressing circuit.