1. A logic test and configuration map control system in a data processing system including processor means and memory means comprising, in combination: first test means responsive to said processor means for determining the functionality of a first section of said memory means; inhibit means responsive to said first test means for issuing a control signal to said processor means to inhibit further operation of said logic test and configuration map control system if said first memory section is determined to function erroneously; second test means in electrical communication with said first test means and said inhibit means for determining the functionality of a second section of said memory; and means in electrical communication with said second test means for storing in a predetermined location of said first memory section the results of the operation of said second test means indicating the functionality of said second memory section.