1. A method for identifying defects in fabrication of a semiconductor wafer, comprising: determining locations of some defects on the semiconductor wafer; determining if a set of defect areas, each surrounding a different one of the defects, contains one or more common circuit structural elements; if one or more common circuit structural elements are identified, categorizing the defects surrounded by the set of defect areas as corresponding to the common circuit structural elements; selecting a subset of defects categorized as corresponding to the matched common circuit structural elements for sampling; and matching the common circuit structural element in similar defected neighborhoods in different locations across the wafer to identify defects associated with the common circuit structural element.