1. A method comprising: selecting a predetermined number, n, of structures representing an integrated circuit (IC) design layout eligible for SEM measurement; specifying an image parameter space of image parameters for the n structures; optimizing a redundancy in the image parameter space of measurement sites for the n structures; calibrating an optical proximity correction (OPC) model for the IC design layout based on the optimized redundancy; and manufacturing an IC based on the calibrated OPC model, wherein the selecting step comprises: calculating simulated contours of one or more structures representing the IC design layout; calculating evaluation cutlines along the simulated contours; extracting one or more image parameters for the evaluation cutlines; overlaying the image parameter space with a grid of a 1 Ã—a 2 Ã—. .. Ã—a y bins (where y represents a number of the image parameters extracted); mapping the image parameters of all structures representing the IC design layout; determining for each non-empty bin which structure contributes the most points to the bin; and selecting for each non-empty bin the determined structure.