1. A method of producing masks for control of integrated circuit fabrication comprising the steps of: receiving a Resistor-Transistor Logic (RTL) design of the integrated circuit; receiving a set of clock gating constraints; inferring clock gates in the RTL design from the set of clock gating constraints; synthesizing the RTL design with the inferred clock gates; globally placing the synthesized design; performing placement aware clock gate cloning in the globally placed design; optimizing placement of the clock gate clones in the globally placed design; synthesizing a clock tree from the placement optimized globally placed design; and generating a corresponding set of masks from the clock synthesized placement optimized globally placed design.