1. A method for analyzing a circuit network having transistors, comprising: representing a circuit by an equivalent circuit that comprises at least one linear network and at least one nonlinear cell to interface with each other; solving circuit equations for the at least one linear network and the at least one nonlinear cell, respectively; and matching solutions to the at least one linear network and the at least one nonlinear cell at an interface between the at least one linear network and the at least one nonlinear cell.