1. A fault-detecting apparatus for processing information useful for detecting faults in the operation of a principal apparatus where the principal apparatus includes a plurality of principal circuit points each having a digital expected state and a digital actual state at any one point in time during the operation of said principal apparatus where the state of each said principal circuit point is faulty if the corresponding actual state is not the same as the expected state, said fault-detecting apparatus comprising, a secondary apparatus for processing state information independently from said principal apparatus without altering the actual states of said principal circuit points, said secondary apparatus including, accessing means, connected to said pincipal circuit points, for accessing state information at said one point in time indicating the actual states of said principal circuit points, subset means for causing said state information from said accessing means to include the actual states of only a subset of said principal circuit points, said subset means including a memory for storing identification values for identifying said subset of said principal circuit points, and including means for selecting said data information to include the actual states of said subset of principal circuit points identified in said memory, generator means connected to receive said state information from said subset means for generating an actual checksum having a value dependent upon the actual states of said subset of said principal circuit points, and means for storing an expected checksum having a value determined by the expected states at said one point in time of said subset of said principal circuit points whereby the expected checksum can be compared with the actual checksum for detecting faults in the principal apparatus.