1. A method of adaptively adjusting the phase of an internal clock signal, the method comprising: receiving a digital signal having a plurality of transitions; comparing transitions of the digital signal to transitions of the internal clock signal at different phases of the internal clock signal; determining respective delay times of the digital signal relative to the internal clock signal based on each of the comparisons; identifying each phase of the internal clock signal that resulted in a delay time within a predetermined range of delay times; selecting one of the identified phases of the internal clock signal; and adjusting the phase of the internal clock signal to the selected phase of the internal clock signal.