1. A computer-implemented method for evaluating a layout of an electronic circuit, comprising: identifying one or more situations for said layout, wherein each of the one or more situations comprises a configuration of one or more shapes or cell instances which are arranged to represent one or more circuit features in the layout; determining a canonical set for the one or more situations by using situation merging or overlap removal, wherein the act of determining the canonical set is performed by a processor; performing analysis on the canonical set for the one or more situations to improve yield; and evaluating the layout by transforming or modifying the layout into a second layout that is to be used for fabrication of the electronic circuit based at least in part on a result of the analysis.