1. A synchronous DRAM operating synchronously with an external clock, comprising: a clock buffer, for receiving the external clock, and for generating an internal clock; a plurality of pipelines; a plurality of gates, interposed among said pipelines; an operation mode judgement circuit for determining an operation mode in response to a command input and for outputting a mode signal; and a gate control circuit, receiving the mode signal, for providing said internal clock to the gates when said operation mode is a first operation mode, and for not providing said internal clock to the gates when said operation mode is a second operation mode.