1. A method of patterning an integrated circuit, comprising: depositing a layer of resist on a substrate; and projecting energy through a mask onto the layer of resist; wherein the mask is produced by a method comprising: determining overlay error variation across a field of the mask; defining at least two zones within the field of the mask, wherein each zone is a continuous portion of the field containing substantially similar overlay error values, and wherein each zone has a nominal overlay error value; defining a correction for each of the at least two zones, wherein the correction for each zone is approximately the nominal overlay error value for that zone; mapping each of a plurality of features to one of the at least two zones; and modifying coordinates of each of the plurality of features in response to the correction for the zone in which each feature is mapped.