1. A defect pattern evaluation method, comprising: performing, after a predetermined process for manufacturing a semiconductor device, optical defect inspection on a pattern on a substrate; detecting defects by the optical defect inspection; classifying, on the basis of a pattern layout that corresponds to coordinates of the defects, the defects by a type of the pattern layout; counting a number of the defects that are in each type of the pattern layout; calculating, using a computer, a defect occurrence rate for each type of the pattern layout by dividing the number of defects counted in each type of the pattern layout by a number of pattern layouts in each type of the pattern layout; and outputting the defect occurrence rate for each of the pattern layout as an evaluation result.