1. A system for electronically investigating a pattern that can be divided into an array of points, the system comprising: signal producing means for producing an electrical signal for each point on a matrix of points, said matrix having "K" points by "L" points, wherein K and L are real integers with one representing the points in the matrix line and the other representing the points in a matrix column, said signal producing means providing a serial stream of signals; selecting means for progressively selecting locatable known groups of said produced electrical signals, which groups correspond to subarrays of said points, each said subarray having M lines by N columns, including a peripheral set of 2(M-2)+2N points and a central set of M.times.N-2(M-2)-2N points, wherein said selecting means is comprised of a first storage means for storing and providing said electrical signals from said signal producing means on a first-in, first-out basis; first determining means for checking and determining for each selected group of said signals whether a first, preselected number of signals corresponding to said central set of points have a first predetermined value and hence whether there is a central hit; second determining means for checking and determining for each selected group of signals whether no more than a second, preselected number of the signals corresponding to said peripheral set of points have a second predetermined value, and hence whether there is a peripheral hit, wherein said second determining means comprises a memory means for storing 2.sup.2(M-2)+2N coded outputs, said memory means having an enable input and 2(M-2)+2N address lines which are connected to said 2(M-2)+2N peripheral storage cells; and said first determining means comprises gate means, the inputs of which are connected to said central storage cells and the output of which is connected to said enable input, said gate means for providing an output signal to enable said memory means when said central storage cells contain said first preselected number of signals such that said memory means outputs the data stored at the memory address indicated by the signals stored in said peripheral storage cells; third determining means responsive to said first and second determining means for determining the location of each subarray of points for which a central hit and a peripheral hit for the same group of corresponding signals were determined; and memory means for storing each determined location.