1. A method for using a processor to identify a squish pattern in an integrated circuit design layout, the method comprising: upon input of the design layout, identifying with the processor an anchor in the design layout; defining, with the processor, a window for the anchor comprising elements of the design layout; identifying, with the processor, a delta between every adjacent scan line in the window that contains an element edge; reducing, with the processor, each delta to the same width, the plurality of reduced deltas forming a squish pattern for the window, and storing a record comprising original dimensions for the plurality of deltas with the squish pattern in a memory storage device.