1. A memory device, comprising: a plurality of storage cells arranged in an array or rows and columns; a plurality of bitlines, each bitline coupled to a plurality of storage cells along one of the columns; a plurality of wordlines, each wordline coupled to a plurality of storage cells along one of the rows; a column decoder having a plurality of control outputs, each of the control outputs coupled to a column of the array; and a variable delay circuit coupled to the column decoder and including a control input, the delay circuit causing the control outputs of the column decoder to be variably delayed based upon the control input.