1. A semiconductor memory module comprising: at least one memory chip; a buffer chip which drives clock, address, and command signals to the memory chip and drives data signals to, and receives them from, the memory chip via module-internal clock, address, command and data bus lines, the buffer chip forming an interface to an external memory main bus; wherein the data bus lines or the clock, command and address bus lines are respectively connected to the buffer chip at their two ends and can be driven by the buffer chip from these two ends; and control means for respectively matching directions of propagation of the data signals and of the clock, command and address signals on the corresponding bus lines during writing and reading.