1. A method to provide a capacitance to a design an integrated circuit comprising: receiving a layout of the integrated circuit; applying canonical hierarchical models to the layout, wherein the canonical hierarchical models include a first type canonical model to capture a first capacitance of a device having a plurality of first conductors and a second type canonical model to capture a second capacitance between at least a portion of the device and one or more second conductors of the integrated circuit; and determining a capacitance for the layout based on the applying.