1. An output multiplexing circuit for a Double Data Rate (DDR) synchronous memory device, the output multiplexing circuit comprising: n (where n is an integer) first latches, which simultaneously prefetch n-bit data transmitted from a memory cell array via a data path; n first switches, which simultaneously transfer the n-bit data prefetched into the first latches to n nodes in response to a CAS latency information signal; n second switches, which simultaneously transfer data on the nodes in response to n signals that are synchronized with a clock signal and sequentially generated at a predetermined interval; n second latches, which store the data transferred via the second switches; and two third switches, which sequentially transfer the data stored in the n second latches to an input terminal of an output driver of the memory device at a rising edge and a falling edge of a delay signal of the clock signal.