1. An integrated circuit memory device comprising: a memory cell array; an address buffer that buffers address data for the memory cell array in response to a clock signal; a command buffer that buffers read and write commands for the memory cell array in response to the clock signal; a data input and output buffer that buffers data for the memory cell array in response to a data strobe signal that is different from the clock signal; and a data masking buffer that buffers a data masking signal that masks the data in response to the data strobe signal.