1. A memory device comprising: a storage array comprised of a plurality of memory cells; an interface buffer coupled to the storage array, and having a first interface to couple the memory device to a first memory bus to couple the memory device to an external memory controller; and memory error logic associated with the interface buffer to carry out a check for memory errors within the storage array during a period of time in which there are no transactions carried out by the external memory controller on the first memory bus that involve the storage array.