1. A method for classifying a set of patterns in a set of layout patterns, comprising: for an integrated circuit layout having a plurality of pattern windows, decomposing the pattern windows into a low frequency component and a high frequency component using a wavelet analysis; using the low frequency component as an approximation, computing a plurality of moments for each pattern window; and classifying the pattern windows into pattern classes using a distance computation for respective moments of the pattern windows by comparing the distance computation to an error value to determine similarities between the pattern windows.