1. An integrated circuit (IC) method comprising: building a pattern bank including a pattern having an area of interest; recognizing that the pattern of the pattern bank corresponds to a pattern of an IC design layout; identifying an area of interest of the pattern of the IC design layout that corresponds to the area of interest of the pattern of the pattern bank; performing pattern recognition dissection on the area of interest of the pattern of the IC design layout to dissect the area of interest of the pattern of the IC design layout into a plurality of segments; and after performing pattern recognition dissection, producing a modified IC design layout.