1. A method for testing an integrated circuit comprising: generating a test pattern; generating a reference signature corresponding to said test pattern; executing an integrated circuit test in response to said test pattern; generating a result signature in response to data output from said executing an integrated circuit test; comparing said result signature to said reference signature; creating a current failing signature in response to a mismatch between said result signature and said reference signature, wherein said current failing signature is a copy of said result signature; and executing common error analysis in response to said creating a current failing signature.