1. A method for statically analyzing timing of an electronic circuit design, the method comprising: characterizing substantially all circuit cells of a cell library to determine output waveform change information responsive to variations in one or more circuit parameters; in response to the characterizing, generating a time varying linear input model for each input and a time varying linear output model for each output of each logic gate of the integrated circuit; receiving a model for each linear interconnection network coupled between an output of a logic gate and an input of another logic gate; for each stage of the electronic circuit design, combining the time varying linear input model, the model for the respective linear interconnection network, and the time varying linear output model together into a set of matrix equations representative of the combined models; and solving, by using a processor, at each time step the set of matrix equations to determine an output waveform for each output of each stage of the electronic circuit design to efficiently simulate the electronic circuit design.