1. A semiconductor memory device, comprising: a central control circuit for generating an active signal and a control signal for executing an operation command received from an external chipset, and generating a precharge signal and a refresh signal after a predetermined time; a row path control circuit for controlling a bank according to the active signal or the precharge signal of the central control circuit; and a delay circuit for setting a delay path depending upon a normal operation or a refresh operation of the control signal to be different according to the refresh signal, and outputting a delay signal having a different delay time, thus controlling generation of the precharge signal of the central control circuit.