1. A system that employs digital column gain mismatch correction for a complementary metal-oxide-semiconductor (CMOS) imaging system-on-chip (iSoC) sensor, comprising: a test signal generation component that provides tunable voltages that mimic presence of photo-charge to test pixels in one or more rows of a pixel array; and a column mismatch mitigation component that calibrates column-specific digital gain corrections based upon digital input data obtained from the test pixels via an analog readout architecture and mitigates column gain mismatch by employing the column-specific digital gain corrections for digital input data obtained from non-test pixels via the analog readout architecture to yield digital output data.