1. A computer-implemented method for design analysis comprising: identifying a cell and multiple instances of the cell from a semiconductor design including a plurality of cells and a plurality of virtual hierarchical levels; loading virtual hierarchical layer (VHL) data based on the cell; obtaining a virtual cell model, representative of the cell; determining interactions, using one or more processors, between data within the cell and the VHL data, and selecting relevant portions of shapes based on the determining; reducing, using one or more processors, an amount of data within the virtual cell model based on the interactions which were determined, wherein the reducing further comprises removing shapes which are not part of the relevant portions; and producing, using one or more processors, a final design layout for fabrication wherein the final design layout is based on the virtual cell model with the amount of data being reduced.