1. A design assist apparatus comprising a processor that selects, as an insertion candidate, a signal line onto which a test point for test controlling is to be inserted and which is included in a circuit to be designed, wherein the processor: selects first insertion candidates being a plurality of signal lines in a circuit net the vertex of which is a maximum observation point having a maximum diagnosis difficulty index among a plurality of diagnosis difficulty indexes of all the observation points that are used for observing signal lines in the circuit, each of the plurality of diagnosis difficulty indexes of the observation points representing the difficulty in fault diagnosis at the corresponding observation point; and selects a second insertion candidate onto which the test point is to be inserted from the first insertion candidates, considering effects of inserting the test point onto the respective first insertion candidates.