1. A process in a computer system for generating a high level schematic from a project schematic of basic components, comprising: a. scanning the project schematic for a predetermined cell, wherein the cell comprises a select group of components and their interconnections; b. replacing the group of select components found in the project schematic by a cell symbol having input and outputs to generate the high level schematic; c. repeating steps (a) and (b) for other predetermined cells.