1. A method for optimizing an integrated circuit layout design, comprising: obtaining a first integrated circuit layout design comprising a metal line feature having several metal lines and a second integrated circuit layout design comprising a hole feature having several holes by a computer system, wherein the metal line feature and the hole feature are printed in adjacent layers of a wafer; selecting a line-end hole feature of the hole feature by piecing the metal line feature with the hole feature by the computer system; and classifying the line-end hole feature into a single hole feature and a redundant hole feature depending on whether spacings between adjacent holes of the line-end hole feature exceeding or falling into a minimum dense hole space tolerance by the computer system.