1. A method for verifying a pattern of a semiconductor device, the method comprising: providing a designed layout of target patterns; transferring the designed layout on a wafer to form wafer patterns; obtaining an image contour of the wafer patterns; matching the image contour of the wafer patterns on the designed layout; extracting edge differences between the designed layout and the image contour of the wafer patterns; obtaining a checking layout for detecting wafer pattern defects by adding the edge differences on the designed layout; and identifying defects on the checking layout.