1. A synchronous dynamic random access memory (SDRAM) comprising: an SDRAM memory array; an SDRAM data output circuit; a clock signal; and a delay locked loop (DLL) having an adjustable delay line for generating a driving clock signal from the clock input signal, the driving clock signal to be applied to the SDRAM data output circuit, the adjustable delay line being a tapped delay line and the DLL being used and not used, as the clock input signal is maintained, in response to external control, wherein taps provide plural outputs of the delay line and a comparator in the DLL determined one of the tap outputs that forms the driving clock signal.