1. A method of generating an integrated circuit capacitor layout comprising the steps of: (a) receiving fractal input parameters; (b) generating a fractal based upon the fractal input parameters; (c) converting the fractal into a circuit layout generator compatible form; (d) inputting the fractal description code into an integrated circuit layout generator; (e) generating an integrated circuit capacitor layout wherein the plates of the capacitor are generated so as to approximate the shape of the fractal.