1. A memory module comprising: a plurality of memory devices; a control circuit configured to generate a chip select signal that is provided to each of said plurality of memory devices, wherein said chip select signal is dependent upon assertions of a first bank chip select signal and a second bank chip select signal; wherein said control circuit is further configured to generate an address signal that is provided to each of said plurality of memory devices, wherein said address signal is asserted dependent upon which of said first bank chip select signal and said second bank chip select signal are asserted.