1. In a photolithography processing system having an associated numerical aperture (NA) value in which a reticle having a set of reticle parameters is exposed to an illuminator having a set of illuminator parameters to pattern a wafer with a desired layout, a method for manufacturing an integrated circuit device comprising the steps of: simulating how the desired layout will pattern on a wafer for a plurality of combinations of different NA values, illuminator parameters and reticle parameters; for each combination of NA values, illuminator parameters and reticle parameters, classifying structures within the associated simulated layouts based on manufacturability; and selecting at least one combination of NA value, illuminator parameters and reticle parameters based on the classifying step.