1. An apparatus for simulating at least one virtual memory circuit, the apparatus comprising: a plurality of physical memory circuits; and an interface circuit configured to: communicate with the plurality of physical memory circuits; communicate with a memory controller via a bus; and simulate at least one virtual memory circuit for the memory controller, wherein a precharge-to-active ratio of the simulated virtual memory circuit is different from a precharge-to-active ratio of at least one physical memory circuit of the plurality of physical memory circuits, and wherein a change in a timing of the bus changes the precharge-to-active ratio of the simulated virtual memory circuit.