1. A DRAM system with internal refreshing of dynamic memory cells, comprising: a self-refresh internal oscillator circuit that provides an internal self-refresh (RFSH) output signal for the DRAM system; a RAS input terminal for receiving an input row access select (RAS) signals for reading from or writing to memory cells of the DRAM system; an arbitration and selection control circuit that receives the RFSH signal and the input RAS signal and that arbitrates between those two signals to provide two alternative output signals: one of which is an internal-refresh selection SEL_RFSH command output signal when the RFSH input signal is given priority by the arbitration and selection circuit and the other of which is an external-address selection SEL_RAS command output signal when the RAS input signal is given priority by the arbitration and selection circuit; two or more DRAM blocks of memory cells, each DRAM block arranged in word rows and each of said word rows having a row-access signal line for receiving a row-access select signal that causes DRAM memory cells in a corresponding word row to be addressed and refreshed; each DRAM block having a corresponding wordline decoder that receives multi-bit row-line address input signals and that also receives a wordline-decoder control signal to provide row-access select output signals to corresponding row-access signal lines; each DRAM block having a corresponding wordline address multiplexer that provides either internally-provided refresh wordline input address signals REF_ADDR to the wordline decoder or externally-provided row-line address signals to the wordline decoder.