1. A memory subsystem for use in a system including a processing unit coupled to a multiword bus in common with said subsystem, said processing unit being operative to generate memory requests on said bus to said subsystem, each of said requests including a multibit address, said memory subsystem comprising: a plurality of independently addressable memory module units, each memory unit being individually coupled to said multiword bus, said each memory unit including a plurality of rows of random access memory chips; decode logic circuit means having a number of outputs, said decode logic circuit means generating decode outputs signals at said number of outputs in response to at least significant portion of each said multibit address of each request received from said bus; and gating means having a plurality of inputs and outputs, said outputs being selectively coupled to said plurality of rows of chips of said addressable memory module units and said gating means inputs being selectively connected to said decoder means outputs so as to simultaneously generate at a plurality of sequential row address select signals at a plurality of said outputs in response to each said least significant address portion enabling simultaneous access to a plurality of word locations of said memory module units specified by another more significant portion of each said multibit address during a single bus cycle of operation.