1. A method for evaluating a layout, comprising: using at least one processor to perform a process, the process comprising: simulating a plurality of situations, which are extracted from the layout, for the layout, wherein at least one situation of the plurality of situations includes an arrangement of one or more shapes or cell instances that represent one or more circuit features to be manufactured from the layout; tiling the plurality of situations, which have been simulated, back into locations in the layout based at least in part upon a result of simulating the plurality of situations, and determining data indicative of an amount of variability or disorder that exists in the layout by using at least the some of the plurality of situations.