1. Asynchronous Parallel Arithmetic (APA) processor utilizing Coefficient Polynomial Arithmetic (CPA) capable of processing given arithmetic operations on multiple sets of input binary numbers A and B, said APA processor comprising modular hardware components and being capable of achieving parallelism and concurrency at the data-path level, thereby facilitating the mapping of algorithms to hardware for embedded systems, said modular hardware components comprising: a means for holding therein the input binary numbers A and B; a parallel multiplier, coupled to said holding means, for processing said input binary numbers and producing therefrom a first set of coefficient polynomials p n in CPA form, said first set of coefficient polynomials being organized into a plurality of columns; a means for receiving and parallel-merging said first set of coefficient polynomials in said columns to produce a second set of coefficient polynomials and continuing said parallel-merging of the last set of coefficient polynomials until the degree of “1” for the resultant coefficient polynomial set is achieved; and a two-stage adder coupled to said parallel-merging means for rendering the result of said arithmetic operations on said input binary numbers A and B in ordinary binary form.