1. A method for performing statistical static timing analysis for an integrated circuit design comprising: receiving said integrated circuit design into a computer; automatically computing at least one mean timing value of said integrated circuit design using first manufacturing process variables and a first timing calculation, using said computer; automatically computing second timing values of said integrated circuit design using a second sets of manufacturing process variables and a second timing calculation, using said computer, said second timing calculation having a lower accuracy relative to said first timing calculation; automatically calculating finite differences of each of said second timing values to said at least one mean timing value, using said computer; and automatically computing at least one statistical sensitivity of said at least one mean timing value to said second sets of manufacturing process variables based on said finite differences, using said computer to improve operating speed and decrease malfunction of integrated circuits fabricated according to said integrated circuit design.