1. A processor for an imaging device, the processor comprising: an image sensor interface for receiving data from an image sensor; multiple processing units configured to operate in parallel for processing data from the image sensor interface, wherein each of the multiple processing units includes rewritable memory for storing microcode to operatively control the processing unit; and an instruction input interface for receiving encoded data indicative of an image processing instruction executed by the multiple processing units, the instruction input interface being configured to decode the encoded data corresponding to the image processing instruction, wherein the multiple processing units, the instruction input interface, and the image sensor interface are integrated onto a single chip.