1. A design verification apparatus for a semiconductor device comprising: a storage for storing layout information of the semiconductor device, the layout information including information of interconnection regions and via regions; and a controller for dividing the interconnection regions into wire regions and cross regions, the cross regions corresponding to the via regions, respectively, the wire regions extending between the cross regions, respectively, and extracting at least one of the wire regions as a candidate having a potential risk of future disconnection defect on the basis of the length of the wire regions.