1. A method for verifying a mask pattern of a semiconductor device, the method comprising: providing a designed layout of target patterns; forming wafer patterns on a wafer by transferring the designed layout on the wafer; obtaining an image contour of the wafer patterns from the wafer; matching the image contour of the wafer patterns on the designed layout; extracting edge differences data between edge points of the designed layout and the image contour of the wafer patterns; generating checking layout for detecting wafer pattern defects by including the edge differences data on a data of the designed layout; and checking defects on the checking layout.