1. A method of utilizing associated process data parameters to predict wafer electrical test results during the manufacture of semiconductor wafers, the method comprising: starting a wafer in a series of semiconductor manufacturing processes; setting process parameters for a first process in the series of semiconductor manufacturing processes; running the first process; measuring in-line critical dimensions of the wafer after the running of the first process; determining a first set of lot based data obtained from the measured in-line critical dimensions of the wafer; converting tool based data obtained from the measured in-line critical dimensions of the wafer to a second set of lot based data by interpolating tool based data between a first measurement obtained from a tool at a first time and a second measurement obtained from the tool at a second time using LaPlace-Everett Interpolation; and predicting wafer electrical test results for the wafer from the measured in-line critical dimensions, the first set of lot based data and the second set of lot based data converted from the tool based data.