1. A structure for extracting interconnect parasitic in a ring oscillator which comprises N logical units connected in head to tail series, wherein N is an odd number and is greater than or equal to 3; the structure comprises: parasitic resistance sub-structures and/or parasitic capacitance sub-structures each connected to a corresponding logical unit for determining errors in extracting parasitic resistance of polysilicon interconnects and metal interconnects and/or errors in extracting parasitic capacitance in the polysilicon interconnects and the metal interconnects