1. A fast settling output line circuit, comprising: a pixel cell comprising: a photodiode (PD) adapted to accumulate image charges in response to incident light; a transfer (TX) transistor coupled between the PD and a floating diffusion (FD) to transfer the image charges from the PD to the floating diffusion (FD), wherein a transfer (TX) gate voltage controls the transmission of the image charges from the PD to the FD; a reset (RST) transistor coupled to supply a reset FD voltage (VPIX) to the FD, wherein a reset (RST) gate voltage (HVDD) controls the RST transistor; a source follower (SF) transistor coupled to receive voltage of the FD from a SF gate terminal and provide an amplified signal to a SF source terminal; a row select (RS) transistor coupled between the SF transistor and a bitline, wherein a row select (RS) gate voltage controls the RS transistor, and wherein the RS transistor passes the amplified signal from the SF source terminal to the bitline; and M first voltage generators, wherein each first voltage generator is configured to receive the VPIX and provide a first voltage to the bitline under the control of a first voltage enable, wherein M is an integer equal or larger than one, and wherein the first voltage is one of an idle voltage provided by an idle voltage generator, a blacksun voltage provided by a blacksun voltage generator, and a clamp voltage provided by a clamp voltage generator, wherein the first voltage generator comprises a modified dummy pixel (MDP), and wherein the MDP is the same cell as the pixel cell except that (i) the TX gate is coupled to receive VPIX instead of the TX gate voltage, (ii) the RST gate is coupled to receive VPIX instead of the RST gate voltage (HVDD), and (iii) the SF gate is coupled to receive VPIX instead of the FD; and a bitline enable transistor coupled between a bitline and a bitline source node (BLSN), wherein a bitline enable voltage controls the bitline enable transistor.