1. A computer implemented method for implementing a physical electronic design of an electronic circuit using one or more constraint checking windows, comprising: using at least one processor or at least one processor core to perform a process the process comprising: identifying a constraint for multiple mask designs of a multiple-patterning lithography process for manufacturing the electronic circuit; identifying or determining a first characteristic of a first constraint checking window; and determining whether the constraint is satisfied for the first constraint checking window, or is satisfied for a physical design for an assignment of a first shape in the physical electronic design to a first mask design of the multiple mask designs.