1. A pattern design method of a semiconductor device, comprising: preparing design pattern data; separating a pattern region of a semiconductor device on the basis of the design pattern data into a dummy pattern region and a dummy pattern prohibition region; dividing the dummy pattern region into a plurality of dummy pattern unit regions; setting a plurality of inspection areas in the dummy pattern region and the dummy pattern prohibition region, the inspection area closing round at least the two or more dummy pattern unit regions, a part of one dummy pattern unit region overlapping a part of another dummy pattern unit region; calculating a tentative pattern-covering fraction of a dummy pattern, the dummy pattern being formed in the dummy pattern unit region of the inspection area; calculating a final pattern-covering fraction of the dummy pattern unit region, the final pattern-covering fraction being obtained by averaging the tentative pattern-covering fraction of the dummy pattern unit region in the inspection area; and generating the dummy pattern in the dummy pattern unit region on the basis of the final pattern-covering fraction calculated on the dummy pattern unit region.