1. An image processing circuit, comprising: a full search engine, which executes a full search to generate a sum of sum of absolute difference (SAD) distribution according to a reference image and a current image, wherein the SAD distribution comprises a plurality of sums of absolute differences; and a frame rate conversion (FRC) engine, which generates an interpolated image according to the reference image, the current image and a plurality of the control parameters, wherein the FRC engine determines whether the number of sums of absolute differences larger than the smallest threshold is equal to 1 when partial of the sums of absolute differences is smaller than the smallest threshold, the current image comprises a good scene when the number of sums of absolute differences is equal to 1, the current image comprises a periodic scene when the number of sums of absolute differences is larger than 1, the FRC engine determines whether the sum of absolute differences is larger than an average pixel level (APL) when the sum of absolute differences is not smaller than the smallest threshold, the current image comprises a flash scene when the sum of absolute differences is larger than the APL, the current image comprises a bad scene when the sum of absolute differences is not larger than the APL, and the FRC engine adjusts the at least one of the control parameters according to the good scene, the periodic scene, the flash scene or the bad scene.