1. Image processing circuitry that produces an output data frame during a frame time interval, comprising: control circuitry coupled to an image sensor, wherein the image sensor comprises a plurality of pixels arranged in rows and columns, wherein the control circuitry is configured to output test data during a first portion of the frame time interval of a first checking operation and pixel data during a second portion of the frame time interval of the first checking operation that is subsequent to the first portion; a plurality of image processing blocks that are configured to process the test data and the pixel data output by the control circuitry, wherein the plurality of image processing blocks comprises: a first subset of image processing blocks that is configured to process only the test data; and a second subset of image processing blocks that is configured to process only the pixel data, wherein the control circuitry is configured to bypass a selected subset of the plurality of image processing blocks, and wherein the image processing circuitry further comprises: a test pattern generator that is configured to output test patterns to the plurality of image processing blocks during the second portion of the frame time interval of a second checking operation, the second checking operation different from the first checking operation, wherein the test pattern generator is configured to output test patterns corresponding to the pixel data during at least part of the second portion of the frame time interval of the second checking operation, wherein the test pattern generator is further configured to output test patterns corresponding to digital test data during the entire first portion of the frame time interval of the second checking operation, and wherein the second subset of image processing blocks are configured to process the test patterns based on the pixel data to produce a processed test value.