1. A semiconductor memory device configured to automatically refresh data stored in memory cells and to allow an external asynchronous access, said device including: a switch circuit inserted into a leak path between a system of circuits associated with refresh operations and either a power source or a ground; and a control circuit for controlling said switch circuit to be in an OFF-state in an interval time period between refresh operations for breaking down said leak path and also controlling said switch circuit to turn ON prior to said refresh operation, so that operations of a power system and a control system are previously activated for subsequent start of internal operations for said refresh, wherein a consumption of current is reduced with refresh timings matched between either a read mode or a write mode and a stand-by mode.