1. A method of forming an integrated circuit (IC), comprising the steps of: generating a mathematically predictive, scalable two-dimensional (2D) optical proximity correction (OPC) model, further comprising the steps of: laying out 2D test patterns of basic features occurring in IC layouts; and generating said scalable OPC model from measured contours of printed and etched features of said 2D test patterns; generating a reticle pattern file using said scalable 2D OPC model; generating a reticle using said reticle pattern file; and forming an IC using said reticle.