1. A memory device for performing write and read operations of external input and output data in synchronism with an external clock, comprising: a multiplying circuit for generating an internal clock obtained by multiplying the external clock by a value by using said multiplying circuit; an external I/O for performing write and read operations to and from said memory device at a predetermined external bit width; and an internal I/O for performing write and read operations to and from a memory cell array of said memory device at a predetermined internal bit width, wherein the write and read operations to and from said memory cell array are controlled by said internal clock, and said internal bit width is set smaller than said external bit width.