1. A pattern shape evaluation apparatus comprising: an evaluation area generator which receives an input of design data for a semiconductor device including a first pattern in a lower layer and a second pattern in an upper layer and which adds information on a particular evaluation area within the first pattern or the second pattern, to the design data to generate the design data accompanied by the evaluation area; a pattern edge detector which receives an image of both the first and second patterns and which processes the image to generate edge data for the first and second patterns; an aligner which aligns the edge data for one of the first and second patterns with corresponding design data accompanied by the evaluation area; and a pattern shape measurer which evaluates the other of the first and second patterns within the evaluation area accompanying the design data of the aligned pattern, using the edge data of the other of the first and second patterns.