1. A method for determining a plurality of clock delay values, each delay value associated with a delay element on a clock line leading to a clock sink in a synchronous circuit, the method comprising: determining an initial set of delay values; and executing an optimization algorithm, beginning with the initial set of delay values, to arrive at a set of delay values that at least approximately meet a criteria while satisfying timing constraints associated with selected pairs of logically connected clock sinks, wherein the optimization algorithm comprises randomly modifying the set of delay values.