1. A computer-implemented method for statistical static timing analysis of an integrated circuit, the method comprising: performing, by a processor, an initial statistical static timing analysis of the integrated circuit to create a parameterized model of the integrated circuit for a plurality of paths using a plurality of timing corners to calculate a timing slack for each of the plurality of paths; determining, by the processor, at least one worst timing corner from the parameterized model for each of the plurality of paths based on the initial statistical static timing analysis and calculated timing value for each of the plurality of paths; selecting a margin to provide a desired coverage for a number of selected timing corners; performing, by the processor, a subsequent statistical static timing analysis of the integrated circuit using the at least one worst timing corner and the margin; and delivering a timing setup to a deterministic timing tool based on the subsequent statistical static timing analysis using the at least one worst timing corner and the margin.