1. A synchronous dynamic memory operating in synchronized with an external clock, comprising: a clock input buffer receiving said external clock and outputting an internal clock; a command input buffer receiving commands in synchronization with said internal clock; an address input buffer receiving addresses in synchronization with said internal clock; and a data input buffer receiving data in synchronization with said internal clock; wherein said clock input buffer supplies said internal clock to said command, address, and data input buffers in normal operation mode, and wherein said clock input buffer supplies said internal clock to said command input buffer and stops supply of said internal clock to said address input buffer or data input buffer in data hold mode.