1. An apparatus, comprising: a physical memory sub-system including: a first memory of a first memory class; and a second memory of a second memory class, the second memory communicatively coupled to the first memory; wherein the apparatus is configured such that the first memory and the second memory are capable of being used for a random access data read from the first memory via the second memory as a result of the physical memory sub-system receiving multiple instructions via a single memory bus, by: receiving an instruction via the single memory bus for operating on data, that results in: a first operation on at least a portion of the data in connection with the first memory, a second operation in connection with the second memory, that results in storage of the at least portion of the data in the second memory, and a status being provided; and after the status being provided, receiving another instruction via the single memory bus for operating on the at least portion of the data, that results in the at least portion of the data being read from the second memory; wherein the apparatus is configured such that the physical memory sub-system requires receipt of the multiple instructions via the single memory bus for the random access data read from the first memory via the second memory.