1. An apparatus comprising: a memory array; and an error code module coupled to the memory array and including a data buffer having a plurality of data registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles, the error code module operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles, wherein the error code module is further operable to interleave operations of the read/modify/write processes such that read and write operations do not occur simultaneously.