1. A computer-implemented method for deriving a set of input stimulus for use during verification of an electronic design, the method comprising: identifying an electronic design to be verified; identifying the potential inputs to the design; identifying a set of constraints on the potential inputs; forming a state space exploration problem from the inputs and constraints; fracturing the state space exploration problem into subspaces; converting a one of the subspaces into a singular state space problem, delimited in the step of the overall state space exploration problem; translating the converted subspace into suitable mathematical form for a particular constraint solver; launching a solver to determine if the translated converted subspace has at least one solution; aborting the state space exploration of that subspace if the solver determines that no solution exists. launching multiple solvers simultaneously.