1. A semiconductor memory device with a mode register, the semiconductor memory device comprising: an internal power supply voltage generator for generating an internal power supply voltage of the semiconductor memory device based on an external power supply voltage when the external power supply voltage is applied to the internal power supply voltage generator; a clock buffer for receiving and buffering external clock and clock enable signals in order to generate internal clock and clock enable signals; a command decoder for receiving the internal clock and clock enable signals from the clock buffer, for receiving an external command signal, and for generating an intermediate deep power down mode entry signal instructing the semiconductor memory device to enter into a deep power down mode or a mode register setting signal commanding a setting of the mode register according to a predetermined combination of the internally received clock and clock enable signals with the received external command signals; a mode register setting latch circuit for latching the mode register setting signal from the command decoder when the mode register setting signal is received, after a stabilization of the external power supply voltage; and a deep power down mode controller for receiving the intermediate deep power down mode entry signal from the command decoder, for generating a final deep power down mode entry signal when the deep power down mode controller receives the mode register setting signal from the command decoder, and for outputting the final generated deep power down mode entry signal to the internal power supply generator.