1. A divider circuit in an electronic device for computing an estimate of a quotient of a fractional dividend and a fractional divisor comprising: a memory coupled to a fractional divisor data path, the memory being arranged to store a plurality of values representative of an estimate of a reciprocal of the fractional divisor, a bit length of each stored value of the plurality of stored values being less than a bit length of a pre-scaled fractional divisor; a scaling circuit coupled to receive a pre-scaled fractional dividend, the pre-scaled fractional divisor, and bits including the estimate of the reciprocal of the fractional divisor, the scaling circuit being arranged to scale the pre-scaled fractional dividend and the pre-scaled fractional divisor using the bits including the estimate of the reciprocal of the fractional divisor; and a series expansion correction circuit coupled to the scaling circuit to compute the estimated quotient of the fractional dividend and the fractional divisor using results of the scaling circuit in accordance with the principles of series expansion.