1. A method of generating post-tape-out photolithographic data for patterning a circuit design onto a semiconductor wafer, comprising the operations of: receiving at a post-tape-out manufacturing phase tool, target layout data and post-OPC bias data for the circuit design, wherein the post-OPC bias data comprises data representing differences between a post-OPC layout represented by post-OPC layout data generated during optical proximity correction and a target layout represented by the target layout data; and using a computer system to apply the post-OPC bias data to the target layout data to regenerate the post-OPC layout data as manufacturing layout data.