1. In a computer means for translating position and motion input to alphanumeric output comprising: a. relative motion and/or relative position sensing input means comprising: i. means for determining when said relative motion and/or relative position sensing input means is active; ii. means for sensing basic motion and/or position attributes of the active relative motion and/or relative position sensing input means; and iii. means for defining a meta attribute of the sensed input, said meta attribute chosen from the group consisting of one or more of turns, weighted input center, and strokes thereof; and the improvement wherein said computer means comprises parallel processor computer means, said parallel processor computer means having a plurality of processor memory elements, at least a first one of said processor memory elements comprising: b. multi-way associative content addressable memory means, said multi-way associative content addressable memory means having i. a comparand register for storing and iteratively updating an input object attribute word; ii. recognition pattern tag field means for input attribute words; iii. character data field means for output attributes; iv. means for concurrently comparing a multi-bit input object attribute word in the comparand register to a plurality of recognition pattern tag field entries in the content addressable memory; and iv. means for outputting from the content addressable memory as an output object the contents of the content addressable memory character data field having a recognition pattern tag field entry most closely corresponding to the multi-bit input object attribute word; and wherein said relative motion and/or relative position sensing input means further comprises: iv. means for forming a multi-bit input object attribute word of the sensed basic attributes and defined meta attributes of the sensed input; said relative motion and/or relative position sensing input means and said content addressable memory means maps motion and position data to alphanumeric data; and wherein at least another one of said processor memory elements is in communication with said first one of the processor memory elements for receiving output therefrom.