1. A system, comprising: a memory controller; a memory module, wherein the memory module includes memory devices, the memory devices having an actual CAS (column address strobe) latency; and an interface circuit coupled to the memory controller, wherein the interface circuit is configured to adjust timing of signals associated with one or more of the memory controller and the memory module, wherein the memory controller is programmed with a CAS latency parameter set to a value that causes the memory controller to view the memory devices on the memory module as having a higher CAS latency than the actual CAS latency of the memory devices.