1. A method of determining possible locations of standard cells in an image of an IC layout, comprising the following steps, implemented using a processor having access to the image, of: extracting points of interest from the image; creating a descriptor in the vicinity of each of the points of interest, wherein the descriptor comprises a grid having a number of non-overlapped rectangles, said non-overlapped rectangles represented by a first bit if they contain at least a predetermined percentage of the first conductive layer and represented by a second bit if they contain less than the predetermined percentage; extracting a first instance of a standard cell from the image; comparing descriptors from the first instance of a standard cell to the other descriptors of the image to identify similar points of interest; casting votes on the similar points of interest to show the level of confidence on the similarity of the similar points of interest; and computing the weight of the votes and determining possible matches by locations on the image showing high weights.