1. A synchronous memory device having at least one memory section which includes a plurality of memory cells, the memory device comprises: a register to store a value which is representative of a delay time after which the memory device responds to a read request; clock receiver circuitry to receive first and second external clock signals; and an output driver to output data on a bus in response to a read request and in accordance with the delay time wherein a first portion of the data is output synchronously with respect to the first external clock signal and a second portion of the data is output synchronously with respect to the second external clock signal.