1. A memory system comprising: a primary memory controller; a memory data bus, having an effective bit-width m, coupled to the primary memory controller; and at least one memory module coupled to the memory data bus, the memory module having a module data bus with an effective bit-width N&equals;R×m, where R is an integer value greater than one, the memory module comprising an interface circuit coupled between the memory data bus and the module data bus, the interface circuit capable of performing m-bit-wide data transfers on the memory data bus, the interface circuit capable of performing N-bit-wide data transfers on the module data bus.