1. A fast data weighted average circuit device comprising: an analog-to-digital converter (ADC) comprising a plurality of comparators; and a data weighted average circuit comprising a shifter; wherein at least one of said plurality of comparators comprises an input signal and at least two switches per said at least one comparator, said at least two switches selecting between signals of at least a first block providing first reference voltages and signals of at least a second block providing second reference voltages as inputs to said plurality of comparators, based on a timing signal; wherein said shifter shifts said outputs of said plurality of comparators with n-gate delays, based on said timing signal, wherein said outputs of said plurality of comparators randomly direct to a plurality of outputs; and wherein non-overlap alternation of said signals of said at least a first block and said at least a second block comprises double sampling quantization.