1. A semiconductor memory module comprising: a substrate; a plurality of semiconductor memory chips arranged on the substrate in a specified topology; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting a first one of the memory chips to a first number of CAwD input signal pins on said substrate, said first number being equal to the first predetermined line number, wherein the signal input lines supply write data, command, and address input signals from an external memory controller to said first memory chip in a first direction; CAwD signal interconnection lines arranged on the substrate, the interconnection lines operable to establish re-driven write data, command, and address signal interconnections between the plurality of memory chips and to supply re-driven write data, command, and address signals from each preceding memory chip to each succeeding memory chip in the first direction; rD signal output lines arranged on the substrate in a second predetermined line number and connecting a last one of the plurality of memory chips different from the first memory chip to a second number of rD output signal pins on the substrate, the second number being equal to the predetermined second line number, wherein the rD output lines are configured to deliver read data output signals generated or re-driven by one or more of the plurality of memory chips to the memory controller; and rD signal interconnection lines arranged on the substrate, wherein the rD signal lines are operable to establish re-driven read data connections between the plurality of memory chips and to supply generated or re-driven read data signals from a preceding memory chip to a succeeding memory chip in the first direction.