1. A method comprising: identifying a pattern at a particular layer of a circuit design layout that does not meet at least one constraint; for the identified pattern, identifying a plurality of different decomposition solutions that each divides the identified pattern into at least two regions; at a computer, performing at least one simulation on each of the plurality of decomposition solutions to assess a manufacturing pattern that will result from each of the decomposition solutions; for the identified pattern, selecting a decomposition solution from the plurality of decomposition solutions that meets the constraint based on results from the simulation; and replacing the identified pattern in the circuit design layout with the selected decomposition solution.