1. A set of masks for defining a layer of material in an integrated circuit, said set of masks comprising: a first mask having phase shifting areas in an opaque field which define at least a transistor gate area having a larger dimension and a smaller dimension in said layer, the phase shifting areas including a first phase shift area and a second phase shift area having respective lengths and widths, where destructive interference occurs between said first phase shift area and said second phase shift area; and a second mask which includes an opaque field including a gate portion corresponding to the transistor gate area, the gate portion having a first dimension at least as long as the larger dimension and a second dimension larger than the smaller dimension.