1. A method of simulating an integrated circuit design, the method comprising: accessing an optimized hierarchical netlist; determining a node order ranking of nodes in the optimized hierarchical netlist; partitioning circuits of the optimized hierarchical netlist with a static current driving scheme and then a dynamic current driving scheme based on the node order ranking; building a hierarchical data structure based on the partitioning; performing solving and integration using the hierarchical data structure to generate an order-ranked hierarchy engine; performing analysis on the order-ranked hierarchy engine; and exporting simulation data of the IC design based on the analysis.