1. A memory system comprising: a memory controller coupled to one or more memory modules, at least one of the memory modules including a buffer; wherein the memory controller is configured to convey a command to at least one of the memory modules in response to detecting that no memory requests addressed to the at least one of the memory modules have been received during a specified window of time; and wherein in response to the command, the buffer of the at least one of the memory modules is configured to enter a reduced power state.