1. A method for back-end-of-line variation modeling, comprising: defining a bounding box for a device within a design layout of a semiconductor arrangement, wherein a size of the bounding box is a function of patterns surrounding the device; determining a back-end-of-line variation parameter for the bounding box; applying, using a computing device, the back-end-of-line variation parameter as a back-end-of-line constraint for simulation of the design layout; and modifying a physical feature of the design layout based upon a result of the simulation, wherein the design layout is implemented in fabrication of the device.