1. A signal processing circuit comprising: an input for receiving an input pattern-data array having values and data order significance; a series of processor blocks processing a pattern-data array to provide improved human perception of the pattern-data array; a feature detector receiving a pattern-data array to identify a predetermined feature in the pattern-data array; and a power management circuit receiving a mode command and operating: (1) in a first mode to activate a first set of the processor blocks to process the input pattern-data array to provide a first processed pattern-data array for output on a human machine interface, the first processed pattern-data array offering improved human perception quality on the human machine interface over the input pattern-data array, and (2) in a second mode to activate a second set of the processor blocks different from the first set to process the input pattern-data array to provide a second processed pattern-data array for processing by the feature detector, the second processed pattern-data array offering reduced human perception quality on the human machine interface compared to the first processed pattern-data array, the second set of processor blocks consuming less power than the first set of processor blocks; wherein the first and second set of processor blocks include perception-enhancing circuits enhancing the human perception quality of pattern-data arrays and wherein the first set of processor blocks activates more of the perception-enhancing circuits than the second set of processor blocks; and wherein the second set of processor blocks operating together provide better accuracy in the feature detector than would be provided by the process blocks excluded from the second set of processor blocks operating together.