1. A semiconductor device manufacturing process evaluation method comprising: acquiring first wiring pattern data corresponding to a shape of a wiring pattern on a layer in a semiconductor device, on the basis of a first image obtained by imaging a sample which permits imaging of said wiring pattern; generating evaluation CAD data which synthesizes CAD data of a plurality of layers, which includes wiring CAD data of the layer with said wiring pattern; making position coordinates of the first wiring pattern data coincide with position coordinates of a wiring pattern contained in the wiring CAD data, and producing synthesis data by synthesizing the first wiring pattern data and the evaluation CAD data; and quantizing, based on the synthesis data, a degree of overlapping between the first wiring pattern data and a pattern in the CAD data of a layer other than the layer with the wiring pattern.