1. A pattern correcting method comprising: computing, using a computer, a distribution of pattern coverages on a design layout of a circuit pattern in a vicinity of a position where an on-substrate pattern corresponding to the design layout becomes an error pattern when the on-substrate pattern is formed on a substrate; setting an area on the design layout as an addition area so that an amount of change in the distribution of the pattern coverages, after adding an addition pattern to the design layout, becomes smaller than the amount of change before adding the addition pattern; generating addition pattern candidates to be added to the addition area; and selecting an addition pattern to be added to the design layout, from the addition pattern candidates on the basis of a predetermined selection criterion, and adding the selected addition pattern to the addition area.