1. A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) semiconductor device comprising: a delay locked loop (“DLL”) circuit, which compensates for skew of an input clock signal and generates an output clock signal; an output unit, which buffers data stored in the DDR SDRAM semiconductor device and outputs the data to the outside of the DDR SDRAM semiconductor device; and an output control unit, which deactivates the output unit while the DLL circuit performs a locking operation on the input clock signal.