1. A device comprising: an image sensor providing signals generating image data associated with an image; and a processor having integrated on a common wafer a CPU, a multi-core processor for processing image data associated with the image, and a common synchronization register, wherein the multi-core processor includes multiple processing units connected in parallel, each of the multiple processing units storing one or more synchronization bits for identifying other processing units that are functioning together to process the image data therewith, and the common synchronization register contains therein synchronization bits from each of the multiple processing units; wherein the CPU is configured to load each of the multiple processing units with instructions; and wherein the CPU is configured to write the synchronization bits from each of the multiple processing units to the common synchronization register upon completion of the loading of instructions to all of the multiple processing units.