1. A method for floorplan visualization comprising the steps of: receiving design information for an integrated circuit design comprising one or more subsystems; generating one or more gate count estimates for said one or more subsystems of said integrated circuit design; generating one or more gate density estimates for gates of said one or more subsystems mapped to one or more programmable areas of a programmable platform device; and generating a visual representation of one or more area estimations of said one or more subsystems based on said one or more gate count estimates and said one or more gate density estimates.