1. A method for predicting lateral position information about a feature represented in an integrated circuit layout for use with an integrated circuit fabrication process, where the process projects an image onto a resist, the method comprising: providing a lateral distribution of intensity values of the image at different depths within the resist; and predicting a lateral position of an edge point of the feature in dependence upon a particular resist development time, and further in dependence upon the intensity values at more than one depth within the resist.