1. An image processing circuit comprising: a plurality of memories for storing line pixels of a frame constituting an image; a specific pixel detecting unit for obtaining, for pixels of an arbitrary N×N (N is a natural number) array of the frame of the image sequentially read from the plurality of memories, a luminance difference value which is a difference of luminance between an observation pixel positioned at a center of the array and each of other (N×N−1) pixels, detecting a first minimum pixel (1) having a minimum luminance difference value among a plurality of pixels adjacent to the observation pixel, detecting a first minimum pixel (2) having a minimum luminance difference value from the observation pixel among three pixels opposite to the first minimum pixel (1) relative to the observation pixel, detecting a second minimum pixel (1) having a minimum luminance difference value from the observation pixel among adjacent pixels on a side one pixel outside the first minimum pixel (1), and detecting a second minimum pixel (2) having a minimum luminance difference value from the observation pixel among adjacent pixels on a side one pixel outside the first minimum pixel (2); and a pixel interpolating unit for applying filter coefficients having predetermined weights to the observation pixel and specific pixels including the first minimum pixel (1), the first minimum pixel (2), the second minimum pixel (1) and the second minimum pixel (2) which are detected at the specific pixel detecting unit, applying filter coefficients having weights corresponding to the luminance difference value and a distance from the observation pixel to pixels other than the specific pixels in the N×N pixels, obtaining a total sum of results of applying each filter coefficient to each pixel, and dividing the total sum by a total sum of filter coefficients of N×N pixels to obtain an interpolated value for the observation pixel.