1. A method comprising: testing an integrated device comprising a plurality of logic nodes with a set of functional vectors; storing a set of data in a register, the data represents a logic state of the plurality of logic nodes after testing; comparing the set of data to the set of functional vectors to determine if there is a clock cycle with a miscompare between the set of data and the set of functional vectors; and unloading the register prior to clock cycle of the miscompare.