1. A method for performing timing analysis on a user design that has been placed on a programmable integrated circuit, the method comprising: generating edge masks to annotate edges in a graph that represents at least a portion of the user design, the edge masks indicating whether a source or destination point is reachable from a corresponding one of the edges; performing at least one depth first search along a time critical path in the graph between the source and the destination points, the at least one depth first search being prevented by the edge masks from analyzing paths that do not lead to the source point or the destination point; and modifying the placement of the user design on the programmable integrated circuit in response to the at least one depth first search.