1. A timing verification method for LSI test data comprising the steps of: generating a test circuit by a test circuit generation tool; extracting information required to create a timing script text for performing static timing analysis from the test circuit; generating the timing script text based on the extracted information and default timing information; performing static timing analysis by using the timing script text to acquire timing information whose timing has been verified; and generating a test pattern by an automatic test pattern generation (ATPG) tool based on the timing information whose timing has been verified.