1. A video hardware engine comprising: a video hardware accelerator unit; a shared memory coupled to the video hardware accelerator unit; a scrambler coupled to the shared memory; a vDMA (video direct memory access) engine coupled to the scrambler; and an external memory coupled to the vDMA engine, wherein the scrambler is configured to receive an LCU (largest coding unit) from the vDMA engine, wherein the LCU comprises N×N pixels, and the scrambler is configured to scramble N×N pixels in the LCU to generate a plurality of blocks with M×M pixels, where N and M are integers and M is less than N.