1. A deblocking filtering apparatus comprising a microprocessor configured to: determine a boundary among four boundaries corresponding to four sides of a current block, the determined boundary being located between the current block and a neighboring block adjacent to the current block; determine a plurality of corresponding filtering directions for boundary pixels along and in the determined boundary of the current block by selecting, per each boundary pixel of the boundary pixels, each of the plurality of corresponding filtering directions from among a plurality of candidate directions based on each pixel value difference between relating pixels positioned, with respect to said each boundary pixel, in every direction of the plurality of candidate directions; determine a filtering direction for the boundary of the current block, by selecting the determined filtering direction mostly selected from among the plurality of the determined corresponding filtering directions for said each boundary pixel of the boundary pixels, wherein each of the plurality of the determined corresponding filtering directions corresponds to said each corresponding filtering direction for said each boundary pixel of the boundary pixels; select pixels for filtering based on the determined filtering direction with respect to said each boundary pixel of the boundary pixels; determine whether to perform the filtering for the determined filtering direction depending on a first condition on a relationship between pixel values of the selected pixels for filtering, with respect to said each boundary pixel of the boundary pixels; and perform the filtering with respect to the selected pixels for filtering in the determined filtering direction, depending on the determination of whether to perform the filtering, the filtering being performed, for all the boundary pixels, in the same determined filtering direction, wherein said each pixel value difference is calculated corresponding to said each boundary pixel of the boundary pixels.