1. A system comprising: a master device; a first memory module including, a plurality of integrated circuit memory devices to store first, second and third data, a first integrated circuit buffer device coupled to the plurality of integrated circuit memory devices; a second memory module including a plurality of integrated circuit memory devices to store fourth data, a second integrated circuit buffer device coupled to the plurality of integrated circuit memory devices; a first signal path coupled to the master device and the first integrated circuit buffer device; a second signal path coupled to the first integrated circuit buffer device and the second memory module; a third signal path coupled to the second memory module and the master device; wherein the system is operable in a first and second mode of operation, wherein: during the first mode of operation first data is transferred from the first integrated circuit buffer device to the master on first signal path and fourth data is transferred from the second integrated circuit buffer device to the master on the third signal path; and during the second mode of operation second data is transferred from the first integrated circuit buffer device to the master device on the first signal path and third data is transferred from the first integrated circuit buffer device to the second memory module on the second signal path, and from the second memory module to the master device on the third signal path.