1. A method for testing an electronic circuit, comprising: defining a first initial vector; defining at least one segment within the first initial vector; offsetting the first initial vector a predetermined amount within the at least one segment; defining a counter loop comprising loops of the first initial vector within the at least one segment to produce a first set of vectors in accordance with the counter loop; defining a progressively changing variation of the first initial vector for each loop of the counter loop so at least one vector of the first set of vectors varies from the first initial vector; and coupling the at least one segment having the first set of vectors including the varied at least one vector to produce a final pattern for a circuit under test.