1. A memory device comprising: a plurality of pipeline stages for accessing data; a plurality of clock domains, each clock domain having circuitry controlled by a separate clock; a clock control circuit configured to selectively supply clock signals to the clock domains so that the clock domains are all activated in advance of, and corresponding to, when the clock domains are needed for a corresponding pipeline stage, all of the clock domains being activated sufficiently in advance so that a clock domain turn-on latency is transparent to a data access.