1. A video display controller for use in a color image display system for expanding a monochrome image pattern stored in a display memory in the form of one bit per image pixel to a color image pattern having multiple bits signifying foreground and background color of each pixel, and integrating such multiple bits with the stored bit pattern to derive a corresponding color image; such video controller comprising: a bit expander circuit including a source latch for storing the pixel bits of a part of said monochrome image; bits per pixel means for setting the number of bits per pixel in the expanded color image of said part of said monochrome image, to thereby define the extent of the multiple bit expansion to be performed; source tracking means which monitor the contents of said source latch and signal when to reload said source latch from said display memory; and expansion logic circuit means having inputs connected to outputs of said source latch, said bits per pixel means, and said source tracking means; said expansion logic circuit means having outputs at which it produces signals respectively representing the contents of said source latch and a number of consecutive bits corresponding to an expansion of the contents of said source latch, the number of consecutive bits in such expansion which correspond to each bit in the source latch being as defined by said bits per pixel means; pattern alignment means for shifting the signals at the outputs of said expansion logic circuit means so as to correspond to the positioning of destination words stored in said display memory; pattern generating circuit means including a foreground color register programmable with pixel values to be substituted for "1" pixel bits of said monochrome image; a background color register programmable with pixel values which are to be substituted for "0" pixel bits of said monochrome image; a single-bit register programmable to control whether "0" pixel bits in said monochrome image pattern are to remain unchanged or are to be replaced by pixel values stored in said background color register; a destination latch for temporarily storing destination words stored in said display memory; and multiplexing means which selects among the contents of said foreground color register, said background color register and said destination latch under control of said single-bit register and said pattern alignment means; said multiplexing means having an output at which it produces new destination words for replacing destination words currently stored in said display memory; and control means which sequence the reading of said display memory and storage of data therefrom in said source latch and in said destination latch, and the writing of said new destination words provided by said multiplexing means into said display memory.