1. A method for verifying densities in a semiconductor device layout, said method comprising: defining rules regarding device feature density gradients; receiving a layout of a device level including said device features; dividing at least a portion of said layout into a plurality of windows; determining average densities of said device features in each of said plurality of windows; determining device density gradients in said layout based on said average densities; comparing said device density gradients to said device feature density gradient rules; and identifying any areas in which one of said device density gradients violates said rules regarding device feature density gradients.