1. A method of measuring neighboring effects in an integrated chip design comprising the steps of: determining thresholds for identifying significant voltage droop and in the process evaluating decoupling capacitance in said integrated chip design and the local effects of decoupling capacitors in voltage droop caused by said integrated chip design; combining charge values for said decoupling capacitors to more easily identify neighboring effects; counting neighbors below the determined threshold to indicate if a current area could be a victim of neighbor effects; and adjusting warning thresholds based on the number of neighbors below a determined threshold for a given area.