1. An imaging system comprising: a plurality of pixels configured to convert light into a charge; one or more amplifier transistors configured to convert a charge from the plurality of pixels; one or more selection transistors configured to select a row or column of the plurality of pixels to be read out; one or more reset transistors configured to reset at least one of the plurality of pixels; a pixel array including the plurality of pixels arranged in one or more shared pixel architectures, the array being arranged in a plurality of rows and columns and further including a plurality of transfer gate transistors, wherein each of the plurality of transfer gate transistors corresponds to one of the plurality of pixels; a plurality of storage capacitors, one of the plurality of storage capacitors electrically connected in series with one of the plurality of pixels via one of the plurality of transfer gate transistors disposed therebetween, each storage capacitor having capacitance for storage of an accumulated charge representing a plurality of charge dumps from the connected pixel, each of the rated in the connected pixel; a timing circuit in communication with each storage capacitor and configured to control the flow of charge from each storage capacitor to a floating diffusion node; a first silicon layer upon which the plurality of pixels, the plurality of storage capacitors, and the plurality of transfer gate transistors are disposed; and a second silicon layer upon which at least one of the one or more amplifier transistors, selection transistors, and reset transistors are disposed.