1. A method of modeling charge distribution associated with steps on FinFET sidewalls for estimating variability in device performance, comprising: inputting structure parameters and simulation parameters for a FinFET structure; identifying a semiconductor-oxide interface of the FinFET structure, the interface including a plurality of atomic steps and a plurality of trapped charges; distributing charges at the semiconductor-oxide interface; and performing device simulation and current-voltage analysis upon generating samples of a given number of devices.