1. A method of generating a set of defect candidates for a wafer, the wafer comprising at least one die manufactured according to a mask, the mask being prepared by combining a plurality of layout areas, the method comprising: generating, by a hardware processor, a filtration area according to a graph operation of one or more of the plurality of layout areas; and generating the set of defect candidates having positions outside the filtration area, wherein the plurality of layout areas comprises a layout area including a layout design of a digital circuit clock, an analog circuit block, a memory circuit block, a power-device circuit block, or an intellectual property (IP) circuit block.