1. A method comprising: generating a write strobe signal to latch output data into a memory unit comprising one or more dual data rate synchronous dynamic random access memory (DDR-SDRAM) devices, the write strobe signal having an edge transition at approximately the center of a data window corresponding to the output data; and delaying a first receive clock signal by a first delay period using a delay locked loop (DLL) circuit to generate a first delayed receive clock signal, the first delayed receive clock signal being used to latch incoming data from the memory unit.