1. A computer-implemented method of performing dynamic voltage-frequency scaling of an integrated circuit, the method comprising: performing statistical timing analysis using a canonical form of a clock, the canonical form of the clock being a function of variability in voltage; obtaining, using a processor, a canonical model expressing timing slack at each test location of the integrated circuit as a function of one or more sources of variability, one of the one or more sources of variability being voltage; determining, using the canonical model, a clock period value or a voltage value based, respectively, on selecting a desired voltage or a desired clock period; and controlling a physical implementation of the integrated circuit according to the clock period value and the desired voltage or the voltage value and the desired clock period to perform the dynamic voltage-frequency scaling.