1. A method for inspecting a chip layout, comprising: providing a chip layout having a plurality of patterns designed according to a design rule; performing a first inspection to the plurality of patterns according to the design rule; determining patterns violating the design rule, as violating patterns, and corresponding violation values; determining violating patterns having a minimum violation value among the violating patterns; classifying the violating patterns having the minimum violation value into at least one sub-category based on characteristics of the violating patterns having the minimum violation value; and performing a second inspection on a selected violating pattern from the sub-category to determine whether the selected violating pattern and other violating patterns in the sub-category satisfy fabrication process conditions.