1. An apparatus for aligning a data signal and a data clock signal received from a memory in a computer system, comprising: a data input that receives the data signal from the memory; a clock input that receives the data clock signal from the memory; an offset mechanism that determines an offset between the data clock signal and the data signal; a comparison mechanism that determines if the offset is outside a valid range; and an adjustment mechanism that adjusts a delay between the data clock signal and the data signal if the offset is outside of the valid range.