1. A buffer chip for actuating a memory arrangement, comprising: a first data interface for receiving a first data item which is to be written in the memory arrangement and for sending a second data item which is read from the memory arrangement; a conversion unit for parallelizing the received first data item and for serializing the second data item; a write buffer for storing the parallelized first data item; a second data interface for writing the parallelized first data item to the memory arrangement via a memory data bus and for receiving the second data item read from the memory arrangement via the memory data bus; and a control unit configured to stop the first data item from being written from the write buffer via the second data interface according to a write command, upon receiving a subsequent read command, and read the second data item from the memory arrangement into the buffer chip via the second data interface.