1. A method for converting a software assembly program to a hardware design, said method comprising the steps of: creating a machine level syntax tree (MST) representation of the software assembly program in a given software binary program; compiling the MST representation into a Control and Data Flow Graph (CDFG) representation of the software assembly program by a processor controlled by an MST engine; compiling the CDFG representation of the software assembly program into a hardware description language (HDL) state machine; compiling the HDL state machine into a Register Transfer Level (RTL) VHDL or Verilog language; and compiling the RTL VHDL or Verilog language onto a hardware representation onto one or more programmable circuit devices using a synthesis program and a physical design program.