1. A voltage image enhancement system comprising: a computer configured to run a test processing sequence; a source adapted to stimulate electrical interconnects of a device under test with energy as part of a test processing sequence; a controller adapted to provide signal inputs and control a device under test during the test processing sequence; a scan rate synchronizer connected to the computer and the controller configured to synchronize the scan rate of the source with the internal clock rate of the device under test such that the scan rate of the source and the internal clock rate of the device under test are substantially similar and thereby ensuring that excitation of the device under test by the source will occur during one or more transistor switching events associated with one or more said electrical interconnects of the device under test, wherein said scan rate synchronizer further adjusts a phase of said signal inputs to correspond to phase of said source; a detector configured and positioned to detect emissions from the device under test that result from the stimulation by the source, said detector outputs data comprising voltage data associated with energy received by the detector; and a post-scan processing unit connected to the detector configured to create a voltage image comprising data associated with said one or more electrical interconnects of the device under test based on stimulation of the electrical interconnects of the device under test by the source during the one or more transistor switching events that occurs at the same time the source excites the electrical interconnect, wherein said post scan processing unit further removes data collected by the detector while the source was not oriented on said one or more electrical interconnects or when said device under test is not undergoing said one or more transistor switching events associated with one or more said electrical interconnects of the device under test; wherein said computer controls said source to stimulate said one or more electrical interconnects a plurality of scans, said post scan processing unit then averages data collected for each scans; wherein said post scan processing unit is further configured to collect all said data during said detector's pixel interval and perform algorithmic processing of said data to create said image.