1. A method for cell-aware fault model generation comprising: determining defects of interest for a cell; using a computer, performing analog fault simulation on a transistor-level cell netlist to identify detectable defects from the defects of interest and specified detection conditions, including simulating at least some of the defects of interest using fault sensitivity analysis (FSA); generating cell-aware fault models for the detectable defects from the detection conditions; and outputting the cell-aware fault models.