1. A process for preparing an electronics structure, said process comprising the following steps: a) providing a substrate stack; b) coating the substrate stack with a multi-layer hardmask stack; c) coating a topmost layer of the hardmask stack with a resist; d) developing a pattern in the resist; e) transferring the pattern developed in the resist into at least the topmost layer of the hardmask stack; f) blocking a portion of the pattern transferred into the topmost layer of the hardmask stack to protect a blocked portion of the pattern against being transferred deeper into the multi-layer hardmask stack; and g) transferring an unblocked portion of the pattern through the multi-layer hardmask stack into the substrate stack.