1. A method for analyzing integrated electric circuits, which comprises the following steps: a) providing a circuit network having circuit elements, the circuit elements being determined by form, property information, and position information selected from the group consisting of absolute position and relative position within the circuit network; the form, property information, and the position information being stored in at least a part of a file on a storage unit of a computer system, and the circuit elements of the integrated electric circuit being produced serially in a production including successive production steps; b) selecting at least a part of the circuit network; c) producing an image of the at least a part of the circuit network selected in step b) on the computer system, from the information stored in the storage unit regarding the circuit elements of the at least part of the circuit network; d) producing on the computer system at least one circuit-network image of at least one new circuit network by starting from the produced image from step c) of the at least part of the circuit network and omitting information about circuit elements being produced in a same production step and in successive production steps of the production process; e) checking the at least one circuit-network image produced in step d) of the circuit networks for correctness by using predefined testing rules to determine faults; and f) individually marking the at least one circuit-network image when the at least one circuit-network image contains a fault determined in step e).