1. A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device, the hybrid mask set comprising: a first subset of one or more multi-layer masks (MLMs) for a first group of the plurality of layers, each MLM including a plurality of different images for different layers, the different images for different layers being separated by an image spacer having a first width; a second subset of one or more masks for a second group of the plurality of layers, each mask including a plurality of similar images for a common layer, each image being separated by a scribe street having a second width narrower than the first width; wherein, the integrated circuit is created using the first and second subsets of masks.