1. A semiconductor device verification system for verifying layout data generated by layout design of a semiconductor device, the system comprising: a pattern matching verification system for performing adaptability verification of the layout data and reference layout data including layout data for general semiconductor integrated circuits, about data included in a compared cell list including a cell extracted from the layout data and for outputting an adaptability verification result and interference pattern information; and a physical verification system for extracting an interference pattern design rule applied to the interference pattern information from a design rule for the general semiconductor integrated circuits, for outputting a verification result obtained by verifying the layout data, the interference pattern information, and the compared cell list with the interference pattern design rule, for extracting inadaptable layout data not adaptable to the compared cell list and adaptable layout data adaptable to the compared cell list from the layout data by performing adaptability verification of the compared cell list and the layout data, and for outputting a verification result obtained by verifying the inadaptable layout data and the adaptable layout data with the design rule.