1. An integrated memory cube which to external circuitry emulates a single memory chip architecture, said integrated memory cube comprising: a combination memory chip and logic chip stack including (i) N memory chips (wherein N.gtoreq.2) each having M storage devices (wherein M.gtoreq.2), along with two substantially parallel planar main surfaces and an edge surface, (ii) a logic chip electrically connected to each of the N memory chips for coordinating external circuitry communication with the N.times.M storage devices of the stack, said electrically connected logic chip and N memory chips having an integrated memory architecture that emulates to said external circuitry a single memory chip architecture with said N.times.M storage devices, wherein said external circuitry addresses said stack through said logic chip as said single memory chip architecture, said logic chip also having two parallel planar main surfaces and an edge surface, and (iii) at least one planar main surface of each chip in the stack being coupled to a planar main surface of an adjacent chip in the stack, the edge surfaces of the N memory chips and the edge surface of the logic chip aligning to form at least one side surface of the stack, said stack also having an end surface disposed parallel to the planar main surfaces of the chips in the stack.