1. A computer-implemented method, performed on at least one computing device, of verifying an integrated circuit (IC) layout, the method comprising: obtaining data about a process variation band for at least one physical feature in the IC layout; determining electrical voltage-based process variation band thresholds for the at least one physical feature in the IC layout; determining whether the process variation band for the at least one physical feature in the IC layout meets design specifications for the IC layout based upon the voltage-based process variation band thresholds for the at least one physical feature in the IC layout; and modifying the IC layout in response to a determination that the process variation band for the at least one physical feature does not meet the design specifications.