1. A semiconductor device design method performed by at least one processor, said method comprising: extracting, using a resistance and capacitance (RC) extraction tool, at least one first parasitic capacitance among electrical components inside one or more regions of a plurality of regions in a layout of a semiconductor device; extracting, using the RC extraction tool, at least one second parasitic capacitance among electrical components outside the regions of the plurality of regions; and combining, using a netlist generator tool, the extracted first and second parasitic capacitances into a netlist representing the layout, wherein the RC extraction tool is configured to extract the first parasitic capacitances inside at least one region of the plurality of regions using a methodology more accurate than that for extracting the second parasitic capacitances.