1. A computing system comprising: an input source; a processing core having access to a dedicated cache memory, the processing core configured to direct operations of the computing system, the processing core configured to store and retrieve data to and from the dedicated cache memory respectively; an audio circuit; an image decoder circuit, the image decoder circuit including: a first onboard memory; a second onboard memory; a third onboard memory; an inverse quantization component; an inverse discrete cosine transform component; a filter circuit; and an adder; a memory interface coupleable to a shared memory, the shared memory configured to store audio data, the shared memory configured to store compressed image data from the input source, the memory interface coupled to the processing core and the decoder, the memory interface configured to arbitrate access to the shared memory; a bus configured to carry data between the processing core and the memory interface, the bus configured to carry the image data between the decoder and the memory interface, the bus having sufficient bandwidth to transfer data in real time between the shared memory and the decoder.