1. A computer system for built-in testing of an unused element on a semiconductor chip, the system comprising: the chip, comprising: a plurality of chip elements, the plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element comprising one of a masked element and a redundant element, the at least one unused element disabled from performing the respective function and configured to be selectively enabled as an active element; and a built-in self test (BIST) engine, the chip configured to perform a method comprising: concurrently performing the respective functions of the respective active elements and a BIST test of the at least one unused element by the BIST engine, the BIST test comprising: inputting an input test pattern to the unused element; receiving an output test pattern based on the input test pattern from the unused element; comparing the input test pattern to the output test pattern; and determining whether the unused element passed or failed the testing based on the comparison.