1. A method for analyzing defects in electronic circuit patterns comprising the following steps: a step for detecting a defect in an inspected object and storing position information for said detected defect; a step for collecting detailed information of said defect for which said position information is stored and storing said collected detailed information in association with said defect position information; a step for electronically testing said inspected object and storing position information for a position at which a fault is generated in said electronic test; a step for comparing said stored defect position information and said fault generating position information; a step for classifying said detected defect based on results from said comparing step; and displaying information relating to said classified defect.