1. A semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and command and address signals to the memory chips and data signals to and from the memory chips via a clock, address, command and data bus inside the module and which forms an interface to an external primary memory bus, the semiconductor memory module comprising: an even number of buffer chips arranged on the semiconductor memory module wherein all of the memory chips are connected to two respective buffer chips at least by one signal line type from the group comprising clock signal lines, data signal lines and command and address signal lines and to only one of the two buffer chips by the remaining signal lines from the group, and the sum of electrical signal propagation times for the clock and command and address signals via their lines from one buffer chip to a respective one of the memory chips and the electrical signal propagation times for the data signals from this memory chip to the other buffer chip during the read operation is the same for all of the memory chips; and control means for controlling respective data write and read operation to or from the memory chips are provided in order to drive the clock signals and command and address signals in the same respective direction as data signals via the bus inside the module when data are being written and read.