1. An image processing circuit, comprising: a full search engine, which executes a full search to generate a sum of absolute differences (SAD) distribution according to a reference image and a current image, wherein the SAD distribution comprises a plurality of sums of absolute differences; and a frame rate conversion (FRC) engine, which generates an interpolated image according to the reference image, the current image and a plurality of control parameters, wherein the FRC engine determines whether the number of the sums of absolute differences which are larger than a smallest threshold is equal to 1 or less than 1 when part of the sums of absolute differences is not larger than the smallest threshold, the current image comprises a good scene when the number of the sums of absolute differences which are larger than the smallest threshold is equal to 1 or less than 1, the current image comprises a periodic scene when the number of the sums of absolute differences which are larger than the smallest threshold is larger than 1, the FRC engine determines whether all of the sums of absolute differences are larger than an average pixel level (APL) when all of the sums of absolute differences are larger than the smallest threshold, the current image comprises a flash scene when all of the sums of absolute differences are larger than the APL, the current image comprises a bad scene when part of the sums of absolute differences is not larger than the APL, and the FRC engine adjusts at least one of the control parameters according to the good scene, the periodic scene, the flash scene or the bad scene.