1. A method for deriving permutations of a layout of standard cells stored in a standard cell library and used in the design of an integrated circuit device, comprising: iteratively placing, using a processor-based system executing program instructions, each standard cell of the standard cells adjacent to each side and corner of itself and each other standard cell of the standard cells to produce an interim test layout comprising a first plurality of cell pair permutations; reducing the cell pair permutations by: identifying at least one of: illegal or redundant left-right and top-bottom boundaries as determined with respect to defined design rules, and removing any cell pair permutations using the identified boundaries to generate a final test layout comprising a second plurality of cell pair permutations; performing a design rule check on the final test cell layout to flag a possible problem associated with any cell pair permutation; and identifying the standard cells comprising any cell pair permutation for which the possible problem has been flagged.