1. A memory control system for controlling addressing of memory arrays in a computer system which can accept memory arrays of various storage capacity, each memory array including multiple array banks, said memory arrays coupled to a memory backplane area of said computer system having a plurality of connectors corresponding to said plurality of memory arrays, and said memory backplane coupled to an input address bus through said memory control system, said memory control system comprising; address shifter means including multiplexer means having a plurality of segments, each segment coupled to receive a plurality of input address lines of said input address bus and having an address output, said multiplexer means having a control input, means for establishing a control signal determined by the largest memory array in the backplane, means for decoupling the address output of each multiplexer means segment to a corresponding backplane connector, said multiplexer means placing at said address output of each segment said plurality of input address lines of said input address bus in accordance with said control signal such that proper memory addressing is established.