1. A computer-implemented method of determining a feature failure coefficient for an integrated circuit design feature, comprising: identifying a plurality of logical units in one or more integrated circuit designs; for each of the identified logical units, determining an amount of occurrences of an integrated circuit design feature in the logical unit, the integrated circuit design feature corresponding to a physical structure in an integrated circuit, and determining a failure rate of an integrated circuit portion corresponding to the logical unit; and correlating by a computer, the amounts of the occurrences of the integrated circuit design feature with the failure rates to determine at least one feature failure coefficient for the integrated circuit design feature.