1. An asynchronous semiconductor memory device comprising: a memory array configured to store data information; a first interface circuit configured to latch command and address information in response to a first strobe signal received by the asynchronous memory device; a read circuit configured to read data information from the memory array in response to the latched command and address information; a signal generator circuit configured to generate a third strobe signal based on a second strobe signal received by the asynchronous semiconductor memory device; and a second interface circuit configured to latch data read from the array by the read circuit in response to the second strobe signal and output the latched data read from the array and the generated the third strobe signal at least partially concurrently with the output of the latched data read from the array.