1. A system comprising: a non-transitory, computer readable storage medium for storing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than two; an EDA tool configured for: inputting a conflict graph having a plurality of vertices representing the circuit patterns; identifying a first vertex and a second vertex of the plurality of vertices, as candidate circuit patterns for inclusion in a same one of the photomasks; merging the first and second vertices to form a reduced graph; and detecting at least one or more vertex in the reduced graph having a conflict.