1. A circuit arrangement, comprising: a memory storage element; and processing logic coupled to the memory storage element and configured to perform anisotropic filtering using a texture including texture data stored in a memory address space and defined in a coordinate system having u and v axes, the processing logic configured to determine a line of anisotropy for the texture by determining lengths au and av respectively representative of distances in texels of the line of anisotropy along the u and v axes, determine a plurality of sample points along a line of anisotropy for the texture, wherein the plurality of sample points includes n sample points, determine a length ulen representative of a distance in texels between a first sample point and a second sample point of the plurality of sample points along the u axis, wherein the length ulen is based upon a length au of the line of anisotropy along the u axis divided by (n−1), determine a length vlen representative of a distance in texels between the first sample point and the second sample point along the v axis, wherein the length vlen is based upon a length av of the line of anisotropy along the v axis divided by (n−1), and the processing logic further configured to initiate a prefetch of texture data for a sample point among the plurality of sample points into the memory storage element using a stride value representative of a distance in the memory address space between sample points in the texture, wherein the stride value is based at least in part on the first length ulen and the length vlen, a width Uw of the texture in texels along the u axis and a data size D for each texel as follows: 
 stride= vlen *( Uw*D )+ ulen*D.