1. A method for identifying a candidate region including a physical defect in a semiconductor device, the method comprising: receiving an electrical test mismatch reported for a scan chain; identifying a suspect logical regionsuspect logical region electrically connected with the scan chain, the suspect logical regionsuspect logical region including a plurality of logic cones; adjusting a scope of the suspect logical regionsuspect logical region by: simulating data flow within the plurality of logic cones, generating a simulated scan chain output for the scan chain based on the simulated data flow within the plurality of logic cones, and excluding at least one of the plurality of logic cones from the suspect logical regionsuspect logical region based on a comparison of the electrical test mismatch and the simulated scan chain output; after adjusting the scope of the suspect logical region, generating a candidate defect region, the candidate defect region being defined to include physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.