1. A memory system comprising: a plurality of memory stacks, each memory stack including a plurality of memory circuits, where a first memory stack of the plurality of memory stacks includes: at least one memory circuit assigned to an address range, and at least one spare memory circuit; and an interface circuit operable to: communicate with the plurality of memory stacks and a memory controller; receive a triggering signal from the memory controller when a number of data read errors in the address range exceeds a predetermined threshold; and replace, during operation of the memory system, the at least one memory circuit assigned to the address range with the at least one spare memory circuit upon receiving the triggering signal from the memory controller, by which triggering signal the interface circuit is instructed to replace the at least one memory circuit.