1. A method of generating a set of defect candidates for a wafer, the wafer comprising at least one die manufactured according to a mask, the mask being prepared by combining a plurality of layout areas, the method comprising: generating, by a hardware processor, a filtration area according to a graph operation of one or more of the plurality of layout areas, and the graph operation comprising at least expanding or shrinking the one or more of the plurality of layout areas; generating the set of defect candidates having positions outside the filtration area; and at least one of the following conditions: (a) wherein the plurality of layout areas comprises a first layout area and a second layout area, a first peripheral edge of the first layout area arranged to be adjacent to a first peripheral edge of the second layout area on the mask, and the graph operation comprises: expanding the first layout area by shifting the first peripheral edge of the first layout area outwardly by a first predetermined distance; and generating the filtration area by subtracting the first layout area from the expanded first layout area; or (b) wherein the plurality of layout areas comprises a third layout area and a fourth layout area, a first peripheral edge of the third layout area arranged to be adjacent to a first peripheral edge of the fourth layout area on the mask, and the graph operation comprises: expanding the third layout area by shifting the first peripheral edge of the third layout area outwardly by a second predetermined distance; shrinking the third layout area by shifting the first peripheral edge of the third layout area inwardly by a third predetermined distance; and generating the filtration area by subtracting the shrunk third layout area from the expanded third layout area; or (c) wherein the graph operation comprises: generating a non-filtration area according to the plurality of layout areas; and generating the filtration area by subtracting the non-filtration area from a full area encompassing all the plurality of layout areas.