1. A layout checking method performed by at least one processor, comprising: analyzing, by the at least one processor, spaces among a plurality of layout segments of an integrated circuit to determine at least one first-type conflicted edge according to a first predetermined length; analyzing, by the at least one processor, spaces among the plurality of layout segments of the integrated circuit to determine a plurality of potential conflicted edges according to a second predetermined length different from the first predetermined length; determining, by the at least one processor, at least one second-type conflicted edge according to the plurality of potential conflicted edges; and checking, by the at least one processor, if at least one odd-vertex loop is formed in the plurality of layout segments according to the at least one first-type conflicted edge and the at least one second-type conflicted edge to determine if a violation occurs in the plurality of layout segments.