1. An integrated circuit, comprising logic configured to: receive a first plurality of symbols comprising real portions and complex portions; apply conjugate symmetry to the first plurality of symbols, producing a second plurality of symbols comprising no complex portions; transform the second plurality of symbols using an inverse fast Fourier transform, producing a third plurality of symbols; generate a short training field comprising at least one real portion of the third plurality of symbols; negate one or more repetitions of a group of bits in the short training field, generate a packet comprising wherein the short training field is part of a synchronization header and a long training field as part of the synchronization header; and use the packet for communication in a wireless network.