1. A method for determining customized defect detection inspection plan, comprising: fabricating a test chip; generating test chip data from the fabricated test chip; defining systematic signatures from the generated test chip data, wherein said systematic signatures define relationships between measurable metrics associated with said fabricated test chip and measurable layout attributes associated with a layout pattern of said fabricated test chip; identifying a yield relevant systematic signature from the defined systematic signatures; identifying the layout pattern associated with the yield relevant systematic signature; locating the identified layout pattern on a process module layer of a product chip; and defining a customized defect detection inspection or metrology methodology for detecting systematic defects on the process module layer based on the identified layout pattern associated with the yield relevant systematic signature.