1. A computer-implemented method of estimating integrated circuit (IC) yield, comprising: providing, to a computer, an IC layout, said IC layout including a set of geometric configurations; providing, to said computer, test site data from test sites including said set of geometric configurations, said test site data including a probability of a defect occurring within each of said set of geometric configurations; providing, to said computer, a set of systematic defects for said IC layout based on said test site data; assigning, by said computer, each of said set of systematic defects, corresponding to one of said set of geometric configurations, a weight based on a probability of a defect occurring in said one of said set of geometric configurations; performing, by said computer, a weighted critical area analysis on said IC layout using said weight for each of said set of systematic defects; computing, by said computer, a fault density value based on said weighted critical area analysis of said set of systematic defects; and comparing, by said computer, said fault density value to a predetermined value, derived from said set of geometric configurations as measured on said test sites, to estimate yield for said IC layout.