1. A computer-implemented method of determining variation in attributes in a design of an integrated circuit, the method comprising: repeatedly applying an estimation technique to each of a plurality of values of at least one variation parameter affected by fabrication of the integrated circuit, to obtain a corresponding plurality of estimated values, of a design attribute of at least one stage in said design; repeatedly performing on each estimated value, a calibration function, to obtain a plurality of calibrated estimates; wherein the calibration function depends on at least a pair of initialization values of the design attribute derived from a predetermined sample, with one initialization value in the pair being obtained by applying said estimation technique and another initialization value in the pair being obtained by a predetermined method known to be more accurate than said estimation technique; and storing in memory the plurality of calibrated estimates.