1. A design optimization method for reducing leakage power for a target circuit design specified by a machine-readable file, comprising: providing a computer-implemented model of timing constrained, leakage power reduction achievable by applying gate length modifications to cells in a circuit design as a function of a set of characteristics of circuit designs, wherein said set of characteristics includes starting slack, logic depth, power sensitivity to gate length modification and delay sensitivity to said gate length modification; determining values of said set of characteristics for a target circuit design; applying the computer-implemented model using said values to produce an indication of susceptibility of the target circuit design to optimization by a procedure to modify said target circuit design using said timing constrained, gate length modifications; and determining whether to execute the procedure to implement gate length modifications in the target circuit design, in response to the indication.