1. A method comprising: obtaining, using at least one computing device, a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes at least one stitched circuitry region; and modifying, using the at least one computing device, the IC chip layout to include a boundary identification identifying a boundary of the at least one stitched circuitry region at which stitching occurs, wherein the boundary identification takes a form of a negative space in the IC chip layout.