1. A built-in self-test (BIST) system for testing of embedded electronic devices, said BIST comprising: shift register device connected to an output pin of an embedded array of electronic devices being tested and for receiving a failure indication signal at a real-time output pin of said device under test, said shift register generating a unique signature in response to receipt of said failure indication; a device for determining whether said generated unique signature is represented in a table comprising known signature values and corresponding bitmaps of prior determined array defects for that device under test, wherein the need to bitmap the array is avoided when a known failure signature is determined.