1. A memory circuit including a plurality of memory cells all connected to a common input bus and a common output bus and each memory cell including data storage means and a control circuit, said control circuit comprising means for generating a data occupancy status signal, write control means responsive to data occupancy status signals from said memory cell and a selectable adjacent memory cell for controlling the writing of data from said input bus into said data storage means, and read control means responsive to data occupancy status signals from said memory cell and a selectable adjacent memory cell for controlling the reading of data from said data storage means to said output bus.