1. An integrated circuit (IC) method comprising: receiving an IC design layout having a main feature, the main feature including a first, second and third edge defining a first corner defined by an intersection of a first and second edges and a second corner defined by an intersection of the second and third edges; performing a dissection to the second edge such that the second edge is divided to include two corner segments and a center segment between the two corner segments; after performing the dissection, assigning a plurality of targets to the main feature, wherein the assigning includes: assigning a first target at a center point in the center segment of the second edge and a second target at a center point of the first edge; assigning a third target at the first corner and a fourth target at the second corner; assigning a fifth target at a central point on the second edge between the third target; after assigning the first, second, third, fourth and fifth targets, performing a first optical proximity correction (OPC) to the main feature for the first and second targets, and not the third, fourth, and fifth targets; thereafter, performing a second OPC to the main feature for the third target and the fourth target, and not the first, second, and fifth targets; and thereafter, performing a third OPC to the main feature for the fifth target, and not the first, second, third, and fourth targets, resulting in a modified IC design layout; and providing the modified IC design layout in a format accessible by a mask making tool.