1. A digital processing unit for multiplying two N-component mathematical quantities, X and Y, wherein each component is represented by an m bit digital word representative of a real portion and an m bit digital word representative of an imaginary portion, said unit comprising: (a) N complex multipliers each having an X input and a Y input, each input having m leads adapted to receive the real portion in parallel and m leads adapted to receive the imaginary portion in parallel, and an output having at least m+1 leads for the real portion and at least m+1 leads for the imaginary portion; (b) real portion summing means connected to the m+1 leads for the real portion at the output of each of said N complex multipliers for providing a real output component including at least m+2 parallel bits representative of the sum of the real portions from each of said complex multipliers; and (c) imaginary portion summing means connected to the m+1 leads for the imaginary portion at the output of each of said N complex multipliers for providing an imaginary output component including at least m+2 parallel bits representative of the sum of the imaginary portions from each of said complex multipliers.