1. A computer-implemented method for generating an inspection process for a wafer, comprising: separately determining a value of a local attribute for different locations within a design for a wafer based on a defect that can cause at least one type of fault mechanism at the different locations; determining a sensitivity with which defects will be reported for different locations on the wafer corresponding to the different locations within the design based on the value of the local attribute; and generating an inspection process for the wafer based on the determined sensitivity.