1. An object detection system for autonomous vehicles, comprising: a radar unit coupled to at least one ultra-low phase noise frequency synthesizer, configured for detecting the presence of one or more objects in one or more directions, the radar unit comprising: a transmitter for transmitting at least one radio signal to the one or more objects; and a receiver for receiving the at least one radio signal returned from the one or more objects; and the at least one ultra-low phase noise frequency synthesizer performing as a Local Oscillator (LO) for the radar unit, both the transmitted and the received signals, and thus determining the phase noise and the quality of the transmitted and the received radio signals, wherein the at least one ultra-low phase noise frequency synthesizer comprises: (i) at least one clocking device configured to generate at least one first clock signal of at least one first clock frequency; (ii) at least one sampling Phase Locked Loop (PLL), wherein the at least one sampling PLL comprises: (a) at least one sampling phase detector configured to receive the at least one first clock signal and a single reference frequency to generate at least one first analog control voltage; and (b) at least one reference Voltage Controlled Oscillator (VCO) configured to receive the at least one analog control voltage to generate the single reference frequency; and (c) a Digital Phase/Frequency detector configured to receive the at least one first clock signal and a single reference frequency to generate at least a second analog control voltage; and (d) a two-way DC switch in communication with the Digital Phase/Frequency detector and the sampling phase detector; (iii) at least one first fixed frequency divider configured to receive the at least one reference frequency and to divide the at least one reference frequency by a first predefined factor to generate at least one clock signal for at least one high frequency low phase noise Direct Digital Synthesizer (DDS) clock signal; (iv) at least one high frequency low phase noise DDS configured to receive the at least one DDS clock signal and to generate at least one second clock signal of at least one second clock frequency; and (v) at least one main Phase Locked Loop (PLL), wherein the at least one main PLL comprises: (a) at least one high frequency Digital Phase/Frequency detector configured to receive and compare the at least one second clock frequency and at least one feedback frequency to generate at least one second analog control voltage and at least one digital control voltage; (b) at least one main VCO configured to receive the at least one first analog control voltage or the at least one second analog control voltage and generate at least one output signal of at least one output frequency, wherein the at least one digital control voltage controls which of the at least one first analog control voltage or the at least one second analog control voltage is received by the at least one main VCO; (c) at least one down convert mixer configured to mix the at least one output frequency and the reference frequency to generate at least one intermediate frequency; and (d) at least one second fixed frequency divider configured to receive and divide the at least one intermediate frequency by a second predefined factor to generate the at least one feedback frequency.