1. A full-duplex transceiver comprising: a first signal processing circuit generating an outgoing signal z(t) and a replica signal r 2 (t), each being proportional to an input signal r 0 (t), for combining the outgoing signal with an incoming signal y(t) to form a combined signal r 1 (t) of magnitude proportional to a sum of magnitudes of the outgoing and incoming signals, and for processing the combined signal and the replica signal to produce a received signal p(t) representing the incoming signal, wherein the input signal and the outgoing signal respectively represent first and second sequences of data elements though patterns of periodic transitions between magnitude levels; a delay circuit supplying the input signal r 0 (t) to the first signal processing circuit with an adjustable delay controlled by a delay control signal supplied as input to the second delay circuit; and second signal processing circuit generating both the delay control signal and a soft decision sequence s(n) of data elements in response to the received signal, wherein the soft decision sequence represents the first data sequence also represented by the incoming signal.