1. A method of operating a synchronous circuit, comprising: applying a reference clock as an input to a voltage controlled delay line (VCDL) in said synchronous circuit, wherein said VCDL includes a plurality of delay stages to delay said reference clock input to said VCDL; obtaining a plurality of output signals at an output of said VCDL; and disabling one or more of said plurality of delay stages using a first set of two or more of said plurality of output signals.