1. A row command unit in an integrated circuit including a plurality of memory banks, comprising: a plurality of row control latches, each row control latch having an output coupled to a respective memory bank and having an enable terminal and a control terminal, the row control latch latching a signal applied on the control terminal when an active enable signal is applied on the enable terminal; a delay circuit having an output terminal coupled to the control terminals of the row control latches and having an input terminal, the delay circuit generating a row control signal on its output responsive to an activation signal applied on its input; and a bank control circuit coupled to the input terminal of the delay circuit and having input terminals adapted to receive respective bank address and bank control signals, the bank control circuit also having a plurality of output terminals, each output terminal coupled to a respective enable terminal of one of the row control latches, the bank control circuit operable to apply an active enable signal to one of the row control latches and to apply an active activation signal to the delay circuit responsive to the bank control and bank address signals.