1. A computer-implemented method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC), said method comprising: identifying, by a computing device, failing observation points in an IC layout, said failing observation points comprising latches and test points; determining, by said computing device, proximity geometry of said failing observation points in said IC layout; determining, by said computing device, if a proximity criteria for said failing observation points is met, based on said proximity geometry; identifying, by said computing device, faults associated with said failing observation points that meet said proximity criteria; and including, by said computing device, said faults associated with said failing observation points that meet said proximity criteria in a fault candidate set.