1. A video hardware engine comprising: a video hardware accelerator unit; a shared memory coupled to the video hardware accelerator unit, the shared memory being configured to store the plurality of blocks with M×M pixels received from a scrambler, and wherein the M×M pixels in the first block are linearly stored in the shared memory, the shared memory, while storing the first block, is configured to store M pixels in a first row of the first block followed by storing M pixels in a second row of the first block; the scrambler coupled to the shared memory; a vDMA (video direct memory access) engine coupled to the scrambler; and an external memory coupled to the vDMA engine, wherein the scrambler is configured to receive an LCU (largest coding unit) from the vDMA engine, wherein the LCU comprises N×N pixels, and the scrambler is configured to scramble N×N pixels in the LCU to generate a plurality of blocks with M×M pixels, where N and M are integers and M is less than N, and wherein the video hardware accelerator unit is configured to process the plurality of blocks to generate a plurality of processed blocks, each processed block of the plurality of processed blocks comprises M×M pixels.