1. An apparatus comprising: a plurality of physical memory circuits; and an interface circuit configured to: communicate between the plurality of physical memory circuits and a memory controller; simulate one or more virtual memory circuits for the memory controller using the plurality of physical memory circuits; receive, from the memory controller, a command to change an address timing of the one or more virtual memory circuits from a first address timing to a second address timing, wherein the change in the address timing causes a change in a precharge-to-active ratio of the one or more virtual memory circuits; and issue one or more commands, satisfying the change in the address timing, to one or more of the plurality of physical memory circuits, wherein the change in the address timing causes a change in a precharge-to-active ratio of the plurality of physical memory circuits.