1. A computer-implemented method of modeling stress in a packaged semiconductor device, comprising: selecting, using a computer, successive portions of a package layout for the semiconductor device, each of the successive portions of the package layout describing physical layout of at least one interconnect structure in the semiconductor device; for each portion of the successive portions of the package layout: (1) selecting a pre-defined layout from a library of pre-defined layouts based on the portion of the package layout, wherein the selecting of the pre-defined layout includes determining the pre-defined layout from the library that matches a number and type of interconnect elements, and a physical position of the interconnect elements of the selected portion; (2) obtaining, from the library of pre-defined layouts, pre-characterization information for the pre-defined layout that defines structural properties of the pre-defined layout; and (3) executing a modeling algorithm to determine a stress measurement for the portion of the package layout using the pre-characterization information as parametric input; and combining stress measurements for the successive portions of the package layout to determine a stress profile for the semiconductor device.