1. A method of forming fine patterns of a semiconductor integrated circuit, comprising: forming a mask layer over a semiconductor structure having a first region and a second region; removing a portion of the mask layer over the first region to expose the semiconductor structure; forming sacrificial layer patterns over the exposed semiconductor structure; forming spacers on sidewalls of the sacrificial layer patterns and the mask layer; removing portions of the spacers to create fine mask patterns; and patterning the semiconductor structure using the fine mask patterns to create fine patterns.