1. A liquid crystal display device, comprising: a plurality of data signal lines; a plurality of scanning signal lines intersecting with the plurality of data signal lines; a plurality of pixels arranged in a matrix to correspond to intersections between the plurality of data signal lines and the plurality of scanning signal lines, each of the pixels including a switching element that is on when the corresponding scanning signal line is in a selected state and is off when it is in a non-selected state, a pixel electrode connected to the corresponding data signal line via the switching element, a common electrode opposed to the pixel electrode, and a liquid crystal layer sandwiched between the pixel electrode and the common electrode; and a potential control section configured to control the potential of the common electrode, wherein when C sd is a parasitic capacitance formed between the data signal line and a drain of the switching element, C lc is a liquid crystal capacitance, C s is a storage capacitance, gray level 0 denotes black display, and gray level 255 denotes white display, when, in the case of alternate display of gray level 0 and gray level 255 every pixel, V H0 is a potential set for the data signal line to apply a positive potential required for display of gray level 0 to the pixel electrode, V L0 is a potential set for the data signal line to apply a negative potential required for display of gray level 0 to the pixel electrode, V H255 is a potential set for the data signal line to apply a positive potential required for display of gray level 255 to the pixel electrode, V L255 is a potential set for the data signal line to apply a negative potential required for display of gray level 255 to the pixel electrode, and V cenf255 is a potential of the common electrode at which flicker is minimum, and when, in the case of display of gray level 255 for all the plurality of pixels, V cen255 is a potential of the common electrode at which flicker is minimum, the potential control section sets a potential obtained by reducing V cenf255 by 1 4 · C sd C lc + C s + C sd ( V H 0 + V L 0 - V H 255 - V L 255 ) as V cen255 .