1. An enhanced four rank enabled buffer device, the buffer device comprising: input ports for receiving address and command data directed to one or more of up to four ranks of memory devices; one or more buffer circuits for driving one or more of the address and command data; four chip select input lines for selecting between the up to four ranks of memory devices; two chip select output lines for accessing one or two of the up to four ranks of memory devices; and a power savings means for causing one or more of the buffer circuits to be in an inactive mode when the chip select input lines are not active; said buffer device operable in a first mode to access the up to four ranks of memory devices when coupled to a second enhanced four rank enabled buffer device and said buffer device operable in a second mode to access the one or two of the up to four ranks of memory devices when not coupled to the second buffer device.