1. A refresh circuit for generating a plurality of refresh signals for a dynamic random access memory (DRAM) comprising memory cells subdivided into a plurality of memory cell banks such that the refresh signals are provided to the memory cell banks in one-to-one correspondence to refresh the memory cells comprising the respective memory cell bank, the refresh circuit comprising a plurality of edge-triggered flip-flops connected in series such that the data input signal to successive flip-flops in the series is provided by an output of the previous flip-flop in the series such that successive flip-flops generate a sequence of refresh signals in response to successive cycles of a clock signal commonly connected to each of the flip-flops, the refresh signals being connected to one-to-one correspondence to the memory cell banks and wherein an output of the last flip-flop in the series of flip-flops is provided via an inverter as the data input signal to the first flip-flop in the series to provide sequential termination of the refresh signals on a subsequent sequence of successive cycles of the clock signal.