1. A design verification apparatus for a semiconductor device, comprising: a storage for storing layout information of the semiconductor device, the layout information including information of interconnection regions and via regions; and a controller for oversizing each of the via regions by a determined value, and for dividing the interconnection regions into wire regions and cross regions, the cross regions corresponding to overlapping regions of the interconnection regions and the oversized via regions, the wire regions excluding the cross regions and extending between the cross regions, and the controller extracting at least one of the wire regions as a candidate having a potential risk of future disconnection defect on the basis of the length of the wire regions.