1. A layout parameter extraction device, comprising: layout data reading means for reading layout data; node generation information adding means for inputting node generation information including coordinates of nodes to be generated and node names capable of uniquely identifying the nodes, and for adding information for node generation to the layout data on the basis of the node generation information; circuit recognizing means, which receives the layout data to which the information for node generation is added, for recognizing a circuit represented by the layout data and storing a result of recognition as circuit information; node generating means, which receive the circuit information, for generating nodes on predetermined points of the circuit indicated by the circuit information on the basis of a shape of the circuit and generating nodes respectively on the coordinates on the basis of the information for node generation included in the received circuit information, for assigning node names capable of uniquely identifying nodes as names of the nodes generated on the coordinates, respectively, and for storing the nodes as node information; parasitic element extracting means for extracting parasitic elements from the layout data, connecting the extracted parasitic elements to the nodes on the basis of the node information, and for storing them as parasitic element information; and circuit output means for forming a circuit from the circuit information and the parasitic element information, and outputting a netlist of a result of formation.