1. A method, comprising: providing at least one buffer in a memory interface between a chipset and a plurality of memory modules, each module having a plurality of memory ranks, said at least one buffer allowing the memory interface to be split into first and second sub-interfaces, where the first sub-interface is between the chipset and said at least one buffer, and the second sub-interface is between said at least one buffer and the memory modules, such that said at least one buffer provides electrical isolation between the chipset and the memory modules; configuring said at least one buffer to latch data being transferred between the chipset and the memory modules, such that the first and second sub-interfaces operate independently but in synchronization with each other; and interleaving outputs of said at least one buffer.