1. A method of classifying defects on a wafer, comprising: receiving a plurality of images acquired by a charged particle beam, wherein said images respectively correspond to a plurality of chips having similar feature on an examined wafer; examining said images, such that at least a defect-free image and at least a defective image are found, wherein said defective image includes at least one defect feature corresponding to a defect on said chip; translating said defect-free image into a simulated layout that corresponds to a real layout of said chips, wherein said defect-free image is formed from a plurality of pixels and has at least a pattern, and at least two of said pixels located on an edge of said pattern are connected, so as to form said simulated layout; and comparing said defective image with said simulated layout to classify said defect on said chip, wherein the comparing step comprises mapping location of said defect feature into a mapped location of said simulated layout such that said defect is classified based on a structure located on said mapped location, said defect is classified as a hole defect when a hole is located on said mapped location, wherein said defect is classified as a line defect when said mapped location corresponds to a line between chips, and wherein said defect is classified as an omissible defect when said mapped location corresponds to neither a semiconductor structure nor a conductive line around said semiconductor structure.