1. A method of manufacturing integrated circuit field effect transistors comprising the steps of: forming on an integrated circuit substrate, a plurality of field effect transistors, each comprising spaced apart source and drain regions, a gate therebetween including a sidewall, a sidewall spacer on the sidewall and contacts comprising conductive material on the source and drain regions, wherein at least one of the plurality of field effect transistors may include undesired conductive material on the sidewall spacer thereof; performing Scanning Electron Microscope (SEM) analysis on the integrated circuit substrate to detect the undesired conductive material on the sidewall spacer; and etching the undesired conductive material from the sidewall spacer if the undesired material is detected by the SEM analysis.