1. A system comprising: a Field Programmable Gate Array (FPGA) to perform a machine learning algorithm using training data; a Peripheral Component Interface (PCI) controller to communicate with a Central Processing Unit (CPU) of a host computing device, and a memory hierarchy composed of Static Random Access Memory (SRAM) and Synchronous Dynamic Random Access Memory (SDRAM) associated with the FPGA and embedded Random Access Memory (RAM) within the FPGA, the training data being loaded onto at least a portion of the memory hierarchy and organized according to a streaming memory access order for streaming memory access by logic associated with the FPGA; and a control unit within the FPGA to direct the FPGA to: build a histogram based in part on at least a subset of the training data; build an integral histogram based in part on the histogram; and send a result of the machine learning algorithm to a First In First Out (FIFO) queue for presentation to the host computing device, the result being based at least in part on the integral histogram.