1. A method of testing an integrated circuit comprising component blocks of random logic in a manufacturing environment comprising the steps of: (a) performing built-in self tests, at least in part to test memory and data paths of the integrated circuit; (b) performing diagnostics tests, at least in part to test the component blocks of random logic individually; (c) performing stress tests using test vectors, at least in part to test the component blocks of random logic collectively; and (d) performing scan-based tests of the integrated circuit, at least in part to test for structural faults in the integrated circuit.