1. A method for performing maximum flow analysis on a portion of an integrated circuit layout, comprising: identifying a portion of an integrated circuit layout to analyze; tessellating the portion of the integrated circuit layout to form a configuration of space tiles, wherein the configuration of space tiles are based at least in part upon an object in the tessellated portion of the integrated circuit layout; analyzing the configuration of space tiles; determining by a computer processor of a computer aided design tool or of a electronic design automation system a maximum flow through the portion of the integrated circuit layout based at least in part upon results for analyzing the configuration of space tiles; generating a routing path based at least in part upon the results for determining the maximum flow; and routing an integrated circuit for fabrication based at least in part upon the routing path.