1. A method to transform a transformable virtual processor model to a user virtual processor model to simulate a user target processor, the method comprising: receiving a transformable virtual processor model, the transformable virtual processor model configured to perform, on a host processor system, a behavior and timing accurate simulation of a seed target processor, the transformable virtual processor model having a transformable instruction set and a transformable pipeline; receiving one or more user-provided descriptions of the user target processor; and transforming the received transformable virtual processor model to the user virtual processor model, wherein the user virtual processor model is configured to perform, on the host processor system, a behavior and timing accurate simulation of the user target processor according to the user-provided descriptions, wherein the transforming includes at least one of the following: adding a new instruction associated with the user virtual processor model to the transformable instruction set of the transformable virtual processor model; modifying a definition of one or more instructions in the transformable instruction set of the transformable virtual processor model according to the user virtual processor model; and modifying a processor structure of the transformable virtual processor model by performing at least one of: adding an additional pipeline associated with the user virtual processor model to the transformable virtual processor model; and modifying the transformable pipeline of the transformable virtual processor model according to the user virtual processor model; wherein at least one of the receiving, and transforming is performed by a processor.