1. In a semiconductor random access memory product, a method of interleaving refresh operations with READ access cycles to effect interlaced asynchronous refresh of a DRAM array, the method comprising: beginning a READ cycle in response to a predetermined input signal, the READ cycle comprising an array access period and a dataout period; extending the duration of the array access period of the READ cycle by a predetermined refresh time slot; and deferring commencement of the READ cycle access to the array until after the refresh time slot, so as to ensure adequate time for a pending refresh operation to complete before the READ cycle access to the array begins.