1. A memory device, comprising: a plurality of connections for coupling to an interconnect structure for receiving row operation information, column operation information, and data information, said column operation information including read commands and write commands, said data information including read data and write data; a memory core for storing said data information; and memory interface circuitry coupled to said plurality of connections and said memory core, for generating row timing signals and column timing signals to operate on said memory core in response to said row operation information and said column operation information, said memory interface circuitry including circuitry for delaying a write operation at said memory core by delaying said column timing signals such that the delay at said plurality of connections between a write command and write data is approximately equal to the delay between a read command and read data.