1. A memory circuit comprising: at least one memory bank, each said memory bank being divided into at least two planes, each of said planes having memory cells organized into rows and columns; an interface circuit, said interface circuit being coupled to said at least one memory bank for accessing selected memory cells of said at least one memory bank; and an addressing circuit coupled to said interface circuit, said addressing circuit receiving a first address of a location within at least a first plane of one memory bank and generating a second address of a location within at least a second plane of said one memory bank, said addressing circuit receiving said first address and generating said second address associated with a first portion of a first clock signal, said addressing circuit applying said first and second addresses to said interface circuit to access said memory cells of said one memory bank.