1. A method of determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level comprising: creating a first target pattern on a lithographic field containing a first integrated circuit pattern, the first target pattern and the lithographic field being on a lithographic level, the first target pattern comprising two first sub-patterns at first opposing corners of a first rectangle having a first width and a first length, the first length being different than the first width; creating a second target pattern on a different lithographic field containing a second integrated circuit pattern, the second target pattern and the different lithographic field being on the a different lithographic level than the first target pattern, the second target pattern comprising two second sub-patterns at second opposing corners of the first rectangle; determining the center of the first target pattern and the center of the second target pattern; and measuring positioning error between the lithographic fields by comparing locations of the first target pattern center and the second target pattern center.