1. A registered memory module, comprising: a register receiving a plurality of signals at respective input terminals, the register storing the input signals responsive to a transition of an internal clock signal applied to a clock terminal when an enable signal is active, the register having output terminals on which the stored input signals are present; a plurality of memory devices coupled to the output terminals of the register, each of the memory devices being selected by a respective select signal being active; and a logic circuit receiving the select signals for the memory devices and applying the enable signal to the register, the logic circuit being structured to make the enable signal active responsive to any of the select signals being active and to make the enable signal inactive response to none of the select signals being active.