1. A method of enhancing a performance of circuits integral to a VLSI chip using a static timing analysis of an integrated circuit (IC) macro abstract model, the method comprising: a. identifying an interconnect segment of the macro abstract model and its timing model that is connected to one or more abstract primary outputs; b. synthesizing an electrical network from said timing model and incorporating said synthesized electrical network into said interconnect segment; c. stitching said synthesized electrical network with electrical parasitics of an external interconnect connected to one or more of said abstract primary outputs; d. performing with a computer a static timing analysis on the interconnects of said stitched electrical network; and e. modifying said circuits integral to said VLSI chip by applying thereto results from said interconnect static timing analyses of said macro abstract models.