1. An aircraft-based infrared image recognition device for a ground moving target, comprising: an infrared non-uniformity correction SoC chip, an image rotation ASIC chip, a multi-level filtering ASIC chip, a connected domain labeling and profile tracing ASIC chip, a main DSP processor, an auxiliary DSP processor, a main FPGA processor, and an auxiliary FPGA processor, wherein said main DSP processor operates to control whole target detection and recognition, to enable target detection and feature recognition, to communicate with external interfaces, to receive imaging parameters from an aircraft, and to output results of detection, tracing and recognition; said auxiliary DSP processor operates to enable SIFT feature extraction and image registration with said auxiliary FPGA processor, comprising calculating a keypoint descriptor and image registration, and transmitting a keypoint descriptor vector (namely a SIFT feature that is obtained) to said main DSP processor as a target feature for target recognition; said main FPGA processor operates to form data transmission channels for each ASIC/SoC chip, said main DSP processor and said auxiliary FPGA processor, to conduct image pretreatment comprising perspective transformation and window setting, and to assist said main DSP processor in controlling each ASIC/SoC chip; said auxiliary FPGA processor operates to enable SIFT feature extraction and image registration with said auxiliary DSP processor, comprising scale space extrema detection, keypoint positioning, and orientation determination; said infrared non-uniformity correction SoC chip comprises an embedded CPU and a correction ASIC core, said embedded CPU operates to enable calibration and updating of gain calibration parameters, and said correction ASIC core operates to enable real-time correction; said image rotation ASIC chip operates to transform two-dimensional rotation into three-time one-dimensional translation, and to enable image rotation via a cubic convolution interpolation (namely bicubic interpolation) algorithm; said multi-level filtering ASIC chip operates to provide a band-pass filter for suppress background and noise based on spectral analysis on small targets, background and noise, and to adjust a bandwidth of said filter via a cascaded filtering module based on a multilevel filter algorithm thereby extracting targets with different size in the case that said targets exist; and said connected domain labeling and profile tracing ASIC chip operates to uniformly and uniquely label connected pixels having the same gray value in an input multi-level segmented image, based on an eight-neighborhood relationship, with natural numbers in an appearance order of said connected domain in said image from the left to the right, and from the top to the bottom, and to output a labeled image.