1. A method of designing a semiconductor device having a circuit information region, said semiconductor device comprising: a first region having component patterns formed in locations based on grid points as intersections of grid lines that divide the circuit information region; and a second region including a plurality of layout cells an outer edge of which is defined by the grid points, the layout cells having component patterns formed based on a predetermined wiring rule with patterns connected to the component patterns of the first region among the patterns being formed based on the grid points at a boundary with the first region.