1. An image processing device, comprising: a processor for processing multiple rows of pixels of an image simultaneously with a single instruction; a plurality of horizontal load registers; and a plurality of vertical load registers, including a first vertical load register and a second vertical load register; wherein the multiple rows of pixels of the image are arranged in (i) the plurality of vertical load registers and (ii) the plurality of horizontal load registers; wherein the processor is configured to shift pixels from the first vertical load register to the second vertical load register; and wherein the processor is further configured to shift at least one pixel corresponding to a bit of each of the plurality of horizontal load registers into the first vertical load register.