1. An interface circuit comprising: a clock signal; a first phase locked loop coupled to the clock signal line and generating a reference clock signal; a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more phase shifted reference clock signals; and a data transceiver circuit coupled to receive at least one of the clock signal, the reference clock signal, or one or more of the phase shifted reference clock signals to control the flow of data between a first circuit and a second circuit.