1. A memory module comprising: a printed circuit board having an edge, a first side, and a common signal trace connector area positioned along the edge; a first row of integrated circuits identical to one another, the first row mounted on the first side of the printed circuit board, the first row being substantially parallel to the edge and in proximity to the common signal trace connector area, the integrated circuits of the first row having a first orientation direction; a second row of integrated circuits identical to the integrated circuits of the first row, the second row mounted on the first side of the printed circuit board, the second row being substantially parallel to the edge and in proximity to the first row and located physically farther from the common signal trace connector than is the first row, the integrated circuits of the second row having a second orientation direction different from the first orientation direction; a first plurality of data lines electrically connecting data pins of the first row of integrated circuits to the common signal trace connector area; and a second plurality of data lines electrically connecting data pins of the second row of integrated circuits to the common signal trace connector area, whereby lengths of corresponding data lines of the first plurality of data lines and the second plurality of data lines are substantially the same.