1. In an integrated circuit adapted to receive a clock signal and to perform internal operations including producing a control signal, a control signal timing circuit comprising: clock sensing circuitry operable to receive the clock signal and to responsively produce a speed signal having a value corresponding to a frequency of the clock signal; and control signal delay circuitry operable to receive the control signal and the speed signal, the control signal timing circuitry responsively producing a delayed control signal that is time-delayed relative to the control signal by a time-delay value corresponding to the speed signal value.