1. A memory subsystem comprising: a) at least two semiconductor devices; b) a main bus containing a plurality of bus lines for carrying substantially all data, and command information needed by said devices, said semiconductor devices including at least one memory device connected in parallel to said bus; c) a loopback clock including a pair of said bus lines constituting first and second lines of said loopback clock, each said memory device including first and second clock inputs for connection to respective ones of said clock lines; and d) a controller having a clock output and a clock input for coupling to said first and second lines respectively.