1. A method for developing a scan-based test design for an integrated circuit design, comprising the steps of: developing a plurality of candidate test designs for the circuit design, including using a computer system, generating a plurality of test vectors in dependence upon the circuit design; using a computer system, generating a test protocol figure of merit for each of the candidate test designs; and selecting, in dependence upon a comparison among the test protocol figures of merit generated for each of the candidate test designs, one of the candidate test designs for implementation in an integrated circuit device, wherein generating a plurality of test vectors employs an automatic test pattern generation algorithm, and wherein the plurality of candidate test designs include differing configuration parameter values for controlling the operation of the automatic test pattern generation algorithm.