1. A memory interface device combining memory control circuits and control interface circuits for coupling a memory module using DRAM memory to data and command processor circuits of a computer system via said memory interface device, comprising: a memory interface device (MID) including memory control circuits and control interface circuits for providing a DRAM controller that is used to send commands to the DRAM and to drive and receive data from the DRAM, and a driver impedance adjustment engine for exercising a DDR SDRAM conforming to a double data rate standard for a high frequency DDR SDRAM supporting a posted CAS function, on chip driver calibration and on die termination for transmitting and receiving data at a coupled one of said DDR SDRAMs on both rising and falling edges of a clock, said coupled one of said DDR SDRAMs form a part of the memory module coupled to said memory interface device, and off chip driver calibration circuits, and data bus and a command bus IO elements for coupling said memory module to said memory interface device, and wherein said off chip driver calibration circuits and said driver impedance adjustment engine are exercisable to find an optimal driver impedance setting for said DRAM by adjusting the value of the driver impedance through said memory interface device and then sampling the known value sent back from the DRAM, said state machine stopping when the optimal value of the driver impedance is found to automate the process of setting the optimal driver impedance in the DRAM module.