1. A method of generating a layout for a semiconductor device, comprising: receiving a first layout; defining a portion of the first layout as a first FinFET region, the first FinFET region having first and second sides that each extend approximately in a first direction; performing a first design rule check (DRC) simulation; obtaining a first DRC simulation result; defining a second FinFET region by moving the first side in a second direction perpendicular to the first direction; performing a second DRC simulation; obtaining a second DRC simulation result; selecting one of the first and second FinFET regions based on the first and second DRC simulation results; and generating a second layout using the selected FinFET region.