1. A computer system including: a processor; a memory array, including at least two banks of SDRAM memory; a memory controller coupled to said processor via a host bus including: a first data queue for buffering data transferred between each of said SDRAM memory banks and said processor, wherein said first data queue temporarily stores data during write cycles from said processor to said at least one SDRAM memory bank; and a second data queue for buffering data signals during read cycles from said SDRAM memory to said processor; wherein said memory controller generates a first clock signal that is provided to a first SDRAM memory bank and said memory controller generates a second clock signal that is provided to a second SDRAM memory bank.