1. A dual port memory controller for use in interfacing a pair of processors to a common memory having a plurality of memory banks each organized into row and column defined addresses, said dual port memory controller comprising: RAS means for generating row address strobe signals; CAS means for generating column address strobe signals; refresh means for periodically refreshing said common memory, said refresh means operating upon each of said banks within said common memory in a staggered manner; arbitration means coupled to said pair of processors having logic means for granting either of said processors or said refresh means access to said common memory in accordance with a predetermined priority; and memory cycle sequencing means coupled to said RAS means and said CAS means and said arbitration means for controlling the operation of said RAS means and CAS means upon said common memory.