1. A method for fabricating a semiconductor device comprising: scanning a circuit design layout and proposing patterns for decomposed layouts; comparing the proposed patterns with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns; if a selected proposed pattern matches a forbidden pattern, eliminating the selected proposed pattern; if the selected proposed pattern matches a preferred pattern, identifying the selected proposed pattern for use in the decomposed layouts; communicating detailed decomposition information associated with the identified proposed pattern to a decomposition tool; generating decomposed layouts from the detailed decomposition information; fabricating a plurality of masks based on the decomposed layouts; and performing a multiple patterning lithographic technique with the plurality of masks on a semiconductor substrate.