1. A clock control circuit for a Rambus DRAM, comprising: an input signal detecting unit for generating an enable signal when one of a first comparing signal comparing an address value of the selected Rambus DRAM with an applied device address value of a COLC packet, and a second comparing signal comparing the address value of the selected Rambus DRAM with an applied device address value of a COLX packet is enabled, and when the applied command is a read or current control command, the command being applied with an SCP command packet on a Rambus DRAM module; a signal generating unit for generating a clock enable signal for externally outputting an internal data when one of the first and second comparing signals is enabled; an output signal maintaining unit for outputting to the signal generating unit a control signal for maintaining the clock enable signal generated from the signal generating unit in the read or current control command; and an output signal control unit for outputting to the signal generating unit a control signal for controlling generation of the clock enable signal from the signal generating unit, when the command applied according to the enable signal from the input signal detecting unit is not the read or current control command.