1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, the present invention relates to a semiconductor device including an improved structural stability and an enhanced capacitance, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
In general, semiconductor memory devices such as dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices can store data or information therein. The data or information is stored in the semiconductor memory devices, and also the data or information is read from the semiconductor memory devices. A typical single unit memory cell of the semiconductor memory device includes one capacitor and one transistor. The capacitor of the semiconductor memory device generally has a storage electrode, a dielectric layer, and a plate electrode. To improve the storage capacity of the semiconductor memory device, the capacitor needs a large capacitance.
As the degree of integration of the semiconductor memory device has increased, the unit memory cell of the semiconductor memory device has continuously decreased in area. To ensure a sufficient storage capacitance of the semiconductor memory device, the capacitor may have various shapes such as a box, a fin, a crown, a cylinder, etc. However, due to design constraints of the semiconductor memory device that include size decreases, the capacitor should have an increasingly large aspect ratio, defined as the ratio between the height and width of the capacitor. Thus the capacitor may have sufficient capacitance when formed in a limited unit area of the semiconductor memory device. As a result, however, the capacitors having a high aspect ratio may mechanically collapse so that a so-called two-bit failure may occur between adjacent capacitors.
A conventional capacitor includes a cylindrical storage electrode connected to a contact pad formed on a semiconductor substrate. The cylindrical storage electrode is electrically connected to the contact pad through a contact plug formed in an insulation layer that covers the semiconductor substrate. To increase the storage capacitance of the semiconductor memory device, the cylindrical storage electrode of the capacitor has a greatly increased height. When the cylindrical storage electrode has this greatly increased height, the cylindrical storage electrode may collapse toward an adjacent cylindrical electrode so that adjacent capacitors may be inadvertently connected to each other. The collapse of the cylindrical storage electrode is referred to as a two-bit failure. When the two-bit failure occurs in the semiconductor memory device, the semiconductor memory device may not properly operate.
Accordingly, U.S. Patent Application Publication No. 2003/85420 discloses a semiconductor device including a beam-shaped insulating member between capacitors of the semiconductor device to improve the mechanical strength of the capacitor.
FIG. 1 is a cross-sectional view illustrating the semiconductor device including the beam-shaped insulating member, and FIG. 2 is a plan view illustrating the semiconductor device in FIG. 1.
Referring to FIGS. 1 and 2, after a semiconductor substrate 40 is divided into an active region and a field region by forming an isolation layer 45 on the semiconductor substrate 40, gate structures 60 are formed in the active region of the semiconductor substrate 40. Each of the gate structures 60 includes a gate oxide layer pattern, a gate electrode and a mask pattern.
Impurities are implanted into portions of the semiconductor substrate 40 by an ion implantation process using the gate structures 60 as masks, thereby forming source/drain regions 50 and 55 at the portions of the substrate 40 between the gate structures 60. Thus, metal oxide semiconductor (MOS) transistors are formed on the semiconductor substrate 40.
After a first insulating interlayer 80 is formed on the substrate 40 to cover the MOS transistors, capacitor plugs 63 and a bit line plug 65 are formed through the first insulating interlayer 80. The capacitor plugs 63 and the bit line plug 65 are connected to the source/drain regions 50 and 55, respectively.
After a second insulating interlayer 85 is formed on the first insulating interlayer 80, the second insulating interlayer 85 is partially etched to form a bit line contact plug 70 making contact with the bit line plug 65.
A third insulating interlayer 90 is formed on the second insulating interlayer 85. The third and second insulating interlayers 90 and 85 are successively etched to form capacitor contact plugs 75 making contact with the capacitor plugs 63, respectively.
After an etch stop layer 95 is formed on the third insulating interlayer 90 and the capacitor contact plugs 75, holes 100 exposing the capacitor contact plugs 75 are formed through the etch stop layer 95. Cylindrical bottom electrodes 105 making contact with the capacitor contact plugs 75 are formed in the holes 100, respectively. Here, the cylindrical bottom electrodes 105 are electrically connected to the source/drain regions 50 and 55 through the capacitor contact plugs 75 and the capacitor plugs 63.
After beam-shaped insulating members 130 are formed between sidewalls of adjacent bottom electrodes 105, dielectric layers 110 and top electrodes 115 are successively formed on the bottom electrodes 105 to thereby form capacitors 120 on the semiconductor substrate 40.
An additional insulation layer 125 is formed over the substrate 40 to cover the capacitors 120. Since the beam-shaped insulating members 130 are formed between the sidewalls of the adjacent bottom electrodes 105, the mechanical strength of the capacitor 120 may be improved.
However, in the above-described semiconductor device, processes for manufacturing the semiconductor device are complicated because at least four beam-shaped insulating members 130 should be formed between the adjacent bottom electrodes 105 in order to improve the mechanical strength of the capacitor 120. Thus, manufacturing cost and manufacturing time for the semiconductor device is increased. Additionally, the manufacturing processes are more complicated because the capacitor 120 has a complex structure including the bottom electrode 105, the beam-shaped insulating members 130, the dielectric layer 110 and the top electrode 115 as shown in FIGS. 1 and 2. Further, the additional insulation layer 125 may not be precisely formed between the capacitors 120 having the complex structure so that the capacitors 120 may be inadvertently electrically connected to an upper wiring formed on the capacitors 120. As a result, the processes for manufacturing the semiconductor device including the capacitor 120 having the complex structure may have poor throughput.