1. Field of the Invention
This invention is related to read amplifiers which have at least one load component, at least one differential amplifier and a compensation transistor.
The read amplifier of the invention primarily is utilized in static memories (SRAMs). A SRAM forms a memory wherein after the address has been prescribed, data can be stored under such address and can be read out again with random access. For technical reasons, individual memory cells are not linearly arranged, but are arranged in a quadratic matrix form. Static memories (SRAMs) are preferably utilized in smaller computer systems wherein there are higher costs as compared to dynamic memories (DRAMs) which are offset due to the simpler and cheaper system architect.
2. Description of the Prior Art
Earlier developments in static memories resulted in three different semiconductor technologies. First, bipolar technology; second, NMOS technology; and third, CMOS technology. The CMOS technology is utilized for the read amplifier of the invention which is considered to be an important functional component part of static memories.
Due to the simple peripheral circuits, over 60% of the chip area is covered with memory cells. The remainder of the chip area is principally for row and column decoders as well as for input amplifiers and for read amplifiers.
The circuit oriented arrangement of the read amplifier has a strong influence on important characteristics of the static memory. Thus, for example, the access time and the amount of power dissipated are determined by the properties of the read amplifier.
The following publications disclosed read amplifiers for static CMOS memories:
1. Childs et al, IEEE Journal of Solid State Circuits, Vol. SC-19, Pages 545 through 551, October 1984; and
2. Okazaki et al IEEE Journal of Solid State Circuits, Vol. SC-19, Pages 552 through 556 of October 1984.
The first publication by Childs et al, discloses a 4Kx 4 CMOS static RAM which is produced with a single polysilicon layer and the second publication by Okazaki et al discloses a very fast 2Kx 8 bit CMOS SRAM which enables an access time of 16ns which is comparable to bipolar SRAMs of the same complexity. Both of these publications disclose circuits for read amplifiers which have load components as well as the actual memory cell portion shown in FIG. 10 in the Childs et al publication and in FIG. 6 in the Okazaki et al publication.
FIGS. 1 and 2, except for FIG. 2c, in combination with FIG. 1 show prior art read amplifiers. The read amplifier is divided into a p-channel load component and into a differential amplifier component and there are a number of different circuit possibilities for the p-channel load component. The differential amplifier component is composed of three n-channel field effect transistors which are interconnected in a traditional manner and utilizes an additional p-channel compensation transistor. When clocked memories which have preloading phase are utilized, the compensation transistor improves the compensation of the read amplifier outputs LA and LA during the preloading phase at the first two load component circuits illustrated in FIGS. 2b and 2c. The turn-on of the compensation transistor P4 during the preloading phase and the turn-off during interpretation phase are controlled with a signal at the input AG.
When using the different load components for read amplifier shown in FIGS. 2b, 2c and 2d, the preloading potential V.sub.DD or, respectively, V.sub.DD -V.sub. THP exists at the output LA and LAduring the preloading phase (AG="0", EN="0"). V.sub.THP of about 0.8 volts identifies the threshold voltage of a p-channel transistor. Such a high preloading potential, however, prevents short access times.