1. Technical Field of the Invention
The present invention relates generally to a current mirror.
More specifically, the invention relates to a current mirror of the type comprising at least a first and a second mirror transistors inserted between a first and a second voltage reference and connected to an input terminal and to an output terminal of the current mirror, respectively. A base current compensation block is inserted between said input terminal and common control terminals of the first and second mirror transistors and connected to a voltage reference.
2. Description of Related Art
As it is well known, current mirrors are widely used in all kinds of electronic circuits. Basically, a current mirror is a circuit designed to copy a current flowing through one active device by controlling a current in another active device, keeping an output current of an output terminal of the current mirror constant regardless of loading values applied to the output terminal itself.
A current mirror realized by using bipolar transistors is schematically shown in FIG. 1.
In particular, the current mirror 1 comprises a first or input leg comprising a current generator G1 issuing a reference current Iref, a first mirror transistor Q1 and a first emitter resistor R1, inserted, in series with each other, between a first and a second voltage reference, in particular a supply voltage reference Vcc and ground GND.
Furthermore, the current mirror 1 comprises a second or output leg comprising a second mirror transistor Q2 and a second emitter resistor R2, inserted, in series with each other, between an output terminal OUT of the current mirror 1 and ground GND.
The first and second mirror transistors, Q1 and Q2, are bipolar transistors and have their base terminals connected to each other.
To increase current mirror accuracy, a classic solution is to use emitter resistors and a base current compensation block, as shown in FIG. 1 and globally indicated at 2.
In particular, the base current compensation block 2 is connected to the common base terminals of the mirror transistors, Q1 and Q2, and to the collector terminal of the first mirror transistor Q1. The collector terminal of the first mirror transistor Q1 is also the input terminal IN of the current mirror 1.
The base current compensation block 2 is used to compensate the base currents of the first and second mirror transistors, Q1 and Q2. A well known realization of this block is described in Analysis and Design of Analog Integrated Circuits, Paul R. Gray, Robert G. Meyer, Third edition, page 276, and schematically shown in FIG. 2.
In particular, the base current compensation block 2 comprises a compensation transistor Q3, inserted between the supply voltage reference Vcc and the common control or base terminals of the mirror transistors, Q1 and Q2, and having a base terminal connected to the collector terminal of the first bipolar mirror transistor Q1. The compensation transistor Q3 is a bipolar transistor.
It can be verified that the compensation transistor Q3 reduces the error of an output current of the output terminal OUT according to the following equation:
                    Iout        =                  Iref                      1            +                          2                                                β                  F                                ⁡                                  (                                                            β                      F                                        +                    1                                    )                                                                                        (        1        )            where Iout is the output current, Iref is the reference current and βF is the bipolar current gain of Q1, Q2 and Q3 (supposed to be equal at a first order approximation).
Moreover, the first and second emitter resistors, R1 and R2, increase the matching of the current mirror 1, as explained in the above cited handbook, pages 317 to 320.
Also known is an alternative realization of the base current compensation block 2 using a MOS transistor M3, as shown in FIG. 3.
In this case, as the gate current of a MOS transistor is zero, the output current Iout is equal to the reference current Iref and the base currents of the first and second bipolar mirror transistors, Q1 and Q2, are supplied by the MOS transistor M3.
While advantageous from many points of view, the known solution has shown several drawbacks, among which is the fact that an input voltage applied to the collector terminal of the first mirror transistor Q1 should be higher than a threshold value, which turns out to be too high in many applications. In particular, such a threshold voltage is:                2×Vbe+R1×Iref, for the base current compensation block 2 realized by a bipolar transistor and shown in FIG. 2, or        Vgs+Vbe+R1×Iref, for the base current compensation block 2 realized by a MOS transistor and shown in FIG. 3,where:        Vbe is the base-emitter voltage of the first mirror transistor Q1; and        Vgs is the gate source voltage of the MOS transistor M3.        
As an example, if Vbe=0.8V, Vgs=1V and R1×Iref=0.2V (which are common amounts for these values) the minimum input voltage is about 1.8V or 2V, increasing to 2V or 2.3V with temperature and process variations.