The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device having a burn-in test mode and a method for driving the same.
In the fabrication of semiconductor memory devices, a stress mode is widely used as a test process for increasing the reliability of memory cells.
In particular, a stress mode at a wafer level is called a wafer burn-in process. The wafer burn-in process is to apply a stress to a core region of a DRAM at a relatively high temperature to induce the generation of defects in a weak core region in an early stage. Then, the defects are repaired in a probe test. In addition, the process of applying the stress to the core region of the DRAM includes a process of applying a stress to a cell and a process of applying a stress to a bit line. The two processes can be implemented with simple logic.
In executing the stress pattern, the test modes are sequentially set in each step to perform the stress process. Separate codes are assigned in each test mode. In other words, in addition to a wafer burn-in test mode entry pad and an internal bias forcing pad, another pad is necessary for inputting a separate operation code for entry into the test mode defining each step. The operation code uses a data pad or address pad.
Table 1 below shows operation codes for each mode in a conventional wafer burn-in test.
TABLE 1MODEA<0>A<1>A<2>A<3>TM0HLLLTM1HHLLTM2HLHLTM3HHHLTM4HLLHTM5HHLHTM6HLHHTM7HHHH
The order of the test modes according to the test pattern will be described below.
A cell stress pattern has a procedure of TM2→TM3→apply a logic low level to a cell data→TM2→apply a logic high level→TM2→TM3→apply a logic low level→TM3→apply a logic high level.
An oxide-nitride-oxide (ONO) stress pattern has a procedure of TM2→TM3→apply a logic low level→apply a bias→TM2→TM3→apply a logic high level→apply a logic low level.
A first bit line stress pattern has a procedure of TM7→apply a logic low level→apply a logic high level→apply a logic low level→apply a logic high level.
A second bit line stress pattern has a procedure of TM4→apply a logic low level→TM5→apply a logic high level→TM1→TM6.
As shown in Table 1, the operation codes for each test mode are applied through four address pads. For example, all the addresses A<0:3> must be applied with a logic high level in order to enter into the test mode TM7.
Meanwhile, a test apparatus reduces test time by testing a plurality of dies one time. Because the number of channels of the test apparatus is limited, the number of pads necessary for the test must be reduced so as to test a large number of dies at one time.
A built-in self test (BIST) is widely used in a memory cell test in a conventional ASIC. The built-in self test has an advantage in that a large number of pads are not used because it does not directly access a memory cell from the outside. However, the patterns that can be tested in the built-in self test are complicated. To this end, logic circuits must be added, thus increasing the layout area. Therefore, the built-in self test is difficult to apply to memory devices in which a net die is important. The net die is defined by number of dies per wafer.
In the wafer burn-in test, a probe card is separately manufactured and a stress is applied to a plurality of dies by one-time test. However, because the number of pads for testing one pad increases, the number of dies to which a stress is applied at a time decreases due to the limited channels of the test apparatus.
Therefore, because the number of pads necessary for the burn-in test mode is large, the number of dies that can be tested one time is small, thus increasing the test time.