Added:  Points raised are being addressed. Have left most in and tidied as example of things to consider and that have now been considered. Added PFET level shift comment at end.
  [This comment is for anyone following this - NOT as an edit trace]. 

You do seem to be trying and have a general grasp of what is needed but, no rudeness intended, the circuit shows several signs of very major lack of design. You need to think things through MUCH more carefully.Fine detail cannot be looked at until you get the basic circuit details correct. As shown it will not work AT ALL for several major reasons. 

Drive polarity wrong:    The IC is able to be configured as a buck converter but as shown the output drive is of the wrong polarity if you use a P Channel high side switch and of the wrong voltage swing if you use an N Channel high side switch - see below. If using a P Channel MOSFET (which would be normal here) the output drive needs an inverter in it. As shown it will not work.

Level translator needed in driver:       If you DO run the IC off a 12V supply (and Vdd max = 15V) then the inverting driver which you have not yet got also needs to level translate as the MOSFET is high side and gate drive needs to go to 30V or whatever for MOSFET turn off. While addressing that do also ensure that MOSFET Vgs max is not exceeded when driving.

FET is wrong type          The MOSFET is nice enough BUT is N Channel (as befits the incorrect topology that you are using). An N channel MOSFET COULD be used there but the gate would need to be driven above V+ rail and you would need a gate drive supply. The overwhelmingly usual thing to do would be to use a P Channel MOSFET as the switch

Output diode      The output diode is very nice but is "overkill". The high max voltage leads also to higher than necessary forward operating voltage. You can probably get a few % more efficiency end to end with a lower voltage Schottky.

At a glance without pouring over the details the IC looks competent and should be capable of good efficiency as a buck regulator. I'd expect 90-95% to be achievable once the circuit was correct. 



Driving high side PFET.

Vin max = 32 V (specified).
 Vdd Ic = 12V (user specified) or 15V abs max.

PFET will have a Vgs max. Above that you get magic smoke.
 As PFET source is connected to Vin+ the Vgs is measure relative to Vin+.
 PFET gate can be driven low BELOW Vin+ by Vgsmax - ideally a bit less.

FET's that are not logic FETS often have Vgsmax of 20 to 25V.
 Most FETs are totally "enhanced" (aka turned fully on) by the time they have Vgs = 12V - see curves for FET of choice.
 Let's set Vgs max actual   = -12V relative to Vin+.
 This means that when Vin+ = 32V, Vgs may range from about 32V (FET is off) to 32-12 = 20V (FET is hard on).
 BUT available drive voltage at IC = 0-12V approx.
 So a level shifter is definitely needed.

How can I improve this SMPS design?
I am trying to decide between some math postdoc offers, and I can't decide what is important for a postdoc position. I have talked to several senior mathematicians including my advisor, but they all seem to have different opinions. I just want to hear some more opinions on the following:


How important is prestige? Suppose that I have an offer from school X, which is fairly prestigious (something like top 10, which isn't a well-defined notion). Also suppose that I have an offer from school Y, which is not as prestigious but a better match research-wise. Suppose that the ranking of school Y is approximately n (again, not a well-defined notion). For which values of n should I choose school X over school Y? My goal is to become a tenure-track professor in a PhD-granting institution.
What makes a good postdoc supervisor? I can think of the following criteria: compatible research interests, being well-known in one's field, compatible personalities, generous with time, etc. Am I missing anything else?

