In boundary scan testing, test circuits integrated into various ICs on the board form temporary connections between the PCB traces to test that the ICs are mounted correctly. Boundary scan testing requires that all the ICs to be tested use a standard test configuration procedure, the most common one being the Joint Test Action Group (JTAG) standard. The JTAG test architecture provides a means to test interconnects between integrated circuits on a board without using physical test probes. JTAG tool vendors provide various types of stimulus and sophisticated algorithms, not only to detect the failing nets, but also to isolate the faults to specific nets, devices, and pins. COUNT 5
QSN1 What's the most frequently used test configuration procedure for ICs? ANS1 Joint Test Action Group QSN2 Do test circuits create permanent or temporary connections between traces? ANS2 temporary QSN3 What component of the printed circuit board is appraised with boundary scan testing? ANS3 ICs QSN4 To whom would you go to acquire the algorithms you'd use for the Joint Test Action Group procedures? ANS4 JTAG tool vendors QSN5 What would you avoid by using the Joint Test Action Group standard? ANS5 physical test probes