INTRODUCTION In the context of nanoscale CMOS computing architectures, the quadruple mastery of power, performance, cost and reliability appears almost as impossible as squaring the circle.

the emergence of four-terminal devices, with complementary intrinsic properties, responds to device-level expectations with favorable benchmark figures against Si-CMOS transistors, and shows the potential to provide novel logic blocks for digital architectures.


With the technology scaling and the increased number of transistors on a chip, VDDmin will increase, because the more gates there are, the more likely it is that the worst-case condition will occur, and thus a higher VDD will be required.

the systematic measurements of the VDDmin of the subthreshold logic circuits made with scaled devices have not been reported yet.


The model retains its accuracy because determination of the delay, area, and power are carried out using low level circuit estimation of resistance and capacitance of interconnect components such as wires, repeaters, bu.ers, and .ops using HSPICE[3].

these and other technology and voltage dependent parameters are precomputed for di.erent technology nodes and voltage steps.


On the other hand, such augmented input bu.ers do not dominate NoC area since other components (especially the output bu.ers, sized to 6 slots in this architecture) play a major role.

even for short term chip implementations a 5 slot FIFO does not guarantee a reasonable yield (see for instance [21]).


As for post-encoding and post-synthesis information, we 3.1 Model Space Exploration observe that the knowledge of the actual area would reduce the error from 19 to 5%.

similar improvements can be achieved at the behavioral level by exploiting the knowledge of the number of cubes N¢.


[19] monitored multiple servers on a datacenter as well as the power consumption of several of the internal elements of a server.

they considered that the behavior of this server could be approximated by a model based only on CPU utilization.


{fwchen, chensl}@cs.nthu.edu.tw,g9662586@oz.nthu.edu.tw, tingting@cs.nthu.edu.tw  Abstract To guarantee that an application speci.c integrated circuits (ASIC) meets its timing requirement, at-speed scan testing becomes an indispensable procedure for verifying the performance of ASIC.

at-speed scan test suffers the test-induced yield loss.


Next epoch, the chip will go to lower power mode more aggressively.

if during the last epoch, the system used up all its slack and forces all devices to become active in order to provide a performance guarantee, it indicates that the thresholds are aggressive.


UAVs are usually controlled manually or autonomously, both ways often heavily relying on the use of a global positioning system such as GPS.

especially the wide spread GPS suffers form large positioning errors of 10-30 m on average.


The simplest way to handle this would be to give every PE and switch a memory of this depth and globally clock the design.

this would add substantial energy by (1) making the design larger and hence the wires longer, (2) making the memory energy more expensive, (3) adding substantial energy for clocking.


In the above papers, the topology of the radio networks was known in advance, and broadcasting algorithms were deterministic and centralized.

in [4] a randomized protocol was given for arbitrary radio networks where nodes have no topological knowledge of the network, not even about neighbors.


This should be expected, since only one input combination produces a zero output.

this asymmetry is detrimental to logic processing as shown in Figure 9.


The last of these, for example, constitutes a significant drawback for piezoelectric FBAR resonators, for which resonance frequency is determined by thickness rather than lateral dimensions, making it difficult to specify multiple frequencies on a single-chip via CAD layout.

the frequencies of the capacitively-transduced devices in Table 1 are governed by one or more lateral dimensions, allowing a designer to specify a frequency via CAD layout, and more importantly, allowing automated specification of a larger circuit of resonators with varying frequencies, all on a single chip.


INTRODUCTION Today, most safety-critical applications require the use of some type of computer-based device, causing their implantation to grow and expand into new areas like the automotive and biomedical fields.

as electronic systems increase in complexity and decrease in size their correct operating behavior is becoming harder to guarantee [1].


Thus, the calculation ofe.ective capacitance is an important procedure in the gate modeling process.

most oftechniques on the computation of e.ective capacitance [14, 16] are not explicit and they need several iterations to converge.


A small amount of PF (10%-20%) provides adaptivity for higher load balancing and resource utilization for each individual benchmark, while larger amounts of PF begin to starve the system of the improved performance ef.ciency of the ASIC ABBs.

even the small performance improvement initially seen with the addition of PF is not enough to counterbalance the reduction in power-ef.ciency as ASIC ABBs are replaced by PF.


Mappability-based partitioning alone did not result in a very balanced system.

if we were to implement the convolutional encoding and demodulation algorithms in the hardware, it would lower the requirements for both architectures in the two-processor case to a reasonable level of 500 MOPS.


4.3, a.ecting the con.ict miss probability.

since the LRI policy chooses the M slot to be evicted in a periodic manner, we will eventually be able to evict these With a probability roughly equal to (1 - e - c 1 )k (0.024 for stale key-value pairs and also cleanup their G slots.


[26] provide a further proposal for a software protection system using recon.gurable hardware but the protection of IP contained in bit streams is still an active .eld of research (see, e.g., [18]).

to our knowledge, a holistic approach to transfer the extensive capabilities of Trusted Computing systems to recon.gurable hardware has not been published yet.


The Fully-Bu.ered DIMM (FBDIMM) architecture [12] is characterized by non-uniform access time to DRAM banks, which is similar to CHARM from the viewpoint of a memory controller.

an increase in latency and power consumption incurred by Advanced Memory Bu.ers in FB-DIMM limits its applicability compared to CHARM.


We can also see that even when the size is skewed, which is not known at compile time, the system can dynamically select the kernel launch parameters based on the runtime size to maximize performance.

warp-based mapping (region B) shows poor performance due to its .xed strategy, which leads to resource underutilization.


Conventional pre-silicon statistical optimization is akin to predicting the most likely process conditions and centering the design parameters to give a maximum yield within its vicinity.

post-silicon tunable methodologies leave the compensation for process variation to the post-silicon phase, and aim to provide the maximum tuning flexibility while at the same time limiting overhead incurred by the added hardware.


We see that the software would intervene between 1 and 329 times during benchmark program execution,for the cases of ammp and crafty,respectively.

hardware-only solutions would need to intervene between 35 and 306,698 times, for perlbmk and eon,respectively.


Since Oe capturesthedirectincrease of .H,the exponentialfunctionis used to magnifythepenalty.

as we will soon see, such a function is not general enough since it only considers the contribution of a single edge, rather than that of apath.


Currently dual-Vth is the only practical approach to achieving substantial runtime leakage reduction [9].

using HVT buffers leads to a large degradation in performance.


still clearly suggests that multi-cycle on-chip communication is a necessity in multi-gigahertz synchronous designs.

given the fact that most existing design tools only deal with the first problem but completely lack consideration of multi-cycle communication, further system performance increase is at risk.


D,if A and D belong to the same cluster they will have 0 skew and the delay between them will determine the period 6.

the cluster solution {A, B} and {C, D} is able to keep the best possible period 4, with the constraint of having just 2 clusters.


For the stacked devices whose sources are not connected to VDD or ground, their body-effect increases with supply voltage, such that it would be expected that the relative delay would be a maximum at high voltage.

the sensitivity of device current and circuit delay to gate-to-source voltage exponentially increases as supply voltage goes down.


Prior work [1, 3, 4] has demonstrated the need to consider both cycle time and throughput (IPC) when measuring overall processor performance.

architects often have little or incomplete physical design information about the architectural space they are considering.


We reason this advantage of AES strengthens any argument for using such a parallelisable design approach in block ciphers and cryptographic primitives in general.


2.3 SchmittTrigger Circuits We introduced the use of implications for increasing the reliability of a circuit as a general approach.

we need to .nd an architecture for implementing the feed-forwarding reinforcement.


Addition network In fact, the number of speci.ed carries in column 2, 2 c=1, cannot be observed on the physical carry signals x C1,1 and C1,2 using BCP.

a key observation is that the structure of the addition network can be rearranged using commutative and associative laws such that BCP spec 2 i.es ccarries.


the output of the majority voter (Z) is determined by the input W. Thus, the existing data in memory is looped back.

if the Write control signal is enabled, then the inputs X and Y have the same logic value (either 0 or 1 depending on the input data).


For the broadcast, the blind flooding mechanism is usually employed.

in the blind flooding mechanism, when a sensor node receives a broadcast message, it forwards the message to all of its neighbors.


Overall, the best performing SPR-CC percentage achieves similar performance to that of SPR-ASR.

the best SPR-CC percentage varies by workload Apache and Oltp do best at 70%, Zeus at 30%, and the others at 0% illustrating the bene.t of an adaptive policy.


Little work has been done in this area, with the only exception being the proposed trust evaluation structure in wireless cryptographic ICs [10], which relied on on-chip neural network to analyze side-channel parameters and detect the hardware Trojan at the post-deployment stage.

the trust evaluation framework proposed in [10] suffers from various problems.


Smooth Transitions Being able to produce the right vowel sound and control its loudness should allow the user to effectively move the pointer to a desired target.

if the task demands that the user follow a curvilinear trajectory, it is necessary that the user be able to smoothly transition from one vowel to another and control the rate of transition in conjunction with their loudness.


When the distance between devices is short, the measured Idsat shows the highly correlated characteristics.

the Idsat for long distances is less correlated than that for short distances.


The Read-out path would be turned on when Figure 4. the Write 0 operation completes and the floating bit-line would be pulled down.

in Write 1 mode, the Read-out path would be cut off once the Write operation completes.


The transistor IDS model is being used for our analysis, whichincreases the analysis accuracy.

existing approaches[11, 12] model the electrical behavior of gate using linear RCcircuit.


5.1 Discussion Intense communication is not a good indicator for closeness On the one hand, a high degree of correspondence (i.e., message exchange or frequent phone calls) shows an ongoing social relationship [15].

this communication pattern may also rather imply a dispute than a close and amicable tie.


When reading the input trace file, the simulator uses this timer to access resource utilization data at the corresponding time stamp associated with it.

there are several challenges with using traces that only capture resource utilization information.


Circuit techniques to produce multiple sleep depths are well studied.

how to control their sleep modes have not been established.


An interesting model based on boosting methods has been recently proposed [5].

regression approaches are not suited to top-down methodologies where abstraction levels introduce opaqueness in the system hierarchy that hides the implementation details needed for regression.


INTRODUCTION Three-dimensional ICs (3D ICs) is one of the most promising technologies that enables higher integration and further miniaturization.

through-silicon vias (TSVs), may cause reliability and cost issues that delay mainstream acceptance [8, 15].


By combining simulation with emulation on a prototyping platform, extensive testing of each component minimizes the debug cycle during integration.

porting every single block to a prototyping environment can be a considerable effort.


In [14], and [3], it is shown that the Cholesky factorization of the A matrix, which is composed of G, C, and/or K, can be very ef.cient due to the inherent sparsity of A.

the inverse of A is dense, which in turn implies that each simulation step involves dense matrix-vector multiplications.


In this study, we did not compare the new cells performance to that of Si MOSFETs because any quantitative results would depend to a large extent on the quality of the device model used.

we highlighted the improvement that these new structures, exploiting the back-gate of the DG-CNTFET, could provide.


We use the Elmore delay model and the .rst order Taylor series terms to represent the canonical delay model of Equation (2).

clearly this is not a restriction, as our canonical form is similar in form to that in [1, 2].


It is possible to partition C into a subset C0 that consists of all the stuck-at 0 faults in C , and a subset C1 that consists of all the stuck-at 1 faults in C .

we note that fault collapsing can remove more stuck-at 0 or more stuck-at 1 faults, depending on the circuit.


[2] views the chip-wide variation as a stochastic process and proposes using the Karhunen-Loéve Expansion (KLE) to extract a small set of uncorrelated random variables, which can then be used as parameters for the gate timing models.

the approach is restricted to a theoretically simple, but physically unrealistic, correlation kernel, and no generic method is proposed to handle any realistic kernel extracted from process data (e.g., as per [1]).


The conventional integration architecture composed of one bit address per nanowire is not suitable [16].

we can use a short magnetic nanowire to present one word.


Current BBM tracks both types of bad blocks, and keeps them away from regular use.

when the amount of bad blocks exceeds a threshold, the entire chip is rendered non-functional.


HETEROGENEOUS TOPOLOGIES Switch folding is a time-multiplexed variant of the crossbar switching logic, which enables full routers to be implemented at a lower cost.

depending on the symmetry of the topology and the characteristics of the router algorithm, some parts of the network are more stressed than other parts with lower utilization.


Moreover, this solution does not require any kind of header in the packet structure, reducing the width of the input FIFOs.

as pointed out in [13], the AP architecture requires additional memories to store the routing information of all supported codes.


The second observation is that reducing the crossbar connectivity to 75% largely maintains the packing e.ciency of the full crossbar.

the packing e.ciency for the crossbar with 50% connectivity decreases to a larger extent.


Each access to one memory, for instance, the access to memory 1 in Figure 2.b, only activates the necessary communication path (the black bold lines in the .gure) by controlling the switches.

the whole bus is activated during each access in case of a shared bus in Figure 2.a, whichever memory is accessed.


When the number of threads is small, the number of unique phase combinations is much smaller than the total number of phase combinations, because the combinatorial growth with only two threads is small.

when the number of threads is increased to 16, we can see that out of all the phase combinations seen, a much larger percentage of those combinations are unique.


With past technologies, this problem was limited to radiation hostile environments like in space.

with very-deepsubmicron technologies (VDSM), aggressive device size and power supply reductions have impacted severely circuit sensitivity, as they reduced aggressively the critical charge of memory cells.


Therefore, initially the restriction on J-nodes for decision making would make our solver behave differently from the ZChaff.

after many learned gates are accumulated, effectively the two would follow the same VSIDS algorithm.


Dual supply voltage technique for Domino logic was proposed [40].

this technique does not consider reducing power consumption in the clock tree.


Naturally, such protection tricks work as a placebo effect, and do not provide any information on the EMF they represent cultural fears.

some artists have explored the playful side of exposing ambient signals for example, Haruki Nishijima runs around with a butterfly net antenna to catch and archive broadband RF background, and Toshio Iwai sonified modulation in common background lighting using a portable device made by connecting an amplified photodiode to a speaker in his 2001 installation called Photon.


As a result, the number of assigned layers can be obtained and all the given buses can be assigned onto the used layers.

the proposed heuristic algorithm may not minimize the number of assigned layers for bus-oriented escape routing.


When asked about voice strain only one of our participants said the study was tiring or straining.

that user also said the continuous vocalizations did not bother them much and they would still be happy and able to continue using VoicePen for a while longer.


The irregularities in the decreasing trend past 2 µm interconnect width are due to convergence issues in the numerical analysis methods.

also note that the variation in the transmission s-parameter is not very large with variation in width (approximately 0.5 dB).


The best results are obtained with the UDDC-B with an average tra.c reduction (using the geometric mean) by a factor of 1.85 for 4kB caches.

compared to the DDC and the UDDC-A, this organization has the largest tag implementation cost, since every smaller block needs to be tagged.


It fills the gap in the set of relationships of circuit elements and covers that between the magnetic flux and the charge.

the device was not proven experimentally until 2008 by researchers from HPlabs, and brought an upsurge for the memristors and memristive systems [35].


Delft University of Technology Postbus 5031, 2600 GA,Delft TheNetherlands  ABSTRACT In this paper, we compare the architectural perspectives of theWaveFieldSynthesis(WFS)3D-audioalgorithm mapped on three di.erent platforms: a General Purpose Processor (GPP), aGraphicsProcessorUnit(GPU)and aFieldPro-grammableGateArray(FPGA).Previousrelated work reveals that, up to now, WFS sound systems are based on standard PCs.

on one hand, contemporary GPUs consist of many multiprocessors that can process data concurrently.


Double-balanced Gilbert-type mixer with current-reuse bleeding technique In overall mixer design, higher gain, higher linearity, lower noise and low power consumption are required.

these parameters are not easy to achieve simultaneously.


However, the tolerance to temporal MBEs is kept within an acceptable range.

a CPPC is capable of correcting spatial multi-bit errors with a very small overhead and has some very desirable features.


For example, Graphite [9] provides very ef.cient simulation of a many-core system based on the x86 architecture.

it has yet to provide faithful simulation of network buffers.


We observe that the .rst plot is considerably far from the .rst bisector, which means that distances between paths are very small for c1355 compared to the existing amount of variability.

in the plot for c7552, we can see that the ranks changes are minor.


These penalties were measured while translating loops to target the speci.c LA proposed in Section 3.

the results are representative of a broad class of accelerator architectures.


In this paper, we used Earliest Deadline First (EDF) and a heuristic called Energy Aware Scheduling (EAS) to generate both computation and communication task schedules [11].

in general, the proposed approach can be used with arbitrary schedules.


The wire loads of all these nets have to be estimated based on the statistical models.

because of the unpredictable nature of automated place-androute, some nets may be much longer than the average, as in the case of net n2.


PGR attempts to discharge VR while PUR opposes it.

pGL attempts to charge VL while PDL opposes it.


If the internal node has the same polarity, the channel leakage across the pass-gate is shutoff.

if the internal nodes have opposite polarity to the passgate input, there is channel leakage across both bitcell pass-gates.


Hence, there is a voltage drop on the pass gate on the SL.

the magnitude of this drop is determined mainly by the resistance of the MTJ (other wire loads are relatively constant).


On-chip DRAMs have been explored as a possible alternative to SRAMs due to its small cell size (1-T or 3-T structures).

leakage of information is severe in such memories and periodic refresh rates make them undesirable for portable electronics with limited battery life.


Because only three CP cells are pumping the energy to the output, the response time is a little slower than the regular case.

compared to most existing designs, it is still very competitive.


After determining the positions of blocks, these thermal vias are inserted to the white spaces between blocks for heat dissipation.

two main obstacles exist in extending previous floorplanning approaches to cope with thermal via planning.


In fact, the area overhead over the lock-step architecture is as low as 9% and 1.5% for low-and mid-range systems respectively.

it also inherits almost all of the features and .aws of the lock-step architecture.


The acceleration data shows differences among the .ocks (Figure 5) which is also present in the windowed variance (Figure 7).


Until recently, a unified model that can handle the most common phenomena that designers care about hasproven elusive.

with the recent invention of an electrical, current source-based cell model applicable to timing and noise flows by Croix and Wong in [5], and extensions of this model by other researchers [6]-[11], a unified, electrical model for handling most of these effects isin sight.


As expected the performance in terms of miss rate improves with the size of FVC.

it is interesting to note that in some cases (124.m88ksimand 134.perl) a very small sized FVC of 64 entries is suf.cient to get all the performance improvements.


According to Table 2, the occupied slices then account for only 24% of what are available on the Virtex-6 FPGA device.

the rate of occupied slices rises to 38% for .


This implies at least k-miss-competitiveness (of these two) relative to any online algorithm.

pLRU(4) and PLRU(8) are not k-miss-competitive relative to LRU(4) and LRU(8), respectively, for any k. This is the investigated k. We have proven the generalization to arbitrary k by hand (see [3]).


5.1 Evaluating Isolation Candidates Based on the model presented in Section 4, we can estimate the amount of power saved by isolating a module.

operand isolation also incurs a cost in terms of area, power, and delay due to additional logic introduced into the circuit.


Improving performance by banking is relatively cheap independent banks on a shared bus do not increase controller complexity, and bus arbitration can be implemented with low cost.

superblocks require additional controller complexity in managing blocks across .ash memory banks, as each block must be checked independently (for example, compare Figures 5 & 6 in [23]).


the dotted line for LC3) back to its respective carrier (the distance marked TRC).

if we remap the logical channels to different physical channels, we could tune the rings to the closest channel.


We note that in this path-based SSTA, sia,isb are calculated as vectors of values based on the timing model.

.iis kept symbolically because it is the unknown vector of parameters to be estimated.


If the deadline constraint is too strict, the ILP model may not return a feasible solution.

making the deadline too relaxed will give a feasible solution with a lower cost as the ILP tries to allocate more than one task to a resource.


Hybrid memory units such as the GPU s shared, constant, and texture memories present access patterns that are unfamiliar and unintuitive to programmers and thatfavor speci.c, specialized mappings.

code optimized for specialized access patterns may not perform well or be portable across multiple vendors platforms and different hardware generations.


Dynamic Temperature Analysis Voltage selection based on dynamic temperature analysis is more time consuming than the alternative using static analysis.

dynamic analysis is more accurate and, thus, potentially can lead to huger energy savings.


With a 4 KB data cache, the .rst nested loop would only exhibit cold misses.

the second nested loop would exhibit cold and capacity misses.


For example, at t = 20 s all of the banks are refreshed with a period of 24 ms when the bank-wise refresh is off.

when the bank-wise refresh is active, only the bank 0 and bank 3 are refreshed at this period and other banks are refreshed at higher periods.


Furthermore, full motion video represents highly dynamic content which does not match well with the title cache abstraction of Pixel Bridge.

a more video-speci.c application that marshaled NDDI resources in a manner more in line with how video is compressed and represented may be more e.ective.


On the contrary, the .rst .t policy is widely used in many allocators, such as the buddy system allocator.

the .rst .t policy leads to a higher use of the blocks at the beginning of the free list and a lower use of the blocks at the end of the free list.


Multiple grid legalization with minimum layout perturbation can be formulated as an integer linear programming (ILP) problem.

in general, ILP solvers not only take very long runtime for large scale problems, but also have dif.culty in resolving the con.icts of grid constraints and ground rule constraints.


Unless the in-order commit stage (or some other structural hazard of the processor pipeline) is a bottleneck, the entire computation of the branch condition is removed from the critical path.

in ASH inter-hyperblock control transfers are never speculative.


These simulation and tests are designed by different teams for different purposes.

we believe that some of them may have good correlation to validation results.


Such an arbitrary ordering is decided in the area-minimizing SPFD computation proposedin[5].

inrobustrewiring we take the advantage of the known information of the criticality of a wire and use it to give the privilege (highest .exibility) to the most critical wire, and therefore a replacement for this wire is more likely to be found.


The exponential distribution for state transition times, a prominent property of CTMDP model, is sometimes insufficient to model practical cases, especially when we model the first request arrival in the idle state period [13], where the inter-arrival times of service requests are in this case generally distributed.

it will not hurt the quality of the present paper if we assume that the task inter-arrival times are exponentially distributed during the active state period since thermal management is only in effect during the program execution.


Previously, K2 was one term amortized acrossthecustomer svolumealone;here,thecost ofthe .xed metal routing masksis separately amortized across the totaldevice volume, which produces some savings.

this comes at a slightincreasein K0 and K3 .


Notation i::j::k describes range of i to k in steps of j. which is resilient against bitline noise during voltage sensing.

since manufacturers often choose the density of 6F 2 DRAM cells, we derive models using 6F 2 as a conservative point of reference that favors DRAM.


It is easy to generate twists along the bus line at all possible locations that wires can be twisted.

more twists bring more resistive and capacitive contributions because of the metal-to-metal via in a twist.


GN is a simplified version of the Newton s method, which has a very desirable quadratic convergence close to the minimum point.

for non-convex surfaces, GN can get lost far from the global minimum.


in [8] uses probabilistic transfer matrices to represent gate functionality.

their work focuses only on logical masking for given gate output error probabilities, without considering electrical and latching-window masking.


sumption per operation compared to CMOS nodes since dynamic energy dominates at these voltage nodes for both CMOS and GNR TFETs, and GNR TFETs and CMOS circuits consume comparable dynamic energy.

as the supply voltage is scaled down, whereas static energy is still negligible for GNR TFETs at moderate activity factor, it becomes comparable to dynamic energy for scaled CMOS nodes, such that the bene.t brought by low static energy of GNR TFETs becomes more signi.cant.


The framework provided here can be used to calculate the bending profile of the beam (u(x,t)), which can be subsequently employed to determine the important properties of the NEMS device.

the left-hand side of (3(a)), considering (6), can be easily re-written as (8): .4u(x) .


Compared to Unlimited-pin, Figure 8 shows that the performance of ComboAS is degraded by 5% on average.

after adopting DynLat, the sytem performance is bounced back by 3% on average (up to 14%) and is comparable to the Unlimited-pin in most cases.


These differences follow a similar pattern.

our interest is centered on why circuits with values of current far from the maximal have larger dispersions of those values (Figure 4).


It is also possible to create an equivalent Hough image by performing the transformation at each quantized e and O.

this would run the vertex program once for each point on the approximated curve.


Thus, an exact evaluation of the energy saving for such a soft constraint will require a full pro.ling of all possible value combinations in a group of condition operations.

such a process can be prohibitively expensive.


Because only a few MLs are discharged during a search, the ML power consumption is minimal.

the pull-down path is too long, such that the ML discharge is slow in case of a match.


The accesses to the shared memory can be implemented with various interconnect topologies.

for reasons of low complexity and high speed, the most common approach is to use a common system bus.


Yet another way of estimating the NWC efficiency is to evaluate the performance gains that we can obtain by increasing the baseline caches with the resources invested in the NWC.

although not presented in the paper, we do believe that it will not provide as much benefits as we achieve using an NWC.


[4] propose trading storage overhead for memory power consumption by reducing the number of data devices per rank.

this requires design of custom DIMMs and memory-processor interfaces, which is expensive.


If the circuit were to be mapped using 4-LUTs, then the node v2 will have to be duplicated and the mapped solution would contain 2 LUTs.

if we consider the concept of overlapping reconvergence regions, then the whole sub-circuit can be implemented in a single memory array with 5 inputs and 2 outputs.


2.2 Related Work Traditionally, the cache read power can be reduced significantly by employing a pulsed-wordline technique [4] to turn off the wordline when a sufficient voltage differential has developed on the bitlines.


Therefore, for a circuit with large fan-out for state inputs, such as s838, the area overhead in the FLH technique can be more than the others.

number of fanouts in a circuit are usually not high (2.3 on average per scan .ip-.op as can be obtained from column 2 and 3) to satisfy delay constraint of a circuit, since higher fanout means higher load at the output of a gate and hence, higher delay.


So, millimeter-wave bands make high band-width and therefore high baud-rates available.

when baud-rates approach or exceed 1Gbaud, the implementation of the baseband is no longer a simple extension of existing methods.


5.1 Description of the Experiment In this experiment, similar to Section 4.2, we have tested the modules at a refresh interval of 1 to 20 seconds with a 1-second increment for 100 rounds at 45 .C (corresponding to 82 ms to 1640 ms with an 82 ms increment at 85 .C).

this time, we monitor the retention state of the cells in each round.


It provides basic communication primitives as well as automated logging and timing functionality.

we still had to implement separate user interfaces and simulated functionality for all tested methods in JAVA-MIDP.


In these cases, MPack can achieve large BRAM reductions through buffer packing.

buffer depths just under BRAM con.guration depths (e.g., 1000, 2000, 4000 etc.)


Compared with the conventional D2133-B2133 system, the decoupled DIMM D1066-B2133 system uses slower devices and thus has lower performance.


As expected, some workloads are insensitive, which attenuates the average performance impact of coherence protocol.

in applications with highly contended blocks, such as NAS benchmarks, coherence is very relevant.


Degradations of transistor performance by variations impacts gate delay, and .nally it degrades the speed and yield of the LSIs.

such WID variations can be compensated by recon.guration.


For 1.9 V, if the voltage changes at 4.8 µs , the error rate still reaches 50%.

when the voltage only drops  Figure 7: The bit error rate when erasing E-MLC8 with vari-Figure 9: The latency of erasing E-MLC8 when supply voltage ous voltage change intervalsdroops to 1.8 V 2.6 V at different voltage change intervals Name Program Read Erase A-MLC16 2.3V 2.5V 2.1V B-MLC32 2.2V 2.7V 2.0V B-MLC128 2.1V 2.7V 1.7V E-MLC8 2.1V 2.5V 2.0V F-MLC16 2.4V 2.4V 2.2V Table 3: The minimum operating voltage for each chip we applied in our dynamic voltage scaling scheme 0 500 1000 1500 2000 2500 Voltage Change Interval (us) Figure 8: The program error rates of E-MLC8 of a block when supply voltage droops to 1.8 V 2.6 V during the previous erase operation to 2.0 V during the erase operation, the bit error rate reaches 0% (0.1 V lower than voltage required for programming), the operation succeeds.


Then, the -th solution of the Gauss-Seidel method is written by (10) If the matrix is stored during the transient analysis, the Gauss-Seidel method (10) is ef.ciently applied for solving (5).

the memory required for storing the inverse matrix over.ows even though this method is applied to a relatively small scale problem.


Second, L3 cache is large enough to allocate the the data in cache before they all die.

it is possible to .lter out the data with speci.c DRC with a simple bypassing method.


These methods all combine the LRU and LFU algorithms using heuristics and are not based on reference models.

iGDR is based on a reference model and adapts to reference patterns that prefer LRU or LFU.


Obviously it is desirable that the total cost over all selected pattern pairs are as small as possible, which would diversify the neighborhood signals states as much as possible.

since the ILP model can only optimize one objective function, and the cost function is associated with pairs of patterns, it is not easy to accommodate the cost within the ILP model.


On the one hand, in order to keep high hardware performance, it is necessary to employ an on-chip memory large enough to hold all the intermediate results, but this typically requires several MBs of memory, which leads to expensive and power-consuming solutions.

if the on-chip memory size is limited (only a few kBs for most of the devices used in the multimedia .eld), the performance is bound by the memory transfers that take place between the off-chip and the on-chip memories at each iteration.


we observed that a great portion of these writes are redundant.


The leakage through M13 and M14 is small, since both are turned off.

m12 is between Vdd and the output, which is low, with M11 turned on, is thus a leakage source.


In this case, if another FPGA function used output data from a previous FPGA function, the application would avoid an unnecessary transfer back and forth from the CPU.

this optimization requires that software does not use the data in between the two FPGA functions, which can be difficult to detect statically due to aliases.


The proposed method exhibits a new method of generating synchronizable test sequences that detect output-shifting faults utilizing multiple UIO sequences.

the paper does not consider the overlapping problems.


All the other benchmarks cost less than 100 seconds.

the alu4 benchmark takes much more CPU time, 54.87 seconds, than the other benchmarks of similar size such as the des area and the s38417 benchmarks.


On the other hand, with 101-stage Set B, the correlation coef.cient of 0.3 is obtained in three variation parameters, and skew reduction by the proposed scheme is expected.

high correlation coef.cient, such as >0.8 is dif.cult to obtain.


Based on the type and location of entities that perform different phases of a fault-tolerant LLC access, we can have different policies.

in this architecture we assume all phases of a fault-tolerant LLC access are done in one entity (Issue entity) and based on this assumption we define three policies: 1.


Active and passive devices, along with device parasitics, can also be retargeted using a cell replacing method [6].

the above method lacks a scheme for targeting interconnect parasitics, which are very important in high-performance and sensitive analog/RF layouts.


For circuits with balanced delays, this cost will be low.

for those circuits where a large number of paths have much lower delays than the critical path, the cost may become high.


Clearly, the MOR has the best performance in terms of the latency and the maximum sustained injection rate.

we also observe that the ROS and the SWR provide a better latency (with a minimum of 1.7× better) for all synthetic patterns in comparison to a state of the art mesh.


This paper tackles the task of sleep signal generation for microprocessors functional units.

compared to earlier attempts that focused on static generation of the sleep signal when the functional unit is idle for a speci.ed number of cycles [4], the proposed technique introduces a dynamic approach that has a better accuracy predicting the length of the sleep period with minimal power overhead.


Furthermore, they focused only on memory-intensive behavior such as loads and stores and increased current draw by accessing L1 and L2 data caches.

our approach does not require microarchitectural knowledge and relies on measured voltage droops in a closed-loop measurement infrastructure.


The design is created and verified by using a host PC/workstation, and then transferred to the FPGA prototyping system so that it can be run on the PowerPC hardware cores embedded in the FPGAs, as shown in Figure 1.

it is not always possible to make the design at the specification level run on the embedded PowerPCs, because the entire design might be too large or complex to fit into the embedded PowerPCs.


A common approach to handling these memory errors is to use error detection and correction hardware [14, 13].

embedded systems are usually sold in huge quantities and thus tend to be more sensitive to the per device cost as compared to their high-performance counterparts.


These architectures can also be compared on the basis of flexibility.

no procedure to perform flexibility comparisons for reconfigurable hardware has yet been widely accepted.


The observability Gramian can be approximated similarly.

calculating the Gramians from time-domain Lyapunov-type equations are as dif.cult as calculating the L{{ where L denotes the Laplace transform operation.


Table 1 and Table 2), the MET values from [1] are also included together with the 5-digit activity codes used in the compendium.1 Once again, it has to be noted that this values were not developed to determine the precise energy cost of a speci.c physical activity within individuals, as also pointed out in [1].

these MET levels can be used to distinguish activities of light intensity (< 3.0 METs), moderate intensity (3.0-6.0 METs) or vigorous intensity (> 6.0 METs), which provides the reference data required for the intensity estimation task of this paper: lying, sitting, standing, ironing and walking very slow are regarded as activities of light e.ort; vacuuming, descending stairs, normal walking, Nordic walking and cycling as activities of moderate e.ort; and ascending stairs, running, playing soccer and rope jumping as activities of vigorous e.ort.


Absolute Igate of an NMOS L-Vt/To transistor in dependency of terminal potentials (Fbulk = 0 V) Fsource Fdrain Fgate |Igate| 0 0 0 0 nA 0 0 VDD 24.8 nA 0 VDD VDD 15.04 nA VDD VDD 0 15.04 nA 0 VDD 0 7.83 nA VDD 0 0 7.83 nA VDD VDD 0 15.66 nA VDD VDD VDD 1.1e-9 nA  LLH vs. LHL Internal node voltages Vint of LLH and LHL configurations are nearly the same.

the conductances gsub_stack of the sub-stacks differ.


In this fault model we assume that scan-in and scan-out operations, being relatively slow, can perform correctly even in the presence of a fault.

a .ip-.op may fail to capture a value at correct timing during system clock operation, thus requiring the use of launch-on-capture test strategy to detect such a fault.


Using an appropriate timing constraint for NONDET/8 allows us to move the critical path of the design back into the ALU stage.

selecting a timing constraint that is highly unlikely to be met by the routing process results in a longer critical path delay.


The operation includes writing back dirty L2 data and manipulating the L2 tag bits.

this operation applies only to the L2 lines that are tagged as belonging to the nonspeculative chunk.


It turns out that the PPD is exclusively dependent on PS as expected.

in order to shed light on its portion of the overall time readings in isolation, we conducted disjoint measurement runs freezing the random number to r = 100 for BP = 10 within the backo.


From Table 1, PCM SLC write latency is 10×-40× larger than that SRAM.

through a set of write optimizations such as write coalescing[6] and aggressive  word-line/bit-linecutting[5],PCM canachieveabout the same performance as DRAM ( [6] reported 1.2x slowerthan DRAM).Simulation results[5] showthat the logic density improvement per bit against SRAM is about 10×.


Applications produce different circuit lifetimes.

the circuit life- it is been shown that the distribution of application time is different for different applications.


A. Computational Overhead Imposed by Macromodeling Combining the cost of lookup table generation, VF on the lookup table and regression on residues yields a computational overhead of around 8 hours prior to initiation of RF circuit synthesis.

it must be kept in mind that this is a one time cost for a given RF CMOS technology.


We integrate a temperature-dependent EM model that accurately captures the effects of current crowding and Joule heating on the C4 pads into our MILP-based C4 placement algorithm.

prior work [2] models EM using simple constraints that assume that the maximum current through a C4 is temperature-independent.


This induces a current transient, which causes an upset due to the feedback present in these circuits.

radiation strikes in combinational logic indirectly affect the SER of latches.


The retargetable framework Nimble [8] and the work presented in [9] automatically compiles system-level applications speci.ed in C onto a target architecture of a combined CPU and FPGA.

the compiler only exploits instruction-level parallelism (ILP) in loops but not task-level parallelism.


Error detection usually only provides information about the a.ected memory address or hardware component.

no information on the semantics of the error, e.g., which data is a.ected, is provided.


In BIG, the maximum number of INT operations executed in a single cycle is two operations because the number of INT FUs is two.

hALF+FX can execute upto seven INT operations in a single cycle8 .


Under the same environment condition, Relaxed design reduces data retention time to 3.24s, which is still suf.ciently long and induces trivial refresh overhead [9, 10].

when the applied switching current is .xed at 200µA, the required write period t reduces from the baseline s 8ns to 4ns of the relaxed design.


We observed an asymp-totic linear increase in computational cost versus the number of gates for both cases, which follows the linear increase in computation with number of subcircuits generally seen with waveform relaxation.

note that the linear asymp- tote for mixed-mode with accuracy management grows at a much slower rate with circuit size.


The new idea in our proposal is to predict how long a thread should stay in runahead mode.

existing proposals predict only whether or not to enter in a full runahead execution episode (i.e., a runahead episode that ends when the runahead-causing miss is serviced).


Figure 2 indicates that the memory bandwidth does not become the bottleneck if the .op/DRAM byte ratio reaches 0.5.

if the .op/DRAM byte ratio is between 0.25 and0.5,useof thevectorcacheis mandatory toincreasethe sustained performance up to the peak.


Exploiting Subarrays Inside a Bank to Improve Phase Change Memory Performance Jianhui Yue, Yifeng Zhu Electrical and Computer Engineering, University of Maine jianhui.yue, yifeng.zhu@maine.edu Abstract Enabling subarrays reduces memory latency by allowing concurrent accesses to different subarrays within the same bank in the DRAM system.

this technology has great challenges in the PCM system since an on-going write cannot overlap with other accesses due to large electric current draw for writes.


With RpStacks, architects would explore the structure of processor design just as the insight-driven approach.

as a single run now covers all possible latency con.gurations of a structure in much shorter time, they can test more structures in the same amount of time or .nish the exploration earlier to save the development costs.


Note that burned fuses are reproducible at the foundry, and therefore cannot be used as a countermeasure for the foundry e.ect.

they may not be reproducible for average customers who may not have an access to the fuses without depackaging and invasively probing the chips.


4.3.2 CostResults Finally, we apply the cost model described in section 2 on the area values to estimate thedie-cost.

because the MCNC benchmarks are very small, we need to scale the core area to a reasonable value.


20 15 10 5 plication exhibits very heavy data dependencies; so, the introduced misses can be tolerated in the background withouthurtingperformance, asthe corresponding cycle counts in Table 2 imply.

for lucas, since the increases in miss rates are very small, invalidating dormant linesdoes notintroduceany tangibleperformance overhead.


This model does not include scattering effects that may further effect the I-V characteristics.

since we use the surface potential approach, these models can be easily included in the future.


They introduce a small prefetching cache in the DRAM to improve system performance and reduce power consumption.

their technique is designed for close page mode, where the page hit rate is forced to be zero.


FPGAs implement these very well, but the time-multiplexed Malibu architecture does not, averaging 15x slower (M-CAD, Wf =1).

on the right of the graph where the FPGA performs poorly are the coarse-grained benchmarks.


In general, a state element with a higher Impact Weight is a better candidate for the next trace signal.

simply selecting the state element with the maximum weight may not be a good choice because based on our observations, there may be other state elements with similar yet slightly smaller weight values which may result in a higher state restoration ratio (SRR).


Breaking the cycles in the CDG is either realized by restricting the routing algorithm to avoid the prohibited paths or splitting each physical channel along a cycle into a number of Virtual Channels (VCs) [5].

adding VCs imposes extra hardware requirements and a complex control logic to the routers [6].


Pseudo-code for CVS can be summarized as follows: We note that the step CONSTRAINED TOPOLOGY , guarantees that there will be no VDDL driven gate that feeds directly into a VDDH driven gate.

this constraint acts to curtail many potential VDDL cell assignments as later results will demonstrate.


This contributes to higher performance (Figure 10) and lower energy consumption (Figure 11) at low memory utilization.

figure 10(c) and Figure 11(c) show that DTail-V also performs better at high memory utilizations for higher density DRAMs.


We can see that for 0.4 V case, the standard deviation of current divided by the average current is about 41.45%.

if we boost the VGS to 0.8 V, the standard deviation of current divided by the average current is reduced to 8.89%, about 4.66. of reduction.


Therefore, it can improve both power integrity and power e.ciency with limited decaps budget.


Availability of these memory block addresses are recorded against nine Round-robin cache con.gurations wit B = 2bytes.

their set sizes and associativities are different.


Several behavioral synthesis tools are commercially available [8, 3, 2, 4].

their adoption Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.


Turning off the FP unit may increase the number of instructions executed by a runahead processor, since it allows more instructions to be executed during a runahead period by enabling the processor to make further progress in the instruction stream.

this optimization reduces the number of FP instructions executed during runahead mode, which may increase ef.ciency.


In a random logic network, logic gates are not usually skewed to favor a certain switching direction since outputs can either switch high or low during evaluation.

in a monotonic network, logic gates can be severely skewed to favor a certain switching direction by sizing up devices or using low Vt devices tospeed up evaluation.


Overshadow is a softwareVMM-based memory encryption technique that can protect application data from a security-compromisedOS[9].Similartechniques couldbe usedtoprovide additionallevels ofprotection amongdifferent applications, or different guest virtual machines.

overshadow maybe abletodetect certain cases when an application sdatais modi.edduetohardwarefaultsthat may occur when another applicationis executingthroughdataintegrity checks.it cannotpreventthe corruptionfromoccurringinthe .rstplace.


For the nominal design of analog circuits, big improvements were made in the area of symbolic [5, 12] and simulation-based [4, 10, 14, 16] algorithms.

for the design centering statistical [13, 17] and deterministic methods based e.g.


It can be seen that RR+NLP performs better than the other two local policies.

there is a performance gap of about 30% between the optimal MDP policy and that of RR+NLP.


The average energy overhead of Scheme 2 is 14% over Scheme 1.

scheme 1 minimizes the energy required for additional L2 accesses while requiring signi.cant energy for using SEC for all cache blocks.


This larger area and energy is driven by the wiring required to support a large p design.

[2] also shows that, by using a pt < 0.5 heterogeneous multicontext BFT (previous section), we can bring v the energy per operation below O( N) for any p < 1.


Assuming that the two cache levels are inclusive, the misses in the selected L2 con.guration are considered to be misses in all L1 con.gurations.

once the selected L1 caches are in the system, the accesses seen by the L2 cache change.


The inclusion of pass transistors in the data path adds delay and degrades the signal strength due to the associated voltage drop.

this design decision is fully justi.ed by the fact that inter-layer distances are, in fact, negligible.


These protocols are easy to implement and entail only little overhead since no complex computations have to be performed.

most security architectures based on pre-deployed keys su.er from problems caused by poor scalability and vulnerability to node capture.


Note that the reconfiguration of the noise shaping is clearly visible, together with the domination of white noise (for GSM) or quantization noise (for UMTS) within the corresponding bandwidths.

a certain amount of offset and non-linearity is appreciable in the measured spectra, which is originated in the input signal conditioning at the PCB level (probably in the single-to-differential conversion and the common-mode setting, which is now under improvement).


Ideally, window comparator threshold Vc can be selected to equal V max k when designing PCA BIST circuits.

due to process variations, realized comparator thresholds are random values which are distributed around the designed threshold.


Depending on the design, there is a height where domain walls will no longer be created from in-plane .elds.

as coupling between two layers becomes weaker as the distance increases, Eq.


In this case, the overall failure time is driven by the local via voids rather than the TSV void.

with more void-free local vias, in.uence of TSV void gets stronger.


Extrapolating historical data would lead to 6-8 FO4s per clock cycle within a few generations [6].

such fast-cycling machines pose many difficulties.


Introduction Traditionally, deterministic worst-case analysis has been used to estimate circuit performance.

as technology continued to scale and transistor sizes decreased, concerns regarding the effects of process variation increased accordingly.


For the stack sizing, N stacking transistors are usually sized to be N times bigger than a single transistor to deliver the same amount of current.

the threshold voltage varies substantially with transistor width due to the inverse narrow width effect in the near/sub-threshold region.


Then closed their hand, in a fist, to activate the blackboard.

these controls didn t fit within our user s mental structures because of the WiiMote s A button initial function: blackboard appearing in the LED s glove user interface.


Errors We expected to see a decrease in user input errors over time.


By comparing Figures 6(a) and 6(b) we can seethe e.ect of our simpli.ed out-of-orderprocessor,because anincreasein the number ofMSHRs reduces the execution time of thebenchmark.

comparing Figures 6(c) and 6(d) we can see that the number of MSHRshasnoimpactinanin-orderprocessor, asexpected.


A single microscopic model of NBTI is not fully established yet.

the Hydrogen release from the substrate/gate-oxide interface states [2] and the hole trapping in the gate oxide [18] are the most cited causes of NBTI.


For a system consisting of 16 clients with a worst-case bandwidth requirement of each client equal to 1/16th of the gross memory 2For simplicity, we do not consider the power consumption of the clock sources.

we assume that the clock source of the coupled architecture consume less power than the multiple sources in the decoupled architecture.


For long latency wires, the wire throughput can be increased by inserting pipelined latches at regular intervals.

the use of repeaters and pipeline latches at regular intervals requires that the voltage levels on these wires swing across the full range (0 - Vdd) for proper operation.


MLC(DM) signi.cantly increases 55% of cache energy induced by the complex and long read and write operations.

the overall energy still reduces 3.3% on average, thanks to the doubled cache capacity which reduces the costly accesses to main memory.


The data rate is increased by improvements in the linear density (which had been growing at the rate of 30% per year [HTech]) and the rotational speed of the platters (in Rotations per Minute, RPM).

since the viscous dissipation has a cubic relation to RPM, increasing the rotational speed causes more heat to be generated.


In this paper, we concentrate on estimating yield loss due to read access failures, as this type of failure has a strong impact on determining the performance and power consumption of the memory.

the methodology can be extended to account for other types of memory failures.


Therefore, the additional testing time penalty is determined by serialized capture cycles for each consumer tested through the functional bus.

when the producer is connected directly to consumers, the test application time penalty (for each test vector) is given by the loading time of the producer s outputs.


For regular wire-to-wire coupling, the electrical .eld (E-.eld) is often blocked by other wires.

for the top metal layer, there are no other blockages between TSV and wires, and hence the largest TSV-to-wire coupling capacitance will occur in this region.


As can be seen from Figure 1, the selfcompensating space range is 260nm to 340nm each side.

in our study self-compensation is achieved by having iso spacing on one side and dense spacing on the other.


A fully pipelined functional unit can process new instructions every cycle in the absence of timing errors.

a timing error can happen in any of the internal pipeline stages.


The .rst 3D physical design .ows utilized traditional, proven layout representations, for instance, one slicing tree per active device layer.

the disadvantage of these approaches is that the tight linking between layers is neglected and, for example, successful thermal-driven design is often not achieved.


This platform supported multi-channel sensing, multihop wireless networking and a Linux OS with few resource constraints.

it did not support tight time synchronization; most of the results using this platform were synchronized off-line using a starting pistol as a marker.


Recall that in the split-radix architecture, the type-2 butter.y contains 2 complex multipliers while type1 contains none.

the type-1 butter.y can be used to compute A[k] and A[k +1] while the type-2 computes B[k] and B[k +1], so the existing hardware can be fully utilized.


A higher value on M is preferable since the peak power consumption is spread over a longer time.

the phase difference must satisfy equation 3, which is why case e is not realisable.


Whether the amount of time spent over budget is deemed tolerable or not depends on the particular constraints of the application.

considering the tiny percentage of power spent over budget, we conclude that VL does not greatly impact safety.


When the pFinFET is severely forward-biased, the leakage current approaches very high values, similar to those of LP-mode logic gates.

the difference between the LP-and SG-mode logic gates lies in the delay characteristics.


7 indicate the results of the multiplications after the .rst, second, third and fourth cycle, respectively.

hi is already computed when S/CXYi,a is ready.


Since the Doppler coe.cient only varied during 1 ms (much less than the duration of one OFDM frame), the algorithm was not able to detect this short period of motion.

the damaged data in the a.ected OFDM frame rendered just a few damaged video frames, without a.ecting the visual quality of the rest of the video.


This link is randomly chosen according to pre-assigned probabilities that depend on the message source and destination.

due to the stochastic character of transmission paths and link congestion, neither Dumitras and Marculescu, nor Pirretti et al.


The same argument holds for the induction step also, with the only difference being that the tracks in the P units just below the current newly added power line in the optimal layout (say, in track t) might contain another newly added power line (say, in track w).

in this case, the induction hypothesis guarantees the existence of a newly added power line (say, in track w ) in the adaptively power routed layout (corresponding to the power line added in the optimal solution in w) that lies in a track with coordinate no less than that of w, so that the induction argument goes through as before if w = t, the induction hypothesis is trivially true).


Quality metrics such as OpenMORE [5] support the IP integrator when deciding which of several functionally equivalent IP cores is the one that minimizes risk during integration into a system or platform.

iP provider and integrator have to assess IP cores manually, which is of course time-consuming and subjective.


There is no inherent problem in generating checkers for them.

the e.ciency of the checker will su.er greatly as memory recycling becomes very di.cult (as will be explained in the next section).


below the nominal value) to program a memory cell without causing a failure.

a larger BECD reduces current density and joule heating, requiring a higher magnitude of current to reach the desired temperature.


At this time, the system may sample all sensors at all epochs for a few strides until a sufficient training set has been constructed, so the algorithms may be applied to yield a better sampling schedule.

the assumption here is that the change is subject behavior that has led to the degradation of the original sampling schedule will be long lived so that the energy expended in collecting the training set may be amortized.


In all 16,000+ simulations, all data sequences were found to match exactly.

when the synchro-tokens control logic was bypassed by keeping the data ports and local clocks always enabled, the data sequences nondeterministically mismatched on all local clock cycles.


It has been shown by a computer program [18] that, for the random functions, the percentage of the orthodox functions is approaching 0 when the number of support variables increases.

the situation is different for the functions from the practical applications.


Prefetch instructions are sent to the address queue in the processor.

contrary to other memory access instructions, they do not wait in the queue until retirement.


When an ECO FF is assigned to a scan chain ck with SD(ck)<SD_limit , the value of SD_limit remains unchanged.

when an ECO FF is assigned to a scan chain ck with SD(ck)=SD_limit , the value of SD_limit increases by one as long as the new value is =DMAX .


Therefore, the full merge cost grows rapidly and the performance is decreased.

d-FAST shows the better degree of association compared to FAST.


In this case, we might be committing errors in Elmore delays not only at the merged node but at possibly other nodes in the network.

as we shall see in the next section, the algorithm is able to crunch quite effectively with fairly tight error control on the actual delays measured by transistor-level static timing analysis.


The .rst approach is throughtheuseofadditionalsensors, especiallythetechniquesthat combine compasses with gyroscopes through the Kalman .ltering [10].

since the gyroscope does not measure the absolute orientation, it rely on the initial value of digital compasses, which may suffer from systematic offsets.


Introduction With the demand for high performance systems, dynamic circuits, such as Domino logic, are widely used in critical paths of design.

with continued scaling trends, it becomes more difficult to scale Domino circuits due to its low noise margin.


For an algorithm to be; interesting, it must be better than the oblivious algorithm, in particular, it must have sub-quadratic work complexity.

if messages can be delayed for a "long time", then the processors cannot coordinate their activities, leading to an immediate lower bound on work of ~(p t), even if only one processor crashes.


It implements the ILTOS API, and allows applications to be compiled directly to the Windows host and run signi.cantly faster than the VP.


The main reason for the higher performance of domino logic compared to static CMOS is the reduced input capacitance seen by driver gates in domino logic.

the higher performance of domino logic comes at the expense of higher power consumption because the switching activity in domino circuits is, on the average, double that in CMOS circuits.


By default, the service is not auto-enabled.

upon log-in to the service, the default network control setting is set to drop all traffic, with certain services always required and not available to the instructor (e.g.


Numerous other previous works proposed hardware-based defect tolerance techniques, such as [2, 4, 5].

these works focused on providing hardware-based reliability solutions that are limited to processing cores in uniprocessor systems and do not address the testability of non-core modules that are abundant especially in chip-multiprocessor designs.


In addition, it is distributed because the minimization of ||ei(si)||2 is local for each node at level i +1 when spanning this node to mi nodes at level i.

in the K-Best, the spanning-sorting-deleting process is based on the PED (Ti(si))of KC spanned nodes at level i.


It represents the optimal solution if each region were allowed to operate at its own supply voltage.

this would require several voltage regulators and additional level shifters between the regions.


The potential drawback is a lower system utilization as not all application components will be used at all times.

our results show that network processing applications are very regular and simple.


The CPU time needed to generate the pin assignment for all regions was over one day.

since this is a onetime design e.ort, the high CPU time for this large commercial bichip is acceptable.


3c, when Diluter1 .nishes executing, and there are enough free adjacent cells for accomodating Diluter2.

this delay can be avoided by shifting Diluter1 to another location such that the space fragmentation is minimized.


Variation-Aware Placement for FPGAs with Multi-cycle Statistical Timing Analysis Gregory Lucas Chen Dong Deming Chen Department of Electrical and Computer Engineering, University of Illinois Urbana-Champaign gmlucas2, cdong3, dchen@illinois.edu ABSTRACT Deep submicron processes have allowed FPGAs to grow in complexity and speed.

such technology scaling has caused FPGAs to become more susceptible to the effects of process variation.


Sequence pair outperforms B*-tree by <1.0% in wirelength and, marginally, in runtime.1 The difference is insuf.cient to declare a winner as further tuning may improve results by 1-2%.

the choice of .oorplan representation appears to make little impact overall.


This is because the chains become shorter and require fewer shifts per test pattern.

the scan cell dependencies in broadcast scan mode cause ILS to become inefficient at higher compression values and we observe a drop in fault coverage.


An approach that avoids these currents altogether consists of introducing a select transistor to each memristor element, similarly to a DRAM [9].

this approach severely impacts the density advantage of memristor arrays.


This is especially unfavorable for instruction due to the instruction format.

the proposed VC cache can effectively reduce the cache access power without the necessity for the cluster of 0 bits.


Cooperative multithreading currently seems to be the choice for the simulation kernels of most modeling frameworks as it provides efficient implementations due to low runtime overhead.

as we seek to further improve simulation performance (by exploiting the inherent design parallelism) through the use of multiprocessing we must from cooperative to preemptive multithreading in the simulation kernels.


Our technique would then incorrectly suggest infeasibility.

experimental evidence suggests that such cases are relatively infrequent.


SSD5 is superior to SSD4, because a request that needs to read/write four pages can render two chips busy in SSD4 by executing two consecutive interleave read/write operations.

for the same request only one chip is rendered busy in SSD5 with the execution of a single interleave multi-plane read/write operation.


Slick [14] avoids the redundancy for results predictable instructions to improve the performance whiling running redundant multithreading.

they mainly target on CPUs and largely ignore the GPGPU architecture.


4.1 Selection of target tapping locations Direct computation of register tapping locations that provide a set of clock skew values is very dif.cult due to the close clock-tocircuit coupling in rotary clock based designs.

the derivation of clock skews for a given set of tapping locations is straightforward.


The test signal m ust have the following requirements: i t must disclose faults in the circuit, and, in addition, it must disclose which component is faulty also.

on the other hand, it shouldn t have a n excessive number of different input patterns.


3.1 SDRAM Power Model SDRAM has various power states and they show di.erent behaviors for power consumption.

for simplicity of our presentation, we only consider four power states here: I/O state (I/O), Idle state (IDLE), Powerdown state (PD), Self-Refresh state (SR).


For example, to activate the fault stuck-at 0 on the third bit of the integer signal rmax, the signal fault[56] must be set to 1 , since the range for faults stuck-at 0 on rmax is from 54 to 61.

to activate the fault stuck-at true on the if-then-else condition the signal fault[73] must be set to 1 .


The only di.erence that generates a different behavior is the reduced number of entries per node because of the additional bit array.

as it requires one byte for each 8 entries, the impact is small.


In addition, to reduce leakage, such memory will likely operate at higher Vdd than the logic.

even accounting for this fact, the on-chip memories will incur substantial energy losses due to leakage.


2(a) where no heat diffusion to other modules happens.

consider another type of .oorplan such as .oorplan-2 in Fig.


The process scaling reduces the wire spacing, thus, enhancing the relative inductive coupling.

capacitive coupling is not relatively increased due to the lower aspect ratio.


They were used to working on a test board and spend one second to boot the OS to the system.

in high-level platform, it took more than one second to boot the OS.


This re.ects the cost of invoking the programmer-supplied merge function.

in all the data .ow assertions we encountered, we did not need to apply policies to integers, so this might not have a large impact on real applications.


(which could be counteracted by adding another key bit to the chain.)

when additional bits that are not key bits for an LSIB are present in the chain, the advantage of not repeating guesses is less because the different guesses may vary only in non-key bits until the expected time approaches the initial pure-random case.


Additionally, since graphene has a small thickness of 0.35 nm, its capacitance is smaller compared to copper; hence graphene is expected to have a smaller RC delay.

when graphene is placed on a substrate, the mean free path drops signi.cantly due to the scattering of charge carriers with surface polar phonons, trapped charges at the interface and resonant scatterers [14].


In [2], authors have discussed the method to estimate the leakage of a logic gate considering the interaction of leakage components within a logic gate (intra-gate interaction).

it does not consider the interaction of leakage components of different logic gates (inter-gate interaction).


As we see, the energy reduction of the proposed approach increases as the cache grows in size, because the frequency of footprint invalidations is reduced.

although increasing the BTB associativity has the same e.ect  1.00 129.compress 132.ijpeg 129.compress adpcm(e) 132.ijpeg adpcm(d) adpcm(e) 0.95 adpcm(d) mepg2(e) mepg2(e) mpeg2(d) mpeg2(d) epic(e) epic(e) epic(d) epic(d)0.90 pegwit(e) pegwit(d) pegwit(e) Normalized Execution Time(clock cycle) pegwit(d) Normalized Total Energy 0.85 1 2 4 816 Execution-Footprint Invalidation Penalty (clock cycle) 0.80 4 8 163264 Cache Size [KB] Figure 7: E.ect of Footprint-Invalidation Penalty Figure 8: I-cache energy vs. cache size on the invalidation frequency (i.e., BTB replacements could 0.95 be avoided), the energy e.ciency obtained by the HBTC approach degradeds when the associativity is changed from 1 to 32.


Furthermore, real-time value feedback for discrete optimization does not occur.

multipass, reverse pass (dead code removal), and complex optimizations are easier of.ine.


In principle, these could be encoded in many physical variables, from occupation of quantum dots by single electrons with occupation probability of neighboring dots mutually in.uenced by their Coulomb repulsion, to the orientation of magnetic spins in.uencing each other via the exchange interaction.

we choose to map the MRF probabilistic computation onto nanoscale CMOS, which is by far the most mature and well-controlled technology.


When both threads reach the conditional branch instruction and if the condition is true for both threads then the two threads are concurrently executed (shown in Figure 3.(b)).

if the two threads take different branch paths then only one thread can execute at a time (shown in Figure 3.(c)).


Upon requesting H, if we look up T3 s local L2 bank concurrently with its TR table we will satisfy the request directly from the L2 bank without any need for the replicated entry h. As such, h becomes super.uous.

if H is requestedby atiledi.erentthanT3,H sSHT(T12) needsto be contacted tolocateH.Hence,inthis case we still need to maintain aprincipal tracking entryforH atitsSHT.


Clock gating with multiple clock domains is an efficient technique to reduce unnecessary power dissipation by disabling the clock to a circuit [4].

a certain clock gating pattern may induce the resonance phenomena with large voltage noise.


We find that using small detector and modulator capacitances optical interconnects (~10fF) yield superior performance compared to CNTs (electron mean free path of 0.9µm) and Cu for switching activities greater than 35% and 20%, respectively.

improving mean free path of CNTs to ~2.8µm increases the crossover switching activity to 80%.


Non-tree solutions (e.g., [13], [12]) use redundant paths from clock source to sinks to handle variations.

they typically dissipate more power than clock tree structures, which are relatively less tolerant to variations.


Here the distance r is proportional to the average of the two wire lengths and is chosen such that deviation in routing will have minimal impact on delay.

two interconnects of unequal lengths, could have shared run length and be at a distance less than d from each other.


We showed that area saving is signi.cant, taking advantage of slacks available in a network.

the repeaters are of one size and there is no consideration about the feasibility of repeater locations.


This is also the goal of sub-function growth.

as we mentioned above, there are other factors that in.uence the current distribution.


It is obvious that Singleton algorithm can be directly implemented with the structure in Figure 1.


This instruction is selected in cycle 2, to be executed on the functional unit on cycle 4.

as it is faulty, it takes one additional cycle.


If the order of the target LBAs in the TRD frames is ascending, we refer to the corresponding TRIM command pattern as SEQ-TRIM.

if the order of the target addresses in the TRD frames form a random access pattern, which has been used for writing data in the previous step, we denote this TRIM pattern as RND-TRIM.


This poses no special problem for conventional .nite difference techniques.

allowing asynchronous thermal element times makes it necessary to compute the temperatures of an element s (transitive) neighbors at the local time of the advancing element in order to compute the element s next temperature using a bounded-order approximation function.


In [4] Johnson encoding was first exploited to simplify the control logic of dual-clock FIFOs.

to minimize the throughput drop caused by synchronization latency, the FIFOs have to be sufficiently large.


As we mentioned ab ove, the difference of leakage saving is not very large.

our MLP-C model can achieve a much less sleep transistor area penalty.


IV we developed a method to estimate l.bht;k(·, k)l, which quanti.es the approximation error for the selected subspace Fu,t;k. This metric discloses inaccuracies of the selected subspace, which in turn affects the success rate of an attack.

this metric neither includes the algorithmic noise of parallel active circuits nor the noise inherited from the measurement process.


Our algorithms do not explicitly account for mini-graph performance bene.t; partly because the indirect bene.ts of resource ampli.cation are smaller than the direct costs of serialization and partly because they are also more dif.cult to model.

the models can be easily extended to account for direct performance bene.ts, like ones provided by custom latency reduction [4, 18] or explicit tolerance of some latency in the underlying micro-architecture, e.g., a pipelined scheduler [15].


For smaller values of the median max delay, the power sensitivity to delay increases, as described in Figure 6, amplifying the sixth effect listed in Section I-C, and thus providing more potential bene.t.

the region to the left of dmedian = 300ps corresponds to .hard > 3 and is not likely to be used in signi.cant portions of a microprocessor design.


The gather instruction simpli.es the implementation considerably, since it enables using the indices in the SIMD register directly for addressing.

some peculiarities of the IMCI ISA diminish this bene.t.


Since the proposed approach requires formulating feature computation as a matrix multiplication, it precludes the use of .lter optimizations, such as multiply-accumulate (MAC)-stage folding and polyphase decomposition.

the compressed-domain approach has the bene.t of having to process fewer input samples.


With the assistance of an accurate reference ADC, the coef.cients in the ADF can be dynamically updated by a least-mean-square (LMS) algorithm to track the PVT (process, supply voltage, temperature) variations.

the reference ADC usually incurs signi.cant area overhead and the LMS algorithm demands intensive computation.


This increases the number of memory accesses by N access extra (number of extra memory accesses) and the execution time by N cycles extra (number of extra execution cycles).

consequently, the overall energy overhead, E over, is calculated as follows: E over = N access extra × DE access + N cycles extra × LE active recomputation prevents the banks switching back and forth between the active and power-down modes.


However, since it is unaware of the unique condition of each particular chip, it remains overly pessimistic and results in a merely 3% performance improvement.

with only 25 measurements, the proposed methodology can obtain a well-tightened QTTF distributions and a more precisely optimize voltage for each chip, achieving 15% performance improvement on average and 26% improvement at maximum.


On the one hand, these numbers show that proof_verfication2 is, indeed, more efficient than proof_verification1.

the percentage of tested clauses allows one to estimate the coefficient of efficiency of the used SATsolver that is the share of deduced conflict clauses actually used in the proof of unsatisfiability.


Since the broadcast for instruction wakeup is not modi.ed, no overhead is added to the critical path of instruction scheduling.

the broadcast paths of the processor need to be enhanced to broadcast both the old and the new physical register tags during re-broadcast.


Therefore, our solution is only applied for the system using external memory.


Through the analysis of large volumes of data, scientists can gain new insights more e.ectively.

the big data application also poses a significant challenge on I/O systems for the high-end computing (HEC) community due to the large data volume.


Therefore, R(lp) is not to the right of R(bj ), since xi <xo if yi = yo where (xi,yi)and (xo,yo) are points in region I and O, respectively.


A large effort was already made to help the designer to minimize this problem [3-5].

when the expected variation in output voltage is bigger than the acceptable, a trim circuit can be inserted in the design to mitigate this fabrication process effects [6-7].


Communication that blocks process execution and loops with unknown iteration counts can not be handled.

for communication analysis only communication points and the timing behavior between those nodes are of interest.


Speci.cally, the performance difference between the two schemes is less than 7%, on the average.

the SCMB algorithm is consistently better than SCDB, leading to better solutions in 31 out of the 48 different experimental data-points.


By achieving learnings from the spatially and temporally decomposed subproperties, the test generation time of the original complex property can be reduced.

the requirement of clear understanding of the structure and behavior information of both properties and designs limits the applicability of these approaches.


As expected, Phantom-BTB increases the pressure on the L2 10% 8% 6% cache, since it stores and retrieves temporal groups from the virtual table.

even in the worst case, for the TPCC workload, the number of accesses per 1K instructions is low, reaching only 90.


As shown by the equations below1, the reduction in frequency[5] combined with a quadratic reduction from the supply volt age results in an approximately cubic reduction of power consumption.

with reduced frequency the time to complete a task increases, leading to an overall quadratic reduction in the energy to complete a task.


As mentioned above, a recent trend in computer graphics is to implement computationally intensive algorithms on the GPU.

according to [5] it seems that an implementation on the GPU cannot gain a signi.cant speed-up over a pure CPU-based implementation.


This is because each ALM in a Stratix III device can contain two 4-input LUTs, and Quartus II may merge two 4-input LUTs into one ALM.

there is no user control to force such an optimization to happen, and therefore, in the remaining experiments, all multiplexers in the proposed structures are implemented 0 Configurations  (b) Fmax Fig.


Unfortunately, the irregular control flow and complex data access patterns exhibited by many commercial applications render these simple and area efficient prefetchers ineffective.

correlation prefetching [18-24], which is able to remember complex recurring data access patterns, is a more promising approach for these applications.


One might expect the high-performance version of IceFlex to consistently achieve higher frequency but require more Joules per clock cycle than the low-power version of IceFlex.

it typically requires slightly fewer Joules per clock cycle, as well.


This approach is well suited for the application areas that typically have large message sizes, and by splitting them into packets we can obtain a higher utilization of the bus and reduce the release jitter.

since each packet has to be identified as belonging to a message, and messages have to be split at the sender and reconstructed at the destination, the overhead becomes higher than in the previous approaches.


A8.1 Impact on Circuit Delay Variations The maximum current of a CNFET with a single CNT as its channel is highly sensitive to CNT diameter variations [Paul 07].

vLSI digital circuits require CNFETs consisting of multiple CNTs to provide sufficient drive current.


The most closely related technique used in [3] and [20] takes the di.erence between two ring oscillators to extract subcluster delays.

this approach fails to account for the unique interconnect delay between pairs of LUTs, nor is it able to account for register delays.


both g0 and g1 can be colored with one color.

decomposition with g2(X) = x1 x2 does not exist because one of the cofactor relations produced by this function (not shown in Fig.


Comparison of the traf.c distribution for Workload 2, shown in Figure 10, with the results in Figure 9 (b) indicates that the distribution for job-speci.c routing is most similar to that of AH.


Industry initiatives such as the IEEE P1500 Working Group [26] provide some solutions for IP core testing.

they do not address the requirements of at-speed testing.


The advantage of using this approaach is that one can still employ these design topologies at thee optimum best during normal mode of operation by disabbling the non-volatile blocks.

when encountered wwith the need to transit to sleep mode the non-volatile block is enabled.


For larger spare capacities, even higher speedups may be possible.

the achievable speedup will be smaller than 34 since writing randomly to an SSD, to that a secure erased has been applied, is 34 times faster than in the worst-case (cf.


It has an error constant of 1 1 3 compared with 12 for AM2.

its stability region (Figure 2) extends into the right-half-plane covering the imaginary axis.


In some sense, TotalProf is similar to Trimaran.

totalProf signi.cantly alleviates the e.orts of retargeting, and the execution speed of TotalProf is 3 orders of magnitude higher than that of Trimaran.


For simplicity, as in most of other technology mapping works [6][8], we use the unit delay model (prior to placement and routing).

our technique can be extended to post-placement optimization with more accurate gate delay models.


This is not yet reachable with conservative simulation technologies like Spice.

behavior modeling in combination with usage of sophisticated simulator technology like SystemC-AMS and master-/slave-communication, can o.er such high speed-up factors.


As expected, since Single MILP approach solves the C4 placement problem with one-time MILP optimization, it can search for the optimal solution for the whole circuit, and therefore .nd the best solution.

the cost to solve a large MILP (see Column 7) is prohibitive it takes tens of hours to solve the C4 placement problems with hundreds of C4 candidates.


Strategy for Camera Sensor Networks The camera sensor network aims to combine the values of the information-rich visual data and the diversity-rich distributed sensor network.

the limited bandwidth provided by the wireless link poses a serious constraint on sharing of information in a camera network.


The factor by which the sampling rate can be that the periodic sampler performs better than the random sam-reduced is benchmark-specific as can be seen from Figure 8. pler.

in practice, programs do not generate random input One final conclusion that we can draw from the error graphs is streams and this seems to explain wtly P2s6 does not perform bet- that the stratified sampler and the tagged compressor stabilize more ter than R256 on real workloads.


Moreover, write traf.c is far smaller than read traf.c, so that a write-only .ash disk cache can signi.cantly enhance the write performance and reduce the energy consumption of a disk, without taking up much of the .ash memory.

this has a minimal effect on application launches, which involve very little write traf.c.


2.1.3 Post-Latch Global Data Gating The post-latch gating has the significant advantage of relaxed timing constraint as the enable signal does not need to setup to the latch.

it does not reduce the latch power dissipation.


Note that a full-adder can be implemented using fewer CMOS devices using pass transistors approaches.

such implementations suffer from reliability issues.


To meet increased performance requirements and to achieve shorter development times, a decade ago the EDA industry went from gate level to register-transfer level (RTL) abstraction demanding for higher levels of abstraction in the hardware design process.

rTL hardware design is still too low as an abstraction level to design multimillion-gate systems, and nowadays an important effort is being spent to take another abstraction step moving from RTL level to System level, and to develop new design and verification methodologies.


It is a task of the modeling process to formulate appropriate models.

the design example in section 4 demonstrates that these problems are not prohibitive, and can be avoided easily.


Merging of multipliers for the netlists of Figure 3(a) and (b) would succeed under this clock period.

proceeding with adders sharing would fail because the resulting network would have a false combinational cycle and would be rejected by logic synthesis.


Sizing methods using general purpose optimization techniques, whereby a cost metric, such as power or area, is minimized under a set of performance constraints, have been the subject of active research since the late 1980s [7] and o.er the advantage of being straightforward to evaluate, and hence suitable for large and complex designs, but have the limitation of possibly .nding local minima.

by using convex optimization, a global minimum can be computed with great e.ciency [12].


To each router k, it contains its own attackboard, denoted as abk, which is a two-dimension table, and in which each row stands for a unique dependency pattern, and each column represents the necessity of must having data from this router, i.e., a necessary predecessor.

for example, if there is a 1 in the cell of row i and column j, it means that for satisfying pattern i, router j must have already injected data to router k. if the number in the cell is 0, it means that this pattern is not necessary to be after the injection of router j to k. Each router k contains a Current Status (CSk) with length N in terms of bit.


The traditional method of verification is test- ing through trials.

it becomes exponentially more difficult to fully exercise a system through testing as the number of control paths and corner cases increases.


These techniques rely on increasing the node capacitance and using redundancy to improve the tolerance to soft errors.

these techniques come at the cost of large delay and area overhead.


We don t see any di.erence by increasing the size of control VCs in case C because the bottleneck is in the data VC.

in case D, the reception side has been sized based on the round-trip latency and we achieve the maximum possible throughput.


Global checkpointing, a well-known recovery scheme, recovers detected errors by rolling back all processors to an earlier validated state [16], [23].

it will not be scalable as we move towards many-core systems, due to two main reasons: First, 978-3-9815370-0-0/DATE13/ c @2013 EDAA global checkpointing schemes should implement synchronization mechanisms (either at checkpoint creation or checkpoint validation) to guarantee that all structures (e.g.


For example, in Figure 1(a), all paths from e to f pass through the set of vertices {j,n}.

vertex j is redundant, because n is a single-vertex dominator of e. Note, that the notion of dominator is more general than the notion of min-cut in circuit partitioning [13].


It is interesting to consider the full area-delay space because it might be possible that for di.erent transistor sizings the bu.ers might become useful.

in Figure 4, we see that across the range of the design space the fastest delay for any given area is obtained without using the bu.ers.


The circuit contains a syndrome generator, and a large parity tree consisting of XOR structures.

the circuit netlist we used for c1908 was a .attened netlist with the XOR gates implemented with other logic gates.


In [18], an architecture is presented for .ne-grained DRAM access of memory chips in a DIMM by grouping them in logical sub-ranks of different interface widths and accessing them concurrently.

neither of the aforementioned memory controller architectures are predictable or perform logicalto-physical address translation for requests interleaved with different interleaving granularities.


Commercial ESL tools are capable of providing limited statistical analyses of transaction traces [6].

the diagnosis process is still ad-hoc and unsystematic.


In our design we found that our path selection strategy does not lead to a large number of selected paths.

in designs where delays of the majority of paths are within 5% of the clock period, more sophisticated path selection strategies can keep the number of selected paths low while maintaining high test coverage [18].


The delay of a re-synthesized circuit may be larger because of the extra delay of a voting machine.

because some critical paths may become false, the delay of a re-synthesized circuit may be smaller.


In a traditional adder, one is supposed to compute the product MiMi-1 ···M0 in order to compute the carry bit ci.

in our adder we assume that no carry propagates more than k-bit position for some k. Hence, in our adder, one needs to compute only the product MiMi-1 ···Mi-k+1 to compute the carry bit ci.


2 and the sub-code c1n produces two digital outputs in each region.

there is a relationship between these possible outputs as (16) shows, N = 1 c1n = c1 .


Reusable Component IP Design Refinement-based design is an alternative to the reuse-centric design methodology.

the platform-based design methodology is still attractive to the design teams who have systems that have been pre-integrated and verified.


Due to the structure of these applications, which is represented in Figure 9, the main thread emits heartbeats.

we still attach all the worker threads to the group to make adaptation policies aware that they are actually relevant.


Therefore, we now select the SFFs which are causing timing problems, and replace them with other SFFs with better timing parameters.

this is not always possible, or not the best solution, due to a couple of problems.


SimpleScalar [4] is an interpretive simulator that can model a wide range of architecture/micro-architecture features.

the execution speed is low since the entire process including instruction fetching, decoding and execution has to be simulated at runtime.


Based on ML-OASG, they developed a 4-step algorithm to solve the ML-OARSMT problem.

mL-OASG could not be suitable for the OAPDST problem due to its edges, that is, ML-OASG not only allows horizontal and vertical edges in the same layer but also uses slant edges.


for complex designs, achieving a required veri.cation coverage goal even with both approaches can still be very challenging.


Fajardo et al [10] propose an system where cores and accelerators share a common L2 SRAM, called Buffer-Integrated-Cache (BIC).

accelerators are not tightly-coupled at L1, and their    Interconnect area scaling  350 300 250 200 150 100 50 0  # cores 4 8 16 32 Fig.


It is well known that the maximum-cut problem, even for a 2way partition, is NP-hard.

we observe that in many cases, after the global SDP optimization, the graph size of GM could be quite small, i.e., less than 7.


In contrast, since the rise transition delay is the charging time for output capacitance, the influence from the virtual ground length and power-switch size is not significant.

the situation becomes different in gates such as AND or OR gate consisting of a NAND (or NOR) gate and an inverter inside the cell.


In general a BCH code will work for c>1[16, 25].

with increasing c the compactor size will increase exponentially, and it will be necessary to limit c. Our optimization goal is to limit the number of scan chains covering an output cone by c for as many output cones as possible.


Among the examples, fmm presents a case in which SP-prediction outperforms all other predictors, achieving both higher accuracy and lower bandwidth.

dedup presents a counter case, where SP-prediction is weaker on the accuracy dimension.


Due to the efficient utilization of dynamic reconfigurability, the algorithm leads to a highly compact placement.

the placement with the minimum array area does not provide adequate fault tolerance.


The results were somewhat surprising to the investigators, since a triple processor platform is regarded as processor centric.

what the data is saying is that microarchitecture improvements produce 2nd order effects when placed in the context of systems platforms.


The value estimating the time since last turn shows a more similar pattern within the .ock and dissimilar to other .ocks (Figure 10).

the symmetry in the building layout and the partly synchronized .ocking behavior in the experiment creates additional similarity in the turning behavior between the .ocks.


Several works have been published presenting various algorithms for dual-Vt synthesis (see, for example [8]).

these algorithms, including those used in commercial multi-Vt synthesis tools do not take into account the temperature inversion e.ect; instead, they typically assume worst case conditions to be at the highest allowable operating temperature.


The translation cache is, in essence, an instruction cache.

there are two major differences between these systems and a software-based instruction cache.


The closest next available time slot for a new column access is at Cycle 11.

the cycle cannot be reserved for a new column access because that would require an activation to be issued at the current cycle to open the row.


cryptographic coprocessors) or of software implementations.

some works have addressed the issue of integrating protection mechanisms directly into the processor.


When we remove variables from the problem, we modify the number of subsets, x,and therefore the number of columns, or subsets, in matrix A is changed.

ifwe add clauses, the number ofrows, or number ofelements in S,in matrix A changes.


On average, roughly 50% of pages are accessed more than 100 times after they are predicted as inert.

for applications which showed a large percentage (> 40%) of accesses to encrypted pages (lbm, milc, sjeng, soplex, sphinx), a much larger percentage of pages (> 80% on average, and at least 64%) are accessed more than 100 times.