(e.g., Learning systems for .nger languages and for making handicrafts)  Many devices that directly stimulate a user s .ngers[6] are proposed.

users tend to avoid wearing devices placed on area A, which is shown in Figure 2; this is because area A is used to touch, hold, and pinch real objects.


If we track both goLeft and goRight (along with PWM-Counter), we retain both conditional nodes from the thread FSM.

if we track only goLeft, the second conditional node is removed.


Due to the .xed pin positions of nets, the three approaches have similar numbers of via violations.

the results show that by considering stitching lines, both the ILP-based approach and the graph-based approach slightly improve the routability.


the system designer has no in.uence over the physical design steps.

often because of this compartmentalization the manufactured chips fail to meet design requirements.


These projects quickly grow in scope and consume valuable staff resources.

with good communication and hard work, we have managed to effectively meet the needs of both worlds.


They typically adopt high-level languages such as C++ for quick development of functional models at the transaction level.

since transactions are not synthesizable into hardware in general, circuits are still predominantly implemented in hardware description languages (HDLs) at the register transfer level.


Before measuring the performance of each ML-AHB bus system, the workloads should be determined, since workloads affect simulation results.

it is difficult to find appropriate workloads of real applications since real workloads can be obtained when all applications with real input data are modeled exactly.


As shown in Table 2, execution time for SW functions is insensitive to the number of inference iterations, and is about 57.9msec.

with more inference iterations in the hardware, we can achieve a lower minimum energy.


Once again, we can see that our tool outperforms the circuit output by direct synthesis.

the circuit generated by the Three Greedy Approach (TGA) [10] is slightly faster than our circuit.


The optimal decision rule has the best performance; however, it requires the channel information.

since the suboptimal decision rule does not require the channel information, it has some performance degradation compared with the optimal decision rule.


3.4 Sampling Loads We track long-latency loads through the Itanium-2 PMU interrupt mechanism.

a high rate of interrupts results in considerable overhead in execution time.


Since the goal of this work is to use this veri.er as a hazard checker during technology mapping and the technology mapper that has been developed satis.es this restriction, this seems acceptable.

in the future, we are interested in generalizing this work to the case where there is internal feedback.


INTRODUCTION In the past few years, the development of telecommunication systems has been quite remarkable.

the fast evolution experienced in the backbone networks was not observed in access networks, which remain as the bottleneck between costumers and backbone networks.


A short con.guration has two edges, left and right, for conducting.

only one direction will be used in the actual operation.


[12] also use a branch counting mechanism for run-time hot basic block detection.

our scheme Figure 4: Block diagram of HotSpot cache To achieve energy saving, the mechanism should not incur signi.cant hardware overhead.


IfseveralLUTsareclusteredintoonelogicblock,signalsharing amongLUTscanbeexploited.Sincetheinterconnectinsidethe logicblocksarehardwiredlocalinterconnectcanbemadevery fastandefciently.Thisimprovesroutabilityanddecreasesthe loadontheroutersignifcantly.Ontheotherhand,itisnotfeasi  Some text in this electronic article is rendered in Type 3 or bitmapped fonts, and may display poorly on screen in Adobe Acrobat v. 4.0 and later.

printouts of this file are unaffected by this problem.


In [28], researchers have attempted to replace the CMOS SRAM con.guration bits with STTRAM magnetic tunneling junction (MTJ) devices.

the dynamic sensing scheme for reading the LUT content as presented in [28] is inappropriate for a spatial computing framework such as FPGA.


Path speci.cation The path from a source to destination is often via one or more speci.ed intermediate (x, y, z) coordinates.

rarely is the full path speci.ed, most services just use a small set of intermediate coordinates through which packets must traverse.


In such stateless systems, fair scheduling is purely a fair bandwidth allocation problem since bandwidth directly correlates with performance (because what was scheduled previously does not affect the latency of what is scheduled next).

the existence of row-buffer state and multiple banks in the DRAM system eliminates the direct relationship between bandwidth and performance.


Yang and Gupta [31] proposed a very simple profiling method with low power embedded systems in mind.

this profiling method was intended for data profiling, not code profiling.


Extraction means that some bits (one or more) are extracted from a word signal to form a new word (more than one bit) or Boolean (one bit) signal.

joining some word or Boolean variables together to form a new word variable is called concatenation.


This branch can be removed by recognizing exception conditions as the end of a pre-execution.

because the associated pointer value usually occurs in one of the other sub-slices, this optimization does not signi.cantly reduce total slice size.


In order to improve the loopback observability, the authors proposed to .rst characterize the TX using a subsampling architecture based on Periodically Nonuniform Sampling of second order (PNS2).

as presented, the approach required external (off-unit, off-radio, off-board or off-chip, according to the level of integration) computing capability (still, at reduced cost w.r.t.


Inthe 90nm library that we used, this would mean that SSTA wouldhave to keep track of thousands of random variables for CD variation alone, which is unacceptable.

in our work we hypothesized that since there are two main underlying components of CD variation, exposure and defocus, CD could be modeled as a function of ~2 components.


Although microelectromechanical systems (MEMS) is a relatively young .eld compared to integrated circuits, reliability studies for MEMS have received considerable attention [McCluskey 2002].

due to signi.cant 687 differences in the actuation principles underlying digital micro.uidics and MEMS, these reliability enhancement techniques cannot be directly used for the design of micro.uidics-based biochips.


last ten are from [17]; five are from industry, five are random.

[17] does not have current information; we randomly inject a positive or negative current to each terminal, the current value is normally distributed within the range [-k, +k].


Timing driven placement techniques have often used the ability to specify constraints into the placement algorithm such as net weights and capacitance targets to achieve such goals [9, 20, 14].

they do not directly take into account feedback from for example a timing analyzer.


Conventionally, if we ignore the thermal stress, the impact of temperature on gate and path delay is a monotonically increasing function higher temperature leads to increased delay.

due to the existence of TSV induced thermal stress in 3D-ICs, the impact of temperature on gate and path delay becomes more complex.


This sort of problem is rarely reported in the literature.

power management techniques to reduce and to optimize consumption in embedded systems are numerous [3-4] but many of these articles describe configuration with battery [5-7].


Decompression and compression latencies as well as hardware complexity for the ZCA cache design are low.

only applications that operate on a large number of zero cache lines can bene.t from this design.


4 uses a cross-coupled NAND gate latch structure to perform the signal comparison.

we modify the latches to be more sensitive to the assertion of the lower input to create a locked state where neither an up nor a down is asserted.


5.2.3 Physical Modeling: Today performance and power models do take into consideration some of the physical constraints, such as the number of cycles along critical paths and the projected leakage for a specific technology.

the linkage between these models and physical layout is usually manually maintained.


Vertical and horizontal filtering can take place simultaneously if there is no datadependent.

bilinear filtering always lags one cycle behind since it needs output results from vertical and/or horizontal filters.


Information redundancy techniques can efficiently detect faults on data that is stored or transmitted, such as in memory or on busses or networks.

information redundancy techniques for covering control logic and computation units, such as self-checking circuits [12], may be more difficult to design.


All arcs originating from and ending in a combination of these events can form legal protocols as long as they respect the minimal set of constraints for the chosen logic style.

some of these arcs have more natural translations to circuit implementations than others.


To the best of authors knowledge, the only solution discussed in the public domain is [9].

based on the description from [9], their algorithm restores data only in the combinational logic nodes of the circuit.


In general, this is not the case but it does apply for the majority of cells today; most row-based library cells are intentionally designed this way.

block and hier-archical designs often requires a set of port connections to fulfill a single logical pin connection (known as must connects ).


Each Virtex-II slice has 8 inputs and 2 outputs, so if we were to build a VEB block of 37 slices, it would support a maximum of 295 inputs and 74 outputs.

our embedded FPU requires 446 inputs and 288 outputs.


Any process or resource created by a process is labeled with the same label as the creating process.

their approach is access-control based and it cannot defeat more intelligent malware as we mentioned in Section 5.


In addition, power consumption, traffic and port contention of the baseline caches may decrease.

the loads that miss in the auxiliary caches may experience longer latencies.


Figure 5 brings out this fact more clearly by showing that the dynamic power of repeater reduces signi.cantly whereas leakage power of repeater increases for smaller technology nodes.

the leakage power is a small fraction of overall power of repeater in Figure 5 or interconnect in Figure 4 because we consider a workload with high activity factor in these con.gurations.


This suggests that synthesis will not have to be changed much since this is approximately the maximum size for which logic synthesis is effective.

our analyses on production designs show that the problem is not quite so straightforward, and the efficacy of synthesis using wireload models depends upon technology data as well as specific characteristics of the design.


Those applications, most of whose working set .ts in the RLDRAM memory, bene.t from this organization showing higher bene.ts compared to our scheme.

the loss in performance is due to many accesses to the LPDRAM - since the top 7.6% of pages only account for a maximum of 30% of all accesses for any of the programs.


In summary, RSE detects the older data bit alongside the write operation without an extra read operation in front of the write step.

the new cell structure of RSE has additional bit lines, necessitating a 10% area overhead compared to the original nvSRAM in layout.


Hence the temperature of the local wires is very close to that of the substrate.

the change in the resistivity of the semi-global and global tiers can be up to 20%, because of the temperature rise at the higher levels.


We also conducted experiments with the MiBench benchmarks [19].

because they are small, there is no noticeable performance di.erence among 128KB, 256KB, and 512KB L2 cache sizes.


Therefore, for ultra low-voltage design, Vth needs to be simultaneously reduced in order too compensate the loss of speed.

a lower Vth at the standby mode causes an exponential increase of Ioff and in turn, a higher leakage power.


Even though the previous works can consider the clock skew constraint on every power mode, it would be highly likely that the resulting clock tree uses a substantially long wirelength or there is no clock tree that satis.es the clock skew constraint on every power mode.

post-silicon tuning (e.g., [4, 5, 12, 9]) such as inserting Adjustable Delay Buffers (ADBs) is a widely used method to deal with the timing problem caused by process and environment variations.


Since then, there has been some works analyzing the characteristics of the NoC considering the many mechanisms, protocols and design options available for implementing NoC architectures and proposing techniques to improve its quality [1], [15], [3] and [6].

there have been some proposals of tools to choose the best platform configuration and to map applications to the target NoC architecture.


Needless to say, good performance on arti.cial benchmarks does not guarantee good performance on industrial circuits.

we show that the arti.cial benchmarks presented in this work can be thought of as benchmarks constructed, by abstracting away some of the details of actual circuit elements found in many circuits today.


These algorithms o.ered new directions to robust circuit design.

when applied in practice, these approaches may still su.er from the following drawbacks.


For simplicity, we conservatively assume that this cannot be guaranteed.

our algorithm can easily be extended to support this additional compile-time analysis, which would increase the degrees of freedom available for reordering.


Also for data caches, the invalidating of the cache after every interval incurs more misses which account for more energy.

we observe only 0.3 additional misses/perKiloInstructions due to reinitialization at 1M intervals (analysis not shown due to space constraints), which agrees with the .ndings of [9].


Another scheme uses an em- bedded memory [16].

[8] often generates a local minimum solution and the implementation of hardware is difficult.


Thus, on every clock cycle, all unused entries are ready to be re.lled with new instructions.

a wrap-around buffer cannot re.ll an unused entry until all older instructions have .nished.


The paper shows how Dynamic Time Warping and Viola-Jones algorithms are converted from C speci.cation to a HDL speci.cation, targeting the Convey system.

the approach still requires performing optimizations on the code to fully support the platform.


The DFT solution proposed in [3] enables testing on/off functionality of power switches in both .ne-grain and coarsegrain designs.

dFT solution in [5] addressed the problem of long discharge time, showing effective discharge Fig.


These results indicate that using inverted C-elements can mitigate transient faults effects for 0 to 1 glitches.

for 1 to 0 glitches this is not the case.


Traditional DC-DC converter has been proposed to step up the voltage in recent works [8].

inductors in the converter are costly if being integrated on chip.


When the output Sel is 0, the upper 8 bytes are selected.

when the output Sel is 1, the lower 8 bytes are selected.


The method enables resource sharing among multiple functions by merging them into one function.

the method assumes that there exists only a single sub module in addition to a main module.


This case is also the most bandwidth efficient (85.4% of overall assigned relative BW).

it results in the worst priority channels performances, since the outcome is the lowest average assigned relative priority BW (51.1%) and the highest standard deviation of assigned priority BW (2362).


Our experimental results have proven that our approach can explore a larger bit-width-to-error tradeoff.

we also note the limitations of our methodology.


Seminal work by Sigl, Doll and Johannes in the early 1990s developed a linearization technique that represents the linear wirelength objective on graphs by a dynamically-weighted quadratic objective [25].

the modeling of multi-pin nets remained inaccurate, and the research community has largely replaced quadratic optimization by much more cumbersome and slow non-convex optimization techniques ten years later [7,10,16].


Hence, the number of branch nodes is equal to the count of required dilution operations and the number of buffer droplets.

the number of waste droplets is equal to the count of single-child branch nodes.


Underestimation that might occur due to neglecting the impact of variability or, in some cases, due to inaccurate modeling of reconvergence may result in inadequate protection or hardening choices.

grossly overestimating error rates that can occur due to ignoring electrical and timing masking effects results in overly conservative protection and hardening techniques, and consequently, in overdesigning with higher performance penalty, power or area cost.


In these papers, the idea of using sub-threshold circuits was introduced from a device standpoint, and candidate compensation circuits were proposed.

no systematic design methodology was provided, which addresses the issue of delay compensation across process, temperature and supply variations.


In order to glean contiguous runs of physical pages, the buddy allocator relies on ensuring that memory fragmentation is tightly controlled.

fragmentation is pronounced when multiple processes with large working sets simultaneously run on the system.


Via doubling has long been proposed as a low-cost back-end-of-line (BEOL) yield improvement technique.

the number of vias enhanced by this practice is limited by the space available in the layout.


DDR and LPDDR) have emerged to cope with the increasing demanding memory bandwidth.

these standards have limitations when the bandwidth must be further increased, mainly due to high frequency in a noisy environment.


Under real-world conditions, channel noise increases signal transitions at the zero mark and thereby reduces prediction accuracy.

our experiments on signals acquired under real channel fading show that setting a non-zero threshold value improves the symbol prediction accuracy.


(6) As the number of magnets in an NML circuit increases, the number of coupling pairs increases quadratically (O(n 2)).

because the dipole-dipole interactions between NML devices decay as the inter-device spacing increases, it is not necessary to calculate the coupling energy between all pairs of NML devices.


Consider variable e2 in the subtree under e1 = 1, switching from e2 = 1 to e2 = 0 without .nding a satisfying assignment does not imply that (¬e2) has been learned.

it is possible to learn about non-root variables in some circumstances, as shown by Lemma 2.


However, the scalability extremely degrades as the latency increases.

the SCIMA-SMP model has better scalability than the CACHEonly at a latency of 80 cycles.


The traditional hierarchical paradigm sufficed in the pre-nanometer era when routing abstracted to the granularity of GRCs yielded good estimates of congestion and net-length based delay.

the increasing impact of crosstalk on performance [2][3] has made net adjacencies important (for crosstalk to be predicted) at the global routing level.


The shared memory resides in each streaming multi-processor (SM) and is much faster than the global memory.

the size of shared memory is limited (e.g.


4.1 Logic Synthesis and Technology Mapping There have been many recent attempts to integrate logic synthesis and technology mapping with placement (that approximate global routes by bounding boxes or trees) (e.g., [10,11]).

although this physical synthesis tries to comprehend the capacitive load of wires, the metrics that drive it are still the traditional literal or gate counts and fanout-based wire load metrics, sometimes augmented with estimated wirelengths.


In both cases, all hardware interrupt processing is done in the host by reusing Linux s existing interrupt handling functionality.

vMs must receive notifications in the form of virtual interrupts from emulated devices and multicore guest OSes must be able to send virtual IPIs from one virtual core to another.


3.3.3 Stealthiness Analysis and Optimization Until now, we have presented our defeating approach against VeriTrust.

as discussed in Section 2, whether an HT is able to evade VeriTrust is directly related to the functional veri.cation test cases applied to the circuit.


Generally the separation of parallel and sequential operations and the pipeline control structures were considered useful.

the participants would like to have been able to use this more as a visualisation than for editing directly.


For the level two cache, we use a 64 KB cache with four configurable ways and configurable line sizes of 16, 32, and 64 bytes.

our heuristic is not dependent on these values, nor on embedded applications  for desktop applications, larger total-size values would be appropriate.


Table I reports the size of binaries and con.guration bitstreams, obtained with our approach (multi-objective) and with We can observe that the overhead in terms of binary size is lower than 4%.

the bit-stream overhead is considerable higher in our case (25% for INCAR and 50% for WFS) since there is the need to store all the CCU implementations required by the selected operating points.


The selected schemes provide increasing levels of fault tolerance support, and this is re.ected into the tradeoffs they span between area, power and error control capability.

we do not consider error events for on-chip communication to be so frequent to violate performance speci.cations of applications.


Due to technical issues (problems with Asterisk PBX set-up on the site identification) related to logging information for this line, we are unable to report the breakdown per site for the community line.

based on our observations we are confident that the usage follows a similar pattern to that of the Lwazi CDW service.


With higher throughput, resource sharing opportunitiesare less than the original design, which is the main reason for the area overhead.

latency of the loop body is reducedin most cases with more memory bandwidth; therefore we can even .nd areareduction on one test case(PALIN) aftermemory partitioning.


There also are good reasons for such one-BIST-per-RAM approach, e.g., intellectual property (IP) protection, test wrapping for IP [9, 10], performance requirement, etc.

sometimes it is not feasible to have one BIST circuit for each memory core.


His algorithm runs in constant time and has no space over- head.

it can only implement small (16 to 24 bit) LL/SC objects, which are inadequate for storing arbitrary pointers, large integers and doubles.


Without sampling, the platform s e.ective simulation speed is 38MHz for the random tra.c and 359MHz for the PARSEC benchmarks on average.

with sampling, the platform s e.ective speed can be increased to an average of 130MHz and 660MHz respectively.


These algorithms also have high accuracy in detecting audio information hiding.

there are new algorithms proposed based on feature extraction and classification to detect the LSB substitution [7] [8].


Two exceptions are 179.art (6.3%) and 183.equake (2.6%).

the fraction of the prefetch requests that hit in the primary cache can be much higher.


WR Therefore, if a properly set alternative non-zero mean distribution is used to generate mismatch samples, there is a higher chance of capturing more failure samples.

it is critical to remember that not each overly-drifted distribution, which creates many failure samples, is necessarily a good candidate.


And it is not easy to set good criteria for tie break.

exhaustive search guarantees an Accessgmph Depend~a DAG (a) ~p4mdlmce DAG Access gmplt (b) DependenCe DAG Access graph (c) Flpre4.


[6] use a .oorplanner to determine feasibility of the synthesized design by comparing estimates of wire length with an upper bound on wire length.

none of these e.orts address the leakage power of the SoC.


He wanted to avoid jump cuts and the best way of doing this was being able to know which types of shots were available - Going from a wider shot to a closer one looks pretty as oppose to jumping between medium shots.

he acknowledged that a lot of modern editing actively employs jump cuts as stylistic device, so, from the automatic authoring perspective, a reliable awareness of the shot type would allow it to have rules that could enforce a conventional styles of editing or move towards a modern style of editing, depending on the preferences of the end-users.


Start ( T = {}) red provide the tester with th e model derived from the training data.

this may require a significant amount of additional tester resources.


For SSDs A and C, the random write throughput approaches the throughput of the sequential write workload when the request size is more than or equal to 16MB.

sSD B has a serious performance problem for random write operations even when the request size is large.


As discussed earlier, nets are routed one by one in DR, and the nets routed earlier possibly block the terminals of the nets routed later.

our escape routing algorithm simultaneously allocates routing resources for all terminals in a cluster, preventing other nets to block these terminals during DR.


To quantify this intuition, the bars labeled L are for spawn-target pairs selected with a reaching probability threshold of only 75%.

this lowered threshold does not seem to help signi.cantly.


Viewing consistent features as coherent components imply the mechanisms generating these common structures follow deterministic rules otherwise they would not be consistent/coherent.

the residual components often contain a degree of randomness or stochasticity.


This implies that NCTU-GR 2.0 may already work well on MPL_sb4.

as NCTU-GR 2.0 routes simPLR_sb15, we can see that its total overflow in Table 2 is much larger than its LBTO in Table 4.


There has been important recent research work going in this direction [2, 5].

in all this previous work, the physics that describes the phenomenon, has not been taken into account.


smaller Reff and reducing the time it stays in subthreshold region before the state is switched.

a smaller N also leads to larger leakage when the input is at state 1.


We also demonstrate that it can be a promising candidate for both sub-threshold and super-threshold operation with performances comparable to contemporary bulk Silicon.

due to grain boundaries (GBs), there can be large intrinsic variations in such devices.


Notice that these constraints imply the simpler constraints from De.nition 6.

we have further constrained each a i to a small set of concrete values: we now know that a i < i for every 1 < i < n. This will allow us to create more ef.cient translations for set and get formulas.


Also, without considering the electrical .eld distribution, the noise is over-estimated because aggressors are seeing the whole TSV MOS capacitance.

each aggressor mainly affects the victim charges only on the side that is facing it.


Navid Aziz and Farid Najim explored two operating modes of high performance and low power FPGA block and reported reduction in leakage power by 53% [4].

in recent years increasing demand of battery operated handy devices and emerging IC applications such as distributed sensor networks, RFIDs, medical devices, etc., are trusted for inflexible power budgets.


Since message passing is neighbor pixel local and highly parallelizable, BP is widely used in custom hardware and GPU implementations [14,15,16,17,18].

simple loopy BP on stereo matching problems does not produce the best disparity labeling results in practice ([10]) and can occasionally diverge.


Even with a quite large outline of 20% area relaxation, there are still chances when the result fails to f it in, although the exceeding part is very small(usually around 1% of the outline width).

all the results of n100, n200 and n300 succeed in f itting into the outline with the 20% area relaxation.


This implies that a two-party key exchange protocol that satis.es SK-security preserves its security under arbitrary protocol composition.

katz and Shin [24] de.ne an ideal functionality for the task of GKE in the UC framework and show that this notion of UC-security is strictly stronger than the game-based notions for GKE.


correlation among these low level parameters can be included if necessary, by including the appropriate covariance term in (1) [5].


In [6], [7], [10] the dependence on global variations is explicitly represented using a canonical timing model.

none of these approaches has taken into account the path correlations.


2 Variability Impact on Subthreshold Circuits It is well known that process variability impact is magni.ed in subthreshold operation due to the exponential impact of Vth and Leff on subthreshold drive current.

little analysis has been performed to investigate the dominant components of variability in subthreshold circuits and other key trends.


Previously proposed cache compression schemes make it possible to improve performance with small L2 caches [21, 7, 26].

they increase L2 cache energy consumption because of added extra bits, complex compression/decompression, and more cache accesses, as will be shown in Section 4.


A digital on-chip measurement system is presented that helps to characterize synchronizers in future improve with technology scaling [4].

recent measurements [5][6] indicate that scaling trends of synchronizers should be re-considered: The need to obtain full characterization may be imperative in technologies beyond 45nm.


Another input signal to PFE is bias voltage Vbsf given to SF.

a waveform acquisition kernel includes a reference level generator (VG) supplying Vref from a 10-bit R-2R ladder, a sampling timing generator (TG) providing Tck from a 10bit variable step delay generator, and a data processing unit (DPU) producing a series 10-bit digital word from Dout.


This can be seen in the delay distribution within the .gure, as the .oating point execution unit is limiting further optimization.

the .nal frequency of the 17FO4 machine is limited by the SRAM structures such as the register .le and caches.


The roots of such nonlinear equation correspond to the time when overshoot/undershoot occurs.

solving the nonlinear equation is not an ef.cient way.


TABLE I Ideally each voltage upscaling converts one ECP from protecting SIMULATED CONFIGURATION dormant cell to rescuing a new hard error.

depending on the current precision, more than one dormant cells may be activated.


4.1 System Partition After the DIA system is converted to the abstracted system, this method picks up variables from X that are involved in linear transitions to form a subset XL and variables that are involved in nonlinear transitions to form a subset XNL.

if variables in XL and XNL are independent with each other, then XL n XNL there often exist variables in = f. XL correlated to variables in XNL.


As also stated in the literature, we expect that in a planetary environment there exist areas that receive steadier sunlight; thus, solar power generation on a stationary site would be more efficient than on the peripatetic robots, which would potentially work in a shadowed and dusty environment.

our methodology also works in the case where a site co-locates with another or in the case where all of them co-locate in one place.


One solution to this would be to .nd at ci the worst-case slacks for paths originating at a number of startpoints, and then to estimate the slacks at cj for paths originating from each of these.

such a solution is not necessary mainly because the estimates of worst-case slack from s. will be close enough to the actual worst-case slacks and will still provide good endpoint coverage as our results will show.


When the NotifyTime is 10 s, T2 expires, which results in higher idle time.

the energy cost is still 64% more than the baseline.


Intra-die variation tends to average out over the length of a circuit path and hence can reduce the circuit delay distribution.

the presence of significant intra-die delay variation in two converging paths increases their maximum delay distribution.


FixedC decreases the average number of accessed bytes by 36% compared to Baseline due to accessing shorter compressed blocks.

vSC-2X increases the number of accessed bytes at LLC by nearly a factor of three since it needs to repack sets (copying almost half a set, on average).


ACM 978-1-60558-371-6 gion exhibit consistent low loss and are symmetric [1].

the transitional or gray region is characterized by the presence of unreliable and asymmetric links.


Since pointer p doesn t point to any array element, its index p.index is not used.

pointer q points to a single location set which represents the elements of array table.


Traditionally, a PMOS keeper transistor has been employed to compensate for leakage current of pull down (NMOS) network.

to maintain acceptable noise margin level in sub-100 nm technologies, large PMOS is necessary, which results in substantial contention (during pull down) and severe loss of performance.


If no complete information is available about the types of the activating events, it is no longer possible to apply Mok s and Chen s approach.


ROs that have high-sensitivity to a single device-parameter have been proposed for decomposing the measured superposed variation into each device-parameter variation [10], [12].

when using such ROs, random variations might not be canceled out.


Cache subbanking is a well known approach to reducing the data-read energy, in which the data SRAM array is partitioned into several subbanks and only one subbank including the target instruction is activated [6].

since the whole tag is required for the tag check, this kind of partitioning approach can not be applied to the tag SRAM array.


The main reason for such an increase is that, for lower voltages, even very low energy particles are likely to create a critical charge that leads to a transient fault.

this aspect has received very limited attention.


The result shows that FEMU provides better write performance, about 16% speedup ratio, than QEMU.

for read performance, FEMU is not so good as QEMU, about 1.9% slower than QEMU.


This results in increased performance of up to nX, where n is the number of orientations.

scratchpad memories are not suitable for large volumes of data.


All the above potential solutions could function well under certain conditions.

we will deviate from them in this paper and pursue a di.erent, distributed approach.


Throughout this paper, Elmore delay model is employed due to its high .delity [14] and ease of computation.

hSPICE based Monte Carlo simulations are used for .nal result validation unlike [1].


A Parallel VLSI Architecture for Markov Chain Monte Carlo based MIMO Detection Uwe Deidersen, Dominik Auras, Gerd Ascheid Institute for Communication Technologies and Embedded Systems RWTH Aachen University, 52056 Aachen, Germany {deidersen,auras,ascheid}@ice.rwth-aachen.de ABSTRACT Multiple-input multiple-output (MIMO) wireless transmission together with iterative decoding at the receiver is a key technique to achieve high spectral e.ciency.

particularly the required soft-input soft-output (SISO) MIMO detector entails a very high complexity, which motivates the investigation of suboptimal detectors with reduced complexity.


Based on this fact, the shorter the sample period, the better the perceived quality of the call.

the shorter the sample period, the smaller the frames and the more significant the packet headers become.


Therefore, the efficiency of these techniques is dependent on the application program characteristics and the architecture, such as how frequent the locking attempts occur in the application (i.e., how many CSes exist in the program) or whether there are lots of processors making use of locks.

there are some queue based software solutions like array based queuing locks [7], MCS locks [9] and LH and M locks [10].


This could be achieved by simply guiding the selection of physical addresses for each virtual page (i.e., some bits of the physical address will also designate the directory owner).

such a technique would couple the memory allocation with the directory placement.


The knowledge of the RIR within a room can assist various audio and acoustics applications, such as signal enhancement, room modelling, auralization techniques etc.

in order to measure a RIR at a speci.c position within a room requires the reproduction of speci.c signals (i.e.


As a result, by setting all the un-activated entries as don t-cares, we can determine those redundant inputs as trigger inputs for HTs.

in practice, veri.cation tests are usually incomplete, which means un-activated entries may also belong to normal function.


Assuming that the probability that each bit of S has a 1 value is 0.5, the hamming distance in setting REGS can be regarded the same.

no toggle occurs with REGS in the operation 3).


Figure 7: The impedance characteristics: (a) the nominal impedance values, and (b) variation in the impedance observed by the core due to variation in the VR parameters (impedance response of the off-chip VRs are overlapped on top of each other due to negligible effect of variation TABLE V Comparison of the nominal value and variability of the output parameters and impact on the core performance for offchip VR and IVR under variation Mean Value VDROOP (mV) TS,LOAD (nS) OVREF (mV) TS,SET (nS) FCORE (MHz) Off-Chip VR 171.3 3056.2 231.2 4347.7 49.2 IVR 96.4 584.3 46.1 181.8 103.7 3s/µ (%) VDROOP TS,LOAD OVREF TS,SET FCORE Off-Chip VR 0.78 14.07 26.01 29.55 2.46 IVR 16.17 29.13 135.21 30.57 9.24 We observe that at the higher power corner the ESRL is the most dominant source of variation in the total power (2.07% variability).

it is important to note that variability in the total power is much smaller than the variation in the power loss.


Therefore, AC analysis can be regarded as a formal verification method for linear analog circuits as it can prove if the circuit has the correct linear behavior as intended.

transient analysis can only compute the circuit s response to one particular excitation at a time.


For example, if A is on the left of B, then in the ordinary slicing tree, the left child is A, the right child is B, and the parent node is labeled V .

if we want to switch to other layouts between A and B, then the previous slicing tree has to be changed as well.


4.1 Quantitative Performance Benchmarking 4.1.1 Effect of Host Operating Systems VMware VM s on Red Hat Linux 7.1 host machine performed better than on Windows host in terms of installation time, which would save as much as 40 to 50% of time (Table 5 and Figure 3).

there was no significant difference on CPU performance between Linux and Windows hosts using VMware, although Linux performed slightly better than Windows (Figure 4).


In Appendix A, we will also present the details of our final algorithm, including the exact definitions of these likelihood functions.

we postpone the discussion until the end of Section 3.2.


This temperature inversion e.ect has been known for some time.

only recently have there been works addressing this issue, particularly for digital circuit design.


Unsurprisingly (as shown in Figure 3), using the median by itself produced the most false positives on average.


It reduces the total number of iterations of iterative decoding and results in good FER performance.

as the code rate is over 0.8, the ensemble from the design method I shows poor FER performance over the ensemble from the design 1.0 method II.


In order to minimize performance overheads, ECC can be applied to reduce the number of rewrites.

neither thermal-induced probabilistic switching nor the asymmetric switching property of MTJ were discussed.


One can perform the optimization after detail routing to .x postrouting timing jump [39].

it could be prohibitive due to complicated incremental detail routing, or adding too much power and area to the design without controling router itself, and many times abort without space to insert additional buffers or size the gates.


Since EWT is carried within a write operation, there is no performance overhead to the write latency.

some write requests can even .nish earlier if all the bits are the same as what are already stored in the cache.


While the above literatures do not assume de-allocation of computation/ communication resources, the technique proposed in [17] considered dynamic task remapping on detection of node/link failure in distributed embedded system.

the architectural details and associated run-time overhead are not addressed in their work.


C. Check Window Based Instruction Sampling If every instruction in the program is checked using the proposed techniques, permanent faults can be immediately detected.

since each URISC check routines takes multiple cycles, this would incur a signi.cant performance overhead.


[4], noting that the off-diagonal entries of L-1 diminish much faster than those in L, proposed the sparsi.cation of L-1 by retaining only signi.cant terms; the resulting L -1 can reduce the number of coupling terms and speed up simulation.

l-1 needs to be computed .rst, which is prohibitively expensive.


For a smaller d2, flip-flop bonding starts at later iterations but does not guide flip-flops well because the low flexibility of moving flip-flops.

for a larger d2, flipflop bonding starts from earlier iterations but results in longer wirelength because distant flip-flops are attracted.


Studies also need to be conducted to see if similar patterns are observed at other stations.

increasing the broadcast frequency in P2 increased the absolute number of total and good calls per day.


Because of the error arising from the analytical model, the higher the number of iterations, the more the error that is accumulated.

most of the cases, kSBF is more accurate that eSBF.


In [14], a greedy heuristic on integrated gate sizing and buffer insertion is proposed.


Thus, Co-Located LLT has lower latency for data lines in the stacked DRAM.

it has higher latency for off-chip accesses.


A major problem of the high-level WCET analysis is that the maximal number of computation steps of a statement (like a loop) may heavily depend on the input data, but some of the approaches do simply compute the WCET bounds for the substatements and add these afterwards.

simply adding the maximal bounds for all substatements clearly yields highly pessimistic bounds.


It can be noticed that both the locals and the global controllers are present.

in the case of a system in which the control takes place only at the local level, the global controller can be disregarded from the picture.


This forms the foundation for standard Monte Carlo analysis [6].

standard Monte Carlo forces us to take many samples around the likely case especially in the presence of tailed distributions.


The leakage power of a transistor exponentially increases (decreases) with its decreasing (increasing) threshold voltage.

for small changes in threshold voltage of a transistor, the gate-level leakage power varies almost linearly.


Unlike the SPLASH benchmarks, the reductions from 2-way set-associativity are quite small, around 10 20%.

the 2-way set-associative cache has signi.cantly higher miss ratio to begin with (See Table 2, Appendix A).


Test costs in the design space exploration of the TTA architectures The concept of the test cost as a merit of the testability of the system has also been addressed in some recent papers in the area of the high-level test synthesis [8-13].

none of them was acceptable in the TTA environment.


As the computation time is related to the number of iterations, lesser number of iterations will imply lesser computation time.

the probability of some constraint being violated is also large when several variables are rounded simultaneously.


This variant was solved with a layout-compaction based approach.

the approach can bend only the wires on parts of routing layers at a time and is very time-consuming.


3.8 Cross Platform Verification All previously described experiments were run on an AMD Athlon Opteron 244.

the construction strategies used to maximize performance for this machine work well for other machines.


On the one hand it has to receive and deliver .its at very high rates in order to sustain network throughputs of tens to hundreds gigabits per second, requiring clo ck rates of hundreds of MHz.

the switch logic complexity, as hinted at in the previous section, might be quite relevant, then possibly limiting the switch clock frequency.


ARM supports virtualization through a separate CPU mode, Hyp mode, which is a separate and strictly more privileged CPU mode than previous user and kernel modes.

intel has root and non-root mode [20], which are orthogonal to the CPU protection modes.


In Example 2, we assumed that each custom instruction has an area allocation, independent of the area allocated to other custom instructions.

sometimes it is possible for two custom instructions to share area because of a similar structure, or a similar number of inputs and outputs, which further complicates the problem.


In theory ServerNet II should perform at 1.25 Gbit/sec per link per direction, i.e., 5 Gbits/sec, which translates to over 400 MBytes/sec (after protocol overhead).

our test system s PCI 64/33 bus limits performance to only 250 MBytes/sec.


LUT-P has the largest area among the FinFET based LUTs (due to the internal metal contacts).

lUT-P is still smaller than the bulk based LUT by 35%.


In fully-accurate NNs, the output error originates from untrained or partially trained network parameters.

in the case of AxNNs, we intentionally supplement this error with a secondary source, viz.


In 2006, the first MRAM based on Field Induced Magnetic Switching (FIMS) was commercialized [10] and it addresses particularly some specific niche markets such as space, security and aeronautics thanks to its radiation hardness.

the first MRAM is greatly limited by its FIMS approach, which requires two high currents (~10mA) [5] and this leads to low memory density and high switching power.


A simple comparison between these two values would cause, in most cases, the choice for I4MB partitions, because of the finer prediction granularity and more coding modes.

analyzing the behavior of the difference between these two distortion values when RDO-based decision is applied, it is possible to make a good choice on which partition shall be used for each MB.


In both schemes, helper threads do not directly run the program: Instead, they are designated to perform some specific algorithms such as stride prefetching and self-history branch pre- diction.

since our pre-execution mechanism actually runs the program itself, it is more capable of handling irregular data accesses.


The effect of variations was typically handled by analyzing the circuits at different corners or points of operation of the process.

as pointed out by the authors of [1], [2] this corner-based analysis can be very conservative.


The 2T-1R dual source-line technique was shown to be very e.ective in mitigating the stress condition for the tunneling barrier of the MTJ while the reduction in write power was not signi.cant for RC bit-cells, if it is designed to incur no bit-cell area overhead.

31% of write power reduction was achieved for SC bit-cells.


In [11] distributed RC modeling has been used to obtain quantitative measures of crosstalk-induced pulse peak and width.

the authors have not considered the case slowdown of the victim s transition, where the aggressor is changing in the opposite direction of the victim.


The precision required varies for different applications: those involving measurement of time of .ight or time difference of arrivals often require precisions on the order of microseconds [33], while for long-term recording of event times and for many system mechanisms, millisecond or second resolution is suf.cient.

despite these variations, some form of time synchronization is one of the most common and critical requirements in embedded sensing.


This cleanup can occur lazily since those entries are marked aborted and their XSW pointer cleaned up.

to allow the aborting transaction to restart right away and execute, the XSW should be re-usable.


Therefore, a bottom-up deve lopment approach is rather natural.

now these devices are appearing within much larger systems and the typical development strategy is to partition sections of the microsystem into the mechanical, analog, or digital domains.


In recent years, various watermarking techniques for IPP have made a numerous progress.

previous watermarking methods for IPP require imposing much more than usual design restrictions, therefore the system becomes difficult to guarantee or optimize its performance of original IP design.


[ 22, ]ed In the case of A1, it appears with A3 (k=1).

if A1 » A3 as it is usual, the contribution of A3 in k=1 can be neglected (this is even more true if the summation is extended to a small number of periods).


lRU-Greedy and LRU-Smooth exhibit high degradations for bzip2 and vortex, even under our performance guarantee (not shown).


A sensitive configuration bit may affect the circuit operation if it is flipped by an SEU.

some sensitive bits may be not critical for the application because their soft errors are masked and not propagated to the outputs.


Hard cores and encrypted cores, for which no implementation netlist is available to the SOC integrator, need to be tested by the test patterns as delivered by their core provider, and hence also require stand-alone testing.

even for logic-only SOCs for which the entire netlist is available, modular testing has attractive bene.ts.


One way to deal with this imbalance problem is by under-sizing the majority class or over-sizing the minority class.

the disadvantage is that over-sizing will lead to loss of information while undersizing may lead to over.tting [11].


The logic implements the same four steps as described previously.

the store merge, ECC check bit generation, and new ECC-word store operations may be aborted if it is determined that the store is silent and there is no ECC error.


On a testfor membership, the test returns true onlyif all ofthe checkedbits are set to one.

theprobabilityofgetting apositive matchis: PP (n) = (1 - p0 (n))k we are interested in the probability of false positives, i.e.


The errors found in this paper require dynamic information and can catch very convoluted race conditions.

the static checkers are shal- lower, but more light-weight and do not need to simulate any protocol code.


Scaling of DRAM to smaller technology nodes enabled higher capacity in the same die area for the past few decades.

as DRAM cells scale down in size, they become signi.cantly less reliable.


block can rarely be halted as the threshold value becomes lower.

the higher the threshold, the worse the DMF functional efficiency becomes, because the second .


The FPGA implementation is the one that can o.er thebestperformance andlowestpower consumption, outperforming the others by approximately two orders of magnitude.

its main drawback is that it requires an increased e.ort to design the complete hardware accelerator.


Because an interconnection has two adjacent wires, one is on left and the other is on right, the factors become 4 and 0 times of the coupling capacitances.

when we look into detailed signal schemes, the variation is only (Dmax -Dmin)/2.


One possible approach uses shifted clocks to provide more reading and writing time [17].

adapting this method to multi-ported memories is not trivial due to internal timing paths across the I-LVT.


4.5 Design Decisions The objective is to make the SnoopP circuit as small and as fast as possible so that it doesn t impact the embedded system design.

to be a useful software pro.ler, it must allow the user .exibility in specifying address ranges and the number of counters for the system.


The latter seemed at .rst exciting as it could be the starting point for long-lasting partnerships with state-of-the-art operating system research for parallel hardware, such as Barrel.sh [18], Helios [17] or fos [23, 24].

there is an immense practical obstacle to this latter strategy: not only must we port the new operating system to our platform; the corresponding application-level implementation work, required to make the C library and application programs compatible with the new system, must be compounded with the portability requirement that the code should also run on commodity hardware.


To this end, we point out that e.cient implementations of negotiation-based routing and A*-search require a priority queue, which academic researchers and graduate students may not be willing or able to implement e.ciently.

a highly optimized, reusable, heap-based implementation is now available with all C++ compilers as a part of the Standard Template Library (STL).


On one hand, simple approximations of nodal energy usage derived from estimates of node duty cycle and communication rates [4] do not capture the low level system power pro.le.

simulators that extrapolate system macrobenchmarks the large-scale, long-term, and system-wide behavior of a sensor network from models based on microbenchmarks of a single node cannot assure the accuracy of their generalizations [14].


For the non-adaptive encoder, increase in yield comes at significant PSNR penalty because the encoder has to ensure a low enough complex con.guration (for all die) that satis.es the required yield and hence a staircase PSNR waveform is observed.

adaptation allows for a graceful degradation in PSNR when improving yield, as operating con.gurations can change on a die-by-die basis.


Here, the variation is de.ned as the following equation, and it corresponds to circuit controllability.

max( f#1, ..., f#6) - min( f#1, ..., f#6) variation = × 100 f#1 f#n is oscillation frequency of line #n. when the body-bias voltage becomes larger than 0.5V, the measured oscillation frequency varies depending on the body-biasing position.


As a result, at larger partition sizes we can observe a larger number of nets where the ratio (d1/d2) is much less than 1.0.

it is important to note that even at the smallest partition size that we considered, where each partition contains only 6 gates, we see some local nets with a ratio as small as 0.65.


As the C/A code is modulated onto the I part, the correct match should only be located in the I part of the signal.

as the phase of the acquired signal is unknown, the I part of the signal generated at the satellite may not necessarily correspond to its recovered version.


Owing to these strong points, OFDM has been adopted for wireless local area networks (WLANs) such as IEEE 802.11a (IEEE 802.11g) [1][2], high performance LAN type 2 (HIPERLAN/2) [3].

oFDM systems are extremely sensitive to timing and frequency synchronization [4].


This causes a di.erence of functionality between three pairs of basic blocks bp1 and sp1, bp2 and sp2, and bp3 and sp3.

we know that the functionality of execution path bp1 .


makes the contention for an SRAM tile unavoidable, for our algorithm, the percentage of recon.guration reduction drops signi.cantly and the amount of data access latency reduction diminishes.

even in this case, our algorithm still achieves up to 33% reduction in average data access latency.


For example, when we compare the fastest to the slowest algorithms, we can achieve a speedup of 8x with a quality loss of just 1.1x in critical path delays.

the combinations vary very widely, from speed-ups up to 8x, and up to 4.5x quality degradation.


Becauseweuse LRUhitstodecidetochangethecachesize, we can increase the private size of the cache even when the working set already .ts in it.

this is only going to happen when the shared regionis not used sincein the other casesthe LRUhitsintheshared regionwill compensatethe counter value.


If wires are mostly in one direction, routing is ef.cient and increasing the cellarea is only necessary for very high congestion.

if wires are evenly distributed in the two directions, routing is dif.cult and increasing cell-area is expected for relatively low M1-congestion.


It is certain that users have to exchange battery of active RFID tags regularly in about one year or so.

the battery itself is inexpensive and the bene.ts provided by the system are much greater than the exertion spared for the exchange.


following expression: nstalled i tSLA < (tDM A + texe) * npage , (3) i=0 where nstalled is the number of stalled I/O requests targeti ing the same FIMM and nis the number of pages asso page ciated with the ith stalled request.

withthe queue-examination strategy, Triple-A counts the numberof stalled requests for each FIMM when the queue has nomore room for accepting incoming I/O requests.


Manufacturers today use sophisticated simulation software and model-based methods to perform OPC and RET in mask-making.

designers of chip layout are still using rules (to mimic these models) provided to them by manufacturers - for chip routing, DRC, layout parameter extraction (LPE) and parasitic extraction (RCX).


The generated routers are then injected into the compilation for each FPGA, and compilation proceeds as in the .rst pass.

at the end of this pass, during the local match step, all formerly dangling connections are matched to local endpoints at the synthesized routers.


This heuristic [8] is reported by the name Bounding Box Overlap in Section 4 results.

this approach neglects the fact that large bounding box areas reduce the probability that the net is actually routed to a specific point in that region.


Then, the coverage of a signal can be computed by relating the number of uncovered classes with all possible behavior classes of that signal.

a coverage metric should provide a measure for the complete circuit.


As we can see, the reduced curve cannot match the original when q< 70.

when we try to match high order POD moments, CORE becomes unstable due to the explicit moment matching method it uses.


Accelerometers had been used for ambulatory monitoring [2] and assessment of gait, stability and movement disorders [3].

no published work had been found on the use for posture monitoring in stroke survivors with physical impairment.


ibm01 dragon 0.58 0.86 0 1803 TOOP 0.63 0.90 0 547 3.3x 10% ibm07 dragon 3.55 4.55 0 5002 T OOP 3.96 4.79 0 1998 2.5x 12% ibm09 dragon 3.21 3.77 0 8736 TOOP 3.54 4.05 0 3415 2.6x 7% ibm11 dragon 4.77 5.50 0 9953 T OOP 5.25 6.33 0 4380 2.3x 10%  3.2 Interconnection-Aware Blocking Scheme The pre-fixed blocking scheme can effectively reduce th e size of the solution space for each cluster placement problem.

it blindly posts artificial regulations on clusters to restrict where they can be moved.


For example, although measured power is similar for gcc s regions around 88s, 110s, 140s, 210s and 230s, the similarity matrix reveals that the 88s, 210s and 230s regions are much more similar than the other two regions, which are also shown to be mutually dissimilar.

other applications we have studied, such as gzip, show more regular patterns with several similar phases.


On the RTL power estimation side, some commercial tools provide power estimates [3][14].

at such a high level, it is difficult to guarantee a strong correlation between the high level estimates and the final power dissipation.


1(b), we could decompose the given layout into two masks, and if DPT con.icts occur, we could perform LM on these two masks separately according to the DPT design rules.

this scenario might over-enlarge the layout area and induce redundant stitches, resulting in a poor-quality solution, as the resulting layout illustrated in Fig.


The services that we describe in this paper have been run on this testbed.

to understand how a shipping container size CamCube would perform we use larger-scale simulations.


The Level A scheme uses the smallest size of on-chip memory but it consumes more off-chip memory bandwidth.

the Level D uses more on-chip memory but it archives minimal off-chip memory bandwidth.


Giventhatfaultdetection occurs at ahighlevel, diagnosis is more complex.

since diagnosis is invoked only in the relatively rare event of a fault, a higher overhead is acceptable(but within the constraints of mean time to repair).


When an exception switches to any of the other .ve modes(IRQ, FIQ, Supervisor, Unde.ned or Abort), the $sp switches, disabling the .lter.

the stack is a di.erent memory region for every mode.


Per-process predictor tables eliminate inter-process interference in multi-programmed environments.


Explicit MPC is naturally less vulnerable to .nite precision e.ects, and can achieve high performance for small problems, with sampling intervals on the order of µseconds being reported in [8].

the memory and computational requirements typically grow exponentially with the problem size, making the scheme unattractive for handling large problems.


Moreover, a Moebius circuit has error detection and error gate search features as well.

though CLK tree synthesis which is inevitable for a DCVSL and CMOS circuits are not required in a Moebius circuit, the transistor count and energy per operation in the Moebius are respectively about 12 times and 10 times larger than Non-pipeline  = = = = = = = = = = Figure 6: Simulation comparison with Moebius and static CMOS static CMOS.


During the phase fk, the capacitor Ck is connected to the .xed capacitor CX in parallel.

in the phase fk, the Ck is disconnected from the CX and the transistor MNk is used to avoid charge accumulation [15].


In general, one would prefer to use the new controller as much as possible, provided it does not violate safety.

arbitrarily switching back to the new controller can cause the system to become unstable, even when each controller in isolation ensures stability.


The sequence pair is A1 B1 B2 ) C1 C2 A2 , B1 A1 C1 B2 A2 C2 From this sequence pair, we can conclude that bus u should be below v, v should be below w,and w should be below u.


RELATED W ORK A design-space exploration of DRAM system-level parameters is performed in [10] and [11], although the design choices are targeting non-real-time systems.

some of their conclusions, such as exploiting bank-level parallelism and selecting the correct transaction size to reduce latency, hold true for any system.


SLICC exploits the same way of re-using the instructions already brought into the cache by previous threads.

rather than context-switching on the same core, SLICC migrates threads to another core so that they can continue their execution.


When generating an authenticated encrypted bitstream, both keys are specified to the bitstream generation software.

to save storage space, only the decryption key is stored in the FPGA.


For our purpose, a convenient representation of chip leakage is given by [7].

our experiments showed that we need a more accurate model.


With rapidly growing microelectronics technology, high-speed, cost effective VLSI devices are available ..... ...... .............. .. 1. for implementation of signal processing algorithms like LP filters.

the objective of this paper is to design architectures for linear prediction for low-speed applications such as biomedical signal processing.


= 0.750. response time distribution 0.04 0.035 0.03 0.025 0.02 5 10 15 20 25 30 response time distribution 0.06 0.05 0.04 0.03 0.02 0.01 5 10 15 20 25 30  response time distribution 0.04 0.03 0.02 0.01 5 10 15 20 25 30 Note that, in general, results are sensitive to the complete distributions of the input random variables.

this is especially noticeable for the response time distribution itself, but not for the first moments, as we can see from Table II.


Obviously, the symbols with smaller pulse width require larger compensation coe.cients to compensate the channel attenuation.

the compensation coe.cients a.ect the horizontal eye opening (or level spacing).


On a larger scale, the performance costs of the disc-based analysis as well as the computational overhead of fault tolerance algorithms can presumably be mitigated by overlapping with a decent amount of the required computation.

in order to con.rm or demolish this assumption, a more in-depth performance analysis needs to be carried out.


Switching between the image and the 3D model is much less of a demand in the bottom-up approach.

after the detection of body part candidates it will be a complicated task to assemble them into a certain 3D con.guration within the model constraints.


The DDRx system on the other hand is oracular in nature and the memory controller is fully aware of the entire memory system.

our results showthat even with thesedisadvantages, the simple packet-based interface reaches performance levels very close to the oracular DDRx interface.


Because the S-Boxes and the Linear Transformation form the bulk of the round function, it is fair to estimate the decryption imple- mentation as requiring more space within the FPGA than the amount available for Architectures 2, 3, and 4.

an interesting alternative which explores the specific capa- bilities of FPGAs is to reconfigure the target device with a decryption architecture on-the-fly.


Detecting errors is a critical issue for hard and soft error tolerance, and there is signi.cant ongoing work on detection techniques.

much work still has to be done on the subject currently, ef.cient detection techniques with high coverage for processor logic do not exist, and a detailed discussion of such functionality is beyond the scope of this paper.


[11] conclude that comparable performance can be achieved with up to 28% less energy.

the tests were done in a strictly controlled environment tailored for the task; the firmware of the GPU was modified to facilitate the gradual scaling of the GPU s performance level.


This test involves sequential read/write I/O, especially for the scan step.

by having to actually consume step LOCAL BASE16 copy 0.157 (0.270) 0.163 (0.160) uncompress 43.932 (3.560) 45.337 (3.370) scan 81.524 (0.640) 83.784 (2.210) compress 496.400 (1.160) 501.013 (2.640)  Table 4: Filesystem test results for trace-.le (a single large .le, that is processed in a sequential scan).


The best places for the switches should be the cross points of the buses (Figure 2.b).

at the .oorplanning stage, these places are not predictable especially when we do not use the channel routing.


Applying this methodology to the previous example, the paths through logic cone X and Z are the longest in the circuit and hence are bottlenecks to minimum period retiming.

since X has a small number of paths, very few timing errors are introduced when the paths in X are relaxed.


The High Efficiency Video Coding (HEVC) is the next-generation video coding standard [1] that provides double compression compared to its predecessor H.264/AVC.

this comes at the cost of >40% more computation effort compared to the H.264 encoder as shown by our experimental analysis in Fig.


If we choose the byte-level study for the narrow-width data, the percentage of the narrow-width data in the cache may be high.

the area overhead will be also high due to the extra bit N (1/8 = 12.5%) needed for indicating whether the data is narrow-width or not.


The complexity of this access is in the same range as the complexity of the tag path in the main L3 cache.

many L3 cache designs implement sequential access to tags and data in order to reduce power consumption.


Recent approaches using a gate-array style fabric and top metal-level configuration will also help provide an intermediate point on the NRE-flexibility continuum.

neither of these solutions address the design NRE and time-to-market needs for today s SoC s which can have over 100 million transistors enough to theoretically place the logic of over one thousand 32bit RISC processors on a single die.


Its timing results are nearly as good as those of the Voters After Every Flip-Flop algorithm, and its area results are far better.

when sheer timing performance is the only concern, the Voters After Every Flip-Flop algorithm is the best choice in the average case.


Such an approach, called functional SBST, has a low development cost due to its high abstraction level.

a large number of instruction sequences is usually required to achieve high fault coverage.


For example, bridging [5], stuck-at [6], delay [7] and stuck-open [8] faults are among the most widely used fault models for CMOS.

on account of the double-gate con.guration, it is unclear if CMOS fault models can comprehensively model defects in FinFET circuits.


As a result, the numbers of active ways in a 4-way set-associative cache will follow the state diagram shown in Figure 1(a).

an extra way is allocated by MSA only when the new block and currently active blocks might be accessed in the near future.


So, Mesh-based systems are more resistant against node failures.

the disadvantage of this approach is the overhead for information exchange since the gossip protocol requires control packets containing the available segments in each peer to be forwarded to all neighbors.


Note that C2C frequency and power variations change across different dies.

for our analyses, we pick a typical die map from the 100 generated maps because a large amount of simulation time is required to repeat the same experiment for hundreds of die maps.


As a result, to prevent interruption to today s IC design flow, new, more aggressive RET technologies have been adopted by fabs to correct manufacturing issues seen at 90nm and below.

since manufacturing and yield issues are strongly designdependent and are affected by how the design is laid out, they are now being pushed upstream into the design process.


This is also a reason why the latest NVIDIA Fermi architecture (e.g., GTX 480 GPUs) provides larger shared memory and an L1 cache.

as shown in Section 7, the high number of SPs in an SM in GTX480 (and even higher number of SPs in GTX680) makes TLP more important to hide instruction execution latencies.


Since the memory does not interfere with shift operation of the PSC, there will be no negative impact on diagnosis coverage due to the extra read operations.

an extra scan_en signal is required to control the capture of memory test response and the shift or serialization of the Figure 6.


Note that in our evaluation we have assumed that cache latency does not grow because of this mechanism.

performance will degrade if we take into account that cache latency grows because of the sequential actions taken by this mechanism (cache line reading, SECDED correction of the repair cache line and bit replacement in the data cache line).


On success, the chunk commits in bulk; on failure, a chunk aborts in bulk (e.g., back to a checkpoint).

rerun never aborts an execution, but rather passively records the core s execution.


(i,j) EQ (1) can be written in matrix notation [9] and the problem can be e.ciently solved using SOR or conjugate gradient based methods.

the resulting placement has signi.cant module overlap.


Although both log write style and read-before-write schemes can help reduce energy consumption, they cannot work with each other at the same time.

we believe that these two schemes are used in di.erent scenarios.


Scores of novel applications have exploded into both consumer and commercial markets, giving casual users and professionals alike access to enormous collections of audio and video data through CDs and DVDs, commercial service providers, and public web sites.

the usefulness of this wealth of information will be largely determined by how effectively these collections can be manipulated and searched.


Matrix Multiplication can be hardened adding a checksum on the input matrices, as every thread is independent and does not interact with the others.

fFT requires the introduction of checkpoints at every iteration to avoid error propagation.


It was used by Secareanu and Friedman [9] with a variable-length segment methodology to drive highly resistive RC interconnects.

they partitioned the interconnect using 4 design phases, which unnecessarily complicates the usage of such technique by designers.


If coherent detection is utilized at the receiver, the residual frequency shift can affect the detection process unless it is compensated through dedicated Doppler tracking [6].

if di.erential detection is used, the residual frequency shift does not a.ect the detection process because it is similar between adjacent subcarriers, thus satisfying the assumption that the channel response does not vary drastically between consecutive subcarriers.


The C programming language is effective for improving algorithm because the algorithm can be modified easily.

the software simulation is so slow that it s difficult to simulate the video processing in real time.


Both approaches generate results with identical TOF and 0 unit of LD violation for each test case.

pseudo layer assignment does not consider via minimization.


To follow both the scaling of the minimum channel length and the system-on-chip trends, analog-to-digital converters (ADCs) need to be operated at low voltages, especially in portable devices.

the minimum supply voltage for analog circuits predicted in the road map [3] does not follow the digital supply voltage reduction.


A variety of techniques exist to deal with such faults, from special radiation-hardened circuit designs (e.g., [6]) to localized error detection and correction (e.g., [1]) to architectural redundancy (e.g., [26], [23], [20], [2], [16], [18]).

all of these approaches introduce a significant penalty in performance, power, die size, and design time.


We show that when thermal stress is severe, an aggressive DTM response based on voltage scaling is likely best, because this obtains approximately cubic reductions in power density relative to the reduction in frequency.

when thermal stress is mild and only a mild DTM response is needed, we show that an architectural response that exploits instruction-level parallelism (ILP) has less overhead than DVS possibly even no overhead if ILP is suf.cient.


When not in use, the badge display defaults to an image which represents the corporate ID badge it replaces.

as soon as the badge is pulled away from the belt, the system activates a building floor plan display application.


3.2 Host Classi.cation Using the above classi.cations of each connection in our dataset, 3Bro currently produces 13 different states.

over the years additional codes have been used as understanding of how to best summarize status information evolved.


For the multi-scenario bu.er insertion problem in multicore processor designs, a naive approach is to run Ginneken-Lillis algorithm separately on each instance and then pick one of them, which is most critical (e.g., among the best solutions of all instances in max-slack problem, a critical solution is the one with the smallest slack) and apply it to all instances.

the algorithm run on one instance may prune a partial solution which is preferred in another instance.


We conducted an experiment where we vibrated a Nexus 4 phone in the phone s 3 axial directions (one by one) using strong approximately 1 cm oscillations.

this did not cause a change in the noise value (1 metre without smoothing), nor cause outliers.


In [11] the authors use FDTD and FFT to obtain frequency dependent Poynting vector and decoupling capacitors are iteratively put at the port with maximum Poynting vector.

in both papers the decoupling capacitor value is .xed and ESL or ESR is not considered.


In the first category, circuitry is added to mask selected unload values so that X s do not reach the MISR [7], [11], [12], [13].

if the number of X s is too large or the distribution is unfavorable, masking may have a high area overhead or it may not be selective enough; therefore, non-X values would also be masked out, resulting in a potential loss of coverage or increased number of patterns.


When the present accumulation factor is set to 1.1 for TDVPR, the routability result of TDVPR is improved with TDVPR routing 4 additional instances than SpiralRoute-MCF.

with the exception of des/5 the additional instances do not meet the timing target, and there are 19 problem instances when only SpiralRoute-MCF routed a solution meeting the timing target.


Here, either net D BDCABor net needs to be ripped up for net to be routed successfully.

since net and net have no other available metal2 resources, their terminals will be blocked unless net is ripped up, too.


Note that only the LSB of the b-bit digits Xn and Yn can be equal to one in order to satisfy 0 = X, Y < 2 * M. For digit Tn the two LSBs can be equal to one, while the rest of the bits are zero, because T< 4 * M is always ensured.

in the implementations that are discussed in Sect.


Most have never used it to summon help (65%) and most have never wanted to use it but found it out of reach (85%).

a significant minority (11%) has found themselves without their trigger when it was needed.


If so, in reality, the HPWL of net2 may not be reduced at all.

for net1, no matter how pin1, pin3 are moved in their windows, the summation of HPWL reduction in both windows always equals the global HPWL reduction.


Making C0 equal to C1 is a straightforward approach to divide a region.

larger C0 (C1) does not mean that B0 (B1)has larger N0 (N1).


Up to now, many tests and simulations focused on the EMI influence on the bandgap voltage references [2-6] where performed.

the majority of these studies were focused on the role of the op-amp (inherently embedded in most bandgap).


Note that even if b is executed relatively frequently, but such executions of b are dispersed in the trace T rather than clustered, then self-concomitance s(b,T ) will still be low.

if for certain input a particular loop is frequently executed, then the trace self-concomitance s(a,T ) of each basic block a from this loop will be large.


Certain problems, such as min and max, become trivial to implement, but of course there are many other relationships that are then harder to calculate.

min and max are powerful operators and sufficient (with the proper routing of values) to solve complex optimization problems, including but not limited to those solved by dynamic programming.


The data shown in the figure are average rates for all cache lines, rather than for any specific line.

a program, which contains a large loop revisiting the same code time after time, will show very different behavior.


Our experiments mainly focus on the energy-driven optimization.

we also show some intermediate schemes of the optimization, which demonstrate the speed and distingushiablility improvements of the dual-element cell.


2We could have also chosen a second SRAM size to be 20% of total code + data size, when evaluating the methods for both code and data.

to make comparisions between methods for data only and for both code and data, we had to choose one SRAM size so that the comparison is fair.


Whenever a con.ict occurs during the search, the con.ict is analyzed to .nd the responsible decisions and a con.ict clause is subsequently added to the CNF formula, followed by a backtrack in the search.

because the additional XOR clauses added to the CNF formula are only used for comparing the given pair, all con.ict clauses added to the CNF formula are valid only for that particular node comparison process and should be removed, along with the XOR clauses, before proceeding to the next candidate pair.


This shortage could be alleviated, if a large number of deferrable loads, particularly the high powered ones, could be moved from on-peak to o.-peak times.

conventional DSM strategies may not be suitable for India as the local conditions usually favor only inexpensive solutions with minimal dependence on the pre-existing infrastructure.


A Reuse-Aware Prefetching Scheme for Scratchpad Memory Jason Cong, Hui Huang, Chunyue Liu and Yi Zou Computer Science Department University of California, Los Angeles Los Angeles, CA 90095, USA {cong, huihuang, liucy, zouyi}@cs.ucla.edu ABSTRACT Scratchpad memory (SPM) has been utilized as prefetch buffer in embedded systems and parallel architectures to hide memory access latency.

the impact of reuse pattern on SPM prefetching has not been fully investigated.


For instance, tOP for a read and a write command is given by tRD and tWR, respectively, which correspond to the period of data transfer during the respective read and write operations.

tOP equates to tRAS, tRP and tRFC for ACT, PRE and REF, commands respectively, which are JEDEC-speci.ed minimum timing constraints to be satis.ed for these operations to .nish [20].


Their width is de.nable down to a resolution of a single sample.

there is a trade-off between resolution and processing ef.ciency.


All selectors start with the same pool of minigraphs that are not vulnerable to serialization by virtue of their data.ow shape.

different selectors start with different pools of potentially-serializing mini-graphs, i.e., minigraph that have an external register input to any instruction other than the .rst.


Deadlock-free routing is crucial because it guarantees correct functionality under worst-case scenarios.

some routes calculated from the CDG are nonminimal which increases the average hop count and hurts  Name dodec mesh-dim mesh-romm torus/ring-dim d3 d8 d4 d5 Routing example adaptive deadlock-free routing dimensional order routing 50 ROMM [16] dimensional order routing 45 torus/ring-adp minimal adaptive routing [17] Table III: Topologies & routing algorithms for comparison network performance.


2.2 Video Streaming Datagram protocols, such as the User Datagram Protocol (UDP), can be used to transmit the media stream as a series of small packets.

there is no mechanism within UDP to guarantee data delivery.


If the input is high (tied to VDD), NEMS1 is OFF since the beam and both gatesare at the same voltage level (there is no electrostatic force to bend the beam).

the beam of NEMS2 is tied to GND and the input isconnected to VDD, which creates sufficient electrostatic attraction to deflect the beam and turn the device ON, thus connecting OUT to GND.


In [[4], a cost function of error tolerance was defined based on path delay and then optimized by gate resizing.

it did not consider all factors during the optimization.


If it is storing a 1 , meaning that the resistance is high, the voltage drop on the pass gate is relatively small and ......0 is relatively high.

if the MTJ is storing a 0 , ......0 is relatively low.


The graphs reveal that, as the fraction of neurons approximated by the AxNN methodology increases, the runtime decreases proportionally.

the corresponding decrease in the application output quality is disproportionately small due to the careful selection of neurons and re-training.


However, Wq is the smallest and remains small across the examined .s.

wq is more prominent for designs PEb and PEc once the arrival rate exceeds .


Hence, due to its often non-formal nature, implicit constraints cannot be utilized for any type of controlled constraint-driven design.

explicitly given constraints are accessible to design algorithms and thus are a primary requirement for any constraint-driven design flow.


Recent work suggests a new method of merging con.gurations without fully overwriting the target area [13], and an algorithmic approach for run-time con.guration generation [11].

the proposed designs often involve special-purpose run-time systems, and are not capable of compiling arbitrary con.gurations.


Therefore, it is possible that a small number of parity functions will be adequate to cover all erroneous cases.

a large number of alternative parity functions exist, exponential to the number of state/output bits.


The pdf.les of the documentation did not help because they only explain how to use the design.

most of the source code .les have a description explaining their purpose.


Minimizing ACT commands can also give performance improvement (by reducing clock cycles spent for row opens and closes).

not all the methods of memory performance improvement contribute to the minimization of ACT commands.


Up to 4.3s, the write operation is successful if TWL is larger than TCRIT, WRITE (TCRIT of the write operation).

bSW is pessimistic because the infinitely Figure 5.


Also, PEM can o.er the same accuracy with MMC+APEX method, which implies that PEM can achieve high accuracy of high order moments.

we further validate accuracy of PDF function from PEM against the histogram from Monte Carlo simulation in Fig.


While the timing closure problem has been extensively studied in academia [5][6][7], and several commercial flows have been proposed by the EDA industry, of equal importance is the impact of wiring on defining the block or chip size, in particular for logic synthesis, which traditionally has attempted to minimize cell area in order to minimize the size of a block or IC, without considering the interconnect area.

since the DSM wirelength trends do not scale with feature sizes, cell area minimization can no longer guarantee overall block or die area minimization.


The anomaly detection works aim to detect small deviations in program behavior during an attack such as a bu.er over.ow or control .ow deviation from otherwise mostly benign execution.

we attempt to identify execution of whole programs such as key logger when it is run, typically as the end result of exploitation such as bu.er over.ow vulnerability.


We simulated 5,000,000 cycles, of which the first 1,000,000 cycles were discarded as warm up.

the success rate should be related to the setup delay to make it a useful metric.


The tool uses carefully crafted and tuned cost functions to achieve high-quality timing and placement solutions in reasonable time; these make it the current champion among academic tools for placement of MCNC and other public-domain benchmark circuits.

published versions of VPR do not handle carry-chains or multiple delay constraints, and apply primarily to non-hierarchical, islandstyle architectures.


For any memory access sequence, one can calculate an upper bound on the misses for each block.

there are exponentially many paths in the CFG and it is infeasible to do the above analysis for each individual path.


Note that once the writeEnable signal is activated by the FIFO controller, the write wordline corresponding to the current .it can get activated only after propagation delay through the write counter and the delay through the decoder (illustrated by Wordline Enable Path in Figure 4.3).

writeDataFlit propagates only on metal wire and would always gate the wordline correctly.


As already mentioned in case study 1, a structural ADL canbe used to model an architecture thenboth the software toolkit and theRTL description can be generated.

if the architect wants to evaluate some design variants prior to development, modeling and modifying such kind of ADLs are not an easy task.


The automaton describing the AHB read transfers is smaller, as most transitions are contingent on the behaviour of the slave which is less varied than that of the master as it has fewer signals.

aMBA Peripheral Bus(APB) shown in Figure 4 is extremely small with only three states as it has only two control signals and had no pipelined operation.


We conclude that it is quite challenging to predict up-front when sharing will provide an area bene.t, as it depends on the speci.c technology mapping and packing decisions made by Quartus, which appear to depend on the speci.c pattern implemented.

we observe two general trends: 1) Sharing is more likely to be bene.cial for composite operators that consume signi.cant area, particularly when the MUXes that facilitate sharing can be rolled into the same LUTs as those implementing portions of the operator functionality.


The unknown distribution of circuit behaviors in performance space can be estimated by solving SoP expansion coe.cients [5, 3].

the SoP-based methods require knowing the type of the stochastic distribution of the circuit behavior.


If the device spends relatively little time in standby mode, the impact of this standby energy is negligible.

if the device spends the vast majority of time in standby mode, as is the case for many sensor applications, the standby energy can be many times that of the energy consumed in active mode.


We assume there is no benchmark execution during mode transitions.


In the example, overlap between Regions 1 and 2 is avoided in this manner.

regions 1 and 3 do overlap in the example.


This is in direct contrast to super-threshold design where, without regard for performance, it is always possible to reduce energy requirements by lowering voltage.

subthreshold voltage levels exist where reducing volt- Phenomena Sample Rate (Hz) Atmospheric temperature 0.017 -1 Barometric pressure 0.017 -1 Body temperature 0.1 -1 Natural seismic vibration 0.2 -100 Blood pressure 50 -100 Engine temperature/pressure 100 -150 ECG (electro-cardiogram) 100 -250 Figure 1 illustrates the performance of these benchmarks on a variety of commercial microcontrollers (the .gure is from [13]).


The worst-case a is unique for each gate-arrangement in a logic-path.

in most realistic circuitpaths comprising of non-homogeneous, multiple input gates there will be logic-masking of NBTI stress-sites (as shown in Fig.2) because the applied input signal may not be the controlling input of a gate in the path.


Here, (OP0) reveals the number of nets which is 35344 in this instance.

the remaining cases have transformed all inequalities to equalities and are De.ne a 0-1 variable yij whose value is 1 if the cloud esimmune to this attack.


Obviously, the remaining obligations should not decrease the duty required by the original policies.

we can imagine that many of these obligations are similar to each other since they are obligations associated with similar permissions.


Traditionally, the access time or reuse distance of a cache block is treated as its value.

cache miss latency is variable in modern systems.


For example, the veri.cation of transmissivity and re.ectivity is a very time consuming task in case of the cascade of microresonators with a very large value of N (for example, N = 20 [14]).

this can be veri.ed in a very short time using the infrastructure developed in this research because all the results are veri.ed under the universal quanti.cation of system parameters.


Increasing the size of this window would unfairly in.ate the coverage provided by Shoestring since accommodating large checkpointing intervals requires substantial hardware/software overhead.

if large checkpointing intervals eventually .nd their way into mainstream processors, the heuristics used by Shoestring can be easily tuned to exploit this additional support and provide even greater coverage.


Recently, the sharing degree of shared L2 NUCA caches in CMP design was examined [15].

in these NUCA designs, the access latency di.erences are mainly from interconnect delays.


We .nd that the total area of the circuit decreases by about 5.3% on average.

the average channel width increases by around 15.4%.


Firstly, in this flow, the repeaters introduced within each iteration are treated as first-order objects, just like the other cells required for actual logic computation.

these repeaters should exist only if their location on the net helps alleviate RC concerns.


The families of recurrences presented in this section ensure that we meet some of our requirements: performance (bymaking sure that the criticalpathisFF-LUT-FF), maximummemorybandwidthutilisation, andlogice.ciency(as each active bit uses exactly one LUT).

they only provide necessary conditions for maximum period, quality, andpolynomialdensity,theydon t guaranteeit.


small number of misses eliminated per pre-execution in ms t and In summary, the experimental results in this section demon- raytrace explains why they are more affected by the thread- strate that the additional hardware support for our pre-execution spawn latency.

the other four applications (except scheme can be very minimal: Register copying can be done in compress) eliminate an average of at least 20 misses and can software and a scratchpad may not be necessary.


Base layer includes the coarse level of DCT coefficients and the enhancement layer includes the finer level of DCT coefficients.

the saturation control is clipping the results of IQ.


To avoid the false sense of security produced by shallow properties, one could restrict the signals in each property to one primary output and an arbitrary number of primary inputs.

this may be too restrictive when the relationship between inputs and outputs is complex.


This work was supported in part by NSF grants (0702617, 0903432, 0905365, 0916887) and SRC grant.

in some cases, these methods may not work ef.ciently because it ignores the pattern of data.


The dots, corresponding to measured data in [1], illustrate that the reported MTJ material properties are acceptable for RD.

significant advances are needed in the JC and RAPA parameters to support fast writes under voltage constraints of typical logic processes.


We pick simulation windows using the methodology described in Section 3.2, but we extend their duration to 1 billion instructions.

comparisons against off-line learning (e.g., Section 4.4.1) use the smaller simulation windows of 100 million instructions due to the complexity of simulating OFF-LINE.


Mok and Chen introduced this idea in [1, 4] and showed promising results for MPEG-streams where the average load for a sequence of I-, P-and B-frames is much smaller than in a stream that consists only of large I-frames, which is assumed by a context-blind worst-case response time analysis [1].

the periodic sequence of types of activating events was supposed to be completely known.


For instance, a popular distribution function is the Gaussian model.

for the uncertainties in design parameters, such as supply voltage VDD and temperature, they are usually treated as corners of the operation condition, rather than random parameters.


Iyer discusses cache QoS and a framework of possible solutions [13].

iyer s discussion is based on a definition of QoS that may not apply to certain types of shared resources, in particular, bandwidth resources.


A lot of papers have been published to deal with repeater insertion in a more complicated environment such as: simultaneous area and power optimization [4], delay and bandwidth constraints [5], throughputcentric optimization [6], and throughput-per-energy-area optimization [7].

all of these papers essentially employed the same conventional global interconnect design methodology, and completely ignored the inductance effects, treating the interconnect as an RC delay line.


(c) During cache idle cycles, instead of the traditional single cache, in our approach two caches consume idle power.

since the main memory accesses are much more power hungry than the cache control, this overhead is small compared to the savings obtained by reducing the main memory bandwidth.


In the ideal case, if the CPU requests are distributed evenly across the run time, it will take 40,000 cycles to produce 16 requests, which is within the worse-case capability of the 16-deep debt queue.

the results show that the bandwidth requirement of the CPU trace varies signi.cantly over time; as such, the optimal debt queue depth also varies with time.


MODELING & ANALYSIS OF CNT INTERCONNECTS The first reported work comparing CNT interconnects to copper [7] highlighted the imminent thermal/reliability problems of minimum dimension Cu interconnects, vias and contacts and examined the advantages as well as the process technology requirements for CNT bundle based vias.

several studies comparing only the performance of CNT interconnects to that of Cu have been contradictory.


After choosing one hit point for each I/O pin and the accessing direction for that hit point, the Metal-2 wires can be designed for pin access, accounting for the minimum enclosure design rule for Metal-2 over Via-1.


have explored this further, considering the transient cooling effects in integrated TEC systems and have developed control principles for taking advantage of transient cooling effects [7], [8].

the experimental demonstration of an on-chip TEC controller with programmable current source is not reported in the literature.


[17] discusses the design of a variability-resilient 10T TFET SRAM cell.

the increase in the number of transistors in the TFET SRAM cell results in a reduction in capacity.


The authors of [17] target a coarse-grained recon.gurable fabric and perform online synthesis of the CGRI.

as they do not use FGRAs (and thus do not bene.t from their performance), they do not address placement of FGRAs and binding of operations to FGRAs at runtime (details explained in next section).


Finally, the signal is recti.ed and regulated to a stable DC voltage.

using the audio output driver has signi.cant drawbacks.


Clearly, this is much better than what can be expected from waveform manipulation or pure analog circuit improvement.

the proposed approach builds on a postulated energyscalable reconfigurable analog transmitter that depicts a controllable tradeoff between its performance - in terms of output power and linearity - and its DC power consumption.


Software management of a low associativity cache is overkill; the complexity of a software replacement algorithm is generally not justified when there are only a few replacement choices available.

the complexity of managing replacement state for a large, fully associative cache is generally beyond the capability of a hardware implementation, unless a trivial policy such as random is used.


The inherent advantages of custom-logic hardware devices, such as the FPGA, combined with the versatility of software-driven hardware configuration often boost performance while reducing power consumption.

compared to software design tools, the relatively immature state of RC design tools significantly limits productivity and consequently limits widespread adoption of RC.


In Table 4, there is actually no performance gain when the degree of parallelism is equal to or larger than four.

there is no I/O overhead for the result using embedded microprocessor.


Neural networks have been intensely studied since the beginnings of integrated circuits as an alternative computing architecture beyond Von-Neumann [9-10].

little success has been met partly due to the lack of simple synapselike devices [11-12].


Compared to slew, delay distribution is closer to a normal distribution.

asan approximation, it may be 100 20 80 60 acceptable to use normal distribution for timing analysis.