These works show that predictions can get very accurate.

previous works do not consider the register .les.


We express the function Db(x, y)as Db(x, y)=Px(b, v)Py(b, v), (5) v.V where Px and Py are the overlap functions of bin b and block v along the x and y directions.

the overlap functions Px and Py are neither smooth nor di.erentiable.


When the slice count increases from 16 to 32 the percentage of the throughput attributable to reads is reduced because the increased demand from the clients write requests pushes the compaction load lower.

the Huawei Gen3 exploits channel parallelism for individual 8 MB-patch accesses so it can achieve much higher throughout when the slice count is small, but its throughput does not increase with increasing slice count.


Numerous efforts have been spent on trying to integrate high accuracy stimulus sources on-chip to accomplish ADC BIST [1-7].

the on-chip implementation of sufficiently high accuracy stimulus sources is extremely difficult.


In that work, there is a very small variation in the transient width between four technology nodes (250, 180, 130 and 100 nm) for low energy particles.

for particles with high LET, for instance 70 MeV-cm2/mg, the widths of transients between the 250 nm (948 ps) and 100 nm technologies (694 ps) decreases 27%, while between the 180 and 130 nm technology nodes, the transient width for this level of energy increases from 772 ps to 900 ps, i.e., 17%.


In [6], the authors show that sizing based on time varying discharge current pattern instead of just the peak discharge current can lead to lower sleep transistor sizes, as compared to [5].

one major drawback of this methodology is that there is no control on the virtual ground voltage and hence can lead to signal integrity problems.


In most of the cases, this kind of con.ict should be handled in the same way as Hint 1.

if the con.ict clause is composed of only slot variables, this is a hint of ordering problem.


Applications of communication frameworks for HTH activation and HTH-based covert channels [13], or for capturing the information leakage [17] caused by HTH have also been described.

these works are di.erent from ours in the sense that all of them assumes that the circuit is Trojan infected at the point of its deployment, while in the proposed work the Trojan is inserted run-time through Ethernet communication interface.


It is further divided into .xed-sized physical pages (e.g., 4KB pages) and each physical page is composed of a .xed number of physical lines, where the size of a physical line is the same as the cache line size (e.g., 64B) of the adopted CPU; this is because a cache line is the basic unit of CPU to access memory.

the linear logical (address) space of PCM is partitioned into the main-memory space and the storage space.


Thus, the eigenvalues of [][ ]C are directly concerned with the L propagation modes of the system.

for the transmission line system with the homogeneous media, since the propagation modes are identical, they cannot be mathematically distinguished with the propagation modes.


Each new iteration at time trequires a new set of variables Vbtand Vat.In this way, the number of variables needed grows with the number of iterations of the .xed point procedure.

this does not represent a signi.cant limitation, since the algorithm usually converges after a relatively small number of iterations.


In this case, we have a simple bound n on the critical pulse width: T ()I =CV dd /I (19) crit n n This expression states that when the noise amplitude is sufficiently high, the SRAM cell will undergo a state-flip once the total charge deposited by the transient noise is equal to the charge stored on the node, CVdd .

if the noise amplitude is comparable to those of the driving currents, the critical pulse width given by (18) is greater than that given by (19), as confirmed by the experiments in the next section.


One might expect the SPEC workloads to have a longer optimal pipeline depth than the traditional legacy workloads, due to the fact that the SPEC applications have fewer pipeline stalls than the legacy applications.

the opposing effect that the SPEC applications contain a higher degree of instruction level parallelism, that can be exploited by a superscalar processor, is even more important.


They de.ned the engineering change problem as constraint manipulation where the graph is restructured in such a way that it supports EC.

there are numerous di.erences and novelties.


3.2.2 Method 2: Estimation of local routes based on pin density Based on our experiments, Method 1 is reasonably fast and very effective in modeling congestion due to local routes.

calculating Steiner trees for all the pins of each net in every g-cell can become a productivity bottleneck when congestion analysis is invoked hundreds of times (for example, during physical synthesis).


Figure 4: Architectural view of our SET Tolerant Design DFF modi.ed  Figure 5: Gate Level View of our SET Tolerant Design There was a 66mV reduction in the noise margin of an inverter in the protection logic due to our modi.ed sizing approach.

since thisskewed sizing is only used in the secondary path, and all the nodes inthe protection circuitry are SET immune based on the discussion of Section 3.2, this is not a problem.


Modular Selector The selector presented in [17] meets and even exceeds observation probabilities, and has low delay and wiring overhead ( Modular selector column in Table 1).

it can only support a maximum of 512 chains and a fixed 32:1 compression ratio.


As the C/A code repeats every millisecond, 1 ms of data is enough for acquiring satellites.

as the data packets are modulated by the C/A code at 50 bps, there is a possibility of a bit transition every 20 ms.


This will lead to a larger than nominal voltage swing on them which consequently increases their energy consumption.

the active bitlines can also consume more energy due to larger swing on them and due to short circuit or leakage effects in the cells being activated.


[19] used the modern wire model[9] toformulate aninterconnectmodelpredicting 2D and 3D channel width requirement.

rahman only models wire length L and not the .exibility of the switching blocks.


This in theory meant it was possible for participants to act individually which may not be conducive to effective collaborative learning if participants are not aware of what each other are doing [18].

we observed that periods of completely individual working were few and usually short lived.


It is also seen that the lowest test times are obtained for combinations with a lower degree of sharing.

for W e48and W ea4, the lowest test times can also be obtained with combinations that have a high degree of sharing.


4.3 B-Tree under Overwrite Limits The B-Tree results indicate a high potential for utilizing overwrites.

the actual resulting overwrites also depend on the physical overwrite limit.


This mechanism aim at avoiding the data-dependent dissipation.

there are still some non-adiabatic dissipations.


UWB impulse radios and organic solar cells are still in active research and have groundbreaking future prospects.

we show that current 802.15.4 radios and commercial solar cells are suf.cient to network of small, energy-harvesting sensor nodes.


As a result, it is widely believed that modern synthesizers use CSD to synthesize arithmetic circuits.

after deeper inspection on the synthesized netlist of constant multipliers, we found out that modern synthesizers apply varied kinds of BSDs in addition to CSD.


Although there have been previous attempts to automatically create functional assertions from RTL code [6], none has been able to create fully correct assertions that cover the full range of behaviors of a design.

most modern HDL simulators include an automatic method of extracting all code coverage points, including line, branch and conditional coverage points.


It operates like a gate level pipeline without timing errors and has very high throughput and low latency, with error detection and search features.

including matching stages by inserting bu.ers, its size and power consumption are comparatively large.


COMPRESSION TECHNIQUES: APPLI-CABILITY & IMPLEMENTATION COST Datacompressionhasbeenextensivelystudiedinthepast.


temperature in the system goes up rapidly with the increased power consumption.


In the RC unit, transient errors can be managed with re-computation and the residual errors do not result in packet loss.

the undetected errors in the RRA unit will lead to packet loss and network congestion increase.


This would reduce Vdd on all SRAM circuits, and hence lead to strong leakage power reduction.

the primary reason this idea is not considered is that stacking all circuits on the one power switch puts a heavy current load on the switch during active mode.


B. Substrate Noise Model Several techniques have been proposed to model and analyze substrate noise accurately in integrated circuit level [11] [13].

these techniques require the detailed implementation information in transistors and time-intensive transistor-level simulation.


As shown in Figure 9, when the SMN bit is set, a load access that reaches the LLC does not snoop the lower level caches of other cores, because the compiler explicitly indicated that this variable is not shared.

if the SMN is not set, the hardware performs as usual (lines denoted by esp).


For compress, recall that pre-execution is overlapped with only a single lookup of htab (refer back to Section 2.2.4 for the details).

since most of these lookups are actually found in either the D-cache or L2-cache, there is insufficient time for pre-execution to compute the address for the next lookup.


We also consider an extension of the static scheme presented in the paper that can potentially exploit a larger set of don t cares by allocating them dynamically during the SAT solving process rather than statically.

in practice, the overhead of managing them generally overweighs their performance advantage.


Structural relationships are related to the standard notion of type polymorphism in languages with more advanced type systems than C; commonly (but not exclusively) .elds in a structural relationship would have related polymorphic types in statically typed functional or object-oriented languages.

solving our problem requires more than identifying polymorphic .elds, as we must also understand the actual contents of those .elds, which means .nding and correlating the .eld assignments.


Polynomial coef.cients can be calculated by applying the algorithm of Figure 3 on p nets of a circuit (model making set).

there is no guarantee that the calculated polynomial may be successfully applied on the other circuits.


happens, our algorithm enters the second stage to route each failed ECO net by allowing over.ow to occur during the course of routing a sub-net.

if the routing result of a sub-net causes an edge e to over.ow, the cost of e will be incremented immediately and the previously routed sub-net that passes through e will be ripped up.


Due to the high value of thee PMC resistance in state '0', an uncertainty may exist due to a discharging node between D and DN.

the ON state rresistances of M1 and M7 are less than the resistance of the PMCC; so, the voltage at D is at 0V.


It is observed that the total leakage current of a 16KB memory cell array is exponentially dependent on Tox and Vth.

hence, we approximate the total leakage power as follows: a 1* Vth a 2 * T o x P to ta l (V th , To x ) = A0 + A1 * e + A 2 * e the delay of the array is shown to be linear with Tox and  word address decoders, with address and data buffers consuming the least amount of leakage.


This leads to a high abort rate, which means that many cache line transfers in the system are wasted.

as soon as a CPU obtains a lock, that CPU is guaranteed to .nish the update on all 4 lines and thus less cache bandwidth is wasted.


Provided that there are enough number of transactions, when the memory interleaving depth is expanded to increase the number of channels, the effective bandwidth increases, too.

when it is expanded to increase the number of ranks, the effective bandwidth does not increase or decrease in some cases.


Our pilot experiment also indicated that the use of Parallax Augmented Desktop was faster than use of a mouse for the same task.

these results are drawn from pilot studies with N=3 participants.


Another possible attack would be the degradation of a packet resulting in worse QoS sensed by the user, thus causing damage to another operator s reputation.

users may wish to protect the class of service against eavesdroppers in order not to disclose the type of traf.c.


Even for the 50% case, the performance penalty of our technique is less than 1% of the base case.

as the variation percentage increases beyond 50%, because of many blocks being turned off, not much space is available in the cache, increasing the peformance penalty of our technique.


Assume that wehavederived the raw mousedata containing clicks on a software keyboard, we can derive the clicking topology.

wedo notknowthe exact starting point of the trajectory, and therefore cannot determine which keys are clicked in the topology.


Accordingly, for a microcoded IP that holds a set of applications, the required LUT size is usually determined by the application of the largest code size.

the LUT size required by the proposed hybrid compression technique is less sensitive to the original code size.


Even with the best possible language models, these methods are limited by their ability to represent language statistically.

we propose using Commonsense Knowledge to solve the context problem with semantics in addition to statistics.


This cache word subblock can only store 16-bit and 32-bit narrow-width values.

the cache write hit occurs and this data is modified to a 48-bit narrow-width value.


The closest architecture to ours, in terms of conservatively adding delay to inter-task data dependences is theSkipperarchitecture[5].

skipperlimiteditself to spawning the closest postdominator, while we show that this spawn choice might be suboptimal.


We .nd that, if a benchmark is not very bursty, then the STTRAM-4TSB-SS scheme, in spite of using only 4 TSBs for sending requests from the core to cache layer, on an average improves performance.

if an application is bursty, STT-RAM-4TSB-SS scheme is not able to manage the requests to busy and idle banks well enough due to the lack of congestion estimation among parent and child nodes in this scheme.


Overall, the proposed CAM is quite expensive compared to an energy e.cient unprotected CAM.

if error protection is required, the cost is clearly lower than using multiple unprotected units.


It approximates the wirelength by a convex quadratic function, which can be minimized ef.ciently by solving a linear system.

minimizing just the wirelength would lead to considerable cell overlapping.


Most of the fault-tolerant schemes proposed in this work can be retro.tted to existing router designs.

they are particularly amenable to the RoCo router because of its decoupled nature that allows for graceful degradation.


A more accurate fault modeling methodology is Static Timing Analysis (STA), used by chip designers to identify the critical paths that are likely to fail.

pV changes the order of critical paths: paths that were indicated as non-critical by STA may become faulty, while the paths indicated as critical may not cause timing violations.


A transistor can be viewed as a nonlinear conductance under steady state conditions.

modeling the transient behavior of a transistor requires complicated nonlinear capacitances.


If the vi-glitch-peak is less than the 50% of the .nal value, the 50% delay of the signal can be determined with the RC-like main lobe by using (15).

if it is not the case, the signal delay due to the glitch has to be taken into account since the vi-glitch-peak may exceed the 50% of the .nal value.


The ability to detect or prevent storage based covert channels typically relies on searching for anomalies in packets.

with Analytic cookies it is di.cult to build a reference base of expected values, and thus di.cult to stop this covert channel.


When the standard is viewed in the abstract, it seems to effectively provide security and privacy, because it uses strong cryptographic algorithms.

when you examine the standard in the context of potential user scenarios regarding its use; security, privacy, and usability problems can be identi.ed.


Only two equality constraints -(n+1) 0 p+1 0 (i.e., .s = .s and .s = .s for n incremented, and -n 1 p+2 1 .s = .s and .s = .s for p incremented) need to be added per time-frame expansion.

if we were to append a new time-frame at the end of the array, we would have to add (n+p +2) looping constraints related to the new time-frame added.


The Opteron solution, with 4 parity chips, comes close to this theoretic lower bound.

this result also means that the Opteron solution is only practical with ×4 chips, since 2 ranks of ×8 chips would only provide 2 parity chips.


Each thread has its own program counter, because the two binary images need to be fetched into the instruction caches and decoded by the CPU.

different from the conventional SMT architecture, the two threads have identical program counters.


In one method, the workload chunk size allotted to each thread is .xed.

this may not be      Work Power Processor Mapping Code Partitioning Partitioning 32 CMOS cores Homogeneous: CMOS  Equal Equal CMOS-Base      32 TFET cores Homogeneous: TFET Equal Equal TFET-Base Homogeneous: CMOS or TFET Equal Equal Hetero-Manual-Best 8 CMOS and 24 TFET cores  Heterogeneous: CMOS and TFET Dynamic Dynamic Hetero-Auto   Table 2: Evaluated multicore con.gurations.


The delay model also can be more complicated.

our methodology is generic in that it is applicable as long as the interconnect delay between two adjacent nodes is always smaller than any delays between non-adjacent nodes and d9,du are constants.


The replication or migration of shared data blocks at arbitrary locations on chip require the use of directory- or broadcast-based mechanisms for lookup and coherence enforcement, as each block is likely to have different placement requirements.

to date, there have been only few promising directions to provide fast lookup [31], while the area and latency overheads of directory-based schemes (Section 2.2) discourage their use, and broadcast-based mechanisms do not scale due to the bandwidth and power overheads of probing multiple cache slices per access.


C. Overlap reduction and .nal legalization After the rough .oorplanning stage, the modules are relatively uniformly distributed across the .xed die.

some overlaps between modules are often present after this stage.


Furthermore, it should be noted that the refreshing energy is less than the write energy; because for the write operation transfer energy is needed to bring in the data from memory controller unit (MMU) via the H-Tree bus.

the refreshing operation can be locally performed, and such transfer energy is not needed.


We use request success rate versus offered load5 as metric, since it has been reported in [8].

in [8], setup delay data is not reported.


It is worth noting that due to the higher hop counts, F2 BFLY has slightly higher packet latencies than Corona.

both networks have roughly the same saturation throughputs.


For a given raw signal X, they de.ne a compression algorithm to produce a smaller .le Y and also a decompression algorithm to reproduce the output signal Z.

due to information loss in the compression stage, the output Z is not the same as input X.


transfer data between neighbouring tiles and between tiles and the main memory.

dMA controllers do not provide any guarantees on their timing behaviour.


This technique, called power gating (PG), is a coarse-grained application of multi-threshold CMOS (MTCMOS) and widely used for reducing sub-threshold leakage current [8].

in a header-based PG design, the PMOS sleep transistors suffer continuous NBTI stress during active mode (sleep = 0 ) and age very rapidly.


In practice, boosted deci sion trees [13] where additional trees are built to better ex plain data that previous trees misclassi.ed is a good default choice.

models to capture speci.c interactions (eg.


In this model, the programmer declares atomicity boundaries (transactions), while the runtime system ensures a consistent ordering among concurrent reads and writes to the shared memory.

a typical software transactional memory (STM), an implementation of such a runtime system solely with software, tends to exhibit huge performance overhead.


As the heap gets tight, the duration in cycles for STW rises quickly.

when we obtain the physical time by dividing total duration in cycles by synthesized clock frequency, as shown in Figure 8(c), things become less cut and dried.


increased approximately proportionally to 1/VDD.

in the sub-threshold region, where VGS is smaller than VTH, gm of the MOSFET is expressed as W .


It is considered that the effectiveness with the priority values depends on a circuit structure.

it is worthwhile to use the priority values since the difference in CPU time is negligible.


Currently, eDRAMs are offeredby a number ofleadingASIC andfoundry vendors, such as IBM,TSMC,STandNEC.

eDRAMshave a memory retentionproblem: Thedata in each memory cell wears out over time and needs tobe refreshed periodically to avoid loss.


Traditionally, optimization targeted towards the total cell area for a semi-custom design does not consider the interconnect area.

since the DSM wirelength trends do not scale with feature sizes, cell area minimization can no longer guarantee overall block or chip area minimization.


Because only a single tile of a chip is .oorplanned, some nets that connect di.erent clusters will have .oating terminals that must be placed on one of the boundaries of the tile.

the placement of this terminal must lie adjacent to the placement of a corresponding terminal on the next cluster.


For instance, consider the impact the size of subroutine foo() has on spawn-target pair selection.

if foo(),together with blocks b, d, e,and x .t inside the instruction cache, then initiating a prefetch of block x starting at block a is e.ective, because the loop will likely iterate several times before the main thread branches from b to access x.if foo() together with of its callees (if any) require more instruction storage than the cache capacity, then there is no point in spawning a prefetch thread to target x from any block.


This means, that it is not possible to obtain the elapsed time e, which is required by the RecDEVS transition functions dext(s, x, e) and dcon(s, x, e) as stated in Equation 2.

there is a wide range of applications where the elapsed time is either not required, or it is only used to preserve the timeout of the originating state.


A whole class of applications anddesigns 20 that can make use of sub-threshold operation have been shown  in the literature [14]-[16]-[23].

due to very low per formance, low functional yield and very high performance/energy variabilityduetoparametric variation[8], sub-thresholdlogic ap plications in commercial products have been limited.


To deal with this situation, designers can rely on introducing buffers at the ATE interface solely to mitigate this problem.

with the increase of .it error rate and/or test data volume, the required buffer size increases dramatically and hence it is not a scalable solution.


EBS volumes are attached to every instance separately over the network and hence there is no sharing of disks or volumes.

our results show that there are certain spikes in the graphs which may be attributed to the network tra.c or the behavior of the hypervisor.


The EICE has been implemented in the many chips such as ARM7TDMI [1].

the architecture of EICE is fixed for fixed processor architecture and the fixed set of instructions.


6), there is only a single path to a particular HMC and thus, minimal routing is suf.cient.

4 with higher connectivity in memory-centric network, non-minimal 4Non-minimal routing can be bene.cial in the PCN for CPU-to-CPU communication.


it uses a di.erent encoding scheme as shown in Table 3 to achieve contain lookup capabilities.


Since the gate dominant curve is convex, combining it with one or more of the other effects curves may lead to a relative delay maxima somewhere between the two voltage extremes.

all the other curves are concave and roughly mirror the gate dominant curve such that this maxima will be less than a few percent higher than at either the lowest or highest voltage, and therefore insignificant.


The language is relatively domain speci.c and the underlying tool may be more powerful in the speci.c domain.

the language includes many of the programming constructs supported by the general purpose veri.cation languages, and we suspect that our experience is highly relevant to the general languages.


An intuitive approach is to use multiple processors to evaluate simultaneously happened events in parallel.

it has been proved that such parallelism is not sufficient to maintain a decent speed-up due to the following 2 reasons: 1) generally only a small percentage (e.g., ~1%) of all circuit elements have active events, and 2) not all elements with active events can be handled simultaneously because the logic dependency actually implies a partial ordering in which the events have to be processed.


In most cases, however, these implementations scarify part of the accuracy; quality reduction compared to the original implementation of the ADSW approach in [4] is ~ 4-5%.

the proposed stereo matching architecture implements the ADSW aggregation step in a different way; by smoothing the SCV with an edge-preserving filter, the GIF.


This way, PC allocator requests which may later have to be invalidated do nottake resourcesawayfrompacketswhich arede.nitelyeligible for chaining.

sub-optimal chaining decisions are still possible because only some of the lower-priority requestsmay actuallybecome eligible,but otherlower-priority requests may have been granted instead.


Compared to SMS and VWQ (results not shown), BuMP improves performance by 3% and 9%, on average, due to higher read coverage.

full-region hurts performance by 67% (up to 4x for Data Serving), due to oversaturation of memory bandwidth, highlighting the importance of avoiding bulk transfer operations upon accesses to low-density regions.


Also, e must be observable since we can restrict the inputs space of X to the observable space of Fc.

these two conditions must imply that we must have a satisfying assignment to CircuitConstrain by lemma 3.3.


The nanocodes can be implemented by logic and the RTL tools may be able to remove unused components.

if the program is large and/or reprogramming is needed, the nanocode must be placed in a RAM or ROM.


Figure 5 indicates that, the overall impact on system performance is an average IPC degradation of 7%.

while TFET caches su.er high performance penalties, they are also very energy e.cient.


INTRODUCTION the color assignment is usually done by applying a minimum As the technology advances, feature size of the chips con-spacing rule, and any features that are closer than ........ (the tinues to scale down.

advancements in lithography minimum spacing) will have to be assigned different colors.


Any block in L encounters at most one miss (the cold miss) every time when the program executes inside L. Proof: Since the miss distance of the underlying cache is X, after the cold miss of a block d, at least X other different blocks are needed for the next miss on d to happen.

this is impossible when the program executes inside the loop L since it does not contain enough blocks.


According to the dual-Vdd assignment results, the ratio between VddL row (cell) number and VddH row (cell) number should be set to 3:1.

the layout pattern constraint for placement increases critical path delay and we usually cannot achieve the ideal ratio.


Ef.ciency results range anywhere from 56% to upwards of 93%.

ultra-low voltage requirements have increased the dif.culty in designing ef.cient DC/DC converters.


Furthermore, when the fault rate is 30%, performance degradation in case of the nw scheme becomes 6.1%, on average.

our proposedscheme shows almost consistent performance results (of 0.9%difference) across two fault rate cases.


To understand these impacts and to develop ways to mitigate such effects, we must understand the urban environment on a .ne-grained level.

traditional .xed sensing systems are expensive to deploy and maintain.


concentration allows the two rows of wire bandwidth to be combined thus, resulting in a reduction of bandwidth per channel by only a factor of 2.

the generalized hypercube (Figure 12(c)) topology would increase the number of channels in the bisection of the network by a factor of 16, which would adversely impact the serialization latency and the overall latency of the network.


Sub-threshold circuit design is an appealing means to dramatically reduce this power consumption.

sub-threshold designs suffer from the drawback of being signi.cantly slower than traditional designs.


The problem with this approach is that it can only be applied to data sets that replicate a known distribution [2][3].

it has been recognized that the dynamic write margin does not fit the normal distribution [3][6].


During normal operation, any time that REQ (request) is raised, the register REG for a given stage is loaded into the 7b down counter.

tABLE I. SUMAMRY OF DTW BLOCKS AND ISPD12 BENCHMARKS  Property  Circuit DTW Blocks ISPD 2012 Benchmarks  DTW4 DTW6 DTW12 USB PCI DMA VGA Levels 10 28 192 10 3 2 6 Synchronous Cell Count 457 1145 5382 360 1606 13649 74885 Post-layout Area Overhead (%) 63 53 58 106 21 4.4 13 Throughput Delay Overhead (%) 9.8 7.7 7.8 12.6 17.4 6.7 2.5   further dynamic resiliency optimization is applied, as shown by the last part of Fig.


The authors propose Compound Access Scheduling so that the second access (for data) is guaranteed to get a row buffer hit.

the second access still incurs approximately half the latency of the .rst, so this design still incurs signi.cant TSL overhead.


Despite having settled the reliability model, both analyses are incomplete, in that the failure rate parameter is missing, which makes a precise, quantitative dependability target difficult to meet.

a reliability analysis is still valuable from a qualitative point of view, allowing a direct comparison of different systems.


The importance of CT converters is due to the inherent anti-aliasing .ltering, low-power and/or high bandwidth operation.

cT converters are sensitive Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.


The average circuit size reduction is 8.6% and the CPU time is 1453.1 seconds.

if we optimize these benchmarks by repeatedly using the resyn2 script 6 times resyn2 x6, the average circuit size reduction is only 4.3% with a CPU time of 157.1 seconds.


As far as we know, this is the only solution promoted by the provider to secure the client s data.

the solution s only concern is to protect the data, and no operations are possible on the data after it s encryption (including searching).


In an ideal case without delay variations, tDB is larger than tFB, because tDB - tFB equals to the delay of an inverter.

in reality with the large transistor delay variations at low VDD, tDB may be smaller than tFB and the write-error occurs.


The weights are a mean to smooth transitions between state space regions and allow contributions of closest models.

the weights computation should be simple, otherwise, the simulation time will increase extensively without any gain in terms of accuracy.


In the steady-state formulation, each processor is assigned a constant frequency and voltage at all time instances.

many MPSoCs have the capability of utilizing DVFS, where the frequency and voltage of operation of the processors can be varied over time, so that the system performance, power consumption and temperature distribution can be highly optimized.


Typically, the aim of the designer is to create a clock tree with zero skew, referred to as a zero-skew clock tree.

in highperformance design, clock skew is sometimes intentionally introduced by the designer to accommodate unbalanced combinational logic delays in the circuit, referred to as a non-zero skew clock tree.


It is obvious that the potential replacement of this .nal block can cause a greater vertical leftover.

on the other hand the decrease in the horizontal leftover can make up for this.


Massachusetts Institute of Technology, MA ABSTRACT Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly-scaled technology nodes.

carbon nanotubes (CNTs) are inherently subject to variations that reduce circuit yield, increase susceptibility to noise, and severely degrade their anticipated energy and speed benefits.


This is a reasonable assumption because the global grid is of a coarse granularity and it is implemented in the top level metal.

in our implementation we still apply the multi-grid method to speed up the simulation procedure.


Further reduction in buffer costs is one of the most benefits of this global view.

due to the large number of paths, the run time of these algorithms is usually high.


Experiments show that increasing the size of the write buffer could generally increase the page hit rate consistently.

increasing the page hit rate may or may not lead to significant reduction in power consumption.


Hence, in real-life problems after constant propagation there always remains some logic that separates the arithmetic parts from each other.

it turns out that this logic is transparent, i.e., a SAT algorithm can easily prove that equivalences between the outputs of one arithmetic block and the inputs of some other arithmetic block exist or that certain signals are constant.


4, but also reveals that CPI is the dominant factor on the scalability of power network solver on multi-core.

it provides an emphasis on the importance of CPI impacts.


For structural correlations, the covariance of two paths equals the sum of the variances of all gate and interconnect delays, which are shared by both paths.

depending on the particular circuit model, the estimation of spatial correlations can be signi.cantly more dif.cult and is beyond the scope of this paper.


A Wear-Leveling-Aware Dynamic Stack for PCM Memory in Embedded Systems Qingan Li* , Yanxiang He * , Yong Chen * , Chun Jason Xue , Nan Jiang * , and Chao Xu * * School of Computer Science, Wuhan University, China Department of Computer Science, City University of Hong Kong, Hong Kong ww345ww@gmail.com, {yxhe,cyong}@whu.edu.cn, jasonxue@cityu.edu.hk, {nanjiang,xuch}@whu.edu.cn Abstract Phase Change Memory (PCM) is a promising DRAM replacement in embedded systems due to its attractive characteristics such as extremely low leakage power, high storage density and good scalability.

pCM s low endurance constrains its practical applications.


GPGPUs features automated hardware-assisted low-latency programming of DMA transfers when coalesced threads are intercepted [14].

coalescence is not always feasible due to divergence of threads.


As pointed out in [8], a signi.cant portion of the total execution time of min-area retiming is spent on computing the clocking constraints.

solving the minimum-cost .ow problem is known to be quite ef.cient.


For a symmetric placement, it is better that the two unit capacitors in a pair belong to the same capacitor.

a capacitor may comprise an odd number of unit capacitors, and it is inevitable to leave one unit capacitor while pairing the unit capacitors.


It requires two different orientations, a 90 degree and a 45 degree cell structure.

manufacturing nano-scale cells with two orientations is a challenging task.


As technology advances, less voltage is required to drive a single cell.

driving voltage transmitted to a cell may not be suf.cient due to unacceptable voltage drop.


3.5.2 Router Merging: Stage 2 Both the topology synthesis step (via router duplication) and router merging stage 1 aim to avoid interference between transactions belonging to different traces.

it must be noted that interference between two transactions could occur as a consequence of the problem specification itself.


However, the supply noises increase slightly.

strategy 2 (LDs, GDs, and RDs) reduces both rush current and switching noises by 10% with similar leakage saving of Strategy 1.


Designers treat this component of variations as correlated random variables during analysis and optimization.

some systematic component of intradie variations, such as Chemical Mechanical Polishing (CMP) and Optical Proximity Correction (OPC) effects, can be directly accounted for during timing or power analysis if  Figure 2.


For the case of a 266 MHz clock with a triangular modulation and with a 2.5% frequency deviation, around 13 dB attenuation is measured with this technique [4].

the previous work ignores the potential of clock modulation on reducing the ground bounce, which is the subject of this paper.


This is a consequence of these cells not presenting repeated literals.

when instantiated in a circuit, these cells may have logically equivalent signals connected to different cell inputs and as a consequence some instances may not respect the lower bounds.


All predicates in the backward slices of instructions in the decoupled loops that are not replicated must be communicated.

predicates are not sent directly to the instruction fetch unit of the other core.


It generates interconnect information very close to the .nal routing implementation and can be used for accurate estimation of interconnect topology, wirelength, delay, congestion, bu.ering solution, etc.

due to the high runtime of the traditional global routers, it is impractical to perform global routing repeatedly during placement.


Thus, no energy is spent in bitlines, sense amps and the associated multiplexers.

it burns more energy on writes than COR since it performs in addition to the write a normal read that includes the code bits and ECC logic.


= 362,880 VIA characters and 362,880×9×9 ~ 3.0×107 grids of stencil area, which exceeds the 3.6×106 limit.

if we adopt2-stepswitchingwith6!=720flexibilityinthesecondVIAlayer,therequiredflexibilityforthefirstVIAlayeris9!/6!=540,resulting in the total VIA character number of 720+540 = 1260.


The breakaway pins leave an open space wide at the bottom.

inside the array the channels connected to the opening are still limited by the existing pins.


Homogeneous WSNs contain only one type of devices, the sensor nodes.

heterogeneous WSNs contain devices of different capabilities.


Encounter True-Time Delay Test Tool TM[6] is one such available commercial ATPG tool that uses actual design timing information for ATPG.

most of the widely used commercial ATPG tools are still timing unaware and generate test patterns based on the ease of .nding an affected path, instead of a least slack path.


when the same test is applied at faster-than-at-speed (6ns), then the defect is detected through .ip .op FF2 (shown in Figure 1.1(b)).


Measuring the architecture-independent characteristics may be achieved by exploiting the notion of data similarity (e.g., instruction level parallelism, data locality).

it is not straightforward to estimate the performance of a particular architecture-independent enhancement; therefore, we do not consider them here.


MULTI-CHANNEL SSD SCALABILITY During last two decades, the improvements in .ash memory technology have led to di.erent e.ects on storage devices: bit density increases, but other important features including performance, lifetime, and energy are drastically reduced.

the SSD vendors strive to provide higher capacity products while keeping their performance at a reasonable level [20, 49].


Since mem2 is in the RON state, the voltage drop across mem2 has a low value and the voltage at node Y (VY) is approximately equal to VDD.


7), trying to improve prediction accuracy with extra hardware is not cost-effective.

for the second limitation, we intend to introduce warp throttling to control the amount of requests that are allowed to be issued to the memory subsystem.


As discussed in Section 3.2, we try to maintain a low signal slew in our clock tree.

the number of bu.er levels B should not be increased while trying to maintain a low slew.


The time reported for via minimization is not the time taken by the entire binary search, but rather the time for the .nal SAT solve with the via bound equal to the minimum possible.

it can be shown that with a few processors searching in parallel for the minimum number of vias possible, the expected total runtime is a small factor larger than the average SAT solve time Tavg (for example, with k = 3 processors the expected runtime is less than 4Tavg ).


Decoupling for Power Gating: Sources of Power Noise and Design Strategies Tong XuPeng LiBoyuan Yan Department of ECE Department of ECE Department of ECE Texas A&M University Texas A&M University Texas A&M University College Station, Texas 77843 College Station, Texas 77843 College Station, Texas 77843 xutong85@tamu.edu pli@tamu.edu byan@tamu.edu ABSTRACT Power gating is essential for controlling leakage power dissipation of modern chip designs.

power gating introduces unique power delivery integrity issues and tradeo.s between switching and rush current (wake-up) supply noises.


All necessary discrepant terms to block f1 will be those pairs with observability conditions at the sensitive cofactor.

the observability conditions at node gd are the same for both faults f1 and f2.


In a bandpass filter the phase shift between the input signal and output of the filter at the center frequency is zero.

in the case of lowpass or highpass fil ter there is always a 900 phase shift between input and output signals at the center frequency.


However, this causes an increase in the size and weight, not suitable for handheld devices.

low input voltage based DC-DC boost converter is better option due to its minimum requirement on the battery cells.


For instance, if a window happens to enclose a point common to all boxes associated with a node, we know that each box in the set will overlap the window.

if the global bounding box of the entire set happens to be disjoint adaptive quadtree skipping underpopulated levels WW (a) no oblong children yet (b) oblong children of N dark nodes require inspection light nodes are contained by W white nodes are disjoint of W Figure 2: Oblong nodes are bene.cial of the window, none of the boxes will overlap it.


If all paths in a circuit are considered, the critical path coverage would be 1.

the number of critical paths could potentially be exponential in terms of the circuit size.


In Section VII-B, our modeling treated a fault group with overlapping SDC ACE and DUE ACE as SDC ACE because we could not guarantee detection of the DUE before the SDC propagated to program output.

a GPU reads and writes registers from multiple threads simultaneously.


Robust tests prohibit the reconvergence of fault effects in this case and remain valid for transition faults along the paths.

they only exist for a small number of path delay faults.


The same holds for very large search-space sizes due to the resulting lengthy test sequences.

the proposed metric's values are higher in the former than in the latter case, as a seeds result of the greater weight of the ratio in relation max _seeds (1) [k = 2].


Many low power bus encoding techniques have also been proposed and can be readily used on network links.

these encoding techniques may not be readily applied to router components such as buffers and crossbars whose wire lengths are short relative to links, and thus unable to offset the overhead of encoding/decoding circuitry.


This is in contrast with the BILP solution.

it needs a subsequent step to convert .nal results to binary values.


Traditional design strategies increase the number of HDD spindles to boost the performance of a storage system.

with single-disk capacity growing much faster than the performance nowadays, adding HDDs for performance becomes inappropriate because additional spindles mean more power, more space, more cooling, and under-utilized capacity.


Text, in conventional wikis, can be presented in parallel so that by scanning through the document users can quickly locate the unit of editing (UoE).

audio as a temporal medium, cannot be concurrently presented by auditory modality.


The NI then extracts the user data and sends to the receiving resource, main memory in this example.

the extracted user data might not be able to be sent right away since a packet only contains 32 bits of user data.


Since the energy consumption improves as the number of wafers is increased, the die area can be scaled in a proportional fashion so as to maintain a constant average temperature.

if it is desired not to sacri.ce silicon for thermal purposes, the runaway thermal behavior of Figure 13 must be controlled by advanced packaging and cooling techniques.


Hierarchical solutions to the store queue design [1] ensure the latency tolerant processor meets cycle time constraints.

these hierarchical structures occupy significant area and display power inefficiencies.


A.2 Hill-Climbing Algorithm The previous heuristic yields a set ofpi values that closely approximate the behavior of the TCP equation.

because the analysis is clearly only approximate, we now describe an alternative approach that allows us to find a set of pi values that provide a closer match, if this is desired, by applying a simple hill-climbing algorithm.


[6] present a genetic algorithm for partial RTR that considers columnar task placement.

their approach does not consider prefetch or the single recon.guration controller bottleneck.


DBAR considers the congestion value of the nodes along the X and Y directions that reside in the minimal path to the destination node.

if the congestion conditions of both nodes 11 and 14 are zero or one, the congestion status of nodes 7, and 3 in the Y direction are compared with the value of zero in the X direction, thereby the packet is probably sent to the node 14.


These long equalized links can be used as point-to-point wires between pairs of cores, but as there is insu.cient on-die wiring to support dedicated links between all pairs of cores, equalized links map more readily to indirect, multi-stage NoC topologies with long global links.

as we mentioned earlier, such topologies do not leverage application locality, turning all traf.c into cross-die global traversals, which leads to high NoC latency and energy overheads.


Other components, such as, the VCMs and their motor drivers, head suspensions, pivot bearings, and head preampli.ers are expected to constitute only a small part of the overallcost of anintra-diskparalleldrive.

the overarchingquestionis whetherthisincreasedcost(and its correspondinghigher sellingprice)wouldbe worth the investment for the eventual customer of the product.


Note that the unfiltered HOB technique (the baseline) incurs no power overhead for the error masking filter.

the proposed method requires additional filter power which was included in our results.


Moreover, the test was required to be very short, to avoid heating effects.

stress tests intentionally exploit overheating and are designed to work with different architectures.


4.3 Low-Swing Signaling Low-swing signaling has demonstrated substantial energygains in domains such as off-chip interconnects and SRAMs.

in NoCs, there are few chip prototypes employing low-swing signaling [2, 14].


Since executing applications may not be tolerant to even a single bit error, caches must be operated at a high Vdd with a very low probability of failure leading to high energy consumption.

by exploiting mechanisms that allow a cache to become inherently resilient to large number of cell failures, we can operate the cache at a lower Vdd and thus gain significant energy savings.


This usually requires extensive simulations of the whole circuit.

sPICE-level simulation of large circuits is inappropriate due to its extremely expensive computational cost.


The propagation of signals in the circuit can be modeled by using a Colored Petri net (CPN) and de.ning two different tokens labeled one and zero , to specify the two different states of a logic signal.

the CPNs do not allow the modeling of inertial gate delays and interconnect delays in a circuit.


A typical value to include is a timestamp, to prevent replay attacks.

this requires secure clock synchronization of A and B, which is expensive (see [24] for a security protocol to achieve this).


The obvious effect is any change in performance from the activation of the new behavior.

the time at which the activation occurs, also affects the usable lifetime of the battery cell, as a result of non-linearities in the battery electro-chemical characteristics, particularly, if the activation might cause a temporary or permanent change in the current discharge pro.le.


Simulation based approaches have also been proposed to estimate either the maximum peak or RMS value of the supply current [6].

those techniques require not only an extensive simulation time due to the large number of input patterns but also the produced vectors are still large to be used for an exhaustive optimization.


As for short defects, it is well-known that supply current tests like IDDQ test are very effective and useful, since short defects are modeled as bridging faults in logic circuits and bridging faults are very difficult to be detected by measuring logic values of the primary output terminals.

it is very difficult to detect open defects by measuring supply current of ICs.


For video frames, a small inter-arrival time standard deviation is acceptable, since this corresponds to a small lost, not perceptible by the user.

to meet hard-real time constraints, this performance figure must be zero.


The proposed BDD-based symbolic error manipulation algorithm succeeds in effectively capturing such logical masking [3][4].

the formation and propagation of the pulses symbolically is intrinsically linked in the algorithm with the accurate characterization of cell electrical properties, contained in the library.


In theory, .V is given by the difference of reference voltages Vref1 and Vref2.

due to parasitic, comparator offset, gain, settling time and device diffusion, .V is larger than Vref1-Vref2.


With the CTR mode of operation, AES can be easily implemented in a parallel manner (section 4), and di.erent parts of the cleartext message are processed on di.erent GPU processing units.

since each round in the algorithm depends on the previous round result, we cannot go any further and introduce a .ner grain parallelism.


Distributed shared memory, on the other hand, offers an easy to use abstraction of the underlying distributed memory and hides several protocol and transport level details from the developer.

as would be expected from a generic implementation, it suffers from lack of scalability and inadequate performance due to its inability to exploit application level knowledge.


Since for digital circuits, an RTL representation, or even just a .nite state machine model, can describe circuit behaviors well enough, it is preferable to use these high-level models during simulations of the whole system.

the ideal high-level block may not exhibit correct circuit behaviors in many situations.


The cool spot experiences higher von Mises stress, since the temperature difference from the stress free temperature, 275.C in our case, is larger in the cool spot than in the hot spot.

since the maximum temperature difference across the die is only 20.C, the impact of an operating temperature on the TSV reliability across the die is not signi.cant.


The detection of S-CDC faults requires fault excitation and propagation through paths from the sender domain.

this requirement is not always met when TDF ATPG tools are used for test generation.


Low power designs are especially vulnerable as low Vth devices exhibit larger sensitivity to variation.

high performance parts are vulnerable as they tend to have highest leakage power leading to large yield loss in the high performance bin [11].


This may be a significant overhead for accesses that would have hit in the L1.

such an access is more likely to first miss in the L1 (after all, it is a shared variable), in which case the overhead becomes insignificant.


8.3 Alternative Data Sets and Interactive Simulations The applications presented in this paper illustrate how Phoxel-Space can be used to explore static 3-dimensional data.

there is an increasing number of dynamic dataset sources available such as brain activity maps, CFD simulations, and astrophysical evolution models.


TDM is very effective for single-site testing as it minimizes the test time per chip.

multi-site testing is widely employed in large production lines as it is more ef.cient than single-site testing [22], [23], [26].


The delays computed by Synopsys Design Compiler (as in Figure 7b) are worst-case values for a particular RAC design.

because programming is done in advance, the switching activity of some arithmetic or logic components will not a.ect the outputs.


GPP1,1 is mapped to software same as in Mapping A, and shows the same average performance.

it shows a higher variability and standard deviation in this experiment because the number of events is much lower.


The main dif.culty arises from the fact that we only have access to the oracle to solve the Restricted Problem for the individual components.

we can overcome this dif.culty as follows: at every step we identify the interval at the system-level where the approximation error is maximum.


Increasing the number of WIs improves the connectivity of the network as they establish one-hop shortcuts.

the wireless medium is shared among all the WIs and hence, as the number of WIs increases beyond a certain limit, performance starts to degrade due to the large token returning period [10].


Similar to the line representation, dependency information is not easily visible.

vertical and logarithmic trends clearly delimit events starting or ending simultaneously.


This additional interactive training could be performed using any sheet music, but we prefer to use musical scales and exercises as they are traditionally a fundamental step in instrumental practice; as a musician, it feels natural to hear (and correct) mistakes in timbre by practicing scales.

there are also solid technical reasons to practice scales before attempting more complicated music: it allows us to pinpoint and .x problems in isolation.


Our results show that as the amount of process variation in the system increases, the gap between LTMax and random schemes widens in general as a percentage of lifetime savings.

on the absolute time scale, slight process variations (those within ±5%) yield the most savings of up to two years over the worst and a year over the average cases, under the heavy workload we use.


Prediction in the MDCT domain as suggested in [9] is also computationally expensive.

if we perform the error concealment operation directly in the Huffman coded domain, which we define as the compressed domain, we need only a small fraction of memory (~418 bytes in our example) to store an MP3 frame in comparison with the much larger amount (18432 bytes) for a single frame in the MDCT domain approach.


Thus for the commercial workloads, we measured transactions completed and for the scienti.c workloads, runs were completed after the cache warm-up period indicated in Table 5.

for the SpecOMP workloads using the reference input sets, runs were too long to be completed in a reasonable amount of time.


The sub-threshold current changes in an exponential manner with respect to Vdd and Vth, and hence the regression to polynomials is not appropriate.

generally speaking, in those combina tions, gate delay is unacceptably large.


CELL SHIFTING Global Optimization gives a placement which minimizes the quadratic objective function.

it does not consider the overlap among cells.


Weights wx attached to nodes of the CCG represent a function s WCET for a particular context, and edge weights w(x,y) computed by aiT represent how many times y is called by x in a context.

the WC-path required for cache contents selection can not be computed using the CCG, because information about the control .ow within functions is hidden in the CCG.


is de.ned simply as max{2, maxi ai/ai+1}.

a few simple preprocessing steps can usually be used to reduce this value signi.cantly.


While LID will have a cost in area and frequency compared to a perfectly pipelined non-LI system, as design sizes continue to grow and CAD run time for each design iteration increases, the design costs of such systems become large enough to make LID attractive at the system level to interconnect large modules.

to fully exploit the promise and bene.ts of LID it must be integrated into CAD .ows and exploited by CAD tools to improve designer productivity and design quality.


Often, transformational derivation is also used for postveri.cation, e. g. , for the veri.cation of the scheduling step [5].

the transformational synthesis approach succeeds only if the transformations actually do not change the behavior of the circuit.


978-3-9815370-2-4/DATE14/&#169;2014 EDAA Certain parts of the standard SRAMs are alreaady optimized to avoid full swing operation limiting the bennefit of voltage reduction in such cases.

other portionns of the memory still feature full-swing dynamic and static operaation that benefits from power reduction with supply voltage.


In most existing work, they are considered separately using dedicated techniques.

it is particularly important to consider both types of faults in an uni.ed manner, in order to achieve the most e.cient and reliable design.


Historically, power dissipation in CMOS circuits has primarily been the result of the charging and discharging of load capacitances, referred to as dynamic power dissipation.

as we begin to enter the realm of sub-100 nm technology, static power consumption is expected to become much more important.


This simplifies the technology realization drastically and enables even more regularity.

the polarity selection comes at the cost of extra routing.


On-chip SRAM peripherals multiple sleep mode normalized leakage power savings 4.1 Reducing Leakage In On-Chip SRAM Peripherals To maximize the leakage reduction in each of the on-chip SRAM memories peripherals one solution would be to always put them into ultra low power mode.

this requires wakeup of their peripheral circuits before accessing them adding 3 cycles to their access latency and significantly reducing performance.


The wire resistance is determined by the wire area.

inductance is not proportional to the wire area.


Sora has put substantial e.ort into designing a C++ template library that eases the programming pain.

use of templates imposes several limitations, in particular on state sharing and dynamic recon.gurability of the data.ow graphs.


Figure5showsmultiplierperformanevs.supplyvoltage forbothtehnologies.Therangeofpointsateahvalue ofVddtoombinationsof(Vdd.V orrespondsvariousVwell) andVfromtoStandard Vwellranging(0,0)(.4,.4).CMOS runsat136MHzatVdd=3.3V.LowthresholdCMOSruns at188MHzatVdd=2.0V,136MHzatVdd=1.3Vandat 40MHzatVdd=0.4V.

inlowthresholdCMOS,thekeytoahieveminimumpower attherequiredperformaneistohoosetheoptimumra 40 20 0 0 0.511.522.53 3.5 V [V] dd Figure5:Multiplierfrequenyvs.supplyvoltage forstandardandlow-Vihimplementation 0.4 0.35 0.3  0.25 Optimum P/P leakagetotal 0.2 0.15 0.1 0.05 0 Frequency [MHz]Frequency [MHz] Figure6:Optimumsupplyandwellvoltagesvs.fre-Figure7:Optimumratioofleakagepowertototal quenyforlow-Vihimplementation powervs.frequenyforlow-Vihimplementation  tioofleakagepowertototalpower.Forexample,forthe multipliertorunat40MHz,oneanhoosetheasupply voltagerangingfrom0.37to0.6V.Althoughalowersupply voltagemayseemadvantageous,itrequiresverylowthresh-oldswhihinturnmakesleakagepowertoolarge.Figure6 showsthesupplyandwellvoltageswhihresultinminimum totalpoweratthegivenfrequeny.Valuesareguaranteed tobeoptimumonlyinthefrequenyrangebetween12and 171MHz.Namely,athighestfrequeniesitismoreeÆient torunathighersupplyandthresholdvoltages.sinewelimitedoursupplyvoltageto2V,theonlywayto ahievethehighestfrequeniesistorunatmaximumsupply voltageandlowestthresholds.


So far, we have discussed the pro.le for two simulations that use fourth order interpolation and have particular FFT sizes.

the interpolation order and the size of the FFTs used in the simulation can signi.cantly impact the application pro.le.


Moreover, the latch in Figure 2 is often shared with an existing scan latch/.ip-.op in the datapath, which further reduces the test cost.

any two Figure 2: A Mux-based Scan C-Element multiplexer-based scan elements connected in series cannot capture the circuit response at the same time, hence they cannot be enabled at the same time and are, thus, connected to different scan enable signals.


This signi.cant storage thus drastically degrades decompression speed.

the pure XOR network-based technique requires no on-chip storage at all, while the hybrid compression technique only needs to use 2.3% of the original code size in the on-chip LUT.


Therefore, the test set for type-1 fault must include any one from the above pair.

only the first vector can test the type-2 fault (like line 3 stuck-at-1 as in Fig.


Huh and co-authors demonstrate that the latency penalty of false sharing can be eliminated through coherence decoupling speculative use of incoherent data [15].

even if false sharing is eliminated, true sharing and replacement misses nonetheless result in nearly double the L2 miss rate of the oracle opportunity at 8kB blocks.


In [3], 3D stacking STT-RAM is used to build a hybrid cache system with SRAM.

none of the prior works have considered dynamic powering on/off of SRAM and NVM arrays to adapt to varied workloads.


Because the room size of the package we have is much bigger than the die size, the final operating frequency is shifted to 1.6GHz due to the huge parasitics of the package.

it is possible to the shift the operating frequency back to 2GHz by adding additional shunt capacitor and resistor on input and output terminals respectively.


They had to press a button with their finger if the series of letters represented a word.

they had to withdraw their finger in case of a non-word.


Since the leakage current through a sleep transistor is proportional to the size of the sleep transistor in standby mode, the size of sleep transistor should be as small as possible.

given switching current in active mode, the voltage drop is inversely proportional to the size of sleep transistor.


Self-Calibration Technique for Reduction of Hold Failures in Low-Power Nano-scaled SRAM Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, and, Kaushik Roy School of Electrical and Computer Engineering, Purdue University, IN, USA {ghosh3, sm, keejong, kaushik}@ecn.purdue.edu ABSTRACT Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays.

due to process variation, a higher source voltage can significantly increase data flipping in standby mode (Hold Failures) resulting in faulty memories.


The 2nd level DTLB on the Itanium 2 processor contains 128 entries, covering only a megabyte of virtual space when using 8KB virtual pages.

the processor supports up to a 4GB virtual page, and most operating systems support large virtual page allocation (1MB+) in both memory management APIs, static/global data allocation, and instruction page allocation.


At its most basic level, it measures the relative performance of single devices on important computational kernels.

data collected from SHOC can make an important contribution to far more sophisticated analyses.


Westressthatthese results are preliminary, and we do not expect perfect accuracy in actual use.

the use of slack lets us .nd the mostpromisinggestures.


By utilizing virtual channel .ow control (Figure 14(b)), buffers are partitioned into multiple VCs, which allow packets to pass blocked packets.

with the 100 use of high-radix routers and the .attened butter.y topology, the additional wire resources available can be used to over-80 come the blocking that can occur as shown in Figure 14(c).


However, on the one hand, this situation is a result of human factors that are out of the scope of our model and therefore is not related to temporal constraints.

this situation can be avoided somewhat by the condition of an obligation.


Integrated resistors are limited to tenths of MO.

components in these ranges of value already represent a signi.cant cost in silicon area.


Unfortunately, the simulation speeds of this detailed microarchitectural framework are slow; hence we cannot use it to run full Linux distributions with the memory allocation behavior necessary to study CoLT on suf.ciently long-running, large-data applications.

while this simulator does not maintain virtualto-physical address translations, it does observe the performance effects of TLB misses by tracking the allocated virtual pages.


The distribution of a sum of lognormals is not known to have a close form in general.

one can compute its mean and variance by E(S)= u1 (4) var(S)= u2 - u12 (5) where u1 and u2 are the .rst and the second moments de.ned and computed as N X u1 = E(S)= E(Ik) (6) k=1 NN XX u2 = E(S2)= E(IkIl) k=1 l=1 NN XX = (Cov(Ik,Il)+ E(Ik)E(Il)) (7) k=1 l=1 Once the mean and variance (and correspondingly the two moments) are obtained, Wilkinson s method [11, 12] can be adopted 1The detail of this is not the primary concern in this paper.


At last, many systems such as communication devices are very sensitive to noise.

a conventional pulse-width modulation (PWM) switching power converter generates a series of large noise tones at the switching frequency and its harmonics.


It is possible to develop vectorless veri.cation techniques that take this into account [3].

in most cases, and because of the near-symmetry of the two portions of the grid, a virtual ground node is assumed to represent the half-way point between the two.


This shows a clear trend of improved parallelism in each case.

in a very deep circuits where there is not much parallelism, our heuristics make unnecessary attempts to improve parallelism, therefore the reachability analysis gets worse as compared to the standard VIS or the standard POBDD-based reachability analysis.


Then, the proposed modeling method provides a convenient tool to estimate the expected mismatch.

analyzing only 5 combinations of sLER and .LER is far from enough for a real mismatch analysis.


Software approaches are always more .exible compared to hardware approaches.

the error coverage can be limited by the granularity of programmers (or compiler s) code insertion.


The main contributions of energy reduction are from: 1) reduced RF access energy; 2) reduced datapath and control path overhead due to merged operations.

the SFU-32 increases the average core energy by 0.3%.


To convert a polygon to rectangles, we can adopt a scan-line algorithm [6] to decompose the polygon to a set of abutted rectangles.

it is not trivial to convert polygons (such as polysilicon, metal) to sticks.


For example, for 5EC6ED code based on 16B data word, almost 25% of the code word is ECC.

for a 4KB word, the number of check bits doubles, but the overhead reduces to 0.3%.


The global view enables better decisions and hence better schedules in some cases compared to the local decisions made by FLASH.

since GRP is done as a pre-scheduling phase, it is not adaptive when the actual scheduler decisions differ from the suggested resource preferences.


Another option is to record all signal activity at the microarchitectural blocks I/O and cross-validate it against a reference model maintained in software after the simulation completes.

that solution requires recording of a large number of bits in each cycle, leading to an unacceptable slowdown during simulation.


It should be noticed that sometimes the number of thermal sensors are limited due to the design constraint.

it is also possible that the power errors among functional blocks are highly independent and as a result, the clustering correlation algorithm will generate a large number of clusters.


In principle, we could achieve .ne-grained monitoring by simply attaching a metering device to every end load.

this brute-force solution is impractical given the prohibitive costs of the metering devices, the installation, and the maintenance in large scale.


For this reason, we store the checkpoint data in memory.

since we target a broad range of errors, we must assume that the contents of main memory can be damaged and even a node can be lost.


To implement this CAM in an ordinary RAM we would require 2^32 (= 4,294,967,296) 5-bit words of RAM.

in this example, only 32 of the 2^32 words would contain the "ADDRESS" (5 bit) contents.


To be fair, these overall results show not just the bene.ts of increased memory parallelism, but also increased operator parallelism resulting from both loop unrolling and custom data layout.

operator parallelism often depends on exploiting memory parallelism, so that serialization of memory accesses does not inhibit operator parallelism.


It grants higher priority to the requests which hit an open row in the DRAM, and save the time spent on precharge and activation to open a new row.

its impact on alleviating the request congestion is ambiguous since a limited number of requests (e.g.


This is because of using dual-rail than the similar one in the ASPIN design since it has ex data encoding in asynchronous router, the area of the bu.er, tra transistors to prevent Metastability.

reported crossbar switch and speci.cally routing unit is about two throughput of Asynchronous to Synchronous interface in the times larger in asynchronous router than in synchronous proposed design is less than similar component of ASPIN ar router.


For example, the number of multi-node relations hARhh around an OR gate Ywith ninputs , 2, ..., ncan be as wnGlhARRw hlnXwnGlhw hRnn wnGlhw hlnXwnGn hwnGlhenRh large as 2... nY, where hn represents the number of single-node implications of the node .

since the primary multi-node relation for the OR gate is suf.cient to deduce all such multi-node relations, they do not help in increasing the necessary assignments for any fault.


Closed-form expressions by using 2p and 4p configurations have been developed in [9] and [10], respectively.

the quality of their analysis and optimization tools degrades when using linear equations to model the nonlinear behavior of the drivers.


This approach provides the system integrator high .exibility in terms of test resource partitioning, and the core provider the chance to .ne-tune the converter design with respect to the core test needs.

it also results in high test hardware overhead.


As a result, missing stores incur the invalidation penalty before they can leave the store queue.

most missing stores access private data that are repeatedly brought into the L2 cache, modified and then evicted (due to capacity constraints).


4(e), by using CWS the energy consumption was reduced by up to 23% of that by using the other congestion-aware algorithms on a NoC with a size varying from 4×4 to 8×8.

when the size of NoC increases, the improvement of energy consumption using the the CWS was thus lowered.


In the best case, if the block counter is initially 0, invalidating cache lines is not necessary.

searching all sets in the data cache has to be performed when the block counter is saturated.


The functionalities provided by the TPM allow to securely bind (sensitive) data to a speci.c platform meaning that the data is only accessible when the underlying platform has the valid and desired con.guration.

there are several issues to deal with: .rst, actual TPM chips are currently mainly available for workstations and servers and rather for speci.c domain applications, in particular barely not for embedded systems.1 Second, TPM speci.cations are continuously growing in size and complexity, and there is still no published analysis on the minimal TPM functionalities that are practically needed.


Other spikes may be caused by people leaning forward or rolling their seats.

7 of the 396 range measurements are unrealistic.


This tells us that the artifact labeled as very soft should have been designed a little bit softer, if we wanted to achieve this linear relationship.

this does not significantly influence the outcome of this study.


For such timing-critical connections, the principal concern should be to route the connections using the fastest routing resources, with less focus on the demand for such resources by other nets.

if the criticality of the connection being routed is low (i.e.


Our implementation of this method is discussed in Section 4.

if these program fragments are not simple enough, it applies the rules shown in Table 1(b) to simplify the programs recursively till the programs are simple enough to be analyzed symbolically.


A solution is feasible if there are enough spaces on both sides of the pair to place all pins of the related link.

if all pins of a link cannot be placed on a side because of already placed pins of other links or because of lacking space, the solution is not feasible and we have to select the next pair.


On many existing architectures, changing the rounding mode is so costly that performance degrades dramatically.

on the Itanium architecture, one can simply set up two status .elds to have di.erent rounding directions and use whichever is desired on each instruction.


With the help of suspendable multi-level memristor writes, long-latency non-critical memristor accesses typically do not slow down critical directory operations.

this is based on the assumption that there is enough time when the RAM is not performing critical reads to .t in non-critical, long-latency writes.


Transient faults mostly occur due to cosmic radiations, alpha particle strikes and electromagnetic interference.

electromigration, gate-oxide breakdown and other manufacturing imperfections have been cited as the major sources of permanent faults.


We can see from this plot that as the PUR transistor (initially on) gets stronger, the TCRIT value increases as expected.

as the PUL transistor (initially off) gets stronger, the TCRIT value decreases.


The authors who proposed this approach evaluate the NCID architecture supporting a selective allocation policy to address transient data, and compare it with a conventional cache with a bimodal insertion policy [26] in terms of miss rate reduction.

nCID with selective allocation could also be used to reduce the data array size maintaining performance.


Moreover, shifting the address space from one billion IPs to at least one trillion content names [7] causes a neat increase of the routing state to be stored at content routers.

allowing routers to serve content from a local cache can potentially alleviate the frequency of forwarding operations.


GNURadio [1] is a purely software based implementation of SDR platform, and efforts [42] have been made to use it as a software de.ned cognitive radio.

large processing delays [20] in the processing pipeline of GNURadio platform is a fundamental limitation in implementing a radio chain in real time.


Thus the probability that a die fails because of a SA with an offset <= 3s from the mean remains under 2%.

(A) if the SA's offset is 3.5s from the mean, then almost half of all possibilities for IREADm:1 fail the yield criterion.


THEORETICAL BACKGROUND 2.1 Problem description One of the main strengths of theoretical mathematics is writing symbolic expressions or formal equations which abstract the essence of a problem and reveal its underlying structure.

this same strength carries with it an inherent weakness: the more general and formal its language, the less is theory ready to provide a numerical solution in a particular application [1].


FRAMEWORK As explained in Section 2, to improve the small delay defect screening capability of a test pattern, the timing can be adjusted such that the path delay affected by a pattern is relatively close to the clock period (pattern slack near zero).

the performance degradation due to IR-drop effect also needs to be considered to avoid any good chips failing the test.


Floorplacement appears promising for SoC layout because of its high capacity and the ability to pack blocks.

as our experiments demonstrate, existing tools for .oorplacement are fragile  on many instances we tried they fail, or produce remarkably poor placements.


The accuracy of this sensitization criterion is determined by how close the estimated delay is against the actual delay.

an exact sensitization criterion can exactly estimate the same delay as the exhaustive timing simulation approach does [8].


by capturing a speci.c circuit architecture in schematic form.

instead of entering a sized schematic, the designer creates a parametric schematic where only the connectivity among circuit devices is fully speci.ed, while neither device sizes nor process information are provided.


This mix of control-data .ow limits the effectiveness of common sub-expression elimination (CSE), when applied as a pass before scheduling.

the movement and duplication of operations caused by speculative code motions frequently creates new opportunities for applying transformations such as CSE and copy propagation.


Because there are no multipliers, any sort of LinearCongruentialGeneratororMultiplyRecursive Generator is impossible, and the 256 byte memory (which must also contain the instructions) makes a classic Lagged Fibonacci generator impossible.

the SR does contain a basic set of binary linear operations, such as shifts, exclusive-or, and bit-wise and.


As a result, these three levels of parallelism can only overlap or pipeline step (2) of an operation.

the channel-level parallelism overlaps not only step (2), but also step (1) of an operation.


Figure 9 (a) shows that the falling delays are almost similar for all ESD types as the total capacitance (TSV + input capacitance of the ESD + input capacitance of the receiver) are similar.

the rising delay from the receiver output is different (90.6ps 154.1ps) because of the difference in receiver size.


The function of primary ESD and secondary ESD is same as limiting the voltage at I/O pins from VSS to VDD by bypassing the discharging current to power deliver network.

the secondary ESD is much (~100X) smaller than the primary ESD.


If states B and Dare selected as the intermediate states to optimize the transfer sequence from state Ato state B, then A E Band A C D E B, will be found as the shortest state sequences respectively.

neither sequence can activate error (because the assumption was that the error only corrupted the transition from F to B).


The classic way is to interpret all topological relations of edges within a pattern to design rules.

doing so may generate numerous design rules and induce tremendous locations reported by DRC thus making subsequent analysis difficult.


The advantage of ultra regular layout of SRAM matrix in achieving area reduction is quite obvious.

achieving the same benefit from the logic circuit is difficult because the logic circuit layout tends to be irregular.


Hence, it does not lead to a generic CNN design.

some simple image processing tasks, like edge detection, can be performed using such networks, as they employ only four to five non-zero terms in the A-template.


Therefore, at node j,waveform W4 and W5 will be removed because of the negative sign in the occurrence probability of W4.Only W1, W2 and W3 will be left which is exactly as algorithm I.

the node k mask tags are false for waveforms W1..4 so that they will be removed, leaving only waveform W5.


It is not well de.ned how to build weights in presence of multiple parameter variations.

the parameterized subspace is well covered by the zonotope in the proposed method, which results in higher accuracy as shown by experiments.


As a re-sult, reducing component temperature also tends to extend com-ponent, and therefore, system lifetime.

temperature-aware task mapping fails to capture at least two importance classes of factors that also influence system life-time: core properties, such as power density, supply voltage, and circuit geometry; and, system architecture, such as the organiza-tion of the communication architecture and the distribution of slack.


As a result, an adversary may typically try to disclose the secret exponent by identifying the repetitive patterns constituting a complete EM trace.

according to the hardware device on which is mapped the RSA algorithm, patterns associated to a squaring and a product might be really similar so that they cannot be distinguished.


It is hard to demonstrate succinctly why a speci.cation is unrealizable.

if we play the realizability game then we have a real counter-example after reaching the refutation.


Ideally, speedpaths would be correctly predicted by static timing analysis (STA) tools, prior to fabrication.

accurately modeling all the e.ects present in modern IC technologies is an overly complex task.


As a result, we will use multiple nodes, each performing lookup on a portion of FIB.

similar to RouteBricks, connecting these nodes creates another bottleneck: the interconnection links.


If the stripe selected to be evicted is a read stripe, that is, a stripe in the read caching space, this stripe is simply thrown away as the original copy of this cached data resides in the Primary Storage Layer.

if the selected stripe is a stripe that is in the write caching space, this stripe must be destaged to storage.


When the bus net size increases, experiments show that both the run time and dead space percentage of our .oorplanner will increase.

comparing with [1], our algorithm still perform better in run time by 32.07% and in dead space percentage with and without soft module adjustment by 11.17% and 21.34% respectively.


Tradeoffs between Knowledge and Time of Communication Some text in this electronic article is rendered in Type 3 or bitmapped fonts, and may display poorly on screen in Adobe Acrobat v. 4.0 and later.

printouts of this file are unaffected by this problem.


Equation (4) indicates that we can reduce the rotation time t2 by decreasing the average rotational inertia or increasing the applied moment.

the smaller the viscosity coefficient and the bigger the elastic coefficient, the weaker the anchor effect[8] and so the less the recovery time t3.


Though the same virtual tags can be mapped to the different TLB entry, they will not be indexed to the same set in the cache since the VIVP cache is indexed by the index bits from the virtual addresses.

when the size of the virtual tag bits is larger than that of VPN bits, different virtual tags can be mapped to the same TLB entry, which collapses the cache integrity, because of the remaining virtual tag bits.


[26] presented a thermal-driven placement algorithm for common-centroid placement considering thermal gradient, which is a kind of quadratic gradient [4].

their placements did not take account of device correlation for yield enhancement.


Most notably they .rst recognized the importance of relative perturbation as an optimization goal.

they address the last .nal placement stage whereas our method is aimed at more global changes.


Circuitssynthesized from SSRR-encoded FSMs consume less total power than those from SR-encoded FSMs.

sSRR-encoded circuits havean average 2% area overhead than thoseencoded by SR.  5.


These architecture description languages (ADL) automate the generation of code generators and instruction set simulators.

detailed pipeline control-path speci.cation is not explicitly supported by these ADLs.


Spin wave dispersion depends on the waveguide geometry, the strength of the bias magnetic .eld, and varies for different spin wave modes.

in the best scenario, spin wave signal is three orders of magnitude slower and than the photons in silica or electromagnetic wave in a copper coaxial cable.


Most of the published work has focused on the effects of STI [8].

the papers that have analyzed other sources of mechanical stress do not include all of the sources (such as epitaxial SiGe) and only study the PMOS stressors [9, 10].


The general type and count model can be finely tuned to correlate as much as possible with any particular FPGA architecture.

the model can also be parameterized to simplify it even further, without harming its accuracy significantly.


These proposals compute and record the miss penalty when a block is inserted into the cache, and preferentially replace blocks with small miss penalty.

only considering miss penalty is not enough.


It may be unrealistic to develop a Physical Synthesis environment in academia in the near future because the narrower task of timingdriven placement seem to be hitting serious roadblocks.

we do envision a set of benchmarks with valid timing constraints, multiple clock-domains and of representative size.


analytical model is inaccurate in representing the true FEA data even outside the KOZ.

the corresponding scaled versions for BCB and SiO2 liner cases closely follow their FEA counterparts outside the KOZ.


In such a way, the migration from software to hardware requires a limited intervention performed by hand.

this introduces additional issues, in particular when the application contains di.erent constructs whichimply memory operations(e.g.,pointer arithmetic or function calls with parameters passed by reference), where part of the data have to be allocated out of the accelerator.


As discussed earlier, the timing error is detected by re-sampling the output at a speci.ed period later than the clock edge and comparing it with the original output in [5].

if the data, which should be the result of the next clock cycle, comes too early through short paths and arrives at the shadow latch before the rising of the delayed clock, it will overwrite the previous data that should be stored in the shadow latch.


The local oscillator (LO) might be realized by a ring oscillator without on chip component [1].

the low power constraints cannot be easily matched with the requested phase noise, so that this solution was abandoned and replaced by a more usual LC-tank oscillator.


The procedure can be extended to an arbitrary recursion depth to provide a complete Boolean decision procedure.

this can be very expensive on large circuits, and is rarely used as a stand-alone decision procedure.


When the clock gating is disabled, the sleep switch is off.

the retention switch induces a threshold voltage drop between virtual ground and real ground.


So IPC increases quickly when HTh decreases from 96 to 64.

when HTh further decreases from 64 to 16, IPC starts droppingbecause of too many read and swap .


Introduction The hand-crafted fully-custom application-speci.c integrated circuit (ASIC) design methodology usually deliveries chips with lower power consumption, 5 to 8 times higher speed [3] and more compacted chip layouts than conventional standard ASIC design method.

automatic standard ASIC design .ow enables more ef.cient design process.


In this case also,M1 starts out in the linear-region, and enters the saturation region when the node voltage at a rises above V NMOS .

in this dsat case, the PMOS transistor M2 of INV1 also turns on (in saturationmode) when the voltage of node a reaches VDD + |VTP| (here VTP is the threshold voltage of the PMOS transistor) because the VGSof M2 becomes smaller than VTP.


4 Related Work There exists a large body of work on techniques, which effectively use the structure of the circuit to perform branch-and-bound search.

they suffer from two signi.cant drawbacks a) They cannot systematically avoid re-entering previously explored decision spaces, and b) They are signi.cantly slower on hard combinational problems than state-of-the-art SAT solvers implemented speci.cally for solving a problem in a single time-frame.


Previous works [3,4] have tried to improve the optimal clock skew scheduling by combining with retiming transformation.

retiming transformation is likely to have the following effects in the design flow: (1) an extra circuitry may be needed for initial states; (2) the forward retiming may increase the number of registers; and (3) verification issues.


Finally, companies have developed HDL-based cycleaccurate frameworks using post-synthesis libraries from HW vendors [9, 10].

their simulation speeds (10 to 50 KHz) are unsuitable for MPSoC exploration with real-life size inputs.


Each set has a degree of associativity given by the number of ways.

the key feature of a HWS cache is that some sets share the storage devoted to some of their ways to make a more effective use of it, as motivated by the heterogeneous utilization of the cache ways.


In this range, the number of points of larger leakage values is similar to that when spatial correlation is considered.

the large number of remaining points show smaller variations and are within the 20% and 90% contours, due to the same reasoning given above for .Linter =-1s.


On one side, they enable development of conceptually new security mechanisms such as physical unclonable functions (PUFs).

they also directly invalidate numerous hardware security approaches that assume unform temporal and spacial characteristics of similar elements across one chip.


NDRs apply wider wire widths and spacings to address electromigration constraints, and to reduce parasitic and delay variations.

wider wires result in larger driven capacitance and dynamic power.


Finally, starvation for NI resources by the local node is easily avoided by granting priority over bypass traffic to the local node if not served for a predetermined number of consecutive cycles.

this should happen rarely as the router is assumed to be power-gated off only when the load is low and contention is minimal.


201 As expected, the reduction in per access energy is greater when fewer number of bits are used to encode frequent val- ues.

this does not imply that we should use the least number of bits to encode frequent values.


Actually, other clustering methods can be used to determine the cluster number adaptively.

since the threshold is difficult to set, and the speed is a little slower, we did not employ them in our method.


Theoretically, the data in the array can be preteched immediately upon execution of f().

because pointers are passed to f(), the values in the array may be modified through these pointers.


A dead lock is the phenomenon which feedback control is emitted infinitely.

the dead lock state does not happen with the body bias control method which monitors the drain current of MOS devices [4].


Clearly, the MRF implementation of logic functions requires many transistors.

as our simulations will demonstrate, the MRF implementation provides signi.cant advantages over standard, minimum-transistor CMOS designs with respect to noise immunity, fault tolerance (e.g., imperfect threshold voltage Figure 2: A circuit for encoding the clique function of two logic variables de.ning an inverter (total transistor count is 20, as compared to two for standard CMOS inverter) control), and low-voltage operation (e.g., VDD ~ VTH of the transistors).


With a loosely coupled approach, mesochronous synchronizers would have required an oversizing of switch input bu.ers for full throughput operation which would have o.set their inherently lower number of bu.er slots with respect to dual-clock FIFOs.

such augmented input bu.ers do not dominate NoC area since other components (especially the output bu.ers, sized to 6 slots in this architecture) play a major role.


The refresh rate of a DRAM device depends on its leakiest cells.

the number of low retention time cells is relatively small compared to the total number of cells in a DRAM.


On average, because most benchmarks only utilize a small portion of the off-chip bandwidth, both traditional dual-core con.guration and the Orthrus architecture closely match the performance of the baseline: 12.0% slowdown for the dual-core, 2.2% slowdown for Orthrus with symmetric cores, and 2.7% slowdown for Orthrus with asymmetric cores.

for a bandwidth-sensitive benchmark such as mcf,  Parameter Baseline Dual-Core Orthrus Symmetric Orthrus Asymmetric Frequency 3GHz Processing Cores 14-issue OoO 24-issue OoO 24-issue OoO 14-issue OoO & 11-issue in-order Checks None Coarse-grained Fine-grained Fine-grained L1 caches (I$/D$) (32B Block) 4-way 64KB/64KB Core1: 4-way 64KB/64KB Core2: 4-way 64KB/64KB Core1: 4-way 64KB/64KB Core2: 4-way 64KB/64KB MAP: 2-way 32KB Core1: 4-way 64KB/64KB Core2: 2-way 32KB/32KB MAP: 2-way 32KB L1 latency 2cycles L2 cache (64B Block) 2-MB uni.ed, 8-way, 14 cycle latency DRAM Latency: 50 ns, Bandwidth: 8GB/s Table 2.


Note the reset network in LVS logic has to toggle as a whole in every clock cycle, regardless of the input switching patterns, which is clearly power inef.cient.

the switching activity in CMDL only depends on the toggle rate of the inputs.


× nsurf × p(r - r )(BPI × TPI) oi In reality, even this Cmax is not completely usable because: (i) Outer tracks can hold more sectors due to their longer perimeters.

allocating storage on a pertrack basis would require complex channel electronics to accommodate different data rates for each track [3].


The same problem is encountered for PWL simulation with dominant pole methods to compute the breakpoint time [3].

the breakpoint prediction problem is trivial if explicit integration, such as Forward Euler, can be employed for simulation.


Caches are usually considered to be cold .

hot-spots created by other logic blocks such as the execution units, due to their proximity to caches, can affect memory stability.


Every node will use the same element of s2 for a certain period of time before it moves on to another column in the B matrix.

the neighbouring nodes will never need the same element of s2 .


Note that, in Theorem 1, a(t) covers any deterministic arrival curve, linear and nonlinear.

in order to use NetCal theory for performance analysis of self-similar tra.c, we develop in Theorem 2 an extended arrival curve for self-similar tra.c, which is an e-enhanced linear arrival curve.


The introduction of the Wide I/O DRAM standard now provides a platform for integrated processor and 3D-stacked memory design-space exploration to derive future high-performance and extremely energy-ef.cient embedded SoCs and server systems, helping meet both the green [6] and exascale computing goals [7].

the key missing link required to facilitate the exploration of these opportunities is an accurate system-level power model targeting Wide I/O 3D-DRAMs that is: (a) easily integrable with systemlevel SoC design .ows and (b) enables design-time 3D-DRAM energy estimation in future DRAM-stacked SoC architectures.


The delay overhead can be reduced by increasing the supply voltage.

high voltage reduces the GND In supply gated mode (Gating Control = 0 ): if OUT1= 1 V(OUT1)=V(OUT3)=Vdd and V(OUT2)=V(VGND) Vdd-Vt Fig.


In the LR, w is just removed or replaced with a new input wire to vt, if the SPFD-based condition is satis.ed.

the GR takes a trial-and-error-like strategy.


Adiabatic design is based on a slow charge and discharge of a capacitive load using a time-varying clocked power supply, usually realized by resonant LC-based oscillators.

state-of-the-art models for energy estimation in adiabatic gates [2] are not as accurate and generic as the model proposed in this paper, as described in detail in Sec.


Ignoring the Cir-ODC clauses in CNF will not change the satis.ability of the original problem.

it potentially leaves the variables in these clauses under-constrained.


These methods allow for very accurate simulation of the system.

all of these methods are designed for use in design-time thermal-aware optimizations.


They are mainly based on Single-Instruction Multiple-Data (SIMD) architectures, o.ering massive parallel processing capabilities.

their performance are limited because they need to be fed by the video signal, which is slow.


The .rst speaker sits in between two microphones, and thus the TDOA should always equal 0.

the actual GCC-PHAT estimation varies signi.cantly during the speech gap.


This means that inserting one bu.er may bring only one new solution,namely, the one with the smallest W .

in minimum cost timing bu.ering, a bu.er insertion may result in many nondominated (C, W, Q) tuples with the same C value, where Q denotes the require arrival time (RAT).


The results thus suggest that the UC in general is the most efficient in eliminating memory accesses early to provide the best speedup.

the performance of the UC and either the SVC or the RFC are comparable in several cases.


Hence, SMV is semi-automatic, and is of relatively low cost compared to other tests.

due to time and resource constraints, we only afford to validate only a very small portion of dies, con.gurations and operating conditions, and the prediction is made based on these measurements as well as empirical experiences.


Thus, we have (a .ß|ß)=ß, even if a is not a Boolean value.

the current view taken by the Esterelcompiler is that programs like P12 should not be regarded as correct programs, since such programs are not well-formed , because information .ows backwards.


From4 corners to8 corners,thepercentage increase in the power dissipation climbs from 2.5% to 13%.

for a more accurate analysis, the loading on the rings needs tobe considered, which is explained next.


For example, in [19] by transferring only the components of a vector that have changed since previous transfer, the overhead of vector transfer can be reduced.

it requires the channels to be FIFO and imposes an O(N2) space overhead per process.


Neglecting the minimum segment lengths induced by design rules places less metal and may thus reduce the number of failed connections in congested areas of the design.

in addition to the higher e.ort in .xing, the number of wiring integrity errors increases significantly, mainly due to insu.cient space.


This level is added at the beginning of the process and modified throughout the process.

gates are eliminated only from the original circuit (and not from this bottom level).