However, even if simulation performance is much higher on these platforms, checking the functional correctness of a complex system, such as a processor design, presents many new challenges: Mapping checkers to acceleration platforms: Many softwarebased checkers designed for microprocessor validation are expected to execute in lock-step with the RTL or gate-level simulation of the processor model.

acceleration platforms can only simulate synthesized logic descriptions.


In [9], [10], the authors proposed to use on-scribe-line test circuitry to access and digitize the DAC array outputs; this signi.cantly reduces the probe card and test equipment complexity.

the metal wires that are cut during the dicing process may incur reliability issues.


While block-based methods are fast and reasonably accurate, designers are more comfortable with path-based methods because they identify the specific paths in a design that need to be fixed.

since path-based techniques cannot efficiently identify all the paths likely to be critical, block-based methods are often applied as a preprocessing step to extract information that is later used to identify critical paths.


The difference between estimated latency and actual latency is less than 70% and is not significant like the case of fdct without optimization methods.

to minimize the difference between the estimated latency and the actual latency, some improvements are required to the proposed method.


That is, some POs of the network may produce incorrect values if CDCs are derived for several nodes and used independently.

if a CDC is computed for a node and used immediately to optimize and replace that node before computing the CDC of another node, compatibility is not required.


For these preferences, no mechanism can provide both PE and SP [19].

our mechanism does satisfy a weaker property, strategy-proofness in the large (SPL).


[3] .rst produce a probabilistic automaton that accepts the trace and then extract from it likely properties.

learning a single .nite state machine from traces is NP-hard [17].


For example, a programmer could change the export_check method of HotCRP s password policy object to disallow disclosure to the program chair without changing the existing persistent policy objects.

if the application needs to change the .elds of a persistent policy, the programmer will need to update the persistent policies, much like database schema migration.


We would like to mention that MIC(Ci) calculation has been studied extensively in previous works [4][7][13][15] and is assumed given in this paper.

because of the current discharge balance phenomenon for DSTN shown in Figure 4, the exact MIC(STi) cannot be calculated easily.


INTRODUCTION CMOS devices have been scaled down aggressively in each technology generations to achieve higher integration density and performance.

the leakage current has increased drastically with technology scaling and has become a major contributor to the total IC power.


Otherwise, the system cannot tell how long to wait when checking whether or not any remote cache contains an updated copy by broadcasting or multicasting the query.

if multiple cachecoherent domains are shared in the network, congestion can cause nondeterministic latencies.


To estimate routing wirelength, placement algorithms often use the halfperimeter wirelength (HPWL) model to estimate wirelenth.

hPWL is not accurate enough particularly for high-degree nets.


The .rst (which is partly used in [19]) is to (a) make a tempo assumption Tz, (b) use the column corresponding to Tz in fharmo(t, Tz), fspecbal(t, Tz), (c) sample the four features sets fi(t) at lags t corresponding to the sub-harmonics and harmonics of Tz, (d) measure the likelihood of the resulting combination of sampled-features and tempo assumption.


The list above addresses many of today s problems at the two lower abstraction levels.

for the system application and multi-processor SoC platform levels, new approaches need to be considered, and very different design automation tool needs will emerge for each of these levels.


For example, in this k =7 architecture, the fully-populated cluster should contain between 4 and 6 LUTs to be area-ef.cient.

the 50% sparsely-populated cluster should contain between 4 and 9 LUTs.


Like an FPGA, a VPGA consists of an array of PLBs.

there are two key differences: First, the customization of the logic is done by the placement or removal of vias at the potential via locations, as opposed to con.guring SRAM bits.


Additionally, a larger number of MPPR cores per FPGA increases the demand for a large output bu.er.

this can easily be avoided by reducing the size of the distinguished point set D. A direct consequence are longer search trails for distinguished points and, thus, collisions of two or more cores requesting a bu.er lock at the same time will become extremely unlikely.


The .ner the partition, the higher the .exibility to control body bias and reduce leakage current.

in multi-well implementation, the multiplexer s area increases due to compliance with additional design rule such as well-to-well separation.


DOMINO: A System to Detect Greedy Behavior in IEEE 802.11 Hotspots * Maxim Raya, Jean-Pierre Hubaux, Imad Aad Laboratory for computer Communications and Applications(LCA) School of Computer and Communication Sciences EPFL, Switzerland {maxim.raya, jean-pierre.hubaux, imad.aad}@ep..ch ABSTRACT The proliferation of hotspots based on IEEE 802.11 wireless LANs brings the promise of seamless Internet access from a large number of public locations.

as the number of users soars, so does the risk of possible misbehavior; to protect themselves, wireless ISPs already make use of a number of security mechanisms, and require mobile stations to authenticate themselves at the Access Points (APs).


The equal duration of the reset and evaluate phase on the right side of the pipeline can be seen for stage 4 in Figure 3 where the path traversed by N4 = 0 on the reset network loop (i.e., stage 4 in the reset phase) is the same as the one traveled by N4 = 1 (i.e., stage 4 in the evaluate phase).

the evaluate phase of stage n-1 has to wait on the arrival of the reset phase from stage n to the latch-enabling AND gate in order for data to flow from the former to the latter.


The MMTk barriers full checks are much simpler than those usedbyBartok in termsof theirbehavior,andregister pressure.

as we show below, other GC algorithms are more complex than classical generational GC, and the table-based lookups performed by Bartok are common with other applications e.g., implementations of thread-local heaps with each thread s local data placed on a separate set of pages.


Our work draws inspiration from cache replacement and insertion policies in that it attempts to predict when cache lines will be reused.

cache way-management policies decisions are made among a small set of blocks.


M8) provides better robustness then M1 vias, when we pack as much as vias on the landing pad.

in terms of failure time vs. block area ef.ciency, higher metal layer is not as good as lower metal 3Here we use the terminology local via as a via in the BEOL metal layers (V1 V9 ), to differ from the TSV.


In this case, an inverter is the best level shifter.

if VDDI < VDDO, the inverter cannot be used, due to the high leakage currents that result in such a conversion.


The original implication graph analysis continues by replacing the atom at the FIP, (x = y), with its implicants, (y = x4) and (x = x4).

a new clause is also learned representing the exact implication involved at the FIP.


To counter this trend, several bus design strategies have been proposed, such as low voltage differential signaling (LVDS), power aware bus encoding, and hybrid current/voltage mode signaling [3].

these techniques still require the entire line capacitance to be charged to transport a signal (i.e., level-based signaling).


Both of them are being able to communicate over regular TCP/IP-based networking stacks or Remote DMA hardware like In.niband.

each of these translations through software stacks costs performance.


Note that this optimization requires stream address generation logic in the processor pipeline (akin to HEAVYWT) to rename consume instructions to the correct queue addresses to index into the stream cache.

this is still better than HEAVYWT, since SYNCOPTI shares the L3 bus, while HEAVYWT requires extra interconnects connecting the cores to the synchronization array, which can be expensive [12].


Name ofArraysSize(KB)Count tomcatv Specfp95 9 1194,868,048 nasa7/btrix Specfp92 294,31244,430,039 nasa7/mxm Specfp92 3 12047,168,707 nasa7/vpentaSpecfp92 9 1142,274,945 adi Livermore 6 2416,062,860 dtdtz(aps) PerfectClub171,60542,119,337 bmcm(wss) PerfectClub11 12689,539,244 psmoo(tfs) PerfectClub1 20416,955,980 eflux(tfs) PerfectClub5 29712,856,306 Table1:Programsusedintheexperiments.


Since gate dimensions are in the range of few tens of nanometers, it is expected that the gate area will contain only a small number of grains.

work-function of each grain is a function of its orientation, which is not controllable during the growth period and hence, the orientation of each grain is determined randomly [17].


Based on the transmission line theory above, non-monotonic driver output waveforms should ideally be modeled as multipiecewise linear waveforms to capture plateaus and multiple reflections.

it is shown in [2] that reflections and other transmission line phenomena become important only when the source impedance of the driver is less than or comparable to the characteristic line impedance.


Consequently, hardware acceleration is bene.cial to both.

the e.ciency of a hardware implementation often comes at the cost of .exibility and scalability [9].


Low-swing signaling schemes reduce power consumption by not requiring capacitors to be fully charged or discharged at each signal transition.

these techniques su.er from reduced signal to noise ratio as the supply voltage scales in DSM technologies.


Other works [8] [9] [10] exploit binary translation to convert sequential code compiled for single-issue processors into code executable on VLIW architectures.

we are not aware of any previous work combining binary manipulation and FPGAs for providing support in the design of completely con.gurable application-speci.c processing elements.


If the stopping estimates were perfect,we could assignan emissionprobabilityof1to the road segment whose traf.c lights matched with the stopping distances and0to others.

the estimations of distance obtained from accelerometersand gyroscopehavea margin of error.


Such a requirement, andingeneral completely legalcellplacement can be accurately modeled by an integer quadratic programming (IQP) formulation.

the IQP problem is well-known to be NP-hard [6], and such a formulation of the incremental placement problem would be intractable.


5.5 Using High-LevelPerformance Targets The settling time is the time in which the system output get close enough to the targets (for instance, 5% of their values) So far we have assumed that the performance target accommodated by METE are in terms of IPCs.

depending on the application domain, higher level performance metrics (like the number of transactions per second) may be speci.ed to METE in a .exible manner.


In some cases the integral can be solved analytically [35], such as for height .elds or periodic surfaces.

neither of these cases usually applies to architectural models.


3.1 Sensitized Pipe Stage Delay There is a strong correlation between a static instruction and the paths sensitized by each of its dynamic instances [16].

when we analyze different instructions sensitizing speci.c paths in a microprocessor pipe stage, we observe a wide disparity in their sensitized delays.


It was found that a general second order or cubic polynomial is su.cient.

in order to reduce the complexity of this 7-variable model, we ignored all cross-product terms except those with Lnbase,since Lnbase was found to be the most signi.cant variable.


If the measurement process is the only process in the system, the timestamps that the process generates should be spaced at about 50 + 10 = 60 ms. A small deviation in this value is expected when other processes are present in the system.

an excessive (several hundred milliseconds or more) deviation is an indication that the CPU scheduler made a bad decision.


If their base would be excited by a small LO signal, then the nonlinear distortion in this mixing operation would be mainly caused by the nonlinearity of the collector current of Q1 and Q2.

the large amplitude of the .LO signal makes Q1 and Q2 switch from cutoff to the forward active region and further into saturation.


Then, we can further balance them by applying our bit-.ipping scheme.

similar to the bit-.ipping scheme, the problem is how to choose the proper invalidation interval that can reduce the RR phase signi.cantly with negligible performance degradation.


isPrime is atypical in that it contains no memory accesses.

memory accesses are common so their translation must run at close to native speed and have a form that prevents unintentional access to the VMM.


These unmodeled residual taps lead to an unavoidable BER error .oor, even for the genie-aided MLSD.

this error .oor could be suppressed by increasing Na (at the expense of complexity).


The decomposition does not change the total number of literals, so the initial synthesis step may not generate this decomposition.

in the synthesis of GPLAs, the first goal is to get a valid implementation for the given configuration.


For example, referring to Figure 9, the output of gate 5 depends on AB, , C and D .

depMax will identify that inputs 1 and 2 depend on B (since B is at a higher level than A ) and that inputs 3 and 4 depend on C .


For proactive use of redundancy, the lifetime distribution function can be derived using the warm k-out-of-n model.

the wearout pattern of components changes as some of them fail because they may no longer be able to enter into recovery mode.


ASR [4] also controls the replications to improve its performance by dynamically monitoring thebene.ts and costs of the replications.

[16, 17] introduce self-invalidation in order to reduce cache coherence overhead caused by the replicated cache blocks.


Finally,theratioofthetotalavailabletracklengthwithin layeritothesupplied(nominal)tracklengthonthelayer, whichwecalltheutilizationfactorUi,canbewrittenas Ui=Tr(1;vi): (1) Ofcourse,sinceallmodelsfocusontheresourcesusedfor signalnets,theresourceusedforpower/groundandclock distributionmustbeleftoutoftheestimatedavailableresources.Thisleadstoanotherfactor,thefractionofrouting resourcesusedforsignalnetsonly,whichwedefnehereas thesignalnetfractionsi(onlayeri).ThischangesEquation1to Ui=Tr(1;vi)si: (2) 2.2 Review of Existing Models Sai-HalaszThefrstmodeltoaccountfortheefects ofrouterefciencyandviaimpactwasusedbySai-Halasz [15]topredictperformancetrendsinmicroprocessors.The modelassumesthatpowerandgroundwirestakeup20%of eachlevel(si=0:8),thattheroutingefciencyis40%and thateachlayerblocks12%to15%ofthewirecapacityof alllayersunderneathitifthewirepitchesareequal.Ifthe pitchesdifer,thisfactorhastobereducedbytakingthe ratioofthepitchesintoaccount.ForNllayers(numbered from1toNl,goingbottomtotop),theviaimpactfactor onlayeriinSai-Halasz'modelisdefnedtobe Nl Xpi 1;vi=0:85pk, (3) k=i+1 wherepxisthewirepitchonlayerx.


Figure 4: Simplifying re-parameterization for proof of Lemma 5 Thus, the decision rule described in Equation (10) will design the domains for two hybrid systems, Hc and Hcc,which automatically satisfy Conditions (7), (8), and (9).

sk it is not guaranteed that = R2 for either Hc or Hcc.


Thus, the power dissipation of regions connected by a functional interconnect are not expected to have large temperature differences.

the inserted heat pipes can connect distant regions with a large difference in temperature and thus contribute more effectively to the elimination of hot spots.


Hence, conventional dual-Vt designs that did not consider junction BTBT while assigning high-Vt, was extremely effective in saving leakage in submicron technologies.

in a 50nm device, the junction BTBT leakage increases significantly with small change in Vt and becomes comparable to subthreshold leakage at Vt = 0.3V, which is only 100mV higher than the low-Vt (Figure 3b).


Curves assuming an equal frequency use a cycle time of 4.45ns, the maximum obtained from place and route results.

the routers were still optimized for minimum cycle time in the place and route .ow.


One of the advantages of this medium is that the utility would bear only the costs of the terminal equipment and for leasing the line, which would reduce the utility s overhead and improve communication.

the utility would not have control over the medium because, in most cases, it would not own the dedicated wired medium, and it would require physical connections and reduce flexibility.


This results in compact area of combinational designs.

according to [19] the switching delay of the SW devices (ME cells) is inheritely larger than the one of a high-performant CMOS transistor.


This single-core simulation environment is used to evaluate our replacement policies on the single-threaded applications.

the same memoryside con.guration is used for both single-core and multicore environments.


It may provide an even  larger power saving as all the repeaters are removed, with low power pulse generate circuits being used Interconnect width (Pm) 0.20 2.4 0.30 1.6 0.25 2.0 Cutoff region 1.2 0.40 Cutoff length instead.

a longer wire delay is 0.8 0.50 Power ratio R p expected due to the longer transmission distance.


To alleviate these conflicting goals, many approaches to resolve the test problems have been researched over the last several years [2-10].

these techniques lead to high area overhead and the large test data volume and hence are not practical for large circuits.


Thus, if a different wire pair maintains symmetry, power consumption remains constant.

if there are small loading imbalances between the two wires that make up the pair, the amount of energy needed per clock cycle depends on which of the two nodes is switched, and thus, it is correlated with the logical value.


One might think after ICCAD hosts the .fth1 placement contest, we can declare the placement problem to be solved.

this is not the case, as routability is just one dimension when measuring placement quality.


Thus, a natural consequence of this is that large scale complex DMFB can be designed as done in VLSI, once strong CAD frameworks are ready.

cAD research for DMFB design has started very recently.


During SDCT growth, multi-source single-target maze routing is adopted to increase the flexibility of constructing an initial Steiner tree.

the source window of multi-source single-target maze routing may identify such inappropriate sources in SDSubtree growth.


A modulated signal is applied to the input of the transmitter and spectral density at several offset frequencies, EVM, and output power are characterized using vector signal analyzers [2]-[3].

such performancebased characterization does not lend to easy calibration as required parameters are not directly measured.


It can be observed that the original signal is estimated accurately by the proposed technique.

the result of thermal noise aliasing that occurs due to the sampling operation is visible.


To combat this problem, signi.cant advances have been made to improve the e.ciency of FPGA CAD algorithms.

tackling this issue should not be left solely to CAD developers.


As we can see in Figure 8(b), the percentage of communication power consumption of the P2P implementation increases very fast with the increase in the degree of parallelism.

the percentage of communication power in the NoC implementation increases much slower.


Further, since the coherence mechanism must know that data is not local by the time it is ready to generate a signal, this approach has the potential to slow down every miss.

the local memory is also potentially signi.cantly speeding up the response to misses.


In the past, issues of FAA certification were not directly applicable to military systems.

with the potential for unmanned air vehicles to travel in controlled 552 National Airspace, the applicability of certification is becoming We will discuss these challenges and will tell stories about some likely.


As expected, these traps result mostly for decoder faults.

they account for <16% of the fatal traps seen on decoder faults.


INTRODUCTION The static noise margin has been traditionally used for SRAM cell stability characterization.

recently it has been shown that the dynamic noise margin that utilizes the critical WL pulse width or TCRIT to estimate SRAM cell stability is more precise [1] because static read margin overestimates failures and static write margin underestimates failures.


INTRODUCTION Chip-multiprocessors (CMPs) bring abundant parallelism to commodity systems.

the lack of concurrency in software prevents programmers from fully exploiting the additional hardware cores.


To overcome the intrinsic ine.ciency of electrical interconnects, researchers have leveraged recent developments in chip photonics to design novel optical networkon-chip (NoC).

existing optical NoCs are mostly based on passively switched, channel-guided optical interconnect in which large amount of power is wasted in heating the micro-rings and maintaining the optical signal integrity.


contrast to that, random logic functions require relatively few wires because of the limited number of LUT pins.

the overall irregularity of such functions causes that a much higher degree of .exibility is required in the routing resources.


In particular, for LOAD, o.set is added to the base address and the corresponding location into the memory is accessed, directly returning the value on data r, without any access to the bus.

for STORE, the value data w is alsoput on theport M o data to be e.ectively written to the proper location.


Greedily selecting the next relays which connect the most terminals and pruning redundant relays help to reduce the total number of returned relays.

the iterative algorithm takes the longest time to .nd solutions among the three algorithms because iteratively checking k-connectivity at every insertion of a relay is time-consuming.


Several on-chip interconnect architectures have been proposed that leverage photonics for future multi-processors.

most of them are bus-based, such as Cornell hybrid electrical/optical interconnect architecture [2], Firefly [3] which proposes the implementation of reservation-assisted singlewrite-multi-read buses, and HP Corona crossbar architecture [4] which is in fact several multiple writer, single reader buses.


A diode has a simpler structure, and hence it is good for cell density.

a diode cannot satisfy the high write current requirement beyond sub-100nm technology [6].


A delay-based countermeasure (C M) has been recently proposed and validated by [5] to cope with this kind of timing violation.

the question of its ef.ciency against E M glitches was to be raised.


For STT-RAM, the magnetic data storage mechanism makes it resilient to the radiation-induced soft errors after the data is written into the MTJ.

the MTJ switching current is supplied by the connected NMOS transistor.


Since there are two supplies (Vdd and Vss), one its supply or ground will only increase (in magnitude) so that the would think that four signals would be required.


PREVIOUS WORK One of the earliest attempts to balance logic and routing elements to decrease area was performed by DeHon [6].

this analysis was performed for an FPGA with a binary tree interconnect structure.


However, one point to be noted is that we cannot guarantee all the Abnormal Modules will be solved at one time.

lR plans to solve these modules gradually after several iterations.


.LCAV, ESL École Polytechnique Fédérale de Lausanne,Lausanne (Switzerland)name.surname@ep..ch ABSTRACT Chip designers place on-chip sensors to measure local temperatures, thus preventing thermal runaway situations in multicore processing architectures.

thermal characterization is directly dependent on the number of placed sensors, which should be minimized, while guaranteeing full detection of all hot-spots and worst case temperature gradient.


TREE MAINTENANCE The precise composition of an aquasun tree does not affect the ability to insert new boxes and the correctness of the window query processing algorithm.

processing performance depends heavily on the speci.c tree composition.


As shown in this table, although the bus throughput of the CACHE-only model is almost the same as that of the SCIMA-SMP for 0-cycle latency, it greatly degrades as the latency increases.

the SCIMA-SMP model is less in.uenced by latency because of the large granularity of the data transfer.


Our experiments show that the proposed .ow scales up to at least a thousand macros in addition to hundreds of thousands standard cells.

.oorplanning instances with a thousand blocks is a bottleneck and may be improved further.


The target of the ESP tracking scheme is to perform early address resolution of these loads.

not all ESPbased loads can be early resolved, since no address calculation is performed when the ESP value is unknown.


HIGH-LEVEL TOPOLOGY EXPLO-RATION In this section a high-level comparison of topology performance is provided.

this analysis will only give the high-level perspective and is agnostic of physical implementation e.ects.


From the third column, it is clear that the partial-subblock TLB further improves the utilization of superpages by re- laxing the requirement on the contiguity of physical pages.

its result is a little bit disappointing.


All this unnecessary overhead can be avoided at the program level.

it requires knowledge of the underlying platform architecture.


Figure 5(a) presents GPD results for this lowest guaranteed performance level.

most processors will have a higher actual performance (which is the time-weighted average of all the IPCs seen during the lifetime of the processor).


When warp width is 4, the IPC achieved from all the methods is very similar.

with increasing warp width, for all the benchmarks, the scalability of the majority and the majority-threshold methods improve as compared to immediate post-dominator, greedy, and greedy-return methods.


Activity density increases with both connectivity and bandwidth.

mapping has higher impact on activity density for applications with lower connectivity.


The cycle average power (CAP) [21] is de.ned as the average power consumed during a single tester cycle.

it does not factor in the varying time frame window of the entire switching activity for each pattern.


Simulation Time Controlled Modeling In the standard method, the model reduction ratio is the only goal of the simpli.cation.

each simpli.cation is also causing a change of simulation time.


Numerous security applications have been transitioned into FPGA implementations allowing security applications to operate at real-time speeds, such as .rewall and packet scanning on high speed networks.

the utilization of FPGAs to directly secure software vulnerabilities is seemingly non-existent.


This arrangement allows us to place .ip-.ops anywhere in the placement region.

if it is placed in HCR, it incurs the area overhead (about 32% of ZPG .ip-.op area) due to n-well isolation.


Because the way to estimate exact minimum number of cuts in practical time is not known, existing algorithms calculate approximate area cost by some heuristic methods.

depth cost can be calculated exactly in practical time.


Even though OPT1 results in higher junction BTBT leakage compared to low-Vt design, it saves more than 55% of total leakage.

in 25nm technology, due to significant increase in junction BTBT, dual-Vt design using CONV results in negligible leakage saving, while OPT1 results in only 14% leakage saving (Figure 4c).


Path activation probabilities were used in [10] to prune portions of the circuit that are activated the least.

[11] forms quality constraint circuits to identify external don t cares to the circuit and uses conventional Boolean optimizations for logic approximation.


The same is true of the undershoot at t=25 ms. At t=40ms, the controller sets the heater current to 0, immediately dropping microhotplate power to 0.

surface temperature follows a decaying exponential as it cools off, finally stabilizing at 30ºC, since that was set as the ambient room temperature in the simulation.


The high resolution of the ADC makes necessary to accumulate a high number of samples and then a long test time.

a precise production test can help to validate the design of a high-performance ADC, reduce the number of wasted parts, and enable the calibration, so it is necessary to develop methods for accurately characterizing the specification of highresolution and also high-speed ADCs.


This can be shown through the example in Figure 5.

placing a register with small delay target far from the clock root may force all root-sink path length to increase to satisfy skew constraints and therefore is more harmful.


A high speed global clock is attractive to allow a high throughput between the switches.

high speed clocks may have problems such as skew, timing closure and power dissipation.


Also, the number and type of a.ected cells was a function of the particle energy not layout.

the results shown in Figure 6 clearly indicate that 1) both combinational and sequential cells can be a.ected by a single particle strike.


a 45-degree wire crossing a 90-degree wire).

it is most important as at present, all layout is assumed to be two-dimensional.


User Control: Manually, the veri.cation engineer can precisely control the percentage of the new stimuli.

controlling the .avor duration is more complex.


Summary: Software level techniques alleviate or complement hardware level techniques or are deployed when hardware redundancy is prohibitive.

software-level reliability techniques do not ensure 100% correct execution and require hardware-level support, thus motivating the need for cross-layer reliability (see also Section 3.1) to provide a better tradeo.


For the purpose of evaluation and since we want to have a single ISA system, based on the availability of the data on the power, area, and other characteristics of microprocessors, we use an EV6 (DEC Alpha 21264 [20]) for the baseline cores.

for the animator core, we select a simpler core like the EV4 (DEC Alpha 21064) or EV5 (DEC Alpha 21164) to save on the overheads of adding this extra core to the CMP system.


Inter-chip connections can be routed on the interposer by chip-scale wires to enhance design quality.

its design complexity increases dramatically due to the extra interposer interface.


This increases the throughput of the functional unit, thus reducing the effective latency of a group of instructions having some independence amongst them.

the height of the data .ow graph, which is determined by chain of dependent instructions, is not reduced by pipelining.


This may be due to the fact that it operates on a sequence-pair formulation, in which a small perturbation may cause a module to be moved signi.cantly from its original position.

fLOORIST achieves legality and 0% overlap on all instances, preserving the length of most individual wires (and thus global interconnect length) far better than the other legalizers while remaining competitive in runtime.


It must be mentioned that the results have been achieved for the sort kernels but not for a complete system, as the available XUPV5 board provides only a single lane PCIe host interface.

there exist commercial as well as academic systems that would ful.llour I/O requirements (e.g., the BEE3 system [4]).


Step size h of MEXP can be .ne tuned to satisfy the error tolerance without a signi.cant cost.

in the implicit methods, the re-evaluation and error estimation for a new h have to again solve a linear system.


When SPECjbb can only take up to 10% of the total cache size, the MPI for TPCC is reduced by about 25%, and as a result the IPC for TPCC is increased by 11.4%.

as expected, the MPI for SPECjbb is increasing and its IPC is reduced.


This value plays the role of judging how important power is compared to area.

as seen from our results, there is an optimal number of resources, which can achieve minimum total leakage power.


Of all the memory references made, those in the spike with recency 4000 (for 8KB pages) constitute around 0.5% -which we can read directly from the graph.

if we consider only those accesses with a recency value greater than a modest TLB size (say 20 entries), we see that the spike at recency 4000 dominates the other accesses with a probability almost two orders of magnitude higher.


if adjf(ru) is positive, p.f(rrt) is increased.


1 0.5 Normalized Amplitude  0 detect more than 60% of the silence.

in the noisy environment with SNR=0dB, the accuracy is almost halved.


; .o)= s cause continuous-time white noise is basically an unphysical n=-8 process.

it is possible to .nd the power spectral density, if we consider a sampled signal and use discrete time 88 -n 2.


C for 108 seconds (~3 years) indicate that a Vth compensation of 0.2V can almost preserve the WRITE and HOLD stability of the fresh device even after 3 years, while for the READ stability the compensation mechanism is less effective.

the READ Static Noise Margin (SNM) experiences an insigni.cant decrease over the 3 years time span in the presence of a Vth compensation, while without compensation it decreases by a x4 factor.


Methodologies that incorporate congestion within the logic synthesis have been proposed in the past.

in [15] and [16] it was demonstrated that predicting the true congestion prior to layout is not possible, since different layout regions can have very different routing demands, and the effectiveness of any congestion minimization approach can only be evaluated after routing is completed within the assigned die size.


Within (12), de.ne f(t)= f ·(t +a(t)) to represent the phase of the VCO, which is only true if the VCO free-running frequency is a constant.

if the VCO control voltage switches within {vci }, and the free-running frequency varies within {fi}, the phase of the VCO can be generalized to be T f.(t)= f (t)·v 1 (f0(t)+f(t))·bb(t).


Measuring the silence after the utterance does, since the number of utterances for the partner that have not yet been followed by a follow up utterance drops quite fast after ending the utterance, where this is not the case for utterances for the system.

using this feature would in practical implementation lead to delaying the decision whether an utterance is intended for the system or not.


(1) Here, D'is the newly updated page of D0.represents XOR 0 operation.

if more than half of the pages in a stripe are updated together, the parity page is calculated differently: for example, assume the pages D0 ~ D2 are respectively updated to D0'~ D', new parity page D'is generated as: 2 p D' = D' D' D' D3.


The wheelchairs are usually controlled through a joystick.

using a joystick might not be possible for many patients who might have sensori-motor or cognitive impairments [22].


While data with many sharers, such as global synchronization structures, have poor locality and occupy a large amount of cache storage space when using a private style caching scheme.

traditional distributed shared caching (e.g.


Generally, the cache compression increases the e.ective cache capacity.

it does not mean that the miss rate is always decreased.


Therefore, estimating the short-circuit current is important to design high-speed VLSI s. Much effort has been devoted for the extraction of accurate, analytical expressions for timing models of basic circuits.

previous works in the short-circuit power estimation area have not entirely or exactly reflected gate-to-drain coupling capacitance and the short channel effect [2][3][4][5].


4.6 Bitstream Generation  The programmer handles the task of configuring the SRAM bits in the design based on the bitstream supplied to it.

we need a way to generate this bitstream.


Analysis and Mitigation of Variability in Subthreshold Design Bo Zhai, Scott Hanson, David Blaauw, Dennis Sylvester {bzhai, hansons, blaauw, dennis}@umich.edu, University of Michigan, Ann Arbor, MI ABSTRACT Subthreshold circuit design is a compelling method for ultra-low power applications.

subthreshold designs show dramatically increased sensitivity to process variations due to the exponential relationship of subthreshold drive current with Vth variation.


In every HCS benchmark, except GC, performance peaks then falls as KTHROTTLE increases.

since a miss in the L1D cache can incur a signi.cant power cost it may be desirable to and inter-wavefront locality PKI using an unbounded L1 cache with 128 byte cache lines.


The result of the conventional method denotes the same tendency of that of the proposed method.

as the number of sensor instances decreases, the increasing rate in the standard deviation of conventional method is larger than that of the proposed method.


The LCS (within-die and inter-die) and GCS are better for the P-Tree method than the OCC-Tree method in most cases.

both P-Tree method and OCC-Tree method are not able to meet the stringent skew constraints.


The access latency of magnetic disks is 10ms.

the read access latency of .ash memory SSD is 0.1ms [26].


They also propose using nondeterministic FSMs, which can take substantially less space than their deterministic counterparts.

they count on recon.guration to change the wiring of the FSMs, and so their designs are not suitable for an ASIC.


Note that domination in timing bu.ering is de.ned on C, W, Q but not on S, while S is only responsible for eliminating infeasible solutions.

domination in slew bu.ering is de.ned on C, W, S but not on Q.


If a very simple or fine-grained ULG is employed, more ULGs will be required to implement a given circuit and the routing area required for interconnecting the blocks might become excessive.

if a very complex or coarse-grained ULG is used, much of the ULG functionality may be unused with area waste.


An occasional instruction cache miss is acceptable even for embedded real-time applications.

in scenarios where misses come close together and take a long time to service, a realtime system suffers the most since the stalling seriously affects the performance of the entire system.


All experiments used the gate delay model de.ned by the Verilog HDL [19] standard.

instead of real numbers, all delay values X were assumed to have a normal distribution with s(X) = cv|µ(X)| of the nominal value µ(X).


introduced two better feasibility bounds, which they combined in an ef.cient algorithm.


In this case, a balance of operating current between stories of functional logic will take place without putting special efforts and a reduced supply noise will automatically be achieved.

as discussed in section 2, the worst case voltage fluctuation happens when there is a large discrepancy in switching activity between the functional units in the two voltage levels.


Generally, in most of the existing systems, the parameterization techniques used for speaker-dependent and speaker-independent recognition is the same.

in the case of speaker-independent speech recognition, it is well known that the performance of recognizers for female speakers is almost always worse than that obtained for male speakers[8].


From the introduction above, it is not hard for one to note that, all the veri.ed side-channel attacks have been proposed with corresponding countermeasures, which would better protect PUFs.

built on complex inner variations, different PUFs would rely on varied silicon characteristics, it is dif.cult to bring forward a comprehensive countermeasure.


Hence, we expect SOSA to perform poorly for small input sizes, where each instruction is executed in a small number of PEs.

sOSA performance should improve as input size increases and eventually match (or exceed) the performance of the P4, I-SS and 16-CMP.


The most straightforward implementation is to let each sensor transmit the update messages at a same .xed rate.

due to the multi-hop transmission nature and possible packet losses, this results in sensors far away from the control center (thus with more hops to travel) achieving a much lower goodput.


In terms of exploiting SW runtime distribution, there is a similar approach in [8].

the method in [8] has an exponential complexity, O(LP) where L is the number of voltage/frequency levels and P is that of performance setting points.


It is necessary to consider routing obstacles for modern .ip-chip designs, where the obstacles could be regions blocked for signal integrity protection (especially for analog/mixed-signal modules), pre-routed or power/ground nets, and even for through-silicon vias for 3D IC designs.

no existing published works consider obstacles.


Each entry in the matrix therefore requires a separate timing analysis run, leading to a high run time.

the results from this approach were used as reference to check the results obtained with the other two approaches.


A large number of these techniques rely on the replicate/recompute design methodology by using time/space redundancy.

the usage of checkers and logic duplication inherently introduces significant delay, area and power overhead.


Here it is assumed that the threshold voltage of each transistor in the SRAM cell can be adjusted independent of other threshold voltages by changing the channel doping, which is deemed to be a safe assumption because in an SRAM cell the channels of the transistors are not too close to each other [14].

in the Simulation Results Section it will be shown that even if only one threshold voltage is used inside the cell, power reduction can be considerable.


4.2 Race Conditions Most race conditions in our extended protocol can be han- dled in the same way other similar race conditions are handled in the baseline protocol without ReVive - by serializing accesses to the same memory line and sending negative acknowledgments to avoid deadlocks and livelocks.

some race conditions are related to error recovery and need to be carefully considered.


Since 0.043 seconds are required to perform one error correction at level 2 recursion, it will take approximately 16 hours to complete the factorization of a 128 bit number.

assuming success of all the gates, the circuit is repeated on average 1.3 times [56], so the total time to factor a 128 bit number would be around 21 hours.


Althoughsymptom-baseddetectionisinexpensive,the amount of coverage that canbe obtainedfrom a symptom-only approachis typically limited.To address thislimitation, we make use of the second area of prior research, software-basedinstructionduplication[26,27].With this approach, instructions are duplicated and results are validated within a single thread of execution.This solutionhas the advantage of being purely software-based, requiring no specialized hardware, and can achieve coverage of more than 90%.

the overheads in terms ofperformance andpower arequitehigh since alargefraction of the applicationis replicated.


(2) e.E vi,vj .e,i<j vi,vj .e,i<j The advantage of using the quadratic wirelength ob jective is that its unconstrained minimizer can be obtained by solving a positive de.nite linear system of equations.

it over-penalizes the long nets which gives a bad half-perimeter wirelength placement solution.


If the value of the binary variable xk is 0, then the value of state register Rk remains unchanged.

if the value of the binary variable xk is 1, then the value of state register Rk is complemented.


Techniques to detect permanent faults in FPGAs have been discussed previously in [15].

the authors do not discuss the permanent effect of a single upset in the user s combinational logic, but physical faults that cannot be corrected by reconfiguration.


This type of move reduces the power if a faster function unit is replaced by a slower function unit.

the timing yield of this move might be increased  1 1 2 2 3 3 4 4 Tclk Tclk  Delay Delay 00 Fig.


As an example consider the expression E = ac + ad + bc+ bd,Using the brick p1 = a + b or p2 = c + d the number of gates can be reduced from 7 to 4 as discussed in the previous section.

the introduction of brick p2 in presence of p1 reduces the number of gates only from 4 to 3.


2.2 Deep Sub-micron Effects A few years ago, FPGAs used process technology that lagged the state-of-the-art.

in recent years, due partly to their regular structure and high volumes (i.e.


Instead of one agent formulating test sequences for the multi-processor system based on coverage or collision metrics, we chose to create a set of simpler agents cooperating with each other.

for simplicity reasons, agents don t have an understanding of the full system FSM and instead use a dichotomic .nite-state machine (DFSM) to represent their perspective of the protocol and coverage.


Note that we can choose to perform the voting process into the internal MicroBlaze instead of using an external computer (in fact, as a way of increasing the reliability, we could even replicate the MicroBlaze into the FPGA).

in order to keep firmer control of the experiment, we decide to use the arrangement shown in figure 4.


While steep-slope devicesmay offer superior performance at suf.ciently low voltages,state-of-the-art CMOS FinFET technologies continue to offer 978-3-9815370-2-4/DATE14/&#169;2014 EDAA superior peak performance on highly sequential, latency-boundcomputations.

we shall show that, for tasks withthread or data parallelism, with .xed, real-time performancedemands, or with tight thermal constraints, adding steep-slopedevices to the chip designer s tool chest extends the rangeof realizable designs in fundamental ways.


If bit bi is logic 1 in vector vv, then we de.ne the static probability of bit bi, PB (bi), to be equal to P (SB,i).

if bi is logic 0 in vv,then PB (bi) is de.ned to be 1 - P (SB,i).


Van Ginneken s Dynamic Programming Van Ginneken proposed a dynamic programming to minimize the delay of buffered trees [18] and there has been much research on buffer insertion based on Van Ginneken s algorithm.


There is no path for the charge to flow away and node W keeps it charge on the parasitic capacitance.

when both A and B switch from 0 to 1 ( A and B both remain at 0), node W is connected to node Z and the parasitic capacitance discharges.


A more accurate analytical model with description of gate on-set voltage was given [15].

the inaccuracies of the model increase at higher gate voltage.


On the M512B, M1KB, and M2KB benchmarks, the runtime of Cadence SMV is better than the predicate abstraction runtime.

cadence SMV is not able to handle the M4KB benchmark which has a much larger state space.


The caller of a paused operation on an object can access this object again only by resuming the paused operation.

with an abortable or query-abortable object, the caller of an aborted operation is not restricted in any way: it may reapply the same operation, but if applying a different operation on the object better suits its objectives, it is free to do so.


In [22], the typical clock frequency for a single pipeline stage in commercial microprocessor working in super-threshold regime lies in the range of 15~44 F04 delay, depending on specific design differences.

since microprocessors working in the subthreshold regime prefer shallow pipeline (more F04 delay in a single pipeline stage) to mitigate variability[23], higher F04 delay is observed in low voltage microprocessor, for instance ~400 F04 delay of a single pipeline stage from [9].


Most of the existing works on this problem assume an obstacle-free routing plane.

modern integrated circuits often contain many obstacles such as IP cores, macro blocks, and pre-routed nets within the routing region.


This scenario occurs at the precharge phase of dynamic logic gates, where many gates may be precharged to logic high simultaneously through two RC lines driven by same clock.

when input signals switch in the opposite directions, clock skew increases dramatically with the increase of CC.


We would observe that these results are derived from a design containing only theRNG,soinareal-worlddesigntheRNG clock-rate might deteriorate when generating so many bits.

in such a design the performance of other logic is likely to degrade at a faster rate, so the RNG should never form a performance bottle-neck.


It is important to note that the performability of both the conventional R system and the proposed RI system increase withincreasing supply voltage (and consequently increasing operational frequency), since more recovery executions can be performed within the task deadline.

the performability of the RIsystem is in general better than the R system when the same supplyvoltage is used.


The high-current component typically consisted of a memory load/store instruction and the low-current component consisted of a divide instruction followed by a dependent instruction, resulting in a long pipeline stall.

their di/dt stressmark was manually crafted for a specific microarchitecture based on the knowledge of the current draw of various instructions.


Of course, it is quite difficult to compensate precisely the effect of the non-linearities of the operational amplifiers, and therefore, the best solution is to integrate operational Vdd amplifiers with sufficient high DC gain and settling to make this phenomenon negligible.

optimizing operational amplifiers for fast settling-time and high DC gain is a nonsimple task, since both the aspects leads to contradictory demands: high-gain requirement leads to multistage designs, whereas the high unity-gain frequency requirement calls for a single-stage design.


Our experimental results demonstrate that compared to the unpro-tected case, our scheme provides on average 18 dB better PSNR at the cost of a 35% area and 45% performance overhead.

parti-tioned sub-tables and state-retentive power gating provide 58% reduced leakage energy.


[21] is proven secure in the standard model, its security relies on a new non-standard assumption called linear oracle bilinear Di.e-Hellman assumption.

our protocol is proven secure in the random oracle model assuming the hardness of the standard computational Di.e-Hellman problem.


Leading to the fact that image data storage has been in the RGB format for ease of conversion and processing.

it is also well known in video encoding that human sensitivity to chrominance (or chroma) is less than the sensitivity to luminance (or luma) [12].


Reduced absolute drive currents observed from isolated transistor pairs was not unexpected as it was known from CD SEM analysis that isolated lines were patterning slightly larger than dense lines.

increased variation associated with these devices was not expected from prior analysis.


When A = 1000, the self capacitance is almost neglected and bus-inverting coding should bring no more improvement.

because of the bus-inverting reducing the switches on the bus, the energy consumed by coupling capacitance is also reduced.


Since a binary code is statically generated for a predetermined target BEP, the compiler scheme is useful if the actual BEP is known in advance.

bEP can vary according to core temperature and process variation.


Between 8 and 15 encryption threads, we are above the maximum number of threads that can truly run in parallel over the 8 cores.

the CPU hyperthreading technique (HT) enables the parallel execution of these threads.


This dt means that as di is changed, the ki parameters will also change.

dt the absolute voltage that the Px parameters represent (i.e., 5% or 10% of VDD) will remain .xed.


But if the DFG contains a lot of highly concurrent equal operations with a distance of two, it is bene.cial to implement similar FUs, able to execute that operation, in one FPGA.

a lot of different non-concurrent operations on the critical path force the implementation of FUs, which can execute the different operations, in one FPGA.


Obviously, our proposed scheme needs a larger fault bitmap compared to the naïve way-reduction scheme.

overall area and energy overhead is insignificant.


Speci.cally, an initial voltage assignment with high voltage cells physically close to each other and low voltage cells forming large continuous areas, promises a better voltage island partitioning.

in current industry low power design, people only focus on the maximum power reduction on the cells.


Most of the recently proposed approaches are based on native simulation to achieve high simulation performances and .exibility.

native approaches are suitable only for high level simulation and show their limits if the underlying hardware have to be considered with more details.


If all we need is just a large number of particles, but with similar timescales, we can use Barnes-Hut tree algorithm or Fast Multipole method to reduce the calculation cost per timestep from O(N2) to O(N log N) or O(N).

it is very di.cult to achieve high e.ciency with these algorithms when the timesteps of particles vary widely.


FDS is a popular scheduling technique in high-level synthesis.

here we are using it in another scenario.


Computingkernels, which contain statelessloops(such as vector addition) only, canbeimplemented as simplearithmetic modulesthat operatesonacontinuesdata .ow.

itisstill need to maintain registers and loop counters for stateful loops with loop-carrieddependency(vector summation) and someinitializationlogics(image .lters).


By focusing our investigation on the instruction scheduler, we forfeit lessons that might only be obtained from analyzing other structures.

we note that the .elds in the scheduler payload (see Table 1) mirror the .elds found in many other structures throughout our processor.


On one hand, gate delays of G and Gc in Figure 3(b) are both shorter than the delay of G in Figure 3(a) because of driving less load.

denoting the delay of a gate G driving a total load of C (including the net capacitance and the pin capacitance of the fanout gates) as tG|Cload=C, the total delay decrease can be calculated as: dtG = tG - max{t , t } (3) Cload =CN G ' G Cload =CN CCload =CN C delays of driving gate G1 and G2 are increased because of the additional input capacitance of Gc.


Recently, the work in [13] applies the non-volatile PCRAM for system-level data-retention.

this work aims at retaining only a small amount of key system status data called check-points, instead of the whole SRAM/DRAM content.


The same effect can be achieved by unbalancing the bridge with an additional resistor parallel to R. This may pose a problem due to the packaged pressure sensor.

if the voltage transmitter IC was conformant with IEEE 1149.4, the resistor could easily be applied via AT bus (for example, between pins 4 and 15).


Among our benchmark programs, JESS and JACK have similar character- istics as Scheme programs in the sense that they have few frequently-referenced long-lived objects and that most ob-jects are allocated rather linearly and short-lived.

when comparing the miss ratio curves of JESS and JACK to other Java applications in figure 3, we do not see any signif- icant benefit of direct-mapped caches in these applications.


Those delays that are enforcible by the selected fence are removed from the delay set (lines 16,17) and this selection process goes on until all the delays are enforced (line 14).

this algorithm does not deal with cases such as the one shown in Figure 3 because it is not .ow sensitive.


Although the above proposed method can solve the droplet routing problem in a reasonable runtime by global routing followed by incremental routing.

as the increased design complexity of DMFBs, if the routing paths are restricted to the global routing paths, the freedom of droplets is also restricted, which may cause routability problem.


In previous researches, a hybrid main memory approach of DRAM and PRAM is adopted to make up for the latency and endurance limits of PRAM.

large amount of a main memory is used for page cache to hide disk access latency.


Nanotechnologies offer an alternative to ultimate CMOS for addressing these issues.

the nano-scale feature sizes imply orders of magnitude higher defect/fault rates due to manufacturing challenges and to the sensitivity to environmental conditions.


While designing each component, the circuit designer must guarantee that the component functions correctly under the worst possible simulation corner.

as each component is integrated into different parts of the system, some of the assumptions about the operating conditions might be violated.


This yields Totally Uni-Modular (TUM) constraint matrices thereby guaranteeing integral grid-compliant solutions with LP solvers.

advanced technology nodes introduce per-layer grids or discrete tracks that result into non-TUM constraint matrices for the DRC problem.


2, the duration of the first peak is longer than the thresholdd time to cause voltage emergency.

the ssecond peak is too short to cause it.


When the speci.cation of the converter was given by an algorithm written in Verilog, we had a FPGA with 695 4input LUTs and 70.7 ns delay for Xilinx Virtex XCV150-6 (260pin).

when the speci.cation of the circuit was given by a BDD, and then each node of the BDD is replaced by a multiplexer, we had a FPGA with 1659 4input LUTs and a 33.1 ns delay.


One can generate a similar diagram using transient simulation: the transient waveform for a long sequence of bits is simply shifted and overlaid.

the need to analyze extremely low bit-error-rates for modern high-speed serial links makes transient simulation impractical; bit sequences of lengths in the trillions are needed to generate an eye diagram with su.cient probability resolution to accurately assess low BERs.


Comparison with alternative replacement policies: We have used LRU sofar because the partitioning schemes we compareVantage with are based on LRU.

much prior work has improved on LRU, both in performance and implementation cost.


Figure 6(a) illustrates that our approach initially increases the cache size (mostly L3) to incorporate the working set, which is the most energy ef.cient decision.

a larger cache is not very useful for very large working set sizes and decreasing the size adaptively is the best strategy.


For example, the smaller the area of a box, the less the wirelength can be, since total bounding box is smaller.

boxes with lower utilization lead to less congested placement and result in better wirelength when annealing is performed.


The results show that a simple lastvalue page prediction has the same accuracy as a 512 entries PC-based way-predictor.

it is more energy e.cient (no prediction table reads and fewer eTLB reads) and much easier to implement.


0.02 which translates to a maximum of about 70,000 required power traces [8].

the attack on the protected implementation did not succeed.


1The company responded that the hidden super key is used for failure analysis.

it exactly matches the de.nition for backdoor given by the dictionary: "Backdoor -an undocumented way to get access to a computer system or the data it contains".


Resizing the paths which are sensitive to NBTI e.ect can reduce the e.ect of the path delay increase due to NBTI on the whole circuit.

it will increase the area cost, reference [11] has demonstrates that delay degradation due to NBTI e.ect can be o.set using gate sizing (8.7% average circuit size increase).


Note that a fault may have the same March syndrome under different March tests, and different faults may have the same March syndrome under the same March test.

in Table 1, we see that each fault has a unique March syndrome, i.e., the March-17Ntest algorithm can distinguish all the listed faults.


Simulations show that designs based on the conventional approach can fail to meet the performance or noise margin goals due to the underestimated leakage.

the bitline delay and domino gate robustness are accurately characterized using the proposed method.


As cell size grows, more data flows per physical connection.

for larger cells the link bandwidth is dominated by one flow, increasing again the time to transmit the messages (curves 33.2% and 40%).


Subsequent optimization on the persistent nets can indeed cause small perturbations to the pin locations (as a result of cell sizing, buffer insertion, or other transforms).

our flow has the capability to handle many of these changes (through the incremental route completion of the invalidated persistent global routes) to maintain the validity of the persistent global routes.


However, the digital post processing is somewhat complex, and requires the implementation of an FFT [15].

the FFT algorithm is widely known, and software packages to compute this function are available for almost every language and processor in the market.


If VDD is large enough, then Tsi < TCK for all output bits and there will be no errors.

as VDD is reduced, the circuit becomes slower and below a certain voltage denoted by VDD2, we will have Tsi > TCK .


However, in our work, we find that the two-state core power model gives more than 95% of the core power estimation accuracy for all of our benchmarks.

one state model performs very poorly with its accuracy level of less than 70% for some benchmarks.


It is worth to notice that existing techniques apply usually greedy strategies and deliver satisfactory results.

to the best of our knowledge, no one of these methods can achieve the best results even for a set of simple functions when considering only the literal count metric [13].


All of these Maclaurin polynomials evaluate to non-negative values for 0 = t = 1.

for some of these, the maximal evaluation on [0, 1] is greater than 1.


This approach will not reduce the startup latency for the very first FAST message of an UDP packet, because the first lookup will still imply the three cycle penalty.

as the decompressor can always process one field per cycle and is hence much faster than the microcode engine, the FIFO in between the two units will already contain the new branch address as soon as the microcode engine is finished with the first FAST message.


Metallic CNTs can be removed by selective chemical etching [Zhang 06].

such etching can introduce significant variations in CNFET circuits [Deng 07]  P + d o p e d S e m i c o n d u c t i n g V d d C o n t a c t * C N T s f o r s o u r c e & d r a i n L i t h o g r a p h i c P i t c h ( 6 4 n m = 4 . )


Implicit Learning By Signal Grouping The incremental learn-from-con.ict strategy involves explicitly selecting a correlated pair of signals, assigning their values in the way that it will most likely to cause con.icts, and then utilize the SAT solver to accumulate learned clauses (learned gates).

in implicit learning, signal correlations are used to in.uence the decision variable selection and variable value assignment.


It M T J,mean M T J,mean is because that the driving ability of the NMOS transistor is quickly saturated when Vgs reduces.

the ratio between the standard deviations of the MTJ write currents, i.e., s0.1 /s1.0 , slightly increases when the NMOS transistor IM T J IM T J size grows.


Such a design would allow reusing all the work performed in the front-end of the pipeline, offering significant energy reductions at the expense of a small decrease in performance.

as shown in this paper, such a design can be beneficial for both energy and performance if used in a properly designed architecture.


Combining placement and routing into a joint optimization has also been proposed.

it remains unclear if the bene.ts would be signi.cant enough to justify major changes in commercial tools.


For instance, imagine that a user copies a briefcase folder with the same contents from a device A to devices B and C. Devices B and C can synchronize .les and folders with device A.

they cannot synchronize such .les/folders between them.


From the performance point of view, the input handshake rate of the GALS1 circuit, considering the port controller overhead is equivalent to a 61MHz synchronous circuit, which shows an 11% increase in circuit performance.

gALS2 implementation has an equivalent frequency of 53MHz which is close to the synchronous circuit.


In our case, we also select a .nite collection of distributions from the in.nite set.

in contrast to the heuristic (un-justi.ed) selection which is prone to the above criticism, our selection is justi.ed.


We note that all CFI faults in the controller change the con trol signals going into the datapath.

some changes are such that the register transfer level operation of the datapath is not affected.


CHALLENGES IN GATING OFF PE S 4.1 Terminating threads safely To turn o. a PE completely, the hardware needs to terminate all the threads .rst.

the threads are either in the middle of processing a packet or just .nished processing a packet.


To alleviate this issue, in [4] coordinated accesses to instruction and data memories, enabled by a smart crossbar interconnect that supports broadcasting, is proposed.

the bene.t of broadcasting (up to 40.6% active power savings [4]) relies on lockstep execution of algorithm parts that can be carried out using the single instruction multiple data (SIMD) processing paradigm.


Considering fully random search keys allow in more than 99% ( 21 8 ) of all comparisons stopping the comparison after processing the most signi.cant byte.

in databases, search keys might posses a common pre.x that has to be veri.ed (e.g., when sorting a date .eld).


In interval arithmetic, a classical variable xis represented by an - - = x= x + interval x=[x ,x +] which satis.es x .

the interval arithmetic su.ers the overestimation problem as it often yields an interval that is much wider than the exact range of the function.


Although resolution enhancement techniques can mitigate this manufacturability problem, their capabilities are overstretched by the continuous shrinking of VLSI feature size.

the quality and robustness of lithography directly depend on layout patterns.


In the sequel, we shall O2call this grouping scheme as hyperplane grouping.

any other grouping scheme along a speci.c dimension, such as the one presented in Fig.


When the length of the conductor is scaled to the lengths less than the mean free path of scattering of electrons, we enter a regime of ballistic transport.

the current flowing through the CNTs even in the limit of ballistic transport is limited by the fundamental resistance of 1-D transport, namely, the quantum contact resistance.


Variety of techniques have been proposed to improve Read stability and to reduce the standby power for SRAMs [1].

the reduction of active power still poses a challenge due to difficulty in lowering operating voltages and due to read/halfselect disturb [2], and writeability for SRAMs.


In order to perform system-level power estimation, we need to build power models of all components.

a salient feature of SoC is that it has many heterogeneous components with varying power characteristics, ranging from very regular structures such as on-chip SRAM to irregular custom IP blocks such as video codec.


+i +i There might be more than one range for c and c , and vl vr all combinations should be considered.

the ranges will quickly merge together as the DC regions propagate toward the root node.


In reality bu.ers cannot have negative token count.

there is an interesting situation where a trace models an implementable behavior, even though the trace visits states with negative token counts.


There do exist optimization opportunities in selecting the address bits for index decoding to achieve low miss rate.

indexing optimization [11] is out of the range of this paper.


Using the RUG of Figure 2 and scenarios discussed, we decide to construct a TMR using M1, M2, and M3.

because of utilization of the adders as indicated in the RUG, an extra adder (EA) is needed to construct two TMR structures for adder-based reliability enhancement.


From the viewpoint of low power consumption, carry-chain based implementation might be a better solution if speed was not an important factor.

such structures could not satisfy the requisite performance, or GPC-based approach could have advantages if delay and power product was considered.


So, each discording bit pair contributes the same amount of approximation in the entry generated.

pairs such as 1 - x or 0 - x, have an approximating impact only on one of the patterns (the one with the 0 or 1).


* This work was supported in part by NSF grant CCF-0430063 and by Silicon Graphics Inc.

with communication emerging as a larger power and performance constraint than computation,it may become necessary to understand and leverage the properties of the interconnect at a higher level.


It is based on the fact that, under inversion bias, gate leakage through SiO2 for PMOS transistors is an order of magnitude lower than that of NMOS transistors [19].

the PMOS transistors in the logic tree of a P-type Domino have to be up sized to achieve the same performance as N-type Domino, due to lower mobility.


Models Used for Full-chip Analysis The multi-TSV model in [11] is accurate in a wide range of operating frequencies.

this model is not feasible because of the many parasitic elements in the actual netlist.


Thirdly, it is possible that the circuit performance parameters are highly nonlinear with respect to the design variables.

we want to start with a large design space de.ned by the geometry constraints.


However, even for the worst case GNR width variations studied in this paper, the static power is still signi.cantly lower than the scaled CMOS nodes.

variation in 10-5 source doping level has a very small impact on circuit power, but it has a comparably larger in.uence on the delay and noise margin.


technology [3], is effective in reducing dynamic power consumption quadratically.

supply voltage scaling often requires a reduction in the threshold voltage that increases the subthreshold leakage current exponentially, and hence the leakage power consumption.


If the execution time of Pa2 is small, then Pb1 is preempted by Pa3, resulting in a certain response time of Pb1.

if the execution time of Pa2 is large, then it takes longer time for Pa3 to become ready for execution, and consequently Pb1 has time to .nish its execution without any preemption from Pa3, thus resulting in a smaller response time.


For the analysis we have described here, we assumed a 2D mesh or torus topology and a homogeneous network (that is, all of the links have the same bandwidth).

our model is readily applicable to heterogeneous networks of any topology, though its current implementation only supports 2D mesh and torus networks.


For the fully spatial design, all edges have their own physical wires, allowing LUTs to evaluate and send their results as dictated by precedence without coordination between the LUTs.

for the multicontext design, we must control when graph nodes are evaluated on each physical PE and when an edge is routed on a shared wire.


Under ideal scaling theory, power density remains constant.

we expect power density to scale higher in the future as voltages will not scale down as rapidly as feature size, and clock frequency is increasing faster than transistor speed due to deepening of pipelines.


In general the structure of the data.ow graph, where each algorithmic step is represented as an independent node (Figure 1a), offers some opportunity for pipelining.

the gain in throughput is limited as the graph coarsely subdivides the algorithm in a limited number of steps, each of which can take tens of cycles to execute.


For Canny and Fluid, the computation time of hardware accelerators (Column 8) in the Molen with NoC slightly increases compared to the original Molen (Column 4) because some hardware accelerators have to send their results to more than one local memories.

the accompanied reduction in the communication time results in a lower overall execution time.


STT-RAM Designs Supporting Dual-port Accesses Xiuyuan Bi1, Mohamed Anis Weldon2 and Hai Li1 1Department of Electrical & Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA 2Department of Electrical & Computer Engineering, Polytechnic Institute of NYU, New York, NY, USA Email: {xib5, hal66}@pitt.edu, mweldo01@students.poly.edu Abstract The spin-transfer torque random access memory (STT-RAM) has been widely investigated as a promising candidate to replace the static random access memory (SRAM) as on-chip cache memories.

the existing STT-RAM cell designs can be used for only single-port accesses, which limits the memory access bandwidth and constraints the system performance.


Then, we continue to find more hold-critical data paths based on the new 1 This method only guarantees finding enough hold-critical Hedges to provide a feasible padding solution for the lower bound of the clock period.

the lower bound of required inserted delay is not guaranteed.


Performing local blockage avoidance in Stage 3, manipulates the routes within each tile to avoid blockages, thereby allowing more buffer insertion candidates.

this stage does not disturb the tree topology uncovered from Stage 2.


As it can be seen, merely computing independently and multiplying the logical masking and electrical/latching-window masking probabilities leads to a huge error in the probability of latching the glitch, which can be as large as 3100%.

for smaller glitch duration (80ps), the average error is not very large, due to the fact that most glitches are electrically masked, and therefore, separate and unified methods give similar results.


As noted in Section 4.2 above, a Handel-C subset can be the target of a compilation from model-checked CSP, and there is a toolset which can perform the usual veri.cation activities at each development stage.

the Handel-C compiler is complex and as yet is not known to be amenable to quali.cation.


For example, when N=2 we can dedicate one SDM to each of the four possible insertion policies (00, 01, 10, 11) and use the best insertion policy out of the four for the remaining sets of the cache.

the number of SDMs increases exponentially with the number of concurrently executing applications making this bruteforce approach impractical.


[11]) will not be compromised when Flip-N-Write is in place.

flip-N-Write can help simplify the design of the architectural PRAM optimization strategies since it takes care of unnecessary PRAM updates at the lowest, bit level.


However, as the number of users soars, so does the risk of possible misbehavior; to protect themselves, wireless ISPs already make use of a number of security mechanisms, and require mobile stations to authenticate themselves at the Access Points (APs).

iEEE 802.11 works properly only if the stations also respect the MAC protocol.


L1 caches are typically small, and employ moderate associativities and the write-through policy.

the L2 caches are unified and highly associative.


Such an algorithm is more difficult to implement and may require significantly more CPU time to execute.

a path cache data structure cannot effectively utilize all of the potential information that a node might learn about the state of the network.


The proposed models assume that power dissipation of subsystems is constant among operations.

our experimental data suggests that this is not always the case, especially when a DVFS-enabled CPU is present.


Many research work has tackled this problem in 6T SRAM cells [4, 7] by either reducing or removing the power supply to selected cache blocks.

although leakage currents are reduced, they still persist.


, where are constants known a.., and.. ,..,.. ppriori.


Ideally, with a large enough guardband, one would hope that all causes of potential intermittent retention failures can be avoided at manufacturing time.

there are two disadvantages of using a large guardband.


To make a detour, the simplest way is to connect to the corners of obstacles serially.


Our results show that the PCM/DRAM hybrid main memory with a modest DRAM size can give comparable performance to that of the DRAM only main memory.

the hybrid memory with small DRAMs or large footprint programs can suffer from performance degradation due to the long latency of both PCM writes and write preemption penalty, which requires architectural innovations for exploiting the full potential of PCM write performance.


4.3 Mobile Network using DCF Mode The nodes operating under DCF mode compete with each other to get the wireless resource.

some nodes may not use the resource while the others are occupying it.


Few ADLs allow architecture exploration on multiple abstraction levels, that is, the designer is enabled to thoroughly explore the processor s instruction set before elaborating alternative implementations of the microarchitecture.

a .exible choice of the abstraction level is not only a requirement for the speci.cation of the processor core, but also for the memory attached to it.


The number of unique wires and the fan-out of each wire depend on the type of components being connected, and also on the properties of the pattern set.

in all cases, the number, length, and fan-out of these wires increases as the number of pattern characters is increased.


This result drives more and more people to work on neuromorphic computational paradigms beyond digital logic by replicating the brain s extraordinary computational abilities.

the contemporary neuromorphic system s research is mostly con.ned to algorithm .eld, while the hardware implementations are still built upon the traditional CPU/GPU/FPGA systems, which usually consumes a large volume of memory and computing resources [5], [6].


Increasing the number of levels in the logic network allows more complex functions to be realized within a single gate.

each additional level in.uences the switching speed of the gate.


The additional ability to exhibit application-speci.c features that are not set in stone at fabrication time would suggest recon.gurable architectures as particularly good candidates for being integrated in customizable processors.

many of the processors that are available in the market are not based on recon.gurable architectures.


This is justified since delay analysis seeks a worst-case delay failure.

unlike delay which is localized in space and time, dissipated power is a cumulative parameter which integrates many transitions by all signals.


Note that an unresolved unate clause requires only unassigned literals to be positive.

this constraint of unate clause does not work well for our static MIS because the static MIS is pre-computed before any variable assignment.


Using hotness as the power-off metric (Hoff) can disable the rarely reused slices in these high-utilization workloads.

the Hoff policy misses the power-off opportunity when the workload frequently accesses small amount of hot data, such as in ML1, ML2, HL2, HM1, and ferret.


As opposed to native simulation or compiledsimulation[14,26],binarytranslation usesthe exact address for instructions fetch and data accesses.

the target instructions arefetchedfrom memory only once,fortranslation,beforetheir .rstexecution.The simulator always executesthegeneratedbinaryhost code storedintheTranslationCache.So,to accuratelyaccountforthese accesses,inthiscon.guration, wemodeled theinstruction cache as apuredirectory, such that a simple array accessindicatesiftheinstruction wouldin realitybeinthe cache.


The system and processing memories are split to provide the requiredbandwidth.

architectures targeting mobile applications must ful.ll hard area and power consumption constraints.


When combined with aggressive energy-management techniques, such partitioning enables flexibility with reasonable impact on average power consumption and standby time.

this requires SW to be developed on heterogeneous units and makes HW/SW verification difficult.


This processgenerally requires a physical stimulus.

electrical excitation can be used to facilitate the estimation of the calibration coefficients provided that a model relating the electrical response to the physical response is developed.


If a digital core has micro-farad off-chip-capacitors on the power system as shown in Figure 1(a), the current surge is somewhat covered by the capacitors.

with on-die decoupling capacitance of only a few nano-farads, the electrical charge of the on-die capacitor is not sufficient to cover the current surge; therefore, the power supply voltage of the digital core droops severely, as shown in Figure 2.


First, and more common, is to estimate interconnect as a preprocessor to placement, providing useful information to the placement tool.

a second application is in the design of FPGA architectures ([4], [14], [10], [16]).


The algorithm framework is similar to the Prim s algorithm.

in PD1, we consider both source-to-sink path length and edge length when choosing the next node to add into the tree with the balance controlled by a parameter c. In PD2, a node vi is picked when (l(i, j)p + .


In the current form in which the round-robin arbiter is presented, it does not support preemption.

case current state is when Fi ) case s is when zeroes ) next state = Fi .


Note that the best wiring mode for bridging large distances may not be appropriate for short connections.

if we concentrate on minimizing the use of routing resources (small .


In conclusion, we observe that if the product of the compaction ratio and the percentage of unknown values is low, a Block Compactor with larger parity check column weight leads to higher test quality.

if this product is high, a Block Compactor with a smaller parity column weight is better.


It can be seen these nodes are indeed on the longest paths in both VPR and PATH s results.

the delay produced by both algorithms are far away from the optima.


The constraint corresponding to the objective value will become, nn LL ¯ (s.i + s.i -s.i)si = b (.¯i +¯.i -.i)si (18) i=1 i=1 Here, theparameter b corresponds to the coe.cient of variation.

in this work, the modeling does not consider the randomness in the objective function parameters, and hence this constraint is not utilized at all.


Places all cells in one row optimal, i.e., with minimal total movement.

solves (1) PROGRAMMING the = constraints are just allowed for abutting cells, and not in general for all cells in one row.


With monolithic counters, the .rst counter that over.ows causes re-encryption of the entire memory, so the rate of advance of the fastest-advancing counter controls the re-encryption rate for all blocks in the main memory.

with our split counters, the reencryption rate of a block is determined by the rate of advance of the fastest-advancing counter on that page.


We also rely on the load and store operations of the MIPS ISA to retrieve contents from the memory to the MIPS registers.

itis possibletoextendthe URISCtohaveitsownfaultfree load and store instructions.


In the distance range of LSI (H=1 10pm), the coupling capacitance remains almost constant, which means that the coupling capacitance arises mainly from a parallel-plate capacitance at the intersection.

in the distance range of system LCD circuits (H=1000pm), the coupling capacitance does not converge within 5000pm, because the ground plane locates far way, and then 3D effects of coupling capacitance become prominent.


We observe that, with modulation, the magnitude of noise ampli.cation at the carrier frequency decreases.

the noise ampli.cation at frequencies away from, and in-between, the carriers increases.


14) using 3T FinFET model [41] and MEDICI [42].

standard deviation of SNM in bulk-CMOS SRAM is lower than that in FinFET SRAM.


In reality, it can be implemented more ef.ciently using parallelism.

we are missing implementation details necessary to take advantage of that organization.


We can also discard faulty cache sets and access the main memory instead of LLCs when accessing the specific memory addresses (which correspond to faulty cachesets).

in this case, we may suffer severe performance loss due to frequent main memory accesses.


SE offered better control over simulation and stopping condition making the exploration faster.

if parameters are not tuned properly, simulation can often be prematurely aborted ending up with a local optimum.


and.. to be equalities and value in this case.

if (7) is the dominant constraint, we values such that the objective .. and.. need to find the optimal function (4) or (5) is minimized and constraints (7)  (9) are satisfied.


Hence, it is evident that for smaller designs with loose design constraints, a tree will be the best solution.

our proposed structure can still trade o. cost for better robustness.


Because we add extra bits such as way number bits (3bits) to the write buffer, the energy consumption of the write buffer increases.

the area overhead by the extra bits in the write buffer is low (1.17% in our configuration) compared to the write buffer size.


This is expected because Adjacent fill fills X-bits for shift-in power reduction only, which may result in excessive shift-out power dissipation.

the computational time of S-filling is longer than Adjacent fill because we need to calculate the transition probability in test responses, but it is still acceptable: for the largest ISCAS 89 benchmark circuit, s38584, S-filling takes less than 10 minutes to finish with a 2GHz PC with 1G RAM.


The two proposed solutions differ with respect to the simulation kernel (SystemC or the ISS) that drives the co-simulation.

in both cases the interaction with SystemC simulation sessions is implemented at the kernel level, thus making it transparent to the SystemC code written by the user.


Introduction Chemical-mechanical polishing (CMP) is the enabling technology to attain high levels of planarization [2].

as number of layers increases and line widths shrink, tolerance for topographical imperfections decreases.


Figure 7: A problem in the straight-forward implementation of Borah et al.

we can prove that this problem does not exist in our algorithm.


In practice, the two streams share a lot of common blocks and can be combined to form a more compact stream.

the two computing streams will be executed on separated FPGA accelerator card, which renders such kind of combination of little interests for now.


INTRODUCTION Typically, methods for formal veri.cation of security protocols (among the proposals [12, 22, 10, 8]) do not take time into account, and this choice simpli.es the analysis.

security protocols like distributed programs in general are sensitive to the passage of time.


Also, .Vpp is proportional to programming speed [14, 23] for programming time can be shortened if .Vpp is increased.

the programming performance improvement is at the cost of an increased raw bit error rate (RBER) [23].


The improved memory controller was later used in the MORPHEUS recon.gurable architecture [18].

their controller only provides bandwidth guarantees at a coarse grain level.


The decision has to be made jointly with other design parameters, e.g., task mapping and utilization of redundancy.

the existing work assuming perfect fault detection prohibits the exploration of design alternatives using partial fault detectors.


Note that it is also possible to adopt other distributions.

using other distributions in general does not invalidate the trends observed in our work.


While there is a signi.cant reduction in the energy consumed, such large drops in performance are generally unacceptable.

the loss in performance for memory and cache kernels is small, while the energy ef.ciency improves signi.cantly, pushing the kernels into quadrant The primary reason for this behavior is the large periods of inactivity of the compute resources.


We also note that Rio s quest to reduce latency rules out the use of the standard 802.11 power-saving mode.

many known techniques that trade a little latency for much more e.cient use of the wireless link can bene.t Rio, e.g., data compression [26] and µPM [39].


Keywords: High-level Synthesis, Reconfigurable Processor, Dynamic Reconfiguration 1.

introduction these new processors must be competitive with existing programmable chips, such as CPUs, digital signal processors (DSPs), and field programmable gate arrays (FPGAs).


When we began the work, we intended to use state-of-the-art PD, including fieldwork, scenarios, mock-up, prototypes and Future Laboratories with their 'close-to-real-life' exploration of new designs.

as it turned out, the different kinds of reports from fieldwork, scenarios, mock-ups and prototypes did not function well as 'reminders' or 'guidelines' in our daily work.


In parallel systems, workload completion time is always determined by the slowest thread an e.ect not fully captured in simulations with .xed network latency.

netrace faithfully captures both network e.ects and application dependencies, and is likely a more accurate indicator of NOC s impact on application performance than the full-system results here.


2(a), the internal connection among decap cells induces unwanted timing degradation.


Intel also provides a development kit [1] to directly access to NICs from userland process on an operating system.

they focus on the use of NICs from userland process on general-purpose operating systems.


We expect that the load by Thread1 should return the value C written by Thread2, because that appears to be the value of the most recent write (in causal order, according to the Power ISA s weak ordered memory model).

this code snippet does not guarantee when the tlbie instruction will be observed by Thread2 and thus Thread2 could continue to operate with the old translation of VA1 to PA1.


As Figure 5 shows, the reduction in cost of a single accelerator is not linear with respect to decrease in performance.

combining two similar loops can halve the cost.


Finally, it has recently been shown that these dead cache lines (i.e., the lines that have not been accessed for a while) can be used to hold replicas of the lines in active use to enhance the reliability of the cache data [14].

it is to be noted that an optimization targeting at any one goal can potentially a.ect other goals in the process.


The simplest is static partitioning [5, 13, 14], but these techniques cannot adapt to changing workload behavior.

dCRA [2] partitions dynamically based on memory performance.


Techniques using a combination of RSSI and other measurements may lead to reliable location estimates, as proposed in [2, 3, 15].

nonuniform propagation environments make RSSI methods unreliable and inaccurate.


With equal rationing, neither core has enough cache to obtain any reuse.

with cache hints, the software can free up cache space by zeroing every other access bit.


Disk as the permanent store for video, o.ers the much needed capacity to store large number of videos.

a pure disk-based VoD quickly becomes bandwidth limited and cannot meet the latency requirements for real-time playback of video as the workload scales up without a signi.cant investment on the disk infrastructure.


Compared to the most commonly used representations, sum-of-products and Binary Decision Diagrams (BDDs), AIG s multi-level structure is more ef.cient for manipulating Boolean functions.

equivalence checking with AIGs is less ef.cient because AIGs are not canonical.


In this system, we choose to log the error and continue executing, so that we retain the semantics of the program without any assertions.Wediscuss our error reporting schemeinSection2.7.

for future work we would like to explore the other options above, as well as a programmatic interface that would allowtheprogrammertotestthe conditionsdirectly andtake action in an application-speci.c manner.


On one hand, a very small number of evaluations may determine that the solutions are far from giving a high classi.cation accuracy.

allowing too many function evaluations may contribute to improve the quality of the solution on the training data but at the expense of obtaining an over.tted classi.er.


Finally, we also performed the same code layout optimizations on the operating system.

the improvement in performance was much smaller (3.5%), partly be- cause kernel execution constitutes a small fraction of the overall ex- ecution time.


The only concern of the proposed design in this experiment is the NI component which is located in the middle of synchronous and asynchronous zones.

in the GLAS design synchronization should be done at the boundary of the synchronous and asynchronous regions.


In such a case, the two magnetic domains have the the same current density.

if the two domains are in the opposite resistance states, the current densities of them will be different.


One possible approach for maintaining correct memory state, suggested by Paceline, is to re-fetch the cache-lines that are accessed during the last checkpointed interval into the L1 cache of the leader core [16].

since this might happen often for a dead core, we need a low-cost resynchronization approach that does not require substantial book keeping.


A simplistic method to use this FF library for SER mitigation is to replace each library flipflop in a logic circuit with one of the new variants.

this would impose a flat, delay overhead of at least 62.4ps which is not a viable option for most performance sensitive designs.


On the one hand, such matrix multiplications make the SATD more expensive than SAD.

for both inter and intra prediction, the PSNR and bit-rates resulting from SATD are better than those resulting from SAD [12, 2] because, as stated in [27], considering 4x4 blocks, two among four base functions of H4×4 are the same as for the integer DCT used in H.264/AVC.


Latch-based ASUs are very common in asynchronous micropipelines [12, 4, 3, 13] since they are fast: the latches are normally open, and thus eliminate the control overheads associated with opening them.

precisely because of this, glitches are allowed to pass through the latch, leading to large energy consumption overheads.


In addition to the elasticity information derived from power, now we can clearly distinguish from the saddle-shaped maximum surface that the optimal consolidation factor across multiple load factors is 320.

this value is highly dependent of the choice of tenant utility function, which remains an open issue of operational research for cloud and datacenters.


By carefully controlling the number of partitions, the total number of pins is reduced significantly compared to the direct-addressing scheme.

the design method presented in [17] suffers from several drawbacks.


The vulnerability metric (%V) is also shown in the .gure.

as can be seen with slight increase in F, the rate of decrease in V is signi.cant for small values of F. for F higher than 20%, V decreases at a much slower rate.


Therefore, at least one of the four minterms {m3,m4,m5,m6} is contained in function f.However, no matter which minterm belongs to f ,the value of f z * able set Sa and can be respectively mapped to a pair of availableboolean functions {AND, NAND, OR, NOR, XOR, XNOR}.As both of the expansion variable and its complement can be fedas the select bit of the MUX, the order of the boolean functionpairs can be exchanged.

since each input branch ofthe MUX can only implement four of the six boolean functions({AND, NAND, XOR, XNOR} for negative branch and {OR, ** or fno ¯¯ yx longer stays equal to 3, which contradicts the assumption wehave.


Comparisons between different logic styles are very difficult because of the different strategies for clocking.

we try a comparison between Domino, Clock-Delayed (CD) Domino, AC-TSPC (dual-rail) [3] and the presented self-timed single-rail structure using the scheme of [3].


If there are frequent L2 writes, our compiler will generate hint 01 for X.

hint 00 is generated to indicate that X will not be written frequently.


6.3 Comparison with the FFT-based approachand other acceleration techniques There is no prior published work to accelerate the polygon based lithography image simulation.

the 2D FFT-based image convolution has been extensively studied in various platforms.


Thus, if thermals drive your shrinking chip strategy, it is much better to hold your frequency constant and increase cores by 1.4× with a net area decrease of 1.4× than it is to increase your frequency by 1.4× and shrink your chip by 2×.

there is a concern that even without shrinking chips, the power-density of hotspots is still increasing exponentially, and could be a concern.


1) Average Write/Read Delay Consider the delay for the two basic memory operations, as reported in Table III; as the feature size decreases for the MOSFETs, both delays are reduced.

this is related to the operating frequency of the proposed SRAM cell by two limiting factors.


This approach ful.lls the timing constraint on d1 and d2, regardless of the amount of variation.

the number of required extra crosspoints depends on the maximum variation.


Commands Execution Most global commands can be executed straightforwardly.

local commands have arguments associated with on-screen controls.


Given the high AVFs of the corresponding bits, this MBU will most likely affect the user.

if i6 was omitted from the trees, this particular MBU would be detected, although the word would now be vulnerable to single bit upsets affecting bit i6.


Similarly, [11] argues that interconnects composed of wires having di.erent delay and power characteristics improve the overall ED2 of processor signi.cantly.

evaluation is based on earlier circuit level studies[12][29] ignoring many important components of power such as power due to pipelining bu.ers.


Energy savings are more for benchmarks which cause the processor to run in the high Pstates with CG.

benchmarks which cause a high fraction of C0 state show less benefit since they lead to VR parameters that are close to TDP operation (baseline design).


On the board level, both d and h in (10) are large, making the saturation value of the damping factor very small, causing the board level wires to be almost lossless.

in the case of on-chip interconnect, these values are much smaller and are expected to further decrease in future technologies, making the minimum damping factor a serious limit.


Given a 4 M key sorting problem (which is 32 MB data), the con.guration 27ms )-1 overhead is considerable (1 + = 46% of 32 MB·2 s/2 GB the total time.

given a 400 M key problem (which is 3.2 GB data), the con.guration overhead can be neglected.