The checker describing all possible activity of the interface was too complex to be manageable in synthesis and simulation.

when we expressed the checker as a composition of multiple transaction checkers, we were not only able to verify that the checker was an invariant across the entire simulation, but also observe which transactions was occurring.


As shown in the .gures, DT method yields signi.cant simulation errors, as a consequence of L-1 no longer being very close to a multi-band matrix.

both WD and BM methods yields much better simulation results, as they both preserve the the multi-band entries in L matrix.


It is possible to implement our algorithm in a typical programming language, and call it from the ACL2 theorem prover using the clause-processor mechanism.

the clause-processor mechanism does not guarantee the soundness of the newly integrated system, because the called program may contain .aws.


For example, our prototype platformusestheMSP430F1611 microcontroller whichprovides all of the necessary components.

implementing VHT uses all of the available timer resources, impacting other components like the ADC.


Using virtual reconfigurable architectures constitutes a cheaper solution that can be developed in a shorter time compared to the custom IC solution.

building a reconfigurable architecture on top of another reconfigurable architecture implies inefficient resource utilization, given the reconfiguration level redundancy.


To maintain a design s function, we cannot apply firewall registers to dataflows satisfying Lemma 1.

this will reduce the opportunity of using firewall registers for low power, so we should carefully perform scheduling and binding to avoid such conditions.


There do exist some instances in which the size of the ML-VG and the PD-VG is quadratic.

in practice, the size of the ML-VG and the PD-VG is probably close to loglinear.


Since the redundant path and TGs in the TFU will be exactly reused by the 2D redundant clock tree, TFU can be constructed with little area overhead, while increasing the yield rate as much as that of the double-TSV technique [5] that requires too many new TSVs.

to be practically effective in using TFUs, a number of important issues that have not been fully or never been addressed should be resolved.


Because the fault model used in manufacturing test is defined at gate-level, most testing algorithms are operated at gate-level.

the inputs of functional verification problems are register-transfer level (RTL) descriptions.


They attenuated the forward path signal.

we merely considered that there was a 1 mm air gap between the phantom and the electrode in the simulations.


Because of the complexity of the FIFO description, the compiler could not derive optimal annotations in the modular flow, or rule schedules in the flat flow.

by allowing the designer to alter the annotations of the FIFO module (something he only has to do once and can then reuse in all processor designs), we were able to achieve optimal schedules in all modular compilations.


Such systems are becoming increasingly important in this era when spontaneous multimedia capturing and distribution becomes prevalent.

high-cost and lack of portability limits their usage cases.


INTRODUCTION On-chip cache is an important component in modern processors for achieving high performance.

because of its large area and high access frequency, it also becomes a major power consumer in processors.


Inlining of functions at compile time can also eliminate some control flow dependencies.

we have observed in our application that the worst case situations are often caused by interrupt processing and associated context switching, which is unpredictable at run time or compile time.


Hence, asserting a pair contract requires .rst asserting its component contracts.

to obtain completeness, it would be su.cient to seq these computations together: asrt_too_strict (Pair c f) =  (x, y) -> let x = asrt_too_strict c x y = asrt_too_strict (f x ) y in x seq y seq (x , y ) this implementation would be more strict than necessary as evidenced by the divergence of the following contract assertion.


The presence of recurring phases is evident in all the benchmarks by comparing the number of dynamic phases with the number of static phases.

the degree to which phases recur is reduced by the relatively short benchmark runtimes (2 billion instructions).


The authors in [4] proposed an analytical model of a cell s noise stability which is a measure of how much noise a cell can tolerate before functionally failing.

this method can lead to falsely detecting noise violations [5].


These methods add an additional task to perform profiling, in place of an interrupt [22].

the disadvantages are the same as the interrupt approach.


In addition, simulations cannot be used for area estimation.

prototypes can successfully address all of these problems.


On one hand, a larger sample size leads to a more accurate tra.c estimation and a more e.cient channel allocation for the FERI MAC.

a larger dataset slows down the adaptation of tra.c model to the varying link layer tra.c and aggravates the computation overhead of underwater nodes.


Recovering from RIB has a higher penalty than recovering from IQ because RIB recovery is not selective and the distance from the recovery stage to the resolution stage (forwarding check in STB2) is larger [3].

the total cost computed as the number of forwarding misspeculation multiplied by the misspeculation penalty, may be lower than the degradation of stalling dispatch when IQ is full.


Since Fx is a 0-approximation of Fy, the fault Y stuck-at 0 will always violate the self-testing property as X=1, Y=1 is the only input vector that can test Y stuck-at 0.

for Y stuck-at-0, the input to the checker becomes X=1, Y=0, which is a valid codeword and so cannot detect the fault.


Thus, these inter-stage filters should have high selectivity in order to efficiently attenuate the transmission band.

in the proposed dual-standard DCR RFFE, Figure 1 (b), the inter-stage filters are completely suppressed as it imposes the use of exclusive parallel chains.


These effects have been confirmed by measurements on-die.

a simple excitation model is usually not representative of the worst-case transient scenarios causing the largest voltage droop.


In a custom implementation, a CAM address-match cell is programmable so it can match against any key.

in an ordinary SRAM array, the address-match cell is .xed.


So, Spoly( fi, f j) need not be considered in the Gröbner basis computation.

there is one (and only one) pair of polynomials ( fw, fg) .


Typically, the applications in these domains process continuous streams of such packets.

the processing that happens on a single packet is sequential in nature.


For this reason, disabling of readback of encrypted FPGA bitstreams in Virtex and Spartan devices is not controlled in the encrypted bitstream, but by hard configuration logic of the FPGA.

other attacks may attempt to enable the Internal Configuration Access Port, enable I/O blocks or change clock speed in an attempt to gain access to internal data.


For the invalid cachelines, we propose to simply bit-.ip these cachelines periodically.

as we discussed in Section 3, we need to choose a proper bit-.ipping time interval in order to achieve high-balanced duty cycle ratio of the invalid cachelines as well as minimize the overheads.


This is a reasonable assumption for the 0.25µm-or older technologies.

the critical .eld depends on Vgs in the 65nm-technology, and the BSIM3v3 SPICE model [1] uses 2vsat Ua Ub Ec = [1 + (Vgs + Vt)+ t2 (Vgs + Vt)2], (2)µ0 tox ox to specify this dependency.


As another example, if the number of transmissions is very low, the energy overhead of the victim line (that transitions every 10 cycles) can become a bottleneck.

such cases did not happen in the realistic workloads we experimented with.


Insertion of the large resistance Rin dramatically reduces the transient response of the decap.

starting from 90nm, the oxide thickness is so thin that the designer cannot ignore the increased ESD risk.


Single-stage bypassing consumes more ALMs than the non-bypassed version due to address comparators and data muxes.

twostage bypassing requires an additional address comparator and a wider mux; hence it consumes more ALMs than a single-stage bypass.


At low temperatures, 0o to 30o C, leakage effects are still very weak and the compound effect of the variation in all other factors dominates the decay behavior of the 4T cell.

as temperature rises, leakage currents become the dominant factor and determine the overall behavior of the sensor.


A high-valued output p will be obtained when the peak current through the driver is above the peak current of the load, for the critical bias voltages.

vout will be at low level if the sequence is the inverse.


Such attacks assume that the attacker is unimpeded in obtaining CRPs from the hardware.

in a real-world scenario, depending on the implementation, obtaining a suf.cient amount of CRPs may be impossible.


For circuits that are fairly small, or with very easy requirements, such an algorithm might achieve usable results with very fast runtimes.

if the logic blocks are placed very close together, the resultant congestion will affect the route times for the worse.


The solution of equation (4) (5) and (6) determines function f (x).

the function f (x)may have extremum inside [c1,cn], This happens when c1 <-a2/(2a1)<cn.


1) Integrated placement and routing approach (IPR) 2) ROOSTER followed by FastRoute2.0 (ROOSTER + FR2.0) 3) Routability-driven FastPlace followed by FastRoute2.0 (R-FastPlace + FR2.0) 4) FastPlace followed by FastRoute2.0 (FastPlace + FR2.0) For Routability-driven FastPlace, we follow the framework of IPR.

instead of applying global routing to get accurate routabilityinformation, we simply construct rectilinear Steiner minimal Steiner trees(RSMT) to break multi-pin nets into 2-pin nets and use probabilisticcongestion model to get the congestion map.


Hence, in some cases, depending on the constraints, the bene.t from heterogeneity may be limited.

in a number of cases (for speci.c sets of workloads, server cost ratios and energy cost), heterogeneity may yield substantial cost bene.ts, which may translate into millions of dollars of cost savings.


reconfigure new-type decoupling-capacitor cells for timing and voltage drop [13].

functional ECO is considered in recent literature [10][11][12].


They take into account the relative lifetime differences between arrays ( inter in-place ) and between the scalars covered by each array ( intra in-place ).

it is not clear whether the copy candidates can be also parts of arrays instead of entire arrays (and if so, how they identify these parts) since the access patterns are, in general, not uniform.


As Don Norman pointed out, this trend can be interpreted as the return to physical devices, where we control things through physical body movements, by turning, moving, and manipulating the appropriate mechanical devices [8].

whether they are single-or multi-user, we found that the themes and goals of games still tend to be competitive in nature.


Given that only 32B of data can be read/written with BC4, employing it for all the requests can have a negative impact on the performance.

the timing constraints, namely tCC D and tBU RST of OTF remain same as those of BL8[2].


While lM is provided in manufacturer datasheets, lS is typically not.

im and Shin [9] relate the endurance for a speci.c .ash device that explicitly provides SLC and MLC modes.


In some aspects, the proposed design flow is similar to the compilation of applications for processors because in both cases the datapath is fixed during the mapping process.

compilers rely on instruction-set (or microcode) to abstract out the functionality of processor s datapath and assume that the processor translates such abstractions to proper control signals.


Similarly, a 1D-STL-FFT based row-column procedure can be used to get those related FTi,l's.

the form of equation (29) can not be utilized to calculate PTil's because the lengths of those related FTi,l's in row and column directions are less than 2M and 2N, respectively.


Twr is often defined as the time when the node storing 1 is pulled down from VDD to a critical low value.

the proper definition of this critical low value is not so clear.


These dependencies can be offset by using orientationindependent features and training the machine learning algorithm with each dependency case.

addressing these dependencies adds to the cost and complexity of the system, increasing power consumption.


For a considerable number of benchmarks, the potential improvement (the gap between LRU and OPT) in larger L2 caches is indeed small, so all proposals perform similarly.

for some high MPKI benchmarks, like art and mcf, LRF still provides a good performance.


N-detect test compaction Recently, a physically-aware N-detectATPG algorithm has been developed [10].

a signi.cant issue that arises with N-detectistheexpanded test-setsizethat results for both the traditional metric [2, 3, 5] and the physicallyaware metric [10].


INTRODUCTION The last decade has seen the development of nanometric circuits as MOSFET-based design has moved to feature sizes well below 100 nm.

concerns over short channel effects, ultrathin gate leakage, doping fluctuations, and large power dissipation have been widely reported for nanoscale integrated.


In a naive manner, we can inject a partial-state onto the circuit, imply its necessary logic values and check if it satis.es the criteria given in Theorem 1.

checking this for all possible partial-state assignments is impractical even for medium-sized designs.


[1]) to do so have di.culty scaling without grossly approximating the circuit behaviour.

the computational complexity of SPICE simulations forces us to make compromises when using statistical techniques.


As a result, there is only one redundant via candidate that can be selected.

if we are allowed to bend existing wires, we can create one more redundant via candidate d3 for v2, as shown in Figure 1(b).


In this scheme, an external spare cache is used to provide redundancy; thus, applying the interconnection network allows a limited redundancy borrowing across the statically specified, fixed-size groups.

its interconnection network has a noticeable area overhead and power consumption cost.


For example, circuits with registers in general is not suitable for the proposed method.

if the data bits stored in the register is known a prior to be with short memory , such as the SAR ADC illustrated in the next section, then the proposed method is applicable.


Zero body bias is the initial condition and nMOS and pMOS are not balanced.

the drive strength of pMOS and nMOS are balanced by optimizing forward body biasing or reverse body biasing as shown in Table I.


It is well known that clock and power gating are very effective energy saving techniques with relatively low time and energy overheads.

careful power gating and DVS settings are still necessary when considering the entire task schedule, since their aggregate overheads may greatly impact the execution time.


Depending on the access pattern, the design will be able to recover, at the most, only 50% of the [PC lost.

the proposed dynamic allocation of registers through duplication increases the chance of using those faster registers.


Simulation results indicate that such hybrid dynamic OR gates can achieve 60-80% lower switchingpower and almost zero leakage power consumption with minor delay penalty.

the hybrid gate outperforms its CMOS counterpartboth in terms of delay and switching power consumption with increase in fan-in beyond 12.


Equation 4 contains higher order terms and cross product terms, thereby implying that the distribution of first moments is not exactly Gaussian.

experimentally, we find that the higher order terms are not significant and can be neglected without loss of accuracy (results are detailed later in this section).


Due to the presence of complex geometry and the complicated boundary condition, the silicon junction temperature profile can not be solved analytically.

a numerical solution can be found by finite difference approaches and approximation schemes.


SB adopts a linear classi.er, which essentially .nds a linear hyperplane separating the successful region and fail region.

in this example, it is impossible to separate all failed samples from the successful ones using just a linear hyperplane.


CLFF has smaller area than NLFF, because 8 2NAND-gates in NLFF are replaced with 6 2NOR/2NAND-gates in CLFF.

reducing the gates creates a racing problem.


In order to simplify the model, we found that the delay dependence on each voltage is near-linear in the (narrow) range of valid voltages.

to be more accurate, we have used a quadratic polynomial to represent the dependence of delay on each voltage, and made allowance for cross-product terms, by using a template expression for delay as follows: .


Ideally, synthesis tools are able to handle master-servant latch retiming and move the servant latch into the middle of combinational logic.

dC does not support3 retiming in such a way.


The number of small critical section (CS) locks, number of long CS locks, number of processing elements (PEs) and the type of the PEs are parameters that are used by PARLAK to build the lock cache.

pARLAK uses a library of components of the base architectures  built previously of the lock cache.


For reference these two previous works are summarised here in Section 2.

the implemented CWT transfer function in [3] is not identical between di.erent microchips.


Data and Control Message Format The message set supported by the target DSP and FPGA platforms are identical to those supported by the workstation and Serf.

the physical link may be different (e.g.


This condition is also necessary in order to have a mutually disjoint partition of P processors among k applications.

if this condition is not true, we can adopt clustering schemes and treat applications that display symbiotic interaction as one unit.


It should be notedd that the analyssis above was ddone using a linear electric field.

in multiferroic materials the polarization also shoows its own hhysteresis (Figuure 5).


For example, a digital core can only be in the neighborhood of an analog core if it is being reused by this last one, since it can not propagate an analog signal.

a digital core b may be a neighbor of a digital core a in both directions.


5.3 BlockandBlockHistoryQueue[i]Size If we choose a large SigRace block then, with the same BlockHistoryQueue[i] (BHQ[i]) size, we can monitor a larger instruction window for possible data races.

as the block size increases, the signature false-positive rate also increases.


S(t *) s level crossing time k ** is ideal without any timing error.

sj(tkl ) s crossing point has the effect of timing jitter.


Therefore, circuit simulations are required to verify whether they pass the performance specification or not.

simulate all these samples may be still inefficient.


Related work in the literature that makes use of circuit performance in OPC is [5], where the tolerable EPE were predetermined from the timing analysis and the problem was solved as a constrained OPC insertion with geometry matching.

saving of the mask cost is still limited to the non-critical nodes.


This is the same heuristic used by the BASE scheduling algorithm for a clustered processor without L0 buffers.

the heuristic to sort the set P for memory instructions also considers the number of free L0 entries in each cluster and whether the instruction belongs to a memory dependent set or not.


On the other hand, in the full Illinois MESI protocol, a block can be preferentially retrieved from another cache rather than from memory.

when multiple caches share a copy, a voting mechanism is required to decide which cache will supply the data, and this voting mechanism can bene.t from the use of low latency wires.


The performance is also extremely good, with the clock rate usually limited by the clock distribution network for n = 512.

the big drawback of this method is that to createalongperiod sequence,alargenumber ofLUT-FFpairs must be used.


A tremendous amount of research has been dedicated to optimizing multipliers for low power, high speed, and area e.ciency [1, 2, 3].

continued e.ort is being made for further improving multipliers.


Currently, the only parameter that cannot be directly measured is load or queuing delay.

performance monitoring tools can measure average memory latency trivially.


For the bulk current, the effect is seen as a decrease in the amplitude without a change in the pulsewidth.

input transition time dependency is always important, whether the output is switching or not.


NanoTCAD ViDES considers phase coherence of scattering at the two SBs and the energy pro.le is more rigorous, which explains the oscillating nature of the computed transmission coef.cient.

since this treatment is at the atomic level and extremely computationally intensive, it is not feasible in semi-classical approaches.


Here it is important to note that even though MP runs quickly on a high performance microprocessor, the achieved speed falls short for the high data rate required by 3G/4G wireless systems.

the proposed MP core meets the 3G/4G speed requirements, justifying its applicability for implementation in future generations of wireless communications systems.


Since single-driver routing reduces the area required for routing tracks, this may be one reason for the di.erence.

it is alsopossible, that the fully optimized (for area-delay product) electrical designs, which may have reduced transistor sizes for the smaller LUT sizes, also contributed to this di.erence.


In this case, we can .rst set either T or D to an identity matrix, and then use Eq (4), Eq (7) and Eq (8) to determine the other one to localize the target array.

in cases where there are multiple loop nests in the whole program and multiple arrays accessed by these loop nests, to localize the maximum number of arrays (this means we can reduce the inter-thread con.icts for the maximum number of arrays), which one of these two matrices should be determined .rst for an array becomes crucial.


Table I expresses a group of layer constraints refering to a speci.c technology.

according to rule complexity of advanced technologies, the built-in constraint group is inadequate for the new generation technology.


The reason for this is once again frequent accesses to shared data structures without locks which cause frequent data races and put significant stress on the memory system.

as one might expect, streaming applications are least sensitive to the controller latencies because of their latency tolerant nature.


master processor are normally executed by the Microprocessor Unit itself.

when a set instruction is decoded, the arbiter downloads the bit-stream of a speci.ed Custom Computing Unit (CCU) onto the recon.gurable logic.


We can also see that the time spent inside the handler recovering from miss-speculation is relatively less (about 5%), owing to small number of missspeculations.

signi.cant time (about 58%) was spent performing copies.


eparedu .IntelCorporation,Hillsboro,ORkaiyuan.chao@intel.com ABSTRACT In modern VLSI manufacturing processes, dummy .lls are widely used to adjust local metal density in order to improve layout uniformity and yield optimization.

the introduction of a large amount of dummy features also affects wire electrical properties.


k-means was successfully accelerated and performs substantially better on the iSSD than host CPUs with 24 or more FMCs.

string_match required as many as 40 FMCs to outperform host CPUs.


We have observed that memory dependent sets tend to be small in all benchmarks except in epicdec, pgpdec, pgpenc and rasta.

most memory dependences in these benchmarks are conservative and can be eliminated by code specialization [4].


4.2.1 High-level Approximation Models Any approximate computing technique can be thought of as introducing errors in the computations that are being approximated.

these errors are usually constrained by design such that the application output quality is not drastically impacted.


The extra load on L1 links is expected since indirect routing doubles the number of hops on an average.

unlike the benchmarks we have seen so far, the maximum traf.c is lower for direct routing with randomized placements and minimal blocking (RDN and RDR).


Then, for each access subgraph whose variables are all in Vgood , we use the corresponding previous path covers as the path covers for the current reschedule.

for the variables in Vbad , we apply Solve-GOA to the access subgraph for Vbad, and generate new access subgraphs and their path covers.


If a configuration memory bit that controls a resource in a logic cell is stuck,this fault is detected by the tests for the corresponding resource.

the faulty resource and the stuck fault in its controlling configuration bit cannot be distinguished,unless the configuration memory has a readback feature that can detect the stuck bit.


On the one hand, the pseudo-input part (PSI) of the excitation pattern (the internal scan chain part) is generated through functional justi.cation, i.e., load the pseudo-output (PSO) of the second vector.

the PI part is provided using the functional inputs by setting the provider cores in the producer DELTEST mode.


I. INT RO DUCT ION Using pre-designed cores to implement a system-on-chip can signi.cantly shorten the design turnaround time and time-tomarket.

this advantage brings with itself many challenges for SoC testing.


This harness has to be faithful so that the symbolic execution of the virtual device will not generate too many paths infeasible in the real device.

it has to be simple enough so that symbolic engine can handle the symbolic execution ef.ciently.


Post-Routing Redundant Via Insertion and Line End Extension with Via Density Consideration * Kuang-Yao Lee Ting-Chi Wang Kai-Yuan Chao Department of Computer Science National Tsing Hua University Hsinchu, Taiwan Department of Computer Science National Tsing Hua University Hsinchu, Taiwan Intel Corporation Hillsboro, OR 97124 kaiyuan.chao@intel.com d924347@oz.nthu.edu.tw tcwang@cs.nthu.edu.tw Abstract - Redundant via insertion and line end extension employed in the post-routing stage are two well known and highly recommended techniques to reduce yield loss due to via failure.

if the amount of inserted redundant vias is not well controlled, it could violate via density rules and adversely worsen the yield and reliability of the design.


To reduce log sizes, software-only replay systems commonly include disk state within checkpoints and allow replaying software to recreate disk state without logging it explicitly in the same way replaying software recreates memory state [6].

experiments showed that the hardware-level Interleaving log accounts for the majority of data within our replay logs, thus obviating the need to introduce the complexities of including disk state within our checkpoints.


Both memory latency and bandwidth become critical.

for highperformance DRAM memories, thermal control has already become a realistic issue [27].


To accurately determine device headings, Headio computes orientations of the detected ceiling edges relative to the device.

due to users arbitrary phone placements, ceiling images captured using the device s front-facing camera may suffer from horizontal heading deviations and perspective distortions, which cause signi.cant heading errors.


This will save the computational depth from 5 levels in the accelerated MP scheme to at most 2 levels, which improve decoding throughput.

by adapting this novel decoding scheme, only one message sum rather than at most 12 message ( of each column is required for storage, which helps reduce area cost.


Consequently, this work underlines that real-world tra.c captures have to be handled with care by researchers and operators.

this paper also demonstrates that protecting privacy of end users is di.cult when access to tra.c traces is available  even with anonymisation techniques applied.


This example illustrates that the net ordering and track assignment can have impact on the required number of tracks required for global routing.

the net ordering or track assignment step is typically performed after global routing.


Floorplan Driven Leakage Power Aware IP-Based SoC Design Space Exploration * Aseem Gupta , Nikil Dutt , Fadi Kurdahi Center for Embedded Computer Systems University of California, Irvine Irvine, CA 92697 USA {aseemg,dutt,kurdahi}@uci.edu ABSTRACT Multi-million gate System-on-Chip (SoC) designs increasingly rely on Intellectual Property (IP) blocks.

due to technology scaling the leakage power consumption of the IP blocks has risen thus leading to possible thermal runaway.


We observe that for low communication loads, the latency reduction is similar for all three architectures, around 22%.

at loads higher than 3.4 the relatively small number of links of the 4 × 4 NoC get congested and response times grow unboundedly.


It is well known that the problem of minimizing the depth can be solved optimally in polynomial time using dynamic programming [6, 15].

we also target areaminimization as a secondary objective, which is known to be NP-hard for LUTs of size three and greater [7, 16].


This modeling perspective is very attractive, since it provides a more comprehensive view of how traffic behaves.

from the point of view of its analytical treatment, the success of this formulation is rather limited.


3.3 Exploiting the Critical Path QB-SyncFollow, QB-Sharing and QB-SyncSharing The most basic quantum building policy, QB-Count, produces quanta based on counting instructions and breaking a quantum when a deterministic, target number of instructions is reached.

instruction-count based quantum building does not capture the fact that threads do not have the same rate of progress.


With smaller heaps and more garbage collections, IQ, ROB, and L2 cache s energy reduction on the mutator drops.

l1D and L1I caches adaptation efficiencies rarely changes as heap size decreases.


Considering that a typical Duracell alkaline battery is rated at 2850 mAh, dividing this value with the average current yields an expected lifetime of 282 days.

average current measurements can be inaccurate, and actual battery life varies depending on the load.


For example if two components share the same privilege level and one component is compromised, the attacker will also gain access to the next component.

if these two components each have distinct privilege levels then one exploited component will not provide access to another.


During this stage, potential match locations can be quickly identi.ed.

this stage could introduce rounding errors since it is not necessary for every rectangle in the layout and the range pattern to align with the grid.


In the dataset used, for PP onset types, this improvement is of more than 30%.

the improvements brought by the RCD function to the CD function are not as relevant and for the Mix onset class the RCD performs 3 to 4% worse than the CD function.


The management of these entries also makes the design quite complex.

modern processors need to bu.er a large number of in.ight instructions to partially hide the relatively long and perhaps still increasing memory latency.


Ceq can be reduced by increasing G and Cgdf .

g cannot be increased to an arbitrarily large value for a constant RL, since it increases Ci.


The rewriter modi.es the different CFIs to jump to the appropriate entry point.

some CFIs cannot have their addresses placed in the table because their destinations are not known until runtime.


Static schemes with lower K turn off the lasers quickly, saving significant laser energy at low injection rates.

they don t provide enough throughput under heavy utilization, increasing the overall energy consumption.


On the one hand, when a low con.dence branch is actually mispredicted, the control independent loads may have generated useful prefetches.

when a low con.dence branch is actually a correctly predicted branch, not all the right path loads have been blocked, reducing the potential performance degradation.


Using 4-block super-blocks reduces tag area by 70% compared to a conventional cache.

figure 4(a) illustrates that Singletons, Pairs, and Trios such as, super-blocks D, C, and A, respectively result in internal fragmentation, which can lead to significantly higher miss rates [31].


In addition, wave-pipelining does not inherently support latch-based design-for-test (DFT) techniques that are critical in the debug and test of a microprocessor, reducing yields even further.

it is easy to integrate DFT scan elements inside pipeline latches that allow their state to be either observed or controlled (preferably both).


Most existing studies assume that a void occurs when the atomic concentration drops down to a speci.c percentage.

there is no clear answer on how low the concentration threshold should be to declare a void.1 Therefore, we describe a continuous resistivity increase when atomic concentration decreases, but vary the in.nite resistivity values from 32.0 to 300.0 (see Func 32.0 to Func 300.0 in Figure 9(a)).


In practice, a linked list traversal on every cache line evic- tion is far too costly.

the sharer must be removed from the list or repeated evictions and requests can cause the list to grow without bound.


DDF is the most expressive model (in fact, it is Touring-equivalent), but it is very hard to analyze and to prove properties on its ex- ecution (even testing for termination is undecidable in general DDFs).

sDF cannot fully express control- dominated behavior (e.g., conditional execution), but it can be analyzed very eifl~clently.


11%) of dereferences reported as unsafe by our analysis fall under this category, implying that recursive data structures and array accesses are ubiquitous in Java programs.

handling these in a precise and scalable way is quite dif.cult.


As can be seen in Figure 11, the static code size between thedi.erent machines are all relatively close(for example MM is 83 instructions instead of the 73 from in the original GLIFT machine) with only a few glaring exceptions (AES is 2X bigger and BSort is 5X bigger).

even though AES is 2X bigger, it is approximately 68X faster using Leases instead of the original GLIFT ISA.


Putting decoder in pipeline reduces the clock cycle time requirement and enhances the bandwidth.

the cache is still not capable of limiting the overall cache delay in pipeline stages to single clock cycle (Fig.


This leads to the highest number of SLDL blocks and the greatest mapping .exibility.

with many trivial blocks that potentially only contribute negligibly to the overall speci.cation execution time, this only leads to an unnecessary high degree of freedom.


2(a) can be collapsed into a single threshold node.

choosing which node to collapse presents a problem.


Thus, the proposed strategy is better than both the conventional sequences in terms of memory accesses.

it has an additional compute overhead with respect to row sequence, as the Type 0 0 operation count comparison goes as: #Type 0 0...... < #Type 0 0...... < #Type 0 0...... (from Equation 2 and Table I) with reverse ordering for Type X Y.


INTRODUCTION The predicted power and performance limitations of end-oflife CMOS are encouraging researchers to investigate new technologies for computation [1].

to date, investigators have had little success in identifying technologies that can compete with CMOS when using charge based Boolean logic.


To compute the correlation functions for all possible values of n( KnK) results in a com == plexity O(K2).

we later show that we can restrict n to values less than the response time of the power grid without loss in accuracy, which is significantly smaller than K for large vector sequences and hence, the complexity is linear with K. In the next subsection, we describe the computation of mean and standard deviation of voltage supply fluctuations, using the statistical parameters of block currents as derived in this section.


The proposed solution builds on the workof [9] and [20], which demonstrate that transition-signalingsingle-rail bundled data can be ef.ciently employed in basicrouting and arbitration functions.

[9] and [20] targetonly simple tree-based switch architectures, while this workaddresses the intricacy of a full 5-ported switch design.


Further calculations lead to even better results: By simply taking the mean of the .ve devices, we arrive at a very close match to the values measured by the TSI DustTrak .

this is not generalizable and only limited trust can be put into the values of a single device.


For commercial bulk CMOS standard cell library operating at super-threshold Vdd supply voltages, the worst-case (longest) path delay occurs at the highest temperature.

in the near/subthreshold regime [12, 13] or in high-vt devices [14], it has been reported that the delay of these circuits decreases with increasing temperature.


If the input rates are too high, the buffers will over.ow.

too low a rate will lead to play-out buffer under.ow and hence, loss of video output quality.


=0, the wirelength of the .nal tree increases by 2.3 % compared to the initial preliminary topology.

as we replace the topologies of most nets in the .nal solution by a shorter Steiner tree (cf.


Similarly Gates 3 and 4 could be clustered together.

gates 1 and 7 are poor choices to cluster as their means are very different and their correlation is also low.


Signi.cant accuracy improvement has been achieved in statistical timing analysis, e.g., by including into consideration correlations between process and system runtime variations [2, 3], multiple-gate-input switching [1], crosstalk coupling [7, 8], etc.

a fundamental problem remains in achieving accurate VLSI statistical timing analysis, which is addressed in this paper.


5 illustrates the complete result of the simple error modeling for bits 3 5 and it captures the general behavior of the VNU before saturation.

5.2 VNU with registers after saturation placing the registers after the saturation operation yields contrasting results.


In addition, their results show improvement of congestion.

they do not formulate the scan chain optimization as an ECO problem.


If the threshold P is low, the gateway nodes could identify the attack more accurately, thus achieving higher detection ratios.

this could lead to high false positive ratios.


Finally, the gate voltage level of Ninv transistor goes to 0V .

when the gate voltage of VDD VDD gated- VDD  clock gatedgatedclockclock CKEN PGEN CKEN VSS (a) (b) (c) Fig.


This is the only prior work to our knowledge that speci.cally deals with cache partitioning for multithreaded applications.

it is not directly applicable to multiple multithreaded applications as it does not distinguishbetween threads of di.erent applications.


Since details of SSD hardware design, especially their FTL algorithms, are regarded as the intellectual property of SSD manufacturers and remain highly con.dential, we can only speculate about detailed SSD internals and we may not be able to explain all performance behavior observed on SSD hardware.

our intention is not to reverse engineer the internal design of SSDs.


Therefore all layouts inspected will have the same regularity and that is why we are not interested in using this extreme.

the highest LA that can be considered is the complete layout layer (Figure 1b).


Prefetching fundamentally relies on address prediction [13], [12], [10].

such prediction is across instructions (i.e., one needs to predict addresses that will be accessed by future instructions).


It is because a small DRAM bu.er already .lters out many sub-page writes, as the .rst working sets of sub-page writes are small in the two traces.

with 16KB and 32KB pages, the reductions increase, by 21% with 16KB page and by 30% with 32KB page in Financial.


As long as no exceptions are thrown, the Default BBA does not cause any inaccuracies.

in the case of an exception, CProf s assumption that all bytecodes in the BB would be executed is violated, if the exception-throwing bytecode is not the last one in its BB.


For quiet supply, setup and hold margins are half-UI when the strobe itself is delayed by half-UI to sample right in the center of the UI.

supply noise has the effect of slowing down or speeding up signal edges, resulting in timing margin loss that is termed as jitter.


For example in [18], Feuer s model [13] has been modi.ed and used to model the wirelength requirements of designs mapped to FPGAs.

this work did not focus on the impact of architecture on wirelength.


6 shows, circuit noise as well as other nonidealities in the .rst integrator occur unshaped at the output of the modulator.

errors of the second and third integrator, Figure 7.


In the results we have shown so far, our classi.ers are built using training data from all the users and tested on di.erent data from the same users.

a more threatening scenario arises if we can show that it is feasible to train a classi.er with data from a set of users to infer taps from people not involved in the training phase.


When a wires must be increased by more than 100% of their normal width, block is turned on from its idle mode, it draws large current from which means their current densities exceed 2x of the maximum power supply, and thus causes its neighboring blocks to allowed.

since power noise is not always present, a 2x maximum current density improvement can still be considered EM-safe for these wires.


For the 0ºdirection, the image of the right eye without brightness correctionis brighter than that of the left eye, but the brightness of bothimages with brightness correction are identical.

for the 90º direction, brightness of both images are equal in both cases because the entry angle of each projector s light is almost the same.


To operate within the power budget of a DDR3 DIMM, bit-serial search is employed.

as the search width increases, bit serial search becomes less energy e.cient than the 128-bit search mechanism used in the TCAM DIMM design.


Quickly increasing the threshold allows the DSSG to quickly move out of the program areas where the functional units are heavily used.

slowly reducing the threshold ensures that the DSSG does not erroneously follow a brief period of inactivity.


[31] also described a technique to selectively refreshDRAM rows based on their access pattern.

the techniquebased on the limited explanation in the patent can lead to situationswhere the data of a row may be destroyed because it is not refreshedin time.


For formulation of the optimization problem this order is not obligatory.

without those constraints, the yield is a multi-modal function of voltage levels, because any permutation transforms the vector of optimal voltages into another optimal solution.


Williams Implementation Group Synopsys, Inc. Broomfield, CO 80020 Tel : 650-584-4867 Fax : 617-600-9697 e-mail: tww@synopsys.com  Figure 1.

relative improvement in laptop computing technology as more and more transistors are packed closer and closer together, the ability to supply power to, and dissipate heat from, these circuits is becoming harder to accomplish in a reliable, efficient, and cost-effective fashion.


The maximum current-per-width is 2.5X larger than that at the minimum channel length.

using a longer channel length can have a negative impact on device capacitance which can affect the CV/I delay.


But it must be mentioned that this performance is available for up to 16 M keys or (64 MB key storage) where we require three times of streaming the problem through the FPGA, what is then slightly slower.

by adding a second memory port to the system and using partial run-time recon.guration, the FPGA will outperform the GPU in speed.


At VBS= 3V, the mismatch measured for the small 10-6 transistors is in good agreement with the value estimated by our 10-10 IB(A) model.

values of Noi for the small transistors different from those measured for the large transistors were chosen in order to obtain better fitting of the curves.


The possibility to use UML 1.x for system design [4,5] started already at Cadence Design Systems in 1999.

the general opinion was that UML (before version 2.0) was not mature enough as a system design language, in particular if compared to other emerging system design environments.


process splitting, process merging) as optimization techniques.

global optimizations are only possible, if all processes are merged into a single process resulting in a strongly increased latency.


As shown in the table, our algorithm can achieve placement solutions without any routing over.ows on all test cases.

the wirelength-driven NTUplace3 and mPL6 generate many over.ows in all cases since they tend to pack blocks together during wirelength optimization.


LRU, PLRU, and FIFO, can be represented this way.

our approach is not in general limited to policies that allow this kind of representation.


Camposano s path-based scheduling [18] and Wakabayashi s condition vector-based scheduling [19] were two noticeable works in the early 1990s.

camposano s work enumerates all execution paths, which could be exponential in number, while Wakabayashi s work involves a lot of complication in scheduling due to the simultaneous consideration of conditional and unconditional resource sharing by operations.


These early design automation techniques are useful for biochip design and rapid prototyping, but they all rely on the availability of a direct-addressing scheme [13].

as discussed in Section 1, direct-addressing suffers from the drawback of higher wiring complexity.


If the metadata is stored alongside data in the same pages, then 29 blocks (and their metadata) could be stored per page (as in [4]).

a channel typically has 8 16 banks, and thus the interleaved scheme will have only 232 464 metadata entries in open row-buffers per channel8.if the metadata was stored separately, we can store 512 metadata entries per page increasing the likelihood of getting more row-buffer hits.


With power consumption already a key limiter on computational density, there is pressure to reduce the signaling voltage swing as much as possible.

since the con.guration SRAMs do not switch, they can use a higher nominal Vt and voltage that reduces their sensitivity to variation.


Meanwhile, simple division of the output current of a differential pair by a high ratio has been widely considered an expensive technique in terms of area [2].

the use of series parallel division of current in an OTA as in Fig.1 [9,10], allows the implementation of an area efficient current divider.


In addition, as discussed in [1], ATE generates continuous test data, and CUTs expect the same traf.c shape with zerojitter requirement.

if using NoC-TAM scheme, shared channels, shared routers, and load .uctuation (i.e., test data are condensed into bursty format during transmission) render traf.c jitter an inevitable phenomenon.


Researchers have addressed each of these effects throughextensions to the basic cell-based delay (and slope) models.

this profusion of delay models vastly complicates the library development flow as well as the static timingflow during design.


For t = 4, Dirt and Unigine su.er from at least 1% additional LLC misses.

assassin s Creed delivers the best performance for t = 2 saving more than 4% LLC misses relative to t = 16.


Small segmentation deviations, as our experiments show, do not have a signi.cant impact on the .nal chroma templates.

severe segmentation errors that are mainly caused by structural di.erencesbetween thevarious stanzas maydistort the .nal results, as is also illustrated by Fig.


At design time, peak power budget for on-chip communication is ensured by setting communication parameters like maximum bandwidth and communication routing [6].

design time peak power management lacks adaptability which can lead to performance degradation.


In [4, 13], the authors consider both error frequency and relative error metrics.

distinct solutions are provided and the two constraints are never explored jointly.


As we have seen, the reduction in the utilization of fast ALU is largest.

in the case of bzip2, ED2P is not reduced at all.


On one hand, sacrificing security for testability by continuing the scan-based DFT restricts its use in privacy sensitive applications.

sacrificing testability for security by abandoning scan-based DFT hurts product quality.


The system allocates8-bitlocaladdressestoeachlightingelements,anditturnson the LEDs according to their ID in parallel.

this method is prone to misdetections because it cannot always distinguish the positions of multiple devices when their LEDs are blinking at the same time.


These structures were considered for evaluating the hardware cost of the technique.

concerning softerror detection evaluation, we have taken into account examples of adders and multipliers of 8x8 size only, due to the large number of simulations to be performed.


Moreover, although the metrics proposed in previous approaches have been applied during the matching phase, none of them extends these metrics to guide the covering, which actually selects the mapping solution, and thus, these techniques ignore the search space available during the covering.

we utilize the generated congestion maps during the covering process to compute the total track over.ow due to different mapping choices, and to select the one that minimizes this track over.ow while satisfying the delay constraints.


The variant FRW scheme increases the variance of MC procedure, and thus slows down its convergence.

the efficiency benefit of the variant FRW overwhelms its drawback, as demonstrated in Section V. C. Concurrent Extraction of Multiple Nets For the actual application of FRW, instead of the single-net capacitance extraction (with a single master conductor), we often need to extract the capacitances of multiple nets in a same design.


In the case of a springmass MEMS accelerometer, the measured quantity isthe capacitance, or the difference of the two capacitances, and analytical relation between capacitance and internal device parameters can be used to convert this information to acceleration, which is the actual measurement goal.

the accuracyof this information depends on two factors: (a)measurement accuracy of the capacitance difference, and (b) knowledge on the parameters of the internalMEMS structure.


Given this utility function, if M = {1, 2, 3, 4} and the receiver rates Rk, k=(1,2,3,4) are {4, 3, 2, 1 }, then the best thing to do is to not prune any receivers and operate at group rate RM=I.

if the receiver rates are {2, 2, 2, 1 }, then the best thing to do is to prune the fourth member and operate at group rate R[1,2,31=2.


Such formulation guarantees that optimal solution is in the search space.

such approach does not scale well with problem size and can be applied at only very small cases in practice.


An optimal clustering solution in Figure 6(b), with a minimum area of three clusters and a minimum logic level of two, can be obtained from T-VPack.

the optimal placement solution in Figure 6(c) on this optimal clustering yields a longest path delay of 2.0, which cannot be improved by postplacement duplication.


The majority of FPGA implementations are static and require the system to be completely erased before modifications can be loaded.

some FPGAs allow for dynamic circuit modification to enable systems that are re-programmable at runtime.


However the structurally longest paths may not be actual longest paths in a manufactured circuit due to process variation and/or circuit noise [9,10].

[11,12] tried to select actual longest paths by using statistical or dynamic timing analysis.


The performance loss seen by the incomplete bypass results led the authors to explore multi-banked and hierar- chical register file organizations.

in our simula- tions, the performance loss that motivated their work does not exist; the Alpha microarchitecture is limited by other overheads, and has sufficiently aggressive scheduling to overcome the effects of one-cycle bubbles between depen- dent instructions.


Since the endurance cycle of PRAM is considerably higher than that of NAND flash, the bitmap table region in the PRAM will wear out after the NAND flash array does.

the map page table region in the PRAM may potentially face the risk of endurance because some write-intensive workloads or malign attacks may frequently write certain logic pages.


On one hand, a large number of simulation samples must be generated in order to fit a high-dimensional model.

creating a single sampling point by transistor-level simulation can take a large amount of computational time.


With scan, ATEs can efficiently apply ATPG-based test programs to the silicon to check if the manufacturing process introduced physical defects.

this check is only as thorough as the test program itself.


RESULTS AND DISCUSSION The simulated leakage currents in the VT-control method and DG con.guration are compared in Fig.3.As observed in the plots, the leakage current is considerably reduced both for NMOS and PMOS transistors in comparison with the DG con.guration.A controlling range of about three orders of magnitude is achievable in the leakage current, indicating the potential capability of the VT-control method in minimizing the standby power.

the total dynamic power resulting from charge-transfer to the top and bottom gates of the transistors is plotted versus VCN and VCP and compared with the DG con.guration in Fig.4.The values for VT-control method are higher than DG but of the same order.from the previous plot, it can be predicted that the increase in the dynamic power consumption may be well compensated by the dramatically reduced leakage current, especially as the circuit activity is decreased.


We conjecture that there exists a set of guiding templates analogous to the letters in an alphabet which could cover and compose the desired full chip contact layer.

the overlay accuracy of the contact holes as well as the printability of templates may vary among different templates, and in consequence, the cost of each guiding template shape is very different from others.


From (3) it follows that the transitions evoked at the inputs xti, xtj reach the inputs of the gate gik at the same moment tk+1 = tx + (.i-t -d(gik)).


5.3 Multi-Level Optimization Inthe resultspresentedthusfar,wehave observedthatincreasing theeffectiveness ofNBTI mitigationtechniques atonly thecircuit or microarchitecturelevel toimprovetheguardband entailspenalties in terms of area, power, delay, and application performance.

lightweight optimizations at each level could provide a net increase in guardband reduction with less overhead.


These frameworks exploit the heterogeneity in the sensitivity of di.erent programs to varying core frequencies to optimize their cumulative throughput and energy, while guaranteeing a minimum level of performance for each program.

in the context for multithreaded programs, these schemes o.er limited bene.ts as all threads are often homogeneous and the interdependency between them needs to be considered.


4.2 Inter-Region Level The circuitry described in the previous subsection ensures that a single region can be turned on without violating the current constraint of the power grid.

in practice there might be excess current caused by other activity, such as unrelated signals passing through the region (for switch boxes that are not powered down), or from transient signal changes while turning on a region.


Also, the sensors used to meter electricity are actively and constantly powered, meaning they require expensive AC-DC power supplies and draw their own power even when the load they are metering is off.

we propose a system that is easy to deploy, offers .ne grained and automated wireless data collection, and uses inexpensive energy-harvesting sensors which draw zero power when the measured loads are turned off.


Most prior studies in architecture support for QoS assume that the QoS target is expressed in IPC.

we believe that IPC is not suitable to specify a QoS target because IPC is not easily convertible.


Scaling has the advantage of implementing complex functionalities on the silicon chip and operating them at lower supply voltages.

the exponential increase in the leakage implies higher power consumption and poses a significant design challenge.


Due to such an opposite stapling trend, a via-stapling in a sequential fashion results in excessive number of vias.

the vias are distributed more uniformly in all levels when simultaneously considering the thermal and power integrity.


Unfortunately, there is no general solution to this problem, which maintains a correct perspective and the consistency of the shared virtual world for all users without requiring that all users are looking from the same position as the navigator, which is physically impossible.

we suggest various approaches to mitigate the problem: Stop and crowd.


Phoenix increases wire load by tapping signals.

if designers see a bene.t to Phoenix, they will make slight modi.cations to the circuits to ensure such load increase has no performance impact.


After servicing the transition, the head pointer will traverse two entries and point to the ALU-2 entry in the queue.

consider an alternate case where ALU-1 has a higher weight that results in the weight of the sliding window to exceed the current threshold budget.


SIMD: SIMD architectures, examples of which include the CM-2 [7] and the Maspar MP1 [3], use global control with a single instruction fetch and decode.

unlike vector architectures, either private memories are present at each node or values are broadcast in a regular manner from a centralized memory.


In the case that the application requires less than w bits we argue that the generator itself should still use r = w, as this maximises the utilisation of memory bandwidth, and maximises the change in RNG state per-cycle.

if the number of required random bits is greater than w then clearly the RNG must support a larger number of active bits.


The Necessity of Pseudo-Deadspace Notice that a corner should be selected before placing a module in LFF.

in the left subplot of Figure 5, Module c should be placed at neither of Corner 1 and 2.


Most works aim characterizing the tail of an output specification distribution for a given valid distribution of the input parametric space.

our premise is that this original multi-dimensional distribution of the input parameter space has changed, and our objective is to identify those combinations in the new input parameter space that could lead to output specification violations.


In many design cases, a higher sampling rate satis.es (i) but violates (ii).

a lower sampling rate 978-3-9815370-0-0/DATE13/ c @2013 EDAA Fig.


The CABAC is the most important entropy encoding method defined by the H.264/AVC standard, allowing 15% coding gain over CAVLC [12].

the algorithms of CABAC are significantly more complex than CAVLC.


Like past work [2, 3, 6, 7, 8], o we focus on data references because they traditionally de- N5 termine performance.

these techniques will also No  r5 ro 5 o -5 improving instruction reference behavior, particularly as instruction footprints increase in emerging server workloads [13, 20].


this technique on-demand gated precharge incurs an extra penalty cycle when a cache access pointer transitions from one to another sub-bank.


Such option does not require updating VS bits everytime that Vcc is changed.

disabling schemes cannot be recon.gured to operate at more than two di.erent Vcc levels (either low or high Vcc).


On the other hand, physical segments are considered young physical segments when their remaining write counts are larger than 10N' and called old physical segments when their ' remaining write counts are no more than 10N' ,where N<N and 10N' is regarded as the retiring threshold Tr to separate young  ciently .nd out all the young physical segments in the storage space with the next-.t algorithm.

when a virtual segment in the storage space needs a new free physical segment, the space manager is invoked by the storage manager to return an comparatively old free physical segment.


INTRODUCTION Embedded systems have been widely used in various fields in today s world.

designing a modern embedded system in nanometer technologies is more difficult than ever, and the problems continue to worsen with shrinking feature sizes.


The benefit of employing larger hierarchical LEs for pin permutation is the added flexibility, not only from enlarged permutation groups, but also from the ability of reexpressing the underlying logic of the cluster via logic resynthesis.

except for special cases, the complexity of determining the permutation groups and the nominal cell delays is higher with a larger, more complicated LE.


Directly applying these algorithms may mix up nets from di.erent buses, as seen in Figure 2(a).

designers always prefer nets in the same bus to be routed together without foreigners, as in Figure 2(b).


SAMR o.ers potentially large savings in memory and computational e.ort when compared to globally-uniform static mesh calculations.

di.culties associated with its implementation often make the application of SAMR prohibitive.


Traditional simulation approaches operate at the cycle-accurate level, employing detailed contention models of shared resources at the cost of execution time [4] [5].

the analytical models, based on averages or statistical properties, abstract away much of the detail in a system in exchange for quick evaluation times [2].


As expected in 90nm technology, 95th percentile leakage savings are almost same for all the designs due to negligible intra-die process variation.

in 50nm technology OPT3 results in 30% and 12% extra leakage power saving compared to CONV and OPT2, respectively.


Design of Mixed Gates for Leakage Reduction Frank Sill Jiaxi You Dirk Timmermann College of CSEE College of CSEE College of CSEE University of Rostock University of Rostock University of Rostock Germany Germany Germany frank.sill@uni-rostock.de jiaxi.you@uni-rostock.de dirk.timmermann@uni-rostock.de ABSTRACT Leakage power dissipation is one of the most critical factors for the overall current dissipation and future designs.

design techniques for the reduction of leakage power should not decrease design performance.


Some assist features such as cell VSS (CVSS) boost aim to weaken the cross coupled inverters, by reducing the gate to source voltage of the PMOS device.

we will show that this technique actually increases the worst case TCRIT value.


The complexity of our method is O(M*P) where M is the number of quantization points in the histogram.

in Eqn (3) and (6), we assume that there is no correlation between two PR s. in reality, there can be correlations, especially when cache behavior is concerned.


more warps waiting for data to come back from memory than warps ready to issue to memory.

for two intervals, there are signi.cantly more warps ready to issue to memory, putting pressure on the memory pipeline.


Similar to unary stochastic, it uses lean hardware and avoids carry propagation both in the addition operation and when adding partial products in multiplications.

it cuts down on the number of bits required to represent a unary stochastic number by an exponential factor of 2K by using K positional digits, similar to binary.


Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs Sudarshan Bahukudumbi and Krishnendu Chakrabarty Richard Kacprowicz Department of Electrical and Computer Engineering Intel Corporation Duke University, Durham, NC 27708 Email: {spb, krish}@ee.duke.edu Abstract Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing.

the testing of multiple cores of a system-on-chip (SoC) in parallel during WLTBI leads to constantly-varying device power during the duration of the test.


Since there is some read stability overhead, all writeassist techniques are applicable in some range.

for simplicity only bitline underdriving is used.


[6] consider the via minimization to insert redundant vias in an existing multi-level routing framework.

post-routing ECO operations may modify the final routing result and introduce the extra vias to fix the timing or antenna purpose.


Also, an intervention port request is generated, to broadcast the initiating coherent master s request to all coherent masters.

4 in a snoopy-bus system this request is not needed, because the request has already been broadcasted in step 2b.


As evident, the path from carry-in to carry-out is critical and determines the frequency of operation of the adder.

note that the critical path is activated only when Ci,0 = 1 and at the same time, P0P1P2P3 = 1.


For a partially failed via, the contact resistance and the parasitic capacitance will increase and cause unexpected delay.

a complete via failure will leave an open net in an IC layout and invalidate the functionality of the design.


5.4.1 Hop on Stop vs. Do No Harm The do no harm policy dictates shift to another channel, as soon as it is occupied.

hop on stop policy can resist PUE attacks [16], by continuing with transmission, regardless of the presence of PUE and shifting channel only when sensing interference.


Ef.cient SMT-based ATPG for Interconnect Open Defects Dominik Erb, Karsten Scheibler, Matthias Sauer, Bernd Becker University of Freiburg, Georges-Köhler-Allee 51, 79110 Freiburg, Germany Abstract Interconnect opens are known to be one of the predominant defects in nanoscale technologies.

automatic testpattern generation for open faults is challenging, because of theirrather unstable behaviour and the numerous electric parameterswhich need to be considered.


If eFlash is present in these products, emerging eNVM can replace it and provide all the system-level benefits explained above.

an essential question for emerging eNVM adoption in this category of products is whether it can lower active power consumption at a low or intermediate operating frequency and allow larger memory capacity at comparable or lower cost.


This transformation is similar to the previous one obtained by annealing in vacuum.

the details of the transformation are very different.


Bugs with error detection latencies longer than a few thousand clock 978-3-9815370-0-0/DATE13/&#169;2013 EDAA cycles are highly challenging because it is extremely difficult to trace too far back in history for bug localization.

bugs in complex SoCs can result in very long error detection latencies of several millions to billions of clock cycles [Hong 10, Lin 12, Reick 12].


This is particularly visible in MediaBench programs.

in rare cases (e.g., vortex and mesa.m) RENO reduces fetch criticality.


Innovative ideas in the development of computer-aided design (CAD) tools for multi-layer SOP technology is crucial to fully exploit the potential of this new emerging technology.

there has been very little development, if not none, of CAD tools that handle the complexity of automatic 3D SOP layout generation.


SpecTLB proposes speculative translations by using address interpolation on TLB misses in systems that allow superpage promotion [6].

preTrans speculates on the TLB hit path.


For the 8-bit butterfly datapath, the data and input gating to the unused hardware leads to a 66% energy dissipation reduction over a non-scalable design.

for 16-bit computations, the energy dissipation of the scalable designs increases over the non-scalable design, due to the energy overhead from the energy-scalability enabling logic.


In practice, we do not typically track values this far.

we do track values well beyond the point that they are committed to architectural registers or stored to memory to determine whether they could potentially influence the output.


INTRODUCTION STT-RAM [3], [15] is a promising candidate for conventional SRAM caches given its attractive features, negligible leakage power, high storage density and fast access speed.

the high power consumption and long latency write operations [4], [7], [12] impede the widespread adoption of STT-RAM.


Hence, the topmost transistor works in saturation region only (Vds > Pv[Vgs -Vth]a/2, see section 2.1) when all input voltages Vin of the stack start to change.

the other transistors in the sub-stack (see figure 3) work in linear region (Vds < Pv[Vgs -Vth]a/2, see section 2.1) [15].


Such methods of statistical design in general are either deterministic or statistical [8], with standard Monte Carlo analysis being the most widely-adopted technique.

standard Monte Carlo techniques are to a first order dependent on the sample size and are in general slow at estimating low failure/tail probabilities.


Dipole sources are optimal for features that are oriented perpendicular to the axis of the dipole.

dipole illumination results in a significantly degraded image contrast for the features that are parallel to the illumination direction.


The failure regions of fully-salicided NMOS after 125-V MM ESD stress are only located within a few gate regions, which is due to current crowding within the weak salicided surface channel.

the failure regions of NMOS with dummy-gate structure after 325-V MM ESD stress are uniformly located among all the contact regions of drain side.


The ultimate idea is to directly utilize the high-frequencycarrier signal for the localization purpose.

since the available FPGAs cannot directly process 2.5 GHz signals, the experimental setup is using an f = 5MHz low-frequency (localization) signal, which is modulated onto a fc = 2.484 GHz carrier (channel 14 of the 802.11b standard).


The volume of test data for an SOC is growing rapidly as IP cores become more complex and an increasing number of these cores are integrated in a chip.

the I/O channel capacity, speed and accuracy, and data memory of automatic test equipment (ATE) are severely limited.


2.3 Support-Circuit Preconditioning Approach An on-the-.y support-circuit preconditioning (SCP) technique has been recently proposed in [5].SCP starts from sparsifying the linear circuit networks to generate ultra-sparsi.er support graphs, and subsequently combines these support graphs with other nonlinear devices to build the supportcircuit preconditioner.This technique is very e.ective for parasitic-dominated circuit designs within which the linear circuit elements or parasitics dominate (the number of linear   gd g2 d d h g h Cds g3 gds h Cgdd g2 s g5 g1 Ultra-Spparsifier gmm g Active Devices Active Devices g2 g 3 g hh g C d Cds mgsh gV s g5 g1 Support-Circuitit Preconditioner SSupportt GGraphh S t Ci Figure 2: Support circuit generation.

circuit elements is much greater than the number of nonlinear devices), since the support-circuit preconditioning matrix can be signi.cantly sparsi.ed, and thus more e.cient to factorize.when nonlinear devices dominate in a design, the e.ectiveness of the prior support-circuit preconditioner can be drastically weakened: as a result, factorizing the support-circuit preconditioner matrix can be as expensive as factorizing the original system matrix.


Most frequently supported dynamic power features include voltage islands, frequency scaling, power-aware synthesis, placement and routing and clock gating.

support for leakageaware design includes multi-Vth libraries, MTCMOS and VTC-MOS design techniques and thermal analysis.


The number of ALMs used by XOR memories grows very slowly as memory depth increases, since for the XOR design ALMs are used only to implement the XOR operations and forwarding logic, both of which grow linearly with memory width and only logarithmically with memory depth.

the number of ALMs used by LVT memoriesgrows with memorydepth since(i) they are used to construct the LVT itself, which grows signi.cantly for deep and/or many-ported memories, and(ii) theyimplementforwarding logic, which grows with the number of BRAMs used.


It is clear that the HTFET is a superior device compared to Si NMOS in its sub-threshold region, showing both higher IOn as well as higher IOn/IOf f ratio.

it is also important to consider the Id-Vd characteristics of the HTFET, since the saturation voltage (Vd-sat)plays an important role in the noise-margin characteristics of digital circuits.


can capture all pairwise relationships in a circuit.

for large circuits, the depth of recursion is kept low to avoid excessive computational costs.


We prefer a full mesh because, in the worst case, it only adds one hop to the lookup.

if a full mesh proves insuf.cient, then we will experiment with multi-hop topologies.


The encoder needs the content of the FVfinder and there is no need in replicat- ing storage for frequent values.

it is necessary to pass the captured frequent values to the decoder shown in Figure 2.


This danger may be reduced if the robot carries a radar and/or has access via radio to commercial Automatic Identification System (AIS) information.

radars are expensive and both radars and radio can only be used above the water, while AIS status is not always broadcast by passing shipping.


proposed a parity commit delay approach which reschedules the updated parity commits to the NFSS idle time.

this scheme may fail to recover the corrupted data when its parity is not committed in time.


We would like to reiterate that, spin wave propagation does not involve physical movement of charge and thereby, there is no power consumption associated with wave propagation in the SWB.

external energy is needed to excite input spin wave signals and to assist the output ME cell switching.


This approach presents all the typical advantages of analog systems (large not-quantized accuracy, no distributed clock, etc.).

it requires that the tuning system is continuously active (thus increasing the overall power consumption), since storing a high accuracy analog control voltage would be difficult.


The author leverages the technique of sensing the magnetic .eld that is induced by the 60Hz current in order to infer the total power consumption in real-time.

all these system requires additional custom sensing hardware to be installed in the house s power line for continuous period of sensing.


Many circuit design and architectural solutions, such as VDD scaling [12], power-gating [15], and body-biasing [11], have been invented to reduce the standby power of caches.

these techniques are becoming less e.cient as technology continues to scale, causing the transistor s leakage current to increase exponentially.


The existing paradigm can easily remain if the fin pitch equals the M2 pitch.

fin and metal pitches have different scaling pressures, so they have not tended to line up.


The improvement of TFS over PFS in overall tra.c is evident in Figure 8.

we notice that event latency may be increasedinTFS sinceeach message maygothrough several proxies, each of which has a bu.ering period.


Structural test methods for performance veri.cation include transition fault patterns and path delay tests [6, 16].

path delay test patterns are cumbersome to develop because of the exponential search space and the large number of false and structurally-untestable paths involved [7].


Intypicalcases, conventional level shifter is able to achieve less than 5 fanout-of-four inverter(FO4)delays atVDDL, whichis su.cientlyfastfor most subthreshold applications.

considering 3s processvariation,Wnneedstobeup-sizedatleasttwotimes larger than the nominal case to maintain functionality.


Focusing on the pipeline-related components in all stages, we computed their gate count to be almost 20% of the total gate count of the processor.

they remain poorly tested the fault coverage of the entire pipeline logic is less than 72%.


5 Conclusions L0/.lter instruction caches can greatly reduce the energy consumption of a processor by allowing the most frequent instructions to be accessed in a more ef.cient manner.

l0-IC misses can accumulate and lead to signi.cant application slowdown.


A more complete implication engine is based on recursive learning [7].

in order to keep * Supported in part by NSF Grant CCR-0196470 and NJ Commission  on Science & Technology simulation time within reasonable bounds, the recursion depth has to be kept low.


From Figures 7 and 8, for minimal area and delay it is better to employ SA when the number of bus masters is greater than 4 and is a power of two.

when the number of masters is not a power of two, a user might prefer to choose a bus arbiter option in our tool because of possible waste of ports in the SA.


The .ne-grain nature of these decisions make it dif.cult for the programmer to specify.

the compiler can take advantage of the data-.ow and memory access behavior analyses to make better decisions to how to distribute the application.


While simpler techniques such as stride prefetching [14,19] have been shown to be effective for scientific, desktop and engineering applications, they are largely ineffective for commercial workloads.

recent research with more sophisticated prefetchers has shown promise for these workloads.


There currently exist a number of mouse alternative de vices that provide pointing capabilities to individuals who cannot use a conventional mouse, such as eye trackers, head trackers, and mouth operated joysticks.

many such devices are costly or have limited level of controlla bility in terms of speed and degrees of freedom a.orded.


For example, if a module has a FIFO in which the output is stored for an external module to read from, after the computation is completed all rules can stop .ring while the output methods become ready.

this is not a universal fact, and there are instances where module registers need to be read externally and these might be always ready.


equalizing the inputand outputofan FF for the launch capture pulse).

due to the constraints from the decompressor, these two techniques in theiroriginal forms are not effective in generalbroadcastscan-basedtest compression.


Automatic designs of Type II are 1.2 times larger in area and 0.9 times faster in maximum frequency than manual designs on the average.

every address and data has at least one cycle delay becauseall data have to be stored and then passed to other IPs.


If this path did not exist, p1 could safely use the stale value of A.

because it does exist p1 must not use the stale value, thus the dotted WAR edge must be transformed to a RAW edge, eliminating the cycle.


Of course, this level 3 optimization is mainly reasonable if processes are in a tight communication relationship to each other.

the described way of grouping is not limited to processes of a single module.


This is because time consuming procedures may rarely switch control .ow to other procedures or be frequently called by other procedures.

procedure placement is a technique that aims to reduce con.ict misses due to procedure switching.


In [11], the authors propose an architecture to improve thememoryaccesses, exploitinglocal cachesand speculative reads.

the authors do not describe how to derive the allocation of operations to units and how to manage allocation on internal memories as well as memory accesses for nested functions.


We do not consider multithreaded benchmarks in this work.

we do not foresee any problems of using ACS with multithreaded programs.


For example, during a particular program execution, certain instructions may experience a mere fraction of the clock cycle delay, meeting the timing with a large margin to spare.

other instructions may experience a much larger delay, with limited slack.


Whengoing from a HC-SD to a HC-SD-SA(2)con.guration, the CDF curvesfor these two workloads shift upby a large amount, indicating a signi.cant improvement in performance.

the HC-SD and (1/2)R curves for these two workloads in Figure 4 show a smaller performance improvement.


Sharing modem for phone calls: Through the device .le interface, Rio can initiate and receive phone calls.

it requires further development to relay the incoming and outgoing audio for the phone call.


For example, we have assumed that there is no correlation between device and interconnect variations, and that wires not sharing downstream paths are independent.

in a modern process, the variation between devices and interconnects may be interdependent, and wires nearby may also exhibit correlation due to chemical-mechanical planarization (CMP).


4.3.2 Approximate graph matching After building the structural dependency graphs of the two circuits under debugging, one could match these two graphs in the context of approximate graph matching [12] which is in general an NP problem.

we believe it is more manageable in the current context due to a number of reasons: 1.


The most general version of this problem of matching two graphs may well have an exponential computational complexity.

since the number of nodes in a cluster is typically small (not greater than 10), clustering the nodes usually does not require excessive running time.


The while construct and the other loop structures (for and until, illustrated in Figure 5) are essentially the same as those in N-S diagrams.

the N-S representation for choice constructs uses too much room when sequential and parallel operations are expressed.


In this case, there is also a single state where Celements are not vulnerable.

in all remaining vulnerable states, components have 1s in the output, because spacers in RTO are represented by the all-1s codeword.


many researchers [7], [8], [11], [12] have proven that this type of exploration simpli.cations inherently reduces the effectiveness of the DSE and thus the optimality of the approximated Pareto curve.


They are capable of eliminating capacitive crosstalk since electrical .eld e.ect is of short range and tends to terminate in neighboring metal materials.

magnetic .eld e.ect is of long range, and thus these techniques can not suppress inductive crosstalk.


On-chip hash functions are also used to enable authentication without exposing the direct PUF responses [19].

it should be noted that on-chip hash functions incur considerable cost in both area and run-time that typically exceed those of the PUF by more than an order of magnitude [7], [20].


The change in gate oxide current resulting from OBD is modeled by the power-law expression in Equation 1: p .Igate =K(Vgd) (1) The change in gate-to-drain (gate-to-source) current is represented as a function of a linear scaling factor K, the gate-to-drain (gate-to-source) voltage Vgd (Vgs), and a power-law exponent, p. Both .tting parameters K and p vary depending on the amount of degradation experienced by the transistor in question.

for much of the empirical data collected in [26], choosing a p =5.0, while still allowing K to track degree of degradation, resulted in a good .t throughout the majority of the progressive breakdown region.


To precisely evaluate the contribution of each way among the ways using the distribution of references on the cache, we need to examine entire counts of LRU states.

it requires a considerable amount of hardware to implement and a larger overhead to evaluate at execution time.


It is the purpose of this work to reach a prede.ned MPEG videostream 4 decoder coverage, and for that matter many real movies have been used in the simulation.

the Bitstream processor (BS) -part of MPEG-4 decoder -has not achieved the desired coverage by means of these stimuli.


WCET estimation tools rely on a deterministic behavior of caches.

faults introduce nondeterminism (fault number and location is unknown a priori).


On one hand, the effect of device scaling is covered in the theoretical deduction by the specific dependence of the variance from the filament area Afil.

(23), (30), (39), and  (19) show that the obtained variance of the conductance G depends on parameters which are not ECM device parameters but parameters of the regulating device: VDD, VB, VThp, and k. Hence, as initially stated, the variance is the consequence of a joint interaction between RS device and the load circuit.


IMPROVING COVERAGE OF MULTI-CYCLE FAULTS Thus far, we have assumed that transient faults are of very short duration, so that simple time redundancy is as effective as space redundancy for fault detection.

some faults may persist for multiple cycles, such that two redundant operations could pass through the same hardware during the duration of the fault and experience the same error.


+ + .L .1L .R .2R Figure 11: The change in .L and .R with l w + t The physical explanation of this trend for a constant aspect ratio isthat increasing the length, width, and thickness of the interconnect such that l/(w+t) is kept constant decreases the frequency point .R since the skin depth becomes comparable to the wire width at lowerfrequencies.

this scaling in the wire dimensions decreases the resistance and at the same time increases the inductive impedance.


Our observations that certain regions can execute and commit outof-order, and that con.ict checks and region execution in different processors can allproceedinparallelisunique.Itmayhelpimprove the ef.ciency and complexity ofBulk system as well.

sC can be guaranteed at the language level even on hardware that supports a weaker consistency model using static analysis toinsertfences[24,39,41].computing a minimal set of fences for a program is NP-complete [25].


Since rerouting a .it may or may not increase link sharing, the total energy does not always decrease over iterations.

our heuristic does dig out more opportunities of capacity sharing as illustrated by the example in Figure 2.


Given the immaturity of the field, the models are likely to change with increased understanding.

these models and their seamless integration into the existing design methodology demonstrate the possibility of abstraction-based nano design.


We show that current performance counters o.er a good number of features that lead to good classi.cation of malware.

it is likely that the accuracy can be improved further if we included more features.


(Fixed-order means that each bit-weight or column is assumed to have the same number of bits to compress.)

the algorithm in [6] creates directly N-th-order compressors for each partial product bit-weight since multiplications usually result in the need to compress varying numbers of bits, depending on the bit weight.


in order to provide on-demand performance and energy savings.

such techniques do not explore how these resources can be better used, and what other resources can be turned-off when TLP is available.


Optical Proximity Correction (OPC) techniques are also employed [8] with the same goals.

during printability checks and layout design rule assessment, electrical quality of the layout is often ignored.


Main di.erences with our work were that they studied four di.erent power management policies under DVFS and centered their study on the relationship between CPU utilization and power consumption.

they also present interesting results about disk consumption that match partially our results, showing a .at consumption in reading operations and variations in the writing ones that they attribute to the size of the .les being written.


Because our system frequently adds one or two instructions to each block (to handle the fall-through case), we expected to see an average block size of 8 or 9.

for 16-word cache blocks, we actually see an average of 5.75.


The .rst approach, used in [17, 23], consists in having a one-cell distance between any two adjacent modules, which is suf.cient for isolating the functional regions on which operations are executing.

if routing is not considered at the same time with placement, the resulted solution will require signi.cant modi.cations for accomodating the necessary routes.


Reading a frequent value is done after the 32-bits flow through the output multiplexer.

if the tlag bit is clear indicating a nonfrequent value, it turns off the decoder letting the partial data value flow to an internal latch where the remaining part of the value is filled from reading the high-bit array in the second cycle.


In all three fault injection experiments, our diagnosis technique ranked the faulty module as a top candidate among the 278 modules.

on average 6 other modules are also ranked as top candidates.


The power mixer shown in Figure 2 works well in hybrid electric vehicles (HEV) and other similar applications.

when conforming to chip-scale dimensions and self-powered schemes, the use of two or more inductors is prohibitive.


a generalization of BCP) using a propositional satis.ability (SAT) algorithm.

the algorithm described in [1] is based on the Davis-Putnam [5] procedure, which has been shown to be particularly inef.cient for a large number of instances of SAT.


The symbolic approach in [3] deploys formal veri.cation techniques to discover subprograms which are semantically equivalent, therefore it can handle more syntactic variations than other approaches.

both cognitive approaches and symbolic approaches suffer from the scalability problem and are generally not applicable in practice.


Equation systems as the one above are suf.cient to describe the semantics of synchronous programs with immediate actions.

the use of delayed actions results in more general equation systems of the following form: 8 >>>: n init(xy)= xx,x .


A prediction-based architecture is proposed in [12] to reduce the latency associated with the root computation.

the speedup can be achieved by this architecture is limited by the serial nature of the computations involved in the factorization.


The 4/2 encoded bus should ideally result in energy savings at lower switching activities than the 8/4 encoded bus since the probability of the energy saving cycles (more than 2 bits switching) is higher than the probability of the energy saving cycles for the 8/4 encoded bus (more than 4 bits switching).

the energy gains are marginal due to the fact that the standard bus energy can be reduced further under the increased area penalty (25%) of the 4/2 encoder.


Hence, the model reduction algorithms of the equivalent circuits have received much attentions [6]-[11].

since global wires of the integrated circuits are far from the substrate, they are modeled by RLC distributed interconnects driven by the load resistance and output parasitic capacitance and driving the load capacitance [4].


The resynthesis is performed by mapping logic blocks extracted from a circuit against a library set of logic blocks (e.g., hard-wired LUTs) and replacing them with a functionally equivalent logic block if area can be reduced.

o1 O1 O1O1  x1 x2 x3 x1 x2 x3 x1x2x3 x1x2 x3 (a) (b) (c) (d) Figure 1: Motivating example for resynthesis considering retiming and multi-output logic blocks existing techniques perform resynthesis only within the combinational portion of a circuit, and only consider singleoutput Boolean functions [15, 16].


When we consider reusing a wire segment S which is shorted to an unused segment,the delay of S increases because of the additional capacitance provided by its partner.

a conventional path tracing tool that reports the delay along the traced path,will not see the additional delay caused by the short.


In [4], wiring area is treated as wire cost, and is added up directly to the buffer cost.

utilizaton of area on thicker layers could be more costly than lower layers and .nding the appropriate tradeoff between buffer cost and wire area is dif.cult.


arandomsequenceof223 ;1resultsinaBERof 1:28x10;6 .


3.5 Clustering segments After segmentation, music clip is divided into a few segments.

such segmentation does not have any structural information.


The crucial part is the decision for OSD(0) (only LRIP errors) or OSD(1) (MRP and LRIP errors), which can not always be accomplished correctly by the syndrome weight.


Today s largest FPGAs incorporate billions of transistors and can implement large complex systems.

the growing complexity of such systems has made them increasingly dif.cult to design.


Because of this parallel access, the state of the page in the target wordline can be captured simultaneously.

figure 5: Voltage requirement and write disturbance analysis with varying crossbar con.gurations.


The latching function is still the same as that of a conventional C-Element.

now only these two transistors need to be high threshold, and they will e.ciently cut-o.


Another problem with using large cliques is that corresponding (small) intersections of net bounding boxes may not include any aligned deadspace, preventing the insertion of a TSV island.

a smaller clique would imply fewer bounding boxes and a larger intersection that is more likely to admit TSV-island insertion.


Test chips and test structures help foundry process development and provide design guidelines in SPICE models, technology .le parameters, and design rules.

they provide only limited capability for production monitoring and yield analysis [22].


Practicality of the ESL approach crucially depends on correctness of behavioral synthesis, i.e., compilation from the ESL description to RTL [1].

many behavioral synthesis transformations are complex, depending on subtle design invariants.


We .nd that a 60 pixel projection is roughly the lower bound for reliable frequency decoding.

as camera resolutions increase, our usable distance will improve.


Rafiq et al [3] [4] put forward a bus-based integrated floorplanning.

permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.


Similar to FAB, BPLRU organizes the WBC in blocks of logical pages.

regardless of their sizes, all the blocks in BPLRU are organized in the LRU order: a write to a page will result in the corresponding block being moved to the most-recently-used (MRU) position.


Recently, hybrid-operation (high Vcc, ultralow Vcc) single-Vcc-domain cache designs have been proposed to tackle the needs of those chips.

existing data management policies are far from being optimal during high Vcc operation.


This is because the underlying cache parameters match exactly with the assumed cache parameters during procedure placement.

the code layout generated for C may perform badly for other con.gurations, though it is good for con.guration C. For example, for benchmark Ispell, 4k-1-way code layout is better than 4k-2-way code layout for 4k-1-way cache con.guration, but worse than 4k-2-way code layout for 4k-2-way cache con.guration.


Though the potential benefits are slightly larger, the overall impact is still low.

the benefits of this extension are higher for selected programs.


(the .rst Euler angle), resulting in a horizontal heading change.

since Headio is meant to determine the device s horizontal heading, it would always simplify the derivation if we de.ne the Initial Pose in such a way that .


For fixed write time, larger GX result in considerable errors making further adaptation necessary which is potentially possible as long as the memristive device sufficiently reacts to the applied stimulus.

the additional margin is not very large.


t) (1) RF c c VRF (t) = A(t) · cos(.ct +f(t)) (2) divided into two completely different paths and they must arrive at the PA where they are mixed at exactly the same time.

process variations cause a delay skew between envelope path and phase path, which is damaging to the operation [13].


As we mentioned previously, Table II confirms that our proposed method can correctly identify the equivalence even if speculative code motions (Sp, SSp, RSp) and global CSE are utilized during scheduling.

the method proposed in [17] fails to do so.


In the case of setup analysis, this is done by adding a margin of 5% to maximum signal arrival times, and a margin of -5% to capture-clock signal arrival times.

in the case of hold analysis, this is done by using a margin of -5% with minimum signal arrival times, and 5% with capture-clock signal arrival times.


From Table 1 we can see that TPLPlacer can achiever slightly better HPWL (0.22%).

tPLPlacer-SPD can achieve 14x speedup and less stitch number (5% less).


3.3.3 Integrating Con.dence Estimation The baseline Leader-Follower prefetching scheme prefetches atranslation into all the follower cores every time a TLB and PBmiss occurs on the leader core.

this approach may beover-aggressive and cause bad prefetches.


For mapping applications onto eFPGA, there is an attempt[4] to use a standard VLSI routing tool to perform the routing of nets between LEs.

mapping and placement of LEs are done manually.


The resulting ACA is slightly larger than a ripple carry adder, and is exponentially faster than fast traditional adders.

it may produce incorrect result on a very small fraction of inputs.


Along with the lower bounds provided by the vector generation based approaches, designers could make judgments to estimate the peak power range.

a difficult question still remains to be answered; it is not uncommon that the above upper bounds could be ten times bigger than the lower bounds.


Now the advantage of our special hash table design should be clear.

the size of BAT is much larger due to more complicated data structures.


CMesh has a lower node count than Mesh, but this comes at the expense of half the bisection bandwidth.

dB enjoys the bene.ts of concentration while still providing the same bisection bandwidth as Mesh despite having no more router ports than CMesh and having signi.cantly fewer total links than Mesh.


If it was a transition that caused the mismatch, the exact signals within the interface are identi.ed by comparing the pair of events that the transition connects.

if an unknown event is .agged, BiPeD compares this event to the other events in the interface (from the protocol database), identifying those events which are most similar to the errant event.


2.2 MOTIVATION The half-perimeter wirelength metric is capable of reducing global congestion substantially.

natural solutions derived contain regional variations in interconnection density, as nonhomogeneity in interconnection complexity is not considered.


4.2 Multiple-Tile Integer Linear Program Ideally, we should seek AREFs for the .ll features with respect to the entire layout, rather than for each tile independently.

the large number of tiles and possible AREFs across the entire layout make such a global strategy intractable.