To understand this numerical issue, we note that the condition number of the matrix ATA in (23) is equal to the square of the condition number of the matrix A.

the pseudo-inverse in (23) substantially increases the condition number and, hence, can result in an inaccurate solution.


As a result, SINR is often used as a measure of quality of service (QoS) at the physical layer.

each user flow is assumed to have a fixed SINR requirements representing its QoS needs and the CDMA system strives to meet the SINR requirements of all flows.


At the core of this correspondence there is the relative ordering of the I/O primitive statements.

a shrewd order reduces the number of clock cycles that a component circuit spends waiting for a successful communication.


The clock frequency was established according to the critical path of the functional circuit.

the circuit is operating at its maximum speed, as in the case of a design not using fault tolerant mechanisms.


INTRODUCTION 3D integrations, the mixed-technology stacking is especially attractive for stacking MRAM memory on top of CMOS logics, pro- Magnetic Random Access Memory (MRAM) has been considviding a mean to mount MRAM layer on top of logic layers, so ered as one of the most promising universal memory technologies that designers can take full advantage of the attractive bene.ts that due to its non-volatility, fast speed, zero standby power, and high MRAM provides.

the integration of MRAM with mi density.


Widely used at the system level, this approach is also valid at the device level, where devices can present an enhanced-functionality.

several novel devices demonstrate controllable polarity [4-7].


The objective function used to evaluate channel subsets favors selecting a group of channels that has lower false positive rates.

the objective function will tend to reject a channel that reliably exhibits epileptiform activity at seizure onset if that channel exhibits the same activity at other times.


This increases the number of used paths in switching crossbar, adding to the routing complexity.

the duplication method introduces extra constraints on routing in the form of additional paths.


Repeater switches are used in the global wordlines to electrically isolate each subarray.

subarrays 0 and 1 do not suffer additional global wordline delay due to the presence of subarrays 2 and 3.


on-period) duration distribution G, we show that the asymptotic tail distribution of the response times is dominated by the heavier one of the residual service time and the residual session duration.

the waiting time distribution is asymptotically equal to the tail distribution of the residual service time if the latter is heavier than that of the residual session duration time.


The two data structures are updated whenever the SOC TAM design is changed.

in data structure for TestRail r,we use timein(r), timesi(r) and timeused (r) to denote the internal testing time, the SI testing time and the utilized testing time on TAM r, respectively.


m = 6, and the baseline H noc1 has 6 levels.


(2) varying task parameters for each task in a chain of given length (3) varying area constraints.

for each chain length in the given range (4 to 20), we had a set of testcases where the tasks had different parameters.


Although there has been extensive research on low-power ME [3, 4, 16], related work does not provide run-time adaptivity.

state-of-the-art low- Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.


It turns out that our distributed switch arbiters generated by RAG lead to significant area and delay improvements when compared with other switch arbiters such as PPA and PPE.

rAG can be used to generate a switch arbiter for a 128x128 terabit switch which, assuming as stated in [5] that the critical path is the switch arbitration logic, achieves throughput 1.9X higher than PPA and 2.4X higher than PPE for the same 128x128 configuration.


Overall, we consider these results to be a satisfactory indication that our approximations work well both in terms of progressive processing and for our temporal scheduling algorithm.

there is a strong indication that increasing the budget does result in perceptually improved sounds, and that only a small percentage of users perceive asynchrony with temporal scheduling with delays less than 200ms.


We will describe the algorithm with reference to a concrete example.

we demonstrate here how our technique generates pronunciations for the Hebrew word for one , roughly pronounced EH-HUD , using the English recognizer from the Microsoft Speech Server.


The clock distribution network does not have to be a tree.

buffers/inverters connected in parallel, as well as the mesh, grid, and crosslink interconnect structures are allowed.


Compared with the FSMs obtained by SIS without considering power consumption, our approach generated FSMs with 30% to 90% less power at the cost of 20% to 120% area overhead, as shown in the ratio columns.

we obtained two designs with extremely lower power consumption.


The information obtained in the previous consistency relaxation stage is used to guide consistency restoration.

a speci.c gate implementation (size and Vt level) of a node is associated with a unique required arrival time value obtained in the relaxation stage according to Property 1.


3a) no longer applies to our characterizations of the severe short-channel effects in which the off-state current (at VGS = 0V) is very large even with a very high channel doping.

its very poor on-to-off current ratio renders this device useless.


As a result, some of the omitted edges may have to reconsidered to keep the underlying graphs connected.

wash droplets may have to traverse through some of the cell boundaries even if there is no residue.


Using de.nition 3 as primitives, we are able to tabulate the horizontal breaking for quick information lookup and update.

successor is a pointer table referring each node to its successive horizontal breaking node, while satellite is a sentinel table for each breaking node to keep track of its furthest predecessor for such breaking property to hold.


As a result, the new paradigm not only prevents the long wire delays from increasing the cycle time but also enables parallel computation and communication.

the FUs can perform computing when the global data is transferring.


From the simulation results of Figures 1(b) and (c) in Table 1, considering coupling e.ects during length ratio matching can further reduce the mismatch of the resulting capacitance ratio.

the in.uence of parasitic capacitance is typically more signi.cant for more advanced technology nodes.


The error trace can also be used to simulate .. and generate internal simulated values for all nets.

they can be used to generate a predicate ...... and .... .. corresponding to a module .. s .. .. input and output values for time-frame ... B.


Let VthH (VthL) be the high and low threshold voltages.

a driven gate interprets the input voltage as logic 1 (0) if it is greater (less) than or equal to VthH (VthL).


In this paper, we make the new observation that knowing (or, more broadly, distinguishing) the value programmed in the immediate-neighbor cell makes it easier to determine the value stored in the flash cell that is being read.

one can classify the threshold voltage distribution of flash memory cells into multiple threshold voltage distributions based on the logical value of the immediate-neighbor flash cell and use the appropriate "classified" (or, conditional) voltage distribution (and the corresponding read reference voltage values associated with it, called the "local optimum read reference voltages") to more accurately determine the value of the cell that is being read.


Furthermore, it provides the flexibility to inject transient current pulses anywhere in a large circuit and directly observe the propagation of the resulting transient through a large combinational network.

this approach combines the proven accuracy in ion strike modeling of 3D device simulations [5] and the efficiency of commercial circuit simulators such as SPICE.


At specified intervals, the history of the renaming constraints is evaluated and register redistribution can be performed.

architected registers that have been detected to be bottlenecks are supplemented with additional physical entries, taken from other pools that are only infrequently accessed.


This may have caused a large within-class variance.

load modality does not work robustly when ingredient has di.erences in their local physical properties.


Our approach, on the other hand, executes this: Q11, Q21, Q31, Q12, Q22, Q32, Q13, Q23, Q33, Q14, Q24, Q34.

we restructure query parts (Qij) around the data and make use of the best cache locality.


We conducted an experiment to see if the application miss rate varies when run concurrently with other applications.


Also, the average false negative rate is 13.12%.

about 13% of interposer samples which we claimed to be defective are actually functional.


This result also implies that the maximum achievable throughput of an energy ef.cient sensor network is always less than that of a normal ad hoc network.

the reduction in channel contention due to the nodes periodically switching over to sleep state is outweighed by the longer delays incurred due to the nodes not being able to Figure 4: Maximum achievable effective throughput versus probability that a node is active.


We maintained usability by adopting a suspension mechanism, which allows the microphone s position to be partially independent of the neckpiece.

the microphone remains in place and .rmly attached to the neckpiece even when moving, thus minimizing friction noise.


6.4 Energy Cost of Measuring While no system can monitor power draw with zero overhead, Monjolo adds a much smaller power overhead than today s commercial power meters.

when a load is completely off Monjolo draws no power due to its load current based energy harvesting technique.


The major feature that differentiates it from all the previous RO-based schemes is that we equip each TSV s output inverter with variable thresholds.

sometimes a TSV s output inverter behaves like a normal CMOS logic inverter, while at some other time its 0Æ1 and  1Æ0 thresholds are made different, by switching it to a Schmitt-Trigger inverter as will be detailed later.


However, in contrast to the endtoend latency, the network latency is always finite.

network latencies are meaningful even when the network is saturated (Figure 4(b)).


However, the logical content of the box is not provided, which prevents logical redundancies from being propagated through the box.

the absence of set/reset control white box logic prevents sequential analysis because the input to the flip-flop is not longer related to the rest of the circuit.


For space concerns, several extensions have not been presented.

we have considered another logic domain (combining 0, 1, 0, 1, U, and U) and the extension of our analysis to Single-Event Transient (SET) (which may cause multiple cell upsets).


Since in this fault injection simulation, the goal was detecting eventual design-errors in the circuits of the fault tolerance mechanisms implemented in the target microprocessor.

it was to verify whether these mechanisms mitigate appropriately SETs and SEUs in accord to the constraints of their features.


Secondly, all worst discrepancies correspond to components which either exist practically identical in the AIC cluster or which are redesigned for it following the very same methodology and circuit structure.

if we are making a mistake, the error is independent of the cluster type and is systematic across the simulated architectures: it should thus bring only a minimal bias to our conclusions.


Moreover, we should not loss sight that both of our approaches permit incremental computation while the CUTSET method does not.

each subsequent query of criticality or yield gradients can be answered much faster than CUTSET.


The two left most columns describe the data value which is processed in that specific time step; while the two right most columns specify the command that shall be executed by the microcode engine.

the first column defines the field with its presence attribute, while the second column maps the field to a unique identifier such that it can be later interpreted by software.


To accommodate this, we decided to try a multifocal mapping function consisting of a sum of sigmoids.

we mapped time t to 11 x(t,ta,tb)= s(t,ta)+ s(t,tb)= + 1 + u-v*(t-ta ) 1 + u-v*(t-tb ) Figure 6: Gantt chart with two .sheye zooms.


If an error occurs, the replication cache needs to be accessed to .nd the replica, which takes an extra cycle.

load operations take 2 cycles in case of soft errors.


Hence, finding the optimal xk to maximize the determinant det(Fk) is equivalent to maximizing the determinant det(Skk -SkS·SSS -1·SSk).

only det(Skk -SkS·SSS -1·SSk) should be repeatedly calculated for different xk during the search process.


the weights for frequencies that exist in the test items spatial patterns) might be very different.

their spatial patterns could still be distinct.


We were also able to perform detailed comparisons of theory and simulation for all of the metrics studied in a far more comprehensive manner than was previously possible.

in this paper we show that as dynamic power increases in importance, the optimal pipeline depth shifts to shorter pipelines.


It indicates that many of the rows in G are similar.

for many pairs of paths such as pi and pk, few entries such as gij and gkj in G might be di.erent, indicating that the two paths only di.er in a few segments (i.e., segment sj ).


In our design Metastability issue happens if a wrong data is read while the Load signal is enabled.

newer .its are overwritten by proceeding ones because of wrong data sampling as a result of synchronization failure.


100W/cm2 for force-air cooling, 1 10W/cm2 for ambient cooling), not transistor integration density, is the key limitation for computations [12].

we cannot a.ord to turn on all the transistors that we can integrate onto an integrated circuit [15], a phenomenon now termed Dark Silicon [29, 10].


5.3 Optimizing Acknowledgments based on MAC characteristics Due to processing constraints in sensor systems, as well as the ine.ciency of copies in FLASH memory, we choose to compress the traditional layered protocol architecture to reduce data copies and management overhead.

impala uni.es the session-based transport control with the timeslot-based media access control.


... .... .. ..... .... ... .... ..... ....... (10) (14) otherwise given that is the remaining transitive neighbor depth.

it is necessary to consider the heat .ow from and to transitive neighbors to a depth of .


In this experiment, the PPS for the macro-blocks are generated using the recently developed efficient post-synthesis statistical power minimization techniques [12,13].

statistical gate sizing is used here to trade circuit slack for lower power consumption [12].


Note that in our processing pipeline, we compute tuning parameters on the stanza level.

signi.cant shifts in tuning within a stanza cannot yet be captured by our methods.


An immediate goal for future work is to see if all optimizations performed by FFTW can be achieved using abstract interpretation.

the implementation presented here performs only obvious optimizations.


(1) 2(1 - .T ) However, unlike the systems with exponentially distributed service times, the output from an M/D/1 system is no longer a Poisson process: the time between two consecutive outputs is guaranteed to be greater than or equal to the service time value T .

a constant-time server produces a de-randomization of the Poisson process, thus reducing the degree of randomness of the inter-arrival times, which is the main cause of contention delays at the input queue.


A primitive condition can be described as two bytes; a primitive action can also be described as a byte.

the length of the shortest rule is only 4 bytes.


Previous works have observed that there exists a correlation between the concept of idleness exploited in power management strategies and aging.

the hardware implementation of a low-power state (i.e., voltage scaling for dynamic power and power/ground gating for static power) can be leveraged to reduce NBTI-induced aging [4, 5].


From Theorem 4 it follows that Smx < Sx and hence the sensitivity bound Smx can be used to prune gate x before its perturbation front reaches the sink node.

if at any time during the propagation of the front for gate x the bound Smx become less than a previously computed sen sitivity Si of gate i, gate x can be eliminated from further consideration.


A perceptual study described in [8] found that humans have a limited capacity to discriminate between frequencies that are close to each other.

if two close enough frequencies are played in succession, the average human listener is unable to tell whether they were two different frequencies or the same frequency played out twice.


With superposition, the problem of generating input vectors for characterizing a system is dramatically simplified since the output response is simply the sum of the contributions from each of the analog inputs: N Y=c + La· X (1) ii i=1 where li denotes the partial gain from the input Xi to the output Y and c is a DC offset.

a linear system is completely described by a set of gains, li's, which can be determined by a set of test vectors whose size grows linearly with the number of inputs, N. Said differently, the result surface for a linear system is smooth, so it doesn t take many points to completely characterize it.


3, the transfer gate TG1 is removed as in the previous approach and a second additional pass-transistor PT2 is inserted and connected in-between the memory logic and the output of the .ip-.op itself.

pT2 will increase the performance of the entire circuit, since it acts as a sense-ampli.er which o.sets the memory logic by its metastability when the .ip-.op is re-activated or de-activated, leading to faster sleep-in and sleep-out operations.


Among different PUF architectures, we focus on silicon PUFs, which can be easily applied to ICs.

we consider Arbiter PUFs (APUFs) [7] which are based on race conditions on two identical logic paths.


In this paper we propose a method that maximizes the resolution of each path delay measurement, in terms of its ability to detect the targeted Trojan.

for each Trojan, our approach accentuates the Trojan s impact by generating a vector that sensitizes the shortest path passing via the Trojan s site.


TABLEI LOK-UPPERIODFOR OPTIMIZEDLF'sPARAMETERCAsE LokUpConventionalPLLPhaseAdjustPLL Frequeny 7.11fse 6.08fse Phase 3.82fse 2.73fse TABLEII LOK-UPPERIODFOR UN-OPTIMIZEDLF'sPARAMETERCAsE LokUpConventionalPLLPhaseAdjustPLL Frequeny 18.60fse 16.09fse Phase 8.67fse 6.49fse Forallases,thelok-upperiodisimprovedby10to30%.

theredutioninthelok-upperiodismorethan2fs fortheun-optimizedLFparameters,whihorresponds tomorethan400lokylesofthePLL.Fig.10and Fig.11showtheunloksignalleveloftheonventional andtheproposedPLLforun-optimizedLFparameters, respetively.ThesefguresshowtheproposedPLLhas Unlock Signal Level (V) 5 4 3 2 1 0 0 10 20 30 40 50 60 Time (usec) Fig.10.UnlokSignalTransitionofConventionalPLLwith Un-optimizedLFParameters Unlock Signal Level (V) 5 4 3 2 1 0 0 10 20 30 40 50 60 Time (usec) Fig.11.UnlokSignalTransitionofPhaseAdjustPLLwith Un-optimizedLFParameters shorterlok-upperiodthantheonvetionalPLLforinitialfrequenyloking.Thephaselokingstartsat40fs asthereferenelokinvertsitsphase(shiftsphaseby theamountof)atthismoment.TheonventionalPLL leavesthelok-uponditionafteritmeetsthetheonditiononetime.Thelok-upstabilityisimprovedinthe proposedPLLbeauseitneverleavesthelok-upondi-tiononeitmeetstheondition.Fig.12andFig.13 Frequency (MHz) 220 215 210 205 200 195 190 185 180 175 170 1015202530 3540455055 60 Time (usec) Fig.12.FrequenyTransitionofConventionalPLLwith Un-optimizedLFParameters showthetransitionofthefrequenyoftheonventional PLLandtheproposedPLLforthesameun-optimized LFparametersasinFig.10andFig.11,respetively.In Frequency (MHz) 220 215 210 205 200 195 190 185 180 175 170 1015202530 35404550 55 Time (usec) Fig.13.UnlokSignalTransitionofPhaseAdjustPLLwith Un-optimizedLFParameters theproposedmethod,thefrequenylok-upprofleisimproved.Theamountoffrequenyovershootissuppressed intheproposedPLL.Fig.14showsthe"DelayControl Delay Contorl Bits 9 8 7 6 5 4 3 2 1 0 0 102030405060 Time (usec) Fig.14.DelayControlBitTransitionofPhaseAdjustPLLwith Un-optimizedLFParameters Bits"valuefortheVDintheproposedmethod.The "DelayControlBits"areontrolledappropriately.whenthephasedeviationofthePLLlokfromthe targetreferenelokislarge,thevalueismodifedfrequently.Asaresult,theproposedmethodimprovesnot onlythePLL'sfrequenyandphaselok-upperiodbut alsothePLL'sstability.


This section describes the logic architecture of the Altera Stratix II FPGA (the same basic architecture was kept for the subsequent Stratix III as well).

the existing carry-chains propagate through all 8 cells at a time; the carry chain in our proposed logic block, in contrast, propagates only through 2 at a time, thereby increasing flexibility and reducing delay.


The semantics of Quartz and Esterel can be de.ned in several ways that lead all to the same transition system.

there is a semantics based on process-algebraic transition rules, and a direct translation into hardware circuits [3].


Errors Causing Application Hangs: While the MFU could enable some error-tolerant operation, it would be insuf.cient without the MIS.

without the MIS s ability to keep control .ow on track, errors not only affect program and address values, but they also cause the programs to hang and fail to reach the end of the computation.


Operations on Boolean functions over the same domain can be viewed as operations on the set of their minterms.

sum and product of two functions are the union (n) and intersection (n) of their minterm sets, respectively.


While component-based design allows for modularization and component reuse, integration is still an ad hoc process, lacking the support of rigorous methodology, theory, and tools.

the design of the requisite communication and control logic to connect the blocks is a manual and error-prone process.


Given the correlations we observed between errors in the previous subsections, an interesting question is whether it is possible to predict an increased likelihood of future multi-bit or chipkill errors based on the previous error behavior in the system.

one might speculate that prior repeat errors, which likely indicate hard errors, will increase the probability of later multi-bit or chipkill errors.


SYSTEM DESIGN 2.1 Mote Design and Placement Designing our mote involved several mundane, but practical issues including proper design of vent holes and internal circuitry to provide optimal air-.ow and sensor response, optimal placement of the internal patch antenna, etc.

from interviewing several .eld operators of building management systems, we learned that traditional temperature sensors that are mounted on walls often are o. by a degree in Celsius or more compared to the actual ambient air temperature1.We designed our motes to have their sensors elevated somewhat from the surface they are installed on, and e.ec 1this applies even when both sides of the wall are inside the building, which implies that the temperature di.erence is due to convection, not conduction 421  Figure 1: Layout of the 99-node deployment tively mitigated this phenomenon.


From Table 1, we infer that the # of .its saved must be large in order to keep the PPF to a low value.

a Multi2 router must have a large degree of multicast transfers happening, which is highly application-speci.c.


Note that this somewhat unorthodox de.nition results in non-deterministic monotonic virtual counters.

the value of a particular virtual counter C is guaranteed to always increase, but can increase by unpredictable amounts, since operations on other virtual counters can cause the global counter to increment in between increment requests for C. This is not a problem, however, since for detecting forking and replay attacks as described in Sect.


It is understood that similar discussion applies to subtraction and minimum operations, as well.

given D1 and D2 in the form of (4), X D1 = d01 + (ai1Xi + bi1Xi 2) + ar1Xr1 + br1Xr2 1, (8) X D2 = d02 + (ai2Xi + bi2Xi 2) + ar2Xr2 + br2Xr2 2, (9) we want to compute D = D1 + D2 or D = max(D1, D2) such that the resulting D can be represented as (4).


The aspect ratio of the modules is allowed to vary in the design, providing significant power/access time/area tradeoffs.

each block (B0 through B15 in Figure 1) is a factor of 16X smaller than the traditional memory configuration; as a result, bit- and word-lines are reduced by a factor of 16X, dramatically reducing dynamic power consumption during access of a particular memory location.


Two types of RDF  1It should be noted that the state fault should be understood in the static sense.

the cell should .ip in the short time period after initialization and before accessing the cell.


Such cooperation and competition engendered by oscillatory nonlinear dynamics can produce complicated and beautiful spatio-temporal patterns of collective behavior.

pattern formation arising from the nonlinear interaction of many individual cells in biochemical systems is a fascinating and extensively noted phenomenon (e.g., [6] [8]) for example, an important issue in developmental biology is understanding the formation of spatial patterns in the embryo.


It yields reasonable result, but its ef.ciency is below what we had expected.


2.3.2 Finding Input Patterns for Maximal Overshoot Overshoot occurs when a signal momentarily exceeds Vdd .

overshoot is the global maximum of the output waveform of the system.


esoteric requirements such as Image Quality  which lead to a perception of smooth operation by the end user and pleasing visual results in the final image cannot be captured as a C model.


In this paradigm, though programmers can write code assuming independent execution of threads, the actual execution is in SIMD fashion to match the SIMD architecture.

a modern GPU comprises a set of streaming multiprocessors (SMs), within which a batch of the threads, referred to as warp in CUDA or wavefront in OpenCL, is executed in a lock-step manner.


PERFORMANCE RESULT The testing sessions have been carried out by sending audio and video streaming, remote monitoring and bulk data on different ports in order to verify the different treatment operated on different traffic flows.

real audio and video traffics have been captured by means of ZTI Sniffer Module, and replayed by ZTI IP Generator Module that also performs remote monitoring and FTP bulk data traffics with userdefined patterns.


As can be seen, SD+GPD (points with both a performance loss and cost increase) provides larger MTTF bene.t than SD or GPD alone.

at the extreme point, a guaranteed loss of 50%or an actual loss of 15% in performance (performance value of 0.5in Figure 7(a) and 0.85in Figure 7(b)), coupled with a cost 2.25times the base cost, provides an average MTTF 4.16times better than base MTTF.


We give a general class of problems in sensor networks where the event-triggered algorithm can be used.

this paper uses the data gathering problem as an example.


Therefore, one of the goals of this paper is to efficiently estimate reliability for further developing enhancement techniques.

this paper makes the following contributions: (1) A pseudo complementary CNTFET-based MVL design is proposed as an alternative to the previously proposed resistor-loaded and complementary CNTFET MVL (Section III).


In particular, the focus of the four papers included here is centered on the ideas of communication , platform-based design , schedulability analysis , and architecture exploration as foundations of ef.cient design for complex (possibly recon.gurable or distributed real-time) systems of the future.

these articles cover issues speci.c to both design methodologies and CAD tools for system-on-chip (SOC) communication infrastructure design, wireless (and ad-hoc) network design, and automotive electronics.


Moreover, we want an accurate analysis that, combined with a low-level analysis (i.e., pipeline timing analysis), allows us to obtain a tight WCET.


ACKNOWLEDGMENTS We would like to thank the anonymous reviewers and the Computer Architecture Group at Cambridge University for their constructive comments and suggestions.

we would like to thank Arnab Banerjee and Robert Mullins for their insightful discussions, Christophe Dubach and Timothy Jones for providing valuable feedback, and Kate Aufses for her assistance editing the .nal paper.


3.2 Scenario Two: Set S is not given andthe elements are not duplicable In Scenario One, when solving the optimization problem, the  2n-1 minimal difference i=0 ziri -q is actually a function of q, which we denote as h(q).


In this way, we can iteratively update the Elmore delay targets for each sink to compensate the errors.

we sequentially use a quadratic function akx+bkx+kas our approximation function, where ak,bk, and kare the respective new coef.cients for next iteration and new xis the Elmore delay target.


The current source loadings can be formulated as matrix · F · z1.1(j,j) R W (i, j)= r1 F .

grid vias are modeled as current loadings in brackets performs Hadamard matrix multiplication with from top layer to bottom layer which can be formulated as matrix W .


We adopted a fast-iterated Voronoi algorithm based on the Voronoi graph and dual graph, which is from K. Mehlhorn [7].

we improve it with space division to seek better performance for large-scale layouts.


The ADC is made up of 4 multi-bit stages and includes digital calibration circuits to enhance performance.

the Digital-to-Analog sub-Converter (DAC) errors are canceled with the DAC Noise Cancelation (DNC) technique [21] and the .rst stage Sample-and-Hold Ampli.er (SHA) errors are corrected through a Gain and Distortion Error Correction (GDEC) algorithm as in [22].


For further reducing the pipeline stages, a double speculation that performs the RC, VA, and SA operations in parallel is possible, however it would degrade the overall performance because of frequent mis-speculations and retries.

2.2.2 Look-ahead Router The look-ahead routing technique removes the control dependency between the routing computation and switch allocation in order to perform them in parallel, by selecting the output channel of the i-th hop router in the (i - 1)-th hop router.each router performs the routing computation for the next hop (NRC).


Various researches [4, 6, 26] have focused on solving this problem, but most of them concentrate on the allocation of CPU and network bandwidth, little attentions have been paid to alleviate disk I/O performance interference among virtual machines, which is a critical factor in determining the overall performance of I/O applications running in virtual machines.

once an I/O intensive application starts to run, the I/O performance of co-located applications residing in other virtual machines will be seriously injured.


As canbe observed,variations among the IPCs of the threads that belong to the same application are very low (below 2%).

in a .xed interval of time, the number of instructions executed by the di.erent threads of the same application are similar.


The memory allocator performs the block allocation such that the aggregation of blocks with same pattern are page aligned.

data blocks with di.erent access patterns are not allocated in the same page.


The mean and variance change over P/E cycles for the distribution for the P1 or P2 states is much larger than the mean and variance change over the same number of P/E cycles for the P3 State.

the voltage distribution of a state with a lower threshold voltage gets distorted much more with P/E cycles (this effect can be observed in Fig.


Utilizing the properties of Manhattan distance and coordinate transformation, we successfully encode the timing-safe regions of .ip-.ops into two interval graphs [6, 8].

to remedy the time and space complexities, we neither convert two interval graphs into one intersection graph nor enumerate all possible combinations of compatible .ip-.ops.


Thus, our lifetime management technique enables lossless compression only when the improvement of lifetime and performance is larger than an increase in energy consumption.

data compression is enabled if (1.0 - Dcomp) = (Ecomp - 1.0).


In the implementation of the hierarchical carry lookahead and carry select architectures the advantage of the hierarchization was used through the reuse of the code of another descriptions.

blocks common to several operators were described in a separate way so that they could be referenced as components in these adders.


BE exploits the network resource that is unused by the GS.

gS is always combined with BE in order to avoid the low resource utilization which is mainly due to the resource reservations for the worst-case scenarios.


The third author thanks Google for hosting her as a visiting faculty during the summer of 2009, where part of this work started.

she would like to thank John Hawley, Xin Li, Eduardo Pinheiro, Nick Sanders, and Wolf-Dietrich Weber for their help in accessing the data and answering questions about the data and systems at Google.


We take a different approach: we involve humans in the validation process.

we ask human voters to cast test votes on the voting machine during pre-election testing.


The aforementioned high-quality ADSWbased systems follow a similar algorithm-to-hardware mapping methodology.

a complex, but accurate, algorithm is adapted for dedicated hardware implementation through a series of algorithmic modifications/approximations.


ePE refers to the di.erence between the placements of edges of lines as well as other features in the printed image and those in the intended image.


The performance of the hardware-assisted sharing detectors, shown in Figure 11, is almost always higher than when using software.

the range based systems, even with low hit rates, can still outperform a software system that must check every memory access.


Through the evolutionary process into the E-Table, some rows in some F-Tables are ex- pected to be changed to match unknown case records whose categories are not identified.

through the evolutionary process, each E-Table is ex- pected to obtain generalization capability to catego- rize the unknown case records; i.e., the rules behind each category are expected to be embedded in the E-Table automatically.


As depicted in this figure, for all traffic conditions, total latency for data transmission is dominated by optical data routing through the waveguides.

in the case of light traffic conditions, latency of the control phase is negligible compared to the total latency, and this ratio retains small values even for high traffics imposed to the network.


In spite of the diversity of these oscillator circuits, we note that all of them preserve the monotonicity requirements upon which our analysis is based.

lemma 3 can be adapted to apply to each of these circuits.


Our prior work has shown the viability of energy harvesting energy meters [4].

we have shown that the energy emit ted from many electrical loads is roughly proportional to the energy consumed by that load, and that by harvesting this side-channel energy, it is possible to intermittently power sensors whose activation interval (and in turn packet transmission period) approximately encodes the underlying energy use.


This inherent synchronization is an important feature in the proposed scheme: both the generated stimulus frequency and the S. modulation in the evaluator are accurately controlled by the master clock.

the oversampling ratio keeps constant when sweeping the master clock frequency.


In open page mode, activate power is also a function of page hit rate.

higher page hit rate means same number of read and write operations could be completed with fewer activate operations.


The return value of FcmGen(k ), generated properties of subgraph k., is assigned as concurrent edge group of ns.

the concurrent edge group of ns becomes the set of generated properties from FcmGen(k ) where the number of concurrent edge group is one.


Proportional makes popular items easier to .nd and less popular items harder to .nd.

proportional replication requires a much higher limit on the maximum search size while Uniform minimizes this limit and, thus, minimizes resources consumed on processing insoluble queries.


Hence, SNR can be used as a quantitative measure of design optimality to compare different memory systems.

given the statistical algorithm developed in Section 3.2A, we can explore a number of design parameters (e.g., the number of rows MR, the number of columns MC, the word length N, etc.)


However,thereareimportantdifferencebetween [4] and our approach in handling the C++ language.


All these processor subsystems quasi-continuously face state changes at run-time and we are concerned with state changes which affect the temporal behavior of the executing tasks.

it is the case for task preemptions: when a task resumes its execution (after being preempted), for example, the cache(s) will display a state which is different from its state at the time the task got interrupted.


This leads ultimately to the point where the energy reduction potential of all variables in each blocks is balanced.

the balance of system intensity among all blocks, along with the block level optimality criteria described by eq.8 lead to minimum system energy at the right amount of quality, while meeting each block s target delay and system quality.


2.3 FF/Latch-Based Design Hold violations due to both FU and register sharing occur only if the output register is latch-based.

if the output register is FF-based, the lifetimes of the relevant data and operations do not need to be extended.


To the best of our knowledge, there is no design technique addressing optimization of design profit (instead of parametric yield at a fixed target delay), considering frequency bins and product price profile.

this paper makes the following contributions:  A weighted yield model to represent profit that considers price of ICs running at different frequencies and satisfying specific power dissipation requirement.


The end-to-end perturbation for HPMs is either within or close to the standard deviation of the executions without HPMs.

end-to-end perturbation is 2.77% for Cyc and 0.11% for InstCmpl, which is less than the standard deviation for executions without HPMs: 2.92% for Cyc, 0.23% for InstCmpl.


Such a modification obviously introduces discrepancies in all three components (delay, load, power) of a solution point.

changing the buffer size alters the leakage and input capacitance directly while the delay values are affected as a result of the parent node of the modified buffer encountering a different downstream load value.


The problem we address is therefore: assign VT s such that the leakage power is minimized while strictly maintaining the delay goal.

we seek to swap cells to a higher VT to absorb the available slack in the design without sacrificing delay.


Efficient ILP solvers are now readily available, both commercially and in the public domain.

for our experiments in Section 5, a public domain ILP solver (2) Assume rowi (corresponding to fault fi) and rowj (corresponding to fault fj) be two rows in the constraint matrix B. Rowi dominates rowj if (A) for each column k, if Bjk = 1, then Bik = 1, AND (B) if fi needs to be covered Ci times and fj needs to be covered Cj times, then Cj t Ci   fault fi is detected at least Ci times whenever fault fj is detected Cj times.


At the 35 nm node the pad pitch is forecasted to be 80 µm.

the linear density of the pads doubles for a fourfold reduction in circuit feature size.


We also enhance the RAMP reliability model by addressing some of its limitations.

we incorporate time dependence in RAMP s failure mechanisms by modeling them as lognormal distributions, and use Monte-Carlo methods to calculate processor lifetimes.


We introduce a buffering mechanism to hold write operations that may cause a page miss.

we propose to embed a Page Hit Aware Write Buffer (PHA-WB) mechanism into the DRAM to utilize the relationship between page hit rate and power consumption.


Both wire and TSV cross links are non-critical because each cross link is typically inserted between two points in the clock tree that have the same delay (or even better, same voltage waveform).

cross links are designed to deliver minimal (or no) current in an ideal situation.


In this experiment, ISBA tries to find the DPR scheme with the least reconfiguration delay within the resource limits as shown in Table II.

there are complex design constraints and the non-concurrency relations among candidate PR Modules.


In contrast, higher order effects that result from deep process scaling can impact the process balance more significantly by altering VT.

the short channel effect, reverse short channel effect, narrow channel effect, or reverse narrow channel effect can dramatically alter the relationship between PMOS and NMOS current.


3c) on the 0-branch of the control line D, not the second one.

the variable E must be set to 0, so that the fault-free complete path and the faulty path (in the presence of the above type-2 fault) arrive at the two complementary leaf nodes of the BDD.


The variable scope of an advice is equal to that of its woven context.

an advice can directly refer variables of its woven context.


For developers, this means a gradual migration path, performance scalability at a reduced engineering cost, and vendor independence.

it dimin- ishes the impact of legacy code.


It is interesting that the solution to (10) is a linear operator acting on q.Moreover, the L+ 1 parameters .i control the degree of smoothing applied to each of the L+1 segments of q.

even though .0,...,.L interact, .i mainly controls the quadratic variation of the segment x(ki,ki+1).


Note that, these percentages are valid for each nest of each application.

in each loop nest, the same percentage of TABLE IV STAT I S T I C S W H E N 20% OF T H E I DL E P RO CE SSORS ARE USE D FOR COMPUTAT ION DUPL ICAT ION .ASC O M PA R E D T O TABL E III, WE HAVE MORE CYCL E S AND MORE E N E R GY CONSUMPT ION HE RE DUE TO DUPL ICAT ION .


at least one stream in the kernel (either an input or an output stream) has to be declared as a proper stream (i.e., not a scatter/gather stream).


Speci.cally, this model makes sure that if the num ber of extra grid cells allocated for netis S;, it is possible to extend length of netby an amount equal to S;through snaking.

resource allocation is done in such a way that every allocated grid cell can be used for snaking later.


2.1.4 Compare Speculation By default, compares have to be treated as non-speculative instructions because they may control other non-speculative instructions (e.g., conditional branches) by means of the predicates they generate.

we have introduced predicated code motion in Sec.


We consider here only a subset of them to keep our analysis tractable.

we compare a heterogeneous policy, which allows the controller to assign different voltage and frequencies across the cores, to a homogeneous policy, where the same voltage and frequency is set for all cores.


In this paper, we enhance Karfa s algorithm by further defining the equivalence of paths for Sp and RSp, as well as introducing the notion of available statements to handle CSE.

our algorithm can verify scheduling generated by code transformations employing speculation and global CSE.


We believe our work lays the foundation for more work in this space.

we are currently extending our evaluation to consider other power management solutions, but are particularly interested in extending our architecture to include coordination with the equivalent spectrum of solutions in the performance and cooling domains.


Since the idle and loaded memory latency reductions are both important to address, we will focus the discussion on some micro-architecture approaches to reducing idle and loaded latencies.

we will discuss some aspects of the Intel E8870 memory controller micro-architecture and its optimization for reducing idle and loaded latencies, avoiding deadlocks and livelocks while maintaining coherency.


If the .it is to continue traversal to the west, it is buffered in the dx VC.

dx and dy VCs are used for on-going .its along the same dimension, while txy and tyx are used for changing from the Row-Module to the Column-Module and the other way around.


increasing the error probability in the switching process [8].

this kind of wire can be considered equivalent  Fig.


The switching activity of the FSR can take any value between 0 and n. Opposite to most other systems, the switching activity in an FSR has a regular distribution.

the number of internal states of an n-bits FSR with switching activity i is equal to the binomial coe.cients of i out of n: !


Table 2 shows an excerpt of the results related to network performance.

a subset of all the scenarios is presented with an increasing level of network complexity, enabling the comparison between simulation and experimental results for the e2e-BE delay, as well as between simulation 6Rememer that larger system scale can be achieved through the multiple patches mechanism.


Using information from the control models, we relax some of the typical conservative assumptions that are usually made in the design and development process.

we show that is possible to meet performance requirements even if some control-related messages are lost in the communication bus.


2.3.2 EIDF and EIDD Similar to IDF in text document analysis, EIDF of an audio element ci can be computed as the log of the number of all documents divided by the expected number of documents containing the audio element ci.


However, there is still a chance that a transient error can strike during execution of an unduplicated computation, which cannot be detected by our approach.

TABLE I MAJOR SIMULATION PARAMETERS AND THEIR VAL UE S.   Parameter Value Number of Processors 8 8KB L1 Instruction Cache 2-way associative 32 byte blocks 8KB L1 Data Cache 2-way associative 32 byte blocks 1MB L2 Cache 4-way associative 64 byte blocks L1 Dynamic Energy Consumption 0.16 nJ/access L2 Dynamic Energy Consumption  0.65 nJ/access r 0.1 Reactivation Latency 4cycles Off-Chip Memory Energy  6.32 nJ/access Off-Chip Memory Access Latency 80 cycles On-Chip Bus Arbitration Delay 5cycles Replacement Policy Strict LRU while we increase the resilience of execution against soft errors, the number of errors we actually detect is another matter, and depends on error injection rate, error injection pattern, and other factors.


Through this tutorial we show the benefits high-level languages offer for system-level design and productivity.

altera s OpenCL compiler is shown to enable high-performance application design that fully utilizes capabilities of modern FPGAs.


However, this approach adds to the computational burden of the synthesis tool.

if a routing plan involving all the droplets on the array is generated for each chromosome in the PRSA-based unified synthesis method, the overall synthesis time will be overwhelming due to the large number of chromosomes and evolution steps in the synthesis flow.


In order to detect data corruption, the Mapping Manager also keeps checksum information of each data block along with the mapping information.

the validity of the data is checked using the checksum value.


2 Hard Faults in Microprocessors In this section, we discuss the hard faults that motivate this work.

we focus on the technological trends that are leading towards greater incidences of these faults.


As depicted in these figures, in general, 2DHERT is the most efficient optical architecture under various traffic patterns, while ETorus leads to the worst power and delay metrics compared to the optical architectures.

averaging through different traffic patterns, 2DHERT ONoC reduces data transmission delay by 18%, 4%, and 70% over OXbar, LR, and ETorus, respectively.


It communicates with actual microcontroller C programs compiled and loaded into the SystemC model of the microcontroller, rather than with mathematical idealizations of program behavior.

system interrupts, computation time, microcontroller CPU states, and the busses are all cycle-accurate representations of the hardware being designed, validated against HDL simulations.


Therefore, for any trace, it is suf.cient to solve the trace and its two adjacent traces via numerical extraction.

we are able to reduce the n-trace capacitance problem to a number of 3-trace subproblems.


(9) In (5)-(9), the DCT coefficients {G(u, v); u = 1,2,...,P, v = 1,2,...,Q} are the problem unknowns.

we need to determine {G(u, v); u = 1,2,...,P, v = 1,2,...,Q} based on the measurement data {g(xm, ym); m = 1,2,...,M}.


This is because that we have to partition not only solid polygons, but also empty space areas in corner stitching.

to partition empty space areas, one can partition a polygon which is created by inversely transforming the original empty space into solid space and transforming the original solid polygons into holes.


If the input skew is su.ciently large, the short-circuit power accounts for most of the clock power.

any e.ort to reduce the total clock mesh power must attempt to minimize the shortcircuit power.


Rn and z .Rq, which in conjunction are the design variables for each of S applications, or scenarios.The variable xmust be chosen before the particular scenario s is known; the variable z, however, is chosen after the value of the scenario random variable is known.

z is a function of the scenario random variable s. To describe our choice for z, we list the values we would choose under the di.erent scenarios; i.e., we list the vectors z1,...,zS .


Similar to the input setup time, the enable signal should be stable before the rising edge of the clock.

the clock frequency of the design will be slower proportional to the delay introduced by the clock control logic.


Since p is a probability, we need prior distributions de.ned over [0,1].

for mathematical convenience one uses Beta priors, which are de.ned by the following probability density (for real parameters a,ß > 0): .u .


The performance of these applications is limited by the high cache miss rates resulting from their large instruction and data footprints [1-5].

a large fraction of their execution time is attributable to cache misses that result in off-chip memory accesses.


During design testing but before fabrication3, the inserted checks will detect actions that violate security and translate those actions into pre-speci.ed (by the hardware designer) nonviolating actions.

policy violations will show up during the design testing phase as functional bugs.


We emphasize that the main utility of this operator-based approach is that the choice of solution method of the linear system at each step of the model-order reduction procedure can be made completely dynamic.

the original system does not need to be discretized a-priori using a given frequency-or timedomain technique.


Our aim, with the SMARTdriver, is to delay the response for the best-case without a.ecting the worst-case, so that the variation in delay becomes as small as possible.

the concept is to make the response slower with minimum e.ective capacitance, as the cycle delay has to be set to the worst-case delay anyway.


With the help of this simulator, we can infer (Table 1) end-to-end delays for both real-time and best-e.ort tra.c, as well as compute network statistics such as packet loss, network throughput and lifetime, via per-node energy consumption estimation.

this simulation model gets user-de.ned attributes (network topology and nodes parameters) through an XML .le, which we automatically generate through an ad-hoc MATLAB script, which takes as inputs the outputs of the Network Deployment Simulator (i.e., nodes positions and parent-child relations, Section 3) and the windows o.set de.ned by the TDCS scheduling tool (Section 4.1).


Moreover, the number of bu.er and wire size options for clock network is often small.

the bu.er and wire sizing problem for ASIC clock networks is highly discrete.


At this point, if P2 rises, then the PLA p enters the evaluation phase.

if the PLA p has been precharged, and if the PLAs a level below complete their computation, then p enters the evaluation phase.


As shown, nine MSBs from a row address is used as a sub-region index.

a row in one PCM bank is virtually partitioned into 512 sub-regions.


Any higher noise amplitude will result in there snm remaining a single equilibrium state, making the SRAM cell unable to store either 0 or 1 .

if the remaining equilibrium state represents a 1 , the charging/discharging process on the two capacitors will pull any initial state, even if it is a 0 , to the only equilibrium state 1 .


Deploying a ring in a modern CMP requires aggressive implementation techniques.

to minimize latency a ring-based system should immediately forward request messages to the next node (i.e., eager forwarding [47]) instead of .rst performing a snoop and then forwarding the message.


In this way, we can guarantee there are as many don t care bits as possible in the selected seed at each step, and the each seed can embed more test cubes.


We also believe that HIP does consume more power beside the non-HIP applications if compared to the data throughput.

due to a lower bitrate caused by ESP data Table 3: Power consumption by applications.


Please note that this worst-corner resides in the opposite side of the variation space compared with the worst-corner of the time constant.

the worst-case interconnect structure (cross-section) for a short interconnect moves toward the best-case as the interconnect length increases.


Waiting for 50 cycles before deciding whether or not to exit runahead mode reduces the probability of prematurely incorrect predictions).

if too many of the loads executed during runahead mode are INV, this is used as an indication that the current runahead period will not generate useful prefetches, therefore the processor is better off exiting runahead mode.


We also take the assignment constraints into account during scheduling.

we only schedule memory operations in parallel if a con.ict exists between their corresponding data in the con.ict graph.


Following convention, we refer to the wire of interest as victim and the coupling wires as aggressors.

the switching of the aggressors around the same time as the victim transition causes changes in the delay of the victim signal.


However, our experiments reveal that the maximum voltage difference between cores at each dynamic V/F scaling (DVFS) interval is small for most intervals when the voltages are optimized to maximize the performance under a power constraint.

the VO values of multiple LDO VRs can be close to the shared VI value.


This result indicates assigned to a cluster that does not already have (and will not soon that, in the integer applications we examined, critical data.ow exhave) ready instructions.

choosing the least-full hibits very modest ILP; equally, non-critical data.ow is very tolcluster in these circumstances is not always appropriate.


These testcases come from hard Combinational Equivalence Checking (CEC) problems of HDL speci.cations against their gate level implementation.


Butingeneral, the2and 3-reused lines have longer life span than 1-reused lines.

for 1-reused lines, which take a notable fraction(40.8%) of all lines, the .gure shows the major portion of them concentrates at a short life span.


The state of the chemical reactor is the 5-tuple (nA,nB,nC ,nD,nE ).

the state consists of the number of each type of molecules in the chemical reactor.


Here, a mechanical stress buildup causes a reversed migration process which reduces or even compensates the effective material flow towards the anode (Figure 6).

a conductor line is not susceptible to electromigration if the product of the wire s current Figure 4.


- All paths that belong from MaxNS to MinNS are divided into 2 groups by DivNS.

they are divided into group A (MaxNS to DivNS) and group B (DivNS to MinNS).


Section 3 deals with implementation issues.

it describes the aggregated bitmap data structure and shows how it can be used to implement the LR(T )CMA.


While the requirement to operate at slower frequencies doesn t affect timing analysis, it does affect noise analysis.

a chip that meets timing requirements at fmax will also meet timing requirements at slower frequencies, but a chip that operates at fmax can fail at a slower frequency due to noise.


Note that the number of grid partitions needed is determined by the process, but not the circuit.

the same correlation model can be applied to different designs under the same process.


It has been proven effective in recent detailed evaluations on a range of traf.c for chip multiprocessors (CMPs).

for the CMP platform introduced by Vishkin et al.


This is not encouraged because it will lose the original spirit of H.264.

achieving big gain by accumulating small gain in every part of the coding process.


2.2 Other combinations of static and dynamic analyzers 2.2.1 Reverse engineering The combination of static and dynamic information extraction is used in other domains.

several reverse engineering techniques use a comparable approach: in [9], the dynamic analysis is used to re.ne the result of the static analysis and eliminate false positive in design pattern recognition, and in [14], the static and dynamic information are combined to generate UML diagrams.


For instance, patterns of these .gures could be recognized, suggesting one architectural choice over another.

the .gures related to the channel analysis could suggest the use of a communication mean rather than another.


Finally, to achieve extreme performance gains from memcomputing, we also implement the idea of having a speci.c memcomputing cache as suggested in [6].

this cache is used exclusively to accommodate LUTs for inmemory computation, and this is achieved by inheriting the Cache class and assembling it to the system through the .exible python-enabled con.guration scripts in gem5.


Figure 4(b) shows the stall circuitry after our modi.cation.

the combinational logic that generates stalls is now replaced by a more sophisticated .nite-state machine (FSM).


A negative delay indicates that the client may receive packets out of order.

a client bu.er is needed or packet dropping is expected.


To achieve these goals, the cost function for each grid node used in a routing path is augmented by a penalty function for each routing directive.

the PathCost formula (see VPR [3]) is modified in the following manner to account for the effects introduced by bias factors: PathCost (n) = PathCost (m) + num _ factors PresCost (n) · HistCost (n) ·.


One general principle of the damage assessment planning is that anyone performing the study must not interfere with authorities specially those performing rescue operations and needs to be as much self sufficient as possible in order to minimize the use of resources of the people affected by the disaster.

anyone participating in a damage assessment should plan to carry its own sufficient rations of food and water.


In the ST regime, our method outperforms the method in [9] by achieving better energy-delay trade-off curves, as shown in Figure 9.

we provide the same softness with lower energy consumption by using the proposed DL design.


We also specify that the instruction is executed only when ?

p -n. the instruction is disabled when p or p: -n, where nrepresents the original loop counter.


The results show consistent reductions in violation counts for these checks.

the number of violations of the minimum spacing check is reduced by 80%.


Each edge represents a driver-sink path along a net and is associated with a delay value which is linearly proportional to the distance between the driver and the sink gate.

we decompose each multi-pin net into a set of 2-pin edges which connect the driver to each sink of the net.


The objective of our work is to develop techniques that permit these measurements to be used to predict the corresponding sample of d on the same die.

we de.ne the problem of post-silicon statistical delay prediction as .nding the conditional PDF given by f(d|dt = dr).


By applying and interpreting the results from Canonical Correlation Analysis we are able to determine both simple and more complex correspondences between features of motion and features of sound in our data set.

the presence of a distinct pitch seems to in.uence how people relate gesture to sound.


Then the n ×n matrix A is partitioned into in/blblocks, of size n ×b.

each block contains b columns of A.At the same time, the n ×1 vector x is partitioned into in/blblocks, of size b×1.


4.W.1.2 Transforming into a MLGP Prob/em In this section, we show that, for a given wire order as obtained by the algorithm in section 4.2, the formulation in section 3 can be transformed into a MLGP problem.

it can be shown that the constraints (a)-(g) can all be expressed in the form of: f (Wi gsi; ) h( Pi gdi gAyie/d gAtiming )(I6) where f (Wi,si;) represents a posynomial function of Wi and si; g and h (PigdigAyie/dgAtiming) represents an affine function of Pi, di, Ayie/d and Atiming.


pixels with insufficient drivability) at the expense of slight increase in the operating frequency of peripheral circuits.

to maintain the same refresh rate, the charging time of each row of pixel array is slightly decreased for creating timing slacks which allow a few rows to execute two-cycle operation.


To exploit this fact, we use an adaptive mechanism that prefetches larger amounts of data (2 values in our case -see .gure 3) only when a load byte instruction misses in both the prefetch bu.er and the RB.

prefetch is enabled for speci.c instructions that are known to show locality.


The kernel operates on sub-blocks of a video frame, trying to .nd each sub-block s location in a previous and/or future reference frame of the video stream.

in H.264, motion estimation is computed in two steps: IME and FME.


The immediate future work will be focused on this line.

on the study and integration of a prototype for this solution.


Conclusions We proposed a new BIST architecture for sequential circuits, which is based on CSTP and improves it by removing some of its drawbacks.

the architecture is based on a new cell that may implement any 4-input Boolean function.


As long as the design is in a reasonably good state after applying fast optimization, one can always apply slower, but more accurate optimization to further polish the design.

the philosophy is to get it done as fast as possible even though you may make some messes along the way.


Fortunately, this work also indicates that signi.cant commonality exists in TLB miss patterns across cores of aCMP.

a large number of TLB misses are predictable inthat they are caused by virtual page accesses seen on multiple coresor by virtual pages that experience repetitive inter-core strides.


Then, we propose a routing graph, called preferred direction evading graph (PDEG), embedding the optimal solution for the OAPDST problem.

if there exists an optimal solution for the OAPDST problem, at least one must be found on PDEG.


4.1 Scheduling for power management Task scheduling on single or multiple processing elements is considered as one of the most common methods to achieve lower power consumption.

in light-weight embedded systems, scheduling saves power by shutting down devices when they are not operating.


The sparsity can be analytically deduced from equation (7), where collocation points and variables related to each other are within the same medium.

collocation points and variables in different mediums have no direct numerical relationship.


However, we show that the clustered architecture benefits from value prediction more than a centralized one, since value prediction removes some inter-cluster communications.

we show that the IPC degradation caused by inter-cluster communications can be reduced by 18% through a simple value prediction scheme when the steering logic is designed to take advantage of the value predictor.


With scaling, it is expected that this metric will be greatly improved.

if the junction diameter is decreased from 300 um to 30 nm, the junction area and current will decrease by a factor of 108, and if the length is decreased from 400 um to 40 nm, the delay will decrease by a factor of 104.


It is easy to see that the time complexity of the algorithm is on the average linear with respect to the product of these two figures.

it is faster than quadratic considering that the number of unique references N is much smaller than the number of total references N.  Benchmark Time (sec) Benchmark Time (sec) adpcm 2.9 adpcm 27 bcnt 0.11 bcnt 0.13 blit 6.8 blit 2.0 compress 290 compress 30 crc 0.80 crc 5.1 des 19 des 31 engine 28 engine 56 fir 0.67 fir 2.3 g3fax 1200 g3fax 390 pocsag 3.2 pocsag 8.2 qurt 0.090 qurt 0.20 ucbqsort 23 ucbqsort 31 Table 8: Algorithm run Table 9: Algorithm run time: data traces.


This solutions is low-complexity, avoiding the additional cost of coherency protocol, which is often used by state-of-the-art synchronization solutions.

we show a spin lock implementation requiring a constant number of network transactions and memory accesses per lock acquisition.


In these situations, we need an optimized communication block.

we automatically insert a reuse buffer [15] that stores data that will be temporally reused.


In the sequel we extend the observations made here to arbitrary number of items (m =2).

we develop a notion of an allocation being between Uniform and Proportional and show that these allocations have better ESS, and that outside allocations have worse ESS.


However, the amount of reducing leakage current in this technique is limited because low-Vth cells still exist on the critical paths.

as long as the number of low-Vth cells is not a negligible share, the leakage current would not be lowered to the value at the design with single high-Vth.


This is shown in Figure 10, which plots the standard deviation of each of the samples of a pulse.

all possible samplings (different starting points) of the 25Gs/s data was sampled at 70MHz.


The proposed Gibbs sampling adaptively explores the variation space so that a large number of random samples fall into the failure region.

it iteratively samples a sequence of one-dimensional PDF s by an efficient inverse-transform method.


For both memory and logic chips, the result has been exponential increases in speed and functional density versus time combined with exponential decreases in power dissipation and cost per function versus time.

the number of logic transistors and memory bits per chip have been quadrupling every three to four years, while the speed of microprocessors, for example, has been more than doubling every three years, increasing from about 2 MHz for the Intel® 8080 in the mid-1970 s to well over 1 GHz for current leading-edge chips.


In the IQC framework, the nonlinear functions can be bounded using sector-bounded limiting nonlinearity.

the nonlinear functions in a system are replaced by linear functions that are upper bound of the nonlinear functions.


ME T S: Metric for Electro-Thermal Sensitivity Contrasting electrical and electro-thermal simulations can evaluate the particular contribution of self-heating for a particular device at a speci.ed temperature.

at a particular temperature in Figure 4(a), the difference between Ia and Iet is the degradation in current due to self-heating.


If the resulting OM is greater than 1, then it is clamped to 1.

theorectically, it can be shown that [16] if a signal f has an observability measure less than 1, then the input vector v under consideration is not in the B oolean difference [1] of the output z i with respect to f. a fault effect at f cannot be sensitized to z i under input vector v. As a result, it is safe to conclude that f is a false single defect candidate because it is not solely responsible for the failing output under consideration.


In this section, we would like to show how we can utilize that information to reduce energy consumption of cache hierarchy comprising nonvolatile memory.

we incorporate our predictor into SRAM/STT-RAM hybrid caches to reduce write energy consumption of STT-RAM.


A .oorplan is L compact if and only if there is no block that can shift left from its original position without overlapping other .xed blocks [19].

a .oorplan is L-compact when it is x direction compacted to the left edge of the chip.


Therefore, the proposed protocol is narrow does not need to derive it from rs1.


The characteristics of the MPEG-2 Encoder algorithm are good to highlight the main challenges of designing a complex SoC accelerator.

its system-level block diagram contains struc- Fig.


When there are function calls in the function being processed, it becomes a little complicated, since variables might be modified inside the callee function.

the function call site can act like a store to variables, and in some cases we cannot know exactly which variables are modified by the callee function.


Assume the the maximum variation on switching delays of the crosspoints is 200%.

if the expected switching delay of the crosspoints is T ,then for a crosspoint it can be a value between T and 3T .Therefore, in the worst case, the delays of both crosspoints n1 and s1 are 3T , while delays of n2 and s2 are T .


When constructing model reduction algorithms for distributed systems, we must keep in mind that the condition in Equation (4) is not suf.cient by itself to insure passivity.

it is known that passive systems are required to be causal [9, 10].


Empirical Results We have imp lemented the most straightforward version of the edge-mask idea.

we created edge masks only for full clock domains, but not yet for any of the more complicated exceptions.


This re-sampling method guarantees that: (1) The training and testing sets do not have overlapping samples.

the verification of accuracy performs classification only on samples unknown to the training process, thus providing unbiased accuracy estimations.


4.3 Connection to multigrid The efficiency of classical multigrid methods is built upon aproper understanding of the properties of relaxation methods suchas Guass Jacobi and Guass Seidel.

they are quite efficient in removing spatial high-frequency solution errors while being ineffective for damping long-range low-frequency errors.


Most tuning algorithms use trial-and-error mechanisms to arrive at the optimal configuration.

they simply try a series of different configurations and determine the best one.


Translation Caching: Skip, Don t Walk (the Page Table) Thomas W. Barr, Alan L. Cox, Scott Rixner Rice University Houston, TX {twb, alc, rixner}@rice.edu  ABSTRACT This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page table.

these caches accelerate the page table walk that occurs after a miss in the Translation Lookaside Buffer.


In this paper, we explore some of the limits of FPGA side-channel communication.

we identify a previously unexplored capability that significantly increases both the potential benefits and risks associated with side-channel communication on an FPGA: an in-device receiver.


More recently, a number of theoretical results show that polynomial-size, bounded level networks of threshold gates can implement functions that require unbounded level networks of standard logic gates [24].

important functions like multiple-addition, multiplication, division, or sorting can be implemented by polynomialsize threshold circuits of small constant depth.


We remind the readers that our STM library itself is a very complicated piece of software which orchestrates the correct execution of our tightly-coupled HW-SW system.

there was no way of writing simple test-bench for our system level simulation but executing the whole software.


As the number of test structures is increased, more information can be derived about variations on the die, and its delay PDF can be predicted with greater con.dence: the standard deviation of the PDF from SSTA is always an upper bound on the standard deviation of this new delay PDF, as shown in Figure 1(d).

by using more or fewer test structures, the approach is scalable in terms of statistical con.dence.


We want to identify branches whose outcomes infer a value range of the same variable and the range (of the store) subsumes the range of the load.

to put it in a simple form, our goal is to discover the follow relationship: branch bs s directionÎstore st s range; store st s range subsumes load ld s range; load ld s rangeÎ branch bl s direction; such a relationship indicates that from branch instruction bs s direction we can know bl s direction exactly.


After that, we have randomly chosen a set of nets from each benchmark circuit to impose matching constraints on, and we have removed their global routes.

we have chosen the nets with driver-toreceiver distances between 100 and 200 GR grid cells.


However, many great challenges must be addressed in order to achieve the above aggressive goals.

in FB-DIMM architecture, AMB is treated as a passive synchronous device.


3.2 Solution In this section, we describe the solution technique to deal with the semantics we are going to adopt in the MCS modelling.

we refer to the technique developed in [4, 10, 11] to evaluate reliability and availability of systems subject to changes in the environment.


As a result, the system current is no longer conservative.

the current drawn out of the power (vcc) net is not always the same as the current sinking into the ground (vss) net.


These environments provide digital logic elements at a level of abstraction that allows students to experiment with basic digital design issues.

logisim provides a friendly educational tool for performing basic digital simulations [4].


After that, grouping is performed in a way similar to heaviest-.rst selection in the knapsack problem.

dFGs are selected with most PE requirement .rst and packed into a sack while the capacity of the sack is not exceeded.


The superior node conditions above are insuf.cient to guarantee that an added edge will preserve the minimum cost of a superblock.

exits require special treatment because a transformation which forces an exit to be scheduled later can increase the minimum cost.


A Universal Approach to Data Center Network Design Bruce Maggs Department of Computer Science, Duke University Durham, North Carolina, USA Abstract This talk proposes an approach to the design of large-scale general-purpose data center networks based on the notions of volume and area universality introduced by Leiserson in the 1980's in the context of VLSI design.

we suggest that the principle goal of the network designer should be to build a single network that is provably competitive, for any application, with any network that can be built for the same amount of money.


Although many core architectures potentially provide increased performance, they also suffer from increased IC power densities and thermal issues are a serious concern in latest designs with deep submicron process technologies [5, 8].

it is key to design many core designs that prevent hot spots and large on-chip temperature gradients, as both conditions severely affect system s characteristics.


The increased application of RET techniques clearly points out that wafer lithographers are applying sub wavelength lithography in a regime of declining printing contrast so that reticle CD errors do not transfer linearly to the wafer.

errors on the mask are not reduced by the same reduction factor as in the stepper.


Here, data lifetime intervals are said to be un-overlapping .

those two data can be stored in the same storage element.


3.5 Maintaining the A-pipe success rate Since an instruction gets only a single chance at preexecution in the A-pipe, a deferred instruction and all its data.ow successors (until an update arrives from the B-pipe) will fully expose any stalls associated with the consumption of their results.

the twopass scheme provides one second chance to expose ILP; for these instructions, that chance has been lost.


Note that the fault coverage reported by our .oating-mode fault simulator is fault size dependent since some faults going through short paths are ATPG untestable with small fault sizes.

the best fault coverage is not necessarily 100%, and the comparison is relative among the three methods.


For instance, given four load instructions load a[i], load a[i+1], load a[i+2], load a[i+3] scheduled in consecutive clusters and marked as interleaved mapping, only one of them is marked to prefetch the next L1 block to the buffers (POSITIVE prefetch in case variable i is increased at the end of the loop).

only the .rst instruction in the .nal schedule is marked.


Significant computational savings can be realized, however, by solving them together.

a solution is found for the common prefix, which is then extended or slightly modified to obtain solutions to each of the m extensions.


In the case of loops, the marginalization must be done combinatorially over a region of the network that bounds the loops in order to guarantee maximum probability solutions.

one would partition the network into a loop-free network of blocks which internally contain loops.


That is, the random placement will allocate memory objects into the S sets with a probability of 1/S while the random replacement policy will evict a way to allocate a new fetched cache line with a probability of 1/W .

an access A will miss only if a previous access misses in its same cache set and it randomly evicts its cache line.


The SIGMA and IKE protocols followed here have been rigorously analyzed and proven correct [6], which is a major bene.t in any system planning to be evaluated at the highest levels of the Common Criteria.

see [28] for more details on the cryptographic rationale of these protocols and the subtle cryptographic attacks they prevent.


Properties of the Veri.cation Algorithm We will now investigate the properties of the veri.cation algorithm.

we prove that the algorithm is sound, that it is complete (under the assumption that the auxiliary procedure Interpolate returns the right assertions), and that its time and space complexity is polynomial in the data complexity of the input program and speci.cation (again, under the assumption about Interpolate).


(2) What used to be indirect (global) memory references for x in col vector (for the CSR format) are now direct (local) memory references for y in the row vector.

when a column of A is multiplied by an element of x, in the manner shown in Fig.


These implementations are generally applicable to the forward stage as well, although our benchmarks do not exercise this stage.

in our experiments, the PNI always acts as a consumer, or observer, of packets.


The results indicate that the Wi-Fi logger may reduce the battery s lifetime by 9% at least, 14% in average, and 27% at most, since 60% of people use their 5 Day 1Day 7 Used Storage (Mbytes) 4 Day 14 3 2 1 smartphone for 14 to 41 hours with a single battery charge [31].

a user can use the smartphone with the proposed system for 12.4 to 31.8 hours depending on individual usage patterns.


At low voltages, ...... -....h decreases making it more sensitive to changes in ....h. Hence higher temperature increases the delay at high voltages, but decreases the delay at low voltages.

depending on the magnitude of ......, the delay increases or decreases as temperature grows.


Second, for different bit cells in the same column, they share the same Bernoulli distribution.

while different bit cells in different columns correspond to different failure probabilities, all bit cells in the same column share the same failure rate.


Such high design and performance overheads are apparently unaffordable in embedded and on-chip applications.

the error rate of an MLC cell must be signi.cantly reduced (i.e., down to ~ 10-6 )so that the error rate of a 64B cache line can be improved to ~ 1.5× 10-8 .


If we assume the function contains 1K instructions, the tag will have 10 bits.

the size of the tag could be much larger than the information to be store in BSV and BCV.


We use a simple example to illustrate the idea.

we want to show how the states and transition probabilities are de.ned.


Each new instance is assigneda functional orfail labelby comparing the elements I of Pk with the limits in Table I.

we have .xed the limits of the j-th performance metric at a distance 3.9sj from its mean value, µj, where sj denotes its standard deviation.


Compared with C/DC, S/DC significantly reduces the redundant prefetches through the three filtering mechanisms while issuing comparable new prefetches.

s/DC_conf0 only avoids generating redundant prefetches when handling stride patterns, and S/DC_conf1 can further eliminate most of the redundant prefetches generated when handling other DC patterns.


This is not always the en2 u R3 en1 S3:    en1 en1 R3: case.

actors often have data-dependent behavior.


As can be clearly observed from the .gure, the time distance between two adjacent misses from the same instruction is likely to be small.

31% of the intervals are only one miss, which means that the corresponding misses are required by certain instruction continuously.


Since the serial scan mode requires a full scan test pattern, it is very important to reduce the number of test patterns applied in the serial scan mode.

reducing the number of conflicts across multiple scan chains is a key factor for test compression, and heavily dependent on the scan chain configuration, i.e., the number of the scan Figure 3.1 (a).


For example, while discrete event traces only de.ne a partial order between events, their corresponding simulation traces are made up of a total ordered set of events, according to the simulator s MoC.

the discrete event simulator de.nes a mapping from partial ordered traces to total ordered traces de.ned on the underlying simulation time.


However, in our opinion, additional work in this direction is required.

in the field of logic circuits, estimations of performance/count devices improvements obtained through the addition of RTDs have been evaluated for a set of logic functionalities (combinational gates and flip-flops) [13], [14] but without taking into account their usage in gate networks.


The method used combines the advantages of 3D device simulations and SPICE circuit simulations.

we use 3D device simulations to characterize current pulses for ion strikes and later these pulses are used as inputs to SPICE circuit simulations for the emulation of ion strikes on standard cells in a commercial ASIC library.


In this case, we conclude that the solution already converges to the optimal solution.

the iteration stops when v =s/6 where s is the current approximation error bound (gradually approaching E).


POSITION SELECTION FOR ADJUSTABLE DELAY BUFFERS In this section, given a clock tree, try to select m positions of clock buffers to be replaced by ADB wes so that the cost function in EQ1 is minimized.

we select m ADB positions with the minimum cost calculated by MPMLP.


rors using the dictionary of autoregressive models estimated by £1-regularized methods.

the .gure shows the percentages of false positives and negatives due speci.cally to octave and note transition errors.


The nominal RSNM of case (C) (90mV at Vdd = 0.4V) is comparable to the value of the 10T bulk subthreshold SRAM (~ 90 mV at Vdd = 0.4V) [8].

the 6T UTB SOI SRAM cell with back-gating technique can provide sufficient margin for subthreshold operation comparable to the 10T bulk subthreshold SRAM cell.


5.5.1 Jump detection (Jumpdet) Vehicles that move at a high speed, or vehicles that move on highly sloped roads tend to observe a large rate of height change.

they undergo jumps in height, both in the up and down direction.


Hence a data transfer no longer occupies the whole wire within a cycle but uses only a wire segment instead.

at a single cycle, a long dedicated wire between two clusters can be shared by several data transfers as long as these transfers do not use the same segment.


Since the applications are networkbounded, we would like to increase as much as possible the rate of remote memory operations issued, and injected on the network.

we would like to match the injection rate sustained by the nodes and the network bandwidth, to avoid, or at least minimize, the undesirable stalls for the core pipeline(s) caused by remote memory accesses.


It was a hardware test to see if the system was routed properly.

it was a test to see if the system was operating the right functions.


According to the original paper, a physical address is mapped to one memory line for 1 × K writes before this physical address is migrated to another memory line.

1 × K is large enough to consume one half of the lifetime of one physical cell, thus two rotation phases are good enough to fail the system.


For the 4SM, we can also adopt the architecture of the 8SM.

to use permutation network and selector instead of the 16-byte cyclic shifter.


In this case, the new first hop direction is other than the original one.

if the old direction is in x direction, the new one will be on the y direction, and vice-versa.


We are able to significantly reduce the data segment size of safe partitions showing the efficiency of our pointer analysis.

using the old partitioning algorithm, the percentage of mean data size to full data size ranges from 0.15% to 1.39%.


The tool represents a best-efforts approach because it utilizes dynamic analysis to detect write skew.

it does not provide full soundness in the sense of guaranteeing the detection of all write skews.


As shown in Figure 3, [15] usesonly one type of CWSP element.


Table 2 shows how the merging affects the power and area.

before and After show the area and power estimations for the corresponding operations before and after the merging, respectively.


CONCLUSION We have investigated the classi.cation of activities from environmental RF-signals.

we exploited the .uctuation in the time evolution of the strength of a received signal due to movement and activities of individuals in proximity.


In addition, the user-de.ned logic is also treated as a wrapped core.

the SOC is assumed to contain wrapped cores and interconnect wires (or simple glue logic) that are affected by signal integrity faults, without large blocks of logic between the embedded cores.


Reviewing the base functions outlined in Table 1, it is evident that there are considerable similarities between the agents involved in coherence.

the relationship between processor and client agents has similarities to that between manager agents and memory: in both cases, data suppliers are asked to supply data from a mechanism closer to main memory in the memory hierarchy.


For this reason, SCRS also proposes different reporting windows to better describe the risk landscape.

the Attack scenario window (shown in Fig.


These circuits will be introduced in Section 2.5.

adder trees constructed from carry-propagate adders (CPAs) such as ripple-carry or carry-select do not perform well at all.


The voltage VTHC is defined as the input signal in which the output changes state.

vTHC is the input value that causes the output to be VDD/2.


In particular, a simple admission control independent of user locations is su.cient in practice;  the number of active users is typically rather small in steady state.

the impact of opportunistic schedulers like PF that take advantage of fast fading is typically much smaller than one would expect with an assumed static user population.


By individually controlling the body bias voltage of all the elemental circuits in the FPGA tile, fabricated FPGA drastically reduces the static current by 92.6% in the maximum case and by 91.4% on average, while the FPGA tile area is increased by well-separation margins and programmable body bias circuits.

well-separation margins occupy 41% of the tile area.


With STBC, two or more signals can be transmitted simultaneously with multiple antennas and these signals can be easily separated at the receiving end if the receiver estimates the channel attenuation perfectly.

sTBC utilizes the spatial and temporal domain to achieve the diversity transmission of the signals.


joint statistical distributions of inter-/intra-die variations, are available.

these techniques do not lend themselves naturally to the capability of handling any uncertainty existing in the underlying statistical process models.


However, wire delays have become a dominant factor in determining the system performance, which is more evident in deep submicron (DSM) technologies.

the shrinking clock periods have made across-chip communication a performance bottleneck, where some global wires may have delays larger than the intended clock period.


This effect also favors the slip configurations that we present in the next sec- tion.

if the machine were more constrained on resources, the relative benefits of dynamic scheduling, or quasi-dynamic scheduling with slip, would likely be de- creased.


The di.erence is signi.cantly increased with the increase of the line numbers.

it is 3200 times faster than SPICE simulation for 5-coupled lines.


However, SVWNLQ (SVW on top of NLQ) still requires associative search logic in the store queue.

when a load executes, it still searches the SQ to .nd earlier stores that have already computed their addresses from which data may be read.


The method searches for the optimum BOL (Vdd, Vcs) repair corner that maximizes the EOL yield at desired EOL functional (Vdd, Vcs) corners.

it searches for the BOL (Vdd, Vcs) biasing whose fails cover most of the fails of typical functional corners at EOL.


hn Lemma 1: If the intersection of two mutually exclusive nodes hown and is non-empty under a condition Y, then the nodes in the nhnn intersection are implicants of node Y.

if (&&Y) FgnFgneFgg lSand (how&&Y) lS, then YlS, where lSis the set of common implications.


SpimVista is aimed at being used by undergraduate students, and the graphical interface has been designed addressed to ease the learning process.

the tool offers an intuitive and easy interface that allows the student to focus on particular and interesting events as the program instructions are executed step-by-step.


Due to the rising-transition-only property, delay variation tolerance in domino circuits is much easier to accomplish than that in static circuits.

directly applying the same method as [3] to domino circuits may have an unnecessarily large area.


Using a set of 60 properties, we have shown that the obtained generators are fast and relatively compact, which can be helpful in real design veri.cation .ows.

our tool can produce a library of reusable parameterized components (SPI, OCP etc.


Our simulations account for all performance and energy overheads incurred by our schemes.

the energy numbers we present include the energy spent in maintaining the idleness predictors (in the hardware-directed scheme) and the energy spent in maintaining the table-to-bank mappings (in the query-directed scheme), and in fetching and executing the bank turn-on/off instructions (in the query-directed scheme).


Elements that are separated from this graph cannot be reached by the traversal algorithm and, hence, are ignored.


On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis Saurabh N. Adya Igor L. Markov Paul G. Villarrubia University of Michigan University of Michigan IBM, Corporation EECS Department EECS Department 11501 Burnet Road Ann Arbor, MI 48109-2122 Ann Arbor, MI 48109-2122 Austin, TX 78758 sadya@eecs.umich.edu imarkov@eecs.umich.edu pgvillar@us.ibm.com ABSTRACT In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global.

.exible gate sizing, net buffering and detail placement require a certain amount of unused space in every region of the die.


2(b-c), for which traditional optimization reaches its limits while the proposed methodology can optimize further.

mIGs open the opportunity for ef.cient synthesis of datapath circuits, where majority logic is dominant.


Introduction Embedded consumer systems that perform advanced media processing typically contain one or more Systemson-Chip (SoCs) for processing video, audio and graphics.

video processing poses interesting challenges due to the large data sets that need to be processed, stored, and communicated, while satisfying real-time constraints.


Since picture-by-picture peak signal-to-noise-ratio (PSNR) cannot accurately reflect the impact of different frame rates on human vision system, we propose to utilize the mean opinion score (MOS) metric instead of PSNR metric for better VQ evaluation.

given the extraction parameter {t,q}, the empirical model for SVC in [9] can be adopted to quantitatively measure the VQ of the reconstructed video as (, ) Qq() uTCF t (1) VQt q () the MOS for picture quality Q(q) is written as 1 () 92.8 u(1 ) Qq (2) 0.34( Gq() s) 1 e where G(q) is the average peak signal-to-noise ratio (PSNR) at quality level q.


However, recent studies show that NoCs can draw a substantial percentage of a chip s power, by up to 10%~36% [8, 9, 28].

the static power of routers has become a significant contributor of power consumption, consisting of more than 35% and 43% of the total NoC power at 45nm and 32nm processes, respectively (more details in Section 2).


We assume that the wavelength budget is homogeneously spread across all optical channels.

2bit parallelism (the case of interest) allows for more than 52%average improvement and up to 61% for bodytrack application,while 4-bit parallelism reaches 68% average improvement witha peak of 80% for canneal.


Then, i will further calculate the set of nodes S0 (including j *)that will not collide with each other except ati.

j * .S0 and there is no other node except i in N such that it has distances of less than R to any two nodes in S0, where N is the set of neighbors.


In addition, the probability that the distance of an active user to the BS is between r and r+ dr is proportional to the actual load generated by these users, namely: d.(r) (1 - B) .

c(r) the density of active users is inversely proportional to their peak rate C(r) as in the absence of admission control (refer to §3.1).


T , Is0 in equation (10) can es sentially be assumed temperature independent [13].

it can be regarded as a technology parameter, independent of device parameters such as effective channel length, supply voltage, and temperature.


Based on this method an input with the real value of 0 = p = 1isconverted to 0 by the probability of (1 - p) and converted to 1 by the probability of p. Using constraints of form I and II in the relaxed mode improves the LP solver runtime signi.cantly, however, due to this random conversion from real to binary, the optimality of the solution is greatly reduced.

the solutions obtained by RLP are extremely sub-optimal.


Thus, by induction we have shown that IO(zi)= zi ' for all i s.t.


The DNS resolver maintains a mapping between client IP, domain names queried, and the server IP(s) included in the DNS response.

for each response, it stores the set of serverIP addresses returned for the fully quali.ed domain name (FQDN) queried, associating them to the clientIP that generated the query.


The source driver supplies the desired voltage level (called grayscale voltage) according to the pixel value.

ideally, the pixel value transmittance, t(X), is a linear function of the grayscale voltage v(X), which is in turn a linear function of the pixel value X.


ABB research showed that adjusting the body voltage is an effective method for 3.1 Thermally-Dependent Delay Modeling Delay constraints are imposed by setting the delay at each register input and at each primary output (PO) node to be less than Tclk , the clock period.

the delay at the output of gate k, dkO , is obtained by adding dk, the delay of gate k, to the maximum delay at gate k s inputs while considering all gates j in the fanin of k. + max ) dkO = dk (djO (1) jEF I(k) Logical effort provides a simpli.ed means of modeling gate delays.


The search process is driven by a cost function, shown below, that includes both physical and logical distance information: ACTFi = ODC(xj) DIST(i, j)= af(D(i, j)) + ßg(L(i, j)) j=1 In fact, module Mi is idle for all the conditions such that none of its inputs is observable to the environment.

when ACTFi = 1, the clock signal feeding module Mi can be disabled, as no useful computation is going to be performed by the logic in Mi.


fn+1 depends the most on (t) .n , and also takes the past history into consideration when (t) 0 <a< 1.


Therefore, to avoid any confusion, instead of referring to a wire as a req or ack, we will simply refer to it by the direction in which it carries information forward or backward and by the index of the stage associated with it.

as shown in Figure 3, all the forward .owing signals are named Fi and backward .owing signals Bi.


For robustness, the streaming interfaces use blocking .ow control by means of back pressure.

writing to a streaming targetport that is not ready to accept data (e.g.


Synthesis results are architectures of sized OTAs and capacitors with appropriate tolerances and some specific constraints such that the desired performance specifications are satisfied.

this technique has been shown to be able to minimize the L2 sensitivity of the target system that is supposed to be a vital performance metric.


This methodology aims at trimming samples no matter which sampling technique is used in MC analysis.

we do not improve the algorithms of LHS and LDS, but we keep their benefits and reduce their simulation time cost further.


Synchronous languages have a clean formal semantics.

the de.nition of control .ow predicates in [29] supports static runtime analysis.


, N. (18) In .nding an optimal solution, the solver can determine which wires should be pushed upwards or downwards.

the wires are partitioned to two groups automatically by setting the values ti, i = 1, .