In contrast, for the cases of 10% and 90% row hit rates, the error rates are as high as 42% and -50%, respectively.

sFDM can be very inaccurate although it is efficient.


Furthermore, note that our scheme allows the memory controller to utilize data locality at a row buffer due to the nature of bitwise XOR operations.

as shown in Figure 8, our remapping method uses a bitwise operation without shuf.ing address bit positions.


This means with increasing time, di.erent a sets tend to generate more and more diversi.ed e.ects on the circuit degradation.

several a sets might result in similar circuit delay degradation in a short time period.


F nodes are special operators in compiler transformations and are widely used in resolving conditional branches in a number of compilers, and used to postpone computation of control .ow to run time.

a F node is introduced in a basic block which has multiple predecessors; the values of variables in a F node for a speci.c execution are given by the speci.c block which actually precedes the node in that execution.


The method in [13] can reduce capture power for the UMC (Universal Multi-Casting) test compression architecture, which is a form similar to the Illinois Scan architecture.

these methods cannot be applied for IR-drop reduction in general broadcast-scan-based test compression, which usually uses a more complex compressor composed of such gates as XOR, MUX, invertors, etc.


3.1 Simulation methodology The above-mentioned four state-of-the-art MLSAsare evaluated in terms of power, delay stability using a conperature.

the reliability analysis of each design is studied using 50000-cycle Monte-Carlo simulations.


In KNN algorithm, we used euclid distance as an indicator represents the similarity between one data set pattern and another.

the smaller the euclid distance is, the more similar the data sets are.


As for SAs, we verified that the 48% of all possible SAs may result in the generation of a Pass, rather than a Fail, at the BIST structure output, with a detrimental effect on the microprocessor test quality and effectiveness.

these are the SA1 possibly affecting node oi (i= 1, ., 32) and noj (j= 1, ., 4) and the SA0 affecting node nak (k= 1, ., 8) (Fig.


For a given variable ordering, ROBDDs are canonical.

the ROBDDs of equivalent functions are identical.


Actually, addition of graphics may have made it easier for the subjects to focus on discrepancies between the audio and visual rendering quality.

some of our subjects speci.cally complained about having trouble associating voices with the pedestrians.


Because SAR algorithm has an open loop characteristic which means it cannot track the environmental variations, we used another strategy to make the system in a closed loop when the SAR control finished.

the control unit continues the tracking procedure by adding or subtracting C[5:0] by 1 at a time because keeping the circuit in close loop guarantees the clock generator is still locked to reference clock.


For both CWC and MLWC, we give a randomized 2O(log* n)approximation algorithm respectively, where log * n is the iterated logarithm of n with base 2.

log * n is the number of times the logarithm function must be iteratively applied to n before the result is less than or equal to 1.


4.4 Circuit-Level Evaluation In order to evaluate the impact of contact routing on design, we design a ring oscillator using a modi.ed 45 nm standard cell library as shown in Figure 9.

this ring oscillator consists of 47 fanout-1 stages of 4X inverter cells.5 We then repeat the design with standard cells that utilize contact-level routing.


Cluster feedback connections are also sparsely populated, and this may cause some problems during routing.

there may be too few switches to satisfy all possible feedback connection patterns, so feedback signals are also permitted to leave the cluster and re-enter through the cluster inputs.


Since the bits computed by PE(1, 1) affect only the bits of PE(2, 1) and PE(2, 2), the bits computed by PE(2, i) (i = 3, 4, · · · , m - 1) are all zeros and hence these PEs can be eliminated.

only PE(2, 1) and PE(2, 2) are necessary among the m - 1 rightmost PEs in the second row.


We now consider a more diverse range of workload types: we consider all possible two-benchmark workload mixes and determine the potential bene.t from heterogeneity; this is to study how sensitive a heterogeneous datacenter is with respect to its workload.

for each possible twobenchmarkworkload mix, we determine the cost reduction through heterogeneity relative to homogeneous datacenters, see Figure 4.


The last aspect adds code that prints the bit width of __asp_x at exit.

the estimated result is printed after the simulation ends.


The latency, however, is only a couple of cycles for the individual components, but due to the distributed nature of the interconnect, thebest-case round-trip forareadoperationfrom the ARM to the SRAM in Figure 2 (running at 200 MHz and the network at 500 MHz), is in the order of 30 processor cycles.

the logical and physical modularity comes at the price of increased latencies.


Accordingly, the maximum power point (MPP) of the ambient source can be 0.95 V considering the built-in hysteresis band of 100 mV.

the MPP tracker adjusts the center voltage VMPP of the hysteresis comparator to 0.95 V.  350F-Supercap.


After ATPG, however, if path A turns out to be un-sensitizable, then we are only left with path B and C fortesting; orif both A and C are un-sensitizable, we only have B left for testing.

the post-ATPG coverage is much reduced depending on sensitization results.


The sub-budgets should be divided into equal portions.

each PFA in a column consumes identical amount of energy.


( d, if io MAX wi(k)= wi(k-1)+ (2) -d, if io MIN, where wi(k)is the eviction weight of core i at the kth time interval, and MIN and MAX are the sets of minimum and maximumrankvalues,respectively,receivedby theL2 Managers.

eviction weights at the kth interval are computed using the rank values as well as the eviction weights used at the(k-1)th interval.


Given that the latency and size parameters of a DRAM cache are so widely different from traditional caches, and the technology constraints are disparate, we must be careful about the implicit optimizations that get incorporated in the architecture of the DRAM cache.

we point out that DRAM caches are much slower than traditional caches, so optimizations that exacerbate the already high hit latency may degrade overall performance even if they provide a marginal improvement in hit rate.


However, in practice it works well in typical use cases such as an architectural walk through or a tour through a virtual museum.

it was suf.cient for our purpose of evaluating the general applicability and user acceptance of these different collision handling techniques for group navigation.


If this is successful for all cubes, we have shown that from an overapproximation of the reachable states in frame fl we cannot reach any state outside this overapproximation in frame fl+1.


The lack of order in test vector application constitutes an aspect exploitable in test compression literature.

in combination with the sizable number of unspeci.ed bits in test cubes, especially prevalent in large SOCs, stitching the test vectors together in a bene.cial order promises to provide signi.cant reductions both in test vector application time and in test volume, a signi.cant issue by itself for today s costly ATEs, achieving these reductions essentially at no hardware cost.


For each state, we simulate the injection of a trapezoidal glitch in the input that can cause the output to switch.

for states 100 and 010, 0 to 1 glitches were injected in B and A, respectively.


When two or more notes are connected with a slur, the bow direction does not change between notes.

vb does not alternate, and the interior notes have kb and kv enabled.


From the performance comparison, it can be seen that our method has much higher precision than the other two.

77.6% of the extracted snippets are overlapped with the ground truths, our algorithm performs well on nearly 80% of music, while Logan s selection is 2.5 2 1.5 only 41.9%, only slightly better than the random method, which is 1 about 32%.


5.2 Local Memory As we have seen above, the organization of local memory can have a signi.cant e.ect on the performance of the coherence protocol changes we have proposed.

if the local memory must be snooped on every transaction, the organization must be able to provide negative search result information quickly.


CONCLUSIONS In this paper, we study the design issue of an energye.cient virtual memory system with .ash memory as the secondary storage.

we look at the subpaging technique and storage cache management.


3.1 Basic Building Blocks The basic idea behind our performance estimation is based on providing a network theoretic view of the system architecture.

packet streams and resource streams .ow through a network and thereby respectively change their arrival and service curves.


These critical nets performance requirements can be easily met using transmission lines in packaging layers.

significant performance improvements can be expected for key parameters such as global clock skew, clock power dissipation, simultaneous switching noise and signal integrity.


The sensors operate periodically at discrete time.

measurements D(t) are updated at time t0,t1,t2,... with tk+1 = tk + .. For convenience, we denote the measurements at time tk by Dk.


The work proposed in this paper is orthogonal with the majority of the schemes mentioned; most of the authors concentrate on the highlevel protocols, the topology and the interfaces that should be used in an efficient NoC while we propose an innovative way for the core interconnection network within such a framework.

the majority of the proposed NoC schemes can be applied on the top of our buffered-crossbar architecture.


To deal with memory dependencies, the scheduler uses the memory dependence pattern of the most recent execution of the frame.

an assumption is made that the same memory instructions that are were dependent last time will be dependent in the same way in the future (and likewise for independence).


ture can not only provide a framework for incorporating existing adaptive solutions, but can also enable novel adaptations and applications that can signi.cantly expand the scope and utility of the cellular infrastructure (Section 2).

we develop a meta-architectural model of cellular systems and show that emerging applications may not necessarily require restructuring the network and its components, but a change in the way information is observed, gathered and used.


(4) signals of multiplexers, we can determine which adder units are combined together as groups, operating as an individual sub-adder.

the problem of recon.guring GDA adder into a certain mode is just equivalent to the problem of combining adder units into certain sub-adders: the more e.ort we pay, the less accuracy loss we su.er from.


In contrast, this work proposes power efficiencies at a larger scale by leveraging statistical properties of concurrent resource usage across a collection of systems ( ensemble ).

we discuss an implementation of this approach at the blade enclosure level to monitor and manage the power across the individual blades in a chassis.


Graph rewriting is a very powerful technique, and several libraries are available to program graph rewriting systems.


It can be seen that for a given number of scan outputs, a Block Compactor can support a much larger number of scan chains than X-compact by using a sequential signature that requires a small number of memory elements.

block Compactors have the potential to achieve much higher compaction ratios than X-Compact.


DSN allows the user to specify an application using a high-level declarative language, Snlog, which is subsequently fed to a compiler which builds a runtime query processor that executes on each node.

snlog, is a modi.ed version of Datalog [20] that is able to specify certain physical properties such as where tuples are stored and sent.


We assume the delay of the gate as a interval with a lower and a upper bound value.

every gate s delay is now a triangular value (average, low, high), instead of a discrete value.


Enforcing De.nite Detection at Circuit Outputs: To establish de.nite detection of the fault according to equation (1) of section II, we need to constrain the solution space by limiting the detecting outputs to a single .xed one.

for all possible assignments to the X-sources, the fault effect must be observable at one particular output.


PROJECTION-BASED ANALYSIS We propose a projection-based analysis algorithm that is facilitated by exploring the underlying sparse structure of the leakage analysis problem.

we propose the following methodology, which includes: 1) a two-step iterative algorithm for quadratic leakage modeling; 2) a quadratic model compaction algorithm for leakage distribution estimation; and 3) an incremental analysis algorithm for locally updating the leakage distribution.


Figure 5 shows 1000 Monte-Carlo simulation results for the c3540 circuit.

self-compensated, dense + iso, and original + iso library options meet timing requirement at all randomly chosen defocus points the two optimization strategies suggested in Sections 4.2.1 and 4.2.2 demonstrate appreciably tighter distributions than the self-compensated cell-based approach.


While this will be possible only if the array includes local memory elements, or can access the system bus, this simple case is not so uncommon.

if the compiler is to perform software pipelining (including modulo scheduling) [11], all possible candidates are of this kind.


The CableCARD controller charges of the whole CableCARD operation on the session, resource, and application layers.

the MPEG TS descrambler should perform the decryption of multiple programs within about 200Mbps of Cable Receiver Multi-Stream CableCARD Pre-header MPEG TS Packet Figure 2.


It would probably be advisable to read the entire pmif.xml file into memory then interpret and insert parameters into appropriate internal data structures because of the ordering in the XML schema.

some transformations may require information from elements that have not been read yet.


Thus, Warp is at the other end of the spectrum of integration complexity as Capo.

to enhance our ability to do future research on Warp, we are willing to abandon our ad hoc database infrastructure and replace it completely with OA and OA Gear components at a native level.


A certain level of symmetry can be identified in these combinations.

we aim to exploit the dynamic reconfigurability of the CNT_DRC_7T cell to set the actual function of the cell to one which will give the same output as an XOR/XNOR for a given input combination.


Another key observation is that, due to the relatively small number of active users in steady state, the impact of opportunistic schedulers that take advantage of fast fading is much more limited than one would expect from the analysis of a static scenario with a .xed user population.

the cell capacity does not much di.er from that obtained with a simple round-robin scheduler, especially for large cells.


We generalize this idea by allowing the compiler .ner grain control over the individual ways.

on a cache access, the compiler decides the partitions or ways to be probed for the referenced data.


Introduction Chip-Multiprocessors (CMPs) present microarchitects with new challenges and opportunities.

because the primary means of communication between the individual processors is via shared-memory, the memory system is now a .rst-order design issue at the chip level instead of the system level.


Unfortunately, the relation E(4, 5) cannot be resolved as easily; no other pairwise relationship between modules 4 and 5 can be introduced without either violating some other non-overlap constraint, or extending the layout beyond the given .xed outline.

the edges corresponding to the relations in the set {L(4, 5), R(4, 5), A(4, 5), B(4, 5)} are in con.ict with the current constraint graphs, and hence we must perform some modi.cations before we can repair this particular violated constraint.


To make matters more complicated, there is recent submicron data showing that aging itself can be affected by process variation [20].

there is significant dependence of NBTI and PBTI on device geometry, e.g., channel length, which is variable as virtue of process also.


However, increasedmobility not only improves the drain current in the saturation regime of MOSFET operation, but it also increases the subthreshold leakage current.

short-channel MOSFET saturation drain current, ID,sat, has a sub-linear dependence on mobility, µ0, while the subthresh  2 1 0 Ion (normalized) Figure 1.


The paper also provides a methodology for estimating ME cell switching energy.

we show that this energy can be as low as 10aJ.


The objective of this paper is to propose a design that improves not only the logging overheads but also the recovery performance for DBMSs over MLC (and SLC) .ash memory, where the low reliability and the partial-programming constraints of the MLC .ash memory must be considered.

a logging mechanism with start, update and end log blocks are proposed to support e.cient transaction recovery in joint considerations of both wear-leveling and garbage collection over .ash memory.


We assume that the attacker wants its attack to be stealthy.

the attacker wants the failure detector to have a very small probability to detect its presence.


The DIC scheme makes an extra copy of recently generated Java code in the DIC cache, so the number of instruction misses can be reduced.

we .nd that the DIC cache can reduce almost all instruction cold misses.


The results also indicate that recovery is slower compared to weearout since the chip cannot be fully recovered with symmetric ACC stress.

aC stress is a partially self-healing proces s with a slow recovery rate.


The is achievable with the help of retiming technique.

to shorten the propagation delay on a particular path, we can move backward the critical path s receiving FF towards the path s starting point and/or move forward its sending FF towards the ending point (see Fig.


However, the power estimation provides information related to the density of accesses, which is not directly correlated with the hit rate.

java has a larger instruction cache hit density but a smaller hit rate.


Thus, consider the idea that designing an amplifier immune to electromagnetic interference would be sufficient to guarantee the immunity of the entire circuit of a voltage reference.

the amplifiers are designed to achieve a high power supply rejection ratio (PSRR) and low distortion, because it was considered the only or, at least, the main responsible of the overall voltage reference immunity degradation in the presence of interference of these works.


However, since the code fragment in Figure 2 does not exhibit any data dependence, the processors do not have to stick to the same tile processing order; that is, they do not have to process their data tiles in the same order.

they can bring (and process) their data tiles in such a way that whenever one processor needs a non-local array element (to perform some computation), the needed data can be found in some remote SPM.


For a signal to be latched, it needs to be stable during the setup time tsetup before the rising edge of the clock and hold time thold after the rising edge of the clock.

it needs to be stable inside interval [Tclk tsetup , Tclk + thold].


For an N-vertex tree T and an integer a = a0, T can be laid out into M(l(N),2t(T)+ a),where l(n) 26n is Ca -16a if n> Ca2 , a-2 otherwise.

t can be laid out into M(l(N),t(T)+ a) if T is binary.


It provides the opportunity to reevaluate this large-scale architecture, now with 50 TFLOPS of peak performance.

we evaluate the performance of peta-scale targeted applications from scientific fields including astrophysics, climate, combustion, fusion, and materials science.


we want to prove that IO(zi)= zi ' for all i s.t.


Then the constant 0 will be an interpolant of A and B under the cls refuted subspace.

proof: Since cls is a clause in A, we have: A -cls (1) By contraposition, we have: ¬cls -¬A (2) the projection of A in the ¬cls cofactor subspace will be null.


STRUCTURAL RESILIENCE TO FAULTS We investigate the impact of WSN topology structure with respect to node failure rate.

we are interested in the relation between the node density and the failure rate of the nodes themselves.


(8), if the eigenvalues of K exhibit some decay.

xc is closer to a low-rank matrix than X if the inputs1 exhibit some correlated behavior.


We have shown [7] that ANT technique reduces the drop in SNR over a noiseless system from 11dB to 2dB for a value of perr as high as 10-3 .

the ANT based system improves the SNR by 9dB when each .lter output bit is being .ipped at an average rate of once every 1000 samples independent of each other.


The computation of their parameters remains tractable and a remarkable corpus of techniques is available in this matter.

gaussian mixtures are conveniently amenable to incremental estimation of their parameters, as further data is made available for a given speaker; 3. they can lead to a tree structure, that will enable speeding up speaker matching, compared to exhaustive search.


The lower bounds in Section 4 and 5 clearly hold for the online version as well, but stronger lower bounds can be shown.

for reuse distance 2, using the techniques of [7], a lower bound of 19/9 can be obtained for the competitive ratio.


On the other hand, if the data of the current miss had not been accessed recently, the data will be loaded to a cache line in the target cache set and the least recently used (LRU) cache block in the same cache set will be deactivated.

the number of active ways remains the same.


Regarding per-sender wavelength for control packets, address of the target should be embedded in the packet to enable control data processing at the respective destination node.

each control packets is organized as follows.


An analogous approach can be taken with respect to efficiency vs. accuracy.

the default processing invoked by the tool assumes a simple data model, and this is overridden only if the data proves more complex.


The new methods start with a placement obtained from any existing placer, and improve CD accuracy through postprocessing optimizations.

the location and the orientation of each cell can be perturbed to achieve a lithography-friendly design.


Adifferent approachhasbeen consideredin[12],whereaprobabilistic framework based on Markov Random Fields (MRF) is proposed for designing noise-immune circuits.

the MRF frameworkused feedbackofthe satis.ability constraintsofagate s function to reinforce correct behavior.


One of the ways to allow recon.guration at this granularity is to decouple the pipeline stages from each other.

remove all direct point-to-point communication between the stages and replace them by a switch based interconnection network.


The algorithm starts with randomly choosing a small subset of samples of multiple people.

k randomly selected samples are used as input to our constructive iterative optimizer (Algorithm II).


We also include nonredundant candidates whose Q are decided by both T(v1)and T(v2)simultaneously.

for each candidate ai in A(v2), we want to .nd a candidate ßj in A(v1) such that Q(v1,ßj) =Q(v2,ai), and C(v1,ßj) is the minimum among all such ßj s. we want to .nd index j: j =min {k |ßk .A(v1),Q(v1,ßk) =Q(v2,ai)}.


In multimedia and DSP applications, the multiplication operations used in these applications useually have the special fixed-width property.

both input as well as output has same bit width.


Here, we have run simula- tions using an "oracle" predictor of when dead time starts in each cache line.

we note when a cache item has had its last suc- cessful hit, before the cache miss that begins the next generation.


In the example of Figure 1, we partition the STT-RAM cache based on write latency and set 21 clock cycles as the threshold to di.erentiate SAP from FAP.

for the cache lines that can be written within 21 cycles, they are grouped together as the FAP of the STT-RAM cache.


The .rst latch is transparent when f1 is high and opaque when f1 is low.

if f1 and data are both high, then transistors m1 and m2 will overpower inverter i2 if necessary to pull down node x1 which then brings node x1 high.


All caches maintain an exclusive policy in order to maximize the number of unique lines that can be stored on-chip.

no line can be contained in more than one cache at any time.


And the throughput gains for TU+dyn and RZ+dyn are 25% and 19% for the adder, respectively.

we manage to transform 70% (53%) of the frequency increase into real performance gain throughput.


are approximated by Taylor series expansion of a response surface model; while this approach is suitable for early design stages, the method in general is prone to errors and may not be accurate for predicting low/rare failure probabilities.

the performance metric Gaussian approximations may not replicate well the tail probabilities.


If so, ROM retroactively adjusts to the new conditions and takes corrective measures.

a mistake of an overly optimistic initial prediction is .xed at the end.


On the system level, our platform simulate neuron populations synchronously.

all computing engines synchronize at each time step.


There areat leastafew responses.Tobegin with,itis notalways the case that the constraints canbeexpressedina decidable theory.

timing constraints that contain non-linear inequalities cannot be decided (in this case, it so happens that our expression of the BMP constraints are linear).


LUT, multiplexor, buffer, inverter, pass transistor, con.guration memory bit) is designed and properly sized at the transistor level.

each has been designed at spice-level and is appropriately sized to a reasonable area-delay tradeoff [4].


Theorem 1: For two random variables (possibly correlated), Aand B, with arbitrary distributions, the following identity holds: P(A = B)= P(A = A&A = B)= P(A = max(A,B)).

(4) the probability that A exceeds B is the same as the probability that A exceeds max(A,B).


Fast and Accurate Transaction Level Models using Result Oriented Modeling Gunar Schirner and Rainer D ¨omer Center for Embedded Computer Systems University of California, Irvine, USA {hschirne,doemer}@uci.edu ABSTRACT E.cient communication modeling is a critical task in SoC design and exploration.

fast and accurate communication is needed to predict the performance of a system.


Not only did the paths share similar characteristics to one or more speedpaths, but also if we were to select potential speedpaths manually, after the root cause analysis these 13 paths would have been selected.

all the paths had either identical or very similar combination of active device types as one or more of the speedpaths.


According to Theorem 1, we can compute edge criticality as t = P(A = B)= P(A = max(A,B))= P(A = C), (5) where A is the edge slack, B is the complement edge slack, and C = max(A,B) is the chip slack, which is the max delay of all paths from the source to the sink or simply AT at the sink node.

the criticality of edge e is the probability that its edge slack dominates the chip slack.


With minimum dimensions and less infrastructures, sensory networks need to embed computing resources and wireless data communication at a minimum energy budget, maximizing its operating lifetime and minimizing environmental footprint.

vision is the sensing technology with the largest information density, which is required to be processed in real-time through high-performance computing platforms.


These two functions, Fb and Fc, must respect F = M aj(Fa, Fb, Fc) for all the possible input combinations.

for the input combinations such that F and Fa have different values, the functions Fb and Fc must assume the same logic of function X w.r.t.


Then we analyze the impact of WID variations and the number of cores per die on the optimal PG-device size and VDD.

both the GC and FI schemes will be examined since they impact performance and power efficiency of multi-core processors differently in the presence of WID variations.


In addition, based on the throughput rate of 400 M pixels/sec, Wang s design [4] re-designed and the proposed SPSTbased design respectively consume 10.96mW and 9.83mW.

the proposed design achieve about 10% power improvement when compared with Wang s design [4] re-designed, based on the same data throughput rate.


As shown in Figure 8a, tTAW has signi.cant impact on the memory-intensive applications.

sTREAM has 21.5% performance drop compared with larger tTAW.


Thus, for a state register, its output capacitance is often much larger than its internal capacitances.

for a state register, power is primarily consumed for charging and discharging the output capacitance.


The .rst peice of apriori information is that in Calamari every transmitter/receiver pair is also a receiver/transmitter pair.

there are two distance estimates for each pair of motes.


To summarize, in BCR, both Cvariant and Cdynamic are signi.cantly in.uenced by Nupdate ; however their correlations are different.

4the update means unique update in the case of register .le [10].


To check whether running IP-based security on lightweight hardware is feasible, we performed HIP measurements over WLAN with Nokia 770 acting as a mobile client, thus mainly being the initiator of a HIP association.

we measured data throughput, latency, and power consumption of the HIP base exchange and mobility update.


As each CLB input (other than LUT feedbacks) is driven by a W×Fcin:1 multiplexer, reducing the number of CLB inputs reduces the overall cost of the C Block, at the expense of some flexibility.

n independent K-input logic functions cannot be packed into a CLB due to I/O limitations, despite the fact that the CLB has sufficient LUT capacity.


A basic logic element (e.g., a Logic Element in Altera Stratix FPGAs or a Slice in Xilinx Virtex series FPGAs) contains a LUT as well as a flip-flop, so that the output of a logic gate (implemented in LUTs) can be configured as either an unregistered mode or a registered mode.

if a logic gate is connected to only one register, it can be implemented in the registered mode.


3.3 Advanced features and veri.cation The elasticity with anti-tokens can be enhanced with some advanced features.

the propagation of antitokens can be stopped (passive anti-tokens), thus saving area and energy to handle early evaluation.


The control bits generating algorithm is presented in Section V. }, at least one encoded cofactor of each pair is equal to ** {f ,f ¯ 3 or 5.

the theorem is true if we can prove thatno matrix X can yield a 3, 5, or both for all the three encoded x zz cofactor pairs at the same time.


Our LCP design allows the exception storage to contain unused space.

not all entries in the exception storage may store valid exceptions.


With this addition, Vout tends to drift back to 0V.

if Vout is increasing, it increases faster when it is far below 0V than when it is near or above 0V.


4.2 Floorplanning of Rectangular Blocks We apply and evaluate further optimization heuristics besides SA to provide a thorough evaluation of obtainable solution quality.

we leverage concepts for an evolutionary algorithm (EA) [29] and the Great Deluge algorithm (GDA) [30].


The signi.cant di.erences between MPICH-GF and M3 are as follows: M3 GF does not.


0.25, only when its signal probabilities being 0 and 1 are equal.

improving the transition probability for one signal net corresponds to making its signal probability be close to 0.5.


Different from the guard-banding approach employed in [1,16], where multiple models are required to make identical decisions, the guard band invoked here uses a single model.

testing is only terminated after the model predicts test termination for M successive failing patterns, where M is an integer that can be 0 (no guard banding), 1, 2, etc.


To thoroughly investigate the aforementioned performance im pact and interplay of SSD advanced commands, allocation strategy, and data granularity, in this paper, we carefully examine several internal behaviors rarely discussed in the literature, which may have potentially important impact on the performance and endurance of SSD.

we carry out in-depth evaluations of these fea tures and their interplay, obtaining the following main insights.


The following timing constraints should be satisfied for this implementation to work properly: First, due to the feedback loop it is necessary to guarantee that after each change in the inputs of the csc0 LUT, the circuit reaches a steady state before any other changes in its inputs are made.

the delay of the feedback loop must be less than the delay of environmental feedback circuitry.


In this paper, we statistically represent the prior knowledge as a probability density function (PDF) that is referred to as the prior distribution [19].

we model each late-stage model coefficient as a zero-mean Gaussian distribution: .


In case qk increases monotonically, i. e., the optimization result of a transition step is either equal or better than the result of the former ones, one can reuse these bounds.

if we have determined an optimization result qi in transition step i we can commit qi as a minimum bound for all following transition steps to the MaxSAT solver.


This paper extends ReSim [4], our previous work, to support the simulation of a design recon.guring both module logic and module state.

we consider designs that utilize the Con.guration Port (CP) to save and restore state (e.g., [6] [11]).


Moreover, we can also note that the possible P-circuit implementations of f differ in the distribution of the = d= points of I among the three sets f, f, fI .

each minterm in I can be associated to one of the following outputs of Rf: 001 if it belongs only to fI, that is, it has been kept = in I, and not added to f= and fd; = 101 if it has been added to fand it is kept in I; d = 011 if it has been added to fand it is kept in I; = d= 111 if it has been added to fand f, and it is kept in I; = 110 if it has been added to f= and fd, and it is removed from I.


Speci.cally, with the presence of feedback loop, the timing-wise transparent levelsensitive latches may cause timing random variables to be self-dependent.

a timing random variable will be dependent on a time variable with the same name, but instantiated in the previous iteration.


INTRODUCTION The design of reliable circuits is becoming increasingly challenging for scaled CMOS technologies.

nBTI is recognized as the primary parametric failure mechanism in modern ICs [1].


3 We need to show that the probability that the NLFSR output does not repeat within the composite m-sequence of the 3 LFSRs can be made asymptotically low.

we need to show that for two different clock cycles j and k in the composite m-sequence of jjj the 3 LFSRs, p(M(V1 ,V2 ,V )= M(V1 k ,V2 k ,Vk)) .0 for an appro 33 priately large n. To show this, we note that for the majority function computing the output of the ith bit of the NLFSR, the output will be the same across two clock cycles j and k if at least two of the sets {V1 j ,V1 k}, {V2 j ,Vk}, and {V3 j ,Vk} contain identical values.


Experimental results .rst demonstrate that reducing corners in power rings signi.cantly mitigates IR drop, and then show that the proposed algorithm can reduce the number of corners by 33% on average for the GSRC .oorplan benchmarks.

the total running time for the 16 GSRC benchmarks is less than one second on an AMD-64 machine with a 2.2 GHz CPU and 8 GB memory.


Memory Power Model: We use a modern memory subsystem that is capable of operating in multiple power modes.

our model follows the speci.cations for Rambus DRAM (RDRAM) [15].


The encrypted data of protected processes are exchanged between off-chip memory and secure cache in page-sized units.

the line size in the softwaremanaged cache is equal to the page size.


In comparison, the curves marked 1D give the same results with 1D allocation.

each STG node is allocated the entire height of the CLB array, and, as many contiguous columns as are needed to layout the circuit.


An ETP de.nes the different execution times of a program (or latencies of an instruction) and its associated probabilities.

the timing behaviour of a program/instruction can be de.ned by the pair of .


Alternatively, it could be used for routing two nets, both of e.ective width 2W , or one of e.ective width 3W and one of 1W .

using only tracks of 1W (and spacing of 1S), routing perhaps can be more .exible, and di.erent wiring patterns may be advantageous in di.erent scenarios.


We will focus on this problem and propose a machine learning based solution, while we leave the discussion of the .rst two problems in an extended version of this paper.

we propose different sets of features, and conduct extensive experiments on evaluating the features and choosing the best machine learning algorithms.


However, the code layout generated for C may perform badly for other con.gurations, though it is good for con.guration C. For example, for benchmark Ispell, 4k-1-way code layout is better than 4k-2-way code layout for 4k-1-way cache con.guration, but worse than 4k-2-way code layout for 4k-2-way cache con.guration.

there is no single code layout that performs better than other code layouts for all the con.gurations.


The performance numbers are collected by running the optimized program with a different input.

we use different inputs for training and evaluation run.


Moreover, the unification of assertions with design and verification code streamlines interaction to augment the power of assertions.

systemVerilog allows assertions to communicate information to the testbench and allows the testbench to react to the status of assertions without requiring a separate application programming interface (API) of any kind.


A MAX7000 macrocell uses product terms that can be ORed or XORed together to implement logic functions.

the APEX E ESB can be configured to implement up to 16-product term macrocells with 2 product terms each at one extreme, or 1 product term macrocell with 32 product terms at the other extreme.


The constraints are captured by functional input sequences of the design.

the peak switching activity in the circuit under the functional input sequences is used to bound the switching activity during on-chip test generation.


Different synthesis algorithms can be characterized by the restrictions they impose on this generic decomposition template to achieve various trade-offs between synthesis ef.ciency and resultant circuit quality.

we de.ne support-reducing decomposition by requiring the composition function h to depend on fewer variables than the original function f .


We .rst develop stochastic, nonstationary models for charge carrier traps in semiconductors, i.e., RTS noise, by bene.ting from the two decades of ion channel noise modeling and simulation work in neurobiology [32] and the extensive literature on modeling and simulation of stochastic chemical kinetics [43], [44].

we develop (i) a continuous-time, discrete-space, .ne-grained Markov chain model in Section II-B (previously known [8]), and (ii) a continuous-time, continuous-space, coarse-grained Langevin stochastic model (completely new) in Section II-C for a charge carrier trap, that are both fully nonstationary capturing the impact of arbitrary time-varying bias conditions.


10 shows that, in general, superblock-based code caching helps reduce I-cache misses, except for the threaded variation which suffers more I-cache misses due to the replicated dispatch code.

improved I-cache locality by superblock caching works to offset increased Icache pressure from chaining (as is implied by the dynamic instruction count increase).


6.1 Long-term performance optimization The optimization objective of subcontroller 1 is to maximize the minimal available energy ED(t) per day.

we would like to guarantee sustainable operation in a worst case sense.


For example, video codecs, which are increasingly being included in wireless devices like mobile phones, utilize large data bu.ers and signi.cantly su.er from cache thrashing [1].

in mobile phone systems, where power and area e.ciency are paramount, smaller, less-associative caches are typically chosen.


The resultant encoding efficiency is equal to 98.23%.

this logic is able to encode, on the average, 32 × 0.9823 = 31.43 gating signals (scan chains).


In such a system, the memory bandwidth from all DRAM devices is at least double of the bus bandwidth.

dRAM devices can operate at a much lower data rate and their combined bandwidth can still match the bus bandwidth.


n .. n is monotonic  To this end, we have to extend the basic Boolean operators ¬, ., and .to corresponding operators ¬e, .e, and .eon ..

the monotonicity is a strong requirement that predetermines most of the extensions: there is only one possible extension ¬efor the negation ¬.


The amount of delay to be inserted is forand Ii f mulated as the minimum and maximum variables Im i f M , respectively.

a delay element with delay values in the Ii f interval [Im i f , Ii f ], thus a delay uncertainty of Ui f = (M - Im i f ) is M formulated on each path.


UVM is for sure a step further from the point view of the universality of the simulation tool, however, it is not for sure a universal approach with respect to the design and veri.cation language.

the methodology is too language centered, while an ideal universal veri.cation methodology should be language independent: veri.cation is not a matter of syntax, but of semantics.


Section 4 describes the hardware algorithms and architectures that solve the maximum matching problem.

the tradeoff of hardware timing and area cost are considered.


One explanation of why pose-speci.c did not outperform pose-independent classi.ers could be the number of training samples, because, for k poses, each pose-speci.c classi.er was able to use only about 1/k of the training data that the all-pose classi.er had.

the number of training examples compensates for pose-speci.c difference in walking speed estimation.


In short, the need for having a deep knowledge in the way code is to be transformed, have lead us to develop an entire instruction level hardening infrastructure from scratch.

a hardening strategy based on assembler code.


K is selected (Line 4), the kernel matrix F is updated (Line 7) to represent the residual knob settings, so that the next selection would be picked among those under-represented by previously selected settings.

the algorithm tends to select knob settings that cannot be well represented by selected ones, i.e., to favor potentially hard-to-predict knob settings if not being selected as training examples.


If given full access to the network's resources, these infected users then represent a clear threat to the network in the form of a lurking Trojan horse, a worm, denial-of-service daemon, or a tunnel to an outside attacker or freeloader, Other local devices also make easy targets for further exploitation, and may in turn carry malicious code into other possibly more secure environments.

people may place their exploited machines on your network and behind your firewall, and by doing so expose your machines to crackers or malicious code.


It also needs a method to feed real-life user requests into the experimental environment.

real user requests need to be captured and recorded in a real data center and then need to be replayed in our experimental environment.


Under the noise model in (1), the change is not continuous and only occurs at t =0and t =pw .

equations (7) and (8) simplify to Iinv(,) 0= (9) V V 2 1 .I (0 t pw) .


As we decrease the TAM width, the non-TDM approach worsens considerably in terms of test time.

when one of the two buses is removed (all the cores are connected to the remaining bus), the test time almost doubles, thus offering no gain in multi-site ef.ciency.


Hence, we do not ulative execution support.

we assume that the NPU is based on a superscalar RISC architecture which is representative of many NPUs available in the market.


We are currently working on the synthesis of the control-intensive Although both flows use the same functional unit allocation application to the RDR architecture.

we are solution, MCAS uses 18% more LEs and 24% more registers than developing global scheduling and resource-sharing techniques to the conventional flow in order to support the RDR architecture.


According to our evaluation, the carpool lane sharing scheme increases the overall throughput signi.cantly because more frame buffers are available to a packet at each node.

any packet can occupy any frame buffer, except that the head frame buffers are reserved only for packets in the head frame.


Each Evaluate for Pi need to resolve NP convex optimization problems in serial, which NS is O( NP ).

comparing to the exhaustive approach, the complexity NS is restricted to K and S. we need to traverse every combination from speci.cation space in ZK×S for O(SK ) complexity.


This organization would thus require multiple accesses to the global memory.Therefore, it is important that the memory coalescing constraintfor a global memory access is satis.ed.

memoryaccesses should be performed in sizes equal to 32-bit, 64-bit, or128-bit values.


Adapting to Intermittent Faults in Multicore Systems PhilipM.Wells KoushikChakraborty GurindarS.Sohi ComputerSciencesDepartment University ofWisconsin,Madison {pwells,kchak, sohi}@cs.wisc.edu Abstract Future multicoreprocessors willbe more susceptibleto a varietyof hardware failures.

intermittent faults, caused in part bymanufacturing, thermal, and voltage variations, can causebursts of frequent faults that last from several cycles to several seconds or more.


Using this design for water metering with TEG devices has a key difference from the AC electricity metering application Monjolo was originally described with: saturation.

the temperature differential across the TEG device drops as heat transfers from one side to the other.


The number of times synthesis transforms are performed is increased several fold as a result albeit with a low success rate.

after an analysis many of these transforms are undone..


2.3 PID Logging Due to the competitive nature of process scheduling in the Linux kernel, the variance in statistical results from one run to the next is greater than one would .nd when running a stand alone application.

one could potentially see large di.erences in execution time if an infrequent process, such as a kernel daemon, should be scheduled in one experimental run but not in another.


We have presented simulation numbers showing the effectiveness of our technique.

our technique is able reduce the overall power consumption of the processor by 8.6% for a single-core processor.


4.4 Reference-based Detection In Section 4.1, we have seen conditions under which antiforensic operations can be detected.

a forged and an unforged audio signal can be distinguished if their narrowband characteristics are available.


when all the pairwise equalities between the arguments of two occurrences of an uninterpreted function are established and not vice versa.

if for instance in our running example of (3), we activate (f (x, z1) .f(y, z2)), we would not imply = (x .y) .


Exhaustive Scheduler One way to improve the scheduling decision of an FU for an operation is to consider the effects of the current decision on all future decisions, accounting for all of the interactions between dependent operations, resources, and bypass paths.

for each possible resource and time assignment for a given operation, the scheduler could look at possible resource and time assignments for future operations, taking into account bypass path availability, and choose the assignment that gives the shortest overall schedule length.


A key idea for solving the multicore bu.ering problem is to propagate the same bu.ering solutions among all instances.


A possible solution to this problem is to delay assignment of values by the test generator to parts of the generated stimuli, until these values are actually used in the design.

as long as the unde.ned value is copied or moved from place to another, there is no need to set its value.


The success of a DCE is measured in the number of extractions it makes divided by maximum possible extractions.

a 4-entry DCE captures 65% of the source correlated loads.


It will take the same amount of time for thedata element to reach the consumer no matter how the different FIFOs are sized as long as the total storage space is same and each FIFO at least has a capacity of 2.

the time taken by andata element in the queue to reach the consumer de pends only upon the total number of storage elements between theelement and the consumer and not on the distribution of the storage elements among different stages.


Pointers must be considered as references: references to memory elements, registers, wires or ports.

pointers can be used to allocate, read, write and deallocate data.


In the weight function, x1(v, r) is the size of MUXR(r) if v is assigned to r. This item tries to reduce the maximal MUX width.

x2(v, r) represents the increase of the width of MUXR(r) if v is assigned to r. x2(v, r) = 0 if the functional unit producing v already drove register r before this register binding iteration.


The above result has later been generalized to Markovmodulated G/GI/1 queues [19], and for short range dependent arrival processes [2].

when the arrival process is stationary and ergodic, but can otherwise be dependent, [2] provided a su.cient condition under which (1) still holds.


(14) Substituting (13) and (14) into (10) yields g-1 g-1 1 1 k k VT H(s) Uk,r Vr T (s-zQ)= Uk,r (s-zQ)r .

(15) k=0 k=0 we have computed an approximate low g-1 rank SVD for H(s)inwhich Ur(s)= .


We propose an FPGA based accelerator for High Frequency Trading that is able to decrease latency by an order of magnitude and increase the data rate by the same rate compared to software based CPU approaches.

we focus on the acceleration of FAST, the most commonly used protocol for distributing pricing information of stock and options over the network.


We have implemented two different versions of selective theory deduction: Forward deduction: .nding only implications in the form of (yj j - x : c).

let {xi j } be {x} to reduce the overhead.


p1 p2 p3 a1: Wx1 b1: Rx1 c1: Ry1 b2: Wy1 c2: Rx0 In the absence of barriers, P3:x=0 is permissible.

p3 is not guaranteed to see the write from P1 and the write from P2 in any particular order (despite the fact that the store from P2 can only happen after P2 has observed the store from P1).


4.2 Design Choice for Neural Networks Neural networks of one hidden layer and one output layer are used, because a neural network with two layers of appropriate units can approximate everybounded continuous function [4].

sigmoid units with output range [-1, 1] and linear units are respectively adopted for the hid- Figure 3: The spatialpositions of the road junctions and links used for analysis.


Measured data [5, 6] from commercial processors such as Intel s StrongARM and Hitachi s SH-3 indicates that as much as 17% on-chip power is consumed in the TLBs with an escalating trend.

in this paper, we analyze the access pattern of memory operations performed within a cycle and in successive cycles, and exploit the characteristics of the addresses for energy reduction opportunities we .nd that concurrent and consecutive memory operations demonstrate very high locality and are often synonymous accessing the same memory page.


On the other hand, in the execution scenario built by Algorithm 1, (k+1) ti s execution reaches a progression of prog= pnext by being executed for Qi time units, and with a cumulative preemption delay of total delay(k+1) = total delay(k) + delay= max total delay(k).

algorithm 1 manages to progress slower in ti s execution while suffering from a greater preemption delay.


Among other things, age is used to select among stores matching the same address.

if one or more stores match a load address we make use of store age to select the nearest, older store in program order.


In Figure 2(b), however, the nodes n1 and n2 areabletomove to other stable state.

to have a successful write, WL = WLcrit.


Otherwise, the sleepmode logic is removed.

the delay and power penalty due to the inserted gating logic is considered during the commitment phase.


Based on this observation, this paper proposes to use unused physical registers as duplicates for the actively used ones.

we investigate two different strategies: conservative and aggressive.


The value of sm should be optimized so that the probability distribution pdf(aL,m) correctly represents our prior knowledge.

by appropriately choosing the value of sm, the prior distribution pdf(aL,m) should take a large value (i.e., a high probability) at the location where the actual late-stage model coefficient aL,m occurs.


Due to those capacitances, the coupling capacitance is a smaller fraction of the total capacitance.

those capacitances which make a circuit slower contribute to stabilizing the path delay by reducing the impact of neighboring switching.


(7) the BTBM algorithm can be thought of as projecting L to F1 in the KL distance sense.


Since state changes cause delay and consume energy, h d fewer changes reduce state-transition overhead (and d ).

task scheduling can save power E h d dh yfP P P h dN5 }hTh 552}T5 h Device { T E8 T dd 2 2Thh 22 8 dd h { T5{ }6 66h d 5 2 {2 } TT T 5 Table 3: hardware parameters.


PRO POSED APPROACH Similarly to the previous methods also the proposed approach consists of two phases to write a row of a memristor array.

like the S-b-R method the proposed method writes all memristors that have to be set to 1 in the .rst phase.


3.7 SUEF Heuristic Note that the greedy scheme discussed in the preceding section attempts to reduce the processing speed for the selected tasks aggressively without considering overall energy ef.ciency.

to evaluate the ef.ciency of slack usage for each task, we de.ne the slack usage ef.ciency factor (SUEF) for task Tk running at speed f as: E0 k - Ek(f) SUEFk(f)= (14) sk(f) where Ek 0 and Ek(f)is the energy consumption of task Tk at fmax and f, respectively; and sk(f)is the total amount of slack needed (including the slack reserved for recovery) for task Tk to run at f. it is the ratio of the amount of energy saved to the total amount of slack needed when task Tk runs at a certain speed.


This method of encryption is used in place of a compression method when preparing the encrypted CBLOCK record, with uncomp-byte-count and comp-byte-count referring to the decrypted and encrypted byte-counts.

the PSE-CBLOCK format will be: '34' enc-type decrypt-byte-count encrypt-bytecount encrypted-bytes  Since CBLOCKs can be used at the cell level, at the top of a hierarchy, or at the level of individual polygons, encryption can occur at any of these levels as well.


The identi.ers of the blocks and its corresponding modules did not match.


Figure 2 illustrates these concepts by highlighting a program fragment containing three distinct control-.ow regions.

the region following the target is called the post.x region, and is assumed to su.er signi.cant instruction cache misses.


Obtaining a high layout density within a region become a problem when wide wires require a wide spacing.

if a wire of width nW needs a spacing of nS , the layout density of a design within a region would be negatively a.ected.


Note that we focus on AC line powered systems that strive to deliver maximum performance while operating under temperature constraints.

the purpose of this optimization problem is to maximize the system s power-performance-efficiency while constraining the probability that the peak temperature is greater than Tcrit to be less than a pre-defined probability value, Pcrit.


An intuitive migration scheme is to always move the data to the fastest subbank.

all 16 subbanks in a memory rank are sorted by their access latencies in ascending order from Bank0 to Bank-15.


Based on this, we propose a model which handles operations on sampled signals and on vectors.

the transformation between the different signal types receives attention.


The system provides reasonably accurate statistics that match our prior knowledge of what each of these programs are doing.

it was able to rapidly highlight a previous known performance bottleneck in the web crawler related to accessing robots.txt, a problem that had taken us several weeks to track down with standard tools.


This on-chip block holds each data block in turn, and when a data block is resident in it, all the 3 nodes (coming from the different nests) are scheduled one after another.

in this particular case, we achieve perfect data block reuse, i.e., even if we have more on-chip blocks, we could not achieve a better performance.


Note that the conventional kernel estimation requires 10× more simulation samples than BMF to achieve the same accuracy.

bMF achieves 10× runtime speedup over kernel estimation in this example.


We also aim our temperature-aware scheme to be able to dynamically adjust the trade-off between the aggressiveness of the power optimization mechanism and resulting temperature reduction at the expense of more storage for buffering the data and orchestrating the buffer-DRAM coordination.

throughout the execution of an application, power consumption will vary depending on the nature of the application and the workload, resulting in varying power densities and operating temperatures.


To begin with, an upper-bound and a lower-bound temperatures are set for each thermal pro.le.

bu.ers cannot be placed into a location with temperature higher than the upper-bound temperature or lower than the lower-bound temperature.


Maintaining Placement Quality We initially experimented with the above formulation and found that while it was successful at minimizing clock capacitance, it also moved logic blocks unnecessarily from their original placement locations.

we observed there to be multiple solutions to the ILP problem.


Then, the input space was reduced by a feature selection process based on the notion of Shannon Entropy4 .

let LN and LD be the set of keywords appearing as node labels and document words respectively.


The operations are different only in how the terminal vertices are processed.

when typically between 1 and 3, the cost is manageable.


All sound sources are then rendered in 5.1 or 7.1 surround sound.

for implementationon the XBOX360, Eden Games adopted a variant of the recursive variable budget technique describedabove.abudgetof8clusterswasusedateach recursionlevel.


By this, we mean the fraction of writes that would have reached memory without our technique in place.

if the program would normally have issued N writes, but with our technique in place, only K writes are issued, then we have squashed N-K writes.


Tables 2-5 compares the number of resulting move instructions on the di.erent out-of-SSA algorithms detailed in Table 1.

we illustrate here com- Experiments Sreedhar pinningCSSA pinningSP pinningABI pinningf out-of-pinned-SSA NaiveABI Coalescing Lf+C2 CTable Sf+C Lf,ABI+C Sf+LABI +CTable 3 LABI +C C Lf,ABI 4 SfTable LABI Table 1.


Using a list scheduler con.gured for each of our cluster con.gurations, we then build schedules for the trace.2 We use the term schedule here to denote a placement (at a cluster) and a slotting (into an issue slot) of each instruction in the trace.

our list scheduler performs both steering and instruction scheduling in a single pass.


The state evolution depends on both the CSI available at stage k and the corresponding control, uk .

the state xk = (qk , ck , lk ) evolves according to the following: .


Let us suppose that the k upper order statistics X , X ,K, X belong to the right tail of the distribution n-k +1:n n-k +2:n n:n (we discuss the appropriate selection of their number k in Section II-D).

let the (n - k) -th order statistic X n-k:n  constitute a high threshold u marking the beginning of the right tail.


Specifically, we implemented an idealized processor capable of issuing memory requests without ever stopping instruction execution, until a maximum number of outstanding misses is reached.

the idealized processor is capable of completely overlapping instruction execution with cache misses until a cache miss occurs that would exceed the maximum number of outstanding misses.


We combine two regions Ri and Rj if P(Ri .Rj |F)> .

p (Ri|F) | i .j = (7) a signi.cant number .


This implies two constraints on a parallel implementation: 1) It should not change the order in which processes are allowed to be executed.

the simulated time imposes an order on the execution of processes.


Vo, v.tprech = v.tc = 0 and v.teval = 0.

we assume the environment can produce tokens to the pipeline inputs whenever available and consume tokens from the pipeline outputs with a certain consumption delay.


Early Estimation of the Size of VHDL Projects William Fornaciari, Fabio Salice, Daniele Paolo Scarpazza, Politecnico di Milano -DEI Piazza Leonardo da Vinci, 32, Milano, Italy {fornacia, salice, scarpazz}@elet.polimi.it ABSTRACT The analysis of the amount of human resources required to complete a project is felt as a critical issue in any company of the electronics industry.

early estimating the effort involved in a development process is a key requirement for any cost-driven system-level design decision.


Since the row has Xz = * and X5 = *, the crosspoints of Xa and X5 are not connected (i.e., not marked) in the AND-plane.

the input which is *, will not be in- volved in the AND gate operation, thus will not be connected in the AND-plane.


The GFE, on the other hand, has no speci.c functionality upon bootstrap but to accept instructions from the CE for de.ning its functionalities.

the GFE s functionality is programmed from scratchby theCE; thus theCEdecideshow theGFE should behave.


show that these codes have a performance very close to ideal, i.e., the failure probability of the code is such that if N is only slightly more than K, the code can recover the source block with a given probability.

for K > 200 the small inef.ciency of the Raptor code can quite well be modeled by the following equation, 1 if m < K, Pf (m, K) = 0.85 ×0.567m-K if m =K, whereby Pf (m, K) denotes the failure probability of the code with K source symbols if m symbols have been received.


More in detail, Figure 5 shows the approximate Pareto curves for the two accelerators, found by using the proposed methodology, compared to the exact Pareto curves 2 .

figures 5(a) and 5(b) present the results for the 2D-IDCT and YUV2RGBA obtained respectively after 154 and 263 evaluations.


We chose the best con.guration that presents higher PV N without loosing too much SP EC.

the setup selected for the Decoupled Counters con.dence estimator uses a 16Kentry table with two 4-bit saturated counters for both taken and not taken branches.


Let ªº «» denotes the upper round operator.

if the result inside the round operator in (1) is not an integer, it is necessary to add a number of zero bits to binary input data.


Thereafter, the regression functions replace circuit simulation.

a point in the space of input parameters (e.g.


The con.guration setting is based on results of the Verilog implementation.

the multicore CPU has multiple con.gurations with different instruction cache sizes.


Acknowledgements We would like to thank a number of people who helped us realize DCA under very trying circumstances.

we would like to acknowledge the contributions and support from Jeff Gilbert, Jack Doweck, Julius Mandelblat, Suresh Chittor, Siva Radhakrishnan, Don Newell, Ravi Iyer, Luke Chang, Linden Cornett, Scott Tetrick, Ittai Anati and Thom Sawicki.


By looking at which benchmarks were present in which workloads, and how these workloads fared in terms of predictions, we were able to determine that some applications are more dif.cult to predict.

workloads including the COREMARK and VITERBI benchmarks fared badly in these predictions, as did workloads with a small number of benchmarks.


Consequently, the internal logic layout and the routing of a macro will be preserved by the low level tools.

as macros can be arranged following a don t touch policy.


However, as aforementioned in Section III-A, the MTJ switching is probabilistic process under thermal .uctuations.

the STT-RAM write error rate PW F is the probability that the MTJ switching time t is longer than the write pulse width TW , or: PW F = aßP (tth0 > TW ) + (1 - a)(1 - ß)P (tth1 > TW ) (5) Here, a is the probability of a cell storing 1 , ß is the probability that a cell will be written to 0 .


5, a validity proof enables a client to determine the validity of the output of the read or increment protocol, and to detect any malicious or erroneous behavior by the VCM in the past.

for each of the past increments by any of a client s devices, the client can check whether the increment was based on a retrieved counter value (received from the virtual counter manager during one of its protocols) that is equal to the current counter value just prior to the increment.


As mentioned earlier, to go from active mode to the sleep mode, instead of simply turning off the sleep transistors, we do charge recycling between CG and CP as soon as the circuit enters the sleep mode.

we close switch M at t=ts0 which is the time when we turn off sleep transistors.


Statistical techniques with raw metrics alone would not provide this perspective immediately.

the optimizations to one of the representatives in this group will most likely propagate to its peers in the same cluster.


In order to produce gavage fluids that reflect realistic product-use exposures to an edible sensor, physiologic extraction vehicles were employed.

test items were extracted with simulated gastrointestinal fluids, with extraction time in each fluid reflecting transit times through these gut compartments in humans.


This ef.ciencyenables, for the .rst time, a comprehensiveassessment of potential bene.ts from high temporal and comprehensive spatial adaptivity.

the following summarizes the contributions of this work: 1.


As the CPL-based de 2 sign is a class of static pass-transistor logic, it inherits the design problems that are specific to that circuit class.

as we have chains of nMOS transistors in the nMOS networks, after a careful study of the situation additional intermediate swing restoration may be needed (see the arrows in Figure 8 for their possible placement, after 4-transistor paths).


For example, in addition to running STA at signo., timing runs are usually performed after logic synthesis and before place and route to help identify timing violations early in the .ow.

sTA is heavily employed during circuit optimization, where circuit timing and/or power are .xed by iteratively introducing changes and running STA until satisfactory results are achieved.


We need a very simple, lightweight mechanism which can be inserted inside the warping optimization loop.

we want wirelength calculations to at least roughly reflect the fact that depositing gates on top of macrocells likely has a wirelength impact -- the extra length needed to move those gates off the cell.


V (f )must be executed for each packet of stream f while respecting the precedence relations in E(f ).

the tasks V (f )must be executed by the packet processor for each packet in stream f .


This can be attributed to the fact that the impacts of TOX and VTH variation on bitline delay are independent, as discussed in section 3.

the TOX variation impacts only the first of the two Monte Carlo runs while VTH affects the second run only so the fact that the two Monte Carlo runs use different variation data does not affect the final results.


Finally, our evaluation is performed using the projected 0.10um technology in ITRS 2001 [ITRS01] and the evaluation results are especially useful to guide the design of power-efficient FPGAs in the future technology generations.

our results show that leakage power emerges as a major source of power consumption in future FPGAs.


Figure 2 (d) and (h) illustrate the third and the fourth classes whose applications require very few SLLC resources.

milc is a streaming application due to its high miss rate regardless of the amount of allocated SLLC capacity, while crafty is CPU-bound and can yield very high hit rates given a small amount of allocated SLLC capacity.


Indeed, the results appear to be asymptotically approaching the constant factor slowdown of guided simulation.


The handshaking protocol between stages follows similar rules to PS0 (see Section 2), but with added explicit synchronization to ensure more robust operation.

a stage in the precharge phase cannot enter precharge-release until its precharge operation is complete (checked by the output CD) and its previous data inputs have been reset (checked by the input CD).


We believe that there are signi.cant speedups that can be integrated into this stage to achieve runtimes comparable to that of Stages 1, 3, and 4.

the wavefront expansion is currently stored as a linked list; using a priority queue should result in signi.cant savings.


we develop a general circuit analysis framework to incorporate the NBTI e.ect.


WALKING PADS WP is based on the hypothesis that, when all pads are at their locally noise-balanced positions, with equal voltage noise along wires in two opposite directions from each pad, global voltage noise will be minimized.

if we move a noise-balanced pad in any direction, it will cause more noise in the opposite direction.


Their schemes can lead to negative net energy saving and signi.cant extra area overhead.

the scheme in [7] can yield negative energy saving if clock gating signals .ip frequently.


commitment succeeds at step 3, then it is called fully committed.

whatever candidates and enable logic identified at RTL is fully committed to save power without violating timing constraints.


Also from the .gure, we observe more and more input a sets tend to generate bigger timing degradation.

more and more a sets appear in the right part (bigger timing degradation) of the .gure.


We size our buffets in direct Woportion to the length of this tile.

if the tile length has doubled, then we double the size of the routing buffers.


To achieve an accurate simulation, we have added the energy overhead required for this module.

we augment the read/write energy to account for the fact that we read/write 39 bits instead of 32.


The number of unspeci.ed entries in the truth table are 43 3 (2- 2) · 4 + 2 · 2= 48.

48 of the 64 entries in the truth table are don t cares.


We now describe our heuristics 1 - xi otherwise.

some variables in x are replaced by their for selection of these matrices.


The results show that the proposed approach can design e.cient memory subsystems for component-based accelerators.

it can deal with di.erent requirements of the processes in terms of read and write interfaces and can update the memory subsystem accordingly.


Reachability in a graph is bounded by the number of vertices n = ]V].

in the worst case a DGP must propagate a signal along at most n edges serially.


20) () k Experiments show that the expression (20) is consistent with the general concept of timing jitter.

(20) is equivalent to the expression (2) in the case of dominant contribution of phase noise: y^t () « yt(tk) (eq.


It is shown that we can increase the maximum clock by up toafactorof 2X, and reduce the total energy to as low as 51.94%.

the total energy can be reduced by up to 48.06%.


Indeed, with the safe-load mechanism, the number of false replays is reduced by an average of 52% and as high as 97% in integer applications.

without safe loads, the number of replays will double.


Leakage reduction techniques have been widely researched for application processors used in mobile phones, and their standby power is very small (e.g., the leakage current is only 11µA in ultra standby mode [8]).

the more leakage reduction such processor cores achieve, the more impact the leakage power of on-chip routers will give; therefore leakage reduction techniques are essential for on-chip routers as well as processing cores in order to reduce the standby power of the chip.


Another way to deal with this problem is to assign a high cost to the misclassi.cation of the minority class and a low cost to the misclassi.cation of the majority class while trying to maximize the overall accuracy.

it is desirable to have a metric that gives high prediction accuracy over the minority class, while maintaining reasonable accuracy for the majority class.


There are placement blockages in the layout while no wiring blockage exists.

no buffer/inverter can be placed on top of any blockage but routing can be done over the blockages.


In comparison to most of the previous SPM related work, our approach is based on the recomputation of off-chip data, needed by the current computation, by using the data that currently resides in on-chip SPMs, instead of fetching it from off-chip memory, if doing so is bene.cial in terms of performance.

we substitute recomputation for off-chip data access.


· For every duplicated exclusion cell (represented by 0), all the column copies have to be mapped without mismatches.


Using this technique, to be able to parse any SystemC program (requirement 1), one must be able to compute the state of any program at the end of the execution of the constructors knowing their bodies.

the tool must contain a re-implementation of a C++ interpreter (which does not satisfy requirement 3).


solution and perform local adjustment to make its wirelength increase fall into the requirement.

our local adjustment is an iterative approach and it gradually turns the cell placement to be closer and closer to the original placement until the wirelength increase satis.es the constraint.


Our main goal is to verify whether M0 behaves exactly as M1.This means that for all possible input sequences, M0 and M1 produce the same sequences of output values and eventually, when the respective reset states are re-visited, they are visited with the same storage element values.

for every computation from the reset state back to itself of one FSMD, there exists an equivalent computation from the reset state back to itself in the other FSMD and vice-versa.


While most industrial compact models like BSIMs are written in C, Verilog-A, nevertheless, is chosen in this work due to its many advantages over C in compact modeling [5].

verilog-A enables the model to be developed quickly and reliably.


250 200  number of instances 150 100 50  5.3 Min-Cost Solution Min-cost solutions are from the formulation that minimizes the total bu.er cost subject to timing constraints.

a min-cost solution should have non-negative slack.


In this paper, we face the previously described problems by presenting an automatic High Level Synthesis (HLS) .ow that, given a processing algorithm, generates a set of hardware implementations that are Pareto-optimal with respect to cost and performance (measured as throughput).

the .ow: 1) takes a high level description (C language) of the algorithm as input, 2) systematically analyses data dependencies between elements of subsequent iterations, 3) generates synthesizable VHDL descriptions of all the cones that are best suited to custom .ne-grained programmable devices (e.g., FPGAs), 4) ef.ciently explores the cone architecture solution space with a minimum number of synthesis runs.


3.4 The Case of Multiple Tasks The problem gains new dimensions when we consider a realtime application consisting of multiple tasks.

we need to allocate available slack to multiple tasks, possibly in different amounts, to maximize the energy savings.


Generally, the number of inputs to a complex cluster is less than the total number of LUT inputs contained in the cluster.

a cluster of four 4-input LUTs has less than 16 inputs.


Also, it can be observed that some applications are particularly susceptible to poor power performance with the more aggressive con.gurations.

we found .t and radix to be particularly susceptible, mainly due to the fact that these algorithms have close to the same number of writes as reads.


The measurement results (i.e., control vectors) serve as calibration values for given Vdd.

a mapping relationship between control vector C and supply voltage Vdd is established.


The di.erence between our algorithm and traditional algorithm is that per-length wire capacitance is not a constant, but varyingwith the change of its position and its surrounding pattern.

c in equation (1) and (2) is related to the position of the wire and surrounding density of the wire.


The set of equivalence classes of is .nite, as it only depends on the relative positions of elements contained in both sets.

the index of is independent of the number of memory blocks.


We have shown that some results for planar Steiner tree formulations do not hold for our routing model.

the ratio of minimum spanning tree to Steiner minimal tree cost is 2:1, and not 1.5:1.


The discrete state =0, transitions are labeled so the transitions occur in sequential order.

the system is initialized in q0, and proceeds to q1, q2, and eventually to qR.


Coverage metrics can not only measure how well a design is verified objectively but also help improve the quality of verification patterns.

they are capable of guiding either direct (deterministic) or random patterns to target those unverified design corners.


So far, we have not found benchmark circuits thatbene.tfrom both clockgating and clock spine reduction cumulatively.

while a circuit may bene.t from gating orspine reduction,wehaveyetto.nd circuitswherewe conclusively observeadditivegains.


OUR APPROACH As mentioned previously, LFSRs have some key weaknesses if they are used in the context of cryptographic key generation.

the LFSR polynomial can be discovered in 2n cycles, where n is the order of the LFSR polynomial.


To the best of our knowledge there are no other works in the literature about CLUE results and experimentation.

this work represents a .rst attempt of combining CLUE mechanisms with the upcoming web real time communication technologies.


In this paper we present techniques for the transformation of behaviors of selected hardware blocks into equivalent software implementations.

we describe SOFTENIT, a methodology for softening of SoC hardware, that takes as input, a partitioned and mapped system description, and generates a modi.ed system architecture in which the fraction of system functionality implemented using embedded software is signi.cantly boosted.


Static test set compaction reduces the size of the test set by removing any unnecessary vectors while retaining the useful ones.

static compaction .lters unwanted noise from the derived test sequence, leaving a cleaner signal (narrower spectrum) to analyze.


= The product Zi, j(t)= Vi(t) ·Vj(t) of two orthogonal basis noise bits is orthogonal to Vk(t) (k = 1, 2, ··· , M).

this property was used [3] to realize a logic hyperspace.(Zi, j(t),Vk(t)) =0 DEFINITION 3.


The latter prevents the application of abstraction techniques e.g., localisation [12].

verifying liveness of communication fabrics is a very hard problem [3].


5 7 9 11 13 15 17 19 21 LAB:Medium Memory Block In the initial version of LUT RAM, the focus was entirely on low cost, and consequently as much functionality as reasonably possible was left in soft logic.

the Stratix III device included 2 flip-flops per ALM, or 20 per LAB, which was just sufficient for the write data registers.


Highly-associative caches are very common in embedded processors due to their relatively lower miss rates.

a 16 KB 32-way set-associative level 1 instruction cache is studied.


Each output NW in the plane can be programmed to perform the or of its set of inputs.

there is a low resistance path between the inputs and the output NW only where the crosspoints are programmed into the on position.


4.5 Hardware Output Control DataSafe hardware checks to see whether copying the data to another memory location or output device is allowed, or whether writing to memory locations within the SDC is allowed, according to the hardware tags.

hardware checks if a memory location to be written to is a memory-mapped output device, and enforces output control according to the tag of the word being written.


Proactive-SET request has lower priority comparing to normal read and write, and is sent only when a WoM-encoded line has .ag 00 .

if the .ag is 11 , the request is not sent as the corresponding memory line can be written another time before proactive-SET.


Our experiments use a technology setup based on the ISPD 2009 clock synthesis contest [16].

the device and interconnect models are based on the 45nm Predictive Technology Models (PTM) [1].


To implement this approach we calculated a pseudo area for clusters that makes the perimeter-degree of the clusters uniform.

cluster with a larger perimeter-degree gets larger pseudo area when compared with a cluster with a lower perimeter-degree.


The reduced UR path set contains paths that are critical in SVM learning for deriving its statistical learned model.

other paths do not provide useful statistical information.


Therefore, fast and accurate estimation of error rates resulting from transient faults in logic circuits is crucial for identifying the features needed for future reliable circuits.

these models can be used to reduce the cost of applying various techniques for error hardening, detection and correction.


INTRODUCTION On shared memory multiprocessor systems, synchronization is one of the central design issues.

lock synchronization and the proper reading/writing of lock variables are essential in order to guarantee mutual exclusion (orderly accesses to shared data structures in memory) among Processing Elements (PEs) such as processors.


Consequently, key tendencies can be efficiently identified.

the goal of our work is to answer the following questions: How to define the complexity of program dynamics?


With such a separate design methodology, the architecture of the target hardware in general does not re.ect the computation granularity and the communication structure of a particular application.

the number of processor cores and the interconnection among the cores do not match the number of concurrent computation tasks and the communication paths among these tasks.


The goal of this work is to architect an SCM-based memory to play the dual roles at the same time.


Because the virtual ground line is shared among logic gates, the voltage of the virtual ground fluctuates depending on the discharge pattern of the gates.

the circuit speed varies depending on input vectors.


Although several patterns might be helpful in establishing and evaluating security in WSNs they were not widely considered with this focus and consequently do not cover relevant aspects yet.

retaining security with the possibility of compromised nodes is not included [16].


Notice that the zero crossing points of the each waveform (in time scale) occur roughly at the same time.

roughly zero phase is encountered across several probing points on the ring.


Previously proposed devices have several types of sensors to extract bene.cial real information such as temperature, proximity, acceleration, light, pressure, and magnetism [3][4][5].

acceleration is one of the most signi.cant types of information for recognizing dynamic motions, both of humans and objects, in real time.


Architectural design decisions that reshape the slack distribution by devoting less area to regular structures or moving regular structures o. the critical path can enable more overscaling and increase energy e.ciency for timing speculative processors.

additional overscaling enabled by architectures with smaller regular structures can outweigh the energy bene.ts of regularity when designing a resilience-aware architecture.


Beside the TFCI based Transport Format detection the 3GPP standard de.nes the requirement to blindly detect the Transport Format in use.

using only the received block of data which is convolutional-encoded to estimate the correct size of that Transport Block.


The signal Mj0 is 1 iff the unit U0 has to be shifted by j positions in order to be connected to the first fault-free unit.

when FBI0 = FBI1 = = FBIj-1 = 1 and FBIj = 0.


Since set-associative caches can avoid the thrashing problem of direct-mapped caches, MSA exploits this idea and activates more ways only when it can be identi.ed the situation has occurred that a piece of code repeatedly alternates between accessing different locations that map to the same cache set [20].

mSA increases the number of active ways of a cache block only if the data of current miss has be accessed before within the time window.


Due to the high read performance of .ash memory, read requests are not cached by the proposed design.

when a read miss is served directly by .ash memory, the cache will not retain a copy of the accessed .ash page.


Moreover, considering the relationship between soft error rates, critical charge, supply voltage and the number of particles in the cosmic rays [14, 19, 30], we proposed an exponential fault rate d(1-f) model: g(f)= .0101-fmin where the exponent d (> 0)is a constant, indicating the sensitivity of fault rates to DVFS.

reducing the supply voltage and frequency for energy savings results in exponentially increased fault rates.


Unfortunately, the above approach cannot directly handle certi.cation of designs from other domains that involve considerably less structure.

one key requirement to achieve compositionality in SEC is the availability of equivalent internal operations or modules between the abstract CCDFG and the corresponding RTL, which are then used as cutpoints.


One can also observe that the crash latency distribution has a long tail and there are a non-negligible percentage of cases when the crash latency exceeds hundreds of millions of CPU cycles.

the processor can execute millions (or even billions) of instructions in presence of an active error before it .nally crashes.


From this observation, we improve the accuracy of the energy detection by factoring an additional parameter, i.e., bandwidth, called EBSS.

both the energy level and bandwidth of the received signal are taken into account while making a decision on a channel s status.


Control Applications Each control application is responsible for controlling a plant or dynamic system.

we consider linear control applications where the dynamic behavior is modeled by a set of differential equations, x.


All control dependencies within a frame are removed, ensuring that all instructions within the frame are mutually control independent.

either all in- structions in a frame commit their results, or none of them do.


Second, strong leakage faults below a certain threshold, RL 1 kO, prevent the circuit from oscillating.


In order to store constraints in our algorithm, a hash table is used.

parameter names are treated as hash keys, and minimal and maximal values are stored as hash data for the corresponding keys.


4.4 VAWOM s Process Variation-Aware Scheme The move to deep submicron process technologies have caused process variations to become a major challenge that must be dealt with during design of chip multiprocessors.

device parameters such as threshold voltage, resistance per unit length, gate length and width suffer large variation.


Within the network topology, there is a certain fraction of sensor nodes that act as so called cluster heads.

these nodes administrate local clusters of sensors, aggregate data from the neighbors and transmit the data across other cluster heads towards the data sink [11].


Suppose net yj in logic block D has fanout branches connected to at least a node that is not in D. In this case, register R2 should be loaded with new values in each cycle; otherwise, yj may have incorrect value on it.

net yj and those nets in its input cone do not belong to DCNS(p).


ID badges are common in the workplace and they offer some interesting possibilities from an interaction perspective.

we propose embedding a display in the badge to facilitate the presentation of nuggets of information in a manner which is very accessible to the wearer.


Design space of the dual-element memory cell is studied and it shows that the trade-o.s among the energy, speed, and distingushiablility should be explored for di.erent design objectives.

we show that under the energy-driven optimization, the proposed dual-element memory achieves the same programming speed and distinguishability as conventional single-element memory but the energy consumption can be reduced by up to 80%.


However, this constraint of unate clause does not work well for our static MIS because the static MIS is pre-computed before any variable assignment.

an initially non-unate clause may become an unresolved unate clause during the search when all its negative literals are assigned to be false.


In general, a fork is not isochronic iff all of its branches are acknowledged on positive and negative edges.

the fork being isochronic means that some transitions on one of the branches of the fork are not acknowledged by any other transition in system.


we could not simply perform the evaluation using a single stereo tiled-screen system.

we were also interested in the variation of these parameters outside the range of currently available LCD screens (e.g., make the bezels extremely small).


To reduce the complexity, we make a reasonable approximation by attaching all current sources to the intersection nodes of the vertical and horizontal power lines.

every P/G pin is connected to its nearest node with a power strap, and the length of the strap is the Manhattan distance between the P/G pin and the node.


The experimental setup and workload is speci.c for embedded systems.

we picked four embedded devices (details later in the section), and used some test scenarios to collect traces.


Note that, to avoid being trapped in local optimal points, we use e-greedy to select the coarse grid lines for p × q partitioning.

we set up a probability parameter e (e.g., e = 10%), and hence we have the probability of e to select a grid line randomly, instead of the one with largest metric de.ned in Eq.


While previous work has proposed new security mechanisms for control systems, few of them have explored new and fundamentally different research problems for securing control systems when compared to securing traditional information technology (IT) systems.

the sophistication of new malware attacking control systems malware including zero-days attacks, rootkits created for control systems, and software signed by trusted certi.cate authorities has shown that it is very dif.cult to prevent and detect these attacks based solely on IT system information.


Unfortunately, these bene.ts come at the cost of a considerable complexity.

the exponential complexity of the optimal soft-input soft-output (SISO) detector has led to the investigation of numerous suboptimal detectors with lower complexity.


(2) When valid pages of the two blocks are written back to the caching bu.er (with new primary and over.ow blocks), they are written back in an LRU fashion.

valid pages in the over.ow block are written back to the bu.er earlier than those in the primary block, and valid pages in the over.ow block are written back to the bu.er from the bottom to the top of the over.ow block.


Then we isolate the bene.ts of each feature of the recursive schedule.

we answer the following questions: (1) How much does locality-aware scheduling matter?


Many scientists agree with the statement that the essence of ecology is the study of interactions among species in their native habitats [18].

animal communities in tropical forests have extremely complex interactions involving vast numbers of species [19].


(15) i=1 I(.j) × w(.j , µ , s) It is obvious that the calculation of si depends on the optimization result µ from (14).

the potential error from the optimization of µ can propagate into the computation of si and lead to completely misleading results, which is especially undesired because the performance of importance sampling is highly sensitive to the sampling distribution.


As can be seen in Figure 6, RALM NSEL reduces the energy consumption by 63.7% and 22.6% on average over BASELINE and DECAY, respectively.

for MPGdecoder and MPGencoder, RALM NSEL can reduce the energy consumptionbyupto 19.3%and 44.2%overDECAY while the SPLASH2benchmarks show smaller reduction.


The GCM is a graphical speci.cation language that was developed to to aid designers in creating SBML models of genetic circuits by providing a method of describing them at a higher level of abstraction.

in a GCM, only important species and their in.uence upon each other are represented which greatly reduces the model size.


In many similar systems, we can suppose: We can forecast the future status based on the current status and can ignore the past status.

the future stochastic variable has nothing to do with the past, yet conditionally depend on the current status.


Monte Carlo method cannot even reach 90% accuracy with up to 1.2e+6 samples.

the proposed method can achieve 5200X speedup over Monte Carlo, 123X speedup over MixIS [4] and 42X speedup over SS [6].


This transistor is identi.ed by measuring the increase in the total average leakage, Lkg, with respect to the delay reduction, D, of the critical path when such a change is made.

we evaluate D Cost = (8) Lkg The transistor with the minimum (most negative) cost provides the largest delay reduction for the smallest increase in leakage power, and is selected for assignment to ToxLo.


However, in the proposed design only a clock frequency of f1 =f2=fCLK/2 and a two-time slower comparator are needed.

with the same circuit modules, the proposed scheme doubles the sampling resolution.


We also evaluate our system on subscription patterns that arise in large-scale collaborative applications.

we used a trace of all edits of Wikipedia articles by registered users over a 6 year period to both directly evaluate Magnet and to generate a model of real-world subscription patterns.


If so, we can identify blocks to serialize even if the rest of the system cannot change.

the block would still have a parallel interface, but would do its internal processing in a serial fashion.


In these cases, delay and power of the proposed architecture decrease according to the limited number of optical routers capable of transmitting data packets to each destination node.

one and three nodes are allowed to originate optical packets targeted to each optical router in the case of FMT and local traffics, respectively.


According to Theorem 1, we shall make the nodes corresponding to the modules of a power-hungry group in the boundary ring .T .

we prefers to make those nodes a sublist of the ring .T during the perturbation in simulated annealing.


The latest generations of mobile phones have huge computational capabilities and, therefore, they provide the ability to run complex applications.

in most modern embedded systems users have the ability to install new applications, and, thus, add new functionalities.


The results indicate that the aggressive scheme performs better, in terms of error recovery, than CE.

aG + parity and AG + ecc can recover over 77.1% and 95.0% of the transient errors, respectively.


The combined period of false detections and false alarms is 1112 µsec (2×364 + 384) while the duration of correct detections is only 448µsec (2× 224).

the best CCA can correctly detect and avoid collisions is only about 29%.


We used a single test template that speci.es the scenario requirements as is.

the test template speci.es that the .rst instruction is a load (from the set of loads in the experiment) and  TABLE I EFFORT AND SUCCESS RATE FOR THE THREE GENERATION SETTINGS Setting Stream Basic Expert Test templates 1 1 7 Effort 10 min 10 min 3 hours Success Rate 97% 59% 92% the second instruction is a store whose memory operand has the same address as the memory operand of the load.


Compared to Table 4, the boundaries for both global/intermediate and intermediate/local are reduced due to the reduced number of long interconnects.

a higher portion of random interconnects can be assigned to the global and intermediate layers Table 7: Modules and their correspondent microarchitecture, gate count, and power under different repeater and .ip-.op insertion models.


Most recent RFID researches do not http://dx.doi.org/10.1145/2554850.2555189 713 deal with the heterogeneity of the IoT.

most authors proposes algorithms and mechanisms to deal with a simple technology [7], making the current proposal in this abstract original and new.


For this hierarchy, we also see that ordering provides less bene.t over grouping the performance of L1 and L2 grouping with random ordering (L1 & L2 + RO) is very similar to recursive schedule.

conv and mmm, which exhibit sensitivity to ordering on the Throughput Processor, now barely bene.t from ordering.


Because the leakage power is negligible for DRAM devices and AMBs, we do not include the thermal-leakage feedback loop in the equation.

we assume their leakage power rate does not increase with the temperature.


HALF+FX reduces the energy consumption as compared to BIG and HALF by 17% and 3.3%, respectively.

this is mainly because the energy consumption of the IQ and the LSQ is reduced, as described in Section V. the energy consumption of the IQ is signi.cantly reduced.


We can count the number of bits required by charging each edge for each subtree it must exit.

when a graph edge needs to cross out of the top of a tree at level i, we need one bit to specify which way the edge connects at that tree level.


To ensure that the instruction cache is kept coherent, and that stale instructions are not fetched, JIT compilers use softwareassisted coherence.

the JIT compiler is responsible for managing the invalidation and writeback of the a.ected cache lines.


Batson and Madison defined a phase as a maximal interval during which a given set of segments stay on top of the LRU stack [ 18].

a phase is defined as the maximum interval over which the working set re- mains more or less constant.


Furthermore, since resizing cells perturbs the initial global placement and routing, we demand an effective ECO (engineering change order) mode.

after cells have been resized, we require that the placement be topologically similar to the previous one, and that the wire lengths are also largely the same.