The way in which the extra edges are to be added to semi-eulerize and subsequently, the identi.cation of an Euler path depends on the choice of the source and sink ports.

the graph model of an M × N micro.uidic array can be semi-eulerized simply by exploiting its regular structure as demonstrated in 1(b), with dashed line representing extra edges, for a 5 × 5 array shown in Figure 1(a).


User D, from another project team, did not subscribe User A s posts.

he meets User A at the restaurant and after chat, user D realizes that he may help User A with some previous works he did on retailing system.


As abstraction is layered atop abstraction, developers gain the ability to compose systems of extraordinary complexity with relative ease.

many software properties, especially those that cut across abstraction layers, become very dif.cult to understand in such compositions.


Though NBTI impacts only the PMOS devices, it may seem enough to consider only the rise time of a cell.

the timing arcs from an input pin to output pin can be either negative unate (e.g.


For sort, the potential speedup on SOSA over quicksort on a single processor (average case) is O(log(N)).

the overhead introduced by predicated instructions makes it impossible for SOSA to match the performance of the I-SS or P4.


Since multiple virtual addresses can be aliased to an identical real address, the list may contain multiple accesses to the same real address.

the designed logic allowed the accesses in the list to be reshuffled and thereby not maintaining the PowerPC ordering rule.


Even through self-heating of wires plays a very important role in the electro-migration lifetime of the metal wires [1], during the placement stage, we do not have the exact information about the location of the wires and we will ignore the self-heating of the wires at this stage.

it is potentially possible to take this into account during a later stage of placement using the congestion information, though this is beyond the scope of our work.


Historically, thepenalties due to refresh werelow enough to not warrant additional complexity.

the memory retention problem is getting worse over time and is exacerbated by the multi-banked design of eDRAMs andthehigh-performance environmentsinwhichthey aredeployed: 1.


memory-level parallelism and to minimize memory access latency.

we .nd that although such scheduling policy is simple and performance-optimal, it wastes unnecessary energy.


In [2], the pioneering work aiming cell generator, a mapper that uses cells constrained by its size was presented.

the technique was limited in the sense that it was not aware of performance since it only attempts to map the largest cells possible.


As a result, the features used by earlier work cannot be directly used here.

we still try to draw from previous work.


Besides, the temperatures for inactive thermal nodes (e.g., TSV blocks) are also left unspecified.

in order to compute the steady state powers, these temperatures should also be known.


Figure 4(b) shows the tree topology generated by MMM3D.Notethat s1 is merged with s3 and then with s2 because s3 is physically much closer than s2.As a result, two unstable TSV-bu.ers shall be inserted, which then causes propagation delay imbalances on both of the two subtrees, thereby allocating two normal bu.ers, one between x2 and s3 and the other between x3 and s4.

if the sinks partitioned by die layers, and then partitioned by (x,y)-coordinates, the resulting tree topology needs one TSV, as shown in Figure 4(c).


Previous work such as[18]has used an outer-loopiteration spawnpolicywithsome successin suchcases.

monotonically decreasing goodness occurs in cases of .ne-grained parallelism.


Their objective is not only to optimize the clock period, but also to heuristically minimize the required inserted delay.

the time complexity of their algorithm is O(|E|2*|TOCSS|), where |E| is the number of data paths and |TOCSS| is the time complexity of the used optimal clock skew scheduling algorithm.


The experiments reveal that both methods are conservative with respect to the observed execution and that the WCET estimated by LR analysis is up to 3.8 times larger than that of detailed analysis.

the proposed optimizations reduce this factor to 1.4.


However, due to conflicts in the cache, capacity limitations and low visibility into the actions on the lower level caches, these properties cannot be held using the typical LRU policy in the lastlevel cache.

if the priorities were mapped according to the type of the memory access, then the policy used to manage that line in the cache can be changed.


Observe that some previous approaches tend to do the opposite, e.g., by linearizing the quadratic objective in analytical placement so as to minimize linear wirelength [16].


All the above post-silicon variation studies are invasive.

there is a need for noninvasive post-silicon characterization methods.


For example, the subscription arOM,BMW,W}AND nameLiz,Bob,Al} AND (year90) requires 27GRYPHON-like subscriptions.

such disjunctive subscriptions are naturally handled by BDDs.


Although the main memory energy increased due to increasing the bus width by a factor of 16x (compared to 11x), the savings in the other units offsets this increase.

482.sphinx saw a 3.7% increase in energy, which can be attributed to the benchmark having a high number of main memory requests.


Without on-chip inductance, the voltage .uctuations are almost the same even though Trvaries.

figure 5 shows that the voltage .uctuation with on-chip inductance changes and the peak values are 5.6mV, 10.3mV, and 16.4mV, which are almost in inverse proportion to Tr2.


It is able to optimize expressions consisting of only one type of associative and/or commutative operator at a time.

it cannot generate complex common sub-expressions consisting of additions and multiplications and it does not provide a modular factorization.


Obviously, this approach is limited to small problem sizes and is therefore not applicable for practically relevant benchmarks.

some properties, such as redundancy or conformity, encourage a complete investigation of the solution space.


This is because the Rent exponent is uniform, and routing resources demands should be fairly consistent across the entire circuit.

with a high standard deviation, interconnect demands should be non-uniform, thus allowing the depopulation scheme to reduce the routing demands of high Rent regions.


The novel implementation of the 4Dtile-based mapping presented in this work extends the work in [3].

if the size of the tile can be assumed to be a power of two then simpli.cation of 4D-tile-based implementation presented in this paper can be applied to other applications of tile-based mapping as well.


N should include all nets in the shift register and all nets in the feedback function.

for security reasons most stream ciphers use long FSRs.


the Mitsubishi announcements [16] and the IRAM initiative of U.C.Berkeley [17]).

these solutions provide a onetime drop after which the widening energy-delay gap between the storage and the logic will keep on progressing, due to the unavoidable evolution of the interconnect contributions relative to the arithmetic and control logic.


In a CPPC extra read operations (read-before-write) increase the pressure on the read port of an L1 cache, and, in some processors, may affect the scheduling of instructions.

this operation is only required on a Store to a dirty word.


In the past, the impact of process variation (PV) on conventional transistor-based storage cells and combinational logic has been studied extensively.

the implication of PV on non-volatile memory design using emerging phase change techniques has not been well understood.


In theory we could cascade two or more of these circuits to obtain the desired range.

in practice we must be concerned with the undesirable noise and jitter added by each stage.


However, on one hand, contemporary GPUs consist of many multiprocessors that can process data concurrently.

recent FPGAs provide huge level of parallelism, and reasonably high performance potentials, which can be exploited very e.ciently by smart designers.


Thus, when the number of the threads in majority group is high, the original dynamic majority-based scheme is employed in order to achieve high IPC.

when high IPC cannot be achieved, the scheduling strategy is altered to prevent starvation.


In this way, our solution provides a lowcost,high-coverage solutionfor soft errorsin embedded microprocessors targeted for the consumer electronics market.

unlike the high-availability IBM and HP servers that can provide provable guarantees oncoverage,thisworkprovides only opportunistic coverage, andistherefore not suitablefor mission-critical applications.The contributions of this work are asfollows: A software solution which does not need any user annotations in the application to generate reliability-aware code and works on applications writtenin a variety oflanguages.


Currently, Field Programmable Gate Arrays (FPGAs) are used widely because of their .exible recon.guration advantage [1] [3].

since the FPGA s recon.guration requires more than several milliseconds, FPGAs are unsuitable as dynamically recon.gurable devices.


Due to its versatility, radar has found applications in defense, law enforcement, meteorology, and mapping.

widespread commercial applications of radar have been limited because conventional systems are expensive, bulky, and di.cult to use.


Nodes are allocated a slot number at the beginning of deployment.

any node can send a command to another node to release its time slot.


For processes which operate exclusively on sampled signals, we use the more specialised model of synchronous data .ow [16], because it is signi.cantly cheaper to implement.

we deviate from data .ow and synchronous data .ow process semantics by de.ning a few speci.c, atomic processes, which are not causal.


The main reason for this is that we are interested in exploring issues related to the I/O protocol stack, which because of transparency requirements in practice always involves the operating system kernel.

user-space programs can still access the NIC in an unprotected manner for testing and benchmarking.


In this type of mapping, we can access a word of the logical memory by activating exactlyone embedded memory block because each word of the logical memory is stored in exactly one embedded memory block.

we need an address decoder to select an active embedded memory block per access, and a 4-1 multiplexer for a read operation.


Note that when ISR is activated on the MT, the average update rate is .at at around 1.5 updates per hour as the third component is zero.

when ISR is deactivated, the average update rate increases as a square root of Nh while the total area of coverage holes, aAo, is .xed.


The important point is that if there are no loop carried dependencies, any scheduling of iterations groups is legal.

if we have data dependencies, we need to determine a legal schedule that respects all dependencies.


While a potential disadvantage of the aforementioned clocks is that every device may need to be contacted individually, potential advantages include additional energy reductions [18], and more fine-grained control of an NML ensemble (useful architecturally per [7]).

any circuit will still be inherently pipelined [18], bit conflicts can still occur, and our insights are relevant to other clocking approaches too.


P/Invoke calls may only result in an integer value returned from the DLL, which for instance is the case for most GAPI methods.

some GAPI methods return data structures which calls for the use of a C++ wrapper DLL.


Common values are 64 B for 2 KB pages and 128 B for 4 KB pages.

common ECCs as Reed-Solomon or BCH are not designed to be overwrite-compatible, meaning that an overwrite-compatible data change will not necessarily result in an overwrite-compatible change in the corresponding ECC.


Rescheduling the loop, on the other hand, can be computationally expensive.

in practice, only the shifted operations have to be repacked in the schedule.


In the charge pump, the number of stage will increase when the VDD is lowered to 1.8V, and therefore energy loss by MOS diodes increases.

since the boost converter achieves 20-V program voltage with single-stage circuit, the energy loss does not increase.


graph for LM, an edge ei,j between two tiles ti and tj denotes that the distance between the two tiles should be equal to or larger than a constant d(ei,j ).

this de.nition is not suitable for DPT because DPT depends on the conditional spacing, i.e., the spacing between two patterns should be at least sd if these two patterns are on the same mask.


To address this issue, we can minimize the number of cache sets in a module (i.e., M = S), such that each cache set has a set of counters to track each way.


[9] discusses a network topology very similar to the one implemented in this paper; the authors conclude from their limited experiments that it is a feasible topology, which has trouble competing with mesh networks on smaller devices but scales better.

the evaluation here is under the conditions of an MPSoC and not an embedded device, and the conclusions may also be different when application-speci.c information is taken into account.


The same holds for the neuronal correlation detectors of the barn owl auditory system.

the barn owl overcomes this problem by employing a large number of correlation detectors along the two anti-parallel axonal wires .


A good upper-bounding strategy .nds an optimal solution as quickly as possible, thus pruning as many nodes as possible.

a near-optimal upper bound allows pruning of many nodes whose lower bound exceeds that of the root, and may be almost as good.


Among the maximumperiodgenerators,wethenselectedfromthose withthebest equidistribution,whichisa measureoftheoreticalquality[10],Thebestgeneratorfoundisactually maximally equidistributed, which means it has the best possible quality for this type of generator, and provides equivalent quality togenerators such astheXorShift.

alllinear generators have a known statistical .aw, due to their .xed linear complexity [11].


Several recent thermal-aware DVFS techniques are found effective in single-processor scenarios, where the cool tasks interleave the hot 2 tasks to keep the temperature .uctuating below its threshold [11], [12].

in the multiprocessor scenarios, the notion of cool task calls for rede.nition in the presence of shortened thermal conducting paths under increasing chip density, as well as the parasitic thermalrunaway effect.


Again depending upon the external factors, these results might vary but they show that for a moderately large distributed system, DCC can compete with vector clock.

for small number of processes, it is still better to use vector clocks if execution time is the main concern.


3.2 Purpose-Provided Data Publicly released datasets clearly provide a major bene.t to the community in terms of allowing broad access to measurement data.

it behooves us to also consider data shared more informally during collaborations; among friendly researchers to help each other out; or with students for a particular project.


Extensibility: The five power management solutions we consider in this paper represent a large class of existing approaches.

the architectural principles we use enable our design to be easily extended to other classes of controllers and other specific implementations.


Therefore, the above statement for the stuck-at fault model is also true in this case.

if delay information is involved, then the resolution of the diagnosis is not the same as the fault resolution in the logic domain.


In this case, the ISR will jump to the ExIntr_Hdlr() function which recovers task2 from the lock-wait table of lock#6 and marks task2 as ready in the ready table before the scheduler re-schedules it.

if the received interrupt is for a short CS lock release, then the ISR will store back the initial value of Link Register of the processor so that the processor jumps to the last instruction just before sleeping, i.e., the short CS lock primitive execution.


These large capacities allow DR A M Cs to capture a large portion of an application s memory footprint and thus can signi.cantly improve system performance.

using a DR A M C is not free of challenges.


Today, industry is advocating a suite of new and emerging technologies energy-harvesting transducers [13], thin-.lm batteries [1], micropower integrated circuits [9], and nanopower microcontrollers [12] coupled with star network topologies, to address the pressing challenges of energy harvesting operation.

we show how existing technologies  solar cells, simple capacitors, switching regulators, .eld-effect transistors, and lowpower microcontrollers and radios can be combined in new ways, and coupled with simple protocols and good engineering, to achieve hassle-free, energy harvesting operation, without sacri.cing the bene.ts of interoperating with battery-powered meshes.


As this limit is intrinsic to the .ltering approach, the works that have extended the method above have inherited this limit.

keeping the .ow state since a .ow s .rst packet is critical for schemes that rely on the information carried in the .rst packet or .rst few packets.


Given the long latencies associated with fetching data from another processor s cache, this veri.cation operation will most likely stall the processor.

using the constraint graph, we can detect cases where it is safe to use the stale value, without the need for veri.cation.


On one hand, this makes KSC inefficient.

such logical dependency will make the code words non-uniform and weaken the security of the PUF data.


Except for the 2K window size case, simple-JITA cannot outperform the noaccess policy without JITA.

the experiment results shown in Figure 3 suggest that the 2K window size used in [8] does not seem to be acceptable for high-performance applications because of significant run-time increases.


n-Modular Redundancy (nMR): Spatial or temporal redundant execution has long been a cornerstone for detecting soft errors, with hardware DMR (dual-modular redundancy) and TMR (triplemodular redundancy) being the solutions of choice for missioncritical systems.

the cost of such techniques has relegated them to the high-budget server and mainframe domains (e.g., HP NonStop series [3] and IBM zSeries [2] machines).


Hence, the most viable method for estimating power consumption of 3D-DRAMs is to use system-level power models that use JEDEC-speci.ed current and voltage values from memory datasheets, which are based on real hardware measurements.

it should be kept in mind that the accuracy of the DRAM power model using these datasheet measures, de.nes the accuracy of the DRAM power and energy estimates.


If the outcome of m is a global miss or hit, it is not a.ected by the cache state before TR.

if the outcome of m is a local miss, then it may hit or miss in the global trace depending on the cache state before TR.


Bit-interleaved writability with word-line boosting and 57.7% area overhead C. Dual Writability Enhancement In the previous subsections, two writability enhancement techniques are used.

both techniques are practically limited to below 4s.


problem is mitigated by a requirement in section 7 that says, Cryptographic protocols using asymmetric keys that require PIN shall not be used on the contactless interface.

this requirement does NOT state that the PIN shall not be used on the contactless interface without the use of asymmetric keys.


The resulting scheduling is shown in Figure 5.

this approach is not well suited to high throughput applications.


Thus, for performance reasons, a three-level hierarchy with a moderate size (e.g., 512KB) L2 cache will become an attractive alternative to two-level hierarchies at these feature sizes.

the cost may be a signi.cant increase in energy dissipation due to transfers involving the additional cache level.


In this work, we use the Omega Library to capture the iteration and data sets and the mappings between them as well as to generate output code.

its choice is orthogonal to the main focus of this work, i.e., if desired, it can be replaced by another polyhedral tool.


For MPGdecoder, the performance degradation shown in Figure 6 is caused by a large number of read-only replications because they should be read from the other on-chip cache whenever a read miss occurs if they are turned o. while the read-write replications do not cause the signi.cant performance degradation.

by controlling the number of TOS blocks, RALM reduces the energy consumption by 62.4% and 20.0% on average over BASELINE and DE-CAY, respectively.


Thisis because under fewer node numbers, the system requiresmore sound sources to make accurate estimation of interdevice distances.

we do not observe signi.cant difference in the ultimate accuracy among the three cases.This is because as the number of sound sources increases,eventually the system will always have high probability ofaccurately estimating inter-devicedistances for everydevicepair.


For any given relative error E> 0, the running time of the algorithm was proportional to 1/E.

its computational complexity was high, making it inhibitive for large circuits.


This is because the NOR-type standard cell has a stacked pull-up network with a larger Rp compared to the balanced pull-up and pull-down networks of an inverter.

vmin of NAND-based ROs is smaller than that of INV-based ROs especially at TT and FS process corners.


The simplest solution is to throttle memory accesses when temperature reaches a thermal emergency.

such approach may lead toalarge performance overhead.


Thus at most k +1 iterations are needed, where k is the total number of alignment constraints.

if alignment constrained blocks are not aligned after k +1 iterations, then it indicates that there exists crossing between different alignment constraints.


In [8], it is observed that the circuit can be expanded to higher numbers of inputs by expanding the decode tree.

it is important to note that expanding the tree beyond a certain height reduces noise margins and makes the LUT circuit vulnerable to process variations, since it becomes increasingly di.cult to detect the di.erence between high and low MTJ states due to the additional resistance introduced by the transistors in series.


Employing an EDC/ECC to larger data blocks reduces the total number of redundant bits concatenated to the memory; hence, per-line EDC/ECC imposes significantly lower area overhead in comparison to per-word EDC/ECC; lower area overhead leads to lower static power overhead and even lower dynamic power overhead.

per-line EDC/ECC require a whole line access for every read or write operation to check or update the EDC/ECC of the line.


All the aforementioned researches achieve some notable results.

the chip-package design has become increasingly challenging, more considerations must be accounted for: These approaches assume that bumps are arranged in .xed array locations with unique spacing, they then design the area-array ICs by planning the I/O placement with cost functions and constraints or connecting bumps and I/Os with RDL routing.


Asynchronous circuits seem a promising option for logic implementation on nano-crossbar architectures.

the circuit must be designed in such a way to guarantee the required timing constraints, under extreme delay variations, to ensure correct functionality.


INTRODUCTION Sensor networks bear a promising future in many important applications such as habitat monitoring, military surveillance, and target tracking.

sensor networks are also confronted with many security threats such as node compromise, routing disruption and false data injection, because they normally operate in unattended, harsh or hostile environment.


simulation #I simulation #2 It is obvious that the proposed .ow does not work for general circuits, as in general the solution of DAE equations depends on the initial condition, and the time segmentation essentially neglects this inter-segment dependence and thus may lead to incorrect results.

in practice, a lot of circuits of interest satis.es the so-called short-memory condition, i.e.


A C-element behaves as follows: when all inputs assume the same value, the output assumes this value; otherwise, the output does not change.


The critical threshold Ccrit was set to 0.3 for these figures which redundancy was added for each design.

in contrast to the resulted on average in 22.8 % additional shadow transistors.


As for the two exceptional functions, the distribution of care elements are skewed.

by using linear transformations, we can easily smooth out such skewed distributions [8].


To prevent the increasing latencies from affecting the cache throughput, the cache access is pipelined.

even with a pipelined cache access, the instructions dependent on the load instructions still have to wait a signi.cant number of cycles, which leads to signi.cant performance degradation.


3(a)), node 1 will eventually reach supply voltage in an enough long period.


Literature on clock meshes focuses on design methodologies for mesh reduction and optimization, and ignores multi-corner analysis, as the ubiquitous shorting of branches provides remarkable robustness under PVT variations.

this assumption only holds true for a traditional, single-Vdd clock mesh.


Hence, genetic memories can possess various operation modes which are analogous to electrical latches and SRAM cells.

genetic memories behave on a set of mechanisms which have their intrinsic biochemical characteristics and dynamics.


And also since the prediction is not always 100% accurate, CBWT may get sub-optimal performance.

since CBWT precisely controls the intensity of contention and congestion, it predicts well and overall archives competitive performance compared to Best-CBWT.


The increase ratio of the check instruction is high for low OVP thresholds.

for the thresholds over 5%, no additional check instructions are required other than checking the .nal result.


Admittedly, HPWL is not the most widely used metric in FP-GAs.

this is a good starting point for two reasons: First, most of the available academic ASIC placers are HPWL-driven, thus reporting on HPWL provides a fair and credible result; Second, it could be argued that routability or timing-driven placement can be derived from HPWL-driven placement by properly weighting the nets.


If the high-frequency clock is turned off, then the time resolution is automatically set to the slow-frequency crystal.

the HLTimer will not loose time because it increments the counter not like a regular timer by 1 at every clock tick, but by the amount of ticks the high frequency clock takes, during one low fre- Figure 2.


That work was minimizing buffers, akin to hardware buffers in the original hardware pipeline work.

most computers stage values in registers, which are more flexible than buffers as registers can be used to store different values of different variables on a cycle-by-cycle basis.


4, if we reduce power by switching G4 to a lower power higher delay con.guration, such as low-Vt to high-Vt with the slack margin .Smax, no optimization may be further performed on G6 without violating the timing target.

g3 and G5 can be optimized with the same slack margin for better Theoretically, the sum of log-normal random variables does not have a closed-form distribution.


The common solution to provide race free execution is explicit synchronization written by the programmer.

explicit synchronization operations increase program size and complexity: the former costs energy and RAM, the latter increases the chances that, after a month of deployment, a scientist discovers that all of the collected data is invalid and cannot be trusted.


A quadratic programming approach [19] for 3D placement was also proposed, which finds an overlap-free placement by modeling the cell distribution with a discrete cosine transformation-based cost function.

none of these 3D placement methods consider mixed-size circuits, or at least none of these works report 3D placement results on mixed-size examples.


albeit the obtained results show that improvements could be obtained, these are much more modest than the ones obtained by using DIMxS.


All local counters change value with every T pulse.

this happens at very coarse intervals (equal to the period of the global counter).


Whereas, traditional gm-C filters, which can operate at higher bandwidths, suffer from limited linearity.

current-mode active elements, like the second generation current conveyor (CCII) and the current feedback amplifier (CFA) exhibits attractive characteristics such as wide frequency operating range, low power, high linearity, high slew rate and simple circuitry [5].


In prior research, numerous approaches have been proposed to mitigate this issue.

most of them mainly focus on I/O operations of compute-intensive application or only read operations.


Again, the l index is independent of all three metrics under the simulated process variations.

the c, s, and SSIM indexes have the strongest correlation with the variance of the inter-ADC metrics.


This simulation based approach is capable of handling various device models, different 3e-09 circuit design styles, but takes very long simulation time.

4e-13 our hierarchical partitioning approach partially compensates for this 3.5e-13 2.5e-09 problem.


Avoiding duplicate I/O initialization: Some HAL libraries, including sensor and cellular modem s, perform initialization of the I/O device upon system boot.

since the I/O device is already initialized in the server, the client HAL should not attempt to initialize the I/O device.


The methods mentioned above do really help interface compliance verification.

these techniques generally require users to specify what they want to cover in proprietary input formats or languages uncommon to typical designers.


If the network contention is low, .exible-pipeline routers make it possible to scale down network frequency without increasing the latency.

this technique cannot prevent degradation in the network throughput, and thus frequency scaling can still lead to performance degradation.


In the simple example of Figure 2, the position groups and the repeating sequences are easy to identify, and the number of groups and sequences are small.

a test set for a real-life circuit can lead to a large number of groups and sequences.


The authors of [9] presented an analytical framework that provides a closed form expression for the total chip leakage current as a function of process parameters that can be used to estimate yield under power and performance constraints.

none of these have considered the effects of spatial correlations in intra-die process variations.


1Mkeys).thattimeisconstantindependentlyof thedatasetsizebecauseourparameterssands 0 arefxed and,qislimitedto512.Thattimecanbereducedvaryings, s 0andqwhenwehavetosortsmalldatasets.for themeasuresofthispaper,thosevalueshavebeenfxedas wesaid.TheCountingSplitCSEisconstantforallthedata setssortedanditisaroundthe20%ofthetotalexecution time.


To gain true energy savings, cache accesses due to FVs should well exceed non-FVs.

not all applications we analyzed held this property favorably.


This is because the number of activated bit lines and sense ampli.ers is reduced.

the presence of the extra decoding logic and transmission gates tends to increase the cache access time.


As exact decap allocation is a time-consuming process, it is impractical to solve an LP problem for every candidate solution.

our white space insertion takes O(n 2), which is computationally equivalent to computing block location using longest path computation for area.


The Verilog/VHDL code can then be put through the Synopsys tool Design Compiler to obtain timing and area.

adding TIE instructions may incur an increase in the latency of the processor.


These non-overlapped long-latency memory accesses can congest the instruction and issue windows and stall the processor.

the proposed P-load can effectively overlap the interconnect delay in sending/receiving data as shown in Figure 3 (b).


On average, the proposed technique shows around 7% estimation error for 1K vectors compared to the HSPICE measurement.

comparing the simulation speed, the proposed technique completed the estimation within a few seconds while the HSPICE took 3.4 hours on UltraSparc80® 450MHz dual processors with a 4MB L2 cache.


This architecture has high system throughput of 1/tclk data per second, where tclk is system clock period.


These designs are usually seen as superior to a multi-level table, because they only need to be referenced once, whereas the radix table requires one access per level.

hash collisions are unavoidable, so many accesses may require more than one reference to follow a collision chain.


6 shows that the residual norm decreases rapidly for the new algorithm.


One of the most popular models for congestion estimation in digital circuit designs is the probabilistic congestion model [7, 14], which e.ciently estimates routing congestion of a 2-pin net based on L-and Z-shaped pattern routes and has a good e.ciency and accuracy trade-o..

we do not use the probabilistic congestion model because the size of the routing tiles in an analog circuit design is typically much smaller than that in a digital circuit design.


Increasing granularity also incurs an area penalty due to an increase in the number of con.guration vias and total layout area.

due to the faster logic con.gurations, we expect higher granularity to result in higher performance.


A distinctive feature that can be observed is that the number of L1 Dcache misses are usually small during the execution of large packets.

these misses are comparatively large during the .rst few cycles (during which packet headers are processed) of execution (portions near the markers) of nearly all packets.


(instead of the same data cache as in [9]) at the time of the read (note that if we consider the replicas in the L2 cache, the proposed approach can achieve 100% loads with replica.

in our experiments, we focus on investigating how many replicas can be found in the small replication cache at the time of read hits in L1 data cache).


So far, we identified a new source of variation in FinFET devices.

in order to capture and analyze the effect of process variation on the characteristics of the multifin FinFET device, width quantization property of FinFET devices should be considered.


Raising the threshold voltage for the gated-Vdd transistor increases the stacking effect and further reduces leakage current.

this will impact the read time of the SRAM cells and may have to be offset with other techniques.


Reducing Latencies of Pipelined Cache Accesses Through Set Prediction Aneesh Aggarwal Electrical and Computer Engineering Binghamton University Binghamton, NY 13902 aneesh@binghamton.edu Abstract With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors.

with reducing feature sizes and increasing clock speeds, cache access latencies are increasing.


Similarly, the MSA scheme of SSA alone degrades the performance by about 2.4% (the MSA0116 con.guration).

sSA deploys the BO-LSQ by modifying the default LSQ design to compensate this performance loss.


This chip organization has bene.ts in terms of power-ef.ciency, scalability, and system throughput compared to a single-core system.

shared hardware resources pose a signi.cant resource management problem in designing CMP systems.


In their paper, they conjecture that the performance bottleneck is CPUs.

we demonstrate another performance bottleneck from the bottleneck analysis in this paper.


We are also interested in extremal deviations of circuit metrics from a polynomial approximation .tted through regression.

instead of using extreme value theory, we use a statistical hypothesis testing approach.


Energy-Efficient Cache Design Using Variable-Strength Error-Correcting Codes Alaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, Wei Wu, Chris Wilkerson, Shih-Lien Lu Intel Corporation 2111 NE 25th Ave M/S JF2-04, Hillsboro, OR 97124, USA {alaa.r.alameldeen, ilya.wagner, zeshan.a.chishti, wei.a.wu, chris.wilkerson, shih-lien.l.lu}@intel.com ABSTRACT Voltage scaling is one of the most effective mechanisms to improve microprocessors energy efficiency.

processors cannot operate reliably below a minimum voltage, Vccmin, since hardware structures may fail.


This situation should happen rarely since data mapped with a certain granularity will always (or almost always) be accessed in the same way.

this could occur for example if an array of bytes (or the last elements of the array) and a 32-bit integer scalar variable are mapped to the same cache block.


The HEI mechanism is similar to TM with a lazy versioning policy and lazily detecting conflicts among transactions.

it is not based on optimistic synchronization as TM is; there is no notion of abort-and-rollback, nor is there a need for contention management.


When high sequence similarity is detected between a query sequence of unknown function and an annotated database entry, reliable function prediction for the query can be obtained.

lCRs may result in erroneous function predictions, as the high score observed is rather due to the bias effect and not due to genuine homology.


Normally a program s outputs are just the values sent by the program via I/O operations.

if a program is run under a debugger, then program variables examined via the debugger become outputs, and influence the determination of which bits are ACE bits.


As expected, these techniques show that TDC leads to a reduction in test time for the core-based SOC.

they do not provide any quantitative insights on the test-time reduction (at the SOC level) derived from adding a decompressor for any given embedded core.


The probabilistic method checks each memory location only when it is accessed.

the deterministic approach cycles through the whole memory and checks for correctness in all memory locations.


In those cases perform mance benefits of SPWFs may not scale significantly with bitw width.

sPWFs may enable significant reductions in t the number of logic gates used as well as simplify interconnect r requirements.


If the current bisection represents a feasible solution, then the queue that contains the highest gain vertex among the 2m vertices at the top of the priority queues is selected.

if the current bisection is infeasible, then the queue is selected depending on the relative weights of the two partitions.


When increasing the cache line size, the hit ratio initially increases, reaching a peak of 95% for line sizes of 8 and 16 words, then decreases for larger cache lines.

the bandwidth increases with the cache line size slowly initially, then explodes for line sizes larger than 32 words.


Two back-to-back NOR planes are universal gates, and they can implement the traditional AND-OR PLA by applying DeMorgan s theorem.

the CMOL [6] approach combines CMOS with molecular and one-dimensional devices.


clearly, in this case, the structurehypothesis is restrictive in that the procedure does not seek to .nd arbitrary forms ofinvariants.theveri.cation procedureis still sound,becauseifa suitable inductiveinvariantisnot found, onemayfailto prove the property,butabuggy system will notbe deemed correct.


In other words, the error correction needs fewer physical ancilla qubits for every physical data qubit (a ratio of 1 to 2).

the qubits in the compute region actively participate in the quantum operations.


The most common .tness approach is interactive evaluation.

e.ciency challenges with such an approach has inspired the search for automatic alternatives.


As the DRAM-cache frequency increases, the cost of the 24-cycle MissMap increases relative to the DRAMcache latency, and therefore HMP provides a small but increasing relative performance bene.t as well.

increasing the DRAM cache frequency reduces the relative additional bandwidth provided by the off-chip DRAM, thereby potentially decreasing the effectiveness of SBD.


This type of circuit is usually implemented by a CMOS switch.

the demodulator block converts the ASK modulated signal received by the tag into a digital signal.


In order to realize the negative o.set at p, a driver pin is found higher in the clock tree, so that if p is connected to it, the di.erence in Arrival Time (AT) will e.ectively realize the o.set.

these driver pins, called from now on acceptors, should reside at the same scope of hyper-net as p to guarantee the same functionality as mentioned earlier.


While status signal is ON and there are .its waiting for dispatch, the upstream router keeps on .it transmission.

it stops sending .its upon status turn o. since bu.er slot shortage will cause .it loss on the downstream side.


Reducing supply voltage is one of the most effective methods to lower power consumption.

as supply voltage decreases, the effects of process variations become more pronounced, causing many circuits to fail.


Furthermore, all the node devices at the same row in the hexagonal fabric are controlled by a single input variable.

the realization of the BDD architecture in [8] is .xed and not amendable to functional recon.guration.


the constraint can also be satis.ed by putting 1 buffer on both A and B, denoted as S2.


The domain with larger area requires a larger current density to switch and is termed as the hard domain.

the smaller domain switches with a smaller current Fig.


Design and CAD Challenges Ruchir Puri IBM T J Watson Research Center Yorktown Heights, NY 10598 ruchir@us.ibm.com ABSTRACT With the impact of cost crunch in every industry including semi-conductor industry across the world, complexities of 22nm CMOS may appear to be way out in the distance future.

more than the technology complexity, the new era of financial restraint will impose unprecedented productivity requirements on future design flows.


The B-Cache incorporates three tag bits into the PD; therefore the tag length is reduced by three bits, which reduces the tag side access time.

we do not claim this access time reduction since the data and tag path may already be balanced[19] so that the data side would be on the critical path.


Some recent proposals [25] have called for the partial replacement of DRAMs with PCMs in mobile devices.

due to its overhead in dynamic power and access latency, PCM is not expected to completely replace DRAMs, but instead to be used for highendurance but infrequently accessed data [25].


The simulation time of any network that is formed using 2-input gates is bounded on the lower side by the number of gates and on the upper side by an exponential function of type O(2n).

the key observation is that one has just to simulate the frontier of propagated signals.


partitions with no droplets (at any point in time) should be avoided because no droplet manipulation is done in this region with the additional set of pins assigned to it.


The above procedure using PLI interface avoids the VCD .le generation for estimation of switching activity.

the VCD .le is still required for IR-drop analysis but it is performed only on one pattern in each group with the highest number of switching scan .ip-.ops.


The reason is because the window size of 1024Kc is still too small for twolf and it causes many extra L2 misses.

the average drop on execution times of SPECint2000 benchmarks still reaches 3% when the number of BO-LSQ entries is 8.


But this consistent miss rate improvment is realized at the cost of more energy consumption compared to RSC and RHC, which will be discussed later.

since RSC dynamically powers off the cache ways -although this is done based on the cache pressure -the reduced cache capacity consistently impairs the cache performance (77% more cache misses), especially when the dynamic recon.guration scheme can not accurately capture the cache behavior.


Renewable energy from solar or wind might be directly converted into electric power and fed into the electricity grid.

due to the volatility of renewables, electric energy bu.ers become necessary.


Using SMS messaging as an example, when the number of process states de.ned for HMM in pBMDS increases, detection accuracy of pBMDS is improved.

this incurs a longer training and detection process.


in transistor level netlists, the majority of nets connects gate pins only or drain/source pins only.


For instance, the one-to-all pattern is a typical broadcast, and it can be mapped onto a star topology in order to increase the broadcast throughput from master to slaves.

this pattern can change to one-to-one communication and the pipeline topology can be a better option.


To this purpose, many reference circuits have been developed in order to provide accurate, temperature-independent voltages/current.

all efforts oriented to improve the accuracy of these reference circuits can be vanished by the presence of electromagnetic interference (EMI) [1].


Furthermore, the order in which the driver handles OS requests is explicit in the structure of the program.

a passive driver is merely a collection of functions without any indication of the order in which these functions are invoked.


The increased productivity provided by these features comes at a justi.able cost in a more sophisticated runtime system whose responsibility is to implement these features e.ciently.

the virtualization introduced by this sophistication provides a signi.cant challenge to understanding complete system performance, not found in traditionally compiled languages, such as C or C++.


Such invalidation is issued by coherence protocols for achieving multiple caches consistent.

in case of false sharing, the invalidation is not necessary hence causing performance lost.


For example, Authen-thencommit also guarantees that the secure processor only updates memory states based on authenticated code and data.

there are several fundamental di.erences between these two approaches.


It has the advantage of gathering program information through pro.ling (where DIP uses on-line execution history).


For instance, des had a high glitch power in Table II, yet we did not observe a signi.cant power reduction for this circuit.

in Table III, we see that it had only 0.8% of LUT inputs as don t-cares, thus reducing the number of opportunities for optimization.


In a recent paper [10], the lower bound on the number of required operations to implement the MCM is investigated.

the solution found by a heuristic is determined as minimum, if the number of operations in the found solution is equal to the lower bound.


Dogs have the ability to quickly traverse the terrain, squeeze into small openings and use their sensitive sense of smell to allow them to find survivors quickly.

they are unable to communicate their experiences to humans who cannot follow them.


The most simple EVX with all features disabled and a small VMSHR of 8 entries (limited-EVX) decouples memory and computation instructions and transfers multiple operands to the reservation stations in a single cycle.

it provides limited speedup over the scalar baseline for most of the kernels or even performance degradation due to VCU initialization, with the exception of ICCG, Ipred, Matrix and PiCell.


However, the continuous Vth degrada Joint modeling of interdependent degradation effects on logic networks and sleep transistors: Due to the increasing Vth of sleep transistors during active mode, the voltage level (denoted by VVdd as depicted in Figure 1) at which the logic network operates gradually decreases, therefore imposing additive performance loss.

the decrease in VVdd can be offset, to a certain extent, by the smaller current required for normal operation of the logic network due to its own degradation.


DCC uses the same number of tags as Baseline, but almost doubles the per-block metadata largely due to the back pointers.

since the data array is much larger than the tag array, Cacti calculates the overall LLC area overhead as about ~6% [9].


Similarly, the work of [8] applies a round-robin based relaxation schedule in the context of a multicore system.

these approaches would result in signi.cant NBTI-based delay degradation under conditions of heavy load (when all functional units or cores are occupied).


Some scheduling algorithms, like the iterative modulo scheduling for software pipelining [26], adopt iterative search strategies and allow earlier decisions to be adjusted later, so that they are able to work on highly constrained problems.

we are not aware of any algorithm in this category that explicitly supports soft constraints.


FBB decreases Vt, increases on-current and thus improves performance.

researchers have previously reported that the performance peaks at Vfbb 0.45V and then starts decreasing in a 130nm technology [7] .


Usually a margin is reserved to take into account any uncertainties in circuit/device parameters and environmental factors.

such a worst-case-based VDD selection overestimates the actual required VDD: the combination of worst-case conditions is rare.


For example, at Pf =10-1 , the detection probability for t-sensing is still 92%; while in this case AD-sensing and KSsensing perform better than t-sensing.

as indicated in section 1, the exact noise distribution is often unknown in real situations and AD and KS based sensing work only if the exact noise distribution is known a-priori.


A few novel resistive NVM/CMOS circuits have been designed in the last few years, including non-volatile SRAM (nvSRAM) [13], non-volatile Flip-Flop (nvFF) [14], non-volatile Full Adder (nvFA) [15] [17], non-volatile XOR/AND/OR gates [17] [19], etc.

the reported non-volatile full adders in [15], [16] and the AND/OR gates in [18], [19] only use resistive memory as one of their operands.


Depending on the processor con.guration, cost of implementation, ease/di.culty in .nding suitable tuning parameters etc, one may choose between IR and a combined scheme.

if simplicity and a single scheme is desired, exploiting load IR seems to be the best technique to reduce cache tra.c.


Therefore, prior work on test infrastructure design for core-based system-on-a-chip (SOC) has mainly focused on minimizing the test time for core-internal logic.

as feature sizes shrink for newer process technologies, the test time for interconnect signal integrity (SI) faults cannot be neglected.


As a result, they consist of identical circuits repeated in one dimension.

control circuits have less structure and, therefore, lower density.


With oblivious routing, some of the bu.ers are .lled to capacity (16 entries) and average of the maximum bu.er depth is approximately 5 entries.

the average of the maximum bu.er depth is only 3 entries with adaptive routing and the maximum value is only 7, or roughly 50% of the capacity.


Further, simple buffering can be used to replay persistent state output and input to solve the input/output commit problem.

the remaining application state corruptions (with detection latencies reaching millions of instructions) are currently infeasible for hardware recovery and will likely require software checkpointing techniques.


PGR attempts to charge VR while PDR opposes it.

pGL attempts to discharge VL while PUL opposes it.


Thus, scheduling is unnecessary in those languages.

their limited expressiveness makes modeling inconvenient in many applications.


term, but computes it for vertices rather than edges.


After all faults have been processed, the generated testcube t is added to the test set and the next primary target faultis selected until all faults are detected or proven untestable.

determining a solution for the proposed CNFformulation (representing an optimization problem rather thana decision problem) remains the bottleneck of the proposedapproach.


This behavior is largely because the amount of storage within the WDU increases linearly with the number of signals being monitored.

the DPU scales well in both area and power with an increasing number of signals being monitored because only the logic for the arbiter scales with an increasing number of signals, and this increase in logic is for the most part negligible.


However, the cycle cannot be reserved for a new column access because that would require an activation to be issued at the current cycle to open the row.

the current cycle has already been reserved for the column access to Bank 0.


Therefore, processor with higher clock frequency executes behavioral model faster than FPGA.

fPGA is more appropriate for executing simultaneous events and computation-intensive processes in parallel.


3 Motivation for Two-Step Partitioning Prior work on the identification of failing scan cells is based on random-selection partitioning, which is especially effective if the failing scan cells are uniformly distributed across a scan chain.

in practice, faults in a circuit are likely to lead to clustered failing scan cells, thereby invalidating the uniform distribution assumption implicit in random-selection partitioning.


INTRODUCTION Switched-OPAMP (SO) is a well-known solution for implementation of switched-capacitor (SC) circuits as supply voltage decreases below 1.5V [2].

to deal with lowvoltage and high-speed SO circuits, it is necessary to develop new CMFB strategies.


ORNoCC shares similar characteristics tto Snake when considering conservative values.

bbecause ORNoC does not suffer from any waveguide crossinngs, a significant improvement is obtained when considering aaggressive values Lwc Co 43.26 25.875 14.225 28.975 15.8 Arch2: Snake and ORNoC arre crossbars.


Caches have some on-line testing features like parity or ECC [4] to detect and correct errors.

parity does not have error correction capabilities, and hence, cannot deal with permanent faulty bits due to low Vcc.


Because the pull-down path is very short, the NOR-type TCAM can provide the best search performance.

it contributes a lot of drain capacitances to the ML.


The circuit slack is then computed by processing the nets in their topologically sorted order with Lillis (Q, C, W ) framework [4, 9].

looking closely at a single circuit slack computation, we can see that non-redundant assignments for a 2-pin net are independent of the RAT at its sink.


The cell non-overlapping constraint for the standard cell placement is to place all the movable cells on the given rows without overlapping each other.

our algorithm can be easily generalized to the case where we have cells of di.erent heights.


To reduce power usage, GPS is turned on adaptively rather than periodically, using accelerometer and/or cell tower change as a trigger.

the power usage remains high outdoors, where charging sockets are typically unavailable.


For example, as shown in Figure 2, a multiplexer can be expressed as a composition of a pair of AND gate, one OR gate and an inverter.

as thedesired functionalitygrows insize and complexity,hardwaredesign increasingly relies onCAD tools and higher-level hardware description languages and design patterns.


The presented scheme is different from the prior code duplication related studies such as [1, 6, 8], as we focus on an embedded chip multiprocessor and try to minimize a different metric, which captures performance, energy, and reliability.

there is still a chance that a transient error can strike during execution of an unduplicated computation, which cannot be detected by our approach.


This technique resorts to probabilistic techniques to derive BER estimates analytically (without explicit circuit simulations) by starting with appropriate probabilistic models of all random noise and interference sources of the link, and by calculating intermediate probability distributions due to the various link components to the receiver output.

the exact calculation of intermediate probabilitydistributions is not possible for arbitrary and realistic probabilistic noise models, and therefore inevitably these approaches entail many assumptions and approximations both in the noise models and the calculation of intermediate distributions.


It is also observed that the area increase by buffer sizing is very minimal, less than 0.1%.


This relaxes the requirement to .nd the exact test that causes the worst case on every sample.

searching for the tests that allow us to estimate a reliable delay bound on every sample is not trivial, so we need to begin by pruning the aggressor space.


This is particularly true since memory accesses in a program run are extremely unbalanced, causing some cache sets to be accessed heavily while others remain underutilized.

accessing a set-associative cache requires longer access time, more power, and area.


To extend it towards mobile scenarios, the network is periodically re-localized at a succession of time snapshots [13], as illustrated in Figure 1b.

this approach ignores the temporal dimension, as each node s trajectory is now viewed as a set of uncorrelated points in time.


DWM-MLC Cache Architecture The proposed DWM-MLC bit-cell has very high density, fast read/write access, and low leakage power.

the read and write energy depends on the data to be read/written into the cell.


For example, a differential pair designed symmetrically should have zero input offset voltage.

process variation can induce mismatches between the differential pair so that the op amp might have a non-zero offset voltage larger than speci.ed.


Group IBM Research Los Angeles, CA Yorktown Heights, NY East Fishkill, NY Yorktown Heights, NY jinjun@ucla.edu {zolotov,natesan,chandu}@us.ibm.com ABSTRACT In the deterministic approach, a circuit is optimized for a single combination of process parameters.

as Chips manufactured in 90 nm technology have shown large a result of manufacturing we receive chips corresponding parametric variations, and a worsening trend is predicted.


The high energy consumption of existing outof-order implementations is the result of a long period of dedicated pursuit of performance at the expense of energy consumption: speculations are applied very aggressively and the circuitry for orchestrating out-of-order execution is not designed with energy e.ciency as a priority.

the out-of-order model is not inherently more power-hungry.


Hence, keeping all the vectors of Vm in GPU global memory allows GPU to handle those operations, such as inner-product of basis vectors (dot) and vector subtraction (axpy), in parallel.

it is better to keep the Hessenberg matrix H , where intermediate results of the orthogonalization are stored, at the host side.


When the ADAMS of the Out signal of sensing ¯0 ¯0 or ¯1 ¯1 is normally slower than state is ¯0 ¯1 ( 1 ), read disturbance could happen on both P-that of sensing ¯1 ¯0 , we may be able to differentiate these two cell and N-cell.

the probability that read disturbance cases by carefully choosing the cutoff point.


A single shared-bus CTI architecture is low cost and suitable to ac-commodate a small number of banks [7].

multiple con-current charge transfers should be performed through the shared path with the same voltage, which may significantly degrade the efficiency with a large number of banks [19].


dynamic voltage and frequency scaling (DVFS) is widely used to reduce dynamic power [4], while clock/power gating techniques [5] are commonly used to reduce leakage power in cores.

implementing these techniques at a per-core granularity requires separate VDD and ground lines, as well as a prohibitively large number of VLCs (voltage level converters) and MCFIFO (multiple clock firstin-first-out) queue based frequency level converters [6][7], especially as the number of cores on a die increase.


This is because the register overhead for the desired application was found to be 33% of the clock period.

by using the proposed  Figure 6: Parallel TDF type 8-tap FIR .lter structure.


Note that a correct bypassing decision may obtained even with a mis-prediction, as long as the bypassing depth is not affected.

a correct prediction of DRC distribution may also lead to an incorrect decision of cache bypassing due to inaccurate estimation of read/write energy.


When we want to use GLD approximations of performance parameters in gate-level analyses, NLDM and NLPM seem to be principally applicable.

the characterization e.ort to minimize interpolation errors may be too large for an industrial use.


A buffer can become live many times during the schedule, and is not necessarily live for a contiguous amount of time; this could happen, for example, if the buffer is in a nested loop with three or more actors.

the pattern with which the buffer becomes live is periodic in the sense that it depends on the iteration counts of all loops that contain the actors constituting the edge of the buffer.


Henceforth, in this paper we would discuss about NF and IIP3 tuning directly.

actually we are changing the tuning knob voltages to produce these changes.


After the boosted word-line is used, the writability is enhanced.

bSW gets worse beyond 0.7V of the boosted supply because it make the bitcells more prone to half select disturb.


Finally, Figure 7shows the synthesized clock frequencyat differentdesignpoints.Hereweseea signi.canteffectfromthe more complex logic forgarbage collection:even thoughit consumes relatively little area, clock frequencyforgarbage collectionis noticeably slower (15-39%) than Malloc across all design points.

the difference between STW andRTGC is small with RTGC often faster.


This approach requires no help from off-line simulation or compiler and only relies on dynamic event counts from the PMU.

it is not flexible in the sense that frequency domains are obtained through extensive experiments of micro-benchmarks for a given performance loss (set to 10% in that work) and this performance loss is fixed for all different applications.


The hope is that grosser gestures (such as a finger swipe on a touch screen) require less hand-eye coordination than a button press.

these gestures still require a significant amount of visual attention.


On one hand, the speculation-control-sensitive workloads already have much fewer in-flight instructions than the baseline, and the reduced fetching capability does not significantly affect the overall performance.

bwaves does not need a full-capability front-end to begin with because it has a mostly idle back-end due to the memory intensity as well as the infrequent misprediction-caused pipeline flushes.


Her father described the phone as a kind of umbilical cord, that would allow her some independence while ensuring bi-directional accessibility between child and parent.

for one of our subjects, the matter of safety was a real, everyday issue because of a physical disability (S13).


For example, false negatives in [17] result in load re-execution.

a false negative causes a replay in our design, which is much more costly.


Note, Yin and He [6] analytically proved that the conventional modal decoupling technique can be extended to decouple drivers/receivers for identical 2coupled lines.

in general, drivers/receivers of ncoupled lines cannot be decoupled.


They consider application of chip-wide DVFS to manage parallel regions of applications and perform few explorations guided by heuristics to reach an optimal operating point.

our work focuses on per-core DVFS actions guided by policies that predict different power mode behaviors.


Note that our frustum tracing technique is could be seen to be related to adaptive super-sampling techniques in computer graphics such as [48, 17, 20].

recent work in interactive ray tracing (for visual rendering) has shown, that adaptive sampling  despite its natural advantages does not perform near as fast as simpler approaches that are based on ray packets and frustum techniques.


This reduces the time a node has to wait to transmit a packet and hence tends to improve the delay and capacity of the network.

it also tends to have a negative effect on delay and capacity.


The clock reference supply voltage is 1.8V in order to interface to the digital core.

thesupply can be scaled easily to 900mV because start-up is based oncurrent, not voltage, and the current source for the reference hasbeen designed to be power supply independent over a broad range.A summary of these performance parameters is given in Table III.


Let us consider a single fault group of a fault mode with M bits.

if all bits in this group are ACE, the SB-AVF and MB-AVF of this fault group in a single cycle are: M × 1 SB-AV F = = 100% 1 × M 1 MB-AV FM = = 100% = 1 × SB-AV F 1 if only one bit is ACE, then the single-and multi-bit AVFs of this group in a single cycle are: 1 × 1 100 SB-AV F = =% 1 × M M 1 MB-AV FM = = 100% = M × SB-AV F 1 Therefore, from .rst principles, we can see that the MB-AVF can vary between 1x and Mx SB-AVF, where M is the number of bits in the fault mode.


A PUF may reside anywhere in the FPGA and be unidentifiable by an adversary.

pUFs are not stable over the lifetime of an integrated circuit.


So, the length of the bottom net was extended by 6 through snaking.

snaking was not possible for the middle net, because all routing resources around its route were used during routing.


Thus, the random ATPG detects very few faults (only the ones injected into the else branch), because it is unable to uniformly traverse the whole state space.

the EFSM-based ATPG uniformly moves across all transitions of the SEFSM increasing the fault coverage.


[21] model traf.c .ow as a 3-tuple consisting of a Hurst parameter and parameters for hop distance and spatial injection distribution.

these statistical models are not a formal/conservative representation of the underlying traf.c, and designing according to such models can be misleading [12].Formal Methods: The abstraction of a latency-insensitive system [5] has been explored as a veri.cation aid.


3.3 Joint CAC and ECC A joint crosstalk avoidance and error-correction code can be obtained by combining a crosstalk avoidance code with an error-correcting code.

the coding overhead will be signi.cant as the joint code is a concatenation of the two individual codes.


Approximately a 6.5x improvement in latency and a 51x improvement in throughput are possible for the largest problem considered.

notice that even for large problems there is a large portion of unutilized resources, which could be used to extract more parallelism in the interior-point method and achieve even greater speed-ups.


Traditionally the steps of coarse-grain (e.g., task and loop) parallelization and .ne-grain (Instruction Level ILP) parallelism was done separately.

interactions between the two phases can result in many opportunities for modifying the range of performance, memory and power pro.les of the generated software.


TCG is widely used to represent a compact placement; it uses a pair of constraint graphs, Ch and Cv, to record geometric relations among modules.

hotspots may not be in a compact form because of spacing among polygons (see Fig.


In order to ensure a good coverage and, by this, a high veri.cation quality, each scenario is supposed to become su.ciently triggered.

the considered scenario may be triggered in several fashions and information about that is hardly available in the existing CDV approaches.


The functions of this transactional API are brie.y described in Table1.

dealingwith transactionalbehaviorof the application at this verylowlevel of abstraction would require extensive manual modi.cation of the source code, which is a tedious and error-prone task, hindering the ease of use of such a programming abstraction.


Since each experiment consists of only 100 executions, the intervals are larger than in Section 5.

we still have statistical con.dence that our pointer replication technique signi.cantly improves resilience of our parallel executions.


In addition, vertex 20 collects a precedent neighboring ESD connected component, ECC1, through visiting vertex 15 (lines 20 22).

vertex 20 also visits the np-vertex, vertex 11, trying to expand ECC2 and to collect more p-vertices and more precedent neighboring ESD connected components.


Finally, proposals such as decay-based replacement [26] or PIPP [27] modify the replacement policy to provide some control over allocations.

theylack strict control and guarantees over partition sizes and interference, preclude the use of a speci.c replacement policy within each partition, and are often co-designed to work with a speci.c allocation policy.


Ideal sense ampli.ers output a 0Vor 5Vas a result of the logic functions.

by deliberately mismatching the transistors in the sense ampli.er so that it has a small, Bout Dif  A B C R 4 T1=R 1+R 2+R 3 T2=R 4+R 5+R 6 D if =T1-T2 T3=R 1+R 2 T4=R 4+R 5 B out=T3-T4 0 0 0 L LLL LLL 0 LL LL 0 0 0 1 L LLH LLL 1 LH LL 1 0 1 0 L LH L LLL 1 H L LL 1 0 1 1 H LH H H LH 0 H H H L 1 1 0 0 L H LL LLL 1 LL LL 0 1 0 1 H H LH H LH 0 LH H L 0 1 1 0 H HHL HLH 0 HL HL 0 1 1 1 H HHH HLH 1 HH HL 1 BCA  Figure 4: 1-bit spintronic subtractor using MTJs and its truth table S0/D0 Figure 9: n-bit spintronic adder/subtractor using .rld-driven MTJs positive Voffset, a di.erence of zero will be considered to be negative di.erence.


The data allows the conclusion that more simulation slices lead tomore preciseheuristics.

this effect  0 10000 30000 0 10000 30000 # simulation slices (w*64) # simulation slices (w*64) Figure 4:The quality ofthe heuristicsincrease with simulation effort.


Leakage Power [W] 0.002 0.0015  A4:Combination of System Parameters Using the analysis presented in Table 4 in Section 5.1, it is now possible to estimate the impact of the three system parameters viz., capacity (C), frequency (F) and width (W), on DRAM current consumption.

when a combination of system parameters di.er between two DRAM memories, the in.uence all the concerned system parameters must be taken into account.


We will address the way to group the transistors in later sections.

unlike the concept of sections in [12], our section size can be small to provide .ne-granular adjustments to the circuit without having any impact on area overhead.


Lastly, we notice that for the very low 10%-populated crossbar, AAPack 6.0 no longer packs e.ciently requiring 27% more CLBs than AAPack 7.0.

aAPack 7.0 only runs 2.4-fold faster than AAPack 6.0 for this architecture because the sparsity of the crossbar causes AAPack 7.0 to invoke detailed rout- Table 5: Comparison of AAPack 7.0 vs AAPack 6.0 across di.erent architectures.


We measure an Instructions-per-Cycle (IPC) decrease between 1%to 12% for 3DS-HNCC L1 data caches.

l1 instruction and L2 caches in.ict almost insigni.cant performance penalty (less than 1% IPC reduction on average).


Circuit edge matching was .rst proposed in [6].

these authors did not have a router that could route the wires of the different mode circuits simultaneously.


For each inverter cell,thep:n size ratio was chosen tobe1:1because of symmetricpmos and nmostransistors.

fora3-inputNANDgate,the p:n size ratio was chosen tobe1:3,because thethreepmos transistors are connectedinparallel, whilethe3 nmostransistors are connectedin series, as shown in Figure 3.


On the other hand, there have been many works that propose hardware-based approaches to dynamically change the frequencies and potentially voltages of a VFI system driven by a dynamic workload [6][9].

due to the high latency and power overhead, there is a substantial limitation to freely exploit the bi-synchronous FIFOs.


Wireless NoC is one of the promising alternatives to alleviate the performance limitations of traditional multi-hop counterparts.

wireless interconnects with either Carbon Nanotube (CNT) based antennas or mm-wave metal antennas may encounter significant failure rates pertaining to issues of integration and transceiver design respectively.


Persistent combinational elements, such as MUXCYs and XORCYs, are represented as boxes with combinational delays specified for each input and output pair.

the logical content of the box is not provided, which prevents logical redundancies from being propagated through the box.


This criteria is similar to the typical escape routing which route each individual terminal pin to the boundary of the chips [14].

control pin sharing in pin-constrained EWOD chips makes it di.cult because EWOD chip routing exists many multiple terminal nets instead of two-terminal net in typical escape routing problem.


Figure 5: Internal redundant wire insertion for yield improvement In internal redundant wire insertion for yield improvement, it is assumed that all the inserted redundant wires in a detailed routing result are internal redundant wires.

the redundant wires of some selected L-type or U-type wires may not be successfully routed inside their original connection regions.


(2) Another advantage is accessing the BTB (to detect Branch_on_BQ instructions) and BQ in parallel, because we always examine the BQ head (Section 3.3.5).

accessing a predicate register .le requires accessing the BTB .rst, to get the branch s register index, and then accessing the predicate register .le.


VTn) (12) VDD = 1+.ß a ( -) where k is obtained through (13), -aVDD / U 1-e k = ln( ) (13) -ßVDD / U 1-e Equation (12) is a non-linear equation, it is impossible to solve it analytically.

for given a and ß, k almost remains constant when VDD is swept in the sub-threshold region (see Fig.


For instance, in H.264/AVC, there are only nine 4x4 intra candidates [25].

in HEVC [7] there are 34 candidates in intra 4x4 [18].


Unfortunately, previous mechanisms to improve processor reliability protect all processor instructions equally, causing such approaches to suffer from significant performance degradation and/or substantial hardware overhead.

recent research has shown that in multimedia applications such as photography, video, and audio, not all instructions are created equal: many operations prove to be far more tolerant to faults than others [1].


In particular, word-level decision diagram based techniques [6, 9] share this problem due to the explicit word-level feature, which makes them incapable of representing bit-level errors appearing in a gate-level netlist.

when posed in the equivalence checking setting, modern equivalence checking methodology is often capable of .nding a counterexample for inequivalence quickly, and thus providing a convenient solution to this design error problem.


In this case, we modify adder0 so that it can accept two inputs that belong to different rows.

if both inputs are the last inputs of their own rows, the size of buffer0 has to be increased.


Realizing Near-True Voltage Scaling in Variation-Sensitive L1 Caches via Fault Buffers Tayyeb Mahmood Soontae Kim tayyeb@kaist.ac.kr kims@kaist.ac.kr Department of Computer Science Korea Advanced Institute of Science & Technology Daejeon, South Korea ABSTRACT Voltage scaling can be applied to cache memories to reduce their energy consumptions.

reduced supply voltage to the cache memories increases defective SRAM cells due to process variations, which will decrease their yields and performance nullifying the bene.ts of voltage scaling.


For this purpose, today s microprocessors incorporate a multitude of sophisticated micro-architectural features, such as multiple instruction issue, dynamic scheduling, out-of-order execution, speculative execution, and dynamic branch prediction.

in order to sustain performance growth, future superscalar microprocessors must rely on even more complex architectural innovations.


[7] transform voltage assignment problem into a convex cost network .owproblem,andintegrateitinto.oorplanning stage.

their approach consider neither level-shifters area overhead nor level-shifters positions.


INTEGRATION OF GATED CLOCK TREE INTO INCREMENTAL PLACEMENT As we introduced the motivation in Section 1.2, previous works only construct and optimize the gated clock tree topology, the gates are always inserted after the placement.

they do not consider and discuss the suitability of the gates positions, since the optimal gates positions may have already been occupied by other cells or it will incur a lot of overlaps.


Adaptivevoltage scaling (AVS) after manufacturing testing is another optionto mitigate yield loss [9].

employing multiple voltagedomains on a chip to mitigate WID variations (such as core-to-coreFmax and Pleak variations in multicore processors) is verychallenging in practice due to the increased cost of 1) design,verification, and testing time [10] as well as 2) voltage regulatorsand decoupling capacitors [11].


We remark that AvgRE, REStDev and CC are evaluated on the entire set of data collected in .M, hence, they represent global measures of in-sample accuracy.

the RMSRE has been separately evaluated for each bench- mark, to represent the accuracy that a designer may obtain from the models when they are used to estimate the power consumption of a given controller under different workload conditions.


As a result, the magnitude of Vth variation arising from channel length uncertainty rapidly falls off as Vdd reduces.

since on current (Ion) at low voltages becomes more sensitive to Vth .uctuations (exponentially dependent in subthreshold), the net result is that Ion variation due to DIBL remains roughly constant or slightly increases.


5.7% 1,735.9% Tx/trans (rel) 7.6% 1,301.9% As a sanity check, we can compare this implementation with a callby-value implementation as used by more wide-spread compilers; Ocaml v3.10 computes fib(36) on the same CPU in 0.6 seconds, substantially better than Algol60 and Marst.

the overall throughput of the FPGA remains higher.


RTL Power Optimization with Gate-level Accuracy Qi Wang Sumit Roy  Cadence Design Systems, Inc   Calypto Design Systems, Inc 555 River Oaks Parkway, San Jose 95125 2903  Bunker Hill Lane, Suite 208, SantaClara 95054 qwang@cadence.com    sroy@calypto.com ABSTRACT Traditional RTL power optimization techniques commit transformations at the RTL based on the estimation of area, delay and power.

because of inadequate power and delay information, the power optimization transformations applied at the RTL may cause unexpected results after synthesis, such as worsened delay or increased power dissipation.


Available IP s range from soft blocks, where in general a RT level netlist is available, to hard blocks where everything is .xed up to mask design.

one has to make the SoCs Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.


As we explained in Section 5.1, in case of the PV level 0, all sevenschemes show 100% yield results.

in case of the PVlevel 1, base schemes show significantly low yield results sinceeven only one faulty SRAM cell in the L2 cache leads to the yieldloss.


PROBLEM DEFINITION DSP applications are usually considered as being dominated by arithmetic or datapath computations.

a careful analysis of various DSP benchmarks indicates the presence of other types of computations too, e.g bit-level manipulations or small pieces of random logic.


In order to maintain high circuit performance, the threshold voltage must be scaled down along with the power supply voltage.

it has been shown that for a minimum size NMOS transistor in a0.25µm technology, lowering the threshold voltage from 0.5V to 0.3V multiplies the o.-current of the transistors by a factor of 170 [1].


However if all the available memories are all of the same type then the optimisation freedom of the tool is signi.cantly reduced.

if some heterogeneity already exists in the architecture then the tools can use this freedom for optimisation.


This method lacks modularity and does not allow concurrent charge transfers.

architectures using more than one inductor are a promising approach, see [1, 23].


The data fetched from a DRAM will besent to the corresponding L2 array.

if the L2-tomemory-controller queue is full, the L2 array cannot processthe current DRAM output.


In PCA, linear variable transformations are used to identify transformed variables corresponding to the largest data variance, or principal components.

pCA tries to reduce the dimension of a statistical data set by merely examining the statistical property of the data while neglecting the interaction inter-dependency between data sets.


Despite the success of this technique, the obvious drawback is the substantial amount of processing time.

the IMEP process can be easily implemented as a distributed algorithm since the fitness evaluation of a population of candidate solutions can be performed independently.


In the past, when area and performance are the major design concerns, scan chain ordering techniques were proposed to reduce the total or average scan chain length [1, 6, 2, 10] so that routability and timing constraints are satis.ed.

as IC complexity multiplies, test power management has become the focus of recently reported scan chain ordering techniques.


Assigning individual bias control to each gate leads to severe overhead, rendering the method impractical.

assigning a single bias control to all gates in the circuit prevents the method from compensating for intra-die variation and greatly reduces its effectiveness.


= 2 Av ·Co1 Based on (1), the -3dB bandwidth of the amplifier is improved by Av times compared to the single-stage counterpart by assuming both amplifiers have the same transconductances.

for achieving the phase margin of 45°, .2 should be equal to Av·.-3dB.


Since changes in mobility directly influence the drive current, higher carrier mobility improves transistor performance.

increased mobility not only improves the drain current in the saturation regime of MOSFET operation, but it also increases the subthreshold leakage current.


an optimal amount of SRAM by periodically dumping the We see no reason why simple counter management logic largest counter in SRAM to DRAM.

cannot be deployed (either as a stand-alone chip with inter- it is di.cult to implement LCF at high speeds faces to external DRAM or within a forwarding processor) because of the need to have logic that selects the largest using our LR(b) algorithm.Given that SRAM contributes a SRAM counter to evict.


In 0.13µm technology the maximum clock frequency can reach 80MHz and 200MHz.

without the introduction of a more complex memory hierarchy (i.e.


Therefore, we suggest supporting delayed writebacks in local checkpointing.

simply adding delayed writebacks to Global is not good enough.


[4] claims that the number of distinct capacitive values is small when the distance between buffer insertion locations is uniform and the slew rate bound is tight.

we observe that this number is not that small for large testcases.


However, the minimum output voltage is limited to V = V + 2 ·V , being Von the amount of VGS (out ) min T on that exceeds VT. Obviously, Vout(min) can be reduced with the increase of the transistors aspect ratios and gate-source voltage adjustment.

using TSTs, we can obtain a small minimum excursion with less silicon area.


On a typical tablet, users have at their disposal the pen s pressure on the tablet surface to control one of these extra parameters.

this only allows the control of one extra parameter, and pen pressure may not be the ideal control for many of these parameters.


These requirements make such a system unsuitable for impromptu interactions.

surfaceLink uses lightweight inertial and acoustic sensing to detect devices and enable user-interaction.


Most of the missed lines are evicted early, before 16 accesses, with only 3% evicted after that.

the total occupancy of the latter lines is as high as 16%, whereas for early evicted lines, it is only 8%.


We observe that triple-Vth reduces leakage with respect to dual-Vth (without biasing) by ~ 8% on average.

when biasing is available, dual-Vth can yield reductions comparable to triple-Vth that involves higher process costs.


Therefore, only the local evaluation of the locality based on metric Dat each time is suf.cient to control the cache in this case.

in the case of the SPECint95 benchmarks with highly irregular and time-variant behavior of the locality as shown in Figure 2, more bits can provide more appropriate cache con.gurations in terms of performance/resource-usage.


Our approach reduces energy consumption by increasing disk idle periods.

considering only energy consumption alone may not be a wise choice since performance of the application is also important and affected signi.cantly by the disk layouts chosen for its arrays.


Thanks to the reduced feature size, SoC performances are extremely enhanced.

due to the highly stressed production process, phenomena like metal migration or aging of the circuit may increase the occurrence of permanent faults.


This is mainly because the 3 ns skew constraint reserves more feasible solutions during clock network construction, which helps to obtain a low energy clock network.

using relaxed skew bound of 10 ns cannot hold this bene.t, since it allows larger clock skew thus requires more buffers for tighter slew to reach a similar Fmax as 1 ns or 3 ns skew bound.


In addition, the cell delay and output slew increase linearly with inverse of power-switch size.

since the rise transition delay is the charging time for output capacitance, the influence from the virtual ground length and power-switch size is not significant.


If the packet has been determined to be a control packet, it will not proceed further than the MAC layer, and will be acted upon immediately, for instance to send an ACK, CTS, or any other packet needed for the current protocol in use.

if the packet is for the running application, it will be sent straight through the MAC and control layers to the application.


The effects of these irregular shapes tend to average out for large FETs.


Using these then to (somehow) switch the PPV waveforms suitably during the new variables, (16) can be written as simulation.

this approach is ad-hoc; we prefer a more structured approach that provides a concrete nonlinear differential equation as the macromodel.


The veri.cation procedure is implemented in C. On the computer described above, 115 of the circuit veri.cations each took only a fraction of a CPU second.

the larger circuits take signi.cantly longer, e.g.


This is due to the fact that the no-refresh/LRU scheme tracks the retention time for each cache line, but does not include any special refresh or replacement policy.

no-refresh/LRU scheme has the least hardware overhead and control mechanism among the three schemes.


Moreover, the area demand of P/G TSVs, which can lead to routing congestion, should also be taken into account.

there is a potential con.ict between IR-drop and area demand: using bigger and more P/G TSVs can reduce the IR-drop at the expense of an increased area demand, i.e., increased routing complexity and the possibility of routing congestion.


Sampling reduces code and data overhead, and the sampling rate can be reduced to minimize performance overhead at the expense of accuracy.

interrupting is intrusive and can cause problems in realtime systems.


For the multi-bit routing architecture, electrically, it is also sufficient to place only one isolation buffer for every multi-bit logic block position that a routing track passes.

this topology gives the multi-bit routing architecture an unfair area advantage since it needs only half of the isolation buffers as compared with an equivalent conventional architecture.


The Moore law has long been su.cient to keep a reasonable equilibrium between the available processing power and the physical link throughput.

this is no longer the case with transmission throughput in the order of 10 Gb/s when ciphering is required.


As the three properties required in Section IV-A are satis.ed, theoretically speaking, it can be solved using the similar way.

due to the complexity of color information added on each node, if the original algorithm is straightforward applied, the computational cost would be much higher.


The scattering characteristics of a cylindrical shell with a hemi-spherical cap on one end are calculated by BEM and Finite Element Method considering the coupling effect between the elastic shells and the interior filler [2].

due to the different sizes of the scattering surfaces and the different directions of arrival, the installation position of the vector sensor has a great influence on the measurement results.


For NE symmetry, symmetric pair is an equivalence relation.

this is not true for equivalence (E) symmetry.


Admitting arbitrary functions makes the full power of the language available for writing predicates.

predicates may have e.ects: they may not terminate, they may crash, or they may just be overly strict.


Typically, such failures are detected only while performing extensive pass/fail checks on the circuit after most of the timing closure is achieved.

at this stage, it is often too late to revise circuit topology or architecture in order to improve circuit reliability.


Test results obtained from the differential equation and the fifth order elliptical filter benchmarks are not surprising and are consistent with the results obtained from the illustrative example used in the initial problem formulation.

the degree of improvement in the execution time is primarily dependent on the amount of available hardware resources.


FPGAs provide signi.cant advantages over ASIC in terms of turn-around-time, .exibility, testability and suitability for debugging.

for a given technology ASIC provides over 12 times higher speed, almost 50 times higher density, and more than 500 times lower power per gate [18].


In the proposed protocol, we consider the source-destination link as the preferred transmission link.

l relay nodes are used to handle the transmission whenever the direct link is in severe conditions.


The sink group B and the related standard cells have heavy connections to the bottom macro block.

the two bottom Manhattan rings encourage the sinks in B to move away from the center of B, which will likely increase signalnet wirelength signi.cantly.


In this section, we illustrate how we have applied the idea of macro-modeling to embedded software.

the approach in the case of hardware is quite similar.


Schemes which work at instruction level have low error detection latencies, especially those which operate at hardware level.

schemes which work at process and virtual machine level allow error to propagate before detecting it.


The above problem requires all decisions to be made prior to the actual realization of the uncertain parameters.

in many real-life cases not all the decisions can be made simultaneously: only some variables may become known earlier.


Wn Wp Cin TRL_WC 4.3 8.0 4.73 TRL_A1 2.3 3.7 2.31 TRL_A2 1.8 3.1 1.88 As expected, the use of larger transistors does not guarantee a better result on delay propagation in the ring oscillator (i.e., minimum oscillating period) due to the increase in input capacitances observed in each stage.

power dissipation always increases with the transistor width.


A cache miss may increase the path length from source to the primary replica, and in the worst case the path would be stretched by a factor of 3.

the maximum path length, even in case of cache miss, from a source to the primary replica is still bounded by the network diameter.


Differently, pure software simulation tools [4] use trace driven simulators to obtain a steady state performance analysis of the device.

they often overlook the macroscopic performance implications of key component parameters or subtle microarchitecture-level effects.


A configurable logic block (CLB) has N basic logic elements (BLEs), with each BLE being a K-input LUT and a FF.

unlike VPR, we assume no bandwidth constraint for the input interconnect block (IIB) [12].


At the same, leakage currents decrease linearly.

this reduc tion in leakage current leads to an exponential increase in circuit latency, and ultimately an exponential increase in leakage (static) energy.


Therefore, the initial processor architecture is rich enough to handle function calls and large programs without imposing high overhead.

in ASIP, datapath and controller cannot be customized for an application beyond a certain point.


The CPA attack results for the threshold in [10], [12] on FPGA are not Un p r ot ec t e d s i n g l e- Unp r ot e c t ed available due to some mismatching in modesbetween the ASIC core and the available FPGA experiment system.

the threshold implementation should be considered safe given the attack results of [12].


Typically, a ranges from 0.05 to 0.4, The rationale of changing wuv is that when PDuv is small, i.e., PDuv = PDth, it is a good metric for .nding .ip-.ops for merging.

if it becomes large, i.e., PDuv > PDth, it implies that distant .ip-.ops are clusteredtogether, and from this point, considering LDuv along with PDuv is more effective in .nding .ip-.ops for merging.


2.5 Performance/Energy Overhead The proposed approach allows us to eliminate all tag checks in the Omode.

accessing the execution footprints produces an energy overhead for the BTB.


Figure 4.2 shows that my prototype implementation approximately achieves the line rate at every frame size.

linux cannot achieve the line rate under the frame size of 324.


A single channel multiplexes all external channels, reducing the buffer area and energy consumption.

mago reduces the NoC parallelism, increasing the overall latency.


Hence, PMC is a good candidate for the next generation of non-volatile memories.

simulation tools that are compatible with CMOS based design environments (such as HSPICE) are needed to integrate a PMC into an IC.


An allocation request from another thread mapping to this set must allocate the block in a small processor owned private (POP) cache partition of the last-level cache.

an adaptive setownership hand-over policy makes sure that a thread does not unnecessarily hold a set for too long when other threads are continuously missing on this set.


Based on the nonlinear characteristics, some battery-aware task scheduling methods have been proposed to improve the battery runtime, such as [5] [6].

in the mobile or embedded application, the amount of concurrent tasks is relatively small.


LOOP: This scheme uses the same .xed layout for each array as in the case of the BASE and HW schemes.

it restructures code to increase disk idle periods.


For Vth s s/µ, the 1999 ITRS [17] gave a design target of 0.06 for year 2006 (although no solution existed); however, the projection has since been discontinued.

kahng [19, 20] reckons that the ITRS variability projections (for at least the gate-length parameter that he examines) are too optimistic.


At forty cycles, the average performance penalty from checking is 17%.

the scientific workloads suffer from increased reorder buffer occupancy because they can saturate this resource, which decreases MLP.


If 4s of 16.67mV is selected for the threshold voltage, we will not misjudge the defect-free circuits as the defect circuits.

most of background leakage current (mA) defect circuits with defect currents below 30µA will escape from this test.


For example, it is no longer required that the number of sampling points is equal to or greater than the number of model coefficients.

sTAR can estimate a large number of (e.g., 103~105) model coefficients from a small set of (e.g., 102~103) sampling points without over-fitting.


In addition, it was found that using the force/moment direction sensor method reduced teaching time significantly compared to the conventional teaching pendant method [4, 6] (The force/moment direction sensor is similar to the force/torque sensor).


P0 P1 P2 P3 P4 PG0 012 345 678 91011 121314 PG1 048 3711 61014 913 2 1215 PG2 0714 310 2 613 5 918 12411 PG3 010 5 313 8 6111 9414 1272 PG4 01311 3114 642 975 1210 8 Table 1: 15-input XOR network construction (S = 3, B = 5) The attainment of a lower compression ratio thus requires a smaller value of S. A smaller value of S also implies that the network needs fewer numbers of XOR gates, which in turn reduces the hardware and performance cost of the network.

a smaller value of S degrades the randomness of the network, as the network construction approach delivers a bit overlap ratio of 1/S.


Due to the recon.gurability of DRFPGAs, the placement of digital micro.uidic biochips is similar to the simultaneous scheduling and placement of DRFPGAs.

the placement of biochips is more complicated than that of DRFPGAs for two reasons.


Adding tracks to each channel allows more critical signals to take shorter paths, at least until the critical signals all utilize the least delay routes.

it is not uncommon for VPR to produce graphs like Figure 3 where the delay descent is not monotonic in channel width.


Furthermore, as the temperature is lowered, the decreased values of r0 and r in (18) give extra room for further reduction in the power for a given allowed delay penalty by increasing l and/or decreasing s. Note that since the reduced repeater power also results in a decrease in the power consumed by the logic blocks, the optimal values of l and s that minimize the repeater power also leads to the largest leakage power reduction from the logic blocks.

as mentioned in Section 2.3, there is a possibility that the steady-state temperature is not reached due to thermal runaway, which can further restrict the solution space of l and s in addition to the delay constraint.


The output slew rate of the CMOS bu.er depends on both the input slew and the load capacitance [19].From Equations (1) and (2), the e.ective load capacitance seen by the bu.er output depends on the slew at the bu.er output.This factor introduces a chicken-egg problem which is addressed in [19] using an iterative delay evaluation technique.

3.2 Backward propagation of slew In order to consider the node slews during the clock tree synthesis, we need to calculate the signal slew rate during the bottom-up topology generation phase of the DME [8, 17] algorithm.by de.nition, the slew rate at a child node can be calculated only when the slew rate at theparent nodeisknown.Forexample, in Figure(3), the slew rate at node a can be obtained only when the slew rate at node v is known.An e.cient method for obtaining the transition times at the nodes of the clock tree for a given transition time at the source node has been proposed in [19].