Note that this level of information can allow us to perform detailed optimizations which could not be possible underthe coarse grainimplementation.Forexample, bykeepingharmful prefetch andcachemissinformation ata client pair granularity, we can throttle I/O prefetches from a clientonlyif suchprefetcheswilldiscardthedataofa certain other client or set of clients, and let the remaining prefetches it issues go through.

it can be possible to tunethebehaviorof eachclient asfar asI/Oprefetchingis concerned with respect to the behavior of every other client individually.


This paper presents the exploration of different con.gurations of a double gate fully depleted SOI based FinFETs for ef.cient design of current mirror designs.

comparison among the important Figures-of-Merit (FoMs) current mirror designs including mismatch, variability, output resistance (r0), compliance voltage (VCV ) is presented for: (1) shorted-gate (SG), (2) independent-gate (IG), and (3) low-power (LP) con.gurations.


However, the most promising role for this data is in applications targeting health and fitness.

prior work has shown that wearable sensors can benefit individual patient health [1], individual personal fitness [16], and epidemiology studies to assess the large scale activity of populations [13].


The mutation operator, applied with a probability PM , has been implemented to change the various .elds composing each gene.

it may change the mapping and the frequency/voltage level of a nominal task,  the number of replicas to be inserted for a task, and  the mapping and the frequency/voltage level of each  replica of a task.


Such a potential to move is determined by not only the delay sensitivity of the net it drives, but also the criticality of the net and the cell itself.

how sensitive the timing is subject to the net change and how logically close a cell is to the critical paths.


Signals produced by a relatively slowly-varying linear filtering process are most suitable for LPC, especially, if the filter is excited by infrequent, brief pulses.

[2] a signal s spectral magnitude, as opposed to phase, is widely used (e.g., in human perception, it is more important to model the magnitude of speech spectra accurately than their phase).


4.1 Delay noise from skew window It has been shown in [15] that regardless of the aggressor transition, the worst-case delay noise occurs when the victim input transition occurs at the latest point in its timing window.

adding the worst-case delay noise to the late victim input arrival time will result in the maximum slowdown (increase in the victim output timing window).


Each combinationallibrary cellhas3 threshold voltage(Vt)levels and 10 sizes for each Vt level.

there are 30 different library cells that implement the same combinational logic function.


As mentioned earlier in this paper, we use equal weight columns as in X-Compact.

every column of the parity check matrix should have the same odd number of ones and no two columns are the same.


Architecture speci.c faults are usually more e.cient in targeting the correct diagnosis and structural test of a circuit.

recently, architecture speci.c faults have been presented for the architecture of this work in [2] and [5], where mismatch between current sources of a CS-DAC has been the main fault model.


In [1] both approaches are implemented to increase the yield of an adder structure.

static reconfiguration is achieved by the use of laser fuses for disconnecting defective bit slices and connecting spare ones.


a fixed graph is first trans- formed into a circuit and then fitted to the hardware before queries about it may be answered.


m[j]will be cache miss when the number of con.icting blocks and the locked blocks together exceeds the associativity of the cache.

m[j]will be cache miss when |Locki .TCSm[j]|=A.


Focusing on an wire , the objective can be considered as the sum of two parts: a function of the variable associated with  and terms independent of those parameters.

, in which  depends on the repeater solution of  but other terms (o.t.)


To this end, we examine a variety of fragment construction policies, their possible benefits and drawbacks.

we study and evaluate some of the design decisions that were made within Strata [14], a publicly available, retargetable SDT system supporting three instruction sets: IA-32, SPARC, and MIPS.


we look for a truth assignment to variables xa and xb that satis.es .C and makes the miter constraint .= .A .fc .gc .


Because of the blockages and the boundary restriction in the micro.uidic array, it is hard to directly apply the three rules to the ILP formulations in the cell set C. For example, if a droplet di stalls at the location (0,0) within time t - 1 to t in Figure 2 (a), due to the boundary restriction of micro.uidic array, the exact number of must-be-deactivated cells is 3 instead of 8.

we may need extra constraints and variables to determine the exact number in EC-Rule II, which signi.cantly increases the complexities of the ILP formulations.


CAD tools have enabled designers to manipulate a huge number of transistors on a single die and in a shorten time-to-market.

logic synthesis tools have contributed significantly to reduce the design cycle time.


Associated with each core, there is a locality & utility monitor that dynamically pro.les both NRU and BNRU hit curves from the core s SLLC reference sequence.

the NRU and the BNRU hit curves are captured by an LRU pro.ler and a BNRU pro.ler respectively, both of which are based on auxiliary tag directories (ATD) and the set sampling technique [10].


[5], the bounds derived in Theorem 1 can be used to determine the maximal delay of events and the necessary memory to store packets waiting to be processed.

the following two equations give bounds on both quantities: delayc = sup inf{t= 0: au c (u)= ßl c(u +t)} (7) u=0 {} backlogc = sup{au c (u)- ßl c(u)} (8) u=0 the delay can be bounded by the maximal horizontal distance between the curves au and ßl , whereas the backlog is bounded by the maximal vertical distance between them.


The delay overhead is also limited w.r.t to the balloon-based scheme.

our implementations present a reduction of the delay overhead up to 8.6%, 3.4% and 6.5% for propagation delay, rise and fall times, respectively.


A coalescing operation is optionally conducted to coalesce continuous free blocks.

the dynamic stack allocator implements two functions, alloc and dealloc.


We should try to keep the congestion with newly generated directives similar to that without any directives.

the congestion constraint to the LDA problem can be gLDA = ßgorg , where gLDA and gorg are calculated by a congestion metric of the routing solution with and without assigned directives, respectively, and ß is a user-de.ned parameter.


However, the fact that the effectiveness of [11] relies on HT implementation style enables the simple attack.

it is fairly easy to modify the implementation of the HT so that no signal pairs are equal to each other during veri.cation (an example is given in Section 3.2), which has been shown in [12, 13].


Technical Approach 2.1 Overview In the following approach, we consider a design space that is obtained by varying caches depth D and the degree of associativity A. Cache depth D gives the number of rows in the cache.

log2(D) gives the bit-width of the index portion of the memory address.


This paper elaborates on this challenge and summarizes our ideas and contributions towards a solution, as presented in a hot-topic special session at DATE-2012.

we present several key approaches and tools: the StarPU runtime system, based on performance-aware dynamic scheduling and selection of task variants to automatically run on the most suitable type of execution unit in the context of heterogeneous systems, combined with the SkePU skeleton programming library as front-end to provide abstraction and more parallelism (Section II);  the Of.oad-C++ language, an extension of C++ for highlevel portable programming of accelerator-based systems, and its compiler to OpenCL (Section III);  the PEPPHER component model and methodology to achieve performance portability for applications based on annotated software components that expose their implementation variants, performance-relevant metadata and tunable parameters in an extended composition interface (Section IV).


CSCL does not provide any mechanism to handle communications between nodes.

sockets that were used by a checkpointed process are not re-opened after a restart.


This requires that no two units within a redundancy group are mapped to the same disk.

for a redundancy group a, disk(a, i) .. = disk(a, j)for 0 = i = j = k -1.


Even though we provided a recursive de.nition to the order of evaluation, the evaluation procedure itself need not be recursive and has a simple .ow-chart form.

there is no need to maintain extra state as in a recursive evaluation.


For example, assuming reports of 10 32-bit resource features per second, a large provider like Amazon (say 100K instances) would have at least an overhead 10 * 32 * 100K 32 Mbps of outbound traf.c to send these reports (ignoring metadata and cryptography).

to reduce this bandwidth cost, we envision an aggregation step that processes the log entries before generating R. given the attested reports across multiple time epochs, a trusted aggregator generates a statistical summary of the resource consumption vector across time.


Thoughfor simplicity we currently requirethatOTsbephysically contiguous,theycan themselves be paged, albeit as a single unit.

it makes sense for the OS to swap out the OTs of descheduled threads.


x[14] X[7] X[15] x[n+3N/4] j W 3n N Instead of the row-wise parallelization in pipelined FFTs, it is also possible to parallelize along a column of the SFG as shown in Figure 2(a).

n/r butter.ies are instantiated to compute one stage (i.e.


Analytical models from Section 2 are employed in this part.

the number of PMOS transistors computed from the synthesis in Stage#1 is used to represent the circuit as a bare collection of (PMOS) transistors; this matrix representation is initialized with default threshold voltage values according to the reference technology node and according to process variation parameters (see Section 5 for more details on this).


In the original TPS a simple glitch .ltering approach is followed.

if a rising transition appears close enough to a falling transition in a tagged waveform, they will both be removed from computations.


Since we restrict ourselves to only consider the candidate gates in an extracted subcircuit, we need to ensure that no critical path will emerge outside this subcircuit within an iteration.

we need to ensure the most suitable critical subcircuit is extracted for consideration at each iteration.


In contrast, since their other characteristics such as characteristic impedances or characteristic admittances are completely different, the modal parameters are temporarily represented with the other systemcharacteristic values rather than the propagation speeds, maintaining their physical system characteristics.

the transmission line system is represented with other ** transmission line characteristic parameters, [], L R [], ***1 C - []R .


[17] have provided evidence suggesting that it is possible to tune the recti.cation or current-voltage asymmetry either by changing the end group of the molecular device or by changing the actual metal contact [7].

the asymmetry observed in the molecular current-voltage characteristics may be caused by the di.erences in the metal-molecule coupling at the two contacts.


There are two critical cycles that determine the cycle time twchb (the time between the generation of two successive tokens) of the pipeline [3].

3teval + tprech + 2tCD , if teval = tprech twchb = 2teval + 2tprech + 2tCD , if teval < tprech where teval is the evaluation time, tprech is the precharge time through the PMOS pull-up network, and tCD is the output completion detection time.


Our procedure for computing  proceeds by iterative local re.nement.

we iteratively computes the repeater locations and sizes that locally minimize  until we cannot make further improvement.


Overall, STT-MRAM is regarded as the most promising and capable eNVM for providing a unified eNVM solution for emerging mobile products.

when a mobile system has a low duty cycle, the values of embedded STT-MRAM can be maximized by replacing eFlash, OTP, retention flip-flop, and SRAM simultaneously, delivering the eNVM-only memory configuration.


If the path constraint con.icts with an antecedent A ' of the property being checked, the corresponding path program will also be at con.ict with antecedent A ' .

a ' is always false on the path program, which implies that the property will be true on this path program since our property is in the form of G(A ' * X =tB ' ).


CONCLUSION AND ONGOING WORK In this paper, we study the problem of technology migration for designs with strong RET-driven layout restrictions.

we present the VLSI artwork legalization problem with on-pitch constraints for devices.


; obtain addressing result by solving MCMF network; for each net in addressing result do route the net; if failure route then reroute or drop this addressing result; else update pin assignment; end end escape route for all nets; return pin assignment result and routing solution; end The main idea in our addressing and routing algorithm is we discussed in Section 4.1.

we construct Gvcc 357 problems corresponding to a pin-electrode merging.


Because of this, it makes sense to work with VBS rather than PBS (physical bank space).

we can write our compiler-based optimization strategy only once (using the VBS as the reference point), and when we want to port it to other architectures (with different physical bank structures), we only need to change the virtual bank-to-physical bank mapping.


We also assume that there is no variation in the initial resistance or resistance degradation rate of the cells in a cross-point array.


For example, for a bandwidth allocation change from 5% to 10%, swim receives a bigger boost in performance than applu.

the slope of the performance vs. bandwidth allocation curve for swim is greater than that for applu in the 5-10% operating region.


This is mainly true if the activation of all the gates within the circuit is in.uenced by the inserted sleep transistors.

when the circuit changes from the stand-by mode to the active mode, a penalty in delay corresponding to the sleep transistors re-activation times must be payed.


Based on these de.nitions, and once the algorithm identi.es the number of CPs as well as the number of FPs, the process is very simple: for each switch the algorithm checks if the number of connected ports minus the number of failed ports is more than one (line 15).

the algorithm checks if the switch has more than one alive output port.


Likewise, rerouting .it-2 would not alter its route.

the solution gets stuck at Figure 2(a) even though a better solution (b), where two links are shared, exists.


While the concept of multicore processors goes counter to the traditional approach of increased integration and faster processing through block size scaling, the interconnection complexity of each single core is considerably less than that of a flat design.

this reduced complexity manifests itself in a lower incidence of long wires that require extensive buffering.


Given a task schedule s and an allocation map F, we shall load each FPGA con.guration context with its PE in time.

f(ti ) should be loaded to one FPGA con.guration context before the execution of a task ti.


The wire congestion of layer 1 between via v and the viatothe left of v is denoted by densityl(v).

densityl(v) is the number of wires of layer 1 between them over the distance between them.


We invoke additional semantic web lookup services such as dbpedia and freebase, or foursquare and geonames in order to enrich the descriptions of the 1 http://linkedevents.org/ontology/  Table 1: Number of event/agent/location and photo/user descriptions in the dataset published in [14] In this paper, we consider a subset of this events dataset that corresponds to the intersection of Last.fm, Flickr and YouTube.

we consider the set of last.fm events for which there is at least one photo and one video shared respectively on Flickr and YouTube that has been tagged with the lastfm:event=xxx machine tag.


We have to ensure that the node uses no more than energy ED during the next day.

we have to take into account a worst case situation where all energy used to drive t1 and t2 has to traverse the battery with conversion e.ciency .. We can write N22-1 N22-1 e1 ·L2 · r1(t + i)+ e2 ·L2 · r2(t + i)= .


While filtering has been quite effective in preventing costly analysis for a large number of transform instances, the filtering efficiency is still quite low.

a large number of instances go past the filter but detailed analysis still weeds them out.


Therefore, in order to gain energy ef.ciency, designers must take into account the a difference before estimating the average Vmin.

for the purposes of optimizing DVS, low activ ity and large logic depths are interchangeable as they both lead more quickly to leakage dominated designs.


1.3 Paper Goals and Organization The remainder of this paper focuses on the architectural design choices to enable the SD-MUXes, the supporting CAD toolflow, and the experimental evaluation thereof.

it is of great importance to ensure than the introduction of SD-MUXes does not significantly impair the performance of industrial-scale circuits that do not use the dynamic multiplexing functionality; fortunately, no adverse affects were observed in our experiments.


Each storage block should have dimensions in such a way that Assuming that P denotes the total number of processor its size, SIZEm (given as input), will .t into the allocated cores, M the total number of storage blocks, (CX ,CY ,CZ ) space.

sIZEm =width × height: the dimensions of the chip, (PX ,PY ) the dimensions of the processor core, our approach uses 0-1 variables to specify the CX CY coordinates of each storage block and processor core.


A complementary technique used to address this is spatial interleaving [12] using column muxing, shown in Figure 9.

for an N bit wide memory, the physical memory core is constructed as some multiple of N bits, say 4.


Below, we sketch an illustrative proof for both stability and zero tracking error in one example scenario.

we consider the case where the power efficiency (EC) and the power capping (SM) controllers are nested as shown in Figure 2, and prove the following two results: (i) The EC controller can make the CPU utilization track a specified utilization target by dynamically tuning the clock frequency, in spite of slow changes in the workload demand; (ii) The SM controller can make the server power consumption track a given local power cap, possibly set by the upper layer controllers such as the EM or the GM, by dynamically tuning the utilization target fed into the EC controller.


We now show that the escape routing problem transformed into a SAT problem of the form can be F =FGFEFP FS =1 (2) where G, E, P , and S are the sets of all grid nodes, edges, pin nodes, and slot nodes, respectively.

we are looking for a variable assignment to simultaneously satisfy the 2) Construct FE: For each edge e, either the edge variable is equal to 0, or the two nodes connected by e are equal.


{0,1} (1) denotes the outcome of s |= f,(i.e., model checking f on s).


INTRODUCTION Information Technology (IT) industries have greatly advanced over the past few years.

as the Internet is being rapidly and widely distributed, user created contents (UCCs), which users actively participate in making and sharing multimedia Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.


However, in presence of multiple loops, we also have to account for the paths from other loops to loop Li.

if there is a path from entry node rj of some loop Lj to ri, then entry ri also re-appears after Nj.


To sidestep this problem, we will represent the graph as its adjacency matrix in hardware--described in the next section.

the second comment on the direct construction is that it does not correctly handle the case of a vertex reaching it- sell this construction will indicate that a source vertex vl always reaches itself (through a zero length path) even if no proper path exists.


The minimal as well as the minimal at which the desired performance is achieved is increased.

the minimal power consumption increases for a .xed resolution and signal bandwidth.


It is shown that our model agrees very well with ViDES results and has improved accuracy as compared to 0.05 0 the model in [15].

the proposed model gives a more realistic Ion/Ioff ratio than the model in [15] (e.g.


The design flow is general, and it is illustrated for the case of applications embed-ding CMOS sensors.

applications based on finger- print recognition are considered since a rich variety of sensors and data processing algorithms can be considered.


Although G9 is a tree leaf, we are actually only interested in G9 s output a.Therefore, we let a as the tree leaf.

the tree leaves are the inputs of the trees.


As tongue-based interaction enables hands-free use we believe that it also offers potential for other user groups.

for situations where users cannot use their hands while interacting with the computer, be it while doing maintenance at machines [3], but also while being in a very crowed metro, riding a motorbike or during surgical operations.


Intuitively, c1 is more preferred because it implements more logic.

the cost of c1 should be conversely proportional with its node coverage number.


However, none of the existing methods of energy-delay (E-D) space exploration) considers algorithmic modifications as a tuning variable to facilitate VOS.

complexity reduction through modification of values, number and bitwidth of coefficients are generally considered as efficient design variables that can lead to substantial improvements in throughput and power [5].


di Automatica e Informatica Politecnico di Torino Torino, ITALY 10129  ABSTRACT The e.ects of temperature on delay depend on several parameters, such as cell size, load, supply voltage, and threshold voltage.

variations in Vth can yield a temperature inversion e.ect causing a decreases of cell delay as temperature increases.


The second is maintaining a consistent order of realizing any two circuits that share routers relative to each other in all the shared routers.

for any two circuits, C1 and C2, that share a sub-path, p, either C1 is realized before C2 in all the ports on p, or C2 is realized before C1 (see Fig.


Trunk Decomposition Based Global Routing Optimization Devang Jariwala Dept of Computer Science Uni of Illinois at Chicago djariwal@cs.uic.edu ABSTRACT We present global routing optimization methods which are not based on rip-up and re-route framework.

the routing optimization is based on trunk decomposition [13] of the global routing.


It measures how much of the original design specification has been verified.

the coverage is independent of the details of HDL implementation, and thus is considerably hard to measure.


When applying multigrid like techniques to solve the power gridproblems, a modification from the classical multigrid approach was introduced to better serve the specific need of circuit analysis [1, 2,4].

relaxation steps are removed to make the overall approach a direct solution method, which would be very beneficialfor transient analysis.


HMOR, a fusion of circuit decomposition theorems and mo- ment matching algorithms, can be easily embedded into in- terconnect synthesis algorithms to perform hierarchical tim- ing and multi-attacker noise analysis with great efficiency and accuracy.

we present its application to re- , peater insertion for multiple-attacker noise analysis for both capacitive and inductive coupling.


The actual .lter used for chrominance part is determined by motion vectors.

to increase the throughput, our reprogrammable architecture can be divided into two parts for simultaneously processing Cb and Cr.


However, this does not mean that all components of a given application will work well under the disk layouts determined by our pro.le-driven approach.

while it is expected that the layouts found by our approach will operate well for most of the loop nests of the application, it is still possible that these layouts perform poorly for a couple of nests.


We plan to focus on improving the dynamic adaptation phase as part of our future work.

we plan to perform tuning of the compensation for cache/TLB miss cases.


We have taken a hierarchical approach that largely abstracts away the internals of the node architecture.

we are able to utilize a self-contained speculative CMP as building block, with minimal additions to interface with the rest of the system.


Recall from Section  2.2 that the key reason for the nearest-sharer choice is to achieve observational equivalence between the cache s coherence interface and the internal interface.

because a cache interface would not make a read request for a block already present in shared, the internal interface should not make a read request for a block already present in its sub-tree and rather should require that the nearest sharer in its sub-tree provide the block.


In contrast to this work, there is no restriction of circuit state when choosing the most meaningful lines.

any line in the circuit with low signal probability can be enhanced.


When we utilize our approach using self-adaptive body bias, the process variations described above are reduced to the dark region in Figure 2.

our approach is able to work for all the conditions in Table 2, with a delay contained in the darkened region in Figure 2.


Torefreshmemorycells, extra refresh logic is required which in turn results not only in additional power consumption but also in availability overhead.

when a block of a data array (i.e., a bank) is being refreshed no other line in the bank can be accessed.


In conclusion, ISBA-based performance optimization turns out to be a Minimum-Weight Independent Set Problem on the Intersection Graph under resource constraint.

we need to find an independent set of the Intersection Graph, minimizing the sum of the weights of the vertices in the selected independent set while guaranteeing the DPR implementation can fit into the given FPGA chip.


The controllable buffer is designed so that each buffer delay td can be changed by signal cont from tdf to tds, where tdf <tds.

the buffer operates in fast mode before cont rise edge arrives, and after that it works in slow mode.


We show how the TTD can be used to implement tamper-evident storage where clients are guaranteed to immediately detect illegitimate modi.cations to their data (including replay attacks and forking attacks) whenever they wish to perform a critical operation that relies on the freshness and validity of the data.

we introduce and analyze a log-based scheme in which the TTD is used to securely implement a large number of virtual monotonic counters,which can then be used to time-stamp data and provide tamper-evident storage.


The total calculated equivalent weight of PC-farm system was 77 as shown in Table 3.

the computing performance of PC-farm system may be considered to be equivalent as that of a cluster system that has 77 Pentium III 866 MHz processors.


This value, labeled as VL(flip) in the figure, represents the minimum DC potential required to flip the contents of a cell.

vL(flip) is the maximum potential that can be tolerated by node L without altering its state from zero to one.


Figure 4: Transaction Driven Test Suite Reduction d. Post Silicon Coverage and Debug  This stage is where we reap the harvest of our investment in Pre-Si stages.

we benefit from the work done for test suite optimization and DFx instrumentation.


3D stacking potentially provides more bandwidth between chips.

the bandwidth between two 3Dstacked chips is a function of the chips common surface area, whereas the bandwidth between 2.5D-stacked chips is bounded by their perimeters.


Therefore, the previously described speed bottleneck from the LSP in the full-width multiplier disappears in this case.

we can obtain a high-speed fixed-width multiplier just with an array structure, and we don t need any compressors in the LSP to accelerate the operating speed as proposed in [6].


Among elements of set of transaction bus signals, values of address and control signals of active bus master can be deduced from their values at the start of a burst transfer on the target bus as their values either increase linearly over time or remain constant throughout a single burst transaction on the target bus.


Speci.cally, we use the convergence [9], which states that as , it sand .

wexperiments, where is a constween solution quality and convergence speed.


Only if both are simultaneously improved can their full potential be realized.

the performance improvement of the combination may be greater than the sum of the parts; our results to follow show that this is indeed the case.


There may also be overlap among regions.

the regions may contain identical traces, and this could lead to redundant trace preconstruction effort.


Extra-hardware based detection For convenience or transparency, extra hardware was created for acquiring the contents of system memory without OS or CPU interaction (e.g., [33]).

copilot provides a PCI based solution for checking the integrity of system memory by issuing PCI DMA requests periodically to take snapshot of the physical memory of a live system.


This work also has signi.cant limitations.

it does not address metastability issues that can arise when a data item and an anti-token reach a pipeline stage near simultaneously.


If the function at the output of v were changed from f0/v to g0/v, then g0/v would have to satisfy the union.

all the pairs in the union would have to be distinguished by g0/v.


2) For a switching MOSFET, the update of gm, gmbs, and gds is region-wise.

the change of gm, gmbs, and gds from Reg#i to Reg#j is fixed.


Second, in our methodology, the lock requests are being tracked on a processor-by-processor basis in hardware.

the SoC Lock Cache hardware contains an algorithm to determine the next processor to acquire the lock, thus helping to guarantee fairness, providing a deterministic choice, and improving predictability.


In this code, Thread1 executes a tlbsync instruction that is effectively a fence for the MRF.

the tlbsync guarantees that the tlbie instruction executed by Thread1 has been observed by other cores.1 Similar to the above programming example, a runtime hardware error or design bug could cause a TLB invalidation to be dropped or delayed, resulting in TLB incoherence.


Moreover, the adoption of Field Programmable Gate Arrays (FPGAs) as the .nal implementation platform rather than a rapid prototype target, further motivates the exploration of new techniques with respect to classical ones, tailored for Application Speci.c Integrated Circuit (ASIC) implementations, to focus on the peculiar aspects of the platform and of the faults that may corrupt the system behavior and computations.

fPGAs exhibit a (re)programmable feature that is usually exploited at design time to con.gure the device to perform the required functionality; such a con.gurability characteristic introduces both bene.ts and drawbacks since it derives from the presence of memory elements that can be programmed to provide the desired functions, but that are also a.ected by the considered faults.


the time complexity of the area enumeration is only O(1) because the CB-tree selects an initial searching tile (with corner stitching) near the given node.


The objective of this paper is to propose a design, abbreviated as FlashRec, that improves not only the logging overheads but also the recovery performance for DBMSs over MLC (and SLC) .ash memory, where the low reliability and the partial-programming constraints of the MLC .ash memory must be considered.

a logging mechanism with start, update and end log blocks are proposed to support e.cient transaction recovery in joint considerations of both wear-leveling and garbage collection over .ash memory.


Since memory capacity scalesfaster than bandwidth, this delay is likely to increase in future smartphones.

while it is possible to accelerate the process by writing out only selected portions of the memory state, the challenges in doing so are similarto thosefacedby Flikker.the programmer must identify critical data in the application and be prepared to restore the application based only on the critical data.


While FBA-based techniques have signi.cantly advanced strain optimization and were able to predict successful pathway modi.cations that were achieved experimentally by others, the techniques have limitations.

multiple solutions may maximize the production of a particular target.


In general, we observe that the selection of fault detector and the utilization of redundancy show a tradeo..

when the system features only limited amount of resources or the application has tight timing constraints, inappropriate selection of fault detector might disallow certain options for redundancy due to the timing overhead.


Reverse stress migration in short segments, described above, can block void growth so that it cannot reach Vfail (Figure 9).

the void growth with its increase in resistance .R does not reach the failure state marked by .Rfail.


However, the poor scalability of DC-Nets makes it unsuitable for medium or large-scale use.

in a network of n users, DC-Nets incurs a cost of .


We observe that most of the SPEC CPU 2000 applications manipulate some null data blocks, but in very di.erent proportions.


), a Monte Carlo simulation with 1000 iterations is performed using our FDM configuration algorithm described in Section 3.3 to identify the portion of the cache that should be disabled while achieving a 99% yield.

probability of failure of the cache must below 0.001 when operating in low-power mode.


However in this paper, we have shown that there still exist inef.ciencies in the prior solution.

the assumption that precise cache-content tracking was needed led to a MissMap structure that was over-designed for the DRAM cache.


We call this approach Application-aware hashing.

for pre.x .elds we use the approach proposed in [13] for longest pre.x matching, while for generic .eld we propose a hashing methodology aimed at compacting the number of dont care bits.


However, an additional enhancement (lines 8a and 9) makes it possible to utilize the concrete constraints to enlarge viol(X) further.

a small number of MUSes from the unsatisfiable formula conc X .viol X are extracted and used to select subsets of viol(X) each of which is sufficient to keep the formula unsatisfiable.


Errors must be spatially contained to the target resources of a relax block s execution.

an instruction must not commit corrupted state to a register or memory location not written to by other instructions in the relax block.


With the use of Anedma algorithm and radix-4 and radix-16 multipliers, the filters are more power efficient than the filters of [15].

it can be observed that the semi-parallel filters can reduce more power than the sequential architectures for almost all the filters.


In area of linear programming theory, there has been a deep study on the linear programs that automatically have optimal integer solutions.

it is the case for network .ow problems.


The problem belongs to the family of problems where two types of processes, called signalers and waiters, must exchange information regarding some event (e.g., a shared resource has been released).

the signalers must ensure that the waiters are aware that the event has occurred.


A register rename map provides a level of indirection, redirecting accesses to a given logical register to a particular physical register.

the register rename map directs accesses for a given dynamic value to the appropriate storage that contains the value.


8.2 Tuning for Less Aggressive TDC Since our overall algorithm is a combination of many different additions phase_local, loose nets, looping, etc, we find that it is inherently tunable.

we can trade off improved performance against compile time.


INTRODUCTION In recent years, fundamental physical limitations have forced CMOS scaling to deviate from historical trends.

non-scalability of the transistor threshold voltage and underlying limits on the subthreshold slope have limited supply voltage re duction due to the need to balance leakage power and device per formance.


Experiments were run considering multi-way sets.

we selected a L1 data cache similar to the design used for the Itanium2 (i.e., 16KB, 64B line, 4 way set-associative (64 sets)).


To simplify the following discussion, we omit the initial duration d and amplitude a from the notations of MEI and MMI in Equations (2) and (3), but keep in mind that they actually exist.

after adding wire w into the circuit, no matter how small MEI(s) is, a complete glitch with initial duration and amplitude is propagated from gate s to gate t once a high-energy particle strikes gate s. the resulting increase in error impact of gate s due to glitches propagated along the new connection w does not depend on MEI(s).


It is shown that M driver has the best Figure of Merit.

m e driver is a %faster, and consumes %less power than the conventional D driver.


Check the state of vibration sensor If a vibration sensor also reacts soon after the embedded sensor reaction, the system estimates that object movement should have something to do with the sensor-embedded place.

the object is very likely to be moved from that place.


Meaningful trends would require averaging results from many (more than 20) benchmark circuits for each di.erent number of embedded blocks.

we would need 20 or 30 circuits with only one embedded block, 20 or 30 more circuits with two embedded blocks, etc.


Our approach is based on the latter method assuming that the parametric form of the underlying joint probability density function is unknown.

we use the adaptive kernel estimator [4], which is described in detail in section III.


Even though an SPE already has the page for read, it must obtain write permission from the PPE before it .rst writes to the page.

upgrading the access permission from read to write is treated as a write fault in COMIC.


The private partition of core 0 consists of a hybrid bank, a SRAM bank, and two STT-RAM banks.

the partition can be regarded as a 52-way hybrid cache that consists of forty-seven STT-RAM ways and five SRAM ways.


For these reasons, among others, we have found that testability metrics return the same high value for different veri.cation target signals in a circuit, with widely varying dif.culty of veri.cation.

testability metrics do not provide suf.cient resolution to distinguish easily veri.able targets from dif.cult ones.


Driving Performance The simulator, STISIM Drive, automatically generated and gathered a large variety of data on driving behavior.

we collected information about drivers lane deviation behavior, the use of the brakes, speed, accidents and adherence to traffic regulations.


Exploration of Pipelined FPGA Interconnect Structures Akshay Sharma Katherine Compton Electrical Engineering  Electrical & Computer Engineering University of Washington Northwestern University Seattle, WA  Evanston, IL akshay@ee.washington.edu kati@ece.northwestern.edu ABSTRACT In this work, we parameterize and explore the interconnect structure of pipelined FPGAs.

we explore the effects of interconnect register population, length of registered routing track segments, registered IO terminals of logic units, and the flexibility of the interconnect structure on the performance of a pipelined FPGA.


This function is very e.cient as it only requires symmetric cryptographic operations.

f_read_asym_keys[] checks tag hP K .t to ensure that input data has not been tampered with.


C. Bulk DRAM Write Prediction and Streaming BuMP relies on LLC dirty evictions to enforce bulk DRAM writes.

buMP leverages the observation that the first LLC dirty eviction is a good indicator that a high-density modified region will not be modified prior to its eviction from the last-level cache (Section III).


Misses and writebacks from the L2 cache are sent to the DRAM LLC, which is a traditional write-allocate cache with a write-back policy.

when a modi.ed cache line is evicted from the DRAM LLC, it must be written to the PCM.


P2 is the PDF for the worst bitcell on a whole chip.

if we measured IREAD for every cell on a die whose cells followed P1, then repeated this measurement across many dies, and then finally plotted the distribution for the very worst IREAD from each die, we would get the distribution P2.


Based on this fact, to prevent interference scenarios, the proposed ONoC architecture utilizes path direction to discriminate optical data streams targeted to different wavelength groups.

clockwise direction within a super node is taken for routing data streams to the destination nodes located at the same wavelength group, while counterclockwise direction is chosen for routing data packets targeted to the other wavelength group.


Using the covariance matrix, and the underlying probability distributions of the variables in X, samples of the correlated non-Gaussian variables are generated and are given as inputs to the ICA module, which produces as output, the estimates of the matrices A and W. For a speci.c grid, the independent components of the non-Gaussian random variables must be computed just once, and this can be carried out as a precharacterization step.

iCA need not be recomputed for different circuits or different placements of a circuit.


The label in a duplicated input denotes the number of registers in its path to the output.

the duplicated inputs represent the values of the input in different time frames.


of Informatics, Japan kei@nii.ac.jp ABSTRACT We consider the recognition of activities from passive entities by analysing radio-frequency (RF)-channel .uctuation.

we focus on the recognition of activities by active Software-de.ned-radio (SDR)-based Device-free Activity Recognition (DFAR) systems and investigate the localisation of activities performed, the generalisation of features for alternative environments and the distinction between walking speeds.


This paper shows that many real world game, server, and multimedia applications exhibit such mixed access patterns.

such applications experience bursts of references to non-temporal data (called scans) that discards their active working set from the cache.


These channels are converted to Hjort derivation in order to get the local activity [17].

let xi be the Hjort derivation corresponding ' to xi .


Buffers actually can be inserted into one end or both ends of a TSV.

buffers for metal wires that have no TSVs can be inserted anywhere along the wires, whereas buffer insertion for 3D interconnects that contain TSVs has to avoid TSV obstacles.


This work aims at lowering the production cost of spring-mass capacitive accelerometers by addressing these test/calibration challenges.

the aimof this work is to develop a unified framework for testingand calibration of these devices using a small numberof electrical measurements, thereby eliminating the need for physical stimulus.


In this paper, we assume that intended circuits for scan-based BIST insertion are logic-intensive circuits.

the application-dependent circuits targeted in this paper require LE resources rather than memory resources, which are another resources embedded on FPGAs and can be con.gured to provide various memory functions such as RAM, ROM, FIFO buffers and shift registers without using LEs.


lR=0 returns an element b .Bn with P yrgn(b) = P r.R r s optn(y), where optn(y) := infb.Bn n(b) and s = r.R yrg 1 is a constant.

we assume that we can optimize linear functions over each Bn e.ciently with an approximation factor s. This is indeed true in our case: Theorem 1.


The Nt -k weight for the kth C rit(i, j ) is a .

the criticalities at di.erent temperatures are not treated equally.


In this example, applying k-means clustering or single-link hierarchical clustering fails to detect all the distinct signatures in Figure 6.

k-means clustering generates two clusters where Cluster a , b and d in Figure 6 are merged into one cluster and Cluster c in Figure 6 forms a separate cluster.


2.2 Constraint-Based Framework As in [1], we deal with source current uncertainties within the framework of linear constraints.

we distinguish local constraints and global constraints.


adaptation, the encoder adapts and operates in a con.guration that results in minimum frame loss, eventually giving a high PSNR output.

hardware-aware adaptation achieves the same desired PSNR with a lower frequency of operation, which in turn implies that such a system can tolerate variations to a greater extent.


1A-2 Behavioral Synthesis with Activating Unused Flip-Flops for Reducing Glitch Power in FPGA Cheng-Tao Hsieh+, Jason Cong++, Zhiru Zhang++, Shih-Chieh Chang+ +Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan ++Computer Science Department, University of California, Los Angeles, USA cthsieh@gmail.com, {cong, zhiruz}@cs.ucla.edu, scchang@cs.nthu.edu.tw ABSTRACT In this paper we discuss optimizing the interconnect power of designs implemented in FPGA platforms.

we reduce the glitch power on interconnects associated with the output of functional units in a design.


In this case, the longest recovery path to P3 is k re-executions of P1 plus a single execution of P2.

the availability of data is not only determined by the sending process, but also the processes scheduled before it.


In principle, the signal transition on a wire can be temporally correlated to the signal transition on other adjacent wires.

the transition on tr1for the signal 1 is not an independent event of the transition on tr2for the other signal 2 in Figure 4(a).


As discussed above, this is due to the restricted choices of task migrations in the band-based partitioning.

to preserve the principle of the task reconfiguration, enforcing the movement of the R band above the L band may not sufficiently exploit concurrent execution of tasks.


4.2 Join Cont roller The join controller is a key component in a counter.ow system, since it is this stage that generates the antitokens.

the join stage has multiple inputs, and has the ability to decide when some of those inputs are not required; those inputs are then preempted.


AliasAmbiguous A possible manipulation of some data through a pointer prevented the transformation.

there is a pointer that might point to something the restricts the transformation, but the compiler does not know for sure.


All the results presented in the rest of this section are with respect to the "default scheme", which includes all single-core centric data locality optimizations enabled by the O3 optimization .ag in the commercial compiler.

the results we report represent improvements over already-optimized codes.


Reliability Aware NoC Router Architecture Using Input Channel Buffer Sharing M. H. Neishaburi McGill University Montreal, QC, Canada mh.neishabouri@mail.mcgill.ca ABSTRACT To address the increasing demand for reliability in on-chip networks, we proposed a novel Reliability Aware Virtual channel (RAVC) NoC router micro-architecture that enables both dynamic virtual channel allocations and the rational sharing among the buffers of different input channels.

in the case of failure in routers, the virtual channels of routers surrounding the faulty routers can be totally recaptured and reassigned to other input ports.


Moreover, the minimization must be constrained by the timing yield.

we wish to ensure that the function of chips whose delay satis.es the timing exceeds a given percentage a.


Notice that, the TaxSOM model overcomes the baseline approach for all measures and taxonomies.

the relative coverage of TaxSOM is always greater than baseline; Directories Arch Biol Cook News Heal Relative Coverage Baseline TaxSOM 81.40 88.62 40.75 79.52 67.27 83.84 90.00 98.28 78.25 79.30 Average Coverage Baseline TaxSOM 2.12 2.76 0.99 1.93 3.42 7.42 5.00 6.39 7.25 8.37 Macro F1 Baseline TaxSOM 57.64 58.54 33.77 70.19 28.69 47.07 33.90 39.01 32.43 33.05 Table 2:Stand-alone comparison of the TaxSOM model versus the baseline approach.


In contrast, dynamic channel assignment (DCA) [1, 2, 4, 13, 17] does not partition the channel set, and in principle, allows any channel to be used by any node in the network.

each base station can use any channels that are currently unused by any neighbors with whom there might be a possibility of interference.


Consequently, considering the balance between accuracy and DVR, the best learning technique among those examined is the decision tree.

a decision tree exhibits, on average, an accuracy of over 90% when achieving a DVR of 32.4%.


The last parameter which we can analyze is CPI.

the analysis of our baseline architecture revealed that in average our engine requires 2.66 cycles to process a field, which leads to a maximum data rate of the FAST processor of 4.8Gbit/s: .


Our goal in this paper is to examine the asymptotic behavior of the response time tail distributions under both LRD arrival processes and general (light-tailed or subexponential) service times.

we consider LRD/GI/1 queues, where the arrival process is long-range dependent (LRD) and the service times are independent and identically distributed (i.i.d.)


The experimental results show that our obstacle-avoiding free-assignment .ip-chip routing algorithm is e.ective and e.cient.

our router completed the routing for all the benchmark circuits and consumed only 13 seconds for the largest circuit fc2624.


Subsequently, we use these two histograms to generate random samples (TX and TX)that satisfy these probability density functions, i.e., PDF(TX)= X and PDF(TY ) = Y.

the numerical value of each input value roughly represents the frequency for its index value to appear in the generated random samples.


Also, it should be demonat the cost of some performance impact.

in strated that topologies returned by the algorithm are SRsome cases the lamb switch algorithm disables switches that compliant (without any resegmentation need) and LBDRare still supported by the transition table.


However, recent content formats including the H.264/AVC video standard [8], AAC [1], and the Scalable to Lossless (SLS) audio coder [9] pose significant scalability problems for generic adaptation via BSDL.

bSDL cannot efficiently describe numerous structures which are prevalent in these formats, and the description tools which are available lead to a processing time which increases relative to the bitstream duration according to O(n2).


Subsequently, symbolic analysis and value range analysis is used to determine whether the range of computed addresses per CTA is coalesced with respect to tID.

forward substitution is used to derive the address calculation expression, EA.


cells containing more than one ALU, in the state-of-the-art.

the PACT-XPP cells [18] (like the RAC we overview in Section 2) support conditional operations within one clock cycle, and the Flexible Computational Component [10], while targeted more speci.cally to DSP kernels, is similar to the RAC in size and set of allowed operations.


Our technique is compared to the previous technique in [8], and the same experimental setup, testcases and technology library from [8] are used in this paper.

it includes 10 small testcases with 50 to 100 functional units, 5 large testcases with 500 to 5000 functional units, and a technology library consisting of .ve voltage levels.


Second, partitioning gates into shells according to the slack facilities the desired smooth incremental optimization.

the reduction of slack within each shell is constrained by its shell slack boundary (i.e.


are the most e.cient transistors for a given inversion index if .

the optimal solution for the relaxed GP should also satisfy the equality constraint (8), and thus, will also be the optimal solution for the original nonrelaxed geometric program.


As CMOS processes are typically getting more and more optimized for the needs of digital circuitry, this trend can influence the future milestones for analog design.

cMOS technologies are being developed to improve digital switching speeds, lower the supply voltages, and reduce transistor geometries to increase the packing density of digital circuits, where all these modifications can negatively impact analog and mixed-signal circuit performance by reducing the input voltage swings and the linearity over the range of operation as well as information loss caused by charge injection induced by the digital part.


These important process variabilities must be accounted during design in order to safeguard the manufacturability of circuit designs.

a large body of statistical static timing analysis (SSTA) techniques have been proposed aiming at evaluating not only the nominal case timing performance but also its statistical variations due to random process .uctuations.


Thus, 3D compositing window managers make effective use ofavailable graphics hardwareandprovideef.cientwaysto manipulate desktop and window geometries, as well as their textures.

the Beryl window manager enables us to access the .nal desktop composition in our plugin and to render the desktop image intoa framebuffer object.


This gives rise to the concept of performance binning instead of the traditional frequency binning, where the chips are binned in terms of their actual throughput.

the paper makes the following contributions: 1.


These results clearly show that fault simulation is not a proper approach for SER estimation of sequential circuitsand theestimated values aresigni.cantly lowerthanactual values.

if reliability parameters are obtained using faultsimulations,theactualreliabilityrequirementsmaynotbemet and this may result incatastrophes in criticalapplications.


OTHER EDUCATION-ORIENTED FEATURES AND DETAILS We have largely achieved our original MARS project goal, which was to develop a viable alternative to SPIM for typical undergraduate use.

to provide a tool that implements the important MIPS instructions (those covered in COD3) through a portable and student-friendly IDE.


In this research, therefore, a new speech interface capable of achieving these features simultaneously was studied.

this interface is designed for a command execution method, because command execution is one of the most probable domains for speech interface technologies.


However, all MPML experts share their methods, and only the intermediate representation and grammars are different.

all MPML experts are in the same class in the objectoriented programming framework.


In [POM96], it is showed that the number of times each fault is detected is more important than test set size in determining the defect coverage.

the defect coverage does not have to be sacrificed by test compaction.


A grid is said to be robust if, for every node k, the steady state voltage drop at k over all possible currents satisfying (5) is less than a given threshold vth.Let vub(p.t) be the vector of upper bounds on the peak voltage drop at time point p.t, de.ned in [6].

we will denote vub(.t)by Va.From [6], we have that, as p tends to in.nity, vub(p.t)convergesto: « V8 = I + G-1 CVa (10) .t for all .t = 0.


The policies decide in which cache to insert a line on a miss or where a line is moved ( promoted ) on a hit.

we investigate 4 insertion policies and 4 promotion policies.


Here we assume that other nodes accesses a sampled version of the link state.

let s associate 8 a sequence of sampling instants, {TjL[£]}.with the =0 jth node.


Note that the microarchitecture does not necessarily require modifications to the register file or functional units.

even though a fused pair is scheduled as a unit, the two halves of the pair can actually begin execution in two different (consecutive) clock cycles.


Using incremental solving in BMC, only one SAT instance, which changes with every call of the solver, is used for all calculations.

parts of the formula are removed (e. g. by adding the transition relation Ti,i+1 and related property Pi+1, the property Pi has to be removed), and thus derived clauses originating from removed parts are invalid in later solver calls.


Therefore only forward body biasing will be applied to mitigate this change, and the magnitude of the biasing voltage can be used to characterize the NBTI stress amount.

the value of VOUT of the ABB circuit can be taken as a metric for NBTI monitoring.


2, where we have noted that the leakage correlation of any pair of cells is approximately equal to the correlation in the channel length of these cells.

pm,n : PL, ~m, n. With this simpli.ed correlation assumption, (10) can be used to determine the RG leakage correlation.


As discussed above, it is not possible for VOU T to equal VOU T ,N L. Therefore, when considering both conduction loss and parasitic switching loss [9], it should be as optimally close to VOU T ,N L as possible.

for a given VIN , the optimal VOU T can be de.ned as: VOCR = KOCR * VOU T,N L. (4) Fig.


as opposed to a best-effort NOC has important bene.ts for a design .ow.

this results in a fundamental difference in how performance is validated.


Improving the Error Detection Ability of Concurrent Checkers by Observation Point Insertion in the Circuit Under Check Valery A. Vardanian and Liana B. Mirzoyan STaR Lab, Institute of Informatics & Automation Problems, Armenian NAS Yerevan 375044, Armenia, E-mail: valery@ipia.sci.am Abstract A heuristic design-for-checkability method based on observation point insertion in the Circuit Under Check (CUC) is proposed to increase the error detection ability of Concurrent Checkers (CC).

at least 99% of error detection is obtained for parity checkers and almost all ISCAS 85 benchmark circuits by inserting 2-5 groups of observation points compacted by parity trees.


This time-variant input scheme generates the required steps of a positive half sinewave, while the input switching scheme controlled by signal Fin (in Fig.2c) sets the weight (positive of negative) of the step.

the input capacitor can be described as 4 CI t = .F() F().


This means that the new programcriticalpath should notbe worsethanthe original path(thatpassedthroughdispatchnode ofthe spawnee).

the only reason why it could be worse off than theoriginalpath,couldbeifit .owsthroughoneof theEE edges that aredelayeddue to the act of spawning.


AP covers the worst case timing scenario and its delay needs to be considered for the memory timing closure.

the word line signal is disabled by considering the P .


However, thetest programs for testing the non-programmable corescan beoptimized by adding new instructions.

the sameset oftest instructions added for self-testing the programmable corescanbe usedto reducethesize and run time of the test programs for testing other non-programmable cores.


Although in this case the obtained performance is closer to the high-level estimations, link pipelining techniques may have a great impact over the implementation cost, thus requiring a new metric to asses the real e.ectiveness of link pipelining techniques.

we have considered the area e.ciency metric, de.ned as throughput/area, which correlates the throughput improvement with the area cost that has been paid to achieve that.


The above regions of operation can be modeled using the linear gate model of (6).

in the weak coupling region, Figure 9(a), inverter 1 behaves like a resistor from V2 to the ground, with resistance being the linear-region resistance of M1, R .


The model in sleep mode can be used to determine leakage energy savings in inactive states of the circuit.

some of the key parameters used as optimization criteria for logic clustering have been captured in closed-form expressions.


10.b, high insertion loss of the optical crossbars along with global arbitration increases power consumption perpacket transmission in OXbar.

2DHERT architecture achieves average perpacket power reduction of 53%, 45%, and 95% over OXbar, LR, and ETorus, respectively, for various traffic patterns.


Interconnect Challenges The class of applications mentioned above, particularly those more graphics related, tend to be more parallel in nature and scale well across a large number of core or execution threads.

if the number of core is doubled, the execution time or compute throughput is roughly halved.


The resulting cells were .rst checked to pass the stability test with a 5 sigmas con.dence.

if for a particular metric µmetric -5smetric <thmetric the  discharge delay [ns] Figure 2: Candidate cells presenting an optimal delay-energy tradeo..


It was demonstrated in [5] that there exists a context-dependency for interconnect performance corners.

the papershowed that the delay of one interconnect structure increased while the delay of another interconnect structure decreased when the metal thickness was increased from T0 to Tmax.


Our analysis shows that age of nodes, proximity between nodes, and subscription to common services are factors that in.uence formation of new links in our data set.

our analysis shows that by categorizing nodes based on age one can gain better insights into behavior of nodes, especially for applicability of preferential attachment models.


These units are pipelined, thus are able to operate concurrently, and the interconnection between them is accomplished using on-chip buffers.

the system uses one scanline buffer to temporarily store the image data, and six smaller on-chip buffers to store the rotated matched filters.


This decision was made due to the usefulness of the compiler Intermediate Representation (IR) to analyze the cipher.

the IR provides enough precision concerning the implementation, while retaining independence from the speci.c target architecture allowing an ef.cient and yet general analysis to be performed.


This case is relevant in practice as it points out a non-compliance to the fault injection hypothesis, suggesting a physical failure in the fault injection technique.

results coherent with this observation were reported in [19].


For a segment swe de.ne ¯ ds = ds| (dP = da) (3) Figure 2: Relationship of di.erent segment types.

¯ ds is a random variable expressing delay of sgiven the measurements on the nrepresentative paths.


This implies that the degree of responsiveness signi.cantly a.ects the amount of loss event rate di.erence because TFRC is less responsive than TCP.

the more responsive a .ow is, the higher loss rate it gets, which con.rms the results from [1, 17].


In the worst case, vortex shows the 3.84% performance loss with 31% leakage saving.

bzip2, gcc, mcf, parser, vpr, applu, art, galgel, lucas, and swim nearly the half of the entire SPEC2K workloads show negligible or no performance losses while achieving more than 80% leakage power reduction for the combined technique.


Since an unstructured mesh is essentially a decomposition of the physical domain, the edges and faces follow the physical adjacency of nodes.

edges or faces only connect physically adjacent nodes.


P3: The crosstalk-affected output delay and transition time are weakly sensitive to the wire resistance value.

they monotonically increase as the victim wire resistance increases, while monotonically decreasing as the aggressor wire resistance increases.


gate has a controlling value, the fault is logically masked.

this prevents the fault from propagating through the gate and consequently, prevents the fault from propagating further through the circuit, to the memory element at the end of the path.


Moreover, after edge unification shown in Figure 5(b), path condensation can again be applied along the path (v1, v4, v5) to further reduce the size of CQG.

these two operations can be performed repeatedly until no further reduction can be made.


Built-in selftest (BIST) is an increasingly effective and necessary DFT technique in which part of a circuit is used to test the circuit itself [1].

bIST is now ubiquitous for embedded memories, which do not have pins or pads exposed for testing with automated test equipment (ATE).


the mesh network, for which the best designs incorporate the While there is a network to .t each workload, there is no large, 128-bit packets and short, 4-entry queues to maximize network to .t all workloads.

no network in throughput under the areabudget.


The other stacks can become the longest execution path for different stall-event latency con.gurations.

by keeping these representative stacks, it is possible to accurately predict the performance even when the event latencies are adjusted in a complex way.


During this phase, we ensure that the design is supplied with adequate power.

we ensure that the design has alternating Vdd and Vss tracks separated by no more than the designated power pitch (say, P).


To boost the frame processing performance, we use OpenCV libraries and interface them with Java using Java Native Interface on Android.

we adopt OpenCV s native implementation of the Hough transform, which is more ef.cient than other implementations in our tests.


We demonstrate how this information can be used in an experimental architecture to accelerate applications.

our compiler assisted approach shows a 20% speedup over shared caching and 5% speedup over the closest runtime approximation, .rst touch .


Recognizing these challenges, various techniques at different stages of the design .ow are being developed to aid in variation-aware IC design.

the impact of variations on leakage power is very pronounced (as has been reported widely in the literature [1]), making it imperative to consider it during power analysis and optimization at the system level.


But (a) aims to the case that the states of system are immeasurable.

the control e.ectiveness is similar to [16] in worse case by using the method in this paper.


x ** z or f =5 Combining case 1 and case 2, we conclude that it is impossiblethat all the three encoded cofactor pairs have a 3, 5, or both at thesame time.

no such a function f(x, y, z)whose expansion on every variable can yield a Su cofactor.


While specialized and accelerator architectures tackle the energy e.ciency problem by augmenting conventional processors [11, 18, 22, 24, 40], this paper investigates whether fundamental ine.ciencies in the processor core itself can be eliminated.

we consider the overheads arising from speculative execution, including branch prediction, memory dependence prediction, and execution in the presence of hardware faults or exceptions.


However, MLS only issues one prefetch for each stream and always attempts to traverse the stream chain to .nd new streams.

we can consider the conventional stride prefetcher is a special case of the TAS prefetcher that never goes width in .nding prefetch candidates, while the MLS prefetcher is another special case of TAS prefetcher that never goes depth in .nding prefetch candidates.


This strategy is safe in terms of con.ict number.

when a vertex is pop up from S, there is always one color available without introducing new con.ict.


According to the results, the two Aegis s variants can more e.ciently use the overhead space.

the per-bit contribution of Aegis-rw-p can be higher than that of Aegis-rw.


We assume that tasks consume the same amount of compute power regardless of which processor they get mapped to.

all processors in our component library have the same efficiency; processors and memories differ from one another only in terms of capacity.


The problem here is that each GRAPE hardware, and therefore each host, must have the information of all particles in the system to calculate the total force on a particle.

each host need to receive all informations of particles updated at the end of each timestep.


In this work, unlike the previous works which have solved the ADB minimization problem heuristically or locally optimally, we propose an elegant and easily adoptable solution to overcome the limitation of the previous works.

we propose an O(n log n) time (bottom-up traversal) algorithm that (1) optimally solves the problem of minimizing the number of ADBs to be inserted with continuous delay of ADBs and (2) enables solving the ADB insertion problem with discrete delay of ADBs to be greatly simple and predictable.


Therefore, in an n*n mesh the worst case for a single search takes 3*(2*n-2)+6 cycles, no matter if the result is a success or a fail.

it means the time for every single search is predictable and bounded, and has a complexity of O(n).


A by-product of DREAMS is a significant improvement in diagnostic resolution.

by understanding which rule is most likely responsive for failure of a given chip allows one to further localize the failure to a more precise location.


The set of single-cycle false paths, under a delay con.guration M and a state S, is denoted as .M,S .

1 The set of other paths which do not belong to .M,S 1 M,S M,S M,S is denoted as .. .. .


Next, we perform SSTA on the circuit to obtain the PDF of the circuit delay, dc, in canonical form.

this analysis provides us with the coef.cients of the PCs in the circuit delay expression.


For example, if two cells ci, cj are assigned with p-th and q-th coloring solutions, respectively, then LUT(i, p, j, q) would store the minimum distance required when ci is to the left of cj .

if two colored cells can be legally abutted to each other, the corresponding value would be 0.


3.2 Multi-Pathing Striping the data at the source and sending it across multiple overlay paths can also lead to a better achievable throughput.

multiple independent routes can be employed to simultaneously transfer disjoint chunks of a .le to its destination.


In many array-intensive embedded applications, however, loop nests that are executed one after another access the same set of arrays.

there might be a signi.cant amount of data reuse between two neighboring nests.


They present an automated tool for the construction of .ngerprints and provide recommendations for better localisation.

following this study, access points should have .xed installations near or at walls.


As shown in figure 4, The FIR filter using CSHM consists of one precomputer and M Select units and Final adders (S & A) s, where M represents the number of taps in FIR filter.

we can easily notice from the figure that the precomputer outputs are shared by all the S & A s. the computations ak x, k = 0, 1, 2 .8, are performed only once for all k's and these values are shared by all the Select units for generating ck x, i=0, 1, 2, 3, .


Furthermore, arbitrary temporal properties speci.ed in a temporal logic can be veri.ed.

we have de.ned in [22] an extension called JCTL of the well-known temporal logic CTL by real-time contraints.


Our basic idea is to make use of gate downsizing as possible under the lower bound of the clock period.

only for those hold violations that cannot be resolved by gate downsizing, we apply buffer insertion to them for achieving the lower bound of the clock period.


We do believe that there is potential to further improve the critical path delay, which would require much more aggressive synthesis algorithms that are speci.c to the new logic chain.

this would require a new logic decomposition algorithm that recognizes the cascaded structure of the logic chain; such an algorithm could be integrated with a technology mapper to make better use of the logic chains than the relatively naive and greedy chaining heuristic described here; this is an important research direction that is currently left open for future work.


When routing a path, if passing edge e induces overflow, e is said to be an overflow edge with coste = 1; otherwise coste = 0.

the goal of rerouting a two-pin net here is trying to find a path with minimum number of overflow edges.


The samples always execute the twobit static re-reference interval prediction (SRRIP) policy for all the streams.

a block is .lled into a sample with RRPV equal to two.


we require the latches to hold the same values as in an identical circuit in which all elements, including both gates and wires, have zero propagation delay.


Therefore, we propose a partial selection mechanism on DAPs in order to mitigate the drawback.

dAPs allows one core to execute simulation with aggressive sampling and the others to execute fast-forwarded simulation at the same time.


Loads (ii) (vi) are to distinct objects.

there will be little spatial locality between two references to the same set.


The I/O port controllers were negligible both in power and in area.

around 740 extra DFFs were inserted as input data register on the GALS channels [12], which correspond to buffer each datalink only with a 1.5-word FIFO in average.


Upsizing the keeper transistor is one of the ways to improve robustness, but this causes more increase in power dissipation and delay.

upsizing the keeper increases current contention between the keeper transistor and the evaluation network.


Recall that a voltage partitioning algorithm is a fully polynomial time approximation scheme (FPTAS) to the NP-hard voltage partitioning problem if it can compute a voltage partitioning solution with peak power always within a 1+ E factor of the optimal voltage partitioning solution and it runs in time polynomial in n and 1/E for any E> 0.

it is a linear time approximation scheme if it runs in time linear in n (while usually nonlinear in 1/E).


This method performs a directional search along the orthogonal Arnoldi vectors which span the Krylov subspace of A.

given an initial guess x0 and corresponding residual r0 = b - Ax0, orthogonal vectors {q1, q2...,qm}are generated with the property that they span Sm, the solution search space at iteration m. Sm = x0 + s pan {r0,Ar0, ..., Amr0} = x0 + .


Each logic family has a unique set of advantages and tradeoffs, and the choice of logic family is therefore dependent on application-specific requirements.

eCL consumes a relatively large amount of power, but its small delay time makes it useful for very high-speed applications [18].


MOTIVATION OF THE TLM ANALYSIS The adoption of a TLM level of abstraction in the modelling of a digital system poses new problems that should be addressed by EDA tools [2].

the higher abstraction level implies that the models described at the TLM level can represent functional descriptions of the system prior the hw/sw partition and even before the choice of the target architecture.


The use of low-Q inductor substantially increases NFmin,the minimum noise .gure calculated with (15) for given power, as shown in Figure 4.

to reduce NFmin it is much more effective by increasing inductor quality than by increasing power.


Digitizer using these multi-phase clock signals count the number of 'Hi' delay cell s outputs, and switching detector locates the place where input signal changes from 'Lo' to 'Hi'.

the switching detector spots the last 'Hi' delay cell.


These components are added on per column basis.

all cells in one column share one set of the EWT circuit.


Results show that baseline removal by quadratic variation reduction outperforms wavelet adaptive .ltering, thus introducing minor distortion in the ST segment level.

the median, which is less sensitive to outliers being a robust statistics [17], is signi.cantly lower.


However the formulation in (4) and (5) is general enough to cover both device generators.

a parameters contain all the required information about orientation, guard-ring, dummies, routing, etc...


Therefore, all the paths from FF0 to FF1 are 2-cycle paths.

the circuit would allow 2 clock cycles to complete the propagation of transitions along these paths.


Because it utilizes the geometry information of the original matrix, it can help the iteration process to achieve much faster convergence than the traditional preconditioner.

note that new matrix we can obtain is a symmetric block matrix (see Fig.


However, unlike in the ISF, they can be regarded conversely.

it represents a pair of ISF s. If (hi,1 .hi,0)(hj,1 .hj,0)= 0 holds for any (i,j) where i = j, i =1,...,m and j =1,...,m, then the SPFD represents 2m ISF s. The ISF s can be represented a functional expression in Table 1 where 0 or 1 can be assigned to ai in g for each i =1,2,...,m. Like MSPF s and CSPF s in the Transduction Method, SPFD s are used to determine whether wires can be removed or replaced.


Adding such conflict clauses prevents the algorithm from encountering the same conflict.

clauses prune the search space efficiently [16].


The network composed of surface circuits and substrate parasitic interconnections is obtained by elaborating the circuit layout view and the substrate doping pro.le descriptions.

the layout view (including power devices) is elaborated and an extracted view is obtained.


In LAD, all the ways in a set have the same number of accesses.

if there is a way within the set that has more accesses than the rest of the ways, its accesses are distributed to the other ways.


Nevertheless, (c) the high-frequency behavior of the CUT can be monitored with DC temperature measurements due to the Joule effect.

the product of an AC voltage v(t) = A cos(.0t) and an AC current i(t) = B cos(.0t + .)


In this paper we show that card-based public key Kerberos is .awed.

access to a user s card enables an adversary to impersonate that user even after the adversary s access to the card is revoked.


The percentage of misspeculated load instructions avoided is between 4% (eon ) and 67% (gzip) and the average is 26%.

the number of reduced wrongpath loads is signi.cant for benchmarks vpr and twolf in which the number of loads are reduced by 30 and 20 millions respectively.


Interestingly, Z0 and A, which are inversely proportional to power and wiring density respectively, are independent of each other.

an interconnect system can be designed to have arbitrarily any impedance (Z0) for any cross sectional area (A) of the signal conductor.


E  in - edges(v) degrees_changed = 1 end if end for end while Note that this entire analysis needs to be performed for a representative bus segment.

even if the bus is very wide, the analysis is performed for a single segment (which is typically very small).


is set to be valid when a read operation on the write buffer entry is issued.

when the read operation to the data in the write buffer entry is issued to the data cache, the cache way number that contains the requested data is found.


A partial solution state can be de.ned as the quartet {Sc is the un- H , SV ,last_layer, extra_bend_count},where SV ordered set of vertical segment IDs, and Sc is the unordered set of H pairs of horizontal segment IDs and partial wirelengths.

while the lengths of the vertical segments are discrete, the lengths of the horizontal segments are continuous variables.


Thus, the optimal RCRPs remain the same for the two area budget requirements in these cases.

even when area budget raises to 2%, the area overhead of actual RCRPs is still within 1.5%.


2.3.3Peak-picking After the above procedures, picking the onsets, , is reduced to the identification of local maxima above the defined threshold, which can be summarized as [17]:  (18) 3.APPLICATIONS TO HCI It is possible to use the onsets obtained with any of the methods described above to create more general algorithms that can be used in specific high-level processing of music, like, for instance,easier music-similarity discovery [6].

successful onset detection can be an important first step in the improvement of the current music recommendation systems, facilitating the user's work in finding new and unknown music that he will probably like.


i) Exploiting Thread Level Parallelism: An investigation in standard circuits reveals that each output of the circuit is not dependent on all the inputs.

the logic for most of the applications is bit-sliced, so that the computations for the different output bits may be performed in parallel to one another.


In order to increase the total delay time in DSM mode, extra delay cells can be added to the delay-line chain in Figure 6.

the signals (t1~tn) does not need to select from consecutive delay cells.


Dynamic energy consumption is split into energy due to computation and energy for data transfer.

edyn = Ecomp+Exf er = D·(EP Bcomp+EP Bxf er ), where EP Bcomp is the average energy spent on processing a single byte of input and EP Bxf er is the average energy spent on data transfer per single byte.


Write Serialization All writes to the same location have a total order which is respected by all processors.

for any two writes, w and w ., to the same location then either w<all w .


Note that during a 0-write phase, .eld a1 of a register would not be changed and during a 1-write phase, .eld a0 of a register would not be changed.

these .elds would be written back unmodi.ed.


For each window that is accessed, instances of multiple queries that require data from the particular window are scheduled sequentially.

queries in the query queue are shuf.ed in a safe way to reuse the data that is being processed at a given instance.


CONCLUSIONS In this paper we presented an approach to inkjet printing .exible circuits in the laboratory which has only recently become possible.

a chemical sintering process means that it is now possible to use inexpensive off-the-shelf inkjet printers, making the technology very accessible to practitioners.


The algorithm begins by placing all of the shadow resources for the design.

the algorithm chooses a small set of placement site within the device in which all shadow resources reside.


In order to be generated, the initial LFSR state should be updated according to the solution of the system (i.e., assuming Gauss-Jordan elimination, all the variables belonging in the pivot columns of the system should be replaced by linear expressions of the free variables).

if system svi,j = t is solvable, then test cube t can be encoded at the corresponding position of the search space.


The caches are assumed to be fully associative in our simulations, and they are allowed to "fill up".

we don't replace lines; when the cache is full, preconstruction from its associated region is terminated.


In general, the INIT code indicates the beginning of an active batterycell array.

the preceding battery cells are ignored in spite of their connectivity.


PRIORITY ASSIGNMENT STRATEGIES OF PROCESSING ELEMENTS 3.1 Overview This section explores the PASPL problem in a more unrestricted fashion.

we would consider two cases in this section: (1) an approach to verify the feasibility of a bus transaction graph, and (2) an approach to reduce the number of priorities for each PE to meet the deadlines of a bus transaction graph.


Our results also illustrate the relative benefits from individual solutions.

we find that for current systems with high baseline idle power consumptions, virtual machine consolidation can be a more effective way to save power in spite of its additional overhead, but local power management can still be effective for high-activity workloads.


Therefore, the GHB-PC/DC scheme, which is essentially an address-based correlation prefetcher, was selected as one of the comparison points.

two dif 45% 40% 35% 30% 25% 20% 15% 10%  % Performance Improvement BW = 3.2GB/s BW = 6.4GB/s BW = 9.6GB/s 5% 0% -5% Prefetch Degree Figure 8: Effect of available memory bandwidth on epoch-based correlation prefetcher performance.


An advantage of the proposed circuit is the output voltage settles at the desired voltage level regardless of the output current demand.

the current demand from the load circuitry does not produce a signi.cant DC voltage shift in the output voltage.


(9) The TFT-LCD power consumption decreases as the transmissivity increases.

while maintaining the same luminance, the power consumption of the TFT-LCD decreases when dimming the backlight.


By ignoring partial .ushes, the MDT simply becomes conservative.

the MDT may detect spurious memory ordering violations with respect to canceled loads and stores.


An important observation made by these previous studies is that the effectiveness of low-power management increases as the bank idleness increases.

from the power management angle, we would prefer a single large idle period over a set of small idle periods.


Depending on the decision, a simulation path is chosen and symbolic expressions are simpli.ed by Mathematica.

the veri.cation of user written assertions is performed by this procedure.


, the p,k p+1,k added (P +1)th finger can increase system performance only if the following condition holds.


an niinput/no-output circuit which provides no · 2ni correct output bits when all possible input combinations are evaluated.

the goal is not in minimizing the number of gates, delay or other criteria.


we .nd that an overwhelming number of registered domains (85%) are defensive in nature, with only 5.9% of domains registered for the purpose of serving content.


Our current implementation handles most, but not all, of the cases where convergence is possible.

it does not attempt to perform detection for expressions with a condition speci.ed in the WHERE clause.


The spatial locality of memory accesses results in the address sequences sent to the cache tending to be in the near neighborhood.

only the low-order bits of addresses toggle most of the time.


Note that it is important that the recon.guration cannot be undone.


2b-3) Oldest-.rst: Ready commands from older requests over those from younger requests.

sTFM uses either the baseline FR-FCFS policy (if the level of unfairness across threads with ready requests is acceptable), or a fair FR-FCFS policy in which requests from the most slowed-down thread receive highest priority.


Therefore, in order to evaluate the impact of the mobile radio in a multicellular environment, a channel model using standard models and techniques has been de.ned and developed in 3GPP [2003], partly based on real measurements.

effects such as path loss, Doppler spreads, shadowing, antenna radiation pattern and interference are appropriately dealt with.


(5) All vector inequalities here and thereafter are understood componentwise.

we would like to maximize the probability that the global circuit performances, which form the vector z, meet the prescribed speci.cations for all possible environment data.


To ensure in-order delivery, the path through the network is determined by source routing.

the path is embedded in the packet header, as shown in Figure 4(b).


In addition, the destination variable points to the same set of unde.ned values as the source.

if A:=Bis executed and the unde.ned .ag of Bis set, then the unde.ned .ag of Ais set, Ais added to the unde.ned value set of B, and Ais set to point to the same unde.ned value set as B.


The transient information provides complementary insight in the behavior of complex designs in which electromagnetic interaction can jeopardize the .rsttime-right EDA goal.

rF modeling in the frequency domain is limited to the small-signal response superpositioned to a .xed operation point.


This paper deals with the problem of clock tree construction, which we refer to as clock tree synthesis (CTS).

we address the following important questions that arise in CTS: (1) What are the factors that can a.ect the robustness of the clock tree solutions; (2) Can clock tree structures meet the skew requirements in the presence of variations?


The yellow blocks in the East output VC state represent the additional logic to support the NBTI sensor-less methodology.

we require an additional bit for each VC associated to the output VC state as the most degraded marker.


points can be derived by first efficiently packing constant-radius spheres in a high-dimension space and then taking their center points the angle formed between two vectors pointing adjacent nearest neighbors is always equal to 60-degrees.


Figure 9 shows the performance of the scheduling schemes for a .le pattern which involves data redistribution from a set of source sites to a set of destination sites.


In the example of Figure 2.b three cells (namely 1, i and l) have been chosen by the seed-selection algorithm and, as a result, two test vectors are generated by each one of them, starting from the same initial seed.

each seed is expanded to the predetermined number of test vectors (which is equal to 6 in our example) in different test phases (hence the name multiphase).


The second contribution is the investigation of perceptual issues related to clustering and premixing, based on pilot user studies we conducted.

we investigate the in.uence of visuals on audio clustering for audio-visual scenes, and propose a modi.ed metric taking into account the indication that it is probably better to have more sources in the view frustum.For scalablepremixing, weevaluated the different metrics which can be used, including recently developed perceptual models, such as the audio saliencymap [Kayser et al.


At the L2 level, bank interleaving typically occurs at the granularity of cache lines.

an access to address x would get routed to L2 bank number x » 6 (mod 16), assuming 64-byte cache lines and 16 banks.


Interestingly, using this tool to program in parallel the nodes over the USB tree we were able to save 66% in programming time with respect to a classical serial programming.

in the DEMMON1 deployment, it took around 30 minutes to serially program a patch composed by 100 nodes, while with this tool the programming time reduced to no more than 10-12 minutes.


Capture transition probability can be calculated in the same way as active probability calculation shown in Section 4.2.

bL-Prob0/BL-Prob1 and AL-Prob0/AL-Prob1 are obtained for all signal lines first, and then capture transition probability is calculated for each critical gate.


The key idea to guarantee privacy is obfuscated program execution in hardware; to evaluate an arbitrary instruction, Ascend gives o. the signature of having evaluated any possible instruction.

for an arbitrary ' batch program P , any two encrypted inputs x and x(the user s private query), and any two sets of public input y and y' (server s public data), Ascend guarantees that from the perspective of the chip s input/output (I/O) pins P (x, y) ' ' is indistinguishable from P (x, y), therefore satisfying the criterion for oblivious computation [14].


Since the inter-cluster routing area decreases when K increases, the hybrid FPGA area will vary slightly.

the increase in cluster area and the decrease in inter-cluster routing area will almost balance each other.


The problem stems from the fact that TE and YL have values that are typically in the order of a few hundreds parts per million (ppm).

the probabilities in (1) and (2) are very small.


Due to the huge potential variances in device characteristics, microarchitectures can no longer be designed with an egalitarian view of hardware resources.

.xed parameter leakage models and optimizations will become increasingly less e.ective because they can only target the fraction of chips which have no imperfections, ignoring the ma jority of chips which have signi.cant on-chip variations.


The procedure is based on the idea that n-to-1 multiplexers are generally decomposed and implemented by smaller muxes ordered in a tree structure [1]; therefore, in order to minimize the probability that a fault occurred in a crossbar cannot be traced it is important that the registers are assigned following the rules reported in Table I.

it is mandatory that registers encoded with a bit string having Hamming distance equal to 1 are assigned with different logic values, in order to detect stuck-at faults that occur on the selection of a register in both writing or reading operations.


SVMs accomplish thistaskby mapping thedatapointinto ahyperspace, and then determining the position of the point with respect to the decision boundary, which is a hyperplane generated during training.

the distance of the point from the hyperplane is the basis for classi.cation.


We .nd that for ............ .., functional scan test can detect most of the functional failures due to all three types of injected faults.

all the 100 functional failures each due to stuck-at fault and bridging fault can be detected using functional scan test.


Besides ourtechnique,an alternativeideaistoincorporatethe partial assignment into the MWIS problem.

we could enumerate some partial assignment choices associated with each segment.


We make the following observations: If there is a finite state-path of length m+1 where q=true in all the m+1 states, then this finite segment is also the prefix to an infinite path where q is globally true (a witness loop).

if there is no path from initial states I(s) of length m+1 where q is true in all the m+1 states, then the property F(¬q) is proved correct.


For on-chip and on-board applications, it is important to be able to estimate the effect for single wires rather than complete transmission lines, and with a rectangular rather than circular cross-section.

wires with high aspect ratios Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro.t or commercial advantage and that copies bear this notice and the full citation on the .rst page.


The objective function (1) seeks to minimize the sum of CS values, and consequently, constraint (4) will be met in a way that minimizes the CSi,j values.

cSi,j will be set to exactly 1 only for those cases where a load of clock i is used in column j; otherwise, CSi,j will take on value 0.


In general the burst length has more effect on the quality that the burst occurrence itself.

quality degradation is larger for a .xed awhen pvaries than when avaries for a .xed p. As expected the performance obtained by repetition FEC is better than that of XOR FEC specially for values of alarger than 5%.


US I N G IN C R E M E N TA L QBF F O R BMC O F IN C O M P L E T E DE S I G N S In this section we present an application for incremental QBF solving, namely proving unrealizability of a safety property P in an incomplete design (those containing socalled blackboxes) using BMC.

we prove the existence of a path of length k violating P no matter how the blackboxes are implemented.


However, due to the instinctive di.erence between radio and acoustic communications [1], protocol suites that have been designed for radio networks cannot be used directly in UANs.

a new networking framework is needed for UANs.


Then, in lines 7-18, at each iteration, the algorithm systematically generates new candidate set partitions starting from the set partition chosen from the previous iteration.

in the .rst iteration, the algorithm starts with the initial set partition P0 = {{e1},{e2},...,{en}} with ngroups, each group containing exactly one edge.


(3) Using sweep line and interval tree, detect conflicts between polygons by finding overlapping pairs of rectangles that belong to different polygons and record the conflict edge pairs.

fig.3 the conflict graph is derived from the conflicts between features In AltPSM, we can remove all phase conflicts by assigning opposite phases to each pair of adjacent nodes in the conflict graph G. This can be formalized as bipartization (making 2-colorable, or equivalently, ensuring no odd cycles ) of the conflict graph G. if the conflict graph G is not bipartite, we must delete enough edges such that no odd cycles exist in the remaining modified conflict graph.


Local 0.2 variations that are beneficial in a strong-PMOS technology are likely to be detrimental in a strong-NMOS technology.

the best-case and worst-case tails of the distributions of various metrics may switch.


Furthermore, massive VLIW random testing was impossible with the sequential test generation method resulting in several post-silicon escape bugs.

scenarios that combined hardware loops with VLIW contained bugs that should have been found on the third stage.


When transforming from H nocm-1 to H nocm, each of the IES requires an extra pair of ports, resulting in a steep increase in the number of required ports.

h noc1 and H noc5 respectively have 13.2% and 19.4% fewer buffers compared to a mesh.


The results can then be used to identify high priority sensors and to invest a given security budget in the most cost-effective way.

4.1 Attack models We consider the case when the state of the system is measured by a sensor network of p sensors with measurement vector y(k)= {y1(k),...,yp(k)}, where yi(k) denotes the measurement by sensor i at time k. All sensors have a dynamic range that de.nes the domain of yi for all k. all sensors have de.ned mini min max mum and maximum values .k, yi(k) .


These bounds are tighter than those from [2, 8] in all relevant cases.

we never use input-independent rotation gates.


As the end goal is to achieve energy scalable radios and because of the large amount of data parallelism that is typically exploitable in wireless baseband algorithms, we leverage on the SIMD paradigm to translate reduced bit-width to less energy.

we exploit the fact that multiple data (sub-words) can be packed together and operated on as a single word.


Detailed analysis showed that the accuracy of linear and spline-based regression models remains almost stable and constant in the selected range of training set size.

for the targeted set of Box-Cox transformations, the average normalized error remains between 25% and 13.5% for the linear regression, while between 21% and 11% for the splinebased regression.


In this paper, we develop an efficient importance sampling algorithm to capture the rare failure event of SRAM cells.

we adapt the Gibbs sampling technique from the statistics community to find the optimal probability distribution for importance sampling with minimum computational cost (i.e., a small number of transistor-level simulations).


4.1 Data Sets Each failing test pattern is transformed into a data instance, based on the feature extraction procedure described in Section 2.

multiple data instances are derived for each failing chip.


We say that wiring pattern i is dominated by wiring pattern j.

the wiring pattern library should maintain only a set of non-dominated wiring patterns for an e.cient implementation of the wire sizing algorithm.