Distance-Based Weighting Even considering island-style FPGAs, the standard VPR range limiter technique described above suffers from the artificial constraints of a hard rectangular bounding box.

it completely disregards locations outside of the range limiter window even though it does consider equivalent locations inside.


PM RUN CYC counts the non-idle processor cycles at physical thread-level.

it .lters out those processor cycles during which a particular physical thread is idle and, therefore, constitutes a suitable proxy to estimate physical thread-level utilization.


In comparison, most of the physical features are extracted from multiple sensor axes.

sensor fusion is performed at the feature level for physical features.


In this paper, we study the technology migration problem for designs with strong RET-driven layout restrictions, i.e., RDR constraints, which require devices (gates) to be placed on a coarse pitch and in a single orientation.

we study the legalization problem with on-pitch constraints for devices with an objective of minimum layout perturbation.


Note that current ICLUS = {Iclusi} = {Iclus1, Iclus2, Iclus3, Iclus4} discharging from clusters depends on the input vectors.

for an input vector, we can obtain ICLUS; and then with ICLUS, we can find IST = {ISTi} = {IST1, IST2, IST3, IST4} = F*ICLUS.


Due to a variety of nonidealities, signals in a circuit block might not propagate from input to output in an exactly unique direction.

the reverse gain is nonzero and should be modeled by the backward signal path, as shown in Fig.


For a fair comparison, we apply a global runtime performance constraint rather than a per-interval constraint.

any core can be chosen in an interval as long as the accumulated runtime up to this point (including all core choices made on earlier intervals) remains within 10% of the EV8-alone.


The coarse grid matrices are then cheap to compute and generally as sparse as the original .ne grid matrix.

as we have denoted the conductance matrix G as .ne grid matrix Af which is symmetric and positive de.nite, the coarse grid matrix is computed from the Galerkin formula Ac = RAf P = Af P which P T implies that Ac is cheap to construct using .. (Ac)= akl (2) ij k.Gi l.Gj the entries in the coarse grid matrix are obtained by summing the entries in Af that connect the di.erent aggregates.


Currently, all the assays are programmed by hand and it is very complex to program droplet operations for more than two assays performed in parallel on-chip.

the end user should not be burdened with any programming tasks and the operation of the biochips should ideally be completely transparent, wherein the user only has to specify the assay protocol and input the liquid samples.


We note that in the evaluation phase, the regression simulator usually can run about 1000X faster than the statistical simulator.

it can be a fast and approximate simulator for the statistical timing simulator with high accuracy.


(14) t |Bkt |Bk 2  3.4 Inductive Algorithm A more abstract representation of (14) and (13) helps to simplify subsequent use and also clari.es some of the dependencies.

applying (14) and (13) can be denoted as f k-1 (v|b)= Vt |Bk-1 () G fV k (v|b),d(v- vR(tk )),d(v- vF (tk))(15) t |Bk where G is an operator that maps three PDFs to a single PDF.


BACKGROUND In this section, we will explain how MRF inference maps to an energy minimization method for the stereo matching problem.

we describe the preprocessing part of this method, Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.


As a .nal remark, we note that, due to performance reasons, some nonlinear lookup tables are stored in such a fashion that the output bits of the functions they represent are represented as a permuted and sparse sequence.

this takes place in optimized implementations of ciphers such as the DES, where the actual lookup table action is merged together with a bitwise permutation.


This pruning criterion affords us some important simplifications to the problem.

it is not necessary to measure each receiver's receive rate Rk, which, due to its dynamic nature may be hard to measure accurately.


Use internal representations that are suitable for hardware, embedded software, or compiled simulation generation from the same models.

actions that are speci.ed in C++ can be emitted to back end tools in VHDL or Verilog.


In this paper, we investigated techniques to incorporate temperature-awareness into high-level synthesis.

we developed two temperature-aware resource allocation and binding algorithms that aim to minimize the maximum temperature that can be reached by a resource in a design.


A 50 MHz clock specifies a clock tick of 20 ns period -which means that we cannot wait out the (minimum) active time of 50 ns exactly.

the fidelity of a statemachine wait , will depend on the clock rate: @50 MHz, 3 ticks will wait out 60 ns; @100 MHz, 5 ticks will wait out 50 ns.


In this work we will study the power minimization problem at the logic synthesis level.

we will work on technology mapping for FPGA circuits using dual supply voltages.


Since , , and are r D1 D2 Dio Djo independent, simple expression derived in Section 2 can be used.

the CDF at node o can simply be rewritten as Co = Cr .


We observe that, for all the designs and for all the area and timing constraints, we achieved the same or better results as compared to the approach of [12].

we notice that the savings achievable by the multiple virtual ground methodology of this paper increase as the area constraint is relaxed.


It enables the realization of a quantum memory for light, which is required for many applications in QIS.

it is necessary for scalable implementations of quantum information networks.


To quickly determine the range of a distribution so that we can decide if the Monte-Carlo sampling should stop earlier, a 3-sigma bound measurement is used.

after the .rst k samples, we test to see whether the 3rd standard deviation above the mean is smaller than the value of the reference line (likewise, we test to see whether the 3rd standard deviation below the mean is larger than the value of the reference line).


CONCLUSIONS Power supply noise has signi.cant impact on system reliability.

on-chip communication could easily incur power supply noise without proper isolation.


If the resistor R in fig 3 is negative, the circuit is unstable and the step response of the circuit diverges from the steady state, as shown in fig 3-b.

when t increases, the difference between the capacitor voltage and the steady state solution also increases.


Fortunately this case is easy to identify and .x: we simply unroll (or strip-mine) the loop body such that each epoch gets a block of iterations that perform all of the sequential stores to a given cache line.

we use blockcyclic rather than cyclic (aka round-robin ) scheduling, which is a common technique for avoiding the analogous problem of false sharing in traditional shared-memory multiprocessors.


The total rate of this transition is given by A~[p[ik],p[jk]], which is the sum over all nodes p' such that p'[ik] = p[ik] and p'[jk] = P[jk] of the probability of being in state (p', ik) given that we are in node p[ik], multiplied by the rate of the transition from ik to jk at level k. This transition will continue to affect later levels until all the arcs corresponding to the transition are self-arcs.

if p[ik] = P[jk], then the corresponding arcs at the next level will all be self- arcs, and e will not affect any other levels.


Therefore, the use of the interface can be extended to non-competitive applications.

we want to use multiple WiiRemotes simultaneously to incorporate more expressive interactions.


For timing optimization, we use a standard path-based counting technique.

we seek to minimize both net cut and path cut during recursive bisection.


MEASUREMENT METHODOLOGY The .rst goal of the measurement methodology is to obtain the capacitance values for the global wires used for  Figure 1: Measurement setup routing, as this information contains proprietary technology details and it is unavailable to us.

xilinx Virtex-II Pro devices are the target technology considered inthiswork.


Custom Feedback Control with g Global Feedback Links (CF-g): Custom feedback control is the most general control architecture that encompasses FC and FD control as special cases.

cFg corresponds to FD control augmented with exactly  .M .


For a positive edgetriggered D-type flip-flop, the pin C1 is connected to the clock and the pin C2 is connected to the complement of the clock; on the other hand, for a negative-edge-triggered D-type flip-flop, the pin C2 is connected to the clock and the pin C1 is connected to the complement of the clock.

both the positiveedge-triggered D-type flip-flop and the negative-edge-triggered Dtype flip-flop are implemented in the same circuit structure except for the opposite clocking schemes.


Modern designs are often pipelined to be shallow, resulting in a small D. As we will see the best values of Ct are around 8, so a typical operating regime will have Ct = D. In practice, when Ct = D, it should be possible to keep C F 2.

we need at least Ct leaf routes to handle the leaf interconnect serialization, which is also enough to handle node serialization when Ct = S. Since Ct = D, we will have depths that need more than one context for routing, Cti .


But, compared with the proposed approach, it has another cause of performance penalty.

it needs to advance the local clock during the idle period to be synchronized with the global clock while the virtual synchronization does not need to synchronize two clocks but adjusts the time stamp values after executions.


In summary, the ratios of improvements demonstrate that on average, AIG rewriting performs better than traditional synthesis.

the results of technology mapping for FPGAs confirm that literal-based optimization in MVSIS does not reduce area and delay while AIG rewriting reduces both.


Thus, we introduce a quantile-based time-to-failure which can be interpreted as certain quantile of the time-to-failure distribution.

it is the actual time when chip meets certain reliability target.


INTRODUCTION While the progress in electronics thus far has relied on the scaling of transistors and an increasingly complex maze of interconnecting wires, future advances in circuitry will require mating CMOS technology with new types of fabrication technologies, device principles, and circuit architectures.

power dissipation limits and the interconnect bottleneck at high integration levels, coupled with the inherently low drive capability of small devices, will mandate the use of relatively simple, ultrasmall devices laid out in highly regular arrays and interconnected predominantly locally all done with nanometer-scale precision.


The width of this rectangle (the proximity distance ) de.nes the complexity of our model.

it signi.es how large an area of the IC is assumed to in.uence the temperatures in the node under consideration.


Determining Cases of Scenarios to Improve Coverage in Simulation-based Veri.cation Shuo Yang1 Robert Wille1,2 Rolf Drechsler1,2 1Institute of Computer Science, University of Bremen, 28359 Bremen, Germany 2Cyber-Physical Systems, DFKI GmbH, 28359 Bremen, Germany {shuo,rwille,drechsler}@uni-bremen.de ABSTRACT Functional veri.cation of complex designs is still dominated by simulation-based approaches.

coveragedriven Veri.cation (CDV) is well acknowledged and applied in industry.


In order to add noise to our simulations we considered the methods described in [10] and [19].

we generated additive white Gaussian noise (AWGN) with 0 mean and 10mV standard deviation (a reasonable value for a 22nm technology node), RTS noise with values of the amplitude equal to 50mV , and we considered theFast Slow corner library that represents theworst-case scenario.


As for BIST schemes, included the BIST controllers in [6, 7], and the sticky bit comparator in [2], none of them is generally FS with respect to its possible internal faults.

for all these schemes, the critical block is the output comparator.


Since, the process is supposed to be ergodic, any equilibrated trajectory {xt} induces an equilibrium probability current jxy between any pair (x, y) of states.

jxy is the average number of jumps from x to y per time unit observed in an in.nitesimal time interval dt.


As a result, we can subsequently apply O1.

we can invalidate all H s corresponding tracking entries because H is residing now at its SHT.


Then, the second-most frequently occurring data inputs should be mapped to a bit-string with the secondlowest Hamming weight and so on.

a coding is desired which leads to patterns with Hamming weights as shown in Table I(b).


We have also assumed, for purpose of illustration, that if a slack goes below 90% of its nominal value (due to variations), then this would be considered a timing failure.

we resimplyusing 90% of nominal slack instead of 0 as the threshold for failed slack.


Case IV: We explore another possibility with a sampling period higher than the one in Case III.


Among side-channel attacks, fault attacks seem to be easiest to realize [2].

cRT-RSA proved to be susceptible to fault attacks.


The minimum width constraint of implant layers changes the traditional placement and post-layout gate sizing problems.

beyond existing constraints such as timing, power and area, additional geometric information of cells must be considered.


They are exceptional ly stable in practice.

clock skew (from which we derive PUF bits) does not change if the delays of all clock paths change by the same amount should the chip be baked or frozen.


The nondeterministic behavior is provoked by the usage of the dedicated carry lines in FPGAs over a given threshold of 89%.

our experiments suggest that in order to obtain a good entropy source inside a Xilinx FPGA, it is sufficient to use the carry chain over 89% and to place the rest of the logic blocks in the same region (around the carry line).


As a result, if one were to only look at the unary state machine every three clock cycles, s/he can observe similar transitions in a binary stochastic FSM with three times slower clock speed.

every pair of (x1,x2) presented in one clock of the binary stochastic are equivalent to three consecutive bits in the unary stochastic implementation.


Silicon and simulation results demonstrate the efficacy of the DREAMS methodology.

virtual data is used to demonstrate that the DFM rule most responsible for failure can be reliably identified even in light of the ambiguity inherent to a nonideal diagnostic resolution, and a corresponding rule-violation distribution that is counter-intuitive.


In the former, improving the slacks of a subset of paths does not guarantee an improvement on total negative slack (TNS) or worst negative slack (WNS).

.xing one failing path can cause several passing paths to fail.


At the same time, the larger the load, the smaller the ZTCV.

the ZTCV of a cell with fast input transitions and heavy load is smaller than the ZTCV of a cell with slower input transitions and smaller load.


1, we find out that the probability that the data stored on the array will survive the first failure is only 0.368.


Since the fabric constraint has been employed in the mapping process, we can realize that the consecutive mapping of different bits, e.g., 01 (1 after 0) or 10 (0 after 1), creates the pitfall of invalid path creation during expansion.

if we expand, using short edge in this work, at the second level of the mapping of 01 (1 after 0) or 10 (0 after 1), an invalid path will occur.


We presented designs for stochastic image-processing circuits that outperform existing designs (both conventional and SC) in most aspects.

we have designed an edge-detection circuit that is strictly better than equivalent conventional designs.


Therefore, in order to obtain the maximum number of localized arrays, we need to eliminate these two kinds of con.icts.

we need to determine a proper direction for each edge in this array1 loop1 array1 loop1 array1  loop1 array2 loop2 array2 loop2 array2 loop2 array3 loop3 array3 loop3 array3 loop3 array4 loop4 array4 loop4 array4 loop4 (a) (b) (c) array1 loop1 array2 loop2 array3 loop3 loop3 Figure 6: Global Optimization.


The diagram also shows some of the hardware (light purple) and software (light green) components of a SoC in which the audio subsystem is integrated.

this is an application processor on which an application software stack is executed and from which the audio subsystem is controlled.


We split the signature for the PC from the signature for the other architectural state due to implementation issues.

the IES sometimes needs to be updated in the Execute state for control flow instructions (i.e., if the core determines that a branch was mispredicted).


flag = false repeat if RLL(X) # tagp go to L flag = RSC(X, [p, seqp]) until flag L: if (flag) Implementing read, write It is straightforward to extend our algorithm in Figure 2 to implement read and write operations in addition to LL, SC and VL operations.

the implementa- tion of Write(p, &#169;, v) is the same as the implementation of SO(p, (9, v) with the following changes: replace the CAS on Line 8 with write(X, [p, seqp]) and remove Lines 12 and 13.


In this paper, we propose several improvements to substantially increase the scalability of automated abstraction.

we show how a better integration between the BMC engine and the SAT solver is achieved, resulting in a new hybrid abstraction engine, that is faster and uses less memory.


Note, for instance, that at 2KHz, the frequency discrimination is more than 1Hz.

a human subject cannot tell 1,999Hz from 2,000Hz.


In addition to error counts, the BG systems also record information on the mechanisms that were used to correct errors, which we can use as additional clues regarding the nature of errors.

both BG/P and BG/L provide separate log messages that allow us to distinguish multi-bit errors, and BG/P also records information on chipkill errors (i.e.


In the following section, we will reveal a novel approach that does neither demand extra logic for the communication, nor restricting the placement of recon.gurable modules by the static system.

this permits to migrate modules among multiple di.erent static systems without any additional synthesis or place and route step.


Multiple methods were adopted in Merom verification to make coverage practical and reach optimum return on investment.

we determined that a significant portion of the testing space could be dropped with a minimal impact on quality.


The monitor must be able to detect patterns on di.erent levels of abstraction.

it is often not su.cient to only observe data on bit-level but also observe associated bits as chunks on the word-level, e.g.


[0,N m -1], and Hm is the CTF within the useablesubcarrier band.

the received SPs can be expressed as: mm m YP(()) = HP (()) k + WPk (2) k (()) where Pis the pattern vector storing SP indexes.


More importantly, for workload consolidation with each application mapped to a near convex region [5, 4], DBAR dynamically isolates routing for each region.

the DBAR algorithm has neither intra-nor inter-region interference and provides su.cient adaptivity for congestion.


To provide a basic comparison between this difference in the models of SGX and Iso-X, we show the effect of a statically provisioned compartment memory region on a system where the overall memory pressure is high.

we created a virtual machine with a total of 1000MB of RAM and the host .le system cache disabled (i.e.


EVALUATION In this section, we evaluate SPOT s accuracy as a tool for metering energy and power for a typical sensornet workload.

we evaluate SPOT s dynamic range, resolution, and stability, which represent the most challenging requirements for an embedded power meter.


The abstract tree has only merging point and child node information.

after abstract tree generation, we do not know where clock bu.ers are inserted.


To make the switching activity estimation more flexible, we extend the TCin matrix to support every possible scheduling and binding.

for every two compatible operations Oi and Oj, we pre-calculate the TCin values for scheduling order (Oi .


3.8 Area overhead In this paper, we use an ATCache with a caching ratio of 256.

we use a 46kB cache for caching total tags amounting to 11.5MB (256MB/16-way DRAM cache).


Some interesting observations have been established during the error simulation phase: The model checker can increase the length of the test sequences generated starting from one witness.

it can produce a witness W of length L and other witnesses, for the same rule, which include W , but are longer than L. This extra e.ort in the generation of further witnesses is useless since, such longer test sequences never increased, in our experiments, the error coverage.


3) Formal veri.cation of quality: In ASLAN, we utilize formal veri.cation methods to guarantee that the safety and liveness properties described above are preserved during synthesis.

we employ time frame expansion, a technique widely used in sequential circuit analysis and veri.cation, on the SQCC to verify the validity of the approximate circuit.


Let y be a circuit node, val be a functional requirement, and t be a temporal requirement.

the Boolean function TCF(y=val, t+) characterizes the set of input vectors that, when evaluated, can cause node y=val to be stable later than time t. given an input vector x, the Boolean function TCF(y=val, t+) is equal to 1 if and only if node y=val is stable later than time t when input vector x is applied.


The most important observation from these .gures is that under packet loss, most packets are classi.ed to the interferer that was activated during the experiment.

on average SoNIC correctly attributes most of the packets to the dominant interference source.


This paper thus addresses the issue of variability-aware design of energy-delay optimal linear pipelines that are aimed at operating in both the near-threshold and super-threshold regimes.

this goal is achieved by deriving optimal delay line configuration included in the soft-edge flip-flop design for the near-threshold and the super-threshold operations.


The self-recon.guration uses the diagnosis information to only bypass (recon.gure) the defective portion of that con.guration.

in each iteration, only a partial con.guration, only for the defective portion of the previous con.guration is generated.


Liedtke introduced Guarded Page Tables to address this problem [18].

guarded Page Tables allow for path compression.


No matter in write-1 or write-0 operations, one of them suffers from VGS degradation, as shown in Figure 3(b).

the biasing condition of the access transistors in the 4T-1J cell is much worse than that of a 1T-1J design.


Therefore, groups have to be well utilized for holding faults.

a partition scheme should scatter bits originally in the same group into di.erent groups and prevent faults from meeting in the same group in a re-partition.


G (x, z, x', z') - j.µ(s+ j.e )G (x, z, x' z') = 0, i > 0, z = 0 (2) i iii the point (0, z ), while the second one represents the effect of an opposing current (negative sign) lying at the point (0, -z -2/.).

solving (1) and (2), using continuity at the interface the effect of the substrate is represented, in this boundaries between different regions, results in an integral approximation, by a single image of the source line current.


If vhas label aiand the successors of vare labeled aj, ak, then ai-ajand ai-ak.

for each path, the sequence of labels along the path is strictly increasing with respect to -.


As a result, the accuracy of .oating-mode analysis can be re.ned to take into account the early stablization of the .rst test pattern.

a signal x has arrival time 0 if both the .rst pattern and the second pattern of a test vector impose the same stable values at every signal in the transitive fanin cone of x.


2.3 Performance For a high-performance core, it is critical to maintain the core performance when reducing its power consumption.

commercial high-speed links target a set of markets where bandwidth performance is often fixed by industry standards.


When the linear system for the interior point method becomes highly ill-conditioned, it is usually possible to identify many noncritical constraints.

the linear program has two constraints for each absolute value term from equation 4.


3D integration also provides new opportunities for future CMP design, with a new dimension of design space exploration.

the heterogenous integration capability enabled by 3D integration gives designers new perspective when designing future CMPs.


Our results indicate speedup of up to 20X when counting overheads, and up to 50X when using techniques to overcome these overheads.

we show that our techniques are valid for small device counts, which is typically a well known problem for accelerated parallel computing with communications overheads.


Different from the motion of doping front in the solidstate memristor, the domain-wall movement in the spintronic memristor happens only when the applied current density (J) is above the critical current density (Jcr) [12][13][14][15][16] [17][18].


In the cache with BPS, the power density of the hot spots is minimized through a more uniform distribution of the power dissipation sources, and thus the peak temperature is significantly lowered.

the BPS reduces the peak temperature about 7ºC on average.


To simplify our validation approach, we only consider samples where the output levels are greater than 0.9 Vdd or less than 0.1 Vdd since any output values greater or less than those values can be thought of as being in steady-state.

comparisons are made only when the output voltage from the noise-free inverter is at Vdd or GND.


For each application we measure the fraction of loads that has a certain probability of precedence correlation.

more than 95% of the loads exhibit an 80% or more precedence correlation.


There is, however, one serious restriction when we use trace excep- tions; normally operating system requires that the exception handler should not cause any page fault [9].

all the codes and data structures used by the exception han- dler should be pinned.


Prefetches to open banks are given priority, prefetched data are brought into the LRU position of the L2 sets, and prefetched commands are given low priority in the memory controller.

the SRP prioritizer receives feedback from the memory system and issues prefetch commands only if the channels are idle and there is no pending request from the L2 cache.


The C-Tag works executing the same stages of a real tag: data receiving, data decoding, command executing and response sending.

it reproduces the Digital Block behavior under many conditions, following the ISO 18000-6B standard.


Experimental results show that our algorithm leads to averagely a 2.00×cost reduction for test cases, compared with a reasonable heuristic.

only our algorithm can solve the length-ratio-matching routing problem well for all cases.


The main target is further reduce system latency, but throughput is often also increased.

router nodes observe their local recent traf.c, and rapidly enter or leave a special biased mode which allows an uncontended cut-through path.


1.1 Working Set Identi.cation It is well known that a program doesn t use its entire memory space all the time but in fact uses subsets of its memory space at di.erent periods of time.

a program s runtime can be divided into several phases such that the set of pages touched by the program in each phase (the working set) is more or less constant.


Note that as the subset of ISEs selected is different for different applications, the content of the control memory is different for each application.

the JiTC architecture achieves .exibility by changing the content of the control memory and thereby instantiating different ISEs per application.


In this paper we are tackling this challenge and adopt static hardening-mapping/dynamic scheduling policy.

once the hardening and mapping decisions of all processing elements (PEs) are done, the tasks mapped on each PE are locally scheduled according to the scheduling policy of that PE.


In this paper, we propose a multi-patch generation technique by interpolation with cofactor reduction.

our method considers multiple errors in the design simultaneously and generates multiple patches to .x these errors.


Therefore, even if the optimal clock skew scheduling is applied, the smallest feasible clock period is still 16.

in this example, if we adopt the register binding solution obtained by left edge algorithm, the clock skew cannot be utilized to further improve the circuit performance.


In the high-Vth netlist, the signal MTE exists only at the top module.

mTE does not exist in sub-modules in a hierarchical netlist.


The AD schemes presented in the previous subsection can be used in conjunction with the power-down technique by applying them to the enabled parts of the cache.

in addition to the parts that are disabled, one can also reduce the leakage power of the active parts by applying the AD schemes.


Condition 2 ensures that a new event is not scheduled after a previous event of the same type has already been processed for a node.

when an event is processed for a node, it is the final event of that type for that node.


However, these results con.rm that the overall accuracy of the proposed method is not considerably sensitive to the accuracy of SP values.

it is possible to use less accurate SP values (tractable for large circuits) to achieve a reasonably accurate SER.


The last phase (backend) has concerned with the logic synthesis where the whole set of VHDL files have been synthesized to generate (by means of Mentor Graphics Leonardo [6] and Xilinx Design Manager/EDK [5]) the bitstream for the target platform: the Xilinx Virtex-II Pro FPGA family [5].

it has been used the Memec Design Virtex-II Pro Development Kit [19].


dE jdisplacement = E (2) dt In order to qualify as quasi-static, the .eld must be mostly (quasi) time-invariant (static).

for a sinusoidal time j.t varying .eld E = E0e: jdisplacement E = .


When there are two errors there is a chance for miss-correction.

the checker that assumes the correct implicit value will detect double error whereas the other will behave as if there are three errors.


The research presented in this paper aims to compare a number of approaches to overcome noise during objective evaluation.

we compare two re sampling techniques and a probabilistic approach proposed by Hughes (2001).


Token-based global arbitration enforces considerable power and delay overheads in the case of highly saturated network under hotspot traffic.

the proposed architecture achieves power reduction of 52%, 61%, 47%, and 50% over OXbar under uniform, hotspot, local, and FMT workloads, respectively.


Thus, sPGOPT increases while VDDOPT decreases as the number of cores per die increases unlike the GC case.


We discretize the pass-band of the filter and represent it by K discrete frequency values {hk; k = 1,2, ,K}.

instead of solving the unknowns {µn; n = 1,2, ,N} as continuous variables, we constrain the solution space to a set of discrete values defined by {hk; k = 1,2, ,K}.


These hard blocks have .xed locationsand must communicateoverafairlylong distance.

second, high-bandwidth, bit-serial wires can save area in lowcost devices like Cyclone and Spartan which have a restricted amountof interconnectavailable.itiseasyto generate large designs using EDK and SOPCBuilder; these tools generate complex systems interconnected by a word-oriented crossbar-like fabric.


It can be seen that although the DDC generally reduces the amount of tra.c, there are also cases where it generates signi.cantly more tra.c than the direct-mapped cache.

for gsm-dec at 2kB, it produces a factor of 3.2 more tra.c than the direct-mapped cache.


I. INT RODUC T ION The multi-gate MOSFETs are considered to be among the best candidates to extend the CMOS technology into the 14 nm node [1].

gate-All Around (GAA) devices, closely followed by FinFETs, can be scaled to the shortest channel length possible for a given gate oxide thickness [2].


This sequence satis.es all assumptions, but does not trigger P2.

to create the meaningful scenarios for which P2 was written, the test bench must drive input sequences where r2 is asserted.


Existing work on a VJ-driven mouse has demonstrated the suitability of the system to 2D control [3].

the VJ mouse application enables the user to navigate a windows/icons/mouse/pointer (WIMP) interface using only the voice.


To summarize, a communication algorithm helps to manage the complexity of SAMR data transfer operations by separating grid-dependent details from the variables and operations involved.

a communication algorithm depends only on the variables and operations involved and is independent of a particular grid con.guration.


Pre-Executing Loops Involving Difficult-to-Prefetch Array References Following the fashion that we pre-execute pointer chains, we can also pre-execute array references across multiple loop itera- tions (see Figure l(b) for an illustration).

we are interested in cases that present challenges for the compiler to prefetch.


Using a path of a lower length for testing implies a sub-optimal coverage of certain defect sizes.

we calculate the number of SDDs for which the overflows lead to substantially shorter paths.


Speci.cally, parity check can only detect single bit errors.

it can not detect multiple bit errors and can not correct any errors.


To evaluate AMG s vulnerability we injected faults into its execution and demonstrated that AMG is naturally resilient to numerical errors.

in most cases in which AMG converged correctly, it did so in the same number of V-cycles as during non-faulty runs.


Since CUDA is an extension of C/C++ language, we choose the compiled code approach in this work.

the input RTL HDL is source-to-source translated into equivalent CUDA code for parallel execution.


In this paper, we presented a number of basic physical design problems, and showed why traditional techniques would fail to produce reasonable results.

we overviewed traditional partitioning, floorplanning, placement, and delay estimation techniques, and highlighted their shortcomings for producing good results for modern FPGAs.


We target to generate time-critical sub-cuts from bigger cuts.

given a cut in the CUO, our objective is to enumerate, heuristically, sub-cuts in the critical paths of the CUO.


It is then able to output the .eld coverage analysis.

the algorithm requires a list Ls of all the nodes positions and Figure 5: Field coverage analysis algorithm.


The most prominent design method is related with faulttolerance support at the routing level.

e.cient implementations of fault-tolerant routing solutions are provided within the NaNoC project, such as LBDR [1] and FDOR [3].


To eliminate the dependency of the placement problem on terminal propagation, Huang and Kahng [11] introduced exact objectives (e.g., minimum spanning tree) to drive the partitioning process.

net vectors are used as means to quantify the global contribution of each cut and to eliminate the need for propagation.


Failure boundaries µ1, µ2, and µ3 represent values for the duty cycle of the clock signal under investigation and they are ordered such that µ1 < µ2 < µ3, thereby making µ3 the most aggressive failure boundary to reach among the three.

µ1, µ2, and µ3 are chosen to be 13.7%, 24.9%, and 34.4% over the nominal output, respectively.


Essentially, the problem is that measuring the cost of individual events is only useful for determining how critical a single event is.

standard cost gives no information about the content of secondary critical paths.


One appeal of this approach is that application tuning has the potential to completely remove a resource wall, by eliminating communication, while changing the ef.ciency of the protocol only has the e.ect of moving the resource wall a little further out.

from an overall application performance perspective, it is far better to change the algorithm to remove communication (if possible) then it is to create hardware mechanism to make the communication more e.cient.


SOC MEMORY ALLOCATION Based on the memory controller described in Section 3, we developed a methodology to optimize the memory organization of the entire accelerator.

after the designer has selected an implementation for each process, it is possible to determine the number of parallel memory interfaces that each data structure requires to ensure a su.cient amount of memory bandwidth to the processes.


The comparison takes into account only those pairs of signals that gave rise to extremely dif.cult combinational equivalence problems.

the signals that appear in the plots of this section are only those that ZChaff, Berkmin and SCGLeicut could .nish within 2 hours of CPU time.


Since the Data memory is accessed at about 50-60ns (at the average case), and the major part of the queue handling is done in parallel with the data access, we claim that our system introduces minimum latency.

in terms of latency, you get the queue handling almost for free , since the DMM s latency is about the same as the one of a typical (support only read and write) DRAM subsystem.


This is mainly because the spatial locality of instruction accesses in the standalone cache is not disrupted by the SPM, thus making the BB method especially effective for reducing instruction cache leakage energy.

we observe that the HDG, CD, and PD methods do not work well on the rijndael benchmark.


Presence information can be carried by using the Presence Information Data Format [15].

some specific SIP methods for the presence service (PUBLISH, SUBSCRIBE, NOTIFY) are used.


For this document [15], there are three such text regions, corresponding to text columns that are over white backgrounds.

the given region Rj has a summed probability of 1.0, which represents its relative probabilities over all region types.


Introduction The components offuturemulticoreprocessors willbecomeless reliable as technology scales,becauseindividualdevices areincreasinglysusceptible to a variety ofhardwarefaults[6,8,10,12,34,36].

technology experts warn about an increase in intermittent faults faults which occur frequently and irregularly for a period of time, commonly due to process variation or inprogress wear-out, combined with voltage and temperature .uctuations[6,8,12,13].These arein addition to transient faults(or soft errors), typically caused by particle strikes, and permanent faults, which occur repeatedly after adevice sustainsirreversibledamage.


Unfortunately, the sub-90 nm technology nodes have experienced the increasing constraint of decreasing yield landscape.

the inability of process engineers to guarantee the necessary process window across the entire design space has led to a sharp increase in the number of systematic layout geometry induced faults.


A SAT solver was used to perform all aspects of Boolean functions manipulation during resynthesis.

it was shown how an optimized implementation of a node can be computed directly using interpolation, without first explicitly computing a don t-care set and then minimizing the logic function with this don t-care.


3.4 HLS-Speci.c Optimizations Despite very signi.cant advances in HLS, a variety of complementary source-level transformations are often needed to produce the best result.

.ne-grain parallelism exposure and explicit overlapping of computation and communications dramatically impacts the performance.


In general, for the results of both robustness analyses to be consistent, the ranking of slacks in terms of their robustness should be preserved.

the points should follow some straight line (not necessarily y = x, although y = x would be an ideal case).


Further, we remark that not only are the faults masked by these new system level redundancies dif.cult to detect, but they also have detrimental effects on the system operation.

they can cause a signi.cant increase in dynamic power consumption.


To this end, we recently proposed passive inspection [14], where passive refers to the fact that a sensor network does not have to be modi.ed to allow inspection.

we install a small number of additional nodes alongside the sensor network to overhear messages exchanged among sensor nodes.


Secondly, reachability paths may not span the n = IV[ ver- tices assumed by the above analysis.

for many graphs a smaller number of teachability operations may suf- fice.


Clearly, however, the ultimate assessment of regularity tradeoffs can only be made once the regular logic fabrics have CAD tools and design flows as mature as those for standard cells.

we know that our simple packing step for flow c substantially degrades the timing, and that there is much room for improvement.


Said another way, we assume homogeneous activity on all edges in the graph.

the asymptotic results are unchanged if we say every edge switches 10% of the time.


At .rst, we consider only the binary signature identi.cation, which implies that each obstacle does not have more than one signature.

if the measurement mi does not have the same signature to the track t, it means that the possibility to link these two elements is equal to 0.


In this work we investigated the implications of device scaling on sub-Vth operation.

we found that the slow scaling of gate oxide leads to 60% Ion/Ioff degradation in the sub-Vth regime.


Smaller k results in higher aw: using more pipeline stages for energy optimality.

if pipeline register induces less delay overhead for stages, we can use more stages for achieving an energy optimal design.


5.2 Lifetime Improvement Our first set of experiments is designed to measure the impact of NBTI and NBTI-aware job-to-core mapping on processor lifetime.

we look at different cases of process variations across cores, which result in distinct lifetime improvements.


time-randomised (TR) caches, is that in a TD cache each memory address is mapped into a .xed cache set and way.

certain bits of the address (called the index) determine the cache set in which the address is mapped, while the way is determined by the replacement policy.


Speci.cally, concentrating on a set of array-intensive applications that make frequent use of the disk system, this paper makes the following two contributions: We present an approach which, given a data-intensive application code, determines automatically the parts of the application code that can be executed on the smart disk system.

this approach, which is based on integer linear programming (ILP), partitions the application code between the host system and the smart disk system.


Signi.cant impact on power pro.le: The communication architecture directly controls the timing of system-level communications, and hence the execution of system components.

the communication architecture can be used to control the timing of component idle and active states, impacting the component s power pro.le.


As shown, for all the application, the corresponding curves in .gure 1 and .gure 2 show certain similarity because of applications s temporal locality.

we can use the distribution of few writes to predict the following.


Perhaps surprisingly, we show that this limitation of testing can be eliminated if testing is combined with a limited amount of formal veri.cation and if the machine is designed appropriately.

we show that for an election with N contests in which each contest involves selecting one out of k candidates, we can verify correctness with just O(kN)tests, instead of the O(kN )tests exhaustive testing would require.


Therefore, the WG-16 transformation WGT-16(Xd)can be computed using four multipliers in total, where two multipli ers are utilized for generating Y , one for computing Y 211 +1 -1 and one for calculating Y 211 .

thanks to the nice property for computing the trace of the product of any two elements with tower .eld representations in F(((22 )2 )2 )2 , ( ) Y 211 +1 Y 26 .16 Y 211 -1 the two multiplications and YY 211 (211 -1) inside the trace function have been replaced by bitwise AND and XOR operations, which reduces both hardware and time complexities signi.cantly.


When we increase the slack S1for Sink1 to 2 in Figure 3 (b), b0has tostay VddH restricted by S0 = 1.

b0 is restricted by both S0and S1, and VddL can only be assigned to b0 when S0 =3 .S1 =2.


if A has the known value zero, then the arrival time for the AND gate output is de.ned by the arrival time of A plus a small constant delay determined by the AND gate.


Between rules 1.BS---Marked-requests-first and 2.RH---Row-hit-first, weadd thenew rule PRIORITY---Higher-priority-threads-first.

given the choice between two marked or two unmarked requests, PAR-BS prioritizes the request from the thread with higher priority.


DATAPATH ABSTRACTION REFINEMENT The focus of our work is the application of the CEGAR framework, particularly the afore-mentioned enhanced refinement strategies, in the context of hardware correspondence checking.

we address the task of verifying that an optimized microprocessor implementation is compliant with its functional specification.


Fortunately, the Do-All problem can al-ways be solved as long as at least one processor continues to make progress.

with the standard assumptiou that initially all tasks are known to all processors, the prob- lem can be solved by a communication-oblivious algorithm where each processor performs all tasks.


Our characterization of soundness of simulations above expresses the importance of considering every instance (valid binding) of a sequence of instructions in its simulation.

we do not only deal with the semanticsof the abstract instruction,but withevery possible instance.


Thus the fairness property of the arbiter requires AG(H BU S RE Qm .¬maskm .

aF H GRAN Tm) for any master m. if m is requesting the bus and the arbiter believes that m has not been split, then m is eventually granted bus access.


7, whose basic structure has been introduced in [24, 29] for two-rail encoded self-checking circuits.

the circuit proposed here differs from those in [24, 29] for the presence of the comparator output stage (Fig.


The W1:W2 ratios are (a) 2:1 (b) 8:1 (c) 1:8 and (d) 1:1.  depending on the choice of the termination criteria and adaptive resampling methods.

false split reporting rate was high with the K-means and two-nearest-neighbor algorithm due to the shape of the final cluster not being a loop.


In [4], a Variable-VTH (VTCMOS) strategy is adopted in order to cut o. leakage current.

it applies back-gate bias by exploiting body effect.


Therefore, in this paper, we revisit virtual memory system design considering limitations imposed by .ash memory.

we study the effects of the subpaging technique and storage cache management.


In order to overcome these limitations, we propose to use higherorder logic theorem proving to improve the analysis in the domain of integrated optics or VLSI photonics.

this paper provides a higher-order logic formalization of optical microresonators which are the most fundamental building blocks of many photonic devices.


For simplicity of explanation, we assume that the states of MDP in Figure 1 are observable instead of hidden.

on-chip performance or power counters are readily available for all resources; if the states are hidden, expectation maximization (EM) [2] or other algorithms can be used to predict the state.


6 Design exploration The application described in Section 2 presents interesting implementation trade-offs that must be accurately investigated especially as regards its coexistence on the same hardware platform with other important engine control functionalities.

real time aspects (due to .ltering functions) of the knock detection functionality require early assessments of overall computational loads in order to carefully de.ne the hardware partition of the platform so to minimize cost without compromising performance.


CO., LTD {sp7.hong, sungjoo.yoo, hoonsang.jin, kmchoi, jkong, sookwan.eo}@samsung.com ABSTRACT We propose a new intra-task dynamic voltage scaling (DVS) method to capture an important fact of software runtime distribution and integrate it into DVS effectively.

the proposed method finds performance levels, for a given software runtime distribution, i.e.


Another challenging task is to preserve the placement quality after global placement during the full physical synthesis .ow.

legalization and detail placement, which are used extensively in any physical synthesis .ow, need more innovations.


A natural extension of this approach would be to allow dynamic overlapping of LEs in the topologically ordered processing flow.

in the above example, Ls may have been optimized; the subsequent grouping of Ls with its load Lt may provide added opportunities not realizable by optimizing them separately.


FB CONSTRUCTION In distributed FB (DFB), FB nodes are determined in a distributed way such that all sensor nodes are covered by FB nodes.

each node determines whether it becomes a FB node or not, based on not the entire network topology but its own local information.


Second, our definition of TCRIT gives the minimum TWL in order to write the cell eventually, but in practice a write operation must complete before the next operation begins.

if a read operation at the same address follows the write operation, it should return the correct value.


In this paper we propose solutions to extend recon.gurable hardware architectures with Trusted Computing functionalities, e.g., for use in embedded systems.

our architecture allows to include the TPM implementation itself into the so-called chain of trust.


Note that, although the source-relay link is not error-free, the relay still can cache some uncorrupted packets while overhearing the broadcasting of source.

for the expected scheduling time, the target packet may also exist at the relay besides the source node.


In this new case, OCEAN achieves comparable power savings as in the former case (see Figure 9).

we achieve 34% power savings between OCEAN and no mitigation, and 26% power savings in OCEAN compared to ECC.


Fortunately, the mapping be assumption that all the three pairs have either a 3 or 5, f must ** tween a cofactor and its boolean function implementation is a contain other minterms.

either f or fshould ¯ many-to-many mapping.


While this may not be desirable from the perspective of minimizing the average power, it may also not be possible, in the case where we cannot arbitrarily adjust the adaptive voltage.

if the upper range of the adjustable voltage is .nite, denoted by U, then the expected yield becomes lim(vtol .U-)Pr(.Vadaptive = vtol)p .


This way performance loss for any cache sample concentrates close to the average and hence, performance becomes highly predictable.

the highest standard deviation for each one of the .ve schemes is 3.1% for the Pellston-like scheme, 3.0% for wdis,3.6% for bit .x, and 1.9% and 0.6% for the cache subblock disabling scheme without and with predictability enhancements respectively.


HALF-PIXEL MOTION ESTIMATION REFINEMENT A characteristic that contributes to the high compression rates achieved by the H.264/AVC Motion Estimation is the possibility to generate fractional motion vectors (FMV) with half-pixel or quarter-pixel accuracy [2].

a movement that happens from a frame to another in a video running at 30  frames/sec is not restricted to integer pixel positions only.


our goal is to compute a new cell placement (for this group of cells) with reduced .


All labels of one role of A and all labels of one role of B are in the same process, but never together on any edges, then they are mutually exclusive.

all occurrences of A or B involve the process.


More generally, we represent an eye mask as a set L of undershoot constraints and U of overshoot constraints.

(s, a)in L has the interpretation that for all input patterns where the transmitted value for the wire and sample period of interest is +1, the received value must be at least 1-a.


These transformations are equivalent to pre-multiplying both sides of the equations in (MOP2) using non-singular matrices PE and PI .

(MOP2) can be rewritten as the optimization.


In this experiment, we use the same routing strategy proposed in [5] to ef.ciently route packets in the 3D NoCs that have random topology chips.

the best spanning tree root that can minimize the hop count is selected for each message class or virtual channel layer.


However, (1) the simple Rent s Rule spatial bisection we took to get p did not consider dividing wires and PEs by evaluation time, (2) we can get a pair of nodes at a PE that are the same depth from the input, and (3) there are designs where signi.cantly more than half the nodes are at depth 2.

in the general case, the con.guration memories may need to change at more than two di.erent times.


logically write data of pages p (p + len) back to their corresponding linked LBAs.

when the device driver plans to issue the command U NL INK (p, len) to unlink the mapping between pages l (l + len) and their corresponding len LBAs, it actually derives the starting memory address addrp for page p; then the device driver requests the memory controller to issue a real U NL INK command to request the PCM device to unlink the memory from address addrp for consecutive s bytes that equal to the size of len pages, so that accesses to addresses addrp (addrp +s) are not redirected to other addresses anymore.


All that is not part of the formal speci.cation.

the addition of clock inputs is crucial as this changes the interface of the module.


With this approach, the algorithm requires a small number of iterations, since the competitive phase is performed on the whole data set before computing the cooperative step.

the cooperative phase of the batch training algorithm is formulated using three steps.


When CPU (write) operation increased, it could write more data to the memory.

it executed more data and was able to write back to the memory.


Our implementation exploits the underlying LLVM constructs and information from the synthesis to e.ciently determine relevant post dominance information.

lLVM has a special select instruction of the form y = select cond x1 x2; the synthesis tool typically targets the condition variable of select instructions for operation gating.2 Function Find-Gating-Info crawls over the data .ow graph of CCDFG G, .rst identifying each select instruction; for each y it then .nds all variables that are post-dominated by y recursively.


In this section we explain how we run the experiments of Section 4.

we explain .rst how we performed technology mapping and then we explain the various choices we have made to create architecture description .les for VPR, in order to perform packing, placement, and routing.


falling onto or sitting down upon the couch), our hypothesis is that we will be able to train a classi.er to detect this difference.

there is some separation between the usual and unusual events, and we can use a generative model to distinguish them.


In addition, the algorithm tries to balance the CPU occupation through fair distribution of tasks over the available processors.

tasks that communicate most are grouped as far as they do not compromise more than 100% of CPU use for each processor.


The covering regions C Ri j form the collection of subsets S.  If the bu.er size bj denotes the weight of a subset C Ri j , then the ob jective is to pick minimum weighted sum of subsets such that each node has at least one subset covering it.

the mesh bu.ering problem is identical to the set cover problem with I .


A more important goal for such placement is to see if there is a constructive aliasing behavior between the accesses of the cache lines in the same group.

if the cache lines in the same group have similar access patterns, the saturating counter will be able to trigger cache line swap to the faster region earlier and help improving the performance.


V2 in the same connected component of G , v1 and v2 do not interfere, i.e., Resource interfere(v1, v2)= false.

the graph Gis pruned into connected components such that the total number of deleted edges from EA.nity is minimized and no two resources within the same connected component interfere.


The circuits used for experiments were synthesized from large Burst-mode asynchronous controller speci.cations [8] using the Minimalist and the SIS toolsets.

for single-output implementations, state minimization (min-states in Minimalist) and state assignments (assign-states -s -O -P in Minimalist) were performed by asynchronous tools while twolevel (espresso -Dso) and multilevel synthesis (script-rugged in SIS) as well as technology mapping (map in SIS) were performed using non-hazard-free synchronous tools.


As shown in Figure 14,Triple-A successfully reduces both kinds of contentions bydistributing the extra load of the hot clusters through datamigration and physical data-layout mapping, as the numberof clusters increases.

the link contention timeis almost completely eliminated while the storage contentiontime is steadily reduced as the number of clusters increases.This is because the storage contention time is bounded by (a) Without Triple-A (b) With Triple-A Figure 15: Breakdown of the average execution time of read micro-benchmark on a nonautonomic all-f ash array (a) and Triple-A (b) under varying network sizes.


when the number of original test patterns is high, the proposed method is able to achieve better savings, e.g., for s38417 and s38584.


3.1 HighLow-Bits Technique The HighLow-Bits technique identifies the accesses that are going to miss by examining the bit locations that are high (or low) in the address.

we store the bit locations of the tags that are high (or low) in all the stored blocks.


lets the delays be varied without varying the path delay vector as shown below: T ·(d +.


In general, 2D-HERT outperforms various optical architectures due to its simple all-optical data network and high-speed lowpower control plane.

averaging through different traffic patterns, proposed architecture achieves average perpacket power reduction of 53%, 45%, and 95% over optical crossbar, .-router, and electrical Torus, respectively.


Finally, since every cluster could operate using a different clock domain, we have also analyzed this issue for our intercluster barriers.

we have used two frequencies (300 and 600 MHz) that have been assigned throughout the 16 clusters in a combinatorial way (see x-axis in Figure 11).


In the above de.nition, the terms short and polynomial are relative to the size of the device, which is the security parameter.

short means linear or low degree polynomial.


It can signi.cantly reduce the number of distinct capacitances over all functional units in Fbig with the theoretical guarantee on approximation error.

we round down the capacitance of each functional unit in Fbig to the nearest value in the form of EL ' +t ·E2L ' where t is any nonnegative integer.


We leveraged this framework for variability injection and analysis to perform a Monte Carlo analysis, returning the statistical distribution of the design critical path.

the criticalpathdistributionfor eachpipeline stage was derived.


3.2 Bounding the Distribution of Circuit Delay We now show how we can derive a bound on the cdf of the longest path delay propagating through the probabilistic timing graph that has the properties defined in the previous section.

we derive an upper and a lower bounds on Ft( ) = P(max{D1...DN } = t) where Di is the delay of the ith path.


there exists a computational sequence for which m3 computes f. M is functionally complete for any n. Proof: Let fbe given in the conjunctive normal form (2).


For example, if the address is left blank, X-Gen will try to pick an address that will cause interesting scenarios, such as an address at the end of a cache line or an address that had been previously requested so that there is access contention.

xGen is capable of directing the test on its own instead of simply randomizing unspecified fields.


On applications manipulating large amount of null data blocks, such a ZC cache allows to signi.cantly reduce the miss rate and memory tra.c, and therefore to increase performance for a small hardware overhead.

the write-back tra.c on null blocks is limited.


We found that the drag times for auction, calc, .rstaid, image, jpeg, manyballs, mvideo, and pushpuzzle are 53%, 45%, 59%, 53%, 82%, 54%, 88%, and 48%, respectively.

the objects in our embedded applications spend a large percentage of their lifetimes in the heap beyond their last-use.


Now, suppose we have an algorithm to compute, for each potential defect function Di, the probability pij that e j is 1.

the algorithm outputs an answer for Di as Pi =pi1,pi2 pin].


DH (DV ) is de.ned to be the vector of horizontal (vertical) distances between driver and receiver terminals.

dH [n](DV [n]) is equal to tR.x-tD.x (tR.y-tD.y), for 1=n =N.


Our approach has lesser hardware overhead because we use the proposed gate replacement technique.

in most cases the power decreases by an additional 10% when internal nodes are gated o.. % of Nodes Inserted Figure 5: Scan shift power reduction Vs di.erent percentages of gating logic.


No further aspects ofthe implementations need to be contributed by the developer.

microarchitectural aspects, such as the pipeline structure and its control are not de.ned.


Based on (17), it can be seen that for an RWG edge i, only (fsp)it, 1 and (fsp)it, 2 are non zero, and all the other (fsp)i,·* = 0 .

only adjacent RWG edges and triangular panels can have interactions in fsp .


Thus, we approximate by iterative greedy local re.nement.

for each wire we greedily compute the repeater solution that locally minimizes exactly once.


is a PE for the execution of the corresponding task in T. With the allocation map, each task ti is associated with an execution time pi .

pi is the time to execute ti on PE pk = F(ti ).


Computer-aided design and reliability research community has also seen an extensive research on analyzing the aging of integrated circuits.

ring oscillator based reliability analysis has become a common practice.


By retaining the topics from Google News and not just the articles, we are able to incorporate current trending topics as well as de.ne a separate set of long-term topics we wish to track.

there are 2,000 popular long-term news topics, such as the Syrian Revolution and North Korea, that we always search for regardless of if they make the front page of Google News.


Thus, for any 0 = z = Dij , the skew is within the bound Bz =[tskew z (sr,sl),tskewz (sr,sl)].

if |evi |=0, the 0 minimum and the maximum skew are given as tskew (sr,sl)=K and t 0 sr,sl)=K.


We propose min-cost network .ow based method to optimize the power consumption while maintaining the feasibility of the design.

we enhance the min-cost .ow algorithm to handle discrete non-convex timing models.


In this paper, we describe a case study in formally verifying a widely used SoC bus protocol: the Advanced Micro-controller Bus Architecture (AMBA) protocol from ARM.

we develop a formal speci.cation of the AMBA protocol.


To handle the aforementioned transient soft errors in flash, common practices adopt ECCs in SSDs.

lDPC, a kind of advanced ECC, is appealing and promising in SSD design nowadays.


Therefore, the To the best of our knowledge, there is no previous work spatial locality results in the power sources being in thermal-aware architectural optimizations for caches.

concentrated in a small area in the memory bank, which our two main contributions in this paper are: raises the temperature of the hot spots.


However, with cache capacity as the limiting factor causing increased cache turnover, the FIFO caching algorithms have little control over which cache entry is replaced at which time.

in a different movement scenario with highly non-unitbrm behavior between different nodes, FIFO cache replacement would force the replacement of all paths (containing nodes with different behaviors) to be treated equally.


However, RL has the highest throughput in m_type3, m_type4, m_type7 and m_type8.

when there are many masters with long job length or the job lengths of all masters are similar or the same to each other in a system, the round robin arbitration schemes show the highest performance.


On the other hand, the voltage variation of the heavily loaded bitlines takes a significant share of the dynamic power consumption.

dynamic power consumption is important in write operation since it requires high voltage swings over the bitlines.


Starting with the seminal work on automata-theoretic and deductive synthesis from speci.cations (e.g.

[31, 37]), there has been steady progress on automatic synthesis.manyrecent techniques(e.g.


It is easily seen that on each curve, the Tox value at which the leakage begins to change at exponential rate is about 17° A.

for the entire range of ToxLo candidate values of 12°A, it is clear that A through 15°our choice of ToxHi =17° A is reasonable.


This keeps the backend portion of the product life cycle (Post Si to product qualification) on schedule.

optical probers and Focused Ion Beam (FIB) systems rely on pre-placed PDFD features for navigation, logic and timing modifications, and signal probing.


The special property of our switch is that the path search results can be acknowledged within a predictable, very low time limit under certain policies like retry-for-free-path or no-retry.

worst case delay can be bounded in those policies.


http://dx.doi.org/10.1145/2668332.2668377 Chih-Hang Wang Department of Computer Science National Tsing Hua University superwch7805@gmail.com Po-Yu Chen Department of Computer Science National Tsing Hua University chenpy@mx.nthu.edu.tw built on different platforms.

web services provide network functions through web standards and protocols (e.g., HTTP, XML and SOAP).


The cores in the mesh based layout are aligned along a grid.


However, FPGAs consume more power, are much lower in performance, and come with substantially higher units costs when compare to cell-based ASIC.

fPGAs are unsuitable for certain higher performance, higher volume applications, or those applications with low-power requirements that are best met with cell-based ASIC technology.


Several techniques have been proposed in the last years for achieving ef.cient implementations of modular multipilcation.

blakley s method [5] and Montgomery s method [6] are the most studied ones.


Two new parameters are introduced for CKZ: r describes how many blocks are replicated, and k describes how many times every block is replicated.

k will demonstrate how many kernels are involved in cross kernel.


A Markov chain is used to model the characteristics of the physical channel, and three methodologies are established to compute the MTTF, MTTR, MTBF and availability values in terms of the parameters of the channel.

the Rayleigh fading radio model is considered and analytical results are provided.


The argument is straightforward: if there is a satis.able assignment for g, it is also an unsatis.able assignment for f, which means all the clause in f must be false.

the decomposition that corresponds to this assignment does not violate any constraint and is thus a compatible .nal decomposition.


the vocabulary, was separately determined for each taxonomy by a process of feature selection based on the notion of Shannon Entropy3 .

let LN and LD be the set of keywords appearing as labels of nodes in a given taxonomy and as words of documents in a given dataset respectively.


5.1 Memory Model Comparisons 5.1.1 DRF Both HRF-direct and HRF-indirect are compatible with a DRF model.

any program that exclusively uses system-scope synchronization and is free of ordinary data races will be sequentially consistent with either model.


The C Block in Figure 4 imposes routing constraints that must be satisfied in order to deliver input signals I0 and I1 in the correct order to the SD-MUX inputs.

i0 and I1 must be routed on routing segments w6 and w7; the order is irrelevant, i.e., either I0 can be routed on w6 and I1 on w7, or vice-versa; similarly, I0 and I1 must be routed on w4 and w5 as well.


3.4 Veri.cation procedure Although to describe the feasible set one just needs to solve problem 5 for different values of ., the question of an ef.cient veri.cation procedure still holds.

we wish to .nd out how many instances need to be veri.ed to guarantee that a new instance will in fact meet the required speci.cations.


On the other hand, the 3D-Opt scheme reduces the costs by about 82% and 69% on average for the single-core case and the multi-core case, respectively.

the best 3D design generates much better results than the best 2D design.


result has an error bounded by E (Approximately Correct).

if one desires to simultaneously guarantee the success rate and the result quality of the learning, then the learning problem can be hard.


While some algorithms, e.g., analytical placement, tend to produce consistent results on multiple runs, our techniques can be used to tie the results produced by different placement algorithms and implementations to each other.

placement predictions made by a fast estimator can be enforced at a global scale when a slower placer is used to optimize wirelength and various design objectives.


As a result, going beyond a given processor size increases only the overheads without bringing any performance bene.ts.

using more processors than necessary can have devastating results from the energy consumption angle.


By renaming quanti.ed variables, the quanti.ers of Formula (1) can be removed.

formula (1) can be rewritten as the quanti.er-free formula of (2) because existential quanti.cation is implicit in satis.ability checking.


3.2 Testing Performance and Design Coverage In this section we examine the cost of on-line testing.

we examine the bandwidth requirements for on-line testing each component (i.e., number of vectors required to fully test a component), the area costs of our test harnesses, and we compute the overall design defect coverage.


We conjecture that if one were to constrain a system implementation so that performance monotonicity is strictly satisfied in all cases, then it would rule out many performance optimizations that significantly raise average performance.

by guaranteeing performance monotonicity, one would reduce average performance only to avoid relatively rare cases where performance might degrade slightly.


This software has been built making use of Placelab [13], a set of open-source libraries useful for developing a positioning system.

we used the spotter functionality provided by Placelab.


These two lines show us the high potential of post-silicon skew adjustment.

one extra register (or two extra registers) and optimized resource binding achieves 100 % yeild of the operation with the clock period 37, and 80% with the clock period 33.5 (32.7 for two extra registers).


We will instead focus on the process of starting a series of new tasks and identifying the maximum level of server consolidation that can be achieved.

we will attempt to co-schedule N applications on to S servers, and devise techniques that allow us to minimize S, while ensuring that QoS guarantees are preserved.


SIGNAL INTEGRITY MODELING The 50% delay of the i-th line can be determined by letting the response signal be 0.5vsi in (11).

(b) nn I vi (t)= sikskj vsjpk (t)=0.5vsi.


After such partitioning, we undo all the partitioned blocks but we keep the node locations as assigned by the partitioning.

we uncouple the placement of a node for use in terminal propagation from its block location.


There are many ways of fragmenting one unsigned multiplication into a set of narrower multiplications and additions.

the number of different fragmentations of an m×n multiplication into five multiplications and four additions, obtaining at least one k×l fragment is (m-k+1)×(n-l+1)×16 (being m=k and n=l).


Striking applications of our pipeline could be in the .eld of metabolic engineering of a whole biological network.

we propose a general and automated way to optimize biological models and assess their optimal solutions.


We can identify each operation of S by the loop indices (br,bc,r) of the surrounding loops, but as each operation of S writes 8 values, we need an extra index to distinguish the di.erent values.

we identify each created value by its indices (br,bc,r,c), as in the original array.


Once d is found from (4), the updated response x~ can be easily calculated from (5): x~ = x + d. In most practical cases, a power grid network is often updated with local changes and, hence, the problem unknown d in (4) is sparse.

the incremental change of the power grid voltage is almost zero at many internal nodes, as will be demonstrated by the numerical examples in Section 5.


* Denote by Wu,i the upper bound after iteration i and * ** W the lower bound after iteration i. W = W and l,i u,0 u W * = W * .

instead of querying the oracle with .,wequery l,0 l it with (a series of di.erent) .. which forms a geometric sequence converging to ..set .


ACKNOWLEDGMENTS The authors would like to thank Udeepta Bordoloi, Michael Chu, and Patricia Harell from AMD Stream Computing Group, Santa Clara, for their support and detailed technical discussions leading into implementing these algorithms, as well as for providing the GPU hardware used in this study.

discussions with Dr. Bordoloi was a basis to much of the analysis of our results.


5 is known to have a hysteresis property, meaning that a stronger-than-normal input voltage is needed in order to flip the output state (which has a larger inertia).

we need a much higher voltage to change the output of a ST inverter from 1 to 0 , and much lower voltage to change the output from 0 to 1 .


That is, once a process group and channels are built, this information cannot be altered during runtime.


Such a representation represents an approximation that is good enough to capture the effects of faraway C4s (which supply a small, but not zero, fraction of the current to the active partition).

we ensure that the effects of faraway regions are accounted for at just the level of accuracy required, but that computational ef.ciency is enhanced.


Based on the estimate rk, we predict that the next Rpeak will occur, at most, .r k seconds later.


Previous work has shown that coscheduling to the maximum supported level on modest (up to 8 way) SMT is in general best, [33] and [23] showed that cases of negative symbiosis are rare and actually required (to exhibit it in that study) crippling the base SMT con.g- FRACi = (19 - pi) / (19 - pj ) uration to arti.cially create bottlenecks on system resources.

j=1 There are two related factors in a schedule that can boost utiliza-jobs get scheduled for a fraction of available cycles tion.


The tied gate wraps around the .n, and it s W is twice the height of the .n plus the .n width TFIN .


However, the linear support vector machine (SVM) used in SB can be easily fooled in high dimensional [15], nor can it e.ectively deal with multiple failure regions.

if the existence of multiple failure regions is known, it has to use multiple classi.ers to .nd out each failure region respectively [17].


The library we use permits us choose the most reliable resources for a specific task.

instead of increasing reliability through redundancy, we achieve reliable design by using different versions of the components (as allowed by area and performance bounds).


These variants consist in considering respectively the Hamming Weight or the Hamming Distance of the four output bits of the Sbox1.

we defined two sets of power traces according to the value of the HW or HD, rather than to the value of one output bit.


The shift in energy above the nominal for each of these designs is due to overheads inherent in the PDVS architecture.

the increase in energy comes from ELEAK through the off VDDH power switch while the VSUBVT power switch is on.


From the dataset, a positive correlation between IPC and dynamic power consumption has been observed.

higher IPC contributes to higher dynamic power dissipation, and vice versa, which leads to a positive slope c1.


As Figure 3 (a) shows, the distribution for the PC quantity drops greatly as the number increases from 2 to 12.

the case with 12 unique PCs only appears in less than 1% of the execution time.


An important observation made by one of the prior studies [10] is that, in executing array-intensive codes in a chip multiprocessor, not all the cores are used all the time.

at any given time, certain number of processors are idle and can potentially be switched off or put in a low-power operating mode to save energy.


analytical techniques for bounding the distributions of probabilistic interval variables are proposed.


Another advantage of the LHPN model over our previously published HPN models is that the systems can be modeled more compactly which results in smaller state spaces.

the HPN diode models presented in [18] require over 2000 zones to represent the state space while the LHPN models require 132 zones or less.


The ratio of phrase-aligned snippet Ours Random Boundary Alignment 75% 15% We also tested the computational complexity of our algorithm, with Pentium IV 1.8G running Windows XP, the snippet extraction process can be completed in less than 5% of the time-length of the music.

for a music clip of 4-minute long, the processing time is about 10 seconds.


Multi-pathing involves striping the data at the source and sending it across multiple overlay paths thereby leading to a better achievable throughput.

multiple independent routes can be employed to simultaneously transfer disjoint chunks of a .le to its destination.


In other words, awareness of micro-level errors (i.e., bit errors) is translated into policies that have macro-level impacts in terms of execution failure, performance, energy consumption, and QoS.

we explore a Drop and Forward Recovery (DFR) mechanism (shown in Figure 3(c)) that drops a current encoding frame and moves forward to the next frame once an error is detected in a mobile video encoding system.


As can be observed from Table 3(a), when resolution is poor (= 4), a rule with high GAVR and low yield loss confounds the EM formulation of [4].

the formulation of [4] only identifies the rule most responsible for yield loss when its corresponding .k is extremely high (i.e., out of 18 table entries, 17 are .k=1.00 and the reaming case is .k=0.90).


The effectiveness of the methodologies has been evaluated by generating transactors of two different types: for standard and nonstandard RTL communication protocols (see Section 2).

transactors have been generated for the the following RTL designs: AMBA AHB Bus.


The relatively low test coverage in these modules is due to ATPG untestability of some portions of the combinational logic.

no test patterns exist that can set a combinational node to a speci.c value (lack of controllability), or propagate a combinational node s value to an observable node (lack of observability).


For those functions that are not found in either filter, only 20% of them are implementable.

any function that is not found in either filter has a high probability of being non-implementable, and one can drop it (i.e., considering it as non-implementable) without significantly degrading the quality of synthesis.


Since each SRAM cell has crosscoupled inverters, each inverter is used to charge the gate of the PFET device of the other by storing the proper value to the cell before transitioning to recovery mode.

a 1 needs to be written for recovery of the left PFET devices of the cells (CL) while a 0 needs to be written for recovery of the right PFET devices of the cells (CR).


4.3 Auditory Scene Categorization To better evaluate the performance of the auditory scene categorization with co-clustering algorithm, we first do some minor corrections in the key element spotting based on the available ground truth information.

we delete the noise from the key element list of A2, and add the pure gunshot to the list of A4.


In adaptive routing algorithms, a packet can travel from a source to a destination through multiple paths.

adaptive routing algorithms can be used to avoid congestion by adapting the routing decision to the network status.


Acknowledgement: The authors would like to acknowledge contributions from several members of the Advanced Test Technology group at Intel Corporation.

contributions made by Sanjay Sengupta, Dhiraj Goswami and Rathish Jayabharathi are greatly appreciated.


The different subspaces denoted by capital D , followed by their dimensions.

d2 -D9 refers to (.bt;k - .bt;k )/.bt;k .


We believe that, due to its two unique features, the G4-FET could potentially open a new direction for efficient VLSI design.

not only it enables more efficient designs as a universal and programmable gate, but also, by enabling coplanar line crossing, removes one of the main constraints in the circuit design.


A larger but more aggressive multipumped design can also exploit banking to reduce the number of cycles required to perform reads: each bank can perform two unique reads, and all banks can operate in parallel; when reads are completed, one pair of writes can be performed across all banks each cycle until all writes are performed.

the block RAMs are read like a banked memory and are written like a replicated memory.


Assume that routed wire segments do not cause a coloring conflict in ICG.

no such conflict cycle occurs in ICG composed only of determined vertices and edges.


The origin of this near cancellation and doubling stems from the observation that, after some algebra, the L contribution for these modes may be written as L y z ( d 0 e x ' f x y z dx dy dz (25) whereas the P contribution becomes: P w2 t n f 0 y z dy dz (26) y z both with the same integrand function f x y z .

the P matrix elements, divided by w2, are the collapsed version of the L ones, up to a sign according to whether the element correspond to two modes traveling in the same or opposite sense along the z axis.


The first two have been previously described.

among the solvable systems, those corresponding to the test cubes with the maximum number of defined bits are first selected (first criterion).


i when computing the upper bound of PZ( = z), the intervals with the lower bound Zi no larger than z need to be considered.


Although the maximum skew deviation in Column 6 is only 1.4 ps, the actual skew deviation for a register can be much larger due to the discretization applied in our scheme.

registers might be attached to any location within a bin.


the proposed full adders require the least area, which can also be considered as one of the factors for the enhanced performance.


For example, when RSM uses n random variables and k order polynomial function, it has total Cn 1 + Cn 2 + ··· + Cnk terms and thus APEX requires Cn 1 +Cn 2 +···+Cnk simulation samples.


Given the ability to match cuts to the PLB, the cut enumeration procedure was augmented to ensure that only cuts that are implementableby thePLB are made available to the technology mapper.

we can either .lter cuts usinglibrarymatching after or during cut enumeration.


coef(C) mod coef(N) = 0, where upper_bound(N), lower_bound(N) are bounds of the loop of iterator N; coef(N) is the coefficient of iterator N in index expression; mod is the modulo operation.

all moving iterators should have coefficients that evenly divide each other and for any two iterators the greatest coefficient should not be less than the value on which the loop with iterator with lesser coefficient can change the value of the index expression.


Memory models~ for example, are used to emulate the main memory system in an ARM-based configuration.

they allow the specification of various access times for memories.


The constraint associated with the backward places in the FBCN model are implemented by constraining the upper (m) bound of the auxiliary variable fc .

the t(m)-tc term represents the free-slack of channel c in mode m. This free-slack represents the maximum time the channel can be stalled without impacting the target cycle time.


gorithms and the selection of the components and architecture fault model.

the designers focus on the control al *This research was supported in part by the Marco/Gigascale Systems Re- Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE 04) 1530-1591/04 $20.00 &#169; 2004 IEEE Figure 1.


The design issues such as tile mapping, routing path allocation, link speed assignment have to be re-considered when voltage islands are used.

the design complexity grows significantly with the number of allowed islands.


{(nil, nil)}, P(Pi(msg, p), *) and P(Pj(msg, p), *) are computationally indistinguishable.

each honest party s messages are indistinguishable from those sent by at least k -1 other honest parties.


5, both active-decoupling circuits achieve better decoupling effect especially at higher frequencies, compared to the capacitive decoupling circuit.

the proposed active-decoupling circuit achieves the best decoupling effect to suppress high-frequency substrate noise due to the result of wider -3dB bandwidth achieved by the amplifier with feedforward compensation.


In addition, in the ULV regimes, the small (10-20mV) VT difference out of layout modifications can become sufficient to control driving strength due to the exponential impact of VT on transistor drain current.

the proposed method can benefit driving a large tors, exhibits similar delay-energy performance when LVT tran sistors works at Vdd=0.35-0.38V.


However, any exclusivity conditions still apply to each vector individually.

the t =0- vector must satisfy the external exclusivity conditions, and so must the t =0+ vector.


First, the bottom and top TSV-to-wire interfaces are subject to higher current density due to current crowding.

current is signi.cantly crowded at the bottom-right corner for Z=1um.


However, additional measures are required when the MTCMOS methodology is applied in the design of sequential logic circuits.

storage elements such as latches and .ip-.ops present state-retention problems during the stand-by mode since the .oating virtual ground disconnects the storage nodes from the power supply leading to the corruption of the stored data.


In practice, since many requests do not .nd a supplier node and need to go to memory, Lazy snoops more.

in SPECjbb, threads do not share much data, and many requests go to memory.


The timing diagram of the above step 3) can be drawn as Figure2.

update-DR is active on the dotted line, and Cature-DR is active on the bold line, thus 2.5 TCKs is required from Update-DR to Capture-DR. it can be seen that it takes 2.5 TCKs from the application of interconnect test patterns through output BSCs to the observation of test responses on input BSCs.


The clock tree topology (CTT) that speci.es the hierarchy of the branch nodes within the clock tree can greatly affect the delay uncertainty introduced along the clock paths [18].

as the common portion of two paths in a clock tree increases, the delay uncertainty between the leaves of these paths is likely to decrease.


The practical way is to generate some samples from D and run Monte-Carlo simulations to estimate d(a).

generate n samples drawn from g(x, p) and estimate d(a)as d(a)= 1 .


To see this, the .nal value of the lazy variable is implied by value assignments of free variables in the sat solution.

the values are found by simulating the value assignment on the free variables.


Several other scheduling policies such as [1, 8, 11, 12, 14] have been proposed to prioritize requests with an aim to increase the overall performance of the system.


in computing the average/maximum/minimum over all values kept by the sensors.

if the data to be transmitted from the sink node is a sum of values measured by the sensors, then aggregation would mean summing up the values received before forwarding them.


As indicated above, an e.ective representation is one which is well matched to what it represents.

an intuitive, or well matched, representation is one which clearly captures the key features of the represented artifact and furthermore simpli.es various desired reasoning tasks.


Comparing the solutions produced by the various multi-resource partitioning algorithms we can see that there is a considerable amount of variability on the quality of the .nal solutions.

in the absence of V -cycle re.nement, the quality of the solutions produced by MP are signi.cantly worse than those produced by either MC or MPMC.


This .gure highlights that laser sources (assumed to be Continuous Wave) must be treated in a different way.

as the insertion loss is not the same for each path, CW lasers can be sized accordingly.


It can be observed that, AC A4 and GDA44 achieve smaller delays when compared to RC A and C LA, but are associated with higher hardware and power cost.

aC A4 has about 5.93% smaller delay than GDA44 , but consumes 66.45% more hardware area and 7.97% more power.


For (ii): Anything not contained in P cannot be in Q either.

a cache miss in P must also be a cache miss in Q.


4 Prototype Performance Aside from the delay circuit s ability to span the required delay range, we also require that it be able to pass the high data-rate signals (up to 6.4Gbps) with minimal distortion.

since the delay circuit contains 7 active components, it might be susceptible to jitter (and other noise effects) which accumulate as the signal passes through all the 7 stages.


3.2 Deadlock-Free Routing Algorithm Our routing algorithm is designed to maximally utilize resources in faulty networks that result from the application of our Fine_FM.

it can be applied to discover deadlock-free routes in any irregular network with unidirectional links.


The main problem related to the generation of the SEFSM is that, from a timing point of view, the SEFSM can be not equivalent to the REFSM.

a SEFSM may require a larger number of clock cycles to reach a particular area of the DUV than the REFSM.


To estimate the effects of soft errors on such circuits, we develop a general computational framework based on probabilistic transfer matrices (PTMs).

we apply them to evaluate circuit reliability in the presence of soft errors, which involves combining the PTMs of gates to form an overall circuit PTM.


Our results show that many factors in.uence the appropriateness of the delivery architecture including: the characteristics of the virtual environment, rate of movement, distribution and density of avatars.

we note that peer-to-peer delivery has sig Figure 8: Effect of virtual world density on resource usage multicast performance with varying numbers of POPs lying network supports multicast (if the number of ISPs is large).


Conceptually it encourages a binding of computations with their related data closely within one island, and allows synthesis algorithms to focus on global inter-island communications.

the datarouting logic should be optimized by any synthesis algorithm targeting DRFMs.


As the .rst three conditions are already covered by event register 1, the value for event register 2 can be found to be 1101 to cover the remaining condition ABCD = 1101.

the trigger unit has to detect on the available trigger signals when Z = ABCD = 1011 OR ABCD == 1101 in order to capture the targeted trigger event Y = 1 in this example.


gives us an idea of the minimum necessary speed sacrifice to obtain cycle estimation.

we can observe that execution time is multiplied by 1.69 in average.


Even during the transition time, requests can still be served by other enabled links due to the existence of in-HMC crossbar networks.

long sleep and wakeup latency only a.ects the promptness of our scheme in adapting to application characteristics.


The model has the same problems as the others we have discussed.

the uncertainty about resources of others is ignored.


The key to designing a microprocessor that can achieve both high scalar performance and high throughput performance is to dynamically vary the amount of energy expended to process each instruction according to the amount of parallelism available in the software.

if there is little parallelism, a microprocessor should expend all available energy processing a few instructions; and if there is a lot of parallelism, the microprocessor should expend less energy in processing each instruction.


We write the objective function of the design-time optimization as (1): Prob(Jitter(a) = f¯), (35) where a is a vector which represents the number of unit cells used in the charge pumps.

it represents the value of ICP1 and ICP2.


Minimizing the Hamming distance between the tags of classes that are visited successively is useful in reducing the disks energy consumption.

for a given disk in the I/O system, in going from one class (node) to another, it is better to keep the states of the disks (active or idle) similar as much as possible.


3D-fast represents the combination of all of these previously proposed techniques, and we use this highperformance con.guration as our baseline for comparison in the next section.

our reported performance gains are in addition to those already providedbythis 3D-fastcon.guration.


In this paper we present some modelling ideas that can contribute to the full exploitation of the synthesis capabilities of this new formalism.

we show how these expressive features can be used to design a set of IP modules that can interface high level description of components of the system to the complex bus elements that often compose the communication infrastructure.


3.3 Data Flow of Intra Prediction For the intra prediction, only parts of the PEs in the systolic array are used.

the predictor is produced by the .ltering of boundary pixels with the .lter taps being (1, 2, 1) or (1, 1).


For example, in Figure 4b, the R1.R0.R2 turn is disabled to break the anticlockwise cycle.

the routing algorithm prohibits messages to go from R1 to R2 & R3 via R0 to avoid packets from deadlocking.


This new approach to speculation has a signi.cant performance bene.t.

since the output from the if branch is available in the third step, the .nal output is produced in the fourth step itself.


There are also some FFs that serve as both backward FF and forward FF at the same time and we call it bidirectional FFs.

for this type of FF, if we move them backward, it can help to eliminate the suspicious FF in its fan-in cone or change itself from suspicious to non-suspicious while if moving forward, it can be helpful to eliminate suspicious FF in its fanout cone.


We review previous approaches to this problem in the more general setting of linear dynamical systems (Lacy & Bernstein, 2002; Siddiqi et al., 2008), then describe a simple approach that works well in our setting.

by appealing to Gershgorin circle theorem for eigenvalue bounds (Golub & Loan, 1996), we show that stability is guaranteed by imposing a simple £1-norm constraint on the model coe.cients.


A highly compact and ef.cient design was obtained taking advantage of the architectural characteristics.1 1.. Introduction The ever-increasing demand for security, along with several crucial requirements like performance and tamperresistance, has caused in the recent years an increasing deployment of hardware devices to support security services, such as con.dentiality, authentication, integrity and nonrepudiation.

asymmetric, or public-key, cryptography plays an important role in all modern security-aware applications, since it has the fundamental property of enabling This work was supported in part by the Italian National Research Council (CNR), by Ministero dell Istruzione, dell Universit` a e della Ricerca (MIUR), and by Regione Campania, within the framework of following projects: SP1 Sicurezza dei documenti elettronici, Gestione in sicurezza dei .ussi documentali associati ad applicazioni di commercio elettronico, Centri Regionali di Competenza ICT, and Telemedicina.


One pre-eminently reasonable measure of the value of data is the uncertainty we still possess after learning it.

we are interested in how uncertain we are about x*; as given by the covariance of our Gaussian mixture equation (13).


We propose to obtain this pattern by exposing the layout information of disk resident data to the compiler.

the proposed compiler support obtains disk access pattern by using data access pattern and disk layout information for array data.


Essentially, the processes of clustering auditory scenes and revealing likely co-occurrences of audio elements can be considered dependent on each other [4].

the information on semantic scene clusters can help reveal the audio elements co-occurrence and vice versa.


and the average batch size; accordingly, the traffic intensity remained also constant in all experiments.

we fixed TABLE II SUMMARY OF PARAMETERS AND RESULTS IN THE SECOND SET OF EXPERIMENTS On-Off-Batch Iterations Mean Jitter Skewness HGeo[12, 8, 16]-Uniform[28, 40]-Constant[5] 4 13.222 7.340 0.158 Binomial[8, 0.625]-Constant[34]-Uniform[1, 9] 9 14.085 8.004 0.182 Uniform[4, 8]-Binomial[44, 0.75]-HGeo[20, 5, 20] 5 13.369 7.646 0.266 Constant[6]-Binomial[44, 0.75]-Binomial[10, 0.4] 4 13.161 7.356 0.167 response time distribution 0.06 0.05 0.04 0.03 0.02 0.01 0  5 10 15 20 25 30 Figure 9.


The source driver supplies the desired voltage level (called grayscale voltage) according to the pixel value.

ideally, the transmissivity t(v(x)) is a linear function of the grayscale voltage v(x), which is a linear function of the pixel value x.


The shaded region represent overlaps between two DAGs where the same fundamental nodes are used for both constants.

the shaded regions represents implementation savings due to sharing common subexpressions between different DAGs.


Instead of directly applying Shannon decomposition to the entire circuit, in the proposed approach, first we apply hypergraph partitioning to generate cohesive partitions of the circuit and then choose only a subset of appropriate partitions for supply gating.

the paper makes the following contributions: 1.