In contrast, PuM architectures enable computation to occur within the memory array.
Impactful works in this domain have proposed mechanisms for the execution of bitwise operations (e.g., AND/OR/XOR) [1]}, [2]}, [3]}, arithmetic operations [4]}, [5]}, [6]}, [7]}, and basic LUT-based operations  [8]}, [6]}.
Operations in PuM are usually performed between multiple memory rows.
This fact, combined with the use of vertical data layouts and bit-serial computing algorithms [10]}, [11]}, [12]}, enables a very high degree of parallelism, since there can be as many execution lanes as there are bits in each memory row.
However, the flexibility of PuM architectures is limited by the range of operations they support, and by the difficulty of using these operations to express higher-level algorithms of interest with sufficiently low latency and energy costs.
