Within each CE, there exist a fixed number of im-memory processing elements (imPE), a multiplexer, a switch, an analog-to-digital converter (ADC), a shift and add (S&A) circuit, and a local buffer [1]}, as shown in Fig. REF (c). The ADC precision is set to four bits to avoid any accuracy degradation. There is no digital-to-analog (DAC) converter used in the architecture. A sequential signaling technique to represent multi-bit inputs is adopted [2]}. Each imPE consists of 256\(\times \) 256 IMC crossbars (the memory elements) based on ReRAM (1T1R) technology  [3]}, [4]}, [1]}.
This work incorporates a sequential operation between DNN layers since a pipelined operation may cause pipeline bubbles during inference [6]}, [7]}.
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