For our last exploration study, we explore the benefits of introducing AIMC tiles for CNNs in an 8-CPU core MPSoC. Contrary to the previous studies, where each layer weights are used only once per inference, convolution operations require multiple passes on weights per inference via shifting kernels over the feature maps. To perform the convolution operations in AIMC tile-enabled applications, we flatten the kernels into columns and store these in the columns of the AIMC tile, as described in [1]}, [2]}. The feature maps are also flattened and queued to the AIMC tile.
