The most widely-used quantization technique for microcontrollers is the fixed-precision uniform affine quantizer, where a real number is mapped to a fixed-point representation via a scale factor and zero-point (offset) after training [1]}[2]}. Variations include quantization of weights, weights, and activations, and weights, activations, and inputs [3]}. While post-training quantization (with 4, 8, and 16 bits) has been shown to reduce the model size by 4\(\times \)  and speed up inference by 2-3\(\times \) , quantization-aware training is recommended for microcontroller-class models to mitigate layer-wise quantization error due to a large range of weights across channels [1]}[2]}. This is achieved through the injection of simulated quantization operations, weight clamping, and folding of special layershttps://github.com/quic/aimet. To account for distinct compute and memory requirements of different layers, mixed-precision quantization assigns different bit-widths for weights and activation for each layer [6]}. For microcontrollers, the network subgraph is represented as a quantized convolutional layer with vectorized MAC unit, while special layers are folded into the activation function via integer channel normalization [7]}[8]}. Recently, binarized neural networks [9]} have been ported onto microcontroller-class hardware [10]}, where the weights and activations are quantized to a single bit (-1 or +1).
