Figure REF  shows the high-level overview of the proposed neuromorphic hardware simulator, which facilitates cycle-accurate simulation of the interconnect and the processing tiles. Each tile models 1) a processing element, which is a neuromorphic core, 2) a router for routing spike AER packets on the shared interconnect, 3) a local memory to store cluster parameters, 4) buffer space for spike packets, and 5) AER encoder and decoder. NeuroXplorer's hardware simulator can perform exploration with transistor technologies such as CMOS and FinFET that are used for the neurons and the peripheral circuitry in each tile, and Non-Volatile Memory (NVM) technologies such as Phase-Change Memory (PCM) [1]}, Oxide-Based Resistive Random Access Memory (OxRRAM) [2]}, Ferroelectric RAM (FeRAM) [3]}, and Spin-Transfer Torque Magnetic or Spin-Orbit-Torque RAM (STT/ SoT-MRAM) [4]} used for synaptic weight storage.Beside neuromorphic computing, NVMs are also used as main memory in conventional computers to improve performance and energy efficiency [5]}, [6]}, [7]}, [8]}, [9]}. We now describe the simulator.
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