One approach to exploit in-memory computing for DNNs is to design stand-alone accelerators where multiple AIMC tiles and associated digital logic blocks are interconnected by a suitable communication fabric [1]}, [2]}. In such a multi-tile accelerator, weights associated with different neural network layers can be mapped to different AIMC tiles and data can be propagated via tile-to-tile communication. Yet, these designs fall short on supporting (1) a variety of neural networks types, (2) changes in inter-layer connectivity and data-flow, (3) different processing and activation functions, and (4) multiple number formats (e.g. quantization levels), all of which require a high degree of flexibility, difficult to implement solely in hardware. Combining AIMC with general purpose processors can be key for powerful and cost-effective AI platforms, completely avoiding the need for designing generations of dedicated accelerators to cope with the rapid advances in DNN workloads and models.
