Hardware Synthesis
We implement the spatial accelerator of SALO in Chisel [1]}. The design in Chisel is further compiled to Verilog and synthesized using Synopsys DC compiler with FreePDK 45nm technology to obtain the report of power and area. Table REF  details the parameters and result of the synthesis. For performance analysis, we extend the cycle-accurate performance model from Sanger[2]} while taking different hybrid sparse attention mechanisms, data splitting and reordering involved in the data scheduler into consideration.
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