In PnM architectures, data is transferred from the DRAM to nearby processors or specialized accelerators, which are either
1) a part of the DRAM chip, but separate from the memory array [1]}, or
2) integrated into the logic layer of 3D-stacked memories [2]}, [3]}.
PnM enables the design of flexible substrates that support a diverse range of operations.
However, PnM architectures are limited in functionality and scalability: the design and fabrication of memory chips that integrate specialized processing units (such as [1]}) has proven to be challenging, and 3D-stacked memories are bound by strict thermal and area limitations.
