The proposed FD HBF hardware architecture, comprising of \(N\) -tap analog cancellation for the SI signal as well as A/D precoding and combining for the outgoing and incoming signals, is adopted for the MIMO node \(k\) , as depicted in the left part of Fig\(.\)  REF . Differently from [1]}'s architecture that considered only fully digital TX/RX beamforming, node \(k\)  is capable of HBF through its partially connected beamforming architecture. As shown in the figure, the analog canceller interconnects the \(N_{k}^{(\mathrm {RF})}\)  inputs of the analog TX precoder to the \(M_{k}^{(\mathrm {RF})}\)  outputs of the analog RX combiner. The complexity of the analog canceller expressed in the number of taps \(N\)  is independent of the numbers \(N_{k}\)  and \(M_{k}\)  of the TX and RX antennas, respectively, and as it will be shown next, it scales with the product \(\xi N_{k}^{(\mathrm {RF})}M_{k}^{(\mathrm {RF})}\)  with \(\xi <1\) . This is in contrast to [1]} where the analog canceller interconnects the \(N_{k}\)  TX antenna inputs to the \(M_{k}\)  RX antenna outputs.
