Application-specific integrated circuits (ASICs) for neuromorphic hardware
have been studied intensively with the aim of achieving highly efficient
computation [1]}, [2]}, [3]}, [4]}, [5]}, [6]}.
Although most neuromorphic hardware is designed as digital circuits [3]}, [4]},
some studies have sought higher efficiency by using analog circuits [5]} due to
the advantage that highly efficient multiply-accumulate (MAC) operations can be achieved.
