Recent works divide DRAM-based PiM architectures [1]} in two categories:
1) Processing-near-Memory (PnM), where computation occurs near the memory array [2]}, [3]}, [4]}, [5]}, [6]}, [7]}, and
2) Processing-using-Memory (PuM), where computation occurs within the memory array, by exploiting intrinsic properties of the memory technology [8]}, [9]}, [10]}, [11]}, [12]}.
