The open problems belong broadly in three categories: hardware-focused improvements to the architecture, better encoding, and better decoding strategies.
From the hardware perspective, one of the important open problems is to devise a passive implementation of the hybrid architecture.
In the current architecture, the \(CZ\)  gates on the computational module are active transformations, i.e., they require in-line squeezing and displacements.
If such active transformations can be replaced by passive transformations, then this could further simplify the computational module and thus reduce the experimental requirements.
Possible paths to explore in this direction could be to obtain a hybrid version of macronode-based architectures reviewed in [1]} or perhaps to use techniques demonstrated in [2]}.
