The example instruction implementation in Algorithm REF  is a bitonic sorter of 4 inputs. Such sorting networks are parallel and pipelinable algorithms for sorting a list of \(N\)  values. In each parallel step there is a number of compare-and-swap (CAS) units, that collectively sort the entire input list, as the input moves along the network. The odd-even merge sorter and the bitonic sorter [1]} are two similar sorting network topologies, both consisting of \(\Theta (log^2(N))\)  parallel steps. For a vector register width of 128-bit, this bitonic sorter sorts four 32-bit values in 3 cycles.
