Beyond the FPGA-based sIM implementation we consider in this paper, we make performance projections for massively parallel asynchronous sIMs using nanodevices. Magnetic Tunnel Junctions (MTJ) have recently attracted attention as building blocks for probabilistic computation because of their extreme scalability. The magnetic memory industry have integrated up to billions of single MTJs to replace various parts of the memory hierarchy [1]}. Through minimal modifications such MTJs can be made stochastic [2]}, [3]}, providing the expensive random number generation with negligible hardware cost. Stochastic MTJs have been demonstrated to provide fast fluctuations (\(\tau =\) 1 ns / flip) [4]}, [5]} and at least a million MTJs (\(N=10^6\) ) can be integrated in massively parallel architectures [6]}, [2]} similar to what we consider in this paper. Following the linear scaling law we demonstrated in Fig. REF , such sIMs can provide \(N/\tau \)  flips per second reaching 1 million flips per nanosecond (Table REF ), provided that the connectivity of the hardware is sparse enough to enable the ideal parallelism demonstrated in this paper.
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