Many techniques have been developed to optimize gate synthesis and qubit routing (i.e. compilation) for algorithms to be run on noisy intermediate scale quantum (NISQ) devices featuring a sparse native gate set. Although experimental QAOA work with XY mixers has still not appeared in the literature, numerical analyses predicting circuit durations for problems with XY mixers are not encouraging for very near-term hardware [1]}. In [2]}, [3]} hardware-efficient ansätze were proposed that match the processor topology and the native gates and use the objective function Hamiltonian only to guide the parameter setting procedure and to evaluate the final performance metric. In that approach, QAOA was used as a form of a quantum neural network that needs to be trained to act as an optimization solver, but there is concern as to how well this method, with its many parameters, would work in general.
