Targeting FPGA based DNN applications [1]}, our work investigates voltage scaling techniques of TPU in the FPGA platform. Different \(V_{ccint}\)  for each of the MACs in a systolic array will be an absurd implementation for FPGA, therefore this work partitions FPGA floor according to the slack value of the path of MACs. Each partition consists a group of paths within the MAC having similar slacks. Each partition is connected with different \(V_{ccint}\) . The proposed methodology abstracts the synthesis timing report from the \(Vivado\)  tool. In a synthesized design, the \(Vivado\)  IDE timing engine estimates the net delays of paths based on connectivity and fanout. The clustering algorithms create some clusters or groups based on path delays. The clusters with higher delays causing lower slack are placed in FPGA partitions with higher \(V_{ccint}\)  and the clusters with lower delays causing higher slack are placed in FPGA partitions with lower \(V_{ccint}\) . Here the \(V_{ccint}\)  provides power to a FPGA core.
The tuning of \(V_{ccint}\)  with slack is done by unique \(offline-online\)  strategy.
The circuit level challenges on the implementation of voltage scaling in FPGA platform are beyond the present scope of our article. However, the feasibility of implementing the necessary hardware for voltage scaling support is evident considering the successful implementations in other ASIC technologies. As is unavailable in current FPGAs we have simulated the design for the validation of the claim. The contribution of the paper is as follows:
