One of the most useful insights from such exploration is about the reduction in the number of instructions and cycles required for a task. For instance, if we look at the c2_sort instruction, it is able to sort a list of 8 32-bit elements in 6 cycles. In contrast, a sorting network implementation of only 4 32-bit inputs in older Intel processors required 13 SIMD instructions and 26 cycles [1]}. This 13x and 4.3x reduction of instructions and cycles respectively, while solving a bigger problem, is due to the unavailability of such specialised intrinsics. Even with AVX-512 , for each layer of compare-and-swap (CAS) units, a pair of separate instructions \(min\)  and \(max\)  are required, as well as a few calls of shuffle that permute the inputs for correct alignment [1]}. A similar discussion can be made for prefix sum , though parallel prefix sum uses more comparisons than the serial case, hence the less notable speedups.
