Few works have replaced the LS, and LMMSE channel estimation with computationally complex deep learning (DL) architectures [1]}, [2]}, [3]}, [4]}, [5]}. However, most existing works have not been realized on system-on-chip (SoC). In this context, this work focuses on improving the performance of the channel estimation in wireless PHY, where we design and implement deep neural network (DNN) augmented LS estimation (LSDNN) on Xilinx ZCU111 from Zynq multi-processor SoC (ZMPSoC) family comprising of qual-core ARM Cortex A53 processor and ultra-scale field-programmable gate array (FPGA). Compared to existing works, we augment the LS with blacka Fully Connected Feedforward DNN instead of replacing it with computationally intensive DL networks. We demonstrate the performance gain over the conventional LS and LMMSE approaches. We provide an extensive study of the effects of training SNR on the performance of the LSDNN channel estimation.
