One way to address the limitations of standalone AIMC-based accelerators is to add local CPUs [1]}, [2]}, [3]}, [4]}. The CPU-AIMC interplay nonetheless often is the run-time bottleneck in these systems, as AIMC tiles at competitive technology nodes typically operate on the order of hundreds of nanoseconds [5]}, [6]}. Any communication overhead with the CPU translates into unutilized AIMC tile compute cycles and hence a performance loss. Therefore, it is essential to work towards a tight integration to fully realize the potential of AIMC-based acceleration, including support for a software ecosystem so that systems can be easily configured to implement a wide range of neural networks.
