Devices with racetrack architectures hold promise as a fast, compact, energy-efficient and non-volatile memory solution[1]}, [2]}, [3]}. By design, the bit length is defined by regularly spaced pinning sites fabricated along a magnetic nanowire, and spin polarised current pulses are used to drive a sequence of magnetic bits or DW across a write and read head.[4]}, [5]} Our work forms the cornerstone for functional chiral racetrack device implementation by addressing various fronts pertinent to writing, switching and reading operations. First, we demonstrated deterministic writing of DWs using a current-induced Oersted field generated from a Au wire fabricated perpendicular to the racetrack. [6]}, [7]} The magnetization orientation of the nucleated domain can be controlled by the polarity of current pulse through the Au wire. Second, we demonstrated the SOT-induced dynamics of a dense array of sub-100 nm skyrmions in wire devices, paving the way for materials and device directions involving high-throughput racetracks.[8]} Notably, their modest SkHE, comparable to that in ferrimagnets, suggest that materials design efforts may continue in the direction of ferromagnets. Amorphous multilayer thin films hosting chiral spin textures have also been developed for their enhanced dynamics and compatibility with MTJ integration for detection. [9]} Coupled with ongoing efforts to stabilize RT skyrmions at ZF, our work is poised to support the development of next-generation racetrack devices hosting novel spin textures.
