MERSI protocol was used by the computer that was a fourth generation of what type of processors?
MERSI protocol The MERSI protocol is a cache coherency and memory coherence protocol used by the PowerPC G4. The protocol consists of five states, Modified (M), Exclusive (E), Read Only or Recent (R), Shared (S) and Invalid (I). The M, E, S and I states are the same as in the MESI protocol. The R state is similar to the E state in that it is constrained to be the only clean, valid, copy of that data in the computer system. Unlike the E state, the processor is required to initially request ownership of the cache line in the R state before the processor may modify the cache line and transition to the M state. In both the MESI and MERSI protocols, the transition from the E to M is silent.
XAP processor The XAP processor is a RISC processor architecture developed by Cambridge Consultants since 1994. XAP processors are a family of 16-bit and 32-bit cores, all of which are intended for use in an application-specific integrated circuit or ASIC chip design. XAP processors were designed for use in mixed-signal integrated circuits for sensor or wireless applications including Bluetooth, ZigBee, GPS, RFID or Near Field Communication chips. Typically these integrated circuits are used in low cost, high volume products that are battery-powered and must have low energy consumption. There are other applications where XAP processors have been used to good effect, such as wireless sensor networks and medical devices, e.g. hearing aids.