parameters: (self)
docstring: Sets up the x86 IO devices.
  
          Note: This is mostly copy-paste from prior X86 FS setups. Some of it
          may not be documented and there may be bugs.
docstring_summary: Sets up the x86 IO devices.
docstring_tokens: Sets up the x86 IO devices .
function: def _setup_io_devices(self):
          """ Sets up the x86 IO devices.
  
          Note: This is mostly copy-paste from prior X86 FS setups. Some of it
          may not be documented and there may be bugs.
          """
  
          # Constants similar to x86_traits.hh
          IO_address_space_base = 0x8000000000000000
          pci_config_address_space_base = 0xC000000000000000
          interrupts_address_space_base = 0xA000000000000000
          APIC_range_size = 1 << 12
  
          # Setup memory system specific settings.
          if self.get_cache_hierarchy().is_ruby():
              self.pc.attachIO(self.get_io_bus(), [self.pc.south_bridge.ide.dma])
          else:
              self.bridge = Bridge(delay="50ns")
              self.bridge.mem_side_port = self.get_io_bus().cpu_side_ports
              self.bridge.cpu_side_port = (
                  self.get_cache_hierarchy().get_mem_side_port()
              )
  
              # # Constants similar to x86_traits.hh
              IO_address_space_base = 0x8000000000000000
              pci_config_address_space_base = 0xC000000000000000
              interrupts_address_space_base = 0xA000000000000000
              APIC_range_size = 1 << 12
  
              self.bridge.ranges = [
                  AddrRange(0xC0000000, 0xFFFF0000),
                  AddrRange(
                      IO_address_space_base, interrupts_address_space_base - 1
                  ),
                  AddrRange(pci_config_address_space_base, Addr.max),
              ]
  
              self.apicbridge = Bridge(delay="50ns")
              self.apicbridge.cpu_side_port = self.get_io_bus().mem_side_ports
              self.apicbridge.mem_side_port = (
                  self.get_cache_hierarchy().get_cpu_side_port()
              )
              self.apicbridge.ranges = [
                  AddrRange(
                      interrupts_address_space_base,
                      interrupts_address_space_base
                      + self.get_processor().get_num_cores() * APIC_range_size
                      - 1,
                  )
              ]
              self.pc.attachIO(self.get_io_bus())
  
          # Add in a Bios information structure.
          self.workload.smbios_table.structures = [X86SMBiosBiosInformation()]
  
          # Set up the Intel MP table
          base_entries = []
          ext_entries = []
          for i in range(self.get_processor().get_num_cores()):
              bp = X86IntelMPProcessor(
                  local_apic_id=i,
                  local_apic_version=0x14,
                  enable=True,
                  bootstrap=(i == 0),
              )
              base_entries.append(bp)
  
          io_apic = X86IntelMPIOAPIC(
              id=self.get_processor().get_num_cores(),
              version=0x11,
              enable=True,
              address=0xFEC00000,
          )
  
          self.pc.south_bridge.io_apic.apic_id = io_apic.id
          base_entries.append(io_apic)
          pci_bus = X86IntelMPBus(bus_id=0, bus_type="PCI   ")
          base_entries.append(pci_bus)
          isa_bus = X86IntelMPBus(bus_id=1, bus_type="ISA   ")
          base_entries.append(isa_bus)
          connect_busses = X86IntelMPBusHierarchy(
              bus_id=1, subtractive_decode=True, parent_bus=0
          )
          ext_entries.append(connect_busses)
  
          pci_dev4_inta = X86IntelMPIOIntAssignment(
              interrupt_type="INT",
              polarity="ConformPolarity",
              trigger="ConformTrigger",
              source_bus_id=0,
              source_bus_irq=0 + (4 << 2),
              dest_io_apic_id=io_apic.id,
              dest_io_apic_intin=16,
          )
  
          base_entries.append(pci_dev4_inta)
  
          def assignISAInt(irq, apicPin):
  
              assign_8259_to_apic = X86IntelMPIOIntAssignment(
                  interrupt_type="ExtInt",
                  polarity="ConformPolarity",
                  trigger="ConformTrigger",
                  source_bus_id=1,
                  source_bus_irq=irq,
                  dest_io_apic_id=io_apic.id,
                  dest_io_apic_intin=0,
              )
              base_entries.append(assign_8259_to_apic)
  
              assign_to_apic = X86IntelMPIOIntAssignment(
                  interrupt_type="INT",
                  polarity="ConformPolarity",
                  trigger="ConformTrigger",
                  source_bus_id=1,
                  source_bus_irq=irq,
                  dest_io_apic_id=io_apic.id,
                  dest_io_apic_intin=apicPin,
              )
              base_entries.append(assign_to_apic)
  
          assignISAInt(0, 2)
          assignISAInt(1, 1)
  
          for i in range(3, 15):
              assignISAInt(i, i)
  
          self.workload.intel_mp_table.base_entries = base_entries
          self.workload.intel_mp_table.ext_entries = ext_entries
  
          entries = [
              # Mark the first megabyte of memory as reserved
              X86E820Entry(addr=0, size="639kB", range_type=1),
              X86E820Entry(addr=0x9FC00, size="385kB", range_type=2),
              # Mark the rest of physical memory as available
              X86E820Entry(
                  addr=0x100000,
                  size=f"{self.mem_ranges[0].size() - 0x100000:d}B",
                  range_type=1,
              ),
          ]
  
          # Reserve the last 16kB of the 32-bit address space for m5ops
          entries.append(
              X86E820Entry(addr=0xFFFF0000, size="64kB", range_type=2)
          )
  
          self.workload.e820_table.entries = entries
function_tokens: def _setup_io_devices ( self ) : # Constants similar to x86_traits.hh IO_address_space_base = 0x8000000000000000 pci_config_address_space_base = 0xC000000000000000 interrupts_address_space_base = 0xA000000000000000 APIC_range_size = 1 << 12 # Setup memory system specific settings. if self . get_cache_hierarchy ( ) . is_ruby ( ) : self . pc . attachIO ( self . get_io_bus ( ) , [ self . pc . south_bridge . ide . dma ] ) else : self . bridge = Bridge ( delay = "50ns" ) self . bridge . mem_side_port = self . get_io_bus ( ) . cpu_side_ports self . bridge . cpu_side_port = ( self . get_cache_hierarchy ( ) . get_mem_side_port ( ) ) # # Constants similar to x86_traits.hh IO_address_space_base = 0x8000000000000000 pci_config_address_space_base = 0xC000000000000000 interrupts_address_space_base = 0xA000000000000000 APIC_range_size = 1 << 12 self . bridge . ranges = [ AddrRange ( 0xC0000000 , 0xFFFF0000 ) , AddrRange ( IO_address_space_base , interrupts_address_space_base - 1 ) , AddrRange ( pci_config_address_space_base , Addr . max ) , ] self . apicbridge = Bridge ( delay = "50ns" ) self . apicbridge . cpu_side_port = self . get_io_bus ( ) . mem_side_ports self . apicbridge . mem_side_port = ( self . get_cache_hierarchy ( ) . get_cpu_side_port ( ) ) self . apicbridge . ranges = [ AddrRange ( interrupts_address_space_base , interrupts_address_space_base + self . get_processor ( ) . get_num_cores ( ) * APIC_range_size - 1 , ) ] self . pc . attachIO ( self . get_io_bus ( ) ) # Add in a Bios information structure. self . workload . smbios_table . structures = [ X86SMBiosBiosInformation ( ) ] # Set up the Intel MP table base_entries = [ ] ext_entries = [ ] for i in range ( self . get_processor ( ) . get_num_cores ( ) ) : bp = X86IntelMPProcessor ( local_apic_id = i , local_apic_version = 0x14 , enable = True , bootstrap = ( i == 0 ) , ) base_entries . append ( bp ) io_apic = X86IntelMPIOAPIC ( id = self . get_processor ( ) . get_num_cores ( ) , version = 0x11 , enable = True , address = 0xFEC00000 , ) self . pc . south_bridge . io_apic . apic_id = io_apic . id base_entries . append ( io_apic ) pci_bus = X86IntelMPBus ( bus_id = 0 , bus_type = "PCI   " ) base_entries . append ( pci_bus ) isa_bus = X86IntelMPBus ( bus_id = 1 , bus_type = "ISA   " ) base_entries . append ( isa_bus ) connect_busses = X86IntelMPBusHierarchy ( bus_id = 1 , subtractive_decode = True , parent_bus = 0 ) ext_entries . append ( connect_busses ) pci_dev4_inta = X86IntelMPIOIntAssignment ( interrupt_type = "INT" , polarity = "ConformPolarity" , trigger = "ConformTrigger" , source_bus_id = 0 , source_bus_irq = 0 + ( 4 << 2 ) , dest_io_apic_id = io_apic . id , dest_io_apic_intin = 16 , ) base_entries . append ( pci_dev4_inta ) def assignISAInt ( irq , apicPin ) : assign_8259_to_apic = X86IntelMPIOIntAssignment ( interrupt_type = "ExtInt" , polarity = "ConformPolarity" , trigger = "ConformTrigger" , source_bus_id = 1 , source_bus_irq = irq , dest_io_apic_id = io_apic . id , dest_io_apic_intin = 0 , ) base_entries . append ( assign_8259_to_apic ) assign_to_apic = X86IntelMPIOIntAssignment ( interrupt_type = "INT" , polarity = "ConformPolarity" , trigger = "ConformTrigger" , source_bus_id = 1 , source_bus_irq = irq , dest_io_apic_id = io_apic . id , dest_io_apic_intin = apicPin , ) base_entries . append ( assign_to_apic ) assignISAInt ( 0 , 2 ) assignISAInt ( 1 , 1 ) for i in range ( 3 , 15 ) : assignISAInt ( i , i ) self . workload . intel_mp_table . base_entries = base_entries self . workload . intel_mp_table . ext_entries = ext_entries entries = [ # Mark the first megabyte of memory as reserved X86E820Entry ( addr = 0 , size = "639kB" , range_type = 1 ) , X86E820Entry ( addr = 0x9FC00 , size = "385kB" , range_type = 2 ) , # Mark the rest of physical memory as available X86E820Entry ( addr = 0x100000 , size = f"{self.mem_ranges[0].size() - 0x100000:d}B" , range_type = 1 , ) , ] # Reserve the last 16kB of the 32-bit address space for m5ops entries . append ( X86E820Entry ( addr = 0xFFFF0000 , size = "64kB" , range_type = 2 ) ) self . workload . e820_table . entries = entries