parameters: (
      yosys_script_full_path,
      yosys_models_full_path,
      yosys_spram_full_path,
      yosys_dpram_full_path,
      yosys_spram_rename_full_path,
      yosys_dpram_rename_full_path,
      circuit_list,
      output_netlist,
      memory_addr_width,
      min_hard_mult_size,
      min_hard_adder_size,
  )
docstring: initializing the raw yosys script file
docstring_summary: initializing the raw yosys script file
docstring_tokens: initializing the raw yosys script file
function: def init_script_file(
      yosys_script_full_path,
      yosys_models_full_path,
      yosys_spram_full_path,
      yosys_dpram_full_path,
      yosys_spram_rename_full_path,
      yosys_dpram_rename_full_path,
      circuit_list,
      output_netlist,
      memory_addr_width,
      min_hard_mult_size,
      min_hard_adder_size,
  ):
      """initializing the raw yosys script file"""
      # specify the input files type
      for circuit in circuit_list:
          file_extension = os.path.splitext(circuit)[-1]
          if file_extension not in FILE_TYPES:
              raise vtr.VtrError("Inavlid input file type '{}'".format(file_extension))
  
      # Update the config file
      vtr.file_replace(
          yosys_script_full_path,
          {
              "XXX": circuit_list[0],
              "YYY": "./" + YOSYS_LIB_FILES["YSMDL"],
              "SSS": "./" + YOSYS_LIB_FILES["SPRAM"],
              "DDD": "./" + YOSYS_LIB_FILES["DPRAM"],
              "SSR": "./" + YOSYS_LIB_FILES["SPRAMR"],
              "DDR": "./" + YOSYS_LIB_FILES["DPRAMR"],
              "TTT": str(vtr.paths.yosys_lib_path),
              "ZZZ": output_netlist,
          },
      )
  
      # Update the config file
      vtr.file_replace(
          yosys_models_full_path,
          {"PPP": memory_addr_width, "MMM": min_hard_mult_size, "AAA": min_hard_adder_size},
      )
  
      # Update the config file files
      vtr.file_replace(yosys_spram_full_path, {"PPP": memory_addr_width})
      vtr.file_replace(yosys_dpram_full_path, {"PPP": memory_addr_width})
      vtr.file_replace(yosys_spram_rename_full_path, {"PPP": memory_addr_width})
      vtr.file_replace(yosys_dpram_rename_full_path, {"PPP": memory_addr_width})
function_tokens: def init_script_file ( yosys_script_full_path , yosys_models_full_path , yosys_spram_full_path , yosys_dpram_full_path , yosys_spram_rename_full_path , yosys_dpram_rename_full_path , circuit_list , output_netlist , memory_addr_width , min_hard_mult_size , min_hard_adder_size , ) : # specify the input files type for circuit in circuit_list : file_extension = os . path . splitext ( circuit ) [ - 1 ] if file_extension not in FILE_TYPES : raise vtr . VtrError ( "Inavlid input file type '{}'" . format ( file_extension ) ) # Update the config file vtr . file_replace ( yosys_script_full_path , { "XXX" : circuit_list [ 0 ] , "YYY" : "./" + YOSYS_LIB_FILES [ "YSMDL" ] , "SSS" : "./" + YOSYS_LIB_FILES [ "SPRAM" ] , "DDD" : "./" + YOSYS_LIB_FILES [ "DPRAM" ] , "SSR" : "./" + YOSYS_LIB_FILES [ "SPRAMR" ] , "DDR" : "./" + YOSYS_LIB_FILES [ "DPRAMR" ] , "TTT" : str ( vtr . paths . yosys_lib_path ) , "ZZZ" : output_netlist , } , ) # Update the config file vtr . file_replace ( yosys_models_full_path , { "PPP" : memory_addr_width , "MMM" : min_hard_mult_size , "AAA" : min_hard_adder_size } , ) # Update the config file files vtr . file_replace ( yosys_spram_full_path , { "PPP" : memory_addr_width } ) vtr . file_replace ( yosys_dpram_full_path , { "PPP" : memory_addr_width } ) vtr . file_replace ( yosys_spram_rename_full_path , { "PPP" : memory_addr_width } ) vtr . file_replace ( yosys_dpram_rename_full_path , { "PPP" : memory_addr_width } )