parameters: (self, core: AbstractCore, target_isa: ISA)
return_statement: return False
docstring: True if the CPU model or ISA requires sending evictions from caches
          to the CPU. Scenarios warrant forwarding evictions to the CPU:
          1. The O3 model must keep the LSQ coherent with the caches
          2. The x86 mwait instruction is built on top of coherence
          3. The local exclusive monitor in ARM systems
docstring_summary: True if the CPU model or ISA requires sending evictions from caches
          to the CPU. Scenarios warrant forwarding evictions to the CPU:
          1. The O3 model must keep the LSQ coherent with the caches
          2. The x86 mwait instruction is built on top of coherence
          3. The local exclusive monitor in ARM systems
docstring_tokens: True if the CPU model or ISA requires sending evictions from caches to the CPU . Scenarios warrant forwarding evictions to the CPU : 1 . The O3 model must keep the LSQ coherent with the caches 2 . The x86 mwait instruction is built on top of coherence 3 . The local exclusive monitor in ARM systems
function: def sendEvicts(self, core: AbstractCore, target_isa: ISA):
          """True if the CPU model or ISA requires sending evictions from caches
          to the CPU. Scenarios warrant forwarding evictions to the CPU:
          1. The O3 model must keep the LSQ coherent with the caches
          2. The x86 mwait instruction is built on top of coherence
          3. The local exclusive monitor in ARM systems
          """
          if core.get_type() is CPUTypes.O3 or target_isa in (ISA.X86, ISA.ARM):
              return True
          return False
function_tokens: def sendEvicts ( self , core : AbstractCore , target_isa : ISA ) : if core . get_type ( ) is CPUTypes . O3 or target_isa in ( ISA . X86 , ISA . ARM ) : return True return False