parameters: (self)
return_statement: return design_name
docstring: @brief speculate the design name for dumping out intermediate solutions
function: def design_name(self):
          """
          @brief speculate the design name for dumping out intermediate solutions 
          """
          if self.aux_input: 
              design_name = os.path.basename(self.aux_input).replace(".aux", "").replace(".AUX", "")
          elif self.verilog_input:
              design_name = os.path.basename(self.verilog_input).replace(".v", "").replace(".V", "")
          elif self.def_input: 
              design_name = os.path.basename(self.def_input).replace(".def", "").replace(".DEF", "")
          return design_name
function_tokens: def design_name ( self ) : if self . aux_input : design_name = os . path . basename ( self . aux_input ) . replace ( ".aux" , "" ) . replace ( ".AUX" , "" ) elif self . verilog_input : design_name = os . path . basename ( self . verilog_input ) . replace ( ".v" , "" ) . replace ( ".V" , "" ) elif self . def_input : design_name = os . path . basename ( self . def_input ) . replace ( ".def" , "" ) . replace ( ".DEF" , "" ) return design_name