parameters: (
          self,
          dram_interface_class: Type[DRAMInterface],
          num_channels: Union[int, str],
          interleaving_size: Union[int, str],
          size: Optional[str] = None,
          addr_mapping: Optional[str] = None,
      )
docstring: :param dram_interface_class: The DRAM interface type to create with
              this memory controller
          :param num_channels: The number of channels that needs to be
          simulated
          :param size: Optionally specify the size of the DRAM controller's
              address space. By default, it starts at 0 and ends at the size of
              the DRAM device specified
          :param addr_mapping: Defines the address mapping scheme to be used.
              If None, it is defaulted to addr_mapping from dram_interface_class.
          :param interleaving_size: Defines the interleaving size of the multi-
              channel memory system. By default, it is equivalent to the atom
              size, i.e., 64.
docstring_summary: :param dram_interface_class: The DRAM interface type to create with
              this memory controller
          :param num_channels: The number of channels that needs to be
          simulated
          :param size: Optionally specify the size of the DRAM controller's
              address space. By default, it starts at 0 and ends at the size of
              the DRAM device specified
          :param addr_mapping: Defines the address mapping scheme to be used.
              If None, it is defaulted to addr_mapping from dram_interface_class.
          :param interleaving_size: Defines the interleaving size of the multi-
              channel memory system. By default, it is equivalent to the atom
              size, i.e., 64.
docstring_tokens: : param dram_interface_class : The DRAM interface type to create with this memory controller : param num_channels : The number of channels that needs to be simulated : param size : Optionally specify the size of the DRAM controller s address space . By default it starts at 0 and ends at the size of the DRAM device specified : param addr_mapping : Defines the address mapping scheme to be used . If None it is defaulted to addr_mapping from dram_interface_class . : param interleaving_size : Defines the interleaving size of the multi - channel memory system . By default it is equivalent to the atom size i . e . 64 .
function: def __init__(
          self,
          dram_interface_class: Type[DRAMInterface],
          num_channels: Union[int, str],
          interleaving_size: Union[int, str],
          size: Optional[str] = None,
          addr_mapping: Optional[str] = None,
      ) -> None:
          """
          :param dram_interface_class: The DRAM interface type to create with
              this memory controller
          :param num_channels: The number of channels that needs to be
          simulated
          :param size: Optionally specify the size of the DRAM controller's
              address space. By default, it starts at 0 and ends at the size of
              the DRAM device specified
          :param addr_mapping: Defines the address mapping scheme to be used.
              If None, it is defaulted to addr_mapping from dram_interface_class.
          :param interleaving_size: Defines the interleaving size of the multi-
              channel memory system. By default, it is equivalent to the atom
              size, i.e., 64.
          """
          num_channels = _try_convert(num_channels, int)
          interleaving_size = _try_convert(interleaving_size, int)
  
          if size:
              size = _try_convert(size, str)
  
          if addr_mapping:
              addr_mapping = _try_convert(addr_mapping, str)
  
          super().__init__()
          self._dram_class = dram_interface_class
          self._num_channels = num_channels
  
          if not _isPow2(interleaving_size):
              raise ValueError("Memory interleaving size should be a power of 2")
          self._intlv_size = interleaving_size
  
          if addr_mapping:
              self._addr_mapping = addr_mapping
          else:
              self._addr_mapping = self._dram_class.addr_mapping.value
  
          if size:
              self._size = toMemorySize(size)
          else:
              self._size = self._get_dram_size(num_channels, self._dram_class)
  
          self._dram = [
              self._dram_class(addr_mapping=self._addr_mapping)
              for _ in range(num_channels)
          ]
          self.mem_ctrl = [
              MemCtrl(dram=self._dram[i]) for i in range(num_channels)
          ]
function_tokens: def __init__ ( self , dram_interface_class : Type [ DRAMInterface ] , num_channels : Union [ int , str ] , interleaving_size : Union [ int , str ] , size : Optional [ str ] = None , addr_mapping : Optional [ str ] = None , ) -> None : num_channels = _try_convert ( num_channels , int ) interleaving_size = _try_convert ( interleaving_size , int ) if size : size = _try_convert ( size , str ) if addr_mapping : addr_mapping = _try_convert ( addr_mapping , str ) super ( ) . __init__ ( ) self . _dram_class = dram_interface_class self . _num_channels = num_channels if not _isPow2 ( interleaving_size ) : raise ValueError ( "Memory interleaving size should be a power of 2" ) self . _intlv_size = interleaving_size if addr_mapping : self . _addr_mapping = addr_mapping else : self . _addr_mapping = self . _dram_class . addr_mapping . value if size : self . _size = toMemorySize ( size ) else : self . _size = self . _get_dram_size ( num_channels , self . _dram_class ) self . _dram = [ self . _dram_class ( addr_mapping = self . _addr_mapping ) for _ in range ( num_channels ) ] self . mem_ctrl = [ MemCtrl ( dram = self . _dram [ i ] ) for i in range ( num_channels ) ]