There are many applications which require limiting voltage levels of alternating or oscillating voltage sources.
FIG. 1 shows a simplified circuit diagram of a limiter according to the prior art. There is a voltage source VS represented by an ideal voltage source VC and an impedance RI. The voltage source VS may be, e.g. an oscillator, and most specifically, an oscillator in an RFID application. The output of the voltage source VS is applied to electronic components. A first transistor P1 is coupled with its channel between the output node OUT and ground. A second transistor N1 is coupled with its channel between the output node OUT and a supply voltage level VDD. The gates of the first transistor and the second transistor N1 are biased by BIAS voltage levels VBP1 and VBN1 respectively. However, any currents drawn from the output node OUT through transistors N1 or P1 are finally dissipated and contribute to the overall power consumption.