Semiconductor devices and semiconductor device fabrication processes are well known. For example, metal oxide semiconductor field-effect transistors (MOSFETs) are commonly used in a variety of different applications. As another example, LDMOS devices are often used in applications, such as smart power technologies, where higher voltage rating is desired and device size is at a premium. Indeed, power LDMOS devices are becoming increasingly popular for power applications. Furthermore, some power LDMOS devices must be designed to operate in a “high-side configuration,” which is a configuration in which all the device terminals are level shifted with respect to the substrate potential. A device that may be operated in a high-side configuration is said to be “high-side capable.” High-side capable power LDMOS devices are designed to prevent a direct punch-through path from a body region of the power LDMOS device to an underlying, heavily doped substrate.
Existing technology attempts to satisfy high breakdown voltage requirements by utilizing a power LDMOS device having a reduced surface field (RESURF) structure. A power LDMOS device having a RESURF structure includes a first semiconductor region (which serves as a drift/RESURF region) having one conductivity type, and a second semiconductor region having a different conductivity type. The second region depletes the RESURF region from two different directions (bottom and side), allowing for a more uniform electric field distribution and thus reducing the peak electric field in the drift region, thereby allowing a higher breakdown voltage for the power LDMOS device. The RESURF structure just described is referred to herein as a “single RESURF” structure.
A “double RESURF” LDMOS structure, on the other hand, includes first and third semiconductor regions having one conductivity type, and a second semiconductor region having a different conductivity type. In the double RESURF structure, first and third semiconductor regions deplete the second semiconductor region, thus reducing the peak electric field in the second semiconductor region to a greater degree than is possible with a single RESURF structure. Transistor devices, including power LDMOS devices and bipolar transistors, having single or double RESURF structures, will be referred to herein as “RESURF transistors.”
Lower “on” resistance and higher breakdown voltage characteristics are desirable in most practical LDMOS applications. An existing double RESURF LDMOS design utilizes a heavily doped n-type buried layer (NBL) that facilitates the double RESURF characteristics of the device. Unfortunately, the NBL limits the achievable breakdown voltage due to its depth relative to the source/body region near the surface of the device. Consequently, to achieve higher breakdown voltage, the thickness of the semiconductor material (e.g., p-type epitaxial semiconductor material) between the NBL and the source/body region could be increased. This solution, however, may not be feasible for higher breakdown voltage requirements, such as 80 volts and higher.