1. Field of the Invention
This invention relates to non-volatile semiconductor memory capable of storing an analog value or multiple bits per memory cell.
2. Description of Related Art
A typical electrically erasable non-volatile memory contains a memory array including hundreds or thousands of rows of memory cells and hundreds or thousands of columns of memory cells, where each memory cell contains a transistor such as a floating gate or split-gate transistor having a programmable threshold voltage. The threshold voltage of a memory cell (or a transistor within the memory cell) indicates a stored value and is programmed by applying appropriate programming voltages to the control gate, source, and drain of the memory cell. Depending on the resolution of read and write circuits which read and write threshold voltages, non-volatile memory can store one bit, an analog value, or a multi-bit value per memory cell.
In a typical non-volatile memory architecture, each row of memory cells in a memory array has a row (or word) line coupled to control gates of the memory cells in the row, and each column of memory cells has a column (or bit) line coupled to drains of the memory cells in the column. Sources of the memory cells in an array may be connected in a variety of ways. For example, a virtual ground array often has neighboring columns of memory cells that share a column line so that each column line in a virtual ground array is coupled to the drains of memory cells in one column and to the sources of memory cells in the neighboring column. For flash memory, sources of all memory cells in an erasable sector are coupled to a source line for the sector. Accessing memory cells for erase, write, or read operations applies appropriate voltages to the row, column, and source lines coupled to the memory cell or cells to be erased, written, or read. When programming (or writing to) a selected memory cell, programming voltages applied to selected row, column, and source lines for a sufficient period change the threshold voltage of the memory cell coupled to those lines.
A problem in non-volatile memories is that voltages applied to row and column lines of memory cells selected for a write or erase operation can disturb or change the threshold voltages of memory cells in the same columns or rows as the selected memory cells. The accumulated threshold voltage disturbances from writing to hundreds or thousands of memory cells in the same row or column can significantly change the threshold voltage of a memory cell and the value stored in the memory cell. This problem is particularly significant for large memory arrays which have more memory cells per row and column. The problem is also significant in analog or multilevel memories where a relatively small variation in a threshold voltage changes the value stored. Accordingly, methods and architectures for reducing the write and erase disturb in analog and multilevel memories are sought.