In the course of integrated circuit (IC) evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices. During the scaling trend, various materials have been implemented for the gate electrode and gate dielectric for CMOS devices.
For example, high-dielectric constant gate dielectric materials and metal gates (HK/MG) have been adopted to enhance electrical performance of CMOS devices. During a gate-last HK/MG process, polysilicon gate electrodes are formed in conjunction with other process for forming the CMOS devices. In a later stage, the polysilicon gate electrodes are removed and replaced with one or more metallic materials.