Anti-fuse is one of the One-Time Programmable (OTP) devices that can only be programmed once. Particularly, an anti-fuse has a high impedance state after fabrication and a low impedance state after being programmed. On the contrary, a fuse has a low impedance state after fabrication and a high impedance state after being programmed. The most commonly used anti-fuses are based on MOS gate oxide breakdown, metal-dielectric-metal breakdown, metal-dielectric-silicon breakdown, or silicon-dielectric-silicon breakdown, etc. Silicon dioxide (SiO2) is the most commonly used dielectric for breakdown in anti-fuses. However, Silicon-Oxide-Nitride (SON), Silicon Nitride (SiNx), Oxide-Nitride-Oxide (ONO), or other type of metal oxides, such as Aluminum Oxide (Al2O3), MgO, HfO2, or Cr2O3, can also be used.
MOS gate oxide breakdown is based on applying a high voltage to break down the gate oxide to create a programmed state. However, there is a mechanism called soft-breakdown, other than the desirable hard-breakdown, which makes the dielectric film appear to be broken down, but the film may heal by itself after cycling or burn-in. The reliability may be a concern for practical applications.
Dielectric breakdown anti-fuses have been proven in manufacture. One of conventional dielectric breakdown anti-fuse is shown in FIGS. 1(a), 1(b), and 1(c). This anti-fuse is based on metal-dielectric-silicon with a diode constructed by P+ active region over N+ bar as program selector. FIG. 1(a) shows a portion of process steps by using a first Local Oxidation (LOCOS) to define an N+ bar area. FIG. 1(b) shows a second LOCOS step to further define active regions within each N+ bar in a perpendicular direction. The cell is patterned by two LOCOS steps so that the cell size is determined by the pitches of active regions in the X- and Y-directions. The cell size is generally referred to 4F2, where F stands for figure size. After the active region of the cells is determined, a P type dopant is implanted, a thin silicon dioxide is grown, and then a metal is built on top of each cell as shown in FIG. 1(c). The equivalent circuit of the anti-fuse cell is a capacitor in series with a diode at an X and Y cross-point as shown in FIG. 1(d). For additional information see, e.g., Noriaki, et. al, “A New Cell for High Capacity Mask ROM by the Double LOCOS Techniques,” International Electronics Device Meeting, December, 1983, pp. 581-584.
The anti-fuse cell in FIGS. 1(a), 1(b), and 1(c) is very complicated to fabricate, as it requires three more masks and two LOCOS steps over standard CMOS processes. Fabricating LOCOS requires a mask for field implant, nitride deposition, and a long thermal cycle to grow field oxide. Accordingly, there is a need for an anti-fuse cell that is more compatible with standard CMOS process to save costs.