1. Field of the Invention
The present invention relates to field-programmable gate arrays, and more particularly, to a low voltage differential signaling driver for field programmable gate arrays.
2. Description of the Related Art
A field-programmable gate array (FPGA) is an integrated circuit (IC) that includes a two-dimensional array of general-purpose logic circuits, called cells or logic blocks, whose functions are programmable. The cells are linked to one another by programmable buses. The cell types may be small multifunction circuits (or configurable functional blocks or groups) capable of realizing all Boolean functions of a few variables. The cell types are not restricted to gates. For example, configurable functional groups typically include memory cells and connection transistors that may be used to configure logic functions such as addition, subtraction, etc., inside of the FPGA. A cell may also contain one or two flip-flops. Two types of logic cells found in FPGAs are those based on multiplexers and those based on programmable read only memory (PROM) table-lookup memories. Erasable FPGAs can be reprogrammed many times. This technology is especially convenient when developing and debugging a prototype design for a new product and for small-scale manufacture.
Almost all integrated circuits use input/output (I/O) buffers to connect internal circuit nodes to other circuits external to the integrated circuit. These I/O buffers can be input, output or bi-directional I/O buffers. Further, each I/O buffer may be designed to meet electrical specifications dictated by industry standards such as TTL, LVTTL, LVCMOS, GTL. It is also common for circuit designers to design each I/O buffer with multiple transistors in parallel. For example, 2-4 P-type transistors may be connected in parallel to form the pull-up section of the buffer, while 2-4 N-type transistors may be connected in parallel to form the pull down section of the buffer. Designers may then decide to use some or all of the transistors as needed by the circuit application to meet performance criteria, a particular I/O standard and noise considerations.
The selection of the transistors connected into the circuit is usually done by masking options such as metal, vias and contacts. Moreover, some FPGAs have used similar techniques to select one or more transistors into the I/O buffer to provide slew control. A user may configure his I/O buffer to have either fast slew or slow slew by programming an appropriate antifuse element. This feature allows the user control over speed and noise that is induced into the circuit by the switching I/O buffers.
Different types of FPGAs designed by various manufacturers also feature configurable I/O buffers. These FPGAs may feature highly configurable input and output buffers, which provide support for a wide variety of I/O standards. Input buffers can be configured as either a simple buffer or as a differential amplifier input. Output buffers can be configured as either a push-pull output or as an open drain output. Selection of the desired standard is done by configuration memory bits. Further, different power supplies are provided to the I/O buffer as needed by the standard.
Hence, there is a need for an I/O that has an output buffer which can function as a low voltage differential signaling driver when used together with an adjacent output buffer.