The invention relates to the sequential storage circuits commonly referred to as xe2x80x9cflip-flopsxe2x80x9d. More particularly, the invention relates to a high-speed flip-flop that operates at very low voltage levels and can offer set and/or reset capability.
Flip-flops are sequential circuits storing either a xe2x80x9chighxe2x80x9d value (power high, or logic one) or a xe2x80x9clowxe2x80x9d value (power low, or logic zero). A flip-flop has a next value that depends on the values of one or more input signals. Conventionally, a flip-flop has data, clock, set, and/or reset input signals.
A D (data) input signal is typically clocked into the flip-flop on receipt of a given clock edge, and appears at the flip-flop output on the opposite clock edge. S (set) and R (reset) input signals are generally unclocked, meaning that when the set or reset signal becomes active (e.g., goes high), the stored value changes immediately, without waiting for the arrival of a clock edge. An active set signal forces the stored value (conventionally designated Q) high, no matter what value was previously stored. An active reset signal forces the stored value Q low, no matter what value was previously stored. In set/reset flip-flops (i.e., flip-flops having both set and reset input signals) the set and reset signals are typically restricted such that at most one of them can be active at any given time.
Flip-flops are often designed using two latches separated by passgates. FIG. 1 shows such a flip-flop, comprising a first latch including cross-coupled inverters 101 and 102, a second latch including cross-coupled inverters 103 and 104, and passgates 106, 107. The clock signal C is inverted by inverter 105 to provide inverted clock signal CB. On the falling edge of the clock signal C (or whenever signal C is low), signal CB goes high, and the data signal D passes through passgate 106 to node A, and hence into the first latch. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) The data value is inverted by inverter 101, and appears at node B. On the next rising edge of clock signal C, the inverted data from node B passes through passgate 107 to node QB (the inverted output signal), and hence into the second latch. The data is again inverted by inverter 103, and appears on the output node Q.
For the flip-flop to function properly, it must be possible to write a high value to each of nodes A and QB, and ensure that the new value overcomes a low value previously stored on the node. The new high value must pass through either passgate 106 or passgate 107, and overcome the zero value being provided by inverter 102 or inverter 104, respectively. When passing through an N-channel transistor, a high voltage value is reduced by the threshold voltage of the transistor. Therefore, if an N-channel transistor is used to implement the passgate, as shown in FIG. 1, inverters 102 and 104 are necessarily designed to be weak, and correspondingly slow. (Writing low values is not an issue, because there is no voltage degradation of a low signal through an N-channel transistor.)
At very low voltages, the high voltage value (VDD) approaches the threshold voltage of an N-channel transistor, which is generally about 0.7 volts. It is not practical to reduce this threshold voltage, because transistors with a lower threshold voltage would become unacceptably sensitive to noise. Therefore, at very low voltages, the high value passed through the passgate is not sufficient to overcome even a weak inverter (e.g., inverter 102 in FIG. 1), and therefore may not be high enough to trip inverter 101. The same limitation applies to passgate 107 and inverters 104, 103. One known solution is to implement the passgates using CMOS passgates (i.e., paired N-channel and P-channel transistors), as shown in FIG. 2.
FIG. 2A shows a well-known flip-flop similar to that of FIG. 1. The N-channel transistors forming passgates 106, 107 in FIG. 1 are replaced by CMOS passgates 206, 207, respectively. The P-channel gate terminals are driven by the inverse of the signals used to drive the N-channel gate terminals. A high value on data input D or node B is not reduced as it passes through the P-channel transistor. Therefore, the substitution of the CMOS passgates for the simple N-channel transistors ensures that new high values will be successfully latched, even at low voltages. (Of course, the high voltage level must be higher than the threshold voltage of the N-channel transistor, or no circuit containing N-channel transistors will function properly.)
A disadvantage of using CMOS passgates in flip-flops is that P-channel transistors are relatively slow compared to similarly-sized N-channel transistors. Because flip-flops are ubiquitous in nearly all integrated circuits, minimum sized gates are usually used to implement flip-flops. Passing a high logic level through a minimum sized P-channel transistor introduces a delay that can become significant.
Therefore, the flip-flop of FIG. 2A also includes another modification, which improves the operating speed of the flip-flop. CMOS passgates 208 and 209 are inserted into the latch feedback loops after inverters 202 and 204, respectively. When clock signal C goes low and inverted clock signal CB goes high, CMOS passgate 206 is turned on. In the flip-flop of FIG. 1, an incoming high data signal must then overcome a low value on node A driven by inverter 102. In the flip-flop of FIG. 2A, however, passgate 208 is turned off (because clock signal C is low), and there is no driving inverter to be overcome by the new high value. Similarly, when clock signal C goes high and inverted clock signal CB goes low, passgate 209 is turned off, and a high value on node B passes onto node QB unopposed by inverter 204. Thus, the latches in FIG. 2A change state more rapidly than the corresponding latches in FIG. 1.
FIG. 2B shows another prior art flip-flop similar to that of FIG. 2A. In the flip-flop of FIG. 2A, passgates (208, 209) are inserted between the outputs terminals of the feedback inverters (202, 204) in the latches and the nodes (A, QB) by which data is passed to the latches. These passgates provide a means for electrically isolating the feedback inverters from the-nodes when new data is provided to the latches. However, writing a low value to a latch is generally not a problem, even at low voltages. The problems are encountered only when writing a high value to the latch while overcoming a low value provided by the feedback inverter. Therefore, when writing any new value to the latch, it is only necessary to prevent the feedback inverter from driving a low value.
In the flip-flop of FIG. 2B, P-channel transistor 211 and N-channel transistor 213 form an inverter driven by node B (corresponding to inverter 202 in FIG. 2A). Inserted into the pull-down path of the inverter is an N-channel transistor 212 gated by the clock signal C. Thus, when clock signal C goes low, the new data (e.g., a high value) is written from data input terminal D to node A. Because clock signal C is low, no low signal is provided through N-channel transistor 213. Therefore, the new high value on node A is unopposed.
Similarly, P-channel transistor 221 and N-channel transistor 223 form an inverter driven by node Q (corresponding to inverter 204 in FIG. 2A). Inserted into the pull-down path of the inverter is an N-channel transistor 222 gated by inverted clock signal CB. Thus, when clock signal C goes high, the new data (e.g., a high value) is written from node B to node QB. Because inverted clock signal CB is low, no low signal is provided through N-channel transistor 223. Therefore, the new high value on node QB is unopposed.
It is possible to include feedback passgates 208 and 209 (FIG. 2A) or N-channel transistors 212 and 222 (FIG. 2B) while using N-channel transistors 106 and 107 (FIG. 1) instead of CMOS passgates 206 and 207 (FIGS. 2A and 2B) to feed the latches. Eliminating the feedback paths while writing to nodes A and QB gives improved performance compared to the flip-flop of FIG. 1. However, as described above, at very low voltages an incoming high value can be reduced below the threshold voltage of the N-channel device in the latch inverter. For example, if the power high voltage is 1.4 volts and the threshold voltage of an N-channel device is 0.7 volts, the high voltage after passing through N-channel transistor 106 or 107 is only 0.7 volts, which might or might not be sufficient to trip the latch. When processing variations are taken into account, the flip-flop becomes unreliable even at voltages higher than 1.4 volts. Therefore, the use of N-channel transistors to implement passgates 106 and 107 is not desirable for known flip-flop circuits expected to operate at low voltages.
While CMOS passgates 206 and 207 are necessary to ensure functionality at low voltages, the P-channel transistors included in the passgates still introduce undesirable delay into the data path through the flip-flop when writing high values over low values previously stored in nodes A or QB.
The issue of speed becomes more problematical when reset and/or set capability is added to the flip-flop. FIG. 3 shows a well-known flip-flop similar to that of FIG. 2A, but having reset capability. The reset signal R is inverted through inverter 310 to provide inverted reset signal RB. Inverter 201 is replaced with NAND gate 301, and the second input terminal of NAND gate 301 is driven by inverted reset signal RB. Inverter 203 is replaced with NOR gate 303, and the second input terminal of NOR gate 303 is driven by reset signal R.
Thus, when signal R goes high, signal RB goes low and node B is forced to a high value, while the output signal Q is forced to a low value. Both values are latched through the respective feedback loops.
The reset flip-flop of FIG. 3 is slower than a corresponding flip-flop without reset capability, because of the extra transistors included in NAND gate 301 and NOR gate 303. Assume that reset signal R is inactive (deasserted, or low) and signal RB is high. Whenever a high value is written from data input D to node A, node B goes low. However, node B is now pulled low through two N-channel transistors in series. (See FIG. 3A, which shows a standard CMOS NAND-gate that includes two N-channel transistors 313, 314 coupled in series and two P-channel transistors 311, 312 coupled in parallel.) Therefore, NAND gate 301 is slower than inverter 201.
Similarly, whenever a low value is written from node B to node QB, output node Q goes high (assuming the reset signal R is inactive). However, output node Q is now pulled high through two P-channel transistors in series. (See FIG. 3B, which shows a standard CMOS NOR-gate that includes two P-channel transistors 315, 316 coupled in series and two N-channel transistors 317, 318 coupled in parallel.) Therefore, NOR gate 303 is slower than inverter 203.
FIG. 4 shows a well-known flip-flop similar to that of FIG. 2A, but having set capability. The set signal S is inverted through inverter 460 to provide inverted set signal SB. Inverter 201 is replaced with NOR gate 401, and the second input terminal of NOR gate 401 is driven by set signal S. Inverter 203 is replaced with NAND gate 403, and the second input terminal of NAND gate 403 is driven by inverted set signal SB.
Thus, when signal S goes high, node B is forced to a low value, signal SB goes low, and the output signal Q is forced to a high value. Both values are latched through the respective feedback loops.
Similar to the reset flip-flop of FIG. 3, the set flip-flop of FIG. 4 is slower than a corresponding flip-flop without set capability, because of the extra transistors included in NOR gate 401 and NAND gate 403.
It is part of the nature of transistors that, all else being equal, a lower voltage means a slower operating speed. At one time, virtually all integrated circuits operated at 5 volts. However, voltage levels of integrated circuits have been rapidly decreasing, first to 3.3 volts, then 2.5 volts, and so on. Voltage levels of 1.8 volts or less are now supported by many integrated circuits.
At the same time, the operating frequencies expected from the circuits have been increasing at a rapid rate. Where once 10 megahertz was considered an acceptable clock rate, clock rates of up to 300 megahertz are now commonly specified. Integrated circuit designers are being forced to redesign many common circuits to obtain additional performance at lower voltage levels.
Therefore, it is desirable to provide high-speed flip-flops, particularly set and/or reset flip-flops, that function reliably at reduced voltage levels.
The invention provides flip-flops that are both operable at high speed and reliable at low voltage levels.
According to a first aspect of the invention, a first flip-flop includes first and second latches. When a clock signal is in a first state, a data input signal is passed to a first node of the first latch through a first passgate, and the inverted data input signal is passed to a second node of the first latch through a second passgate. When the clock signal is in a second state, a signal on the second node of the first latch is passed to a first node of the second latch through a third passgate, and the inverse of that signal is passed to a second node of the second latch through a fourth passgate.
In one embodiment, the first, second, third, and fourth passgates are N-channel transistors. CMOS passgates are used in one embodiment. However, they are not necessary in most cases, because whenever a high value is-passed to one node of a latch, a low value is passed to the other node of the latch. Therefore, the latch can safely ignore all high input values. Hence, this feature permits the flip-flops of the invention to function at very low voltages. Because writing a high value is normally much slower than writing a low value, the flip-flops of the invention also function at very high clock rates, even at low voltages.
In some embodiments, means are provided for disabling the feedback loops of each latch while data is passed to the latch. The first latch comprises first and second logic gates, with the first logic gate driving the first node and the second logic gate, and the second logic gate driving the second node and the first logic gate. The second latch also comprises first and second logic gates, with the first logic gate driving the first node and the second logic gate, and the second logic gate driving the second node and the first logic gate.
In one such embodiment, a feedback passgate is coupled between an output terminal of the first logic gate and the first node of each latch. The N-channel gate terminal of the feedback passgate in the first latch is coupled to the gate terminal of the first passgate. The P-channel gate terminal (where provided) is coupled to receive the inverse signal from the N-channel gate terminal. The N-channel gate terminal of the feedback passgate in the second latch is coupled to the gate terminal of the second passgate. The P-channel gate terminal (where provided) is coupled to receive the inverse signal from the N-channel gate terminal.
In another such embodiment, an N-channel transistor is inserted into the pull-down path of the first logic gate of each latch. Thus, when the N-channel transistor is xe2x80x9coffxe2x80x9d, the logic gate does not pull the first node of the latch low, and a high value is easily written to the latch.
A second aspect of the invention enables the use of cross-coupled inverters, rather than NAND gates and NOR gates, to implement set, reset, and set/reset flip-flops. Because inverters are faster than similarly-sized NAND and NOR gates, this features also increases the speed at which the flip-flop can operate.
In a flip-flop according to this aspect of the invention, a first latch comprises first and second inverters, with the first inverter driving the first node and the second inverter, and the second inverter driving the second node and the first inverter. The second latch also comprises first and second inverters, with the first inverter driving the first node and the second inverter, and the second inverter driving the second node and the first inverter. For each latch, at least one pull-up and at least one pull-down are coupled directly to the nodes of the latch. The pull-ups and pull-downs are controlled by set and/or reset signals applied to the flip-flop.
In a reset flip-flop according to one embodiment of the invention, a first pull-down is coupled to the first node of the first latch, with the gate terminal of the first pull-down being driven by a reset signal. A first pull-up is coupled to the first node of the second latch, with the gate terminal of the first pull-up being driven by an inverted reset signal. Optionally, a second pull-up is coupled to the second node of the first latch, with the gate terminal of the second pull-up being driven by the inverted reset signal, and a second pull-down is coupled to the second node of the second latch, with the gate terminal of the second pull-down being driven by the reset signal.
In a set flip-flop according to another embodiment of the invention, a third pull-up is coupled to the first node of the first latch, with the gate terminal of the third pull-up being driven by an inverted set signal. A third pull-down is coupled to the first node of the second latch, with the gate terminal of the third pull-down being driven by the set signal. Optionally, a fourth pull-down is coupled to the second node of the first latch, with the gate terminal of the fourth pull-down being driven by the set signal, and a fourth pull-up is coupled to the second node of the second latch, with the gate terminal of the fourth pull-up being driven by the inverted set signal.
In a set/reset flip-flop according to yet another embodiment of the invention, all of the above-mentioned first and second pull-ups and pull-downs are included. In another embodiment, all of the first, second, third, and fourth pullups and pull-downs are included. In another embodiment, only the third and fourth pull-ups and pull-downs are included. For all of the set/reset flip-flops of the invention, the set and reset signals are preferably restricted such that at most one of them can be active at any given time.
According to a third aspect of the invention, both the first and second aspects are applied. In other words, when an input signal is applied to one terminal of each latch, an inverted input signal is applied to the other terminal of the same latch. In addition, set and/or reset capability is provided by coupling at least one pull-up and at least one pull-down directly to the nodes of the latch. Thus, set and/or reset flip-flops are provided having the advantages of both high speed and the ability to function properly at very low power levels.