The present invention relates generally to computer system delay elements, and, more particularly, to a system and method for balancing delay of signal communication paths through well voltage adjustment.
As technology continues to advance at an unprecedented rate, the transfer of information or data has remained a high priority. In addition, as processing speeds continue to increase, the speed at which information is transferred remains key in increasing overall system speed. Traditionally, parallel busses or cables have been coupled between multiple devices to transfer information during a processing function. However, certain problems that may degrade the transferred data (such as signal loss when transmitted over long distances) have led to improvements in the manner in which such data is transferred. In addition, the multitude of wires or cables necessary for parallel connection may become cumbersome, especially in larger systems. In the past, however, alternatives to parallel connections often led to information bottlenecks, leaving parallel lines as the only viable choice.
As the need for bandwidth expands in both existing networks and those now being developed, serial backplanes (or busses) have become an advantageous alternative for solving these problems. Typically, serial backplanes employ a serializer at a transmitting end to convert and transmit data in serial order and a deserializer at a receiving end to convert the data back to parallel form once received. Such high-speed serializer/deserializer (SERDES) receivers have become the benchmark for asynchronous communication and have provided clear advantages over parallel busses. For example, SERDES receivers include transmitters and receivers, and use simplified wiring harnesses (often only a single wire per channel) that typically consume less power than their parallel-coupled counterparts. Higher performance may also be achieved because SERDES receivers reduce the cross talk that often occurs between parallel wires. In addition, SERDES receivers may be employed to transmit data over long distances without the signal degradation experienced with parallel busses, thus ultimately offering increased reliability and fidelity over parallel busses.
SERDES receivers and transmitters generally classified as mixed-signal devices are comprised of an analog function domain, a digital function domain and a parallel communication path between the analog and digital function domains. The analog domain operates to transmit and receive data over a physical medium or cable, as well as convert between serial and parallel data at high speed, while the digital domain pre or post processes data. Reliable operation of the SERDES device at high speed is dependent not only on the function of the analog and digital domains, but on the parallel communication path that connects these domains. As a result, delay matching of all data path segments that make up the parallel path is required.
Conventionally, the matching of parallel data paths between analog and digital domains has been implemented by using a combination of FET sizing and physical placement techniques in order to reduce the effect of process variance from path to path. However, such methods typically result in the use of larger devices and/or restrictions on the location thereof, both of which hamper physical implementation and can impact circuit speed. Additionally, these techniques do not fully cancel device-to-device variations that can grow, as a percentage of drawn device size, with advancing technologies.
The overall performance of an analog/digital design depends, in part, upon the ability to maintain the synchronous tracking of the two domains. Due to broad process variations, and without some means of better adjusting the delays between the two domains, maximum potential performance may not be obtained. Moreover, if the two domains do not track with one another over temperature and time, the tolerance of the overall system will be further reduced. Accordingly, an improved means of real time adjustment of the communication paths between the domains is desirable.