1. Field of the Invention
This invention relates to methods and apparatus for eliminating clock jitter in Delta-Sigma, Analog-to-Digital Converters, and more particularly methods and apparatus for eliminating clock jitter in Continuous-Time Delta-Sigma Analog-to-Digital Converters.
2. Description of Related Art
Recently there has been a rapid rise in the use of Delta-Sigma analog-to-digital converters. They are capable of high-resolution data conversion without need for tight component matching or trimming of components. Because Delta-Sigma A/D converters are insensitive to a wide range of component non-idealities present in situations where they are implemented, high resolution sampling with relaxed component specifications is obtained by employing a single-bit digital-to-analog (DAC) inside a noise-shaping loop. The noise-shaping loop operates at a sampling rate that is typically much higher than the Nyquist rate of the data that is sampled. This causes sampling and component noise to be pushed to bands that are outside the band of interest. A paper by C. Candy and G. C. Temes, entitled "Oversampling methods for A/D and DIA conversion," in Oversampling Delta-Sigma Data Converters, and published by IEEE Press, 1991, on pages 1-25 describes such converters and is incorporated by reference for its teachings on such. Due to the oversampling performed by Delta-Sigma converters, they typically require a simple anti-aliasing filter at their input.
Many Delta-Sigma converters available and in commercial use today are Switched-Capacitor ("SC") implementations. Delta-Sigma converters are commonly employed as modulators. In the simplest case, a modulator may comprise a single Delta-Sigma converter. SC converter designs are used because the design and simulation of SC filters is well understood. Consequently, SC filters may be easily integrated into a design. However, because the capacitors employed in SC Delta-Sigma converter loops sample continuous valued voltage levels SC implementations require highly linear floating capacitors. In addition, both leads of these SC capacitors are generally switched during operation. These characteristics of SC designs complicate the manufacture of SC converters because the need for high linearity floating capacitors usually necessitates a double-poly manufacturing process.
In order to overcome these shortcomings, a new methodology called Switch-Current ("SI") has emerged as an alternative to SC designs for implementing sampled analog converter designs. SI designs are described in the following references: a paper by T. S. Fiez and D. S. Allstot, entitled "CMOS Switched-Current Ladder Filters," published in IEEE J. of Solid-State Circuits, Vol. 25, No.6. December 1990, on pages 1360-1366; a paper by J. B. Hughes, N. C. Bird, and I. C. Macbeth, entitled "Switched Currents: A New Technique for Analog Sampled-Data Signal Processing," published in Proceedings of the IEEE International Symposium on Circuits and Systems, May 1989, on pages 1584-1587; and a paper by J. B. Hughes and K. W. Moulding, entitled "S-I: A Two-Step approach to Switched-Currents," published in the Proceedings of IEEE International Symposium on Circuits and Systems, 1993 on pages 1235-1238. These papers are hereby incorporated by reference for their teachings on SI designs. SI implementations advantageously can be at reduced implemented cost using standard CMOS processes. However, SI implementations have not yet achieved the same performance levels that have been achieved by the SC designs. Both SC and SI circuit implementations are examples of sampled-data systems. In a sampled-data system, a number of analog switches toggle at the rising edge of a clock signal. The sampled-data circuit is then given sufficient time to settle sampled voltages according to the circuit's switched topology. As a consequence, all voltages and currents are static in-between clock pulses in a sampled-data system.
An alternative to sampled-data systems is "Continuous-Time" ("CT") systems. In CT systems, sampling is performed at the converter output. As a consequence, the circuit nodes in the system operate in a CT mode. The implementation of Delta-Sigma modulators using the CT design approach advantageously performs sampling operations inside the modulator loop. Accordingly, sampling errors and out-of-band signals that alias into the passband are suppressed by the high gain of the loop in the passband. This advantageous effect is described in a paper by J. Schreier and B. Zhang, entitled "Delta-Sigma Modulators Employing Continuous-Time Circuitry," published in EEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications," Vol. 43, No.4, April 1996, on pages 324-332, which is incorporated by reference for its teachings on CT Delta-Sigma Modulators.
The above described effect is particularly important for passband or bandpass Delta-Sigma modulators where the input signal is varying at a rate close to or higher than the sampling rate. Bandpass modulators have become more frequently employed in IF sampling receivers. Further, because of their continuous nature of operation, CT circuits advantageously use relatively low power bandwidth amplifiers to achieve the same performance as SC and SI circuits. As a consequence, CT Delta-Sigma modulator circuits may have lower power consumption due to relatively low amplifier bias currents.
Despite these advantages, two obstacles have impeded the use of CT circuits in Delta-Sigma modulator implementations. The first obstacle is that CT circuits are much more difficult to design and simulate than are SC and SI circuits. The second obstacle is that CT circuits are orders of magnitude more susceptible to clock jitter than are SC and SI circuits. With regard to the first obstacle, recently there has been significant research into the development of tools that map simulation results for sampled-data systems (such as SC & SI circuits) to their CT counterparts. In addition, CT simulations, although tedious and time consuming, are routinely performed by designers of ICs that implement CT RF, or base band filters. Therefore, the first obstacle is not an absolute deterrent against the use of CT Delta-Sigma designs.
The second obstacle, the susceptibility to clock jitter, is much more critical and has not yet been traversed by previous designs. The CT circuit's sensitivity to clock jitter has been a serious barrier against CT implementation of Delta-Sigma converters employed in modulators as noted in the following references: a paper by O. Shoaei and M. Snelgrove, entitled "Optimal (Bandpass) Continuous-Time Sigma-Delta Modulator." published in the Proceedings of the IEEE international Symposium on Circuits and Systems, Vol. 5, May 30-Jun. 2, 1994, on pages 489-492; the Ph.d Thesis of L. Williams for the University of California, Berkeley, 1993 on pages 71-74; and in the Masters Thesis of N. Wongkomet, entitled "A Comparison of Continuous-Time and Discrete-Time Sigma-Delta Modulators," for the University of California on pages 13-17. These references are incorporated by reference for their teachings on CT circuits and implementations.
In contrast to CT implementations, in sampled-data implementations clock jitter affects only the sampling capacitors at the front-end of the modulator. Once signals are sampled by these capacitors, clock jitter has no further effect in the sampled-data systems. This is due in part because the clock period in sampled-data systems is much longer than the required settling time. Hence, clock jitter effects for sampled-data systems may be modeled as modulation of input signals due to nonuniform sampling. Assuming the effects of clock jitter to be uncorrelated with the input signal and that the effects have a white noise spectrum, the clock jitter in a sampled-data system generates a white noise component that is added to the sampled signal. Due to an oversampling ratio ("OSR"), however, the noise caused by the clock jitter in the band of interest is attenuated.
In contrast, in CT implementations, clock jitter substantially adversely affects the operation of CT circuits. In contrast to the sampled-data designs, in CT circuits, the feedback DAC is implemented as a current source that is gated by the clock. In most Delta-Sigma modulator topologies, the signal from the DAC is subtracted from the input signal and thereafter a first integrator in the circuit integrates the result. As a consequence, in CT implementations, clock jitter generates a non-uniform ON-Time in the current source. The current source is directly summed with the input signal and is therefore, indistinguishable from the input signal. Assuming a spectrally "white" clock jitter, the noise added by the current source is proportional to the OSR because during every clock cycle an uncorrelated amount is added to the input signal. Therefore, the clock jitter tolerances for CT systems must be better than that of sampled-data systems by approximately the square of the OSR (e.g. -1000 for a typical OSR of 32). This results in clock jitter tolerances and specifications that are not easily achievable in most systems. Thus, a need exists for an apparatus and method that reduces or eliminates the deleterious effects of clock jitter on CT Delta-Sigma converters and the modulators employing the converters. In particular, a need exists for an apparatus and method that reduces the effects of clock jitter in CT implementations to levels comparable to those in sampled-data implementations. The present invention provides such an apparatus and methods.