1. Field of the Invention
The present invention relates to a method of operating a split gate type of non-volatile memory cell and a semiconductor memory device having the cells, and more particularly, to a method of operating a split gate type of non-volatile memory cell overcoming the problems of the program disturbance and endurance characteristics and a method of operating a semiconductor memory device including the cells.
2. Discussion of Related Art
The split gate type of non-volatile memory cell is known in U.S. Pat. No. 5,045,488 entitled xe2x80x9cmethod of manufacturing a single transistor non-volatile semiconductor devicexe2x80x9d and U.S. Pat. No. 5,029,130 entitled xe2x80x9csingle transistor non-volatile alterable semiconductor memory devicexe2x80x9d. Methods of programming memory cells having floating gate electrodes are disclosed in U.S. Pat. No. 5,659,504 to Bude et al.
FIG. 1 illustrates the structure of a conventional split gate type of non-volatile memory cell in U.S. Pat. Nos. 5,045,488 and 5,029,130.
A source 12 and a drain 14 are formed on a semiconductor substrate 10. Between the source 12 and drain 14 is formed a channel 16. An insulating layer 18 is formed on the source 12, channel 16 and drain 14. A floating gate 20 is formed on a predetermined portion of the insulating layer 18 on the channel 16 and drain 12. Other insulating layer 22 is formed on the floating gate 20. Another insulating layer 24 is formed to be insulated from a control gate 26. The control gate 26 is formed on a predetermined portion of the insulating layer 24 and the insulating layer 18 on the source 12 and channel 16.
The operation of the split gate type of non-volatile memory cell of FIG. 1 is described with reference to FIGS. 2 to 4.
FIG. 2 illustrates a method of erasing the split gate type of non-volatile memory cell of FIG. 1. In the drawing, the source 12 and drain 14 receive the same voltage 0V, and the control gate 26 receives the voltage Vpp higher than that applied to the source 12 and drain 14. Here, an intensive coupling from the floating gate 20 to the substrate 10 and drain 14 decreases a voltage of the floating gate 20. This kind of voltage decrease allows electrons to flow from the floating gate 20 to the control gate 26 by an F-N (Fowler-Nordheim) tunneling mechanism. Accordingly, an erasing function is ascribed to the electron of the floating gate 20 moving to the control gate 26. Through the erasing operation, the floating gate 20 is charged with (+). That is, the erasing operation is performed by the voltage difference between the floating gate 20 and the control gate 26.
FIG. 3 illustrates a method of programming the split gate type of non-volatile memory cell of FIG. 1. A threshold voltage Nth is applied to the control gate 26. A high voltage Vpp is applied to the drain 14. xe2x80x9c0xe2x80x9d voltage is applied through the source 12 to the substrate 10, and thus the programming is performed.
If the high voltage Vpp is applied to the drain, the potential of the floating gate 20 is raised and the channel under the floating gate 20 is turned on. The threshold voltage Vth is applied to the control gate 26 and accordingly the channel under the control gate 26 is lightly turned on. Accordingly, electrons flow from the source 12 to drain 14. These electrons are charged in the floating gate 20 via the insulating layer 18 because of the static electricity of the floating gate 20, thus performing the programming operation. Hence, the floating gate 20 is (xe2x88x92)-charged and programmed to xe2x80x9c0xe2x80x9d.
In other words, the programming operation is performed in such a manner that a high voltage Vpp is applied to the drain of the memory cell to thereby bring the floating gate 20 to a predetermined voltage, and a predetermined voltage (a threshold voltage Vth of a transistor made of the control gate and the channel) is applied to the control gate 26 so that hot channel electrons generated when the current flows between the source 12 and drain 14 are injected into the floating gate.
FIG. 4 illustrates a method of reading the conventional split gate type of non-volatile memory cell of FIG. 1. A reference voltage Vref is applied to the control gate 26; 0V to the drain 14, 2V to the source 12, and 0V to the substrate 10, thus performing the reading operation.
If the floating gate 20 is charged with (+), the channel 16 right under the floating gate 20 is turned on. If the voltage of the control gate 26 is raised to the reference voltage Vref for turning on the channel under the control gate 26, electrons may flow from the drain 14 to the source 12, and thereby reading the data of xe2x80x9c1xe2x80x9d.
On the contrary, if the floating gate 20 is charged with (xe2x88x92), the channel right under the floating gate 20 is slightly turned on or off. A voltage level of the control gate 26 and the source 12 is raised to that of the read voltage so as to turn on the channel under the control gate 26. Hence, the current cannot flow through the channel, thereby reading the data of xe2x80x9c0xe2x80x9d.
In other words, if the floating gate 20 is charged with (+), the current is generated through the channel 16 to thereby read the data of xe2x80x9c1xe2x80x9d, and on the contrary, if the floating gate 20 is charged with (xe2x88x92), the current does not flow through the channel 16, thereby reading the data of xe2x80x9c0xe2x80x9d.
Therefore, the data is read by checking if the current flows through the memory cell or not by applying a predetermined voltage to the source 14 and the control gate 26. For this reason, if to perform the reading operation, the channels should be formed through the control gate and floating gate so that the current flows through the cell.
But, in the semiconductor memory device including the thus-structured split gate type of non-volatile memory cells, a threshold voltage Vth should be applied to the word line of a selected cell; 0V to the word line of a non-selected cell; 0V to the bit line of a selected cell; power voltage Vcc to the bit line of a non-selected cell; high voltage Vpp to the drain of a selected cell; and 0V to the drain of a non-selected cell should be respectively applied in order to generate current between the source and drain, thereby performing the programming operation. Within the programming condition, if the non-selected cell including the drain commonly connected to the drain of a selected cell is erased, the high voltage Vpp is applied to the drain of a non-selected cell, the floating gate being charged with (+), the source receiving 0V, and the substrate receiving 0V. Here, the control gate and source receive 0V, but the channel is formed by the punch through phenomenon and the current flows. The electrons conducted in the channel are injected into the floating gate, and thus programmed. Consequently, an ON-cell becomes an OFF-cell, thus causing the program interference problem.
In addition, the semiconductor memory device including the conventional split gate-typed memory cells repeatedly performs the programming and erasing operations. In the erasing operation, electrons of the floating gate should completely go out towards the control gate. But, they are trapped within the tunneling insulating layers. Consequently, the threshold voltage increases in accordance with the increasing number of operations, thus causing the problem of endurance characteristics.
It is therefore an object of the present invention to provide improved methods of operating non-volatile memory devices.
It is another object of the present invention to provide methods of operating non-volatile memory devices that enhance the endurance characteristics of memory cells therein.
It is still another object of the present invention to provide methods of operating non-volatile memory devices that increase the reliability and speed of programming and erasing operations.
It is still a further object of the present invention to provide methods of operating non-volatile memory devices that reduce the likelihood of programming interference between selected and non-selected memory cells.
Theses and other objects, advantages and features of the present invention are provided by preferred methods of operating non-volatile memory cells (e.g., EEPROM cells) that include the use of negative substrate biases during programming and erasing operations. In particular, a preferred method of operating a non-volatile memory cell includes the step of erasing the memory cell by withdrawing negative charge from a floating gate therein using a positive control electrode bias and a negative substrate bias. The use of a negative substrate bias increases the potential difference between the control electrode and the floating gate and this increase results in faster and more reliable erasing. The preferred method also includes the step of programming the memory cell by accumulating negative charge on the floating gate using a positive control electrode bias, a negative substrate bias and a positive drain bias. Here, the negative substrate bias is used advantageously to reduce the likelihood that non-selected memory cells will become inadvertently programmed during operations to program selected memory cells.