1. Field of the Invention
Embodiments of the invention relate to a computer system; and more specifically, to the use of byte-addressable non-volatile random access memory for BIOS storage.
2. Description of the Related Art
A. Current Memory and Storage Configurations
One of the limiting factors for computer innovation today is memory and storage technology. In conventional computer systems, system memory is typically implemented by dynamic random access memory (DRAM). DRAM-based memory consumes power even when no memory reads or writes occur because it must constantly recharge internal capacitors. DRAM-based memory is volatile, which means data stored in DRAM memory is lost once the power is removed.
With respect to mass storage, conventional mass storage devices typically include non-volatile magnetic media (e.g., hard disk drives) and/or flash memory (also referred to as “flash”) (e.g., solid state drives (SSDs)). These storage devices are block-addressable, which means that a single byte of storage cannot be accessed individually. Rather, bytes are read and written as multi-byte (e.g., 16 bytes) blocks of data. Generally, these storage devices are considered I/O devices because they are accessed by the processor through various I/O adapters that implement various I/O protocols. These I/O adapters and I/O protocols consume a significant amount of power and can have a significant impact on the die area and the form factor of the platform. Additionally, for portable or mobile devices (e.g., tablet computers, cameras and mobile phones) that have limited battery life, their storage devices (e.g., Embedded Multimedia Card (eMMC) and Secure Digital (SD) card) are typically coupled to the processor via low-power interconnects and I/O controllers in order to meet active and idle power budgets. These interconnects and I/O controllers cannot consistently deliver the bandwidth required for a satisfying user experience.
With respect to firmware memory, a conventional computer system typically uses flash memory devices to store persistent system information that is read often but seldom (or never) written to. For example, Basic Input and Output System (BIOS) images are typically stored in a flash memory device. Flash memory devices that are currently available in the market generally have limited speed (e.g., 50 MHz). This speed is further reduced by the overhead for read protocols (e.g., 2.5 MHz). In order to speed up the BIOS execution speed, conventional processors generally cache a portion of BIOS code during the Pre-Extensible Firmware Interface (PEI) phase of the boot process. However, the processor cache has a very limited amount of capacity. Thus, the amount of BIOS code that can be used for the initial system configuration is also very limited. The size limitation of the processor cache places a significant restriction on the size of the BIOS code used in the PEI phase (also known as the “PEI BIOS code”). Therefore, the PEI BIOS code cannot be easily extended to support a large mix of memory configurations and multiple processor families. With the rising demand for initialization of processors, process interconnects, memory and storage implemented with various technologies and multiple processor families, the need for more versatile PEI BIOS code also grows. One solution is to build a larger processor cache for caching the code. However, the size of the processor cache cannot be easily increased without a negative impact on the rest of the system.
B. Phase-Change Memory (PCM) and Related Technologies
Phase-change memory (PCM), also sometimes referred to as PCME, PRAM, PCRAM, Ovonic Unified Memory, Chalcogenide RAM and C-RAM, is a type of non-volatile computer memory which exploits the unique behavior of chalcogenide glass. As a result of heat produced by the passage of an electric current, this material can be switched between two states: crystalline and amorphous. Recent versions of PCM can achieve two additional distinct states, effectively doubling memory storage capacity. PCM is one of a number of new memory technologies competing in the non-volatile role with flash memory. Flash memory has a number of practical problems which these replacements hope to address.
For example, PCM can offer much higher performance in applications where writing quickly is important, in part because the memory element can be switched more quickly, and also because individual bits may be changed to either 1 or 0 without the need to first erase an entire block of cells (as is the case with flash). The high performance of PCM makes it potentially very beneficial in non-volatile memory roles that are currently performance-limited by memory access timing.
Additionally, while PCM devices degrade with use (like flash), they degrade much more slowly. A PCM device may survive approximately 100 million write cycles. PCM lifetime is limited by mechanisms such as degradation due to GeSbTe (GST) thermal expansion during programming, metal (and other material) migration, and other mechanisms.