Bus-masters are devices that can initiate a read or write transaction with the system memory of a bus-based computer system. An example of one such device is a processor. Processors retrieve instructions from the system memory and read, process, and write data to the system memory as dictated by the retrieved instructions.
One way to increase the performance of a computer system is to increase the rate data is transferred between the system memory and the bus-masters in the system. This can be accomplished by using high-speed memory chips for the system memory. However, the cost of memory increases dramatically with the speed of the memory. Thus, it is rarely practical to use the fastest memory available, especially in systems which require large quantities of system memory. Consequently, it has been discovered that by using a relatively small bank of relatively high-speed memory ("cache memory") as a buffer between a bus-master and the larger, slower bank of system memory, system performance can be greatly improved.
The data transfers between the system memory and the cache memory of a bus-master are controlled by a cache controller. A cache controller manages the cache memory based upon the needs of the bus-master which it serves. For example, if a processor requires data that is not currently stored in the processor's cache memory, the data must be transferred from the slower system memory to the cache memory of the processor. Once the data resides in the processor's cache memory, the processor may access the data for subsequent operations at the faster rate of the cache memory. Further, if the processor requires information that does not reside in cache memory and all of the cache memory blocks are already allocated, then the cache controller causes the cache memory to free up storage space for the newly requested data, either by writing over unmodified data in the cache memory or by storing modified data back to the system memory.
In systems having more than one cache, advantages may be gained by sharing one or more cache lines among multiple cache memories. However, such sharing could lead to data conflicts when multiple cache memories assert ownership over the same cache line at the same time. To avoid such conflicts, a protocol must be implemented to allocate the ownership of the cache lines among the various cache memories. Such protocols are referred to herein as ownership protocols, and generally allow the transfer of ownership of a cache line from one cache memory to another.
Ownership protocols may be adapted to govern cache line ownership on systems having more than one cache-equipped bus-master, such as a system with a cache-equipped processor and a cache-equipped I/O device. However, in such a system, multiple versions of the same data may exist. For example, both the cache memory of the processor and the cache memory of the I/O device may hold copies of data originating from the same block in the system memory. Data that is accessible by more than one cache-equipped bus-master is referred to as "shared data". If either the I/O device or the processor modifies a block of shared data in its local cache memory, all other copies of the data, including any copy of the data in the cache of the other bus-master, become "stale" (no longer current).
To prevent the use of stale data, the bus-master that modifies a block of shared data must broadcast the modified version of the data to all other cache-equipped bus-masters in the system. However, this broadcasting process inherently requires a large amount of inter-device communication. Such communication is typically performed over the same bus which connects the bus-masters with the system memory. As a result, these busses can become crowded, resulting in slower data transmission rates and diminished system performance.
In view of the foregoing, a device and method for making a cache-equipped bus-master aware of whether any other cache-equipped bus-master is present in the system is clearly desirable. Further, a device and method which allows a cache-equipped bus-master to determine whether other cache-equipped bus-masters are on the system without increasing the data traffic on the bus connecting the bus-masters to the system memory is clearly desirable. Finally, a device for determining the shared status of a data block without increasing the data traffic on the bus connecting the bus-masters to the system memory is clearly desirable.