This invention relates to a semiconductor memory device as a multi-port DRAM having split SAM registers.
An example of the conventional DRAM of this kind is shown in FIG. 1. As seen from this figure, the cell array constituting the RAM section is divided into a cell array where the value of the Most Significant Bit (MSB) value in the column address is "1" (hereinafter referred to as a high order cell array 1U) and a cell array where the value of the MSB is "0" (hereinafter referred to as a low order cell array 1L), and includes high order and low order SAM registers 2U and 2L in correspondence with the respective cell arrays 1U and 1L. Reference numeral 3U represents bit line pairs constituting data transfer paths between the high order cell array 1U and the high order SAM register 2U, and reference numeral 3L represents bit line pairs constituting data transfer paths between the low order cell array 1L and the low order SAM register 2L. In addition, transfer gates 4U and 4L are inserted into the bit line pairs 3U and the bit line pairs 3L, respectively.
The details of the relationship of the transfer gate 4U, the bit line pairs 3U and the high order SAM register 2U and the relationship of the transfer gate 4L, the line pairs 3L and the low order SAM register 2L are shown in FIGS. 2A and 2B, respectively.
In FIG. 2A, reference numeral 2UC represents cells constituting the high order SAM register 2U, and reference numerals 3U1 and 3U0 represent bit lines constituting respective bit line pairs 3U. The transfer gate 4U is comprised of a plurality of transistors 4UT. In addition, transistors 4UT are respectively inserted into bit lines 3U1 and 3U0 constituting respective bit pairs. Similarly, in FIG. 2B, reference numeral 2LC represents cells constituting the low order SAM register 2L, and reference numerals 3L1 and 3L0 represent bit lines constituting respective bit line pairs 3L. The transfer gate 4L is comprised of a plurality of transistors 4LT. In addition, transistors 4LT are respectively inserted into bit lines 3L1 and 3L0 constituting respective bit pairs.
In the above-mentioned configuration, by respectively allowing the transistors 4UT and 4LT to be turned ON and OFF, only the bit line pairs 3U on the high order side become active, resulting in the state where data transfer from the high order cell array 1U only to the high order SAM register 2U can be carried out. In contrast, by respectively allowing the transistors 4UT and 4LT to be turned OFF and ON, only the bit line pairs 3L on the low order side become active, resulting in the state where data transfer from the low order cell array 1L only the low order SAM register 2L can be carried out. Accordingly, by alternately placing both registers 2U and 2L on the high order and low order sides in a standby state and in an operational state to carry out the split transfer, continuous access from the SAM side can be provided.
As stated above, by employing a configuration in which the RAM section cell array is halved by the value of MSB of the column address and SAM registers are provided in correspondence with respective cell arrays, split transfer is performed every 1/2 row, permitting random access every 1/2 row from the SAM side. Thus, so-called window control can be efficiently carried out.
Namely, FIG. 3 represents a memory space of the RAM section and FIG. 4 represents a display image subjected to mapping in correspondence with the memory space. In these figures, each rectangular region indicates one word, and the figure in the word indicates an address number It is to be noted that when a specific word is designated, a notation is employed in the following description such that alphabetical symbol "AD" is attached before the address number. For example, in the case of the word of the address number "1", that word will be called "word AD1".
Let as now consider the case where a window is set in FIG. 4 in the region extending over the words AD6, AD7, AD10, AD11, AD14 and AD15 to control the window thus set.
Initially, in the case of an access every row, in order to make an access to the region extending over the words AD6, AD7, AD10, AD11, AD14 and AD15, the region including the words AD5, AD8, AD9, AD12, AD13 and AD16 must be accessed, resulting in redundant bits of at least one byte, which are useless for the window control.
On the contrary, if an access every 1/2 row can be made, it is not required to make an access to the region including the words AD5, AD8, AD9, AD12, AD13 and AD16. It is sufficient only to access the region including the words AD6, AD7, AD10, AD11, AD14 and AD15. As a result, the efficiency is improved.
However, in a conventional multi-port DRAM having split registers, there is the problem that when a frame buffer is constructed, mapping on a display image is restricted. Namely, in the case of FIG. 4, by interchangeably making accesses to the SAM registers 2U and 2L on the respective high order and low order sides, continuous access with respect to the words AD6, AD7, AD10, AD11, AD14 and AD15 can be provided.
On the other hand, FIG. 5 shows a display image subjected to mapping in another form. Let now consider the case where the control of a window set in the region extending over the words AD4, AD5, AD7, AD8, AD10 and AD11 is carried out.
In the case of carrying out a continuous split transfer, accesses to the SAM registers 2U and 2L on the respective high order and low order sides are necessarily made. However, in the case of mapping shown in FIG. 5, if such a split transfer is used, since continuous words AD5 and AD7 and continuous words AD8 and AD10 belong to the same cell array 1U or 1L, it is inevitable for maintaining continuity of those words to transfer words AD6 and AD9 to the registers 2U and 2L even if no readout operation is carried out from the registers 2U and 2L. For this reason, such a mapping as shown in FIG. 5 cannot be carried out.
As stated above, in the conventional multi-port DRAM, mapping is disadvantageously restricted in constituting a frame buffer.