In many memory devices, including random access memory (RAM) devices, data is typically accessed by supplying an address to an array of memory cells and then reading data from the memory cells that reside at the supplied address. However, in content addressable memory (CAM) devices, data within a CAM array is not accessed by initially supplying an address, but rather by initially applying data (e.g., search words) to the array and then performing a search operation to identify one or more entries within the CAM array that contain data equivalent to the applied data and thereby represent a “match” condition. In this manner, data is accessed according to its content rather than its address. Upon completion of the search operation, the identified location(s) containing the equivalent data is typically encoded to provide an address (e.g., block address+row address within a block) at which the matching entry is located. If multiple matching entries are identified in response to the search operation, then local priority encoding operations may be performed to identify a location of a best or highest priority matching entry. Such priority encoding operations frequently utilize the relative physical locations of multiple matching entries within the CAM array to identify a highest priority matching entry. An exemplary CAM device that utilizes a priority encoder to identify a highest priority matching entry is disclosed in commonly assigned U.S. Pat. No. 6,370,613 to Diede et al., entitled “Content Addressable Memory with Longest Match Detect,” the disclosure of which is hereby incorporated herein by reference. Additional CAM devices are described in U.S. Pat. Nos. 5,706,224, 5,852,569 and 5,964,857 to Srinivasan et al. and in U.S. Pat. Nos. 6,101,116, 6,256,216 and 6,128,207 to Lien et al., the disclosures of which are hereby incorporated herein by reference.
CAM cells are frequently configured as binary CAM cells that store only data bits (as “1” or “0” logic values) or as ternary CAM cells that store data bits and mask bits. As will be understood by those skilled in the art, when a mask bit within a ternary CAM cell is inactive (e.g., set to a logic 1 value), the ternary CAM cell may operate as a conventional binary CAM cell storing an “unmasked” data bit. When the mask bit is active (e.g., set to a logic 0 value), the ternary CAM cell is treated as storing a “don't care” (X) value, which means that all compare operations performed on the actively masked ternary CAM cell will result in a cell match condition. Thus, if a logic 0 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 1 data bit, the compare operation will indicate a cell match condition. A cell match condition will also be indicated if a logic 1 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 0 data bit. Accordingly, if a data word of length N, where N is an integer, is applied to a ternary CAM array having a plurality of entries therein of logical width N, then a compare operation will yield one or more match conditions whenever all the unmasked data bits of an entry in the ternary CAM array are identical to the corresponding data bits of the applied search word. This means that if the applied search word equals {1011}, the following entries will result in a match condition in a CAM comprising ternary CAM cells: {1011}, {X011}, {1X11}, {10X1}, {101X}, {XX11}, {1XX1}, . . . , {1XXX}, {XXXX}.
Applications using CAM devices include database management, disk caching, pattern and image recognition and artificial intelligence. CAM devices are also well suited for use in routing network traffic, such as in network address lookup or packet switching. A network switch comprising a CAM device having entries therein arranged in sectors is illustrated as FIG. 1 of U.S. application Ser. No. 09/962,737, entitled “Content Addressable Memory (CAM) Devices That Can Identify Highest Priority Matches in Non-Sectored CAM Arrays and Methods of Operating Same, filed Sep. 25, 2001, the disclosure of which is hereby incorporated herein by reference. Each of the illustrated sectors is organized to contain only entries having the same number of actively masked bits, with the number of masked bits identifying entries of same priority.
FIG. 1 herein illustrates a conventional CAM device having a plurality of CAM arrays therein arranged in a plurality of rows and columns. The CAM arrays in the first, second, third and fourth rows are illustrated as CAM00–CAM07, CAM10–CAM17, CAM20–CAM27 and CAM30–CAM37. A respective row priority encoder is also provided between each pair of CAM arrays. Thus, as illustrated, the CAM device of FIG. 1 includes sixteen (16) row priority encoders (shown as Row Priority Encoder00-Row Priority Encoder33). These row priority encoders perform final encoding of all match information generated by a respective pair of CAM arrays. A respective global word line decoder is also provided for each row of CAM arrays. As will be understood by those skilled in the art, each global word line decoder provides word line signals on global word lines to the CAM arrays of a respective row during reading and writing operations. Unfortunately, the CAM device of FIG. 1 may not achieve sufficiently high integration or sufficiently low power consumption because each of the row priority encoders typically consumes substantial chip area and requires substantial duplication of circuitry. Moreover, the pitch between global word lines that span across each row of CAM arrays may not be sufficiently large to achieve high yield and reliability when CAM arrays having many rows of normal and redundant CAM cells are utilized.
U.S. Pat. No. 6,307,767 to Fuh also discloses a CAM device having a plurality of CAM arrays therein that are electrically coupled to a central priority encoder. In particular, FIG. 3 of the '767 patent illustrates a prior art CAM device having a central priority encoder 120 that receives match control signals from multiple CAM arrays 101–116 during a lookup operation and then, in response, generates an output address of a highest priority matching entry. FIG. 4 of the '767 patent discloses a CAM system having a plurality of CAM arrays therein that are assigned different priority levels. Circuitry is provided for identifying which of the plurality of CAM arrays has one or more matching entries of highest priority and then latching match control signals from the identified CAM array. These latched signals are provided to a respective priority encoder, which generates a respective address of a highest priority matching entry in the identified CAM array.