1. Technical Field
The present invention relates to integrated systems on silicon chip, or SoC (“System On Chip”), comprising at least one central processing unit, or CPU, on which programs can be run, a direct memory access, or DMA, controller, and a local memory.
The present invention relates more particularly to such systems in which successive processes, for example using algorithms, are applied to input data, typically digital audio and/or video data. Such SoCs are, for example, included in electronic appliances such as set-top-boxes, personal digital assistants (PDA), mobile phones, and so on.
2. Description of the Related Art
With the dimensions of the processing cores reducing as their processing capabilities increase, one trend is to carry out a maximum of processes via software applications, the hardware components, for example the logic gates, being used only when particularly high processing performance levels, in terms of bit rate in particular, are required.
In practice, the use of software applications allows the use of algorithm languages with a high level of abstraction, for example “C” language, which facilitates the design step. Furthermore, errors are corrected in software applications simply by loading a new code.
One trade-off between the advantages of software implementations and those of hardware implementations is to combine both aspects within one and the same system, then called “firmware”, in which the system comprises on the one hand modules comprising hardware components and on the other hand software applications which are run on the CPU, the tasks to be performed by the system being divided between the hardware modules and the software applications. When executing instructions that are part of these software applications, the CPU interacts with the hardware modules, for example by sending commands to these modules. These commands use, for example, successive processes carried out by the hardware modules, for example of digital filtering, image processing, speech recognition, MPEG encoding/decoding, and other such types, on the digital data received as input to the system.
The hardware modules of the “firmware” type systems therefore receive data as input, carry out processes on this received data, and deliver the processed data as output.
It is also necessary to optimize the processing times of the software applications that the CPU applies to the data which is stored in the local memory of the system, which the CPU accesses quickly. However, in most systems on chip, it is not possible to store in local memory all the data that needs to be processed by the system on chip, for example, all the image data in the case of a system working on images. One, or even several, mass storage memories (for example, disks), hereinafter designated external memories, thus store at respective addresses in the external memories, data intended for processing by the CPU of the system on chip.
The function of the DMA controller of the system on chip is to transfer data from the external memory to the local memory, when this data is needed for the processing currently being carried out by the CPU. Similarly, the function of the DMA controller is to release storage resources in the local memory by transferring data from the local memory to the external memory. The data is thus transferred from memory to memory, from a source address in one memory to a destination address in another memory.
Moreover, in some cases, the data to be processed by the hardware modules is interchanged with the hardware modules via dedicated interfaces of the processor, normally called “streaming” interfaces, each comprising an input port named SDI (Streaming Data In) and an output port named SDO (Streaming Data Out), and a register associated with each of these ports. Each of these ports normally consists of a data bus and a few synchronization signal channels.
Such a configuration is represented in FIG. 1. The “firmware” type system on chip SP1 comprises a CPU 1, hardware modules 2 and 3. The system SP1 has access under control of the CPU 1 to an external or local memory 6. The CPU 1 comprises a register 4 (respectively 5) linked to the hardware module 3 via the output port SDO1 (respectively the input port SDI1). The CPU 1 also comprises a register 4′ (respectively 5′) linked to the hardware module 2 via the output port SDO2 (respectively the input port SDI2).
The writing, controlled by the CPU 1, in the register 4 (respectively 4′), of data from the memory 6, has the effect of applying this written data to the port SDO1 (respectively SDO2). The CPU 1 can then control the writing in the register 4 (respectively 4′), of new data from the memory 6 which will, also, be applied to the port SDO1 (respectively SDO2). The reading, controlled by the CPU 1, of the register 5 (respectively 5′) has the effect of supplying the data then applied to the port SDI1 (respectively SDI2). The writing in the memory 6 of this data is then controlled by the CPU 1.
In some cases, one and the same port can be used for reading and writing.
This solution for supplying input data and recovering output data from the hardware modules is not suitable for large volumes of data because it requires intensive involvement from the CPU.
In other configurations, each hardware module comprises its own DMA controller. For example, the “firmware” system SP2 diagrammatically represented in FIG. 2 comprises a CPU 7 and two hardware modules 8 and 9. The CPU 7 controls access to an external memory 6 via DMA controllers. The hardware modules 8 and 9 in practice each comprise a DMA controller 8′ and 9′. The DMA controller of each hardware module can thus be used to read the data to be processed in the mass memory 6, then, once this data has been processed by the hardware module, to write the data obtained in the mass memory 6. However, this solution increases the cost of the hardware modules. It also constitutes an obstacle to the granularity of the hardware modules. For example, a hardware module comprising a DMA controller carries out two successive processes on the input data, for example a temporal interpolation and a spatial interpolation of image data. If there is a desire to divide it into two hardware modules, one carrying out the temporal interpolation and the other the spatial interpolation, in order for certain data to be able to be subjected to just one of the two processes, it is then necessary to add a DMA controller.
There is therefore a need for a solution to supply input data and collect output data from the hardware modules of a “firmware” type system on chip, reducing the drawbacks of the prior art.