Semiconductor memory devices are generally organized in a bidimensional array, or memory matrix, wherein the memory elements are located at the intersection of rows, or "word lines," and columns, or "bit lines," of the matrix. To access a given memory element, it is necessary to select the word line and the bit line at the intersection of which the memory element is located. To this purpose, the memory address bus is divided into row and column address signals, which are decoded independently.
In the manufacture of semiconductor memories, defects are frequently encountered that afflict a limited number of memory elements in the memory matrix. The reason for the high probability of defects of this type resides in that in a semiconductor memory device the greatest part of the chip area is occupied by the memory matrix. Moreover, it is in the memory matrix, and not in the peripheral circuitry, that the manufacturing process characteristics are usually pushed to limits.
In order to prevent rejection of an entire chip due to the presence of a limited number of defective memory elements, out of many millions of memory elements, and therefore increase the manufacturing process yield, the typical manufacturing technique provides for a certain number of additional memory elements, commonly called redundancy memory elements. Redundancy memory elements are to be used as a replacement of those elements that, during testing of the memory device, prove defective. The selection circuits, with which the integrated component must necessarily be provided, and which allow the above-mentioned functional replacement of a defective memory element with a redundancy memory element, are indicated as a whole with the name of "redundancy circuitry," while the set of redundancy memory elements and circuitry is defined as "redundancy."
The redundancy circuitry comprises programmable non-volatile memory registers, or redundancy registers, suitable to store those address configurations corresponding to the defective memory elements. Such registers are programmed once during the memory device testing, and must retain the information stored therein even in absence of the power supply.
In practical implementations of redundancy in memory devices, both word lines and bit lines of redundancy memory elements are generally provided in the memory matrix. Each redundancy word line or bit line is associated with a respective row or column redundancy register, wherein the address of a defective word line or bit line is stored. Whenever the defective word line or bit line is addressed, the corresponding redundancy word line or bit line is selected.
As far as word lines are concerned, it has been recognized that the most frequent defect consists in short-circuits between adjacent word lines. This situation is, however, easily detected during testing. When the selection of one of two short-circuited word lines is attempted, the potential of such word line cannot rise to the designed value, being linked by the short-circuit to the potential of the adjacent non-selected word line. Therefore, when a defective word line is found during testing, it is assumed that such word line is short-circuited with the adjacent word line and both the word lines are replaced by two respective redundancy word lines. From then on, the two defective word lines will never be selected. The adjacent word line, in the scanning sequence, follows the defective word line.
Since defective word lines always come in pairs, it is known to design the row redundancy registers in such a way as to store a pair of row addresses in each row redundancy register. Therefore, each row redundancy register is associated with a respective pair of redundancy word lines: into each row redundancy register can therefore be programmed the addresses of two adjacent short-circuited word lines.
Each row redundancy register comprises programmable non-volatile memory cells wherein the addresses of two adjacent defective word lines can be programmed. Each one of such memory cells must comprise at least one programmable non-volatile memory element, such as a fuse or a floating-gate MOSFET, a load circuit for reading the information stored therein, and a program load circuit for the programming of the memory element according to the logic state of a respective address bit in the row address signal set, or row address bus.
In memory devices the association between the word lines in the memory matrix and the respective selection signals generated by the row address decoding and selection circuitry is generally such that adjacent word lines have addresses which only differ in one bit. Since, however, such bit can be any one of the bits constituting the row address signal set, it follows that in order to be always able to replace two adjacent short-circuited word lines whatsoever, each row redundancy register should store two full row addresses. This means that each row redundancy register must comprise a number of memory cells equal to twice the number of row address bits. Since the memory cells occupy each a significant chip area, this would lead to an excessive increase in the overall chip size, so that the overall process yield is decreased instead of increased. This is why a compromise is generally reached between the repairability rate for defective word line pairs and the increase in chip size. In practice, designers give up the possibility to replace two adjacent short-circuited word lines whatsoever, limiting such replacement to adjacent word lines whose addresses only differ in one or more bit belonging to a given subset of the whole row address signal set. If, for example, the row address signal set comprises m address bits, it can be thought of as being the sum of two subsets n and q such that n contains the most significant row address bits, while q contains the least significant row address bits. Limiting the replacement of defective word line pairs to take place for adjacent word lines having addresses differing in one or more bits of the subset q, it is sufficient to store in a given row redundancy register the full row address m for one of the pair of adjacent word lines, and the subset q for the other word line of the pair. This means that each row redundancy register must be made up of m+q memory cells, instead of 2 m. The impact on the repairability rate can be appreciated by considering that the probability of having a short-circuit defect between two adjacent word lines with addresses differing in one or more bits in the subset n is 1/2 q.
In the European Patent Application No. 93830474.8, incorporated herein by reference provided as background and not admitted as prior art, a program load circuit for the programming of a memory cell in a non-volatile memory register, such as a row redundancy register, is described. The datum to be programmed into the memory element of the memory cell can be directly supplied by one of the address signal lines already present in the memory device for supplying the decoding circuitry, without the need of generating additional signals.