The present invention relates to a nonvolatile semiconductor storage device that has a means for executing erase in blocks and a storage contents erase method therefor.
There has recently been a growing demand for a nonvolatile semiconductor storage device capable of executing erase in blocks, intended mainly for portable equipment.
The block erase of a conventional nonvolatile semiconductor storage device capable of executing erase in blocks will be described below with reference to FIGS. 9A, 9B, 10A, 10B, 11, 12 and 13.
FIG. 9A shows a typical memory cell structure of an EEPROM (electrically erasable programmable ROM), which is a nonvolatile semiconductor storage device. As shown in this figure, the memory cell has a MOS transistor structure of a two-layer gate constructed of a control gate 701 and a floating gate 702. This memory cell is covered with an insulating film of SiO2 or the like. This insulating film serves to provide electrical insulation of each portion that constitutes the memory cell, a function as a capacitor and protection from the external environment. A state in which a comparatively large number of electrons are injected into the floating gate 702 serves as a written state, where the memory cell has a high threshold value. A state in which a comparatively small number of electrons are injected into the floating gate 702 serves as an erased state, where the memory cell has a low threshold value. This difference between the threshold values is utilized for information storage. An operation for determining whether each memory cell is in the written state or in the erased state is a read operation.
Write into the memory cell, i.e., a transition from the erased state to the written state is achieved by injecting electrons into the floating gate.
There have been put into practice several methods for this purpose, and the write by injecting channel hot electrons (CHE) described below is most general. In concrete, by applying a high voltage (10 V, for example) to the control gate 701, applying a high voltage (6 V, for example) to the drain 705 and setting the source 703 to 0 V, a channel is formed to flow a large current between the drain 705 and the source 703. That is, electrons move from the source 703 to the drain 705. The electrons that have moved from the source 703 to the drain 705 become electrons in a high energy state due to the high voltage of the drain 705. If the energy at this time exceeds the energy barrier of an insulating film 704, then the electrons can move to the floating gate 702. With this mechanism, the memory cell is put in the written state by the injection of electrons into the floating gate 702.
On the other hand, the erase of the memory cell can be achieved by extracting the electrons accumulated in the floating gate 702. Several methods have been put into practice, and a method for extracting electrons from the source 703 is most general. According to this method, the electrons are moved by the tunnel effect from the floating gate 702 to the source 703, i.e., the memory cell is erased by, for example, making the control gate 701 have a voltage of 0 V, making the source 703 have a high voltage (12 V, for example) and floating the drain 705. This is the erase method called the high voltage source erase.
There is also put into practice a negative voltage gate erase, which is a kind of source erase and able to suppress the source voltage low. According to this erase method, the potential of the floating gate 702 is lowered by applying a negative voltage (xe2x88x9210 V, for example) to the control gate 701, applying a high voltage (5 V, for example) to the source 703 and floating the drain 705. According to this erase method, a similar tunnel effect can be obtained by a source voltage lower than that of the method of making the control gate 701 have a voltage of 0 V, and the memory cell erase can be achieved. This negative voltage gate erase is also an erase method that applies a high voltage to the source. In order to distinguish this method from the source erase that is not the negative voltage gate erase, there will be provided the description that the former is referred to as a negative voltage gate erase and the latter is referred to as a high voltage source erase in distinction.
Next, FIG. 9B shows the array structure of a flash memory. This figure shows the array structure of a NOR type flash memory, which is a typical flash memory. Row select lines 711, 712, 713, 714, 715, 716, . . . are connected to the control gates of a plurality of memory cells, and column select lines 732, 731, . . . are connected to the drains of the plurality of memory cells. The plurality of row select lines 711, . . . , 716, . . . and the plurality of column select lines 732, 731, . . . constitute a matrix, forming a memory array. In the flash memory, the memory cells in an identical block share a source line 741, and this facilitates easy batch erase of the cells in a block and also enables a substantial reduction in the memory array area.
During write in this flash memory cell array, the write is effected only on the cell of which both the row select line and the column select line are selected, and therefore, write in bits can be achieved. In the case of division into blocks that respectively have a common source line as in a flash memory, erase is executed by block erase for erasing in a batch all the memory cells in a block. It is to be noted that the block erase can be achieved with a lower source voltage than in the case of the high voltage source erase when the negative voltage gate erase is used, and therefore, only the memory cell to the gate of which a negative voltage is applied can be erased. It is also possible to execute sector erase for selectively erasing only a specified sector by dividing the block that shares a source line into sectors that are more minute erase units.
During the source erase of an EEPROM, a tunnel current between bands (BTBT: Band-To-Band Tunneling current, referred to as a BTBT current hereinafter) described in detail later cannot be avoided in the overlap region of the floating gate and the source diffusion layer. Accordingly, there is a reduction in the current efficiency of the erase operation, i.e., the ratio of electric charges to be extracted from the floating gate with respect to the charges consumed by the high voltage applied to the source.
This BTBT current will be described with reference to FIGS. 10A and 10B.
FIG. 10A schematically shows the state in the vicinity of the source 703 in the aforementioned erase operation. This erase operation is achieved by extracting electrons from the floating gate 702 to the source 703 by the FN (Fowler-Nordheim) tunneling phenomenon. An electron A inside the floating gate 702 is moved to the source 703 by the voltage applied during erase according to the FN tunneling phenomenon. This movement of the electron A is the erase operation.
However, by applying a high voltage to the source 703, a potential slope, i.e., band bending is caused by an electric field that concentrates on the surface and its vicinities of the overlap portion of the floating gate 702 and the source 703. This increases the electron potential in a valence band, and if the potential becomes higher than the conduction band of the N+ region, then there appears an electron (electron B in FIGS. 10A and 10B) that passes through the bandgap between the valence band and the conduction band by the band-to-band tunnel effect and moves to the conduction band. This is the BTBT current, occurring concurrently with a hole. FIG. 10B shows an energy band diagram of the state of electron energy at this time. The electron A is an electron that moves from the floating gate 702 to the source 703 during erase. The electron B moves in the direction of arrow as a consequence of an increase in the electron potential in the valence band due to band bending "psgr"s. That is, the BTBT current is generated. Due to this BTBT current, the current efficiency of the erase operation of source erase deteriorates. The BTBT current not only reduces the current efficiency of the erase operation but also generates a hole, becoming an important factor to deteriorate the reliability of the memory cell. That is, due to the trap of the hole, which has been generated by the band-to-band tunnel effect, in the insulating film, the reliability of the insulating film 704 is degenerated.
Since the sources of all the memory cells in a block are connected to an identical source line in the flash memory in which the block batch erase is executed, an increase in the peak current due to the BTBT current becomes a serious problem. The reason for the above is that a portion that belongs to the consumption current during the erase operation and depends on the BTBT current is roughly proportional to the number of memory cells to which the erase voltage is simultaneously applied to the source. In addition, with regard to the flash memory, due to the fact that the device operable on a single power supply voltage is mainly used for the sake of improvement in operability and the fact that the power supply employed in portable equipment on the big market of the flash memory is limited, it is often the case where a voltage boosted from the power supply voltage by a charge pump circuit is used as a source voltage to be used for source erase. In order to generate a specified high voltage regardless of the low power supply voltage, a larger current is consumed. In addition, the boosting efficiency of a voltage booster circuit, i.e., a ratio of an output electric power to an input consumption power is generally reduced in accordance with a reduction in the power supply voltage. Therefore, an increase in the consumption current due to the BTBT current becomes still more serious problem in accordance with the adoption of a single power supply voltage and a low voltage.
Next, FIG. 11 shows an example of a booster circuit for generating a high voltage to be applied to the source during erase. In this FIG. 11, only the part necessary for explaining the boost is described.
The booster circuit shown in FIG. 11 includes a charge pump circuit 808 for effecting boost from a power supply voltage 801 and generating a boosted voltage 899. In this pump circuit 808, a plurality of sets of a capacitor and a transistor such as the sets of a capacitor 821 and a transistor 822 are connected in series in a plurality of stages. Then, a set constructed of a capacitor N3 and a transistor N4 serves as the final stage of the sets connected in series.
The oscillation circuit 802 of FIG. 11 alternately puts two signal lines 803 and 804 into an enable state. A buffering circuit 805 alternately thrusts nodes 806 and 807 up to the power supply voltage on the basis of signals from these signal lines 803 and 804. For example, in the capacitor 821, the node 806 being thrust up raises the potential of the other electrode, and the boosted charges pass through the transistor 822. This charges, which have passed through the transistor, are further boosted by the operation of the capacitor 823. By repeating this operation, the booster circuit shown in FIG. 11 can generate the higher voltage 899 on the basis of the power supply voltage 801.
Then, since the transistors 822, 824, . . . , N2, N4 and so on are connected so as to prevent the backward flow, the charges of which the potential has been raised by the capacitors flow toward an output node 888. By repeating this operation, the booster circuit of FIG. 11 generates the high voltage. The fundamental operation of the booster circuit is described above.
Next, FIG. 13 shows one example of the current waveform when the erase voltage is applied. It is needless to say that the consumption current is not entirely attributed to the BTBT current. The contents of the consumption current include a variety of elements such as a current consumed by a write state machine for the control of the erase operation and a current used for the voltage control of other than the source. However, during source erase, the consumption current attributed directly to the BTBT current is especially large, and it can be safely said that the greater part of the current that varies on the time base is attributed to the BTBT current. Therefore, no explanation is provided hereinafter for the current attributed to other than the BTBT current so long as the need does not arise.
The current efficiency of the erase operation is very low due to the BTBT current. Moreover, the potential of the floating gate rises as the erase progresses. This reduces the electron potential of this region, suppresses the peak of the potential in the valence band on the surface of the N+ region and reduces the BTBT current. Therefore, the peak of the consumption current is located immediately after the application of the consumption voltage during the source erase, and the consumption current reduces according to the progress of the erase. Generally, in order to control the reduction in the power supply voltage attributed to the consumption of current, a capacitor is connected to the power supply outside the device. However, the erase time of the flash memory is very long (several milliseconds to several seconds), and it is not easy to secure a capacity sufficient for handling a large current for a long time. Due to this large peak current, it has been difficult to use a flash memory in a system such as portable equipment, which has only a small current supply capacity.
A concrete example of the execution of the negative voltage gate erase will be described more in detail with reference to FIG. 12. In the following description, a group constructed of a single or a plurality of row select lines is referred to as a row select line group, and a group constructed of a single or a plurality of column select lines is referred to as a column select line group. FIG. 12 shows only the part necessary for explaining the block erase of a nonvolatile semiconductor storage device capable of executing block erase. There are shown a memory array 910 that becomes an erase unit, a row decoder 920 for controlling the row select line group 921, a negative voltage 901 supplied to the row decoder, a debooster circuit 960 for generating the negative voltage 901, a column decoder 930 for controlling the column select line group 931, a source control circuit 940 for controlling the source line 941, a high voltage 902 supplied to the source control circuit 940 and a booster circuit 950 for generating the high voltage 902. In this case, the booster circuit 950 and the debooster circuit 960 have a construction similar to that of the aforementioned booster circuit shown in the FIG. 11. The row select line group 921 shown in FIG. 12 includes all of the row select lines connected to the memory cells included in the memory array 910. The column select line group 931 includes all of the column select lines connected to the memory cells included in the memory array 910.
When the erase of the memory array 910 is executed, the row decoder 920 applies the negative voltage 901 generated by the debooster circuit 960 to all the row select lines included in the row select line group 921. The source control circuit 940 applies the supplied high voltage 902 to the source line 941 of the memory array 910. The column select line group 931 is controlled so as to be floating by the operation of the column decoder 930 or a circuit that controls the drain voltage and is connected to the column decoder 930. Control of the drain voltage, which is not especially important in terms of the construction of the present invention, is not shown in FIG. 12. By the application of these voltages, all the memory cells included in the memory array 910 receive the negative voltage applied to their control gates and the high voltage applied to their sources and have the drain floating. This is the conventional erase operation, and the consumption current roughly becomes as shown in FIG. 13.
During the negative voltage gate erase, the sector erase can be achieved as described hereinabove. According to this method, erase is executed not on the entire block, and a negative voltage is applied only to a part of the row select lines connected to the erase block. The memory cells connected to the row select line to which this negative voltage is applied are erased, and a BTBT current is generated. On the other hand, the memory cells connected to the row select line to which the negative voltage is not applied are not erased since the electron potential of the floating gate is lowered. Furthermore, since the electron potential of the valence band in the vicinity of the N+ surface of the source is not significantly raised, the BTBT current is largely reduced. However, according to this method, the erase time is increased for the execution of the erase of the entire block. For example, when the erase is executed half-and half with regard to the number of sectors included in a block in order to suppress about half the peak current, twice the erase time is simply required.
Moreover, the BTBT current can be reduced by the channel erase method. According to the channel erase, the erase operation is achieved by extracting the electron in the floating gate to the substrate with a negative voltage applied to the control gate and with a positive voltage applied to the substrate. According to this method, the BTBT current can almost be removed. However, due to the necessity of substrate potential control, there is needed a substantial change of the manufacturing process and the control method, which cannot easily be achieved.
Moreover, the BTBT current can also be suppressed by setting low the source voltage during erase. However, there is a demerit that the time required for the erase largely increases by simply lowering the source voltage.
Accordingly, a technology for restraining the increase of the erase time to a minimum while suppressing the peak current is soft erase. This soft erase, which is originally a technology intended for improving the reliability of the memory cell, also serves as a means for suppressing the BTBT current ascribed to the hole generating mechanism during erase and is also effective for a reduction in the erase current.
During this soft erase, the source voltage is set lower than usual for a certain period from the start of the erase operation, and the source voltage is set back to the normal voltage after the progress of the erase operation to a certain extent. Since the source voltage is low immediately after the application of the erase voltage when the BTBT current is maximized, the peak current is suppressed. When the source voltage is set back to the normal erase voltage, the peak current does not increase so much because the erase has progressed to a certain extent.
However, it is very difficult to quantitatively grasp the correlation between the source voltage and the peak current value if the variations of the process, the deterioration of the memory cells and so on are taken into consideration. Moreover, the same thing can be said for the quantitative correlation between the erase time and the source voltage. Therefore, it can be qualitatively estimated to reduce the peak current by the soft erase, but a quantitative determination is difficult.
Accordingly, as a means for enabling the quantitative estimation of the suppression of the consumption current peak, there is proposed a method for limiting the consumption current of the source voltage generation circuit. This method is a method for providing the source voltage generation circuit with a current limiting means. This technology pays attention to the fact that the consumption current attributed to the BTBT current is consumed by the booster circuit for generating the source voltage. The high voltage generated by the booster circuit flows a current to the substrate in the form of the BTBT current. However, when the electric charges lost by the BTBT current cannot be replenished, the source voltage is lowered due to limitations on the consumption current of the booster circuit, and a soft erase state is established.
Then, the source voltage automatically rises when the BTBT current is reduced with the progress of erase. By using this method, the consumption current attributed to the BTBT current can reliably be suppressed by the required amount. If the consumption current due to the BTBT current is desired to be suppressed to a half, it is proper to limit the consumption current of the booster circuit to a half.
However, since the source voltage during erase is not specified by this method, it is very difficult to estimate the required erase time.
Next, a prior art example of the operation of erasing a plurality of blocks will be described with reference to FIGS. 14 and 15. FIG. 14 shows only a part that belongs to a nonvolatile semiconductor storage device capable of executing block erase and is necessary for explaining the erase of the plurality of blocks. A block 1070 and a block 1075, which are the erase blocks, have respective memory arrays 1010 and 1015 and the peripheral circuits thereof. That is, the block 1070 is constructed of a memory array 1010 that becomes an erase unit, a row decoder 1020 for controlling a row select line group 1021 of the memory array 1010, a column decoder 1030 for controlling a column select line group 1031 of the memory array 1010 and a source control circuit 1040 for controlling a source line 1041 of the memory array 1010.
Likewise, the block 1075 is constructed of a memory array 1015 that becomes an erase unit, a row decoder 1025 for controlling a row select line group 1026 of the memory array 1015, a column decoder 1035 for controlling a column selection group 1036 of the memory array 1015 and a source control circuit 1045 for controlling a source line 1046 of the memory array 1015.
Furthermore, a debooster circuit 1060 shown in FIG. 14 supplies a negative voltage 1001 to the row decoders 1020 and 1025 provided for a plurality of blocks 1070 and 1075, while a booster circuit 1050 supplies a high voltage 1002 to the source control circuits 1040 and 1045 of the blocks 1070 and 1075. In this case, the debooster circuit 1060 and the booster circuit 1050 have a construction similar to that of the aforementioned booster circuit shown in FIG. 11.
The row select line groups 1021 and 1026 shown in FIG. 14 include all the row select lines connected to the memory cells included in the memory arrays 1010 and 1015. The column select line groups 1031 and 1036 include all the column select lines connected to the memory cells included in the memory arrays 1010 and 1015.
These memory arrays 1010 and 1015 are the two of the plurality of memory arrays included in this semiconductor storage device. When the storage contents of either one of these memory arrays 1010 and 1015 are erased, the storage contents of a single memory array are erased according to one example by the operation already explained with reference to FIG. 12.
In this case, a prior art example of the erase voltage applying method when both the memory arrays 1010 and 1015 are concurrently erased will be described with reference to FIG. 15.
Between a time t0 and a time t1, an erase voltage (xe2x88x9210 V, for example) is applied to the row select line group 1021, and an erase voltage (5 V, for example) is applied to the source line 1041. Between the time t1 and a time t2, an erase voltage is applied to the row select line group 1026, and an erase voltage is applied to the source line 1046. As a consequence of this series of operations, the storage contents of the memory cells connected to the memory array 1010 are erased between the time t0 and the time t1, and the storage contents of the memory cells connected to the memory array 1015 are erased between the time t1 and the time t2. Therefore, the storage contents stored in the two memory arrays 1010 and 1015 are entirely erased.
Although the case of the erase of the two blocks 1070 and 1075 has been described with reference to FIGS. 14 and 15, the erase can be executed by a method similar to the aforementioned method when erasing three or more blocks. According to the erase method described with reference to FIG. 15, the time of erase is roughly proportional to the number of blocks erased.
Then, one example of the method for erasing two blocks at a higher speed will be described with reference to FIG. 16. As shown in FIG. 16, between the time t0 and the time t1, the row line voltage during erase is applied to both of the row select line groups 1021 and 1026, and a source line voltage during erase is applied to both of the source lines 1041 and 1046. By this operation, between the time t0 and the time t1, the storage contents of the memory cells included in both the memory arrays 1010 and 1015 are erased. Therefore, according to the erase method shown in FIG. 16, the erase can be executed at a higher speed than in the case of the aforementioned erase method shown in FIG. 15. Although the case of the erase of the two blocks has been described with reference to FIG. 16, the erase voltage can similarly be simultaneously applied to three or more blocks.
However, the erase method shown in FIG. 16 has the problems as follows. That is, the first problem is that the sum total of the BTBT current flowing from the sources of the memory cells is increased by an increase in the number of memory cells to be simultaneously erased, and when the sum of the currents exceeds the current supply capacity of the booster circuit 1050, the potential of the high voltage 1002 cannot be maintained, hindering the erase operation. The second problem is that the number of blocks that can be simultaneously erased is limited also by a resistance that accompanies the high voltage 1002. The limitations will be described with reference to FIG. 18.
FIG. 18 shows a model of the source line when four blocks 1170a, 1170b, 1170c and 1170d are provided as a concrete example of the nonvolatile semiconductor storage device that has a plurality of blocks. The blocks 1170a, b, c and d are each provided with a memory array and its peripheral circuits, which are collectively shown in the form of blocks in FIG. 18. Moreover, a circuit for applying a voltage to the row line group and a control circuit are required for the erase operation. FIG. 18 shows elements necessary for explaining the limitations on the number of erase blocks due to the resistance of the source line.
As shown in FIG. 18, this nonvolatile semiconductor storage device includes a booster circuit 1150 for generating a source voltage during erase, four blocks 1170a through 1170d that become an erase unit and the resistances 1180a through 1180d of the source lines. This booster circuit 1150 generates a high voltage 1102 and supplies high voltages 1102a through 1102d to the blocks 1170a through 1170d. The resistances 1180a through 1180d of the source lines are caused by the wiring of the node, switching elements and so on and do not normally become zero. The parasitism of the source resistance also changes depending on the arrangement of the blocks, and the case of resistances parasitic in series will be described as the most comprehensible example.
In this case, as one example for simplicity, it is assumed that the resistances 1180a through 1180d are all 10 xcexa9, each of the blocks 1170a through 1170d consumes a current of 10 mA at a maximum from the source during erase, the source voltage during erase is permitted to drop to 0.4 V from the voltage generated by the booster circuit 1150, and the current supply capacity of the booster circuit 1150 is sufficient.
For example, when the erase of the block 1170a is executed, the currents flowing through the resistances 1180a through 1180d are 10 mA, 0 mA, 0 mA and 0 mA, respectively. A voltage drop due to a resistance becomes the product of the resistance value and the current value, and therefore, the voltage 1102a becomes a voltage dropped by 0.1 V from the voltage 1102. Since this drop voltage is within a permissible range, the erase can be achieved. Likewise, with regard to the blocks 1170b through 1170d, the voltages 1102b, 1102c and 1102d applied to the sources become the voltages dropped by 0.2 V, 0.3 V and 0.4 V, respectively, from the voltage 1102. The voltages are within a permissible range.
The case where the four blocks of the blocks 1170a through 1170d are required to be all erased in order to execute the erase of a plurality of blocks (i.e., multi-block erase) at high speed will be described next. If an erase voltage is simultaneously applied to all of the blocks 1170a through 1170d, the currents flowing through the resistances 1180a through 1180d become 40 mA, 30 mA, 20 mA and 10 mA, respectively. Consequently, the source voltages 1102a through 1102d drop from the high voltage 1102 to 0.4 V, 0.7 V, 0.9 V and 1.0 V. The drop of the source voltages of the blocks 1170b through 1170d described above exceeds the permissible range and possibly hinders the erase operation. Therefore, even if the booster circuit 1150 has a sufficient current supply capacity, it is not allowed to simultaneously apply the erase voltage to the four blocks 1170a through 1170d. 
Furthermore, when the erase voltage is simultaneously applied to the two blocks of the aforementioned four blocks, there inevitably occurs a situation that the voltage drop on the source line exceeds the permissible range no matter which combination is selected. Therefore, when erasing these four blocks 1170a through 1170d, there has been repeated four times the erase operation of one block.
This source resistance can be reduced by reducing the sheet resistance of the wiring layer of the source line, shortening the source line wiring and increasing the capacity of the switching element when the switching element is employed. As a method for reducing this sheet resistance, the reduction can be achieved by devising the material and thickness of the wiring layer. However, the devising, which requires a change of process, is generally not easy. Moreover, shortening the source wiring has limitations attributed to the layout arrangement of the blocks and so on. Moreover, thickening the source wiring width and increasing the switching element capacity lead to an increase in the chip area, and there is a concern about the sacrifice of the chip size and cost. Therefore, it is unavoidable that a resistance is parasitic on the source line to a certain extent, and this parasitic resistance possibly limits the simultaneous erase of a plurality of blocks.
As described above, there have been limitations on the simultaneous erase of a plurality of blocks due to the current supply capacity of the booster circuit that generates the high voltage applied to the source and the resistance parasitic on the source line.
As described above, according to the conventional source erase method, the peak value of the consumption current during erase is large, and there is a serious hindrance to the use of the method in portable equipment whose current supply capacity is not sufficiently large and the like.
Moreover, the substrate erase, which is the erase method that causes no BTBT current, requires substrate potential control, and therefore, a special process and control must be prepared.
Moreover, according to the method for reducing the peak current by soft erase, it is generally difficult to quantitatively estimate the correlation between the applied source voltage and the peak current value. Using the technology of limiting the consumption current of the booster circuit is also effective for the suppression of the consumption current, but it is difficult to estimate the time necessary for erase.
Moreover, it has conventionally been difficult to execute batch erase of a plurality of blocks, and when only a single block can be simultaneously erased, the time necessary for erasing a plurality of blocks has been increased roughly in proportion to the number of blocks in which the erase is executed.
Accordingly, the object of the present invention is to provide a nonvolatile semiconductor storage device capable of quantitatively estimating the required erase time and the peak value of an erase current, suppressing an increase in the erase time and reducing the erase current and a storage contents erase method therefor. The present invention also provides a method capable of efficiently executing the erase of a plurality of blocks.
In order to achieve the above object, according to the present invention, there is provided a nonvolatile semiconductor storage device having a memory array constructed of a plurality of memory cells, a row select line control circuit, a column select line control circuit and a source line control circuit for controlling row select lines, column select lines and source lines respectively connected to each of the memory cells and a voltage generation circuit for individually generating voltages to be applied to the row select line and the source line, the memory array being subjected to erase by applying specified voltages to the row select line and the source line, wherein
the row select line control circuit comprises a line group independent control means capable of independently controlling a plurality of row select line groups each of which is constructed of at least one row select line, and
the voltage generation circuit comprises a consumption current limiting means for limiting a consumption current of the voltage generation circuit.
In this invention, the line group independent control means independently controls a plurality of row select line groups, and voltages generated by the voltage generation circuit are applied to the individual row select line groups with time shifts. As a result of this, the peak of consumption current can be suppressed, so that the consumption current can be reduced.
Further, in this invention, the consumption current limiting means of the voltage generation circuit limits the consumption current of the voltage generation circuit, allowing voltages to be generated within a range under a specified current value according to the conditions of voltage application from the voltage generation circuit to the individual row select line groups. Thus, a further reduction in consumption current at a shorter scale can be achieved.
In one embodiment, there is provided a nonvolatile semiconductor storage device having a memory array constructed of a plurality of memory cells, a row select line control circuit, a column select line control circuit and a source line control circuit for controlling row select lines, column select lines and source lines respectively connected to each of the memory cells and a voltage generation circuit for individually generating voltages to be applied to the row select line and the source line, the memory array being subjected to erase by applying specified voltages to the row select line and the source line, wherein
the source line control circuit comprises an independent control means capable of independently controlling a plurality of source lines, and
the voltage generation circuit comprises a consumption current limiting means for limiting a consumption current of the voltage generation circuit.
In this one embodiment, the independent control means independently controls a plurality of source lines, and voltages generated by the voltage generation circuit are applied to the individual source lines with time shifts. As a result of this, the peak of consumption current can be suppressed, so that the consumption current can be reduced.
Further, in this embodiment, the consumption current limiting means of the voltage generation circuit limits the consumption current of the voltage generation circuit, allowing voltages to be generated within a range under a specified current value according to the conditions of voltage application from the voltage generation circuit to the individual source lines. Thus, a further reduction in consumption current at a shorter scale can be achieved.
In another embodiment, the consumption current limiting means is constructed of:
an output current limiting means.
In this embodiment, since the consumption current limiting means is implemented by the output current limiting circuit, the voltage generation means outputs voltages within a range under a specified current by virtue of operations of this limiting circuit. As a result of this, output current load is limited, drops due to load currents are reduced, and the power supply capability of the voltage generation means is alleviated, so that the consumption current is limited. This function of reducing the consumption current enables the voltage generation means to be optimum for the source voltage generation circuit in block erase operations in rewritable nonvolatile semiconductor storage devices.
In an embodiment, the consumption current limiting means is constructed of:
an input current limiting circuit.
In this embodiment, since the consumption current limiting means is implemented by an input current limiting circuit, the consumption current can be reduced by limiting the current of the power supply current of the voltage generation means.
In another embodiment, the consumption current limiting means activates only partially the voltage generation circuit.
In this embodiment, since the consumption current limiting means activates only partially the voltage generation circuit, the consumption current of the voltage generation circuit is reduced. This function of reducing the consumption current enables the voltage generation circuit to be optimally usable for the source voltage generation circuit in block erase operations.
In an embodiment, there is provided a storage contents erase method for a nonvolatile semiconductor storage device comprising the step of:
changing a number of row select line groups to which a specified voltage necessary for erase is simultaneously applied by the line group independent control means according to a specified condition before the erase of all the memory cells in the memory array is completed among a plurality of row select line groups capable of being independently controlled.
In this embodiment, the number of row select line groups to which a specified voltage required for erase is simultaneously applied is changed over according to predetermined conditions before the erase of all the memory cells within the memory array is completed. As a result of this, a reduction in peak value of the consumption current can be achieved.
In another embodiment, there is provided a storage contents erase method for a nonvolatile semiconductor storage device comprising the step of:
changing a number of source lines to which a specified voltage necessary for erase is simultaneously applied by the independent control means according to a specified condition before the erase of all the memory cells in the memory array is completed among a plurality of source lines capable of being independently controlled.
In this embodiment, among a plurality of source lines that can be controlled independently by the independent control means, the number of source lines to which a specified voltage required for erase is simultaneously applied is changed over according to predetermined conditions before the erase of all the memory cells within the memory array is completed. As a result of this, a reduction in peak value of the consumption current can be achieved.
In an embodiment, the number of the row select line groups or the source lines to which the specified voltage necessary for the erase is simultaneously applied is changed every time a consumption current in the voltage generation circuit for generating the specified voltage becomes not higher than a specified value.
In this embodiment, a reduction of peak value of the consumption current can be achieved.
In another embodiment, the number of the row select line groups or the source lines to which the specified voltage necessary for the erase is simultaneously applied is changed every predetermined time.
In this embodiment, a reduction in peak value of the consumption current can be achieved.
In an embodiment, the number of the row select line groups or the source lines to which the specified voltage necessary for the erase is simultaneously applied is changed every time a threshold voltage of an objective memory cell to be erased becomes not higher than a specified value.
In this embodiment, the number of row select line groups or source lines to which the erase voltage is applied is changed over stepwise in an erase operation. Thus, the peak consumption current can be reduced efficiently.
In another embodiment, overerase verify after an erase operation is executed after completing the erase operation of all objective memory cells to be erased.
In this embodiment, after the erase operation of all the memory cells that are targeted for erase is completed, an overerase verify subsequent to this erase operation is executed. Therefore, the memory cells never undergo any erase disturb after the overerase verify. As a consequence, it can be ensured that the threshold voltages of the memory cells fall within a reference threshold voltage range that has been checked at the time of the overerase verify. That is, according to this embodiment, a verify precision equivalent to that of the conventional batch erase method can be obtained.
In an embodiment, erase is executed by switchover between an erase method for erasing in a batch a block of a memory cell area selected by the row select line group and the source line by controlling all the row select line groups in an identical operation and controlling all the source lines in an identical operation and the storage contents erase method.
With the erase method of this embodiment, it becomes possible to change over between the conventional block erase and the above-described erase method for reducing the consumption current peak, in accordance with the current supply capability of the power supply.
In another embodiment, a nonvolatile semiconductor storage device further comprises an erase method switchover means for executing the erase by switchover between an erase method for erasing in a batch a block of a memory cell area selected by the row select line group and the source line by controlling all the row select line groups in an identical operation and controlling all the source lines in an identical operation and the storage contents erase method.
In the nonvolatile semiconductor storage device of this embodiment, it becomes possible to change over between the conventional block erase and the above-described erase method for reducing the consumption current peak, in accordance with the current supply capability of the power supply.
In an embodiment, there is provided a nonvolatile semiconductor storage device storage contents erase method for executing erase of storage contents of a nonvolatile semiconductor storage device having a plurality of memory blocks including a memory array constructed of a plurality of memory cells, a row select line control circuit, a column select line control circuit and a source line control circuit for respectively controlling row select lines, column select lines and source lines respectively connected to each of the memory cells in each of the memory blocks and a voltage generation circuit for individually generating voltages to be applied to the row select line and the source line, by applying specified voltages to the row select line and the source line, comprising the steps of:
concurrently selecting the row select lines connected to the memory block by the row select line control circuit;
concurrently selecting the source lines connected to the memory block by the source line control circuit; and
changing according to a specified condition a number of the memory blocks to the row select lines of which a specified voltage necessary for erase is simultaneously applied until the erase of all the memory cells included in the memory block in which the erase is executed is completed.
In this embodiment, the number of memory blocks to row select lines of which a specified voltage required for erase is simultaneously applied is changed over according to predetermined conditions. Thus, while increases in erase time are suppressed, a reduction in the consumption current can be achieved, so that the erase of a plurality of blocks can be executed efficiently.
In an embodiment, the number of the memory blocks to the row select lines or the source lines of which the specified voltage necessary for the erase is simultaneously applied is changed every time a consumption current in the voltage generation circuit for generating the specified voltage becomes not higher than a specified value.
According to this embodiment, while increases in erase time are suppressed, a reduction in the consumption current can be achieved and the peak consumption current can be reduced efficiently, so that the erase of a plurality of blocks can be executed efficiently.
In an embodiment, the number of the memory blocks to both the row select line groups and the source lines of which an erase voltage is simultaneously applied is varied with a block in which the connected source line has a comparatively large wiring resistance and with a block in which the connected source line has a comparatively small wiring resistance.
According to this embodiment, while drops of the source voltage in an erase operation are suppressed, a shortening of the erase time can be achieved and a speedup of erase of a plurality of blocks can be achieved.
In an embodiment, the blocks to which the erase voltage is simultaneously applied are selected so that a maximum value of a potential drop from an output of the voltage generation circuit for generating a voltage to be applied to the source line inputted to the block in which erase is executed falls within a predetermined permissible range.
According to this embodiment, while drops of the source voltage in an erase operation are suppressed to within a permissible range, a shortening of erase time can be achieved and a speedup of erase of a plurality of blocks can be achieved.
In an embodiment, the erase of the memory array in the objective block to be erased is executed by the erase method.
In this embodiment, memory arrays within a block targeted for erase can be erased with high efficiency.