1. Field of the Invention
The invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a non-volatile memory.
2. Description of Related Art
When semiconductor technology enters deep sub-micron manufacturing process, sizes of devices are gradually decreased, which means decreased memory cell size with respect to memory device. On the other hand, as data which information electronic products (such as computer, mobile phone, digital camera and personal digital assistant (PDA)) have to handle and store is increasing, the memory capacity required by these information electronic products becomes larger and larger. In the case of decreased device size and increased memory capacity demand, a common goal in the field is how to manufacture memory devices having decreased size and high integration while maintaining good qualities.
A non-volatile memory is capable of safeguarding stored data even after the power supplied to the non-volatile memory is cut off, and therefore the non-volatile memory has been extensively applied to personal computers and electronic equipments.
A typical non-volatile memory cell has a memory gate and a control gate made by doped polysilicon. A dielectric layer is disposed respectively between the memory gate and a substrate, and between the control gate and the substrate.
However, the manufacture of the above-mentioned non-volatile memory cell requires forming a plurality of polysilicon layers and a plurality of dielectric layers. During the manufacturing process, several photomasking steps are carried out, which not only lengthens the manufacturing process but also incurs more manufacturing cost.
A conventional NOR type non-volatile memory cell formed by two transistors connected in series includes a select transistor and a memory gate transistor. For this type of memory cell, there is no need to form a plurality of polysilicon layers. Hence the manufacturing process of such non-volatile memory cell can be integrated with the manufacturing process of a complementary metal oxide semiconductor transistor.
Generally, the non-volatile memory consists of a plurality of memory cells located in a memory cell region and a plurality of logic devices (such as input/output transistor, core transistor, etc.) located in a periphery circuit region. The select transistor and the input/output transistor in the periphery circuit region are manufactured in the same process. A gate dielectric layer of the input/output transistor is usually thicker for withstanding a higher operating voltage. However, in a situation where the sizes of devices are decreased due to increased integration of an integrated circuit, the size of the memory cell is decreased as well. If a thickness of a gate dielectric layer of the select transistor is equal to the thickness of the gate dielectric layer of the input/output transistor in the periphery circuit region, during operation of the memory, a larger voltage needs to be applied to a gate of the select transistor, with the result that a driving capability of a non-volatile memory device is reduced. Therefore, it will be an important issue that how to enable the non-volatile memory device to have a better driving capability.