1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly, to a wafer level package having connection terminals whose side surfaces are exposed and a method of fabricating the same. The present invention also relates to a semiconductor module including a wafer level package having connection terminals whose side surfaces are exposed, and a method of fabricating the same.
2. Description of the Related Art
A semiconductor package serves to electrically connect inputs and outputs of a semiconductor chip to an external circuit and to protect the semiconductor chip. As electronic devices get smaller and lighter and have higher performances, small, light, economical, and highly reliable semiconductor packages are required. To satisfy these requirements, wafer level packages have been developed in which the assembling or packaging of a semiconductor chip is completed at a wafer level. In the wafer level package, all semiconductor chips on a wafer are collectively subject to fabrication processes such as assembling processes, resulting in greatly reduced semiconductor device fabrication costs, better incorporation of packaging functions and semiconductor chip functions, improvements in thermal and electrical characteristics of the semiconductor devices, and miniaturization of the package to the relative dimension of the semiconductor chip.
FIG. 1 is a cross-sectional view illustrating a conventional wafer level package 100.
Referring to FIG. 1, a metal pad 120 is formed on a front surface of a wafer 110. A metal wiring layer 150 is electrically connected to the metal pad 120 and to a solder ball 170. A first insulating layer 130 and a second insulating layer 140 are formed between the metal pad 120 and the metal wiring layer 150, and a third insulating layer 160 is formed on the metal wiring layer 150. The first to third insulating layers 130, 140, and 160 include openings 135, 145, and 165, respectively.
In the conventional wafer level package 100, the metal wiring layer 150 is made of, for example, copper, and generally needs to be redistributed on the semiconductor chip in order to adhere the solder ball 170 to the metal pad 120 of the semiconductor chip for a proper electrical connection with an external circuit. Such a redistribution process of the metal wiring layer 150 increases the fabricating cost and the metal wiring layer 150 may be separated from the surface of the semiconductor chip, thereby degrading the reliability of the package.
Furthermore, the area of the semiconductor chip limits the number of the solder balls 170 that can be arranged on the semiconductor chip. Accordingly, it is difficult to lay out a large number of solder balls 170 on the semiconductor chip. To solve this problem, the solder balls 170 can be reduced in size so that a plurality of the solder balls 170 can be more easily arranged on the semiconductor chip. However, the reduced size of the solder ball weakens the adhesion of the solder ball to the underlying metal pad.