The present invention relates to a method of refreshing a dynamic RAM (Random Access Memory) used by any personal computer, more particularly to a new method of refreshing a dynamic RAM so that the desired refreshing of a dynamic RAM can be executed by means of relatively simple circuitry, and therefore any of the high-speed devices using the real-time means such as a floppy disc driver unit can easily be accessed.
The semi-conductor manufacturing technology has achieved an overall development in recent years. This modern technology has successfully brought a variety of ICs into the field of the computer memory means. The problem of trading cost economy for further improvement of memory density potentials has been solved by now, and as a result, a large quantity of low-cost ICs, having greater capacities, have been delivered to the industrial markets, including ROM, static RAM, dynamic RAM, and others. Of these, compared to the static RAM, the dynamic RAM must be periodically subject to a refreshing process in order to properly store a variety of data in memory. Usually, such a periodic refreshing process must be executed at intervals of every 2 microseconds. In terms of the operational speed, such a dynamic RAM is rather disadvantageous when compared to other memories having identical access time such as the static RAM. This is because a short period of delay must be taken into account covering a period from the entry of the address up to the data output. Conversely, the dynamic RAM can be advantageously used in a system such as one incorporating a high-density memory, for example, that incorporates a minimum of 16K byte memory. Any dynamic RAM stores its bit data in the bit-cell capacitor as charge. A typical construction of the dynamic RAM is shown in FIG. 1 of the attached drawings. During the write mode, any desired data is fed to the input of the dynamic RAM so that switch S1 is closed. Capacitor C is either charged or discharged according to the status of the input data. During the read mode, switch S2 is closed so that the voltage in capacitor C is compared to the reference voltage Vref of comparator CP, and then according to the difference of the voltages compared, either "1" or "0" of the binary code is transmitted to the output of the dynamic RAM. When the dynamic RAM remains in the data-hold mode, all the switches S1, S2, and S3 remain open so that the data can remain in capacitor C. Nevertheless, since the MOS capacitor is characteristically subject to leakage resistance R, the capacitor charge will be gradually discharged. To compensate for this, a process called "refreshing" must be applied to any dynamic RAM being used. To achieve this, the dynamic RAM controller must be subjected to the "refreshing" process at intervals of every 2 microseconds so that the data stored in the bit-cell can properly be held unaffected.
Conventionally, in regard to the refreshing process applied to the dynamic RAM, a variety of means are made available, for example, "burst mode refreshing process" capable of refreshing all lines within a specific period of time, for example: within 2 microseconds, and the other one called "cycle steal refreshing process" (or called "single cycle refreshing process") capable of sequentially refreshing every line at specific intervals. Of these, the "burst mode refreshing process" can be executed by means of a relatively simple circuitry. However, since this process requires entire operation of the CPU (central processing unit) to periodically halt for a relatively long period, for example, at least for a period of 50-60 microseconds for each cycle, and as a result, using this process, any real-time high-speed devices such as a floppy disc driver system cannot be accessed. Conversely, since the "cycle steal refreshing process" uses the surplus time of the CPU bus cycle, this process is advantageous because it does not cause the CPU to actually decrease the speed needed to execute any operation. On the other hand, this second process still has a difficult problem in that a considerably high speed is needed to properly operate the circuits, and the operation timing cannot easily be controlled. Of these two refreshing processes, in reference to the attached drawings, some of the existing problems related to the "burst mode refreshing process" are described below.
A simplified block diagram shown in FIG. 2 and its flowchart shown in FIG. 3 respectively denote a significant disadvantage of the conventional "burst mode refreshing process". The data contents of a dynamic RAM (DRAM) loaded in the CPU, of a microprocessor are continuously transmitted to the floppy disc controller (FDC). If the time at which the data contents were loaded from the DRAM to the CPU exactly coincides with the period when the DRAM is being refreshed by the "burst mode refreshing process", the CPU will be obliged to remain in a stand-by mode for a long time, and as a result, the contents of the dynamic RAM loaded into the CPU cannot be written into the floppy disc controller (FDC) within a pre determined period. In FIGS. 2 and 3, symbol DRAM represents a dynamic RAM, symbol FDC represents a floppy disc controller, symbol FDD represents a floppy disc device, and symbol CPU represents the central processing unit. Symbol DRQ is a data request signal output from the FDC to the CPU, while symbols RD and WT respectively represent the read and write signals output from the CPU to the FDC.
In reference to the flowchart of the CPU operation shown in FIG. 3, operations of the circuit shown in the block diagram are described below. During step S1, if the floppy disc controller (FDC) outputs a data request signal (DRQ=High) to the CPU, the mode then proceeds to step S2 where the contents of the address designated dynamic RAM (DRAM) are loaded into the CPU. After being temporarily stored in the CPU, said contents are then sent to the floppy disc controller (FDC) during the next step S3. This operation is continuously executed until all the contents of the dynamic RAM (DRAM) loaded in the CPU are completely transmitted to the floppy disc controller (FDC) during the next step S4. In this case, such a floppy disc controller can consist of a microprocessor. If any of the single side floppy discs is used as the floppy disc controller (FDC), all the data contained in the dynamic RAM (DRAM) must be fed to the floppy disc controller within 32 microseconds from the time the data request signal (DRQ) is received. This corresponds to the processing period covering steps S1 through S3 shown in the block diagram of FIG. 2. These processes are actually executed within about 30 microseconds. Using a programmed system like this, when transmitting the data contents of the dynamic RAM (DRAM) temporarily stored in the CPU to the floppy disc controller (FDC), a when such contents output from the dynamic RAM are being fed to the CPU, if this timing coincides with the period of the "burst mode refreshing process", the CPU will be obliged to stand by for a long time, and as a result, the necessary data stored in the CPU cannot be written into the floppy disc controller within the predetermined period of time. To prevent this, if the refreshing process is stopped, the period between refreshes of the RAM which should normally last 2 microseconds will run out, and as a result, the data contents remaining in the dynamic RAM will eventually be destroyed.