1. Field of the Invention
The present invention relates to the field of display, and in particular to a thin film transistor (TFT) backplane and manufacturing method thereof.
2. The Related Arts
In the field of display technology, liquid crystal display (LCD) and organic light emitting diode (OLED) display and other flat panel display technology have gradually replaced CRT monitors, wherein the OLED provides the advantages of self-luminous, low driving voltage, high luminous efficiency, short response time, high clarity and contrast, wide viewing angle of near-180°, wide operating temperature range, enabling flexible display and large full-color display, and is recognized as the technology with most potential.
The driving types of OLED can be divided according to the passive matrix OLED (PMOLED) and active matrix OLED (AMOLED). The low temperature poly silicon (LTPS) thin film transistor (TFT) has gained attention from the industry in high resolution AMOLED technology. Compared with the amorphous silicon (a-Si), LTPS TFT has higher carrier mobility, and the device has fast response and good stability to meet the requirements of high resolution AMOLED display.
The gate insulation (GI) commonly used in known LTPS TFT backplane of AMOLED usually uses the double-layered structure of silicon dioxide/silicon nitride (SiO2/SiNx), wherein the SiO2 layer contacts the polysilicon active layer, and the SiNx layer contacts the gate. Compared to SiO2 layer, SiNx layer provides better barrier for mobile ions, such as, sodium ions (Na+), potassium ions (K+), has a greater dielectric constant, can be made thinner than the SiO2 layer under the same insulating capacity, has a higher hydrogen (H) content, and has a passivation effect on dangling bond in polysilicon. However, the SiNx layer in contact with the polysilicon active layer has a poor interface due to the stress. Hence, a SiO2 layer is often deposited plus a layer of SiNx layer to form the gate insulating layer.
The thicker the SiNx layer is, the better the capabilities are as barrier to mobile ions and passivation effect. However, the reliability of the TFT elements will decrease. This is because the gate will continually inject the carrier stream into the SiNx layer, which will destroy the SiNx layer, so that the quality of the SiNx layer is deteriorated, resulting in reduced reliability of the TFT element. Therefore, under normal circumstances, SiNx layer is not thick. In addition, during fabricating the gate in the etching process, the SiNx layer is often over-etched. If a protective layer is superimposed over the SiNx layer simply to protect the SiNx layer, the thickness of the gate insulating layer corresponding to storage capacitor area is increased, resulting in performance degradation in capacitive storage. The only solution is to increase the capacitance area and sacrifice the opening ratio to ensure the capacitance storage performance.