The inventive concept relates generally to electronic memory technologies. More particularly, the inventive concept relates to a volatile memory device having reconfigurable refresh timing.
A volatile memory device loses stored data in the absence of applied power. One potential cause of this data loss is charge leakage from storage elements. For example, in a typical dynamic random access memory (DRAM), each memory cell comprises an access switch and a storage capacitor. Charges may leak from the storage capacitor due to leakage current in the access switch; as an example, a metal oxide transistor (MOS) forming the access switch may experience leakage current through a PN junction. The loss of charges on the storage capacitor may change the stored data, which can produce errors or malfunctions during system operation.
To prevent data loss, DRAM devices perform periodic refresh operations on the stored data. A refresh operation of a DRAM cell typically involves detecting stored data from the cell and applying charges to the cell according to the detected data.
Refresh operations of a DRAM device can be performed in various alternative modes, such as auto refresh mode or a self refresh mode, for example. In the self refresh mode, the DRAM device typically performs refresh operations on a group of sequentially addressed memory cells by sequentially varying an internal address in response to a refresh instruction signal.
Each memory cell is typically refreshed periodically according to a predetermined refresh cycle time (tREF). For example, if a first refresh operation occurs at a time t=0, a second refresh operation may occur at a time t=tREF, a third refresh operation may occur at a time t=2*tREF, and so on.
In general, the refresh cycle time is determined by a data retention time, which can vary between different devices or memory cells. One source of this variation includes differences in process, voltage, and temperature (PVT) conditions of the different devices or memory cells. Another source of this variation includes heat applied during packaging or set assembling or other environmental factors, which is referred to as a variable retention time (VRT). In general, the refresh characteristics tend to deteriorate during packaging or set assembling, so a refresh cycle time margin in a test stage is typically set to a small value to provide a margin for change.
Due to subtleties of the above sources of variation, it may be difficult to predict with precision the data retention time of all memory cells in a DRAM device. Consequently, it may be difficult to set the refresh cycle time of a DRAM device in a way that avoids unnecessary refresh operations without losing stored data.
In view of the foregoing, there is a general need for improved techniques to address deterioration of refresh characteristics in volatile memory devices such as DRAMs. In particular, there is a need to address deterioration that may occur through various stages of device fabrication, such as a post package repair and a post set assembly repair.