This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
In modern manufacturing of integrated circuits, conventional cell architecture designs are typically generated with two-dimensional Electronic Design Automation (EDA) tools that are inefficient and cumbersome to employ. Some 2D design flows may directly adopt a 2D placement solution to determine the standard cell and inter-tier via locations, with limited results for three-dimensional (3D) optimizations. Some other 2D design flows propose block partitioning for 3D optimizations across multiple tiers. However, the inter-tier via locations are typically determined by the 2D placement solution from a single tier, which lacks co-optimization between multiple tiers.