The present invention relates to a semiconductor storage element, a semiconductor device and manufacturing methods therefor as well as a semiconductor device in which a semiconductor storage element and a semiconductor switching element are consolidated on an identical substrate and a manufacturing method therefor. The present invention also relates to portable electronic equipment and an IC card provided with the above-stated semiconductor device.
Conventionally, there has been a flash memory as a memory device being electrically writable and erasable. As shown in a sectional view of FIG. 19, the conventional flash memory has a floating gate 906 made of polysilicon and arranged on a semiconductor substrate 901 via a first oxide 904, a control gate 907 made of polysilicon and arranged on the floating gate 906 via a second oxide 905, and a pair of source/drain diffusion regions 902 and 903 arranged in the surface of the semiconductor substrate 901. This flash memory constitutes a field-effect transistor (hereinafter referred to as FET), where the control gate 907 operates similarly to the gate electrode of the FET. The first oxide 904, the floating gate 906 and the second oxide 905 are arranged between the control gate 907 and the semiconductor substrate 901. That is, the flash memory includes a memory film (i.e. the floating gate 906) having a charge storage function and arranged in a position corresponding to the gate insulator of the FET, so that the flash memory executes storage, read and erase operations by changing the threshold voltage of the FET according to the amount of charge accumulated in this memory film.
The conventional flash memory has a problem that the memory characteristics deteriorate due to so-called overerase (Masuoka Fujio, “Flash Memory Technology Handbook”, Science Forum Co., Ltd., Aug. 15, 1993, P 55-58). That is, the overerase is caused by excessive extraction of electrons or the injection of positive holes when the flash memory executes the erase operation by extracting the electrons accumulated in the floating gate 906 or injecting positive holes into the floating gate 906. Due to this overerase, the floating gate 906 is electrically positively charged, and the FET is turned on by the influence of the positive electric charge, disadvantageously causing a leakage current flowing between the source/drain diffusion regions. This leakage current is attributed to the fact that the control gate 907 corresponding to the gate electrode of the FET and the floating gate 906 that serves as the memory film are stacked and the FET is turned on and off only by the electric charge retained in the floating gate 906.
A memory cell array formed of the aforementioned flash memory cells has a problem that the current of a selected memory cell cannot be extracted during the read of the selected memory cell due to the leakage current generated from non-selected memory cells, causing a read error.