Semiconductor memories are binary data memories in which a plurality of memory cells are provided. The memory cells are addressable by means of wordlines and bitlines. The main memory comprises a matrix of many memory cells connected to address decoding means and sense amplifiers. Addressing a memory cell, i.e. the selection of a memory cell, is performed by activating wordlines which are connected to address decoding means. The data stored in the addressed memory cells are read out by input/output units having sense amplifiers for amplifying the read-out data signal. The input/output units are connected to a data bus by means of which data can be read out from the memory or written into the memory.
When a random access memory is produced, it can happen that some of the memory cells within the matrix are faulty. Accordingly, the produced memory chip is tested, and it is decided whether it can be repaired. For this purpose, there is normally provided an on-chip circuitry to provide testing of the memory chip. The built-in self-test (BIST) is essentially the implementation of logic built into the memory chip to do testing without the use of a tester for data pattern generation on comparison purposes.
FIG. 1 shows the architecture of a memory chip according to the state of the art. The memory chip comprises a main memory with a plurality of memory cells and a redundancy logic having a built-in self-test device. The memory chip is connected to an address bus, a control bus and a data bus. In a test mode, the addresses of the faulty memory cells are detected. The redundancy logic replaces the faulty memory cells within the main memory with memory cells in the form of redundant registers within the redundancy logic. The address applied to the address bus is compared with the addresses of the detected faulty memory cells, and when there is a match, the redundancy logic maps the faulty address to an address of a register cell within the redundancy logic to replace the faulty memory cell. When reading data from the memory chip, the redundancy logic controls a multiplexer connected to the data bus. When accessing data with an address of a faulty memory cell, the data is read from the register replacing the memory cell within the redundancy logic.
In the conventional memory chip as shown in FIG. 1 the fusebox connected to the redundancy logic contains a plurality of fuses. The fuses are laser fuses which are blown by laser light. Alternatively a read only memory (ROM) is used instead of the fusebox. This ROM is for instance a EPROM or EEPROM. For blowing the fuses in the fusebox or for loading the data values into the read only memory the external tester device calculates which fuses have to be blown or what values have to be loaded into the ROM.
To repair a faulty RAM-memory within the memory chip several interactions are needed between the external tester device and the conventional BIST device as shown in FIG. 1. In a failure analysis the external tester device detects the addresses of the faulty memory cells within the RAM memory cell array and calculates a repair solution for repairing the memory cell array on the memory chip. The external tester device computes the fuses which have to be blown or respectively the values to be loaded into the ROM memory. After the repair solution has been calculated the fuses in the fusebox are blown by the external tester device.
The interactions between the external tester device and the memory chip are performed by using huge communication protocols. Consequently blowing of the fuses or loading of the data values into the read only memory takes a long time since the data exchange between the external tester device and the memory chip is extensive.
When using laser fuses within fusebox for operation of the main memory a further disadvantage resides in that the laser fuses have to be blown by laser light. Accordingly to program the fuses it is necessary to have open access through the chip package to the laser fuses. In the testing process this leads to a complicated handling of the memory chips for reparation purposes.
FIG. 2 shows the architecture of a main memory within the memory chip according to the state of the art. In this example, the main memory is a 8k×16 wide memory having 16 input/output units and wordline address decoders (XDEC) for decoding the wordline address or X-address of the memory cells. The input/output units are connected to the memory cell matrix by means of vertical bitlines. The input/output units receive the bitline address or Y-address of the solected memory cell.
The main memory shown in FIG. 2 according to the state of the art is partitioned in two memory hales wherein the X-address decoders are placed in the center. With this architecture, the length of the wordlines is comparatively short so that the parasitic capacitance of the wordlines can be minimized.
Each input/output unit is connected to the 16 bitlines reading data from the addressed memory cell and for writing data into an addressed memory cell.
FIG. 3 shows the architecture of an input/output unit according to the state of the art. For reading out data, the input/output unit comprises multiplexers which are connected to the bitlines of the memory cell matrix. In the shown example, each memory cell is connected to a multiplexer via a couple or pair of bitlines BL, {overscore (BL)} to provide a differential signal to the input of the multiplexer. In the shown example, each multiplexer has N signal inputs. On the output side, each multiplexer is connected to a differential amplifier and an inverter for amplifying the read-out data signal and to supply the data to a data bus. The multiplexers are controlled by the applied Y-address.
In a conventional memory, there are provided either redundant registers, redundant bitlines and/or wordlines to repair a memory chip in case that faulty memory cells are detected when testing the memory chip.
If the conventional memory chip comprises redundant registers, the number of faulty addresses is limited by the number of redundant registers provided within the redundancy logic. If there are, for instance, 10 redundant registers, it is only possible to repair 10 faulty addresses. When an address is “faulty”, the address is stored in a redundant register. Since the number of faulty addresses detected by the main memory, it is not known before testing a considerable number of registers have to be provided within the redundancy logic to guarantee the repair of the chip even when a lot of memory cells are detected to be faulty.
In case that the memory chip comprises redundant bitlines and/or wordlines, the repair method is much more complex, because all errors have to be known in advance before the error pattern can be diagnosed and an optimal repair solution can be calculated. Storing detected memories with a conventional method implies a very large array.
Such an array needs a lot of space on the memory chip, thus increasing costs when producing the memory chip.
The test diagnose repair performed with an external tester device as shown in FIG. 1 has the main disadvantages that it takes a long time to load the fuses within the fusebox because a very extensive data exchange is necessary between the external tester device and the memory chip. The communication between the external tester device and the memory chip is performed by using predetermined data protocols thus increasing redundancy of data exchange between the tester device and the memory chip. By increasing the reparation time of the memory chip the production costs of the memory chips are also increased.
Accordingly it is the object of the present invention to provide a fuse blowing interface which allows to repair a memory chip within a minimum time span.