1. Field of the Invention
The invention relates to a method of fabricating a dynamic random access memory (DRAM), and more particularly to a method of fabricating a capacitor in a DRAM.
2. Description of the Related Art
Modern semiconductor fabrication technique in an ultra large scale integration (ULSI) highly increases the circuit density on a chip. The increase of circuit density causes the downsizing of devices and the increase of device packing density. Recently, enhanced resolution of photolithography technique, the development of anisotropic plasma etching and other improvements of semiconductor fabrication have all been advantageous to device downsizing. However, in order to develop towards a further higher circuit density, some breakthrough is required for semiconductor fabrication.
DRAM is a device broadly used in electronic industry for data storage due to the characteristic of increased circuit density in an integrated circuit (IC). The stored information or message is determined by the charges stored in an internal capacitor of a memory cell. The access of data is performed by operating the read/write circuit and the peripheral memory in a chip. A single DRAM memory cell comprises a field effect transistor (FET) and a capacitor as a bit for representing a binary data.
As the number of transistors in a DRAM greatly increases, the dimension of the transistors reduces. Thus, during storing charges, a acceptable signal-to-noise (S/N) ratio is difficult to maintain. By decreasing the charges in a capacitor to enhance the S/N ratio, the refresh cycles for storing charges is correspondingly increased.
Being restricted by the limited available surface area of a capacitor in a memory cell, to supply sufficient capacitance to the chip without increasing the occupied space on the substrate, a special and effective capacitor structure is needed to meet the requirement of semiconductor fabrication. As example, a trench capacitor, a cylinder capacitor, and a stack capacitor have been developed and used. However, due to the high complexity of fabrication, the trench capacitor is not as common as the cylinder capacitor and the stack capacitor. The disadvantages of these structures are the complex process and the high cost of fabrication.
In FIG. 3a to FIG. 3g, a conventional method of fabricating a cylinder capacitor in a DRAM is shown.
Referring to FIG. 3a, on a silicon substrate 300 having a metal-oxide-semiconductor (MOS) formed thereon, an oxide layer 301 and a silicon nitride layer 302 are formed in sequence. The silicon nitride layer 302 is used as an etch stop in the subsequent etching process.
In FIG. 3b, using photolithography and etching, the silicon nitride layer 302 and the oxide layer 301 are patterned to form an opening 309, so that the silicon substrate 300 is exposed within the opening 309, for example, a doped region in the MOS is exposed. A poly-silicon layer 303 is formed on silicon nitride layer 302 and fills the opening 309.
In FIG. 3c, the poly-silicon layer 303 is etched back until the surface of the poly-silicon layer and the surface of the silicon nitride layer 302 are at a same level.
In FIG. 3d, an oxide layer 304 is formed over the substrate 300. Using photolithography and etching, the oxide layer 304 is patterned to form an opening 310, so that the poly-silicon layer 303 within the opening 310 and a part of the surface of the silicon nitride layer 302 are exposed. A poly-silicon layer 305 is formed to cover the opening 310 and the oxide layer 304, and thus, the poly-silicon layer 303 and the poly-silicon layer 305 are electrically connected. An oxide layer 306 is formed on the poly-silicon 305.
In FIG. 3e, the oxide layer 306 is etched back with the poly-silicon layer 305 as an etch stop. The poly-silicon layer 305 is etched back with the oxide layer 304 as an etch stop.
In FIG. 3f, the remaining oxide layer 306 and the remaining oxide layer 304 are removed by wet etching with the silicon nitride layer 302 as an etch stop.
In FIG. 3g, an insulation layer 307, for example, an oxide/nitride/oxide (ONO) layer, is formed over the substrate 300. A poly-silicon layer 308 is formed on the insulation layer 307. The fabrication of a conventional cylinder capacitor in a DRAM is formed.
In the above method, two photolithography and etching processes are used, so that two photo-masks are required. Thus, the possibility of misalignment is increased, the process is more complex, and the cost of fabrication is high.