This invention relates to methods for manufacturing and fabricating low impedance metal gates on MESFETS and more particularly to a method for a fabricating a T-gate for an MESFET employing a double exposure, double develop process.
In GaAs MESFETS small gate resistance and short gate length are essential for high gain and low noise performance. The MESFET device is well known and employs a metal semiconductor barrier as a junction. A general approach taken in the prior art for obtaining both low resistance and small length is the adoption of a key-shaped cross section gate (T-gate) structure where the small foot or stem defines the length and the wide top provides a low resistance. The resulting large surface area is essential at operating frequencies above 10 GHZ because of microwave skin effects. T-shaped metal lines have been fabricated by the prior art through the use of a high sensitivity resist on a low sensitivity resist (HI/LO) double layer electronic beam (E-beam) resist system.
Many such techniques have been investigated in the prior art. As indicated by the prior art, the gate consists of a large trapezoidal cross member fused to a narrow stem and looks like and appears like the letter "T". As indicated above, the prior art was well aware of the advantages of such a T-gate and T-gate processing has been employed and described by a number of microwave groups over the past few years. For examples of such prior art, the following references are indicated.
See an article entitled "High Efficiency 35-GHz GaAs MESFETS" published in the IEEE Transaction on Electron Devices. Vol. ED-34 No. 6 June (1987) by G. C. Taylor, et al. This article describes the fabrication of Ti/Pt/Au gates in a shallow (80 nm) recess etched using gate photoresist as a mask into a 2.5 um long ledge channel. After gate metal deposition, the bottom Ti is chemically etched to a final gate length of 0.4 to 0.5 um. One disadvantage of this technique is that it cannot be used with commonly used Al/Ti gates without losing the top Ti layer. In addition the gate cannot be inspected easily after the Ti etch and ungated channel is guaranteed by the gate etch. Nevertheless the simplicity of the approach and the fact that a ledge is not always required may make the technique feasible if controlled undercut of the Ti layer can be achieved.
See also an article entitled "Electron Beam Fabrication of GaAs Low Noise MESFETs Using a New Trilayer Resist Technique" published in the IEEE Transaction on Electron Devices, Vol. ED-32 No. 6 June (1985) by P. C. Chao et al. This article describes a LO/HI/LO resist technique utilized to obtain MESFETs with an Ft greater than 100 GHz. The technique requires three resist coatings. A first coating employs a poly (methylmethacrylate) (PMMA). Then a copolymer of methylmethacrylate and methacrylic (MMA-MAA) is employed and finally a thin layer of PMMA is utilized. The total composite thickness is 1 um with a copolymer thickness of 0.5 um and no intermixing between PMMA and the copolymer.
The structures described are difficult to obtain given the involved resist chemistry. It is conceded in that paper that the bottom line width is difficult to control. In addition it would appear that even inspection of the patterns prior to recess etching or metalization would also be difficult because of the large aspect ratio between resist thickness and base opening. Thus it is felt that the technique described in that article will not result in an efficient production oriented technique.
See an article entitled "Submicron GaAs Microwave FET's With Low Parasitic Gate and Source Resistances" published in the IEEE Electron Device Letters, EDL-4 No. 2, February (1983) by S. G. Bandy et al. The technique described here is a straight forward trilayer composite of PMMA/200A Al/PMMA, utilizing only one 20 kV E-beam exposure. The top layer of PMMA is over developed, presumably without effecting the bottom layer, the Al barrier film is etched, and finally the bottom PMMA layer is developed to the required line width. A factor of 6 reduction in gate resistance was obtained leading to devices with a minimum NF of 1.0 db with 13 db of associated gain at 8 GHZ fabricated on n+-n MBE epi in a 0.5 um ledge channel. When utilizing this technique inspection would be difficult although base layer development should be straightforward and the technique should work with Ti/Al as well as Ti/Pt/Au gates. Major drawbacks of the technique is developing variations associated with the porous Al barrier, lack of dimensional control if the top resist chemistry is the same as the bottom, and potential alignment problems with the 200 A Al buried charged dissipation layer.
See a further article entitled "Submicron Lift Off Line With T-Shaped Cross Sectional Form, published in Electronics Letters, June 11, Volume 17, No. 12 (1981) by M. Matsumura et al. This article describes an E-beam, T-gate processing method in which a bi-layer resist composite is used. The top layer is high sensitivity PMIPK (Poly Methyl Isopropanol Ketone) and the bottom layer is a much lower sensitivity PMB. A proprietary developer was employed.
In reviewing the article one will ascertain that the technique described is extremely complicated depending critically on well established and reproduceable developing rates. This is one area which has been especially difficult to control in PMMA processing and would quite likely be more difficult to control with a composite resist layer using a single developer. In any event, the technique is not viable to be employed in modern day mass production techniques as they are extremely difficult to implement.
See an article entitled "Synchrotron Lithography for Sub-Half Micron T-Gates in GaAs FET" published in the Proceedings of Microcircuit Engineering (1986) by K. H. Mueller et al. This technique employed a trilayer PMMA composite consisting of three different molecular weights designed to yield a T-gate stencil after development and exposure to an X-ray dose of 2 to 3 Joules/cm.sup.2. The main problem associated with this technique involved resist processing, in this case optimized for X-ray rather than E-beam lithography. The technique does not appear to be as advanced as the other techniques described in the prior art.
See an article entitled "Fabrication of 0.5 um Plated T-Gates for MESFETs Using the Suss MJB-3 Aligner", Suss Seminar Series, Publication 101 (1987) by R. W. Baird. This paper describes a very straight forward technique in which a base resist layer is contact printed at 300 nm followed by a recess etching and a sputter deposition of a plating seed (Ti/Pt/Au/Ti). A thicker top resist is then patterned by contact printing to form the top of the T followed by a Ti-etch and gold plating. This technique also proves difficult in that it is dependent on fine line plating techniques and therefore it is incompatible with Al/Ti gates. It is also incompatible with deep recess etching because of the requirement for plating seed continuity.
See also an article entitled "A GaAs Metal-Semiconductor Field-Effect Transistor With a Mushroom Gate Fabricated by Mixed Exposure of Focussed Ion Beams" published in the Journal of Vac. Sci. Technology, B, Vol. 5 No. 1 January/February 1987 by H. Morimoto et al. on pages 211-214. This article shows a focused ion beam lithography used for fabrication of high resolution patterns. Resist materials with a high resolution such as PMMA which are highly sensitive to ions while showing an extremely low sensitivity to UV light, electron or X-ray are employed. The ion beams are advantageous for high resolution lithography with dimensions less than 0.3 um. These characteristics of the ion beams are suitable for the fabrication of a gate pattern for high performance GaAs microwave FETs. The process flow for the fabrication of such devices is shown in FIG. 1 of article. As one can understand, the above techniques are extremely complicated and are difficult to employ.
It is therefore an object of the present invention to provide a T-gate for an FET which includes a deep (0.45 um) recess which increases the height of the stem.
It is a further object of the present invention to provide a T-gate for very high frequency power FETs where both short gate lengths and large cross sectional areas are desired.
It is a further object of the present invention to provide a method for fabricating a T-gate FET which method employs a thin layer of PMMA for the base of the T-gate and an optical Novolak resist to give a re-entrant side profile performed on top of the T.
It is a further object of the present invention to provide a method for forming a T-gate for an FET which method eliminates many of the disadvantages as described in conjunction with the above-noted prior art.