1. Field of the Invention
The present invention relates to a device and a method for transposing a matrix of video signals, which may be applied to a video decoder for decoding a matrix of compressed video bitstream such as signals of an MPEG(Moving Picture Expert Group) format.
2. Discussion of the Related Art
As is well known, recently high definition television(HDTV) broadcasting systems have been developed, some of which are put into pilot operation in some of countries. In the pilot operation of the HDTV broadcasting systems, signals according to the HDTV broadcasting systems are transmitted, which are capable of being processed in an HDTV receiver (hereinafter called as HDTV). In the meantime, there are two classes of signals in the HDTV system of the ATSC (Advanced Television Systems Committee) of the U.S.A. One class of signal is an HD class signal for producing images of a high definition, and the other class of signal is an SD (Standard Definition) class signal(hereinafter called as SD signal) for producing images of a standard definition. The SD class signal has a data transmission rate lower than the HD class signal. The HD TV is adapted to process the two classes of video data, basically. Therefore, there can be four cases of signal transmission between broadcasting stations and HD TV""s; the first case is displaying a HD signal as an HD signal, the second case is displaying an HD signal as an SD signal, the third case is displaying an SD signal as HD class signal, and the fourth is displaying an SD signal as an SD signal. Though the first, third and fourth cases have no particular problems in processing the signals with regard to the system performances, the second case does. That is, the second case has problem in that the images appear broken. Therefore, if an HD signal is to be displayed as an SD class signal, it is necessary to degrade performance of a received HD signal to some extent. For example, an HD signal of 20 MHz MPEG format should be altered to an SD class signal of 6 MHz MPEG format. This degradation of the HD signal performance implies a drop in the resolution. In general, the HD signal performance is degraded by removing a portion of frequency band over a certain frequency from the HD signal. An HD signal of an 8xc3x978 matrix having a portion of frequency band over a certain frequency removed therefrom to suit to the SD class signal is thereby altered into an 8xc3x974 HD signal. This 8xc3x974 HD signal can be displayed as an SD class signal, with a resolution degraded compared to the 8xc3x978 HD signal, but without the problem of broken images. In the meantime, an 8xc3x978 matrix SD signal can be displayed on an HDTV as it is. Because of the aforementioned reason, the HD TV should be adapted to process the 8xc3x978 HD signal as well as the 8xc3x974 HD signal. A general HD TV will be explained with reference to FIGS. 1xcx9c3.
Referring to FIG. 1, upon receiving a compressed video bit stream from a broadcasting station, the general HD TV synchronizes a desired video bitstream in a tuner 10, of the video bitstream received through an antenna Ant, and demodulates in a demodulator 20. This video bitstream, being an MPEG signal, has a form of matrix. Then, the demodulated video bit stream is restored in a video decoder 30 and processed to a displayable condition in a VDP(Video Display Processor) 40. The signal from the VDP 40 is displayed through a displayer 50. In this instance, the VDP 40 processes the decoded signals appropriate to a performance of the displayer 50.
FIG. 2 illustrates a detail block diagram of the video decoder 30 shown in FIG. 1. Upon reception of a matrix of the demodulated video bit stream from the demodulator 20 in FIG. 1, a VLD(Variable Length Decoder) 21 therein decodes the demodulated video bit stream to provide DCT(Discrete Cosine Transform) coefficients and motion vectors. The DCT coefficients are scanned by an inverse scanner 22 and inverse quantized by the inverse quantizer 23. Then, an IDCT(Inverse Discrete Cosine Transformer) 25 makes an inverse discrete cosine transformation of the inverse quantized DCT coefficients to provide spatial pixel values. Here, before the inverse discrete cosine transformation in the IDCT 25, the inverse quantized DCT coefficients are transposed in a transposer 24 for easy inverse discrete cosine transformation. On the other hand, a motion compensator 27 uses the motion vectors from the VLD 21 in compensating a reference video frame stored in the frame memory in advance, and an adder 28 adds a signal from the motion compensator 27 and a signal from the IDCT 25, to provide an added value to the VDP 40 in FIG. 1.
Illustrated in FIG. 3 is an example of the transposer 24 for making alternative read/write of two memories 24a and 24b in transposing them.
Referring to FIG. 3, the transposer 24 is provided with two SRAM(Static Random Access Memory) 24a and 24b each of a 16 bitsxc3x9764 words size and two multiplexed flipflops 24d and 24e. Upon reception of an enable signal in a read/write controller 24c, the read/write controller 24c provides a read/write controlling signal and a selecting signal to the first SRAM 24a and the second SRAM 24b. . The first SRAM 24a and the second SRAM 24b are operative in opposite manner in response to the read/write controlling signal. That is, a first data is written on the first SRAM 24a at the first time, the second SRAM 24b is left at a disabled state in response to the selecting signal. Then, while the first SRAM 24a is read, the second a SRAM 24b is written of a second data. Thus, the first SRAM 24a and the second SRAM 24b are read and written alternatively. The alternative first, second data from the two SRAMs 24a and 24b are transposed by the multiplexed flipflops 24d and 24e. Besides, there are a transposing method disclosed in a U.S Pat. No. 4,769,790 by time delaying and a U.S. Pat. No. 5,418,487 using dual port memories. These two Patents have a disadvantages either in a size of hardware or in a complicated hardware. And, as has been explained, the background art transposer 24 shown in FIG. 2 transposes an mxc3x97m matrix signal(for example, m=8) using two memories of mxc3x97m words capacity each. Because of the use of two memories, such a background art transposer has disadvantages in that the inverse discrete cosine transformer and the video decoder 30 shown in FIG. 2 have increased areas and comparatively low operation speed of 100 M sample/sec.
Accordingly, the present invention is directed to device and method for transposing a matrix of video signals and a television receiver employing the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method and a device for transposing a matrix of video signals which can reduce a chip area of the inverse discrete cosine transformer and, further, an area of the video decoder.
Another object of the present invention is to provide a method and a device for transposing a matrix of video signals which is operable at fast speed.
Other object of the present invention is to provide a video decoder and a television receiver employing the same method and device.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a memory part for writing a matrix of video signals thereon, a write control circuit shift and writes rows of the video signals on the memory part by any one unit either of a row unit or a column unit. The video signals written on the memory are read from the memory by one unit different from the unit in the writing either of the row unit and the column unit by a read control circuit for transposing. Rows of video signals received at the next time are shifted, and written on portions of the memory part emptied in sequence due to the shift in the reading by one unit opposite to the unit in the reading either of the row unit and the column unit in sequence. The memory part may includes either one memory on which the matrix of video signals may be written or two memory of less capacity, resulting to a reduction of an occupied area of the memory part. Because rows of video signals received at the next time is shifted, and written on portions of the memory part emptied in sequence in the reading, a speed of the transposing becomes faster.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.