This invention relates to flash memory storage, and more particularly to a serial-bus controller integrated with a parallel flash memory.
Flash memory has gained wide acceptance for its non-volatile storage, which is ideal for portable devices that may lose power, since the data is not lost when stored in the flash memory. Flash memories are constructed from electrically-erasable programmable read-only memory (EEPROM) cells.
Rather than use a randomly-addressable scheme such as is common with dynamic-random-access memory (DRAM), many flash memories use a block-based addressing where a command and an address are sent over the data bus and then a block of data is read or written. Since the data bus is also used to send commands and addresses, fewer pins are needed on the flash-memory chip, reducing cost. Thus flash memory is often used as a mass-storage device rather than a randomly-addressable device.
Universal-Serial-Bus (USB) has become a popular standard interface for connecting peripherals to a host such as a personal computer (PC). USB-based flash-memory storage devices or “drives” have been developed to transport data from one host to another, replacing floppy disks. While large external flash drives may be used, smaller USB flash drives known as key-chain or key drives have been a rapidly growing market.
A USB flash-memory device can be constructed from a microcontroller, a flash-memory controller or interface, and one or more flash-memory chips. A serial interface on the microcontroller connects to the USB bus to the host, and data from the serial interface is transferred through the microcontroller to then flash controller and the written to the flash-memory chips.
The microcontroller usually contains an internal ROM with a control program that is read by the internal central processing unit (CPU) of the microcontroller when the microcontroller is booted or powered up. Once initialized with the control program, the CPU can control data transfers between the serial interface and the flash controller.
Sometimes the user may desire to connect to more than one USB flash-memory device. The user can install a USB hub, and then plug the USB flash-memory devices into the USB hub's downstream ports. USB hubs allow one USB port on a host to fan out to multiple end USB devices or endpoints. A basic USB hub has a repeater that repeats data from the host to all down-stream devices, while more intelligent hubs based on the USB 2.0 standard can buffer data to different down-stream ports.
FIG. 1 shows a prior-art USB hub that connects to multiple flash-memory USB endpoint devices. Host 10 includes USB host controller 12 that generates transactions to USB devices over USB bus 18 using the USB protocol. USB hub 20 is connected to a cable containing USB bus 18. USB hub 20 fans out USB bus 18 to several downstream USB devices that connect over additional USB bus segments.
Three USB flash-memory systems 14, 15, 16 are connected to USB hub 20 by USB bus segments. USB flash-memory system 14 can be accessed by USB host controller 12 through USB hub 20. Since USB hub 20 passes all host transfers through to downstream devices, USB flash-memory system 15 is visible to host 10 as a second flash drive, while USB flash-memory system 16 is visible to the host as a third flash drive.
Users may be able to purchase a single USB flash-memory drive with a larger storage capacity and directly connect it to USB bus 18, without the need for USB hub 20. Some board manufacturers may integrate USB hub 20 together with USB flash-memory systems 14, 15, 16 on a single USB flash card or box. However, this can be expensive when USB flash-memory systems 14, 15, 16 are flash-memory chips, since each chip may have many pins. For example, a flash-memory chip with an 8-bit or 16-bit data bus may have 48 total pins. This can increase the size of the USB flash device. Power consumption is higher due to the large number of data lines in the parallel buses to each flash-memory chip.
The transfer bandwidth of each flash-memory chip is also somewhat limited. For example, a 50 nanosecond access time for an 8-bit flash chip has a bandwidth of 160 Mbps. While this is sufficient for the USB 1.1 standard that supports a data rate of 12 Mbps, the newer USB 2.0 standard supports a data rate of 480 Mbps. Thus a wider data bus, requiring more flash-memory chips, is needed to support the faster USB 2.0 speeds. However, the additional flash-memory chips and wider buses increases board size, manufacturing cost, and product size.
What is desired is to integrate a microcontroller with a flash-memory array. It is desired to have a wide internal bus from the microcontroller to the flash-memory array to improve the data bandwidth while having few external pins to reduce cost and required board space.
It is further desired to eliminate the internal ROM on the microcontroller. Instead of booting from the internal ROM, it is desired to use a control program stored in the flash-memory array. However, it is also desired to use a block-addressed rather than a randomly-addressable array for the flash storage.