Real space transfer (RST) devices are known to the art. See, for instances, "Heterojunction Band Discontinuities: Physics and Device Applications", F. Capasso et al., editors, Elsevier 1987, especially pages 513-537, incorporated herein by reference.
Known RST devices are a transistor variously called charge-injection transistor (CHNIT) or negative resistance field effect transistor (NERFET), and the hot-electron erasable programmable random access memory (HE.sup.2 PRAM). See, for instances, U.S. Pat. No. 4,903,092, also incorporated herein by reference.
Briefly, the transistor is a three-terminal device based on real-space transfer of hot electrons from a first to a second conducting region. The two conducting regions are separated by a barrier region and are contacted independently, with one of the conducting regions (referred to as the "channel") having two surface contacts (frequently referred to as "source" and "drain"). Application of a source-to-drain bias V.sub.sd leads to a heating of channel electrons and consequent charge injection into the second conducting layer. The channel thus acts as a hot electron emitter and the second conducting layer as a collector. This terminology will be used herein. The above discussed transistor shows a strong negative differential resistance in the source-drain characteristic (the NERFET action) and an efficient control of the injection current (I.sub.c) by the source-drain voltage (CHINT action).
HE.sup.2 PRAM comprises, in addition to the above described elements, a "deep" drain that contacts both the emitter and the collector.
A logic circuit that comprises prior art RST devices is also known. For instance, on page 520 of the above referenced monograph is disclosed a logic circuit comprising two NERFETs.
Those skilled in the art are well aware of the desirability of having available devices that have novel operating characteristics, since such devices may make possible attainment of previously unachievable results, or may result in more economical attainment of some desired results. For instance, prior art implementation of basic logic functions (e.g., AND, NOR) generally requires a multiplicity of active elements (typically transistors). It would clearly be desirable, both from an economic and from a performance point of view, to be able to implement such logic functions with logic elements that comprise only a single active device, and thus reducing the device count and the number of gate delays. As a second example, it would be highly desirable to have available a device that can carry out a logic function which in the prior art required two or more separate logic elements. As a third example, it would be very desirable to have available a device that can carry out either a first or a second logic functions. This application discloses a novel device that has these and other advantageous attributes. It also discloses articles that utilize the novel device.