The present invention relates to memory cell layout of CMOS-type SRAM (Complementary Metal Oxide Semiconductor Static Random Access Memory) among semiconductor memory devices.
The SRAM memory cell that comprises six transistors and is made by a typical semiconductor CMOS process is widely used for system LSIs and so on.
The prior art layout pattern of the CMOS-type SRAM memory cell will be described below with reference to FIG. 8.
The prior art SRAM memory cell comprises nMOS drive transistors TN1 and TN2, nMOS access transistors TN3 and TN4, pMOS load transistors TP1 and TP2, polysilicon wires PL1, PL2, PL3 and PL4, wiring layers AL1 and AL2, and contacts CN1, CN2, CL1 and CL2.
The nMOS drive transistor TN1 and the nMOS access transistor TN3 are formed on an n-type diffusion region DN1 and the nMOS drive transistor TN2 and the nMOS access transistor TN4 are formed on an n-type diffusion region DN2. The pMOS load transistor TP1 is formed on a p-type diffusion region DP1 and the pMOS load transistor TP2 is formed on a p-type diffusion region DP2.
Gates of the nMOS drive transistor TN1 and the pMOS load transistor TP1 are connected to each other with the polysilicon wire PL1 and drains of them are connected to each other with the wiring layer AL1 via contact, thereby forming a first inverter (CMOS structure). Gates of the nMOS drive transistor TN2 and the pMOS load transistor TP2 are connected to each other with the polysilicon wire PL2 and drains of them are connected to each other with the wiring layer AL2 via contact, thereby forming a second inverter (CMOS structure). The wiring layer AL1 as an output node of the first inverter is connected to PL2 as an input node of the second inverter, and the wiring layer AL2 as an output node of the second inverter is connected to PL1 as an input node of the first inverter. Thereby a latch circuit for holding data is formed.
A drain of the nMOS access transistor TN3 is connected to the wiring layer AL1 as the output node of the first inverter and source thereof is connected to a bit line (not shown) extending longitudinally via the contact CN1. A drain of the nMOS access transistor TN4 is connected to the wiring layer AL2 as the output node of the second inverter and source thereof is connected to another bit line (not shown) extending longitudinally via the contact CN2. Gates of TN3 and TN4 are connected to a word line (not shown) extending transversally via the contacts CL1 and CL2, respectively.
With such memory cell layout, long lateral distance allows a wide interval between two bit lines so that coupling capacitance between bit lines, which may cause a problem in micro process, can be reduced. Therefore, such memory cell layout is advantageous to speeding-up.
Next, relationship between capability ratio of drive transistors and access transistors and stability of data holding in the SRAM memory cell will be explained with reference to FIGS. 9, 10 and 11.
FIG. 9 shows a memory cell circuit diagram for evaluating stability of data holding. This circuit assumes the situation that the access transistors TN3 and TN4 turns on when the word line is in VDD level for a reading operation, and the bit line is raised to precharge level.
FIG. 10 shows input/output characteristics of two inverter circuits (INV1, INV2) in the latch circuit.
Ain-Aout and Bin-Bout represent characteristics of INV1 and INV2, respectively and it is plotted so as to be Ain=Bout and Bin=Aout. Cross points P1 and P2 in this drawing are stable points and each point corresponds to memory data 0 or 1. In the plot, as area surrounded by two curved lines becomes larger, stability of data holding at P1 and P2 improves. Here, when driving capability of the access transistors TN3 and TN4 becomes greater than that of nMOS transistors (drive transistors) TN1 and TN2 in the inverter circuits, input/output characteristics of the inverter circuits change as shown in FIG. 11. The reason is that the access transistors transmit VDD level of the bit line to the latch nodes more easily, so that area surrounded by two curved lines becomes smaller. When noise voltage is applied into the memory cell having such characteristics, cross points are reduced to be only P2xe2x80x2 and therefore the memory cell can hold only either data. That is, in the case where data other than P2xe2x80x2 (i.e. P1xe2x80x2) is held, the data is destroyed. Thus, maintaining a constant ratio of access transistors to drive transistors in driving capability is important for holding memory cell data stably. Generally, driving capability of access transistors is set to be 50 to 70% of that of drive transistors.
In the prior art SRAM memory cell, channel width of drive transistors is set to be larger than that of access transistors, thereby generating a difference between them in driving capability.
In the prior art SRAM memory cell in which channel width of the drive transistors is set to be larger than that of the access transistors, thereby generating a difference between them in driving capability, the diffusion regions necessarily include some bent parts and end parts. For example, in FIG. 8, the bent parts that produce round-offs as shown by dashed lines DL3 and DL4 are generated by difference between the nMOS drive transistors TN1 and TN2 and the corresponding nMOS access transistors TN3 and TN4 in channel width.
With such layout, at the bent parts of the diffusion regions, finish pattern is rounded off as shown by dashed lines DL1, DL2, DL3 and DL4 in the figure. As a result, a problem arises that transistor width of the nMOS transistors TN1, TN2, TN3 and TN4 becomes larger than required. Moreover, at the end parts of the diffusion regions, finish pattern is retreated as shown by dashed-lines DL5 and DL6. As a result, there arises a problem of reduction in overlap margin of the p-type diffusion region with respect to the contact as well as variation in channel width of the pMOS transistors TP1 and TP2.
Furthermore, system mounted on a semiconductor chip has increasingly become large scale. In connection with this, there is a tendency that the block of SRAM with a large scale in bit capacity is mounted on the chip. In order to meet these requests on the system side, it is desired to further reduce the size of SRAM memory cell. Although it is effective to use a MOS transistor with smaller channel width for the purpose of reducing cell size, such small-sized pattern is prone to undergo great variations in characteristics due to processing fluctuations. Therefore, reduction in cell size makes stable design by sufficient operational margin difficult. On the other hand, with recent micro process, it is more difficult to obtain desirable processed form and round-off or retreat of pattern tend to take place. Moreover, there often causes the phenomenon that even the same pattern form changes in finished form due to peripheral pattern form.
To suppress such changes of processed form, it has already been implemented to correct mask pattern in consideration of bend up and bend down of layout pattern concerned and in consideration of the peripheral layout pattern in recent micro process. Such process, however, is sensitive to apparatus used in semiconductor diffusion process and processing conditions. Further, correction value must be modified each time processing conditions in diffusion process are changed, adding a burdensome operation.
The present invention is made to solve the above-mentioned problems. With the memory cell layout of the semiconductor memory device according to the present invention, it is possible to lay out diffusion regions in linear shapes without any bent part by generating a difference between access transistors and drive transistors in driving capability without changing their channel width. As a result, processed form of diffusion areas of the SRAM memory cell is hard to change, thereby suppressing variations in characteristics of transistors so that transistors with narrow channel width can be used. An object of the present invention is to provide a highly integrated semiconductor memory device by use of such transistors with narrow channel width
A semiconductor memory device according to one aspect of the present invention has a SRAM memory cell comprising: a first inverter including a first nMOS transistor and a first pMOS transistor; a second inverter including a second nMOS transistor and a second pMOS transistor; a third nMOS transistor; and a fourth nMOS transistor, wherein an input node of the first inverter is connected to an output node of the second inverter; and an input node of the second inverter is connected to an output node of the first inverter; either of drain and source of the third nMOS transistor is connected to the output node of the first inverter; the other of drain and source thereof is connected to a first bit line; and gate thereof is connected to a word line; either of drain and source of the fourth nMOS transistor is connected to the output node of the second inverter; the other of drain and source thereof is connected to a second bit line; and gate thereof is connected to the word line; a first diffusion region forming the first nMOS transistor and the third nMOS transistor and a second diffusion region forming the second nMOS transistor and the fourth nMOS transistor, respectively, are arranged in linear shapes without having any bent part, and current driving capability of the first and second nMOS transistors is higher than that of the third and fourth nMOS transistors.
A semiconductor memory device according to another aspect of the present invention is an above-mentioned semiconductor memory device characterized in that gate length of the third and fourth nMOS transistors is longer than that of the first and second nMOS transistors.
A semiconductor memory device according to another aspect of the present invention is an above-mentioned semiconductor memory device characterized in that threshold voltage characteristics of the third and fourth nMOS transistors are higher than those of the first and second nMOS transistors.
A semiconductor memory device according to another aspect of the present invention is an above-mentioned semiconductor memory device characterized in that a gate oxide film of the third and fourth nMOS transistors are thicker than that of the first and second nMOS transistors.
A semiconductor memory device according to another aspect of the present invention is an above-mentioned semiconductor memory device characterized in that driving voltage of the word line is lower than power supply voltage supplied to the first and second inverters.
A semiconductor memory device according to another aspect of the present invention is an above-mentioned semiconductor memory device characterized in that a third diffusion region forming the first pMOS transistor and a fourth diffusion region forming the second pMOS transistor are arranged in linear shapes without having any bent part and located in parallel to the first and second diffusion regions.
A semiconductor memory device according to another aspect of the present invention is an above-mentioned semiconductor memory device further comprising: a third pMOS transistor formed adjacent to drain of the first pMOS transistor on the third diffusion region; and a fourth pMOS transistor formed adjacent to drain of the second pMOS transistor on the fourth diffusion region, wherein gates of the first nMOS transistor, the first pMOS transistor and the fourth pMOS transistor are connected in succession via a first polysillicon wire; and gates of the second nMOS transistor, the second pMOS transistor and the third pMOS transistor are connected in succession via a second polysillicon wire; and absolute value of threshold voltage of the third and fourth pMOS transistors is higher than power supply voltage supplied to the first and second inverters.
A semiconductor memory device according to another aspect of the present invention is an above-mentioned semiconductor memory device characterized in that n-type diffusion regions are provided on the opposite side of the diffusion region of the third pMOS transistor to the first pMOS transistor and on the opposite side of the diffusion region of the fourth pMOS transistor to the second pMOS transistor to fix potential of N-well region forming pMOS transistors.
A semiconductor memory device according to another aspect of the present invention is an above-mentioned semiconductor memory device characterized in that, in a memory cell array in which the SRAM memory cells are arranged in a grid pattern, a substrate contact region for fixing well potential is provided at regular intervals in the extending direction of the first and second diffusion regions; a diffusion region forming the substrate contact region is arranged in a linear shape without any bent part on the extension of the first diffusion region and the second diffusion region of the memory cell; and a fifth nMOS transistor is provided at the boundary of the memory cell and the substrate contact region wherein gate potential thereof is fixed so as not to become ON state.
A semiconductor memory device according to another aspect of the present invention is an above-mentioned semiconductor memory device characterized in that, in a memory cell array in which the SRAM memory cells are arranged in a grid pattern, a substrate contact region for fixing well potential is provided at regular intervals in the extending direction of the third and fourth diffusion regions;, a diffusion region forming the substrate contact region is arranged in a linear shape without any bent part on the extension of the third diffusion region and the fourth diffusion region of the memory cell; and a fifth pMOS transistor is provided at the boundary of the memory cell and the substrate contact region wherein gate potential thereof is fixed so as not to become ON state.
A semiconductor memory device according to another aspect of the present invention is an above-mentioned semiconductor memory device characterized in that the first pMOS transistor is formed on the third diffusion region; the second pMOS transistor is formed on the fourth diffusion region; and the first, second, third and fourth diffusion regions are arranged at equally spaced intervals in the longitudinal direction of connect line of transistor gate.
A semiconductor memory device according to another aspect of the present invention is an above-mentioned semiconductor memory device characterized in that the first pMOS transistor is formed on the third diffusion region; the second pMOS transistor is formed on the fourth diffusion region; and the first, second, third and fourth diffusion regions are arranged so as to have same width measured in the longitudinal direction of connect line of transistor gate.
As a means of generating a difference in transistors"" capability without changing channel width, channel length of the access transistors is set to be longer than that of the drive transistors. This enables memory cell data to be held stably. In the prior art difference in capability has been generated from difference in channel width. Therefore, even if minimum width of diffusion region, which is possible in processing, can be applied to the access transistors, the drive transistors cannot be laid out at minimum width. According to the present invention, however, minimum width of diffusion region can also be applied to the drive transistors. In typical transistors, channel width is longer than channel length, and therefore reduction in channel width in the present invention probably can reduce cell size.
However, in the prior art memory cell layout as shown in FIG. 8, because of its long sideways structure, longer channel length, which increases cell height, weakens the effect of reducing area by reduction in channel width of the drive transistor. Accordingly, in the present invention, as another means of generating a difference in transistors"" capability, threshold voltage of the access transistor is set to be greater than that of the drive transistor. Further, as other means, gate oxide film of the access transistor is set to be thicker than that of the drive transistor. By use of these means, the access transistor and the drive transistor have different capability while having the same channel length and width so that the effect of reducing area can be obtained. In the case that the above-mentioned means for changing characteristics of the access transistor are employed, it is necessary to add a supplementary process, suffering a slight increase in process costs. Therefore, as another means according to the present invention, power supply voltage supplied to a word line driving circuit for driving the gate of the access transistor is set to be lower than that supplied to a latch circuit in the memory cell. As a result, it is possible to generate a capability difference between the access transistor and the drive transistor having the same size and characteristics, thereby holding process costs down.
As for the p-type diffusion region, removing end parts that exist in the prior art layout is employed. The p-type diffusion regions are arranged in linear shapes, and for the separation of pMOS load transistor devices between vertically adjoining cells, a pMOS separating transistor having an absolute value of threshold voltage greater than power supply voltage and being in OFF state at any time irrespective of gate potential is formed. This suppress changes of processed form in channel width of the load transistor due to retreat of pattern that occurs at the end part in the prior art, and also allows a sufficient overlap of the diffusion region with respect to the contact in the drain of load transistor. Looking from the aspect of the n-type diffusion region, the p-type diffusion region always lies next to the n-type diffusion region as its peripheral layout form. In the prior art layout, as the p-type diffusion region does not exist partly next to the n-type diffusion region, the processed form of the n-type diffusion region changes a part and the change must be corrected on the mask data. According to the present invention, the processed form of the n-type diffusion region can be improved without any correction.
Furthermore, fixing potential of N well forming the pMOS transistors by applying n-type diffusion on the opposite side of a pMOS separating transistor to load transistor is employed. Therefore, vacant region in the memory cell can be used effectively as substrate contact region. The substrate contact region for fixing potential of P well may be separately formed outside of the memory cell. Nevertheless, as potential of N well can be definitely fixed, latch-up resistance is improved. Moreover, a potential-fixed region of P well that formed separately can be set at larger intervals, thereby enabling area of the memory cell array to be suppressed.
Considering the layout of the whole memory cell array, it is necessary to provide the potential-fixed region of P well at regular intervals in the vertical direction of aligning memory cells. With the prior art layout, diffusion regions of memory cells above and under the potential-fixed region are necessarily separated. According to the present invention, by providing transistors whose gates are fixed in OFF state above and under the potential-fixed region both in n-type diffusion region and p-type diffusion region, the above-mentioned potential-fixed region of N well can be arranged in a linear shape in contiguous to the diffusion region of the memory cell. In this way, over the whole memory cell array, diffusion regions can be laid out in linear shapes without any bent part and partial separation, so that change in characteristics of transistors above and under the potential-fixed region can be suppressed.
Furthermore, in the present invention, placing each diffusion region at the same interval is employed. As mentioned above, in recent micro process, finished processed form changes due to peripheral layout form. In the case of plural placement intervals, it becomes difficult to shape plural diffusion regions into desired interval and width. Maintaining a constant placement interval facilitates keeping forms of these diffusion regions constant. Similarly, placing each diffusion region at the same width is employed. It also facilitates keeping width and forms of these diffusion regions constant.
The novel features of the invention are set forth with particularity in the appended claims. The invention as to both structure and content, and other objects and features thereof will best be understood from the detailed description when considered in connection with the accompanying drawings.