In dynamic random access memory (DRAM) integrated circuit devices, a DRAM cell array is typically arranged in rows and columns such that a particular DRAM cell is addressed by specifying its row and column within the array. A wordline connects a row of cells to a set of bitline sense amplifiers that detect the data in the cells. In a read operation, a subset of the data in the bitline sense amplifiers is then chosen, or “column-selected” for output. DRAM cells are “dynamic” in the sense that the stored data, typically in the form of charged and discharged storage capacitors, will dissipate after a relatively short period of time. Thus, in order to retain the information, the contents of the DRAM cells must be refreshed. The charged or discharged state of the storage capacitor must be reapplied to an individual memory cell in a repetitive manner. The maximum amount of time allowable between refreshing operations is determined by the charge storage capabilities of the storage capacitors that make up the DRAM cell array. DRAM manufacturers typically specify a refresh time for which data is retained in the DRAM cells.
A refresh operation is similar to a read operation, but no data is output. The sensing of the data in the cells by the bitline sense amplifiers is followed by a restoring operation that results in the data being rewritten to the cells. The data is, thus, “refreshed”. The refresh operation is performed by enabling a wordline according to a row address, and enabling a bitline sense amplifier. In addition, the refresh operation may be carried out by operating the bitline sense amplifier without receiving an external refresh address. In this case, a refresh address counter, which is integrated in a DRAM device chip, generates a row address subsequent to receiving an external start address.
It is well known that data stored in memory cells of a DRAM is retained therein by refresh operations. A self-refresh operation is performed automatically in a “standby” mode to retain the data written in the memory cells of the DRAM. In known self-refresh operations, automatic burst refresh operations can be performed at the beginning of self-refresh and at the end of self-refresh operations for shortening a refresh regulation time and for securing a stable refresh of the memory cells. U.S. Pat. No. 5,583,818 granted to You et al. on Dec. 10, 1996 discloses a semiconductor memory device having an automatic burst refresh operation in a self-refresh operation.
A simplified description of prior art self-refresh operation is now discussed with reference to FIG. 1 that shows a self-refresh operation with automatic burst refresh function found in conventional DRAM devices. Referring to FIG. 1, in response to a command signal 111, a self-refresh mode detector 113 provides a self-refresh starting signal 115 at an entry into the self-refresh mode. A burst refresh mode controller 117 provides a burst refresh control signal 119 during a “burst self-refresh” period, in response to the self-refresh starting signal 115 and a clock signal 121 fed from a clock generator 123. A self-refresh mode controller 125 provides a self-refresh control signal 127, in response to the burst refresh control signal 119 and the self-refresh starting signal 115. The clock generator 123 provides the clock signal 121 and a self-refresh row signal 129, in response to the self-refresh control signal 127 and the burst refresh control signal 119. At an exit from the self-refresh mode, in response to the command signal 111, the self-refresh mode detector 113 ceases the self-refresh starting signal 115. Therefore, the self-refresh mode controller 125 ceases the generation of the self-refresh control signal 127. A period during the self-refresh control signal 127 being generated is a “self-refresh” period. Also, the burst refresh mode controller 117 provides the burst refresh control signal 119 during another “burst self-refresh” period. In response to the burst self-refresh control signal 119 and the self-refresh control signal 127, the clock generator 123 provides the self-refresh row signal 129 during the burst refresh period, the self-refresh period and the other burst self-refresh period. The self-refresh row signal 129 is provided to an internal row address counter which in turn provides a refresh row address signal to a row address decoder to refresh cells of the wordlines of sequentially selected rows.
The prior art DRAM device shown in FIG. 1 performs the self-refresh operation based on a one-cell-per-bit manner and the refresh of the DRAM cells has to be performed at a relatively high frequency. Therefore, the one-cell-per-bit self-refresh may still consume power during the self-refresh operation period. It is, thus, desirable to reduce power consumption in the self-refresh operation mode in the DRAM device.