One or more embodiments relate to the technology of fabricating a semiconductor device, and more particularly, to a semiconductor device with reduced contact resistance between a substrate and a plug, and a method of fabricating the semiconductor device.
As the degree of integration of semiconductor devices increases, a space between gate patterns becomes narrow and thus a contact processing margin reduces. Therefore, in order to secure a desired contact processing margin, a landing plug contact (LPC) structure is commonly used.
A landing plug contact process is accomplished by filling a space between gate patterns where, previously, a bit line contact and a storage contact are formed with a conductive layer to secure an overlay margin in subsequent contact processes.
FIG. 1 illustrates a cross-sectional view of a conventional semiconductor device.
Referring to FIG. 1, a gate 17 is formed by sequentially stacking a gate insulation layer 14, a gate electrode 15 and a gate hard mask layer 16 over a substrate 11 including a device isolation region 12 and an active region 13, and then etching the gate insulation layer 14, the gate electrode 15 and the gate hard mask layer 16 at once by using a gate mask. Then, after forming gate spacers 18 on sidewalls of the gate 17, a source and drain region (not shown) is formed in the active region 13 between two neighboring gates 17.
After depositing an interlayer insulation layer (not shown) covering the resultant structure, the deposited interlayer insulation layer undergoes a photolithography process and an etching process using a contact mask as an etch barrier. As a result, a contact hole is formed. The contact hole is then filled with a conductive layer, thereby forming a landing plug 19.
However, during the formation of the gate 17, since etch rates of the gate insulation layer 14, the gate electrode 15 and the gate hard mask layer 16 with respect to an etching gas are different from each other, the resultant gate 17 is formed having a sidewall with a positive slope. That is, a bottom line width (bottom CD) W2 of the gate 17 is greater than its top CD W1 (W1<W2). Therefore, a space between two neighboring gates 17 is reduced and thus a contact area between the landing plug 19 and the substrate 11 is also reduced. The reduction of the contact area between the landing plug 19 and the substrate 11 becomes a more serious issue as the gate spacers 18 are formed. Byproduces or residues R generated during formation of the gate 17 may further reduce the contact area between the landing plug 19 and the substrate 11.
As described above, when the contact area between the landing plug 19 and the substrate 11 is reduced, the contact resistance between the landing plug 19 and the substrate 11 is increased, thus, the operational speed of the semiconductor device deteriorates.