1. Field of the Invention
The present invention relates to a memory module which carries a plurality of memory elements on the surface of a laminated substrate having electrodes arranged on one side edge of the substrate.
2. Description of the Prior Art
A conventional memory module will be explained with reference to FIGS. 1 and 2. In FIG. 1, numeral 2 indicates a laminated substrate. A plurality of memory elements 3, for example, static random access memories (SRAMs) are mounted on both sides of the laminated substrate 2. Further, supply electrodes Vcc and grounding electrodes Gnd for the memory elements 3 are linearly arranged along the one side edge of the laminated substrate 2 together with electrodes "In" for signal terminals (address terminal, control terminal and data terminal). These electrodes are generally referenced as numeral 4. Such a memory module 1 is inserted into a socket provided on a circuit substrate of an electronic instrument and is thereby connected to the other electronic circuit elements making up the electronic instrument.
When the removable memory module 1 is connected to its socket, electrodes for high impedance signal lines are not generally degraded in the electrical characteristics due to the configuration described above. However, electrodes for supply lines and ground lines exhibiting how impedances within the memory module 1 are often degraded in electrical characteristics, particularly, the AC characteristics arisen from the inductances and a non-linearity of the V-I characteristic accompanied by the contact with the socket.
More specifically, in a circuit as shown in FIG. 2, there possibly exist non-linear elements D and resistances R and inductances L caused by contamination and the like at an electrode 4 portion where the memory module 1 is brought in contact with the socket. The non-linear element D and the resistance R are not particularly active when carrying a constant current exceeding the specified magnitude. However, in the case where the supply current changes from, e.g., a non-current carrying state to a peak current carrying state, the memory elements 3 may not be supplied with adequate current. Consequently, there is a potential difference between the supply electrodes Vcc and the ground electrodes Gnd outside the memory module 1 and those inside the memory module 1.
The judgment as to which logic state exists should be executed on the basis of the ground level outside the memory module 1. However, this decision is actually executed on the supply and ground levels within the memory module 1. Therefore, in the case that the ground level within the memory module 1 is higher than that outside the memory module 1, a high signal input may be erroneously judged as a low signal input. Conversely, in the case that the ground level within the memory module 1 is lower, a low signal input may be erroneously judged as a high signal input.
For this reason, in the removable memory module, high speed memory elements have been rarely used. Also, in a memory module having a broad data bus range, when a number of bits are changed with the same timing, noise is often induced for the same reason, thus causing data error.
A conventional memory module 1 (for example, SBX1705 type SRAM, Sony Corp.) mounting four memory elements 3 (1M bit high speed SRAM, for example, CXK 581020, Sony Corp.) on one side surface and one memory element 3 (the same as the above) on the other side surface of the laminated substrate 2 are connected to a socket provided on an electronic instrument and assembled. A schmoo plot of an address access time T.sub.AA, which gives such a noise characteristic, is shown in FIG. 3. In this figure, the ordinate shows a supply voltage V (v), and the abscissa shows an address access time T.sub.AA (ns), and also the low level input voltage V.sub.IL input in the memory elements 3 is set as 0.60 v, 0.65 v or 0.70 v. The other measurement conditions are as follows: temperature is room temperature 25.degree. C.; high level input voltage V.sub.IH input in the memory module 3 is 2.2 v; and the threshold voltage V.sub.TH is 1.5 v.
In this schmoo plot, the left region represents a fail region essentially pertained to the memory module 1. Another fail region caused by noise is in the center and is represented by three kinds of hatchings.
Also, the output enable access (hereinafter referred to as OE access) of the same memory module 1 is examined for the noise characteristic, which results in the schmoo plot as shown in FIG. 4. In this figure, the ordinate shows a supply voltage V (v), and the abscissa shows an OE access time T.sub.OE (ns), and also the low level input voltage V.sub.IL input in the memory elements 3 is set as 0.55 v, 0.60 v or 0.70 v. Even in this schmoo plot, over the whole region of T.sub.OE, there exists a fail region caused by noise at the supply voltage V exceeding 5.0 v.