The latest one chip MCU frequently has a RAM monitor function for debugging and tuning an internal program of the MCU in a state implemented on a chip (hereinafter referred to as MCU 100 with a built-in RAM monitor or simply referred to as MCU 100). FIG. 1 shows the configuration of a conventional MCU 100.
The RAM monitor function can be realized when the MCU 100 receives an external clock and external data and outputs data by way of an external interface terminal group 102.
The conventional MCU 100 comprises an external interface terminal group 102, a data transmit/receive section 104, a direct memory access control circuit (hereinafter referred to as DMA controller) 110, and also comprises a CPU 120, a ROM 130, a RAM 140, a peripheral module 1 (150) and a peripheral module 2 (160) respectively connected with one another by way of an internal bus formed of a data bus (DBUS) 106 and an address bus (ABUS) 108.
The DMA controller 110 comprises a GO flag set F/F 111, an AND gate 115, an address register (AReg) 112, a data write register (WReg) 113, a data read register (RReg) 114, and a timing controller 116.
The GO flag set F/F 111 is set upon completion of reception of an address/data from the transmit/receive section 104 and reset upon completion of a DMA transfer operation. An output signal from the GO flag set F/F 111 is inputted to the AND gate 115 together with a bus state recognition signal 101 and generates a DMA start signal 124. The bus state recognition signal 101 is a signal which takes an insignificant value (e.g. “0”) when the CPU 120 occupies the bus and the DMA is placed in a bus use prohibition state, and which takes a significant value (e.g. “1”) when the CPU 120 releases the bus and the DMA is placed in a bus use permission state.
Further, the timing controller 116 executes write/read relative to the registers, the RAM and the like by the DMA operation at a given timing at the time when a GO flag is set by the GO flag set F/F 111 and the bus state recognition signal 101 takes the significant value and the operation of the timing controller 116 is reserved until a starting condition is prepared.
The RAM monitor function is a function to read or rewrite contents of the RAM 140 and registers of the peripheral modules 1 and 2 inside the MCU 100 during the normal operation of the MCU 100, namely, during the operation of the MCU 100 by an application program (hereinafter referred to as AP) which is written in the ROM 130.
In the case of reading data, in FIG. 1, when an address of a RAM or addresses of registers, namely, the RAM 140, the peripheral module 1 (150) and the peripheral module 2 (160) which are provided in the MCU 100 and subjected to debugging are inputted from an external data input/output terminal (hereinafter referred to simply as external data i/o terminal) in synchronization with an external clock from the external interface terminal group 102, necessary data is set in the DMA controller 110 by way of the data transmit/receive section 104. The DMA controller 110 reads data in the RAM or registers serving as objects of set addresses by way of the internal bus, and outputs the read data to the outside by way of the data transmit/receive section 104 and the external interface terminal group 102.
In the case of writing data, when an address of a RAM or addresses of registers, namely, the RAM 140, the peripheral module 1 (150) and the peripheral module 2 (160) which are provided in the MCU 100 and subjected to debugging and data to be written are inputted from the external data i/o terminal in synchronization with the external clock from the external interface terminal group 102, necessary data is set in the DMA controller 110 by way of the data transmit/receive section 104. The DMA controller 110 rewrites data stored in the RAM or registers serving as objects of set addresses by way of the internal bus, and outputs a signal indicating the completion of execution of writing to the outside by way of the data transmit/receive section 104 and the external interface terminal group 102.
However, in the conventional method, since a point (a state of program counter (PC 121) inside the CPU 120) where the data in the RAM and registers inside the MCU 100 are read or data is written on the RAM and registers is a time upon completion of setting the DMA controller 110 after setting data from the external interface terminal group 102, such a point can not be set from the outside, causing a problem of lack of flexibility of debugging and another problem of low accuracy of debugging.
Under the circumstances, an on-chip debugging method of a MCU which is improved in flexibility and accuracy of debugging has been desired.