1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having an output circuit for outputting a balanced signal.
2. Description of the Related Art
An output level of an output circuit for transmitting a signal from an integrated circuit to another integrated circuit is previously defined according to a standard. General examples include PECL (Pseudo-Emitter Coupled Logic), and LADS (Low Voltage Differential Signaling), and recently, PCI-express (Peripheral Component Interconnect-), XAUI (10 Gigabit Attachment Unit Interface), Infini Band, and Serial-ATA. FIG. 4 shows specification of typical interface levels. As apparent from FIG. 4, these interface levels are not compatible with each other. For example, comparing the specification of the PECL interface level with that of the LVDS interface level in FIG. 4, the output level (VOH, VOL) of PECL is a voltage lowered from a power supply voltage by a certain value, while the output level (VOH, VOL) of LVDS is a voltage which is independent of variation in the power supply voltage.
Accordingly, the output circuit is generally configured according to a distinct circuit format suitable for the interface level of each standard. Each of these interfaces has a characteristic which cannot be achieved by other interfaces such as low power consumption. Thus, to use different interfaces for different purposes, there are many system devices having different interface levels with the similar function. As a result, transmission and reception between different interface levels is required. Such examples include an electrical input/output interface of an optical transmitter module.
Generally, the PECL or LVDS interface has become the mainstream of the electrical input/output interface of an optical transmitter module and is widely used in ASSP (Application Specific Standard Product) in many ways. In order to convert a signal into the interface level between PECL and LVDS as DC-coupled interfaces, the level using an external termination resistance is generally used. Hereinafter, an example is shown.
FIG. 1 shows a circuit configuration of a typical example of a level converting method. In FIG. 1, an output of an output circuit 40 in the LVDS interface is converted into the PECL interface level and outputted to a receiver 50. The LVDS interface output circuit 40 has N channel transistors 41 and 42 as a differential pair, a current source 43, load resistances 46 and 47 having a resistance value RL and a level controller 48. A differential signal (INA, INB) is supplied to gates of the N channel transistors 41 and 42 of the differential pair and a signal of LVDS level as shown in FIG. 4 is output from the output terminals OUTA and OUTB.
The output of the output circuit 40 is converted into the PECL interface level by a level converting circuit having resistances 51 to 53, and 55 to 57, and supplied to the receiver 50. The resistance 51 having a resistance value R1, the resistance 52 having a resistance value R2 and the resistance 53 having a resistance value R3 are serially connected between a power supply voltage VDD2 and a ground GND. The output terminal OUTB is connected to a connection node of the resistance 52 and the resistance 53. A signal of the PECL level is outputted from a connection node ROUTB of the resistance 51 and the resistance 52. Symmetrically, the resistance 55 having the resistance value R1, the resistance 56 having the resistance value R2 and the resistance 57 having the resistance value R3 are serially connected between the power supply voltage VDD2 and the ground GND. The output terminal OUTA is connected to a connection node of the resistance 56 and the resistance 57. A signal of the PECL level is outputted from a connection node ROUTA of the resistance 55 and the resistance 56.
Given that the “H” level output voltage of the output nodes ROUTA and ROUTB is VOH, the “L” level output voltage of the output nodes ROUTA and ROUTB is VOL and amplitude, that is, differential output voltage of the output signal is VOD, each of the voltages can be obtained according to the following equations (1-1) to (1-3). With the power supply voltage VDD, VDD1=VDD2=VDD.VOH=VDD×(R2+R3)/(R1+R2+R3)+RL×I1×R1/{2×(R1+R2)}  (1-1)VOL=VDD×(R2+R3)/(R1+R2+R3)−RL×I1×R1/{2×(R1+R2)}  (1-2)VOD=RL×I1×R1/(R1+R2)  (1-3)
By properly selecting the resistances 51 to 53, 55 to 57, the level can be converted to correspond to the PECL interface to some extent. However, as understood from FIG. 4, the signal of the LVDS interface is a signal having a common voltage of 1.2 V and a fixed voltage independently from the power supply voltage. On the contrary, the signal of the PECL interface is a signal having a relative voltage which varies in level in connection with the power supply voltage. In the resistance-dividing level converting circuit in FIG. 1, as represented by Equations (1-1) and (1-2), the output voltages VOH and VOL vary according to a resistance division ratio of the power supply voltage VDD. Thus, the output voltages VOH and VOL satisfy the amplitude standard (VOD) of the PECL interface, but cannot satisfy the standard of the output level (VOH, VOL) unless the resistance values R1, R2 and R3 are changed depending on the power supply voltage VDD.
FIG. 2 shows an example of a circuit for converting the PECL interface into the LVDS interface. An output circuit 60 of the PECL interface has transistors 61 and 62 as a differential pair, a current source 63, output transistors 65 and 66 and load resistances 67 and 68. A differential signal (INA, INB) is supplied to bases of transistors 61 and 62 and the signal of the PECL level in FIG. 4 is output from the output terminals OUTA and OUTB.
The output of the output circuit 60 is converted into the output of the LVDS level by a level converting circuit having resistances 71, 72, 74 and 75 and the converted output is supplied to a receiver 70. The resistance 71 having a resistance value R1 and the resistance 72 having a resistance value R2 are serially connected between the output terminal OUTA and the ground GND. The signal of the LVDS level is outputted from a connection node ROUTA of the resistance 71 and the resistance 72. Symmetrically, the resistance 74 having the resistance value R1 and the resistance 75 having the resistance value R2 are serially connected between the output terminal OUTB and the ground GND. The signal of the LVDS level is outputted from a connection node ROUTB of the resistance 74 and the resistance 75.
Given that a common voltage of balanced signals outputted from the output nodes ROUTA and ROUTB is VCM and an amplitude, that is, differential output voltage of the output signal is VOD, each of the voltages can be obtained according to the following equations (2-1) and (2-2):VCM=(VCC1−RL×I1/2−VF)×R2/(R1+R2)  (2-1)VOD=RL×I1×R2/(R1+R2)  (2-2)
Here, VF is a base-emitter voltage of the transistors 65 and 66. In this example, a conversion reverse to the level conversion described referring to FIG. 1 is performed. By properly selecting the resistance values R1 and R2 according to equation (2-2), LVDS amplitude standard (VOD) can be satisfied. However, as represented by the equation (2-1), in accordance with change in the power supply voltage VCC1, the output common voltage VCM varies depending on the resistance division ratio. Thus, the level converting circuit cannot satisfy the standard of the output common voltage VCM unless the resistance values R1 and R2 changes in accordance with the change in the power supply voltage VCC1.
Some interfaces do not use any external termination resistance. For example, as shown in FIG. 3, a typical example is a PCI-express interface. An output circuit 80 of the PCI-express interface has N channel transistors 81 and 82 as a differential pair, a current source 83 and load resistances 86, 87 and 88. A differential signal (INA, INB) is supplied to gates of the N channel transistors 81 and 82 and a signal of the PCI-express interface level is output from a connection node (OUTA, OUTB) of drains of the N channel transistors 81 and 82 and the load resistances 86 and 87, respectively. Outputs of the output circuit 80 are terminated by the termination resistance 91 having a resistance value RE and supplied to a receiver 90.
The PCI-express interface standard defines only output amplitude (VOD). When the output circuit 80 is used for the receiver 90 of the PECL interface, the resistance 88 having a resistance value RD may be adjusted to correspond to the “H” level output voltage VOH and the “L” level output voltage VOL of the PECL interface. The output levels VOH and VOL of the output terminals OUTA and OUTB and the amplitude VOD can be obtained according to the following equations (3-1) to (3-3):VOH=VDD1−{RL×RL/(2×RL+RE)+RD}×I1  (3-1)VOL=VDD1−{RL×(RL+RE)/(2×RL+RE)+RD}×I1  (3-2)VOD=I1×RL×RE/(2×RL+RE)  (3-3)
The equation (3-3) has a solution which satisfies the amplitude standard (VOD) of the PECL interface and the LVDS interface independently from the power supply voltage. As represented by the equation (3-1) and the equation (3-2), the output levels VOH and VOL of the output terminals OUTA and OUTB are determined based on the resistances 86 to 88 of the output circuit 80 and the terminal resistance 91 (resistance value RE) of the receiver 90. When the resistances 86 to 88 of the output circuit 80 are manufactured in the semiconductor integrated circuit together with the transistors and the like, the resistance values of the resistances have relatively a large manufacturing variation. Generally, it has been said that the resistance value of the resistance in the semiconductor integrated circuit has manufacturing variation of about −20% to +20%. Accordingly, when there is a mismatch between the above-mentioned resistance value and the resistance value of the termination resistance 91 on the receiving side, standards of the PECL interface, output levels VOH and VOL of the LVDS interface and the common voltage VCM cannot be satisfied. For example, to satisfy the standard of the output levels VOH and VOL of the PECL interface, the manufacturing variation of the resistance value needs to fall between −10% and +10%. Thus, it is difficult that the output circuit using the PCI-express interface satisfies the standard of the output levels VOH and VOL of the PECL or LVDS interface, or the standard of the common voltage VCM.
As described above, a load resistance (resistance value RL) in the output circuit and a current source (current value I1) have conflicting characteristics in variables (variation). For example, when the resistance value RL of the load resistance increases by 1.2 times due to the manufacturing variation, the current value I1 of the current source decreases by 1/1.2 times conversely. Accordingly, when the differential output terminals (OUTA and OUTB) are in the opened state, that is, nothing is connected to the output terminals, amplitude generated by the load resistance and the current source is kept constant in both the above-mentioned case.
However, the output level standard of the PECL interface is linked to the power supply voltage and the output level standard of the LVDS interface is fixed with respect to the ground voltage, which have conflicting characteristics. When the level of the output of such an output circuit is converted by a level shift circuit having an external resistance inserted between the current source and the ground, the output level is determined with respect to the power supply voltage depending on the resistance division ratio. For this reason, the standard cannot be satisfied unless the resistance value is adjusted for each interface and each power supply voltage according to use environment.
When a resistance built in the semiconductor integrated circuit is used as the load resistance of the output circuit, the resistance value greatly varies due to manufacturing variation. The output level of the output circuit is determined depending on a deviation ratio of the load resistance and a terminating resistance on the receiving side. For this reason, when the load resistance varies due to manufacturing variation and does not match the value of the terminating resistance on the receiving side, the standard of the interface cannot be satisfied. Especially in the PECL interface having a narrow allowable range of the output level, it is difficult to satisfy the standard.
FIG. 5 summarizes compatibility of level conversion in the above-mentioned typical conventional output circuit. In FIG. 5, a circle represents availability including realization through level shift by the external resistance or the like or switching of current flow.
Japanese Laid Open Patent Publication (JP-P2003-152522A) discloses a circuit for switching between PECL and LVDS, as a method which does not use the above-mentioned level conversion. An output circuit disclosed in Japanese Laid Open Patent Publication (JP-P2003-152522A) has a first output block including a first output port and a second output block including a second output port. The first and second output blocks are configured match a first transmission mode according to a first external control signal and bring about a first output characteristic in the first and second output ports. The first and second output blocks are configured match a second transmission mode according to a second external control signal and bring about a second output characteristic in the first and second output ports. The first transmission mode is a positive ECL (PECL) standard and the second transmission mode is a low-voltage differential signal transmission (LVDS) standard. Each of the first and second output blocks includes a switchable current source for feeding a current selected from a plurality of predetermined currents in the respective port according to the selected external control signal.