A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices, such as memory cells, that are as small as possible. A typical memory cell, which generally is formed from a field effect transistor (FET), includes a source and a drain formed in an active region of a semiconductor substrate by implanting N-type or P-type impurities in the semiconductor substrate. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. It is noted that memory cells can be formed in bulk format (for example, the active region being formed in a silicon substrate) or in a semiconductor-on-insulator (SOI) format (for example, in a silicon film that is disposed on an insulating layer that is, in turn, disposed on a silicon substrate).
Although the fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate for the formation of relatively large circuit systems in a relatively small die area, this downscaling can result in a number of performance degrading effects. In FET devices with a channel having a relatively short length, the FET can experience a number of undesirable electrical characteristics referred to as short channel effect (SCE). SCE generally occur when the gate does not have adequate control over the channel region, and can include threshold voltage (Vt) roll-off, off current (Ioff) roll-up and drain induced barrier lowering (DIBL). As the physical dimensions decrease, SCE can become more severe. SCE is the result of intrinsic properties of the crystalline materials used in the FET devices. Namely, the band gap and built-in potential at the source/body and drain/body junctions are non-scalable with the reduction of physical device dimensions, such as a reduction in channel length.
Another problem due to downscaling of transistors is charge loss in the oxide-nitride-oxide (ONO) layer. Charge loss is due in part to ONO damage during an erase cycle. During the erase cycle, the relatively high voltage (Vpp) applied across the oxide causes tunneling of electrons from the charge trapping nitride layer to the drain region. At the same time, the high voltage could cause holes from the drain to be injected into the oxide. These holes can degrade the performance of the oxide by creating a leakage path in the oxide between the drain and the nitride layer.
Since the oxide is the barrier for electrons traveling to and from the charge trapping layer, the charging and discharging current of a memory cell depends on the voltage applied across the oxide layer, I=C(dv/dt). Therefore, the voltage applied across the oxide has a direct effect on electron tunneling and is the main cause of undesirable hole injection into the oxide during an erase operation.
Therefore, there exists a need in the art for semiconductor devices, such as memory cells, that have reduced SCE and for fabrication techniques to make those semiconductor devices. Furthermore, there is a need in the art for semiconductor devices that have reduced ONO damage during erase operations of the device.