The following disclosure relates generally to integrated circuit (IC) devices, and to methods and apparatus for the design and fabrication of IC devices.
As technology progresses and IC devices include smaller dimensions and increased feature density. As technology nodes shrink, challenges are raised for example, mismatch of device performance becomes more critical. However, for relatively larger devices typically required in system-on-a-chip (SOC), analog, digital signal processing (DSP) and radio frequency (RF) applications, it may be difficult to provide adequate matching of large devices in an IC. These device mismatch issues may arise from the replacement or gate-last methodology employed to provide metal gate technology. The gate-last methodology typically requires additional chemical mechanical processing (CMP) steps. These CMP processes can create differences in gate heights due to loading effects. These loading effects are often exacerbated by the use of large devices (e.g., in concert with smaller features). For example, CMP dishing can result which may result in metal work-function shifts and mismatch degradation of the IC.
Thus, what is needed is an improved manner of circuit design, fabrication and implementation for gate last processes of ICs including differently sized devices.