1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having a memory cell array in which memory cells each comprising a variable resistance element storing information by the change of an electric resistance are arranged in a row direction and a column direction, and more particularly, to a technique for preventing and suppressing the deterioration of stored data due to the reading operation of the memory cell array.
2. Description of the Related Art
Recently, there has been proposed a variable resistance type of memory element (referred to as the variable resistance element hereinafter) having a two-terminal structure in which a metal oxide is sandwiched by conductors serving as electrodes, and capable of changing its electric resistance reversibly by applying a voltage pulse. Various kinds of variable resistance elements are proposed and disclosed by combining oxide materials and electrode materials (or example, refer to document 1: Japanese Laid-Open Patent Publication No. 2004-087069, document 2: Liu, S. Q. et al., “Electric-pulse-induced reversible Resistance change effect in magnetoresistive films”, Applied Physics Letter, Vol. 76, 2749, in 2000, document 3: Seo, S. et al., “Reproducible Resistance Switching in polycrystalline NiO films”, Applied Physics Letters, Vol. 85, 5655, in 2004, document 4: Sim, H et al., “Resistance-switching characteristics of polycrystalline Nb2O5 for nonvolatile memory application”, IEEE Electron Device letters, Vol. 26, 292, in 2005, document 5: Sawa, A. et al., “Hysteretic current-voltage characteristics and resistance switching at rectifying Ti/Pr0.7Ca0.3MnO3 interface”, Applied Physics Letters, Vol. 85, 4073, in 2004, and document 6: Fujii, T. et al., “Hysteretic current-voltage characteristics and resistance switching at an epitaxial oxide Schottky junction SrRuO3/SrTi0.99Nb0.01O3”, Applied Physics Letters, Vol. 86, 12107, in 2005), and each provides distinctive electric characteristics and varies in operation mechanism. Every variable resistance element uses a reversible resistance changing operation (referred to as the “switching operation” occasionally hereinafter) and can be used as a new nonvolatile semiconductor memory device by relating information to a resistance value and reading the resistance value or a current corresponding the resistance value. Here, the information includes binary digital data, a multilevel digital data, analog data and the like, and the high resistance state and the low resistance state are stored as the binary digital data “1” and “0”, the multilevel digital data can be stored using a middle resistance value between the high resistance state and the low resistance state, or the analog data may be stored.
There can be constituted a nonvolatile semiconductor memory device by forming a memory cell array in which memory cells comprising the variable resistance element and storing information by the change of the electric resistance of the variable resistance element are arranged in a row direction and column direction in a matrix state, and providing a circuit for controlling programming, erasing and reading operation of data for each memory cell of the memory cell array in the vicinity of the memory cell array.
The constitution of the memory cell comprising the variable resistance element includes a case where each memory cell comprises a series circuit consisting of the variable resistance element and a transistor as a cell-access element (1T/1R-type memory cell), a case where each memory cell comprises a series circuit consisting of the variable resistance element and a diode as a cell-access element (1D/1R-type memory cell), a case where each memory cell comprises a variable resistance element only (1R-type memory cell) and the like. The 1T/1R-type memory cell and its memory cell array, for example are disclosed in the document 1 by the applicant of this application (refer to FIG. 1, for example). The 1D/1R-type memory cell, for example is disclosed in Japanese Laid-Open Patent Publication No. 2004-260162 by the applicant of this application (refer to FIG. 1, for example). The 1R-type memory cell, for example is disclosed in Japanese Laid-Open Patent Publication No. 2005-32401 (refer to FIG. 4, for example).
When data is read from the memory cell comprising the variable resistance element, a bias voltage is applied to the variable resistance element to flow a reading current and the resistance value of the variable resistance element is determined by the amount of the current, so that the data is read. Therefore, regardless of the constitution of the memory cell, a predetermined bias voltage is applied to the variable resistance element in the reading operation. When a phenomenon in which the resistance value of the variable resistance element is changed a little by the bias voltage applied at the time of this reading operation (referred to as the “reading disturbance” occasionally hereinafter) is repeated, recorded information could be lost in the worst case. Therefore, it is necessary to reduce the degree and frequency of the reading disturbance as much as possible.
As described above, although there are various kinds of nonvolatile variable resistance element capable of changing the electric resistance reversibly by applying the voltage pulse, the behavior of the reading disturbance in the variable resistance element is not clear.
The inventors have found that in the case where the variable resistance element showing the rectifying characteristics disclosed in the document 5 (Sawa, A. et al.) or the document 6 (Fujii, T. et al.) is used, when a reading voltage whose absolute value is not more than a programming voltage is applied to the variable resistance element continuously, the resistance value of the variable resistance element is changed and the resistance value is considerably changed depending on the polarity of the reading voltage. In addition, the variable resistance element showing the rectifying characteristics denotes that the variable resistance element itself has the rectifying characteristics and does not mean that when the memory cell comprises a series circuit consisting of the variable resistance element and a diode as a cell-access element, the memory cell has the rectifying characteristics.
FIG. 1 shows current-voltage characteristics in a high resistance state and a low resistance state of the variable resistance element disclosed in the document 5 (Sawa, A. et al.) and comprising three layers Ti/Pr0.7Ca0.3MnO3 (PCMO)/SrRuO3 (SRO) manufactured by a similar method to that disclosed in the document 5 (Sawa, A. et al.). An upper electrode is Ti and an applied voltage in FIG. 1 is the potential of the upper electrode based on a lower electrode. Referring to FIG. 1, since a negative bias current when a negative voltage is applied (at the time of negative bias) is larger than a positive bias current when a positive voltage is applied (at the time of positive bias), forward bias is provided for the rectifying characteristics at the time of negative bias while reverse bias is provided for the rectifying characteristics at the time of positive bias. In addition, when the potential of the lower electrode based on the upper electrode is defined as the applied voltage, the above relation is reversed. Furthermore, the forward bias is defined by an applied voltage polarity in which a larger current flows to the variable resistance element.
In addition, according to the current-voltage characteristics shown in FIG. 1, when the current-voltage characteristics in the high resistance state is compared with that in the low resistance state, a current difference is largely provided in both forward bias and reverse bias, so that the high resistance state and the low resistance state can be determined in the reading operation in both forward bias and reverse bias.
However, the inventors of the present invention has found that the degree of the reading disturbance is considerably different between the reading operation in the forward bias (forward reading) and the reading operation in the reverse bias (reverse reading). FIG. 2 shows graphs in which the change in resistance value is plotted with a reading voltage applying time (reading voltage pulse applying number of times) when the forward reading and reverse reading are performed for variable resistance elements in the low resistance state and in the high resistance state. The change in resistance value is shown relatively assuming that the resistance value just after the variable resistance element becomes the low resistance state or high resistance state is set to 1, which denotes that the characteristics becomes undesirable as the resistance value (relative value) becomes far from 1. It can be seen from FIG. 2 that the resistance value change is larger when the reverse reading is performed in the low resistance state than the other case. In addition, since the resistance value in the above reading operation tends to increase, when the same reading operation is continued, the resistance state is changed from the low resistance state to the high resistance state, so that recorded information is lost.
Thus, it is clear from the above experimental result that the reading disturbance phenomenon is such that the data stored in the memory cell, that is, the resistance value is changed with the voltage applying time (number of times for applying a pulse) in the reading operation. Especially, the resistance value of the variable resistance element is considerably changed when the reading operation is performed by applying the reading voltage to the variable resistance element in the low resistance state in the reverse bias, so that when the same reading operation to the same memory cell is repeated, stored data could be completely lost and could not read in the worse case.
Furthermore, since in the case of the memory cell array comprising the 1R-type memory cell, the reading voltage is also applied to the selected memory cell that is not to be read but shares the word line or bit line with the memory cell to be read, the above reading disturbance phenomenon appears more notably, so that it is highly necessary to prevent the reading disturbance phenomenon as compared with the other memory cell types.