Scaling of the gate dielectric is a challenge in improving performance of advanced field effect transistors. In a field effect transistor employing a silicon oxide based gate dielectric, the leakage current through the gate dielectric increases exponentially with the decrease in the thickness of the gate dielectric. Such devices typically become too leaky to provide high performance at or below the thickness of 1.1 nm for the silicon oxide gate dielectric.
High-k gate dielectric provides a way of scaling down the thickness of the gate dielectric without an excessive increase in the gate leakage current. However, high-k gate dielectric materials are prone to a change in the effective oxide thickness (EOT) because high-k gate dielectric materials react with oxygen that diffuses through the gate electrode or gate spacers. Regrowth of a silicon oxide interfacial layer between a silicon substrate and the high-k gate dielectric during high-temperature processing steps is a major obstacle to successful effective oxide thickness scaling. Particularly, typical stacks of a high-k gate dielectric and a metal gate is known to be susceptible to a high temperature anneal in an oxygen ambient. Such a high temperature anneal in oxygen ambient results in regrowth of the silicon oxide interfacial layer and produces instability of the threshold voltage of field effect transistors.