The present invention relates to a metallization technique of a semiconductor device, more specifically to a semiconductor device having a wiring or plug of a suitable structure for high integration and a method for fabrication of the semiconductor device.
As LSIs increase their scales, further micronization of the devices is sought. To realize semiconductor integrated circuits having gates, wirings and contact holes of more micronized dimensions, photolithography resolutions have been improved conventionally by making exposure wavelengths shorter.
While the minimum resolution dimensions are thus made smaller, device structures which permit alignment margins between lithography steps to be smaller have been studied, and an attempt has been made to reduce device dimensions without reducing dimensions of patterns to be formed therein. Such device structures are exemplified by self-aligned contact (herein after called SAC), borderless contact (herein after called BLC), and so forth.
The conventional SAC will be explained in comparison with a structure which does not use SAC.
In the structure as shown in FIG. 30A in which two gate electrodes 40 are formed on a semiconductor substrate 10, and an inter-layer insulation film 20 is also formed. In opening a contact hole 22 between the two gate electrodes 40 down to the semiconductor substrate 10, it is necessary to position the gate electrodes 40, considering beforehand the alignment precision for opening the contact hole 22.
That is, an interval a between the contact hole 22 and the gate electrodes 40 must be secured to be at least above the alignment precision so that when a conducting film is buried into the contact hole 22, the conducting film and the gate electrodes 40 are not short-circuited (FIG. 30B). Thus, the interval between the gate electrodes 40 is dependent on the contact hole 22, which makes further micronization impossible.
In SAC as shown in FIG. 30C, gate electrodes 40 are covered with an inter-layer insulating film 20 and an etching selective insulating film 38. This keeps the insulating film 38 from being etched when the inter-layer insulating film 20 is etched, and when a conducting film is buried in a contact hole 22, no short-circuit takes place between the conducting film and the gate electrodes.
Accordingly, when a misalignment takes place in a lithography step for forming the contact hole 22, the opening of the semiconductor substrate 10 is determined only by the gate electrodes 40 and the insulating film 38, which enables the gate electrodes 40 and the contact hole 22 to be arranged without considering alignment as shown in FIG. 30D. This makes micronization of devices possible.
Examples of SAC are disclosed in Japanese Patent Laid-Open Publication No. 292323/1986, Japanese Patent Laid-Open Publication No. 106929/1992 and '94 Symp. VLSI Tech., Tech. Dig., pp. 99-100.
Next, the conventional BLC will be explained in comparison with a structure which does not use BLC.
In the structure as shown in FIG. 31A in which a device isolation film 12 is formed on a semiconductor substrate 10, and an inter-layer insulation film 20 is formed, in opening a contact hole 22 near the device isolation film 12, the contact hole 22 and the device isolation film 12 must be spaced from each other so that the contact hole 22 is not positioned on the device isolation film 12 even when misalignment takes place.
That is, when the contact hole 22 is positioned on the device isolation film, the device isolation film 12 is adversely etched in opening the contact hole 22, and when a conducting film 24 is buried in the contact hole 22, a junction short circuit takes place between the conducting film 24 and the semiconductor substrate 10 (FIG. 31B).
In contrast to this, in the BLC as shown in FIG. 31C, an inter-layer insulation film 20 is formed of insulation films 16, 18 having etching selectivity different from each other. By forming the insulation film 16 in contact with the device isolation film 12 of a material having sufficient etching selectivity with respect to the device isolation film 12, the device isolation film 12 is not etched when a contact hole 22 is opened to expose the surface of the semiconductor substrate 10. A junction short circuit between the conducting film buried in the contact hole 22 and the semiconductor substrate 10 can be prevented.
Thus, in the BLC, even when the device isolation film 12 and the contact hole are overlapped, a junction short circuit can be prevented, and it is not necessary to consider an allowance for alignment between the device isolation film 12 and the contact hole 22. The contact hole 22 can be positioned as exemplified in FIG. 31D. This makes device micronization possible.
Semiconductor devices having the above-described conventional BLC, however, have the following problems.
In etching the insulation film 16, it is preferred that wet etching is used to allow a good selectivity between the insulation film 16 and the device isolation film 12, but because wet etching is isotropic and adversely etches the insulation film 15 below the isolation film 18, a cavity is adversely formed. (FIG. 32A). The thus, formed cavity 30 cannot be covered by conventional sputtering and remains even after the conducting film 24 is deposited (FIG. 32B). When a plug 26 is formed in the next step of forming a contact, made by burying tungsten (W), then WF.sub.6, which is a source gas for tungsten, intrudes through the cavity 30 to cause substrate erosion called a worm hole. Junction spiking adversely occurs within a source/drain diffused layer 14 (FIG. 32C).
In addition, when using Al (aluminum) deposited by CVD as wiring material, in place of the above-described W plug, the Al and the semiconductor substrate directly contact each other in the cavity 30, and the Al and the semiconductor substrate react with each other by means of heat treatments in later steps, with a result that junction spiking takes place in the source/drain diffused layer 14 (FIG. 33A).
In addition, the above is true for a case in which Cu is used as a wiring material. Cu especially forms a deep energy level in the forbidden band when it is diffused in the semiconductor substrate which result much degrades the characteristics of the transistors. In addition, Cu is apt to diffuse in the silicon oxide film, and if the Cu reaches the gate oxide film 34, the Cu may add to leak current between the gate electrode 40 and the semiconductor substrate 10 (FIG. 33B).
In addition, in a semiconductor device shown in FIG. 34, which includes a contact plug 206 buried in an inter-layer insulation film 202 on a semiconductor substrate 200, it is often a case that when the BLC structure is used in opening a via-hole for connection to a wiring layer 210, an insulation film 220 is etched immediately onto the inter-layer insulation film 202 due to misalignment in opening the via-hole, etc., and a contact plug 208 is exposed in a cavity 224 formed when etching the etching stopper film 216, with a result that a contact plug 230 short-circuits with the contact plug 208.
In addition, when an etching stopper film 112 is removed without forming a cavity 124 using an anisotropic reactive ion etching, it is difficult to secure selectivity with respect to a ground film.
That is, in the structure of FIG. 35A, when the etching stopper film 112 in a wiring groove 118 is etched under conditions which secure a sufficient selectivity with respect to an inter-layer insulation film 104, a sufficient selectivity with respect to a contact plug 110, and the contact plug 110 is sometimes etched (FIG. 35B).
Opposite to this, when the etching stopper film 112 is etched under conditions which secure a sufficient etching ration with respect to the contact plug 110, a sufficient selectivity with respect to the inter-layer insulation film 104, and the inter-layer insulation film 104 is sometimes etched (FIG. 35C).
Thus, in etching the etching stopper film 112, it is difficult to concurrently secure etching selectivity with respect to both the contact plug 110 and the inter-layer insulation film 104. Contact characteristics are degraded, which affects reliability of the semiconductor device.
In addition, when the BLC structure is used in forming a contact plug 144 on a wiring layer 122 buried in an inter-layer insulation film 114, the wiring layer 122 is exposed in a cavity 138 formed by retreating an etching stopper film 130. When a plug 142 is buried, a raw material gas of the plug 142 reacts with the wiring layer 122 to form a high-resistance reaction product 146, which sometimes deteriorates contact characteristics between the contact plug 144 and the wiring 122 (FIG. 36).
The inventors have found a new problem which had not been discovered, in studying semiconductor devices of the above-described conventional structures.
That is, in the SAC as exemplified in FIG. 37A in which a gate electrode 40 and a contact hole 22 overlap each other, and a step is formed in the contact hole, it has been found that when the contact hole 22 is opened in an inter-layer insulation film 20 formed of an insulation film 18 and an insulation film 16 which are formed of SiN film, the SiN film is more worn at the shoulder of the step in etching the insulation film 18. As a result, when the worn SiN film is removed using the conventional technique, even an insulation film 38 directly below the SiN film is adversely etched as shown in FIG. 37A by the dotted line, and a gate electrode 40 is adversely exposed.
When phosphoric acid and fluorine radicals are used in the etching to thereby raise etching selectivity between the SiN film and the oxide film to suppress the above-described wearing of the oxide film, as shown in FIG. 37B, the etching horizontally advances in the insulation film 16, and a cavity 30 is adversely formed. Subsequently when a conducting film 24 is deposited, the conduction film 24 is not deposited in the cavity 30. In the next step of forming a contact by burying W, WF.sub.6 intrudes through the cavity 30 to cause substrate erosion called a worm hole. Junction breakdown adversely takes place near a source/drain diffused layer 14.
Also in the case in which a self-aligned silicide (salicide) is formed on the source/drain diffused layer 14, a semiconductor substrate 10 is not sufficiently covered with the silicide layer 44 at the edge of the device isolation film 12, and a worm hole is caused at the edge which results in junction breakdown (FIG. 38).