(a) Field of the invention:
The present invention relates to a large-scale semiconductor integrated circuit device (called LSI hereinafter) and more particularly to an LSI made by a standard-cell system.
(b) Description of the prior art:
In order to construct various hardware systems, there have been already used LSI's of various types shown in FIG. 1, that is, standard logics such as TTL, microprocessor, semi-custom LSI and full-custom LSI. Among them, the types which can realize logic designs as desired are a semi-custom LSI including ROM, PLA (Programmable Logic Array), gate array and standard-cell LSI, and a full-custom LSI of manual design. The gate array LSI is manufactured to change only the final metallization steps of the manufacturing process using a master slice, thereby realizing the desired logic ; and the full-custom LSI is manufactured in accordance with any desired specification from the first step of the manufacturing process.
Of the semi-custom LSI, the standard-cell LSI is designed by selecting proper standard cells from a standard cell library which is stored in a computer and in which are registered in advance such various standard cells having any desired logical functions as counter, buffer, etc. comprising plural circuit elements such as transistor, resistor, etc. An example of the standard cell library is shown in Table 1. The layout on a semiconductor chip is conducted, by means of a CAD/CAE (Computer Aided Design/ Computer Aided Engineering) system, so that the standard cells are automatically placed at proper positions on the semiconductor chip and the routing between the respective standard cells is also automatically carried out. Therefore, the standard-cell LSI is a semi-custom LSI standardized in its constituent elements but is manufactured according to any desired specification from the first step of the manufacturing process as in the full-custom LSI in the manufacture.
TABLE 1 __________________________________________________________________________ (STANDRAD CELL LIBRARY OF SITL LSI) GROUP FUNCTION NAME __________________________________________________________________________ GATE INVERTER, NAND 1 OUTPUT NOT1 INVERTER, NAND 2 OUTPUT NOT2 INVERTER, NAND 3 OUTPUT NOT3 INVERTER, NAND 4 OUTPUT NOT4 2 INPUT OR OR2 3 INPUT OR OR3 4 INPUT OR OR4 2 INPUT NOR NOR2 3 INPUT NOR NOR3 4 INPUT NOR NOR4 EXCLUSIVE OR EOR EXCLUSIVE NOR EORN BUFFER POWER INVERTER NOTP (POWER GATE) NON INVERTING BUFFER 1 OUTPUT BUF1 NON INVERTING BUFFER 2 OUTPUT BUF2 MULTIPLEXER 8 TO 1 MULTIPLEXER MPX1 4 TO 1 MULTIPLEXER MPX2 DUAL 4 TO 1 MULTIPLEXER MPX3 2 TO 1 MULTIPLEXER MPX4 QUAD 2 TO 1 MULTIPLEXER MPX5 FLIP-FLOP D FLIP-FLOP DF1 D FLIP-FLOP WITH OE DF1E D FLIP-FLOP WITH RESET DFR D FLIP-FLOP WITH RESET & OE DFRE D FLIP-FLOP WITH SET & RESET DFQ D FLIP-FLOP WITH SET, RESET & OE DFQE JK FLIP-FLOP JK JK FLIP-FLOP WITH OE JKE SHIFT- 1 BIT SYNC LOAD SR SPL REGISTER 1 BIT ASYNC LOAD SR SP LATCH TRANSPARENT LATCH LC TRANSPARENT LATCH WITH OE LCE TRANSPARENT LATCH WITH RESET LCR TRANSPARENT LATCH WITH RESET & OE LCRE COUNTER 4 BIT SYNC UP COUNTER CTUL 4 BIT SYNC UP COUNTER CTU WITH DIRECT CLEAR 4 BIT SYNC UP/DOWN COUNTER CTUD 4 BIT SYNC UP COUNTER CTR WITHOUT PRESET 1 BIT RIPPLE COUNTER TFQ ADDER 1 BIT FULL ADDER FA 4 BIT FULL ADDER WITH FAST CARRY FA4 1 BIT HALF ADDER HA COMPARATOR 4 BIT MAGNITUDE COMPARATOR CMP DECODER 3 TO 8 DECODER DEC1 DECODER 2 TO 4 DECODER DEC2 DELAY 8 GATES DELAY DLY8 ELEMENT I/O BUFFER LS INPUT BUFFER IBLS S INPUT BUFFER IBS LS OUTPUT BUFFER OBLS S OUTPUT BUFFER OBS LS I/O BUFFER IOBLS LS TRI-STATE OUTPUT BUFFER OBLST LS SCHMITT TRIGGER INPUT BUFFER SIB LS LINE DRIVER OBLSL LS OPEN DRAIN OUTPUT BUFFER OBLSO TRI-STATE CONTROL BUFFER BUFTC SPECIAL CELL CRYSTAL OSCILLATOR XOS ROM 32 WORD .times. 8 Bit (256 Bit) ROM0 128 WORD .times. 8 Bit (1 kBit) ROM1 512 WORD .times. 8 Bit (4 kBit) ROM4 RAM 32 WORD .times. 8 Bit (256 Bit) RAM1 __________________________________________________________________________
Here, the manual design full-custom LSI, standard-cell LSI and gate array are compared in respect of a plurality of items in Table 2.
TABLE 2 __________________________________________________________________________ FULL-CUSTOM SEMI-CUSTOM ITEM MANUAL STANDARD-CELL GATE-ARRAY __________________________________________________________________________ LSI DESIGN BY USERS x .circle. .circle. UNNECESSITY OF x .circle. .circle. KNOWLEDGE OF PROCESS AND DEVICE FREEDOM OF FUNCTION .circleincircle. .circle. x (MEMORY, etc.) LAYOUT ERROR x .circle. .circle. LAYOUT COST x .circle. .circle. LAYOUT PERIOD x .circle. .circle. FREEDOM OF .circle. .circle. x GATE NUMBER OPTIMIZATION OF .circle. .circle. x I/O BUFFER (SPEEED, DRIVING POWER) FREEDOM OF .circle. .circle. x CHARACTERISTICS (SCHMITT TRIGGER, etc. DEVELOPMENT COST x .circle. .circle. DEVELOPMENT TIME x .circle. .circle. INTEGRATION DEGREE .circleincircle. .circle. x (CHIP COST) SPEED CHARACTERISTIC .circleincircle. .circle. x KEEPING OF .circle. .circleincircle. .circleincircle. CONFIDENTIALITY MULTI-FUNCTION .circle. .circle. x __________________________________________________________________________ x NOT GOOD, .circle. GOOD, VERY GOOD
According to Table 2, the standard-cell LSI has following advantages over the gate array. The gate array is formed of a logical block called a macro cell which is constituted by a combination of general-purpose basic gates and which therefore contains gates which are eventually not used; on the other hand, the standard-cell LSI is formed of standard cells having respectively only specific functions, and has no gate which is not used, that is, no excess gate. Therefore, for example, in the case of constructing a same flip-flop, the standard cell LSI will have an occupied area smaller than that of the gate array. Also, it is possible to provide as standard cells CPU, RAM, ROM, PLA, etc., resulting in large freedom of function. Further, in the standard-cell system, there is no restriction on number of gates and the chip can be comprised of properly requisite number of gates. Various speeds and current driving power characteristics are also possible and a buffer such as a Schmitt trigger can be available in the standard-cell system. By the way, the PLA is not shown in Table 2 but is greatly restricted in the integration degree and function, and is therefore found to be inadequate to be made large on the scale.
The standard-cell LSI has many advantages as described above but, at the same time, has a defect that the logic and timing of the first designed specification can not be easily changed. It is recently so increasingly required to develop devices within a short turn around time. To this end, it is required to be able to first develop an LSI with a provisional specification and to finally alter the specification such as logic, timing, etc. of the LSI. The conventional standard-cell LSI has not been able to satisfy such requirement. In the conventional standard-cell LSI, the LSI must be manufactured newly from the first step of the manufacturing process after altering the design. Thus, in the conventional standard-cell LSI, there has been a great problem that, in order to change the specification such as logic, timing, etc., the development time and cost will increase.