1. Field of the Invention
The present invention relates to an inverter controller for controlling a pulse-width modulated inverter. More particularly, the present invention pertains to a controller for controlling inverter switching elements which involves no fear of a short across the power supply during the commutation of a voltage-controlled inverter having a relatively small impedance when viewing the power supply side from the load, and which enables the control accuracy and response to be improved.
2. Description of the Related Art
In pulse-width modulated inverter controllers, an ON signal which is supplied to semiconductor switching elements is generally provided with a dead time of several tens of .mu.sec for the purpose of preventing the occurrence of a short across the power supply during the commutation.
This type of conventional inverter controller will be explained below with reference to FIGS. 10 to 13. FIG. 10 shows the circuit configuration of a conventional inverter controller, in which a single-phase inverter is exemplarily illustrated for simplification of the explanation.
An inverter 1 is constituted by semiconductor switching elements. More specifically, the inverter 1 is formed by series-connecting an anti-parallel circuit of a transistor 9 and a diode 11 and another anti-parallel circuit of a transistor 10 and a diode 12, these anti-parallel circuits being respectively connected to the positive side of a DC power supply 15 and the negative side of a DC power supply 16. One end of a single-phase load 13 is connected to the node of series connection between the transistor 9 and the transistor 10 which defines the output terminal of the inverter 1. The other end of the load 13 is grounded through a current detector 14. The node of series connection between the DC power supplies 15 and 16 is similarly grounded.
A current control amplifier 18 is supplied with, as inputs, an output current command value output from an output current command value calculating section 17 and a detected output current value output from the current detector 14, so as to calculate and output an output potential command for the inverter 1.
A delay circuit 4 is supplied with, as an input, the output potential command from the current control amplifier 18 and outputs a signal obtained by delaying the output potential command.
An AND circuit 6 is supplied with, as inputs, the output potential command and the delayed output potential command. The AND circuit 6 ANDs these signals to form an ON/OFF signal for the transistor 9. Another delay circuit 5 is supplied with the output potential command which is output from the current control amplifier 18 and inverted by a NOT circuit 3. The delay circuit 5 delays this inverted output potential command and outputs the delayed command to an AND circuit 7.
The AND circuit 7 is supplied with, as inputs, the inverted output potential command output from the NOT circuit 3 and the signal obtained by delaying the inverted output potential command through the delay circuit 5. The AND circuit 7 ANDs these signals and outputs the result of the ANDing as an ON/OFF signal for the transistor 10.
A driver 8 supplies the base of the transistor 9 with a signal processed on the basis of the ON/OFF signal for the transistor 9 output from the AND circuit 6 and also supplies the base of the transistor 10 with a signal processed on the basis of the ON/OFF signal for the transistor 10 output from the AND circuit 7.
FIG. 11 is a timing chart of various signals. The output of the delay circuit 4 is a signal which has a predetermined delay .DELTA.T with respect to the output potential command. In consequence, the output of the AND circuit 6, that is, the ON/OFF signal for the transistor 9, rises when a predetermined period of time .DELTA.T has elapsed after the rise of the output potential command. On the other hand, the output of the delay circuit 5 is a signal which has a predetermined delay .DELTA.T with respect to the inverted output potential command. In consequence, the output of the AND circuit 7, that is, the ON/OFF signal for the transistor 10 rises when a predetermined period of time .DELTA.T has elapsed after the fall of the output potential command. As a result, dead time .DELTA.T can be provided between the ON signal for the transistor 9 and the ON signal for the transistor 10. This dead time is provided for the purpose of preventing the occurrence of a short across of the power supply due to a possible delay in operation of the transistors when turned OFF and is generally set at several tens of .mu.sec. The operation of the conventional inverter controller involving such dead time is shown in FIGS. 12 and 13. Referring first to FIG. 12, an ON signal is supplied to the transistor 9 in the mode a, and current is flowing into the load 13 through the transistor 9. When, in this state, an OFF signal is supplied to the transistor 9 (the mode b), the current flowing through the transistor 9 decreases, and the current flowing through the diode 12 gradually increases. In this state, the transistor 9 has not yet been completely turned OFF. Therefore, if an ON signal is supplied to the transistor 10 in this state, the power supply is shorted. For this reason, it is necessary to supply an ON signal to the transistor 10 after the elapse of time which is sufficient for the transistor 9 to turn OFF completely, as shown in the mode c. The period of time during the mode b provided when the operation mode is shifted from the mode a to the mode c is referred to as "dead time".
Dead time is also provided when the operation mode is shifted from the mode c in which the transistor 10 is ON to the mode a in which the transistor 9 is ON. More specifically, the mode d is provided between the modes c and a.
The inverter operates in the above-described modes a to d when the output current is positive. When the output current is negative also, dead time such as modes f and h shown in FIG. 13 is similarly provided.
The dead time is set such to be sufficiently longer than a possible delay in operation of the transistors in order to prevent the occurrence of a short across the power supply and ensure the safety. However, the dead time constitutes an error with respect to the output potential command and therefore leads to lowering in the degree of accuracy in the current control. In addition, since the rise of the ON signal is delayed with respect to the output potential command, the response and stability are deteriorated.
To reduce the losses and noise in the load due to harmonic components, it is necessary to increase the switching frequency of the inverter so that the current ripple is reduced. However, since the above-described problems arise every switching operation of the inverter, such problems become even more conspicuous as the switching frequency becomes higher. Accordingly, the upper limit of switching frequency cannot be set at a high value, and the current ripple cannot be sufficiently reduced.
To solve the above-described problems, a method has already been tried in which the output voltage is fed back to detect an error portion in the output voltage due to the dead time, and the current control is corrected on the basis of this error portion (see, e.g., the specification of Japanese Patent Laid-Open No. 123478/1984).
This method suffers, however, from the following problems. Namely, the current control amplifier 18 shown in FIG. 10 needs to detect the error portion in the output voltage due to the dead time and carry out calculation for correcting the current control on the basis of the detected error. In addition, it is necessary to detect the output voltage at high speed and with a high degree of accuracy. Consequently, the current control method is complicated, and the controller for carrying out the method is costly. Further, since the switching operation of the inverter takes place with a delay corresponding to the dead time with respect to the output potential command at all times, the response and stability cannot be improved. This conventional method further involves a delay by the calculation of an error in the output voltage due to the dead time, and a delay by the calculation for correcting the error. It is therefore impossible to apply this method to the highly responsive current control in which the inverter is directly controlled by the instantaneous value of the current.
In order to overcome the above-described problems, another method has heretofore been tried in which the direction of the output current is fed back, and when the output current is positive, the supply of the ON signal to the transistor 10 is inhibited, whereas, when the output current is negative, the supply of the ON signal to the transistor 9 is inhibited, thereby carrying out current control without the need to provide dead time. This method, however, needs to feed back the direction of the output current, which means that the arrangement of the controller is complicated. The method is therefore disadvantageous from the economical point of view. In addition, when the detection system for detecting the direction of the output current is subjected to external disturbance such as noise, a serious accident, i.e., a short across the power supply may be caused, and this means that this method is unsatisfactory in terms of the reliability. When the output current is at or near the zero-crossing point, any drift of the detector leads to an erroneous detection of the direction of the output current, so that it becomes impossible to effect stable control of the inverter. For example, when the direction of the output current is positive and, therefore, the supply of the ON signal to the transistor 9 should be allowed, if the direction of the output current is errorneously recognized to be negative due to a drift of the detector and the supply of the ON signal to the transistor 9 is consequently inhibited, it becomes impossible to increase the output current any more.