1. Field of the Invention
The present invention relates to a semiconductor structure, and more particularly, to an interconnection structure.
2. Description of the Related Art
After the semiconductor fabricating process has developed into the deep micron field, some originally insignificant issues have become obvious problems due to the reduced size. In order to save space for further reducing the chip size, the electrostatic discharge circuit is commonly disposed below the pad.
During a wire bonding process using a thermocompression method, since too much pressure is applied on the pad, the dielectric layer sometimes cracks or even the pad would come off, leading to poor yield and low reliability of the package production. The cause of such problem is insufficient adherence between the dielectric layer and the metal layer and the stress from wire bonding process applied on the dielectric layer.
In order to prevent the semiconductor element below the pad from such impact and to ensure the successful bonding, it is quite often that the pad uses two metal layers, so the rest of the lower metal layers can be used for circuit wiring. For the fabricating process with fewer metal layers, the number of the metal layers used for circuit wiring is insufficient.