The present application relates to semiconductor device fabrication. More particularly, the present application relates to a flash memory device that can be fabricated using a standard complimentary metal-oxide-semiconductor (CMOS) process.
Embedded non-volatile memory (NVM) devices have been widely used to store code and security information or trim information in integrated circuits. Among them, embedded flash memory cells in particular have been incorporated into CMOS integrated circuits. Commercially available flash memory cells generally include a control gate, a floating gate and two interposed dielectric layers disposed upon a semiconductor substrate. The presence of the additional floating gate in flash memory cells compared to field effect transistors requires dedicated device processing in order to integrate the flash memory cells into an integrated circuit. This includes additional steps of depositing an inter-gate dielectric and a control gate, raising additional challenges in gate patterning and gate spacer formation. These additional processing steps result in longer processing times, higher manufacturing costs and low yield. As such, a process flow to fabricate flash memory cells that is compatible with a standard CMOS fabrication process is highly desirable.