1) Technical field of the Invention
The present invention relates to a power semiconductor device, and in particular, relates to the power semiconductor device with improved reliability for a thermal shock test.
2) Description of Related Arts
A power semiconductor device such as a power module includes, in general, an insulating substrate and a heat radiator (heat sink) bonded thereon via an adhesive layer of electrically conductive material such as a solder layer. Mounted on the substrate are a plurality of semiconductor chips such as an insulating gate bipolar transistor (IGBT) and a free wheel diode (FWD).
The power semiconductor device is often exposed to the thermal shock due to a varying ambient temperature and heat generated from the semiconductor chips in operation. Difference of linear expansion coefficients (linear expansivity) between the insulating substrate and the heat radiator causes a substantial amount of strain (stress) within the intervening solder layer, in which the solder cracking is occurred. When heated, the heat radiator made of metal such as copper expands relative to the insulating substrate from the middle portion towards the circumference thereof, and when cooled, the heat radiator shrinks relative to the insulating substrate from the circumference towards the middle portion thereof. Therefore, the stress of the solder layer adjacent to the circumference is much greater than that adjacent to the middle portion. Thus, the solder cracking is firstly appeared on the circumference and extends towards the middle portion of the solder layer as the power semiconductor device is repeatedly exposed to a number of the thermal shocks.
The solder cracking of the solder layer may arise various problems, in particular, when the solder cracking extends through the area beneath the semiconductor chips generating a substantial amount of heat, it likely blocks the heat conducting from the semiconductor chips to the heat radiator. Thus, the solder cracking may cause the semiconductor chips to be overheated, and hence to malfunction. In order to improve the reliability for the thermal shocks, it is required to prevent and/or delay the extension of the solder cracking from the circumference towards the middle portion of the solder layer so that no solder cracking is generated especially beneath the semiconductor chips.
Many approaches to prevent and/or delay the extension of the solder cracking has been incorporated in the conventional power semiconductor device. For example, the first approach is to design the intervening solder layer with increased thickness to absorb the stress therein. The second one is to design the insulating substrate having a round corner with the increased radius of curvature so that the distance from the corner to the middle portion is reduced.
The third one is to arrange a plurality of different semiconductor chips on the insulating substrate in a symmetric manner so that the deviation in the thermal distribution of the insulating substrate heated by each semiconductor chip is minimized. The fourth one is to develop a new material of the insulating substrate for reducing the stress in the intervening solder layer.
Also, according to the fifth approach, the semiconductor chips are provided on the insulating substrate as far away as possible from the circumference, thereby to prevent the extension of the solder cracking through the area beneath the semiconductor chips.
On the other hand, according to the semiconductor device disclosed in JPA 10-50928, a plurality of bosses are provided between the insulating substrate and the heat radiator in order to control the intervening solder layer to be thicker than a predetermined thickness.
Also, according to the heat sink of the semiconductor device disclosed in JPA 10-189845, a peripheral trench is provided on the heat sink at the position corresponding to the circumference of the insulating substrate, which is filled up with the solder. This effectively increases the thickness of the solder layer so that the strain in the circumference of the solder layer is absorbed.
However, there are several drawbacks with the above-mentioned approaches. That is, the intervening solder layer with the increased thickness causes a poor thermal conductivity of heat from the insulating substrate to the heat radiator via the intervening solder layer. Also, the package or size of the semiconductor device is increased because of the insulating substrate having the round corner (the second approach). Also, much greater space or area for mounting the semiconductor chips is required if the semiconductor chips are arranged on the insulating substrate in a symmetric manner (the third approach), or at positions as far away as possible from the circumference thereof (the fifth approach). Further, even though the new material of the insulating substrate has been developed (the fourth approach), it still needs time and efforts to adapt the material to the actual products.
Furthermore, the bosses indicated in JPA 10-50928 may be used to control the intervening solder layer to be thicker than a predetermined thickness. However, it can hardly controlled such that the thickness of the solder layer is uniform across the solder layer in a precise manner. When the insulating substrate is inclined relative to the heat sink in a certain direction, any one of the corners of the intervening solder layer has the thinner portion, so that the solder cracking extends from the thinner portion to the area beneath the semiconductor chips.
In addition, the trench disclosed in JPA 10-189845 may increase the thickness of the solder layer at the circumference, yet, the semiconductor device has to be mounted on the heat sink in a flat or parallel manner.
To address the aforementioned problems, one of the aspects of the present invention is to provide a power semiconductor device including a heat radiator having a principal surface and an insulating substrate bonded on the principal surface of the heat radiator via a first solder layer. The power semiconductor device also includes at least one semiconductor chip mounted on the insulating substrate via a second solder layer. The insulating substrate has a thin-layer and thick-layer edges, and is bonded on the principal surface of the heat radiator so that the first solder layer has a thickness thinner towards a direction from the thin-layer edge to the thick-layer edge (T1 greater than T2) . Also, the semiconductor chip is mounted on the insulating substrate so that a first distance between the thick-layer edge and the semiconductor chip is less than a second distance between the thin-layer edge and the semiconductor chip (L1 less than L2).
Further scope of applicability of the present invention will become apparent from the detailed description given herein. However it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the sprit and scope of the invention will become apparent to those skilled in the art from this detailed description.