1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit. More particularly, the present invention relates to an apparatus and method for preventing a system error caused by circuit synchronization and control disable circumstances upon the generation of a glitch when switching clocks.
2. Description of the Related Art
Semiconductor integrated circuits use clocks for the synchronization and control of logic circuits, flip-flop circuits and the like. In recent years, semiconductor integrated circuits provide a diversity of functions. The semiconductor integrated circuits integrating a diversity of functions include certain functions that require more clock sources than other functions, thus requiring a process of switching between many clocks.
A conventional clock switching technology performs switching without addressing a glitch of a clock caused by a select signal of a multiplexer. However, if a glitch is generated upon the switching of clocks, such a glitch has adverse effects upon a system, often making the system unstable.
FIGS. 1A and 1B are diagrams illustrating the generation of a glitch in a conventional clock switching circuit.
In FIG. 1A, a clock switching circuit outputs one of two clock signals, i.e., a first clock signal 100, or a second clock signal 102, by using a select signal (SEL) 104 for clock selection.
In FIG. 1B, a clock switching method can output either a first clock 110, or a second clock 120, depending on a value of select signal 130. When select signal 130 is low, clock signal 110 (clk 1) is output. When select signal 130 is high, clock signal 120 (clk 2) is output.
However, upon switching between the clocks 110 and 120, a glitch 140 is generated by a timing difference between the clocks 110 and 120.
In other words, upon switching between the clocks 110 and 120, a glitch is typically generated and may give rise to circuit synchronization problems and control disable problems, thus having a very bad impact upon a system.
Methods for preventing the generation of a glitch have been proposed to solve the glitch problem. However, these methods are mostly technologies for switching between two clocks, or switching to avoid generating a glitch considering a clock switching time or a relationship between the clocks.
For example, there has been previously proposed a method for removing a glitch by counting a predetermined value during a first clock and a second clock change interval while fixing a clock output CLOCK_OUT. This method is suitable when there is no change of a frequency difference between two clocks and switching between two clocks. However, the aforementioned method has problems when there is a large frequency difference between two clocks, or when there is switching between three or more clocks.
In addition to the above method, there is also a method that operates upon detecting a change of a select signal, and in response, gating a first clock and synchronizing a select signal of a multiplexer to a second clock that is a second clock, thus enabling the clock switching and removing a glitch. The above method also has problems when the number of clocks is three or more.