The invention relates to semiconductor memory devices and, more particularly, to a method for fabricating a non-volatile memory device with a charge trapping layer.
Non-volatile memory devices, which are electrically programmable and erasable devices, are used mainly in electronic components that require data retention even when no power is supplied. Such non-volatile memory devices typically have a floating gate structure. According to the existence or nonexistence of charges in a floating gate, a program operation or an erase operation is performed. As the degree of integration of semiconductor memory devices has increased, non-volatile memory devices with new cell structures have been required. Such non-volatile memory devices with new cell structures include non-volatile memory devices with a charge trapping layer. Such non-volatile memory devices with a charge trapping layer are classified as silicon-oxide-nitride-oxide-silicon (SONOS) structures and metal-aluminum oxide-nitride-oxide-silicon (MANOS) structures, depending on the characteristics of the charge trapping layer. According to a bias voltage applied to non-volatile memory devices with such structures, charges are stored in or discharged from the charge trapping layer to electrically perform a program operation or an erase operation.
FIG. 1 illustrates a cross-sectional view of a conventional non-volatile memory device with a charge trapping layer 110. Referring to FIG. 1, the non-volatile memory device with the charge trapping layer 110 includes a tunneling layer 105, the charge trapping layer 110, a blocking layer 115, and a control gate electrode 120 stacked on a semiconductor substrate 100. The blocking layer 115 is disposed between the control gate electrode 120 and the charge trapping layer 110 and generally comprises an aluminum oxide (Al2O3) film. Since the quality of the aluminum oxide (Al2O3) film is not high and a grain size of the aluminum oxide (Al2O3) film is small, a leakage current may occur. When the non-volatile memory device is fabricated with the quality of the film not being sufficiently high, characteristics of data retention may be adversely affected. To address this limitation, a thermal treatment process is performed to increase (i.e., “densify”) the quality of the film of the blocking layer 115, after the blocking layer 115 is deposited. A method for the film of the blocking layer 115 includes a process of depositing the blocking layer 115 at a high temperature ranging from approximately 600° C. to approximately 800° C., or a thermal treatment process performed at a high temperature after a deposition process. However, the thermal treatment process performed at the high temperature adversely affects a layer deposited below the blocking layer 115 or a profile of an impurity region formed in the semiconductor substrate 100. Also, temperature and run time of the thermal treatment process are limited to obtain the desired high-quality of the blocking layer 115 using the process of depositing the blocking layer 115 at the high temperature or the thermal treatment process after the deposition process. To address these limitations, a method is required, which can improve the characteristics of the film quality of the blocking layer 115 without affecting a layer below the blocking layer 115 or the semiconductor substrate 100, thereby improving the characteristics of the non-volatile memory device.