1. Field of the Invention
This invention relates to an improvement of a data reproducing device which was previously filed by the applicant of this invention in U.S. Patent Office on Dec. 14, 1993, and is disclosed in U.S. patent application Ser. No. 08/165,885, and more particularly to a data reproducing device which is suitably used to reproduce both of video data and audio data recorded on an optical disc in a time division multiplexing (TDM) imode while separating and decoding these data.
2. Description of Related Art
FIG. 1 is a block diagram showing the data reproducing device which is disclosed in U.S. patent application Ser. No. 08/165,885 (FIG. 6).
The data reproducing device has a disc driver 1 for reproducing data from an optical disc, on which video data and audio data are recorded in a time division multiplexing (TDM) mode, a decoding unit 2 to which reproduction data output from the driver 1 is supplied to decode the input data, and an ECC circuit 3 for receiving data output from the decoding unit 2 to detect and correct errors of the data. The output of the ECC circuit 3 is supplied to each of a ring buffer 4 and an address extracting circuit 31. The ring buffer 4 serves to accumulate a predetermined amount of data input thereto, and then output the accumulated data to a multiplexed data separating unit 5.
The multiplexed data separating unit 5 has a data separation circuit 21 for separating each of video data, audio data, an SCR (system clock reference), a DTS (decoding time stamp) for video data (hereinafter referred to as "DTSV"), and a DTS for audio data (hereinafter referred to as "DTSA") from data supplied from the ring buffer 4.
A data format for the data to be supplied to multiplexed data separation unit 5 is defined as shown in FIG. 2, for example. The format is defined as a multiplexed bit stream of MPEG (ISO11172). As shown in FIG. 2, the multiplexed bit stream comprises one or more packs (PACK), and each pack comprises one or more packet (PACKET). At the head of the pack is disposed a pack header (PACK HEADER), and at the packheader are disposed a pack start code (PACK START CODE) representing a start point of the pack, SCR and MUX RATE. The SCR represents a time when its final byte is input to the multiplexed data separation unit 5 (a time when a demultiplexing operation is started). The MUX RATE represents a transmission rate.
In an embodiment shown in FIG. 2, a video packet (VIDEO PACKET) and an audio packet (AUDIO PACKET) are successively disposed subsequently to the pack header. A packet header (PACKET HEADER) is disposed at the head of each of these video and audio packets, and the packet header has a video packet start code (VIDEO PACKET START CODE) or audio packet start code (AUDIO PACKET START CODE) representing a start point of the video or audio packet, and a DTSV or DTSA representing a start time of a decoding operation of the video or audio data. The video data (VIDEO DATA) or audio data (AUDIO DATA) are disposed subsequently to each packet header.
The timing data (time information) such as SCR, DTS (DTSV or DTSA) are represented with a count value of 90 kHz frequency clocks, and have 33-bit significant digit.
The video data which are separated in the data separation circuit 21 are supplied to a video code buffer 6 (FIFO), and the audio data are supplied to an audio code buffer 8 (FIFO). The SCR is supplied to and stored in an STC register 26. The STC register 26 serves to count clocks of 90 kHz frequency output from a clock generating circuit 27 and increment its storage value to generate an STC (system time clock).
The DTSV and DTSA which are separated by the data separation circuit 21 are supplied to and stored in a DTSV register 22 and a DTSA register 24 respectively. The data stored in the DTSV register 22 and the DTSA register 24 are supplied to comparators 23 and 25 respectively, and these data are compared with the STC output from the STC register 26.
The data reproducing device shown in FIG. 1 also has a control circuit 28 which comprises a CPU or the like and controls a reproducing operation on the basis of an instruction which is input in correspondence with an user's manipulation of an input unit 29, and an address storing circuit 30 for storing a reproduction start address and a reproduction end address which are input through the input unit 29.
The video data stored in the video code buffer 6 are read out and supplied to a video decoder 7, and decoded by the video decoder 7 to generate video signals. The generated video signals are output to a circuit (not shown). The video decoder 7 is supplied With a video decode start signal output from the comparator 23.
Likewise, the data output from the audio code buffer 8 are supplied to an audio decoder 9, and decoded therein. The audio decoder 9 is also supplied with an audio decode start signal output from the comparator 25.
Next, the operation of the data reproducing device as described above will be described with reference to FIG. 3. First, through manipulation of the input unit 29, a reproduction start address, a reproduction end address and a reproduction start are instructed to the control circuit 28. The reproduction start address and the reproduction end address are stored in the address storing circuit 30. At this time, the control circuit 28 outputs an instruction to the driver 1 to reproduce data recorded on an optical disc which is mounted in the driver 1. The reproduction data output from the driver 1 are supplied to the decoding unit 2 and decoded therein, and then supplied to the ECC circuit 3 in which the data are subjected to an error detection and correction processing.
The data which have been subjected to the error detection and correction processing in the ECC circuit 3 are supplied to the address extraction circuit 31 to read out an address disposed at a predetermined position in the data. The read-out address is supplied to the control circuit 28. The control circuit 28 is on standby until the read-out address supplied thereto is coincident with the reproduction start address from the address storing circuit 30, and if both of the addresses are coincident with each other, the control circuit 28 generates and outputs an accumulation start command to the ring buffer 4. Through this operation, the reproduction data output from the driver 1 are accumulated in the ring buffer 4. Thereafter, the data stored in the ring buffer 4 are read out from the ring buffer 4, and supplied to the data separation circuit 21 of the multiplexed data separation unit 5.
The data separation circuit 21 is controlled by the control circuit 28 to separate the video data and the audio data from the data supplied from the ring buffer 4. These video data and audio data are supplied to the video code buffer 6 and the audio code buffer 8, respectively. In addition, the data separation circuit 21 separates the SCR, the DTSV and the DTSA from the data, and supplied to and stored in the STC register 26, the DTSV register 22 and the DTSA register 24, respectively.
The STC register 26 stores the SCR, and subsequently it counts the clocks output from the clock generating circuit 27 to increment its storage value (SCR) in response to each clock. The storage value of the STC register 26 is supplied to the comparators 23 and 25 as an inner time (STC).
The DTSV register 22 keeps a DTSV which is first supplied thereto after the reproduction is started by the driver 1. This DTSV corresponds to a decode start time of the data of a picture at the head of the video data which are separated by the data separation circuit 21 and supplied to and stored in the video code buffer 6.
Likewise, the DTSA register 24 keeps a DTSA which is first supplied thereto after the reproduction is started. This DTSA corresponds to a decode start time of the data of a decode unit at the head of the audio data which are stored in the audio code buffer 8.
The SCR corresponds to a time when the data are supplied from the ring buffer 4 to the multiplexed data separation unit 5 and the demultiplexing operation is started (a time at the input time point of the input data). That is, it corresponds to a time t1 in FIG. 3. The STC register 26 serves to input a time data (current time) from the time t1 to one inputs of the comparators 23 and 25.
The DTSV register 22 supplies the other input of the comparator 23 with the time DTSV when the video decoder 7 starts its decoding operation. The comparator 23 outputs the video decode start signal to the video decoder 7 when the current time (STC) output from the STC register 26 is coincident with the decode start time output from the DTSV register 22 (time t2 in FIG. 3). The video decoder 7 reads out one frame of video data which have been written in the video code buffer 6 when supplied with the video decode start signal, and starts its decoding operation.
In FIG. 3, a straight line A represents a writing state of data into the video code buffer 6 (its slope represents a write-in transfer rate), and a polygonal line B represents a read-out state of data from the video code buffer 6 by the video decoder 7. Accordingly, data remains in an area represented by a shadow in the video code buffer 6. The storage capacity of the video code buffer 6 is represented by the distance in a vertical direction between lines A and C.
Upon input of the video code start signal, the video decoder 7 starts its decode operation to generate a video vertical synchronizing signal at the time when the decoding operation is completed, that is, at the time when a video decode delay time (VIDEO DECODE DELAY) elapses after the start of the decode operation, and output video signals subsequently to this generation. Accordingly, a display is started when the video decode delay time elapses after the start of the decoding operation.
Likewise, the comparator 25 outputs the audio decode start signal when the current time (STC) output from the STC register 26 is coincident with the decode start time (DTSA) of the audio data output from the DTSA register 24. When the audio decode start signal is input, the audio decoder 9 reads out from the audio code buffer 8 data whose amount corresponds to a decode unit and starts its decode processing to generate audio signals, and outputs the generated audio signals to a circuit (not shown).
During the reproducing operation of the driver 1, addresses being read out are supplied from the address extraction circuit 31 to the control circuit 28 at all times. The control circuit 28 compares the address of data being read out and supplied thereto with the reproduction end address stored in the address storing circuit 30, and if both addresses are coincident with each other, it ends the read-out operation from the driver 1.
Since the data remain in the ring buffer 4 and the code buffers 6 and 8, the actual end time of the reproducing operation is the time when there exists no data to be input to the video decoder 7 and the audio decoder 9. In this case, the control circuit 28 finishes the reproducing operation when detecting the absence of the data to be input to the video decoder 7 and the audio decoder 9.
Now, it is considered to continuously reproduce any discontinuous two points on an optical disc having video signals recorded thereon while compressed in the MPEG system. In other words, an edition of the reproducing operation is now considered.
FIG. 4 is a timing chart for a continuous reproducing operation of a predetermined range of data on the optical disc. Here, sectioning points for an edition are represented by G, H and I, and pictures before and after the sectioning points G, H and I are represented by (a,b), (c,d) and (e, f), respectively.
In FIG. 4, a straight line D represents a write-in state of data into the video code buffer 6, and its slope represents a write-in transfer rate. A polygonal line E represents a data read-out state from the video code buffer 6 by the video decoder 7. Accordingly, data remain in an area represented by a shadow in the video code buffer 6. The storage capacity of the video code buffer 6 is represented by the distance in a vertical direction between the lines D and F.
It is now assumed that the reproduction point is jumped from the point G to the point H in FIG. 4. If a continuous reproduction is performed with no jumping operation, a picture b is reproduced subsequently to a picture a. However, if the jumping operation is performed, a picture d is reproduced subsequently to the picture a. Assuming a time required for the jump from the point G to the point H to be zero, the write-in and read-out operations of the data of the video code buffer 6 when the jumping operation as described above is performed are carried out as shown in FIG. 5.
That is, when no jumping operation is performed, at the point G, the write-in operation of the picture b and subsequent pictures are performed for the video code buffer 6 at a time t11, and this write-in operation is continued until a time t12. At the time t12, the data of the picture b is read out from the video code buffer 6, and supplied to the video decoder 7 to decode the data. The read-out of the data of the picture b at the time t12 is started after a time corresponding to one frame elapses from the read-out of the data of the picture a just before the picture b. The time period Tb between the time t11 and the time t12 is a start up delay of the picture b, and it corresponds to a time from the input of the data of the picture into the video code buffer 6 till the decoding of the data. In the MPEG system, an image compression processing is performed in accordance with complication of an image of each picture, so that a data amount becomes larger as an image is complicated while the data amount becomes smaller as an image is simple. Therefore, a different start up delay is basically adopted every picture in the MPEG system.
In the above case, the start up delay Tb of the picture b to be reproduced subsequently to the picture a when no jump is performed at the point G becomes smaller than the start up delay Td of the picture d to be reproduced subsequently to the picture a through the jumping operation from the point G to the point H.
Accordingly, as shown in FIG. 5, just before the jump is performed at the point G, the video decoder 7 is about to read out and decode the data of the next picture b from the video code buffer 6 at the timing when the data of the picture a written in the video code buffer 6 is decoded and a time corresponding to one frame elapses from the above decoding. However, in this case, since the jump is performed, the write-in operation of the data of the picture d into the video code buffer 6 is started at the time t11. Therefore, when the video decoder 7 is about to read out and decode the data of a next picture at the time t12 when the start up delay Tb of the picture b elapses from the time t11, one frame data of the picture d has not yet been written in the video code buffer 6 because the start up delay Td of the picture d is larger than the start up delay Tb of the picture b. Consequently, if the video decoder 7 reads out one frame data from the video code buffer 6, the video code buffer 6 falls into an underflow state.
On the other hand, in a case where the jump is performed from the point H to the point I in FIG. 4, the start up delay Td of the picture d to be reproduced subsequently to a picture c when no jump is performed at the point H becomes larger than the start up delay Tf of a picture f to be reproduced subsequently to the picture c through the jump operation from the point H to the point I. Consequently, the operation of the video decoder 7 when the jump is performed from the point H to the point I is performed as shown in FIG. 6 on the assumption that the time required for the jump operation is equal to zero as described above.
In this case, through the jump from the point H to the point I at a time t13, the write-in operation of the data of the picture f into the video code buffer 6 is started at the time t13. However, the start up delay Tf of the picture f is smaller than the start up delay Td of the picture d which would be reproduced if no jump is performed at the point H, so that the data of the picture f will have been stored in the video code buffer 6 for a time longer than the original start up delay Tf of the picture f.
That is, the video decoder 7 cannot start the decoding of the data of the picture f from the time when it reads out the data of the picture c until a time t32 when a time corresponding to one frame elapses from the above read-out time (this time corresponds to the end time of the start up delay Td of the picture d). As a result, the decode timing for data which contain the picture f data and subsequent picture data (read-out timing from the video code buffer 6) is delayed by the difference between the start up delay Td of the picture d and the start up delay Tf of the picture f (Td-Tf). Therefore, as shown in FIG. 6, the picture f data and the subsequent data are accumulated, and the video code buffer may fall into an overflow state.
In order to prevent the underflow as described above, the decode timing of the video decoder 7 must be delayed from the time t12 in FIG. 5. Likewise, in order to prevent the overflow, the write-in of the data into the video code buffer 6 from the point I when the jump is performed at the point H is required to be delayed by the difference (Td-Tf) of the start up delays of the pictures d and f.
However, the device shown in FIG. 1 has no element for adjusting the start up delay before and after an edition point. Therefore, when an editing operation is instructed, the overall reproducing operation is temporarily stopped at the reproduction point at which the jump is instructed. Thereafter, the reproducing operation is re-started at a jumped reproduction point.
As a result, for example when the jump is performed from the point G to the point H, the overall reproducing operation of the driver 1 is temporarily stopped at the point G (time t11) as shown in FIG. 8. However, since the data of the picture a has been already written in the video code buffer 6, the video decoder 7 reads out the data of the picture a at a time t41 to decode and output the data. After the decode processing of the data of the picture a is completed, the control circuit 28 controls the driver 1 again to restart the reproducing operation from the point H (time t42). Through this operation, at a time t43 when the start up delay Td of the picture d elapses from the time t42, the data are read out from the video code buffer 6, and then decoded in the video decoder 7.
In a case where the jump is performed from the point H to the point I, the overall reproducing operation of the driver 1 is temporarily stopped at the time t13 (when arriving at the point H) as shown in FIG. 9. Thereafter, the data which have been already written in the video code buffer 6 are decoded in the video decoder 7. The decode processing is completed at a time t51.
As described above, when the decoding operation of the data which have been already stored in the video code buffer 6 is completed, the driver 1 is controlled again, and the reproduction is started from the point I at the time t52 to write the data in the video code buffer 6. Thereafter, at the time t53 when the start up delay Tf of the picture f elapses from the time t52, the decode of the picture f is started.
In the device shown in FIG. 1, when the reproduction point is discontinuously shifted as described above, the reproducing operation is temporarily finished at a predetermined reproduction point, and then the reproducing operation is restarted from a shifted reproduction point. Therefore, there exists a problem of a data lack time of reproduction data, that is, a time in which the reproduction data are lacking (the period from the time t41 till the time t43 in FIG. 8 or the period from the time t51 till the time t53 in FIG. 9).