1. Field of the Invention
The invention relates in general to a vertical channel transistor structure and a manufacturing method thereof, and more particularly to a vertical channel transistor structure with a narrow channel and a manufacturing method therefor.
2. Description of the Related Art
Along with other advances in semiconductor manufacturing technology, the resolution of current semiconductor elements has reached the nanometer level. For example, the reduction in gate length and element pitch in memory units is carried on continually. Although the technology of photolithography has improved greatly, currently manufactured planar transistor structures have reached the limit of resolution, and the transistor elements manufactured thereby are apt to have the problems of electrostatic discharge (ESD), leakage, and decrease in electron mobility, resulting in short channel effect and drain induced barrier lowering (DIBL) effect. Thus, the double-gate or tri-gate vertical channel transistors capable of providing higher packing density, better carrier transport and device scalability, such as the fin field effect transistor (fin FET) for instance, have become transistor structures with great potential.
The fin FET transistor has a vertical channel that can be formed on the two lateral surfaces of the fin FET transistor and turns on the current by the double-gate or the tri-gate, hence having higher efficiency than conventional planar channel transistors.
When manufacturing a fin FET element with high resolution, expensive processes such as the photolithography process and the E-beam process are required. Therefore, the throughput can hardly be increased and large-scale production is difficult to achieve. There is another manufacturing method which reduces the channel width by applying oxidation to the etched channel. However, the element formed according to the above method has poor uniformity and unstable quality.