The present invention relates to a programmable nonvolatile memory, and a technique effective if applied to, for example, an electrically programmable AND type flash memory.
An AND type flash memory has been described in a patent document 1 (Japanese Unexamined Patent Publication No. 2004-152977). As one flash memory, there is shown a structure wherein diffusion regions are repeatedly parallel-formed over a semiconductor substrate, auxiliary electrodes are disposed among the respective diffusion regions through an oxide film interposed thereamong to form control transistors, and memory transistors each based on a charge storage region and a control gate are formed on the right and left sides of the auxiliary electrodes. The control gates extend in the direction of diffusion and intersecting the auxiliary electrodes and function as word lines. Further, there is shown, as another structure, a structure wherein other control transistors using auxiliary electrodes in place of the diffused layers are adopted. When the control transistors are turned on, inversion layers are formed in their channel regions and function as wirings. Since the diffusion regions may not be repeatedly disposed in parallel in the latter structure, the structure is excellent in terms of a further reduction in chip area.
Upon reading for each memory of the structure, the memory transistor for reading is made conductive to its right and left diffusion regions and inversion layers. At this time, memory information is determined according to whether a change in current occurs in the diffusion region according to the threshold voltage of the memory transistor. Upon writing for the memory of the structure, the memory transistor for writing is made conductive to its right and left diffusion regions and inversion layers to allow a write current to flow from the diffusion regions to the inversion layers. At this time, electric field concentration occurs between the corresponding inversion layer and a channel of the memory transistor by reducing the conductance of the control transistor adjacent to the memory transistor for writing, whereby hot electrons generated by the field concentration are injected into the corresponding charge storage region. This write system is referred to as “non cell-through write system”.