The present invention relates generally to integrated circuit chip package technology, and more particularly to a unique package design that facilitates the efficient placement of the leads therein.
Integrated circuit dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the integrated circuit die and an underlying substrate such as a printed circuit board (“PCB”).
Semiconductor packages employing micro lead frames (“MLF”) typically include a metal lead frame (often made from copper (Cu)), an integrated circuit die, bonding material to attach the integrated circuit die to the lead frame, bond wires which electrically connect pads on the integrated circuit die to individual leads of the lead frame, and a hard plastic encapsulant material which covers the other components and forms the exterior of the package.
The lead frame is the central supporting structure of such packages. A portion of the lead frame is internal to the package, i.e., completely surrounded by the plastic encapsulant. Portions of the leads of the lead frame extend externally from the package or are partially exposed within the encapsulant material for use in electrically connecting the die to the underlying substrate. Due to the relatively short electrical path from the die to the lead, such MLF packages can exhibit improved electrical efficiency in comparison to conventional Quad Flat Package (“QFP”) designs.
One of the drawbacks associated with certain MLF semiconductor packages is the limited surface area available to accommodate leads. Modern integrated circuit dies often include larger numbers of input and output pads than previous dies. To accommodate these additional pads, increasing numbers of leads must also be provided with semiconductor packages. Unfortunately, conventional MLF designs typically require these leads to be located on the bottom surface of the semiconductor package around the perimeter of a die paddle portion of the lead frame. Thus, the limited surface area available for lead placement on such packages can significantly impact the number of leads provided.
The present invention addresses this problem by providing various chip on lead configurations (“COL”) which position portions of leads underneath the integrated circuit die, thereby allowing more efficient use of the semiconductor package bottom surface area.