This invention relates to a pattern synchronous circuit for sorting a parallel signal so that a signal evaluation can be made to a signal after making a serial-parallel conversion of an inputted evaluation pattern in a pattern evaluation apparatus for evaluating a frame signal.
A frame signal having a frame identification pattern is used in a transmission device test.
In this kind of test, a pattern based on actual transmission standards is outputted from a pulse pattern generator and is inputted to an evaluation device unit and the output is observed by a pattern evaluation apparatus or an oscilloscope.
The pattern evaluation apparatus normally makes a serial-parallel conversion to a received signal and reduces the signal to a signal speed easy to process and conducts the evaluation. However, timing of inputting the received signal is not determined, so that a leading position of a frame is not determined in a signal after the serial-parallel conversion. As a result of that, it must be constructed so that subsequent evaluations can be made by detecting the frame identification pattern and sorting a parallel signal.
FIG. 11 shows a configuration of a pattern n apparatus after the serial-parallel conversion. In FIG. 11, numeral 1 is a parallel signal input terminal to which a signal changing a received signal into n parallel signals is inputted, and numeral 2 is a clock input terminal, and numeral 31 is a branch circuit, and numeral 32 is a frame detection circuit, and numeral 33 is a shift circuit, and numeral 34 is a measurement circuit, and numeral 35 is a frame position signal, and numeral 300 is a pattern synchronous circuit.
The signal changing the received signal into the n parallel signals is inputted to the frame detection circuit 32 and the shift circuit 33 through the branch circuit 31.
A clock signal for processing a parallel signal is inputted to the clock input terminal 2. In the frame detection circuit 32, a parallel input signal is monitored and a frame identification pattern is detected and a signal indicating its place is outputted to the frame position signal 35. The shift circuit 33 is a sort circuit for sorting the parallel input signal and in the shift circuit 33, the parallel input signal is sorted by the frame position signal 35 and in the measurement circuit 34, an output is produced so that it becomes a measurable state, namely the lead of a frame becomes a leading position of the parallel signal.
In this case, the shift circuit 33 can implement a pattern synchronous operation by performing processing as described in a truth table shown in FIG. 12, for example, when the number n of parallel signals is 16. The truth table shown in FIG. 12 indicates that SEL corresponds to a frame position signal and a signal is selected from the parallel signals of 16 bits as shown in output by SEL input and is outputted. Also, the places described as A(+1), B(+1), C(+1), . . . indicate signals after one clock of inputs A, B, C, . . . ,
Here, when the shift circuit 33 of FIG. 11 produces an increase in circuit scale, particularly an increase in the number n of signals, integration into one integrated circuit becomes difficult. Thus, the shift circuit 33 is implemented by a plurality of integrated circuits.
Next, a pattern synchronous circuit according to a conventional art will be described using FIG. 7. In FIG. 7, numeral 1 is a parallel signal input terminal, and numeral 2 is a clock input terminal, and numeral 3 is a parallel signal output terminal, and numeral 21 is a branch circuit, and numeral 22 is a frame detection circuit, and numeral 23 is a shift part, and numerals 24a to 24d are shift circuits A to D constructing the shift part 23, and numeral 25 is a frame position signal. The shift part 23 comprises a plurality of the shift circuits 24a to 24d. As a result of that, the shift circuit per circuit performs sorting of the number n of parallel signals and data processing of the number divided by the number m of integrated circuits.
A signal inputted to the parallel signal input terminal 1 is branched to the frame detection circuit 22 and all the shift circuits 24a to 24d through the branch circuit 21. The frame detection circuit 22 detects a frame identification pattern in the parallel signals and outputs a signal to the frame position signal 25. The frame position signal 25 is connected to all the shift circuits 24a to 24d, and the shift circuits 24a to 24d sort the parallel signals by the frame position signal 25.
As examples, FIGS. 8 and 9 indicate truth tables showing operations of the shift circuit A and the shift circuit B where the number n of parallel signals is 16 bits and four shift circuits are used.
When the frame position signal is 0, the shift circuit A outputs signals A, B, C, D inputted to D0 to D3. At that time, the shift circuit B outputs signals E, F, G, H inputted to D4 to D7 since the shift circuit B outputs signals subsequent to the signals outputted by the shift circuit 24a. Also, when the frame position signal is 1, the shift circuit 24a outputs signals B, C, D, E inputted to D1 to D4, and the shift circuit 24b outputs signals F, G, H, I which are signals subsequent to the signals outputted by the shift circuit 24a. Truth tables of operations of the shift circuit 24c and the shift circuit 24d are omitted, but the truth tables can be derived in a manner similar to truth values of FIGS. 8 and 9.
Operations of a pattern synchronous circuit 200 of FIG. 7 will be described concretely using FIGS. 10A and 10B.
It is assumed that the number of parallel signal inputs is 16 bits and for the purpose of illustration, parallel signals of 16 bits are described as a, b, c, . . . , o, p and the leading of a frame begins with a. Expressions such as p(−1) indicate a bit earlier than p by one clock.
FIGS. 10A and 10B show an example in which a frame of an input signal begins with BIT 7 of the parallel signal input terminal. The frame detection circuit 22 outputs a value 7 to the frame position signal 25 when detecting the frame in beginning with BIT 7. Then, the shift circuit 24a selects BITs 7 to 10 from the parallel signals of 16 bits, and also the shift circuit 24b selects BITs 11 to 13 and outputs them. Similarly, the shift circuits 24c and 24d select respectively corresponding 4 bits from input signals and thereby, an output signal in which the leading of the frame begins with BIT 0 of the parallel signals as a whole can be obtained.
Here, all the information of the inputted parallel signals needs to be inputted to all the shift circuits 24a to 24d in order to cope with a start position of the frame in all the states. For that purpose, all the bits of the input signals are branched to all the shift circuits 24a to 24d by the branch circuit. Then, all the shift circuits 24a to 24d require the number of input I/Os corresponding to the number n of parallel bits of the input signals.
As described above, in the pattern synchronous circuit according to the conventional art, all the bits of the parallel signals inputted to the parallel signal input terminal 1 are branched by the branch circuit 21 and are inputted to all the shift circuits 24a to 24d constructing the shift part 23. Then, the respective shift circuits 24a to 24d select only the number of signals obtained by dividing the number n of parallel signals of the output signals by the number of sort integrated circuits from the input signals and output it on the basis of the frame position signal 25 outputted by the frame detection circuit 22. An output signal in which the frame begins with BIT 0 of the parallel signals can be obtained by merging outputs of all the shift circuits 24a to 24d. 
However, in the conventional pattern synchronous circuit described above, an input signal is branched to all the shift circuits, so that the number of wirings increases in proportion to the number n of parallel signals and the number m of shift circuits. Also, since all the bits of a parallel signal input are inputted to the shift circuits, the number of I/Os of the shift circuits becomes large with an increase in the number n of parallel signals and thus a large package is required. As a result of that, miniaturization of the pattern synchronous circuit is difficult.