1. Field of the Invention
The present invention relates allowing a memory controller to optimize strobe to clock relationship for a DRAM.
2. Background Information
A Dynamic Random Access Memory, DRAM, is a typical memory to store information for computers and computing systems, such as, personal digital assistants and cellular phones. DRAMs contain a memory cell array having a plurality of individual memory cells; each memory cell is coupled to one of a plurality of sense amplifiers, bit lines, and word lines. The memory cell array is arranged as a matrix of rows and columns, and the matrix is further subdivided into a number of banks.
One type of DRAM is a synchronous dynamic random access memory (SDRAM) that may allow for synchronous operation with a processor. Specific types of SDRAM are a single data rate (SDR) SDRAM and a double data rate (DDR) SDRAM. For example, a present DDR memory type is DDR3. Typically, a DDR DRAM may send data (DQ), when enabled by a DQS clock signal, to a memory controller or memory controller hub (MCH). The memory controller or MCH may receive the data from the DDR DRAM by utilizing precision delay cells to provide a delayed DQS clock signal.
Typically, motherboard specification and guidelines synchronize the DQS to a system clock (SCLK) relationship at a specific DRAM. However, with the advent of DDR3 DRAM, a typical tree structure for clocks is not utilized and the DQS to SCLK relationship differs by DRAM position on a Dual Inline Memory Module (DIMM).