1. Field of the Invention
The present invention relates to a display unit in which light emitting pixels are arrayed in a matrix form, and an image signal having a half tone can be displayed.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a conventional display unit disclosed in Japanese Patent Publication (Kokoku) No. 2-709. In FIG. 1, reference numeral 1 denotes a matrix display panel such as a fluorescent character display tube, 2 is a driver to drive row electrodes of the matrix display panel 1, and 3 is another driver to drive column electrodes of the matrix display panel 1. Display elements (light emitting elements) are disposed at intersections of the row electrodes and the column electrodes, and are turned ON by driving the corresponding row electrode and the corresponding column electrode. Reference numeral 4 denotes a shift register to place an ON/OFF signal from a changing portion 15 on the corresponding column electrode, 5 is a row electrode control circuit to create a drive signal for the row electrode, and 6 is a column electrode control circuit to create a drive signal for the column electrode. The column electrode control circuit 6 latches output of the shift register 4 for a predetermined time interval depending upon a latch signal from a timing generating circuit 8.
Reference numeral 9 denotes a display control unit to write display data onto a memory 7, 10 is a selector to feed the memory 7 with any one of a read address and a write address, 11 is a read/write control circuit to feed the selector 10 with a switching signal, 12 is a clock generating circuit to feed a clock signal to the timing generating circuit 8 and the read/write control circuit 11, 13 is a read address counter to generate the read address, and 15 is the changing portion to transform data read from the memory 7 into the ON/OFF signal for pixel.
The matrix display panel 1 is provided with a structure as shown in FIG. 2. That is, the display elements are disposed at intersections of a group of signal lines for feeding signals to the column electrodes X.sub.1 to X.sub.m and a group of signal lines for feeding signals to the row electrodes Y.sub.1 to Y.sub.m. Thus, the display elements are controlled according to a combination of the signals fed to the two groups of signal lines.
A description will now be given of the operation. The display control unit 9 outputs the display data, an address corresponding to a position at which the display data is displayed, and a timing signal in synchronization with the display data. The timing signal is inputted into the read/write control circuit 11. The read/write control circuit 11 receives the timing signal as input, and thereafter outputs a signal by which the selector 10 is switched over to the write address. Therefore, the address from the display control unit 9 is fed to the memory 7 as the write address. As a result, the display data can be stored in the memory 7 at an area specified by the write address.
Further, the display data stored in the memory 7 is read out according to the read address which is produced in the read address counter 13. The read address counter 13 generates an X address (a column address) fed to the column electrode control circuit 6, a Y address (a row address) fed to the row electrode control circuit 5, and a comparison signal B. The X address and the Y address are fed into the memory 7 through the selector 10. In this case, the selector 10 selects the read address according to control by the read/write control circuit 11. Consequently, it is possible to output data from the memory 7 according to the read address including the X address and the Y address.
Further, the Y address is sent to the row electrode control circuit 5. The row electrode control circuit 5 decodes the Y address so as to drive the row electrodes Y.sub.1 to Y.sub.m of the matrix display panel 1 through the driver 2. The data read from the memory 7 is sent to the changing portion 15. The changing portion 15 compares the data with the comparison signal B produced in the read address counter 13 so as to generate an ON/OFF signal according to the result of comparison. When the data is greater than the signal B, the ON signal is generated. When the data is equal to or less than the signal B, the OFF signal is generated. Here, `1` shows the ON signal and `0` shows the OFF signal. The ON/OFF signal is disposed in the shift register 4 according to a shift clock from the timing generating circuit 8. Further, the signal is latched by the column electrode control circuit 6 in response to a latch signal from the timing generating circuit 8. In response to the latched signal, the column electrode control circuit 6 drives the column electrodes X.sub.1 to X.sub.m through the driver 3.
In such a display unit, an image is displayed by sequentially and periodically driving the row electrodes Y.sub.1 to Y.sub.m, and by switching operation of a signal which is fed to the column electrodes X.sub.1 to X.sub.m in synchronization with the driving of the row electrodes Y.sub.1 to Y.sub.m. The display elements can exclusively provide binary representation, that is, any one of ON and OFF. However, when an image signal having a half tone should be displayed, the data in the memory is read out a predetermined number of times, and a cumulative elapsed ON time in each display element is controlled, thereby realizing gray image display.
A more detailed description will now be given of a display operation by way of, as an example, the matrix display panel 1 including a device having a 4-by-4 pixel array. Pixel positions in the matrix display panel 1 correspond to memory addresses in a one-to-one manner, resulting in a relationship as shown in FIGS. 3 and 4. FIG. 3 shows the pixel positions, and FIG. 4 shows the memory addresses corresponding to the respective pixel positions. FIG. 5 shows illustrative display data stored in the memory 7 at the respective addresses. As shown in FIG. 6, the addresses of the memory 7 can be classified into the X address and the Y address. FIG. 9 is a timing diagram showing row electrode driving timing and column electrode driving timing. FIG. 10 is an explanatory view showing the result of the driving.
When the display data corresponding to each pixel includes a 4-bit structure, it is possible to display a 16-scale gray image (because of 2.sup.4 =16). In this case, as shown in FIG. 7, the read address counter 13 includes a 2-bit counter 13a for generating the X address, a 4-bit counter 13b for generating the comparison signal B, and a 2-bit counter 13c for generating the Y address. The 2-bit counter 13b counts the clock signal from the read/write control circuit 11 to sequentially output values of 0 to 3 corresponding to the column electrodes X.sub.1 to X.sub.4. The 4-bit counter 13b counts a carry signal of the 2-bit counter 13a. In the 4-bit counter 13b, an initial value is set to zero. The 2-bit counter 13c counts a carry signal of the 4-bit counter 13b. The initial value of zero in the 2-bit counter 13c corresponds to the row electrode Y.sub.1.
Accordingly, with the comparison signal B of zero and the Y address of zero, four data stored in the first row shown in FIG. 5 are sequentially read out. As shown in FIG. 8, the changing portion 15 comprises, for example, a comparator 15a. The comparator 15a compares display data A with the comparison signal B so as to output an ON signal when A is greater than B, or output an OFF signal when A is equal to or less than B. As shown in FIGS. 5 and 6, the first row sequentially contains data of "15 (in decimal notation)," "10 (in decimal notation)," "12 (in decimal notation)," and "0". Since the comparison signal B is zero, the changing portion 15 sequentially outputs "1," "1," "1," and "0". Signals from the changing portion 15 are sequentially inputted into the shift register 4.
When the respective signals in the first row are inputted into the shift register 4, the timing generating circuit 8 outputs the latch signal such that the contents of the shift register 4 can be latched by the column electrode control circuit 6. The column electrode control circuit 6 drives the column electrodes X.sub.1 to X.sub.4 through the driver 3 according to the contents of the shift register 4. At the time, a value of zero is fed into the row electrode control circuit 5 as the Y address so that the row electrode control circuit 5 can drive the row electrode Y.sub.1 in the first row through the driver 2. Thus, as shown by a period t1 in FIGS. 9 and 10, display elements at intersections of the first row and the first to third columns are turned ON, and a display element at an intersection of the first row and the fourth column is not turned ON. In FIG. 10, a hollow ring denotes a display element which is turned ON, and a numeral in the hollow ring denotes an ON time interval. Further, reference numerals t1 to t64 correspond to reference numerals t1 to t64 in FIG. 9.
Next, by the read/write control circuit 11, a count value of the 2-bit counter 13a is reset to zero, and a count value of the 4-bit counter 13b is set to one. A count value of the 2-bit counter 13c is zero. Consequently, the four display data in the first row are read from the memory 7 again, and the display data are compared with the comparison signal B (=1) in the changing portion 15. According to the result of comparison, the changing portion 15, the shift register 4, the column electrode control circuit 6, and row electrode control circuit 5 are operated as set forth above. Therefore, as shown by a period t2 in FIGS. 9 and 10, the display elements are turned ON at the intersections of the first row and the first to third columns, and the display element at the intersection of the first row and the fourth column is not turned ON.
When the count value of the 4-bit counter 13b reaches 15 (in decimal notation) after count from 0 to 3 is repeated in the 2-bit counter 13a, the changing portion 15 compares the data in the first row from the memory 7 with the comparison signal B (=15). The first row sequentially contains the data of "15 (in decimal notation)," "10 (in decimal notation)," "12 (in decimal notation)," and "0." Because of the comparison signal of 15, the changing portion 15 sequentially outputs "0," "0," "0," and "0." As a result, as shown by a period t16 in FIGS. 9 and 10, all the display elements at the intersections of the first row and the first to fourth columns are not turned ON. As set forth above, comparison is made the number of times identical with the number of gray scale for each row data. As shown at the leftmost end of the first row in FIGS. 9 and 10, according to the result of comparison, the display element corresponding to the address "0" is held ON for a period of 15 unit times, the display element corresponding to the address "1" is held ON for a period of 10 unit times, and the display element corresponding to the address "2" is held ON for a period of 12 unit times. In such a manner, a gray image can visually be displayed according to the ON time periods.
Next, the count values of the 2-bit counter 13a and the 4-bit counter 13b are reset to zero, thereby setting the count value of the 2-bit counter 13c to one. Thus, the above processing is performed for data in the second row corresponding to the Y address "1". As a result, as shown at the leftmost end of the second row in FIGS. 9 and 10, the display element corresponding to the address "4" is held ON for a period of 8 unit times, the display element corresponding to the address "5" is held ON for a period of 4 unit times, the display element corresponding to the address "6" is held ON for a period of 2 unit times, and the display element corresponding to the address "7" is held ON for a period of 14 unit times.
The above processing is similarly carried out for data in the third row (the Y address of 2) and the fourth row (the Y address of 3), resulting in completion of the display operation in one frame. In the conventional display unit shown in FIG. 1, all the ON signals have a constant time interval as shown in FIG. 11, and a pulse number control method is employed in which the gray image display is realized according to the number of the ON signals.
On the other hand, another display unit is known in which pulse width control is made. In such a display unit, as shown in FIG. 12, a changing portion 15 has a selector 15b which can select one bit among 4-bit display data from a memory 7 according to a select signal S. The selection of the selector 15b results in an ON/OFF signal. Further, a timing generating circuit 8 is controlled to vary a time interval of the ON signal according to a bit weight (selected from weights 1, 2, 4, and 8). FIG. 13 is a timing diagram showing row electrode driving timing and column electrode driving timing. FIG. 14 is an explanatory view showing the result of driving.
In this case, a counter for generating an X address in a read address counter 13 sequentially feeds the memory 7 with values of 0 to 3. Output timing of the values of 0, 1, 2, and 3 do not have a constant interval, but have an interval according to the bit weight. A counter for generating the select signal S is positioned at a subsequent stage of the counter for generating the X address, and is incremented by one after the counter for generating the X address outputs all the values of 0 to 3. Further, another counter for generating a Y address is positioned at a subsequent stage of the counter for generating the select signal S, and is incremented by one after the counter for generating the select signal S outputs all values of 0 to 3.
Therefore, four data in the first row in the memory 7 are respectively read out four times (according to timing of the periods t1 to t4), and are compared with the select signal S for each time. The first select signal S is set to zero, the second select signal S is set to one, the third select signal S is set to two, and the fourth select signal S is set to three. In the first comparison, the changing portion 15 selects and outputs the least significant bit among the 4-bit data from the memory 7. In the second comparison, the changing portion 15 selects and outputs the first bit among the 4-bit data from the memory 7. In the third comparison, the changing portion 15 selects and outputs the second bit among the 4-bit data from the memory 7. Finally, in the fourth comparison, the changing portion 15 selects and outputs the most significant bit among the 4-bit data from the memory 7.
In such a manner, when, for example, data at the address "0" shown in FIG. 6 is outputted from the memory 7 four times, the changing portion 15 outputs "1," "1," "1," and "1" according to the timing of the periods t1 to t4. Since the output respectively have weights 1, 2, 4, and 8, in display modes t1 to t4 in the first row shown in FIG. 14, display is made for time intervals obtained by the leftmost values corresponding to the address "0". When data at the address "1" is outputted from the memory 7 four times, the changing portion 15 outputs "0," "1," "0," and "1" according to the timing of the periods t1 to t4. Thus, in the display modes t1 to t4 in the first row shown in FIG. 14, display is made for time intervals obtained by the second values from the left corresponding to the address "1."
For data at the address "2" and at the address "3," processing identical with the above processing is carried out by the changing portion 15, the timing generating circuit 8, and so forth. In such a manner, signals corresponding to signals in the periods t1 to t4 in FIG. 13 are fed to a row electrode Y.sub.1 and column electrodes X.sub.1 to X.sub.4. As shown by the leftmost display mode in the first row in FIG. 14, a display element corresponding to the address "0" is held ON for a period of 15 unit times, a display element corresponding to the address "1" is held ON for a period of 10 unit times, and a display element corresponding to the address "2" is held ON for a period of 12 unit times.
Subsequently, the Y address fed to both the memory 7 and the row electrode control circuit 5 is set to one, and the same processing as the above processing is carried out for data at the addresses "4" to "7." Thus, in case of data as shown in FIG. 6, signals corresponding to signals in periods t5 to t8 in FIG. 13 are fed to a row electrode Y.sub.2 and column electrodes X.sub.1 to X.sub.4. The same operation is carried out with respect to Y addresses "2" and "3."
In the display unit, the ON signals are set to have four types of time intervals, and a gray image can be realized by a combination of the ON signals as shown in FIG. 15. For example, in case of display data of weight 8, an ON signal having a time interval of 8 is fed to the column electrodes X.sub.1 to X.sub.4. Alternatively, in case of display data of 7, an ON signal having a time interval of 1, an ON signal having a time interval of 2, and an ON signal having a time interval of 4 are respectively fed to the column electrodes X.sub.1 to X.sub.4.
In the display unit employing the pulse number control method, the display data must be read out from the memory 7 the number of times identical with the number of gray scale before one frame can be displayed. Hence, when an increase in the number of bits in the display data increases the number of gray scale, it is necessary to operate the memory 7 and the control circuit at a higher velocity. As a result, the increase in the number of gray scale is limited.
In the display unit employing the pulse width control method, the number of times the display data is read from the memory 7, required to display the one frame, becomes equal to the number of bits in the display data. Thus, the pulse width control method requires considerably less number of times of read than the pulse number control method. However, for a short time interval such as the period t1 or t5, it is necessary to read out the display data expressed as the number of bits per data by the number of pixels per row (for example, four bits by four pixels in case of a 16-scale image including a 4-by-4 pixel array). Consequently, it is also necessary to operate the memory 7 and the control circuit at a higher velocity, and the increase in the number of gray scale is limited.
Further, due to influences such as response velocities of drivers 2 and 3 and light emitting elements, or ripple noise in power supply voltage, it becomes difficult to, for example, realize a pulse width corresponding to a time interval of 7 by summing up the ON signals respectively having the time interval of 1, the time interval of 2, and the time interval of 4. As the number of scale is further increased, such a tendency becomes more pronunced. When the scale number is increased, a value of the display data can not easily be made proportional to brightness of the display panel because of the following reason. That is, when the number of gray scale is increased to reduce an interval of the ON signal, sometimes supply of the ON signal fails to turn ON the display element by a response rise delay time and so forth due to the influences such as response velocity of the display element. That is, at times, the value of the display data can not easily be made proportional to brightness of display.
In addition, both the control circuit in the pulse number control method and the control circuit in the pulse width control method feed the ON signals to the column electrodes and the row electrodes according to the same timing. As a result, an expensive circuit having a higher response velocity is required for both a column electrode drive circuit and a row electrode drive circuit.