In recent years the telecommunications industry has increased its demand for improved performance from current controlled oscillators (CCO). For example, when designing phase locked loops (PLL) for frequency synthesizers and clock recovery circuits, it helps to have a CCO with linear gain to allow better modeling during system design. Better modeling during system design helps avoid possible instability problems.
Additionally, it is important to reduce the CCO's power consumption and reduce the design margin. This can be achieved by designing the CCO to have low process and temperature sensitivity.
Conventional 3-stage ring oscillators of the prior art can have a wide tuning range, but the CCO gain is sensitive to process and temperature variation. The CCO gain is much higher when it works under low temperature, fast-fast (FFL) conditions than it works under high temperature, slow-slow (SSH) conditions. In order to make a conventional CCO oscillate over a certain frequency range, a much larger tuning range is required because of the process and temperature variations. Another problem with conventional CCO's is that the gain will drop, or become flat, at high frequencies, rather than increasing linearly, because of velocity saturation.
FIG. 1 illustrates a prior art circuit 7 comprising a conventional CCO fully differential inverter cell and its loading. Four pMOS transistors 9, 11, 13, 15 have their drains tied to the voltage Vdd. The gates of the transistors 9 and 15 are both tied to a voltage Vb 19. The voltabe Vb 19 is generated from a voltage Vbn 18 through a replica bias. Here, Vbn 18 is the control voltage for controlling the current Icontrol. The gate of transistor 11 is tied to the sources of the transistors 9 and 11 as well as to the output 8 of the differential outputs 10 and 8. The gate of transistor 13 is similarly tied to the sources of the transistors 13 and 15 as well as to the output 8 of the differential outputs 10 and 8. A capacitor 16 is connected between the differential outputs 10 and 8. This capacitor actually reduces the output frequency of the CCO 7, however, it is necessary for improving the jitter performance.
The nMOS transistors 12, 14 have gates supplied by current supply inputs 2 and 3 which are connected to the output of the previous stage of the inverter cell as illustrated in FIG. 9. The sources of the transistors 12, 14 are connected to the sources of the transistors 9, 11 and 13, 15, respectively. The source of the transistor 12 also leads to the differential output 8. Connected to the drains of the transistors 12, 14 is the source of another nMOS transistor 16 having its gate supplied by a voltage 18. The transistor 16 has its drain grounded.
FIG. 6 illustrates the CCO gain of the prior art circuit 7 of FIG. 1. Control current (in amps) is plotted along the x-axis while frequency (in Hertz) is plotted along the y-axis. There are separate curves for different design process corners and temperatures. The curves represent the SSH (slow-slow, high temperature), normal and FFL (fast-fast, low temperature) conditions. The curves, especially for the SSH condition tend to flatten when the control current becomes large. This is because the transistors 9, 15 enter the velocity saturation and their gm value does not continue to increase with control current.
An example of a prior art CCO design providing temperature variation compensation is presented in the paper entitled, “A 622-MHz Interpolating Ring VCO with Temperature Compensation and Jitter Analysis”, by Wing-Hong Chan, published in the IEEE International Symposium on Circuits and Systems, Jun. 9-12, 1997, Hong Kong. However, the method this paper can only provide compensation at one fixed frequency and cannot compensate for process variation. In addition, it requires many additional circuits resulting in greater power consumption, size and cost.
Another example of a prior art CCO design is presented in “Low-Jitter Process-Independent DLL and PLL Based on Self-Bias Techniques', IEEE J. Solid-State Circuits, vol. 31, No. 11, November 1996 by John G. Maneatis. However, this prior art CCO does not sufficiently extend the linear region of the CCO gain or minimize the process and temperature sensitivity.
It would therefore be desirable to provide a CCO with extended linear gain over a broad tuning range, greater stability, reduced size and power consumption and reduced sensitivity to process and temperature variation. Additionally, it would be desirable to provide a CCO with these features while maintaining a good power supply rejection ratio (PSRR).