1. Field of the Invention
The present invention is generally in the field of electrical circuits and systems. More specifically, the present invention is in the field of memory devices.
2. Background Art
In various memory devices, such as RAMs (random access memory), CAMs (content addressable memory), or other memory devices, that handle a large amount of input data, the number of inputs to the memory device need be managed and reduced to, for example, reduce problems associated with data routing when there are numerous input pins. However, the reduction of the number of inputs need be accomplished without impairing the ability of the memory device to handle a large amount of input data. Moreover, it is desirable to preserve flexibility so that various system design requirements in receiving input data can be met.
For example, if a system is capable of providing write or compare data at a high rate into a RAM or a CAM, then it is desirable to utilize the high data rate advantageously so that data can be received by the RAM or CAM at a faster pace. On the other hand, if a system is not capable of providing data at a high rate into a RAM or CAM, then it is desirable to accommodate the slower data rate as well. In this manner a system designer can utilize fewer input pins of the RAM or CAM for providing input data, or can use a more conventional data rate which requires a greater number of input pins. The capability to provide and receive data at higher rates results in speed improvement, and a reduction of input pins and reduces input/output (I/O) routing complexity in memory devices, such as RAMs and CAMs.
Thus, it is desirable to maintain flexibility to accommodate receiving data at various data rates, and to switch between a slower incoming data rate and a faster incoming data rate in various memory devices, such as RAMs, CAM, as well as other memory devices.