Reset signals may be used to initialize electrical circuits as a part of various system operations. In some cases, reset signals may be used to force a circuit into a known state for simulation or a defined state desired by a designer or a user.
A synchronous reset signal is often used to affect or reset state of flip-flops on the active edge of an associated clock signal. Thus, the synchronous reset signal should have a duration that is sufficient to be captured at the active clock edge. While a synchronous reset signal provides some immunity to glitches, unless they occur right at the active edge of an associated clock signal, it may not be very useful in power saving schemes where the clock signal is gated.
An asynchronous reset signal may be used to affect the state of flip-flops and other circuitry asynchronously, without regard to the state of the clock signal. This may be useful in high speed circuits, as the data path becomes independent of reset signal. However, an asynchronous reset signal may not offer the same level of immunity to glitches that is provided by the synchronous reset signal, contributing to spurious circuit reset operations.