Due to the large number of components in state of the art electronic circuits, most of their design and production is computer implemented. An important operation performed during design of electronic circuits is timing analysis that validates timing performance of an electronic design. For example, static timing analysis validates timing performance of a circuit design by checking possible paths for timing violations. Performing timing analysis for large electronic circuits can take significant time.
Furthermore, timing analysis is repeated multiple times for the same electronic design for various combinations of modes and corners. Semiconductor device parameters can vary with conditions such as fabrication process, operating temperature, and power supply voltage. A circuit fabricated using these processes may run slower or faster than specified due to variations in operating conditions or may even fail to function. Therefore timing analysis is performed for various operating conditions to make sure that the circuit performs as specified under these conditions. Such operating conditions for a circuit are modeled using corners that typically comprise a set of libraries characterized for process, voltage, and temperature variations.
The timing analysis of a circuit is also repeated for different operating modes, for example, normal operating mode, test mode, scan mode, reset mode and so on. For example, a circuit used in a computer operates in a stand-by mode when the computer is in a stand-by mode. Similarly, during testing phase, a circuit may be operated in a test mode. A mode is modeled using a unique set of clocks, input voltages, and timing constraints in similar operating conditions.
For performing timing analysis during implementation and sign-off of a circuit, designers may have to verify a large number of modes and corners. Each circuit design may have tens of modes and tens of corners or more. Since each mode should be verified for each corner condition, the total number of scenarios for which the design is verified is the product of the number of modes and number of corners. This results in the timing analysis being performed a large number of times resulting in high costs.
One way to handle the large number of scenarios resulting from multiple modes and corners is to merge the modes into a smaller set, for example, a single mode. Since timing analysis is performed for the combination of modes and corners, reduction in the number of modes reduces the total combinations of modes and corners by a much larger number. For example, if there are 10 modes and 10 corners, the total number of scenarios is 10×10=100. However if the 10 modes were combined to a single mode, the total number of scenarios is reduced to 1×10=10 which is a 90% reduction in the number of scenarios to be verified.
Conventionally, modes are merged manually by designers. However, due to the complexity of constraints associated with circuit designs, the generation of merged modes is difficult to handle manually. Since the number of timing constraints for a given netlist can be large, manual merging of modes can be error prone and have prohibitive costs. For example, a circuit could have millions of constraints and manually determining which modes can be merged together and then merging them may not be practically feasible.