This invention relates generally to computer architectures and more particularly to memory and busing architectures within computers.
Computers are known to include a central processing unit, system memory, a memory controller, a chip set, video graphics circuitry, interconnecting buses, and peripheral ports. The peripheral ports enable the central processing unit and/or other components, to communicate with peripheral devices such as monitors, printers, external memory, etc.
In most computer systems, a computer will include cache memory to more effectively access larger memory, such as a system memory hard drive. As is known, cache memory is relatively small in comparison to system memory and can be accessed by the central processing unit much more quickly than the system memory. As such, when the central processing unit has a read and/or write function to process pertaining to a particular data element stored in the system memory, the data element, and related data elements, are retrieved from system memory and provided to the cache memory. As is also known, the related data elements may be in the same memory line (e.g., 128 bytes) as the data element, or in the same memory block (e.g., several memory lines) as the data element.
The rationale for retrieving a line or several lines of memory is based on the assumption that the central processing unit is processing sequentially related operations that have data elements stored in groupings (i.e., in the same memory line or group of memory lines). For example, video graphics data is often stored in a linear or tiled manner, wherein the memory locations correspond to pixel locations of the display. As such, filling the cache with the needed data element and the related data elements requires only one read operation from the system memory, while the central processing unit may perform multiple reads and/or writes of data in the cache. Thus, memory access is much more efficient. Note that the retrieved data elements may be related temporally or spatially.
As is also known, data elements are bused in a pipeline manner wherein, for a given transaction, i.e., a read and/or write of data, the transaction includes an arbitration phase, a request phase, an error phase, a response phase, and a data phase. Each of these phases may be several clock cycles in length and their length varies depending on the busyness of the bus. As such, some data elements may be processed quickly while others are delayed or preempted due to higher priority data traffic. As is known, the error phase is used to determine whether a particular transaction is being preempted for a higher priority transaction. Thus, additional processing is required due to the varying processing lengths of transactions.
In some computer systems, there are multiple processors, where each processor has its own cache, which may include two levels of cache. The first level cache being smaller and more readily accessible than the second level. Thus, in such multiprocessor environments, when a processor is not utilizing its cache, it remains idle. Conversely, when a processor is processing a significant amount of data its cache may be too small, thus forcing the data to be thrashed between cache memory and system memory, which is inefficient. As such, the cache memory in a multiprocessor environment is not used as effectively as possible.
Therefore, a need exists for a method and apparatus that more efficiently utilizes cache memory and more efficiently buses data within a computer system.