It is well known in the art of integrated circuits that manufacturing processes are imperfect—on each wafer some, but not all, integrated circuits function fully. It is also known that defects tend to occur in clusters. Therefore, for circuits having multiple, large, functional units, there will be a substantial population of manufactured integrated circuits where one functional unit is defective, or even a small portion of a functional unit is defective, but other functional units on the same integrated circuit function properly.
The probability that an integrated circuit will have one or more defects increases as the size of the integrated circuit increases. Further, the cost of fabrication increases as integrated circuit size increases. A high performance single or multiple-processor integrated circuit can be quite large. It is therefore desirable to find ways of selling at least some of those integrated circuits that contain one or a few defects.
Typically, integrated circuits are tested before they are packaged. Those processor circuits that have defective units are often discarded before packaging; their fabrication cost is wasted but further investment in them is prevented.
Solutions that permit selling partially-defective integrated circuits are known for memory integrated circuits. For example, memory integrated circuits often have spare blocks of memory that can be substituted for defective sections of the circuit. Before spare blocks became common, memory circuits were occasionally packaged with a high-order address bit wirebonded to a constant, then sold as memories of half capacity, with defective sections of the chip disabled. Wirebonding a bondpad to a constant to configure an integrated circuit is known as a bonding option; bonding options may also be implemented through a package trace where a particular package lead is tied to a particular logic level. Bonding the high-order address bit to power or ground permitted sale of packaged circuits having partial capacity, with the same circuit pinout for defects in either the high or low half of the memory array.
Modern integrated processor circuits of high performance are fabricated with at least some cache memory on the processor integrated circuit. Some of these circuits have been designed with bonding options such that a portion of cache may be disabled; a technique that permits product differentiation as well as sale of partially defective circuits. Some of these circuits also have spare blocks of memory that can be substituted for defective sections of cache.
It is known that some available processors have multiples of certain functional units. For example, a processor integrated circuit may have more than one integer execution unit, or more than one floating point execution unit. These units are referenced herein as redundant units. Historically, processors with one defective integer unit, or one defective floating point unit, are typically discarded. Similarly, if multiple processor integrated circuits are sold with a defect in an integer unit or floating point unit of one processor, the entire defective processor is disabled.
It is also known that some processors have functional elements that enhance performance but which are not essential to processor operation. For example, deletion of a branch prediction unit, speculative prefetch unit, or a speculative execution unit may degrade but not kill performance. These functional elements are referenced herein as performance-enhancing units.
Branch prediction and speculative execution are common techniques for minimizing the impact of conditional branch instructions on processor performance.
Branch prediction involves using dedicated hardware to guess whether conditional branches will be taken or not taken. This may be done by tracking recent results of particular conditional branch instructions, and predicting that a particular branch instruction will cause a branch if it caused a branch when it was last executed.
Speculative execution involves a machine's beginning execution of instructions after a conditional branch is encountered in an instruction stream when it is not yet known if the instructions are among those that should be executed. Typically, speculatively executed instruction results are not made permanent until it is determined whether they should have been executed. If instructions are speculatively executed, and it is determined that they should not have been executed, their results are discarded.
Integrated circuit fabrication processes are known that are capable of producing read-only memory cells that can be programmed after wafer fabrication is complete. These processes have been used to create programmable memory devices, programmable logic devices, and other circuits. Processes of this type that use fusible links or laser-burnable links are known. Other processes are known that create programmable cells that are programmed by tunneling charge onto a charge-trapping layer, such as a floating polysilicon gate or an oxide-nitride boundary, in the gate region of a device.
It would be desirable to recover some revenue by using post-fabrication programmable cells to selectively disable defective functional units on processors that have multiples of functional units of those types, and selling the partially defective devices as lower performance processors.
It is also known that different application programs have different processor requirements. For example, some programs have much greater floating point computational requirements than others. Similarly, the percentage of branch instructions may also vary significantly.
Built In Self-Test (BIST) is a design technique wherein circuitry of a functional unit is designed, and some additional circuitry added to the unit, such that the unit can effectively test itself.