1. Field of the Invention
The present invention relates to a resistive memory device having a storage element whose data storage state changes based on resistance change dependent on the application voltage, and an operating method thereof.
2. Description of the Related Art
The resistive memory device is being actively used in resent years because it does not demand the electrical power for holding stored data. The floating gate (FG) flash memory, which is mainly employed as the memory device currently, has a disadvantage of low data writing speed. In the FG flash memory, not only that the data writing speed itself is low, but also that verify operation is needed in data writing. Therefore, the total writing time is long.
For resolution of this disadvantage, there are methods in which the verify operation is improved to shorten the total writing time. As one of the methods, there has been proposed a technique in which so-called direct verify operation is applied to a resistive memory device, which has higher writing speed (refer to e.g. Japanese Patent Laid-open No. 2007-133930 (hereinafter, Patent Document 1)).
In normal verify operation, for a memory cell, the bit line is pre-charged after the end of a recording process (program), and thereafter verify readout (detection) operation is carried out. A series of operation of repeating the verify operation composed of the program and the detection until the desired resistance change is obtained is carried out. This series of operation will be referred to as the “writing verify operation” if it is for writing, and will be referred to as the “erasing verify operation” if it is for erasing. Hereinafter, the term “recording process” or “program” will refer to recording (program) of data of “1” or “0” no matter whether it is for writing (changing any storage logic from the initial state) or for erasing (returning the storage logic to the initial state).
In contrast, in the direct verify operation, after the end of a recording process, verify readout (detection) is performed by directly using the charge left in the bit line at this time to thereby shorten the total time. In the direct verify operation, the total writing operation time can be shortened corresponding to the absence of pre-charge for verify readout.
The writing verify operation described in Patent Document 1 will be described below.
FIG. 1 shows how the bit line voltage (hereinafter, referred to as the BL voltage) changes in a recording (writing) process for writing and the subsequent readout (detection) process when the writing verify operation is carried out by the method described in Patent Document 1.
The potential change of the bit line shown in FIG. 1 will be described below.
By the writing operation, the BL voltage changes from a common potential Vcommon to a writing voltage Vwrite. When the writing by this writing operation has succeeded, the resistance of the variable resistance element has become low. Thus, when the supply of the writing voltage to the bit line is stopped, the BL voltage changes to a certain sufficiently-low potential corresponding to the resistance of the variable resistance element.
On the other hand, when the writing has failed, the resistance of the variable resistance element has not become sufficiently-low but is high. Thus, the BL voltage does not much decrease although the supply of the writing voltage is stopped.
If a reference potential Vref-write for writing is set between these potentials in advance, the output dependent on whether the writing has resulted in success or failure is obtained by a sense amplifier, and thus whether the writing has been correctly performed can be checked.
FIG. 2 shows how the BL voltage changes in a recording (erasing) process for erasing and the subsequent readout (detection) process when the erasing verify operation is carried out by the method described in Patent Document 1.
In the method of the related art, the so-called pre-charge process, in which voltage is applied to the bit line BL in order to carry out the verify operation, is carried out in the erasing process, in which an erasing voltage Verase is applied to the bit line BL for erasing.
The potential change of the bit line BL dependent on the state as to the success or failure of erasing is different from the potential change in the writing verify operation.
Specifically, after the BL voltage is lowered from the common potential Vcommon to the erasing voltage Verase in the erasing process, if the erasing has succeeded, the resistance of the variable resistance element has changed to high resistance, and thus the BL voltage does not much change although the erasing signal is turned off.
If the erasing has failed, the resistance of the variable resistance element has not become sufficiently-high but is low, and therefore the BL voltage rises up to a certain potential.
If a reference potential Vref-erase for erasing is set in advance between these two potentials taken as the value of the BL voltage, the output dependent on the success or failure of the erasing is obtained by the sense amplifier. Thus, whether the erasing has been correctly performed can be checked.
By using the process in which voltage is applied to the bit line BL to perform writing or erasing for the variable resistance element in the selected cell also as the pre-charge process for the verify operation in this manner, the time demanded for the writing verify operation and erasing operation is shortened.