A vertical field-effect transistor (FET) has a channel perpendicular to the substrate surface, as opposed to being situated along the plane of the surface of the substrate. By using this design, it is possible to increase packing density. That is, by having the channel perpendicular to the substrate surface, vertical FETs improve the scaling limit beyond planar finFETs.
However, vertical FETs are still severely challenged past the 7 nm node due to high aspect ratios, Vmax limits, and material thickness not scaling well. For example, insulator material and shared contacts formed between gate material of adjacent vertical FETs make it very difficult to scale the devices beyond the 7 nm node, basically due to material thicknesses, leakage concerns, breakdown voltage, decreased resistances and capacitance, etc. Accordingly, these constraints make it very difficult to decrease gate pitch in current vertical FET designs.