1. Field of the Invention
This invention relates to a method of forming very narrow electrically conductive lines and narrow spacing between such lines on printed wiring boards (PWBs).
2. Brief Description of the Prior Art
The continual decrease in the size of electronic components has resulted in a continuing effort to obtain finer circuit lines and spacing between the lines on printed wiring boards. In the manufacture of certain types of printed wiring board systems or modules, particularly those systems having a pair of printed wiring boards with a core therebetween, sequential copper plating steps are required. Generally, plating first takes place on the initial printed wiring boards with the build-up of copper on the board surfaces and vias or holes through the board electrically interconnecting the two major surfaces. That board and a second board on which a similar plating operation has taken place are then bonded to a core layer positioned between the two boards. The module is plated with copper including vias or holes through the two boards and the core to electrically interconnect the two initial boards. These steps involve the drilling of holes in one or both boards, plating of those holes, bonding of the boards to the core layer to form a module, then drilling additional holes through the entire module with subsequent plating of the additional holes. A result of this sequential plating requirement is that there is a build-up of the plating material on the surfaces of the initial boards from the plural plating steps. This large build-up of copper provides a problem in obtaining fine lines of copper and fine spaces between the copper lines. The final etching of the surface copper is dependent upon the etch factor of the etchant chemistry and the copper thickness on the surface to be etched. A consequence of this problem has been relatively poor yields and a large minimum line and space width.
Attempts have been made to improve the etch factor through the use of chemical additives or by minimizing the amount of copper plated on the board surfaces. While both of these approaches are valid and have shown improvement in the ability to reduce line widths, they have limited applications. Even with a greatly improved etch factor due to etchant chemistry, the surface copper thickness will dominate line widths. It is therefore apparent that other approaches are necessary in order to provide line widths and spacing between lines of reduced dimensions while improving the yields.