FIG. 1 illustrates a conventional block diagram of a television (TV) system. The TV system mainly includes a TV controller 100, dynamic random access memory (DRAM) 120, and a cathode ray tube (CRT) 140. The TV controller 100 is capable of receiving a plurality of types of video sources 110, including signals of National Television Standards Committee (NTSC) TV, Phase Alternation Line (PAL) TV, and video signals of super extended graphics array (SXGA)/extended graphics array (XGA)/video graphics array (VGA). The DRAM 120 is necessarily required to store frame data generated by the video sources 110 in FIG. 1. The TV controller 100 then properly displays frame data in the DRAM 120 to the CRT 140. The CRT 140 displays the video signal according to vertical synchronous (VSYNC) and horizontal synchronous (HSYNC) signals (not shown in FIG. 1) generated by the TV controller 100.
However, the DRAM 120 increases the total manufacturing cost of the display system. Further, the CRT 140 cannot change VSYNC and HSYNC signals dramatically. The VSYNC and HSYNC signals can only vary their frequencies under vendor's specific specification, such as the specification of VSYNC signal within 5% and HSYNC signal within 2%. Otherwise the CRT 140 will be seriously damaged or the CRT video display is seriously distorted on the CRT 140. The VSYNC signal is 60 Hz and 50 Hz for NTSC and PAL standards, respectively. SXVGA/XGA/VGA video signals may support a plurality of kinds of VSYNC operation frequencies, preferably ranging from 60 Hz to 85 Hz.
In the prior art, the TV controller 100 separates the input frame data from the output frame data by buffering frame data into the DRAM 120, so the output video signals composed of the output frame data can merely be controlled under approximate fixed frequencies of VSYNC and HSYNC signals to stably display the video signals. Specifically, when a different video source is selected into the TV controller 100 or when the display mode is changed, the TV controller 100 may distort video signals on the CRT 140 or even damage the CRT 140 due to the VSYNC and HSYNC signal variations.
FIG. 2 shows a block diagram of the conventional TV controller in FIG. 1. The TV controller 100 comprises an output phase-locked loop (PLL) 200 and a horizontal and vertical (HV) generator 220. The output PLL 200 receives a fixed input clock 210 and then outputs Output_CLK signal. The HV generator 220 generates VSYNC and HSYNC signals according to Output_CLK signal. The conventional display controller processes image frames based on pixels. Persons skilled in the art considers CRT TV cannot be implemented without the DRAM 120 since the output VSYNC signal must change significantly to cause the CRT to be seriously damaged or cause the CRT video display to be seriously distorted when the input TV video source is changed. It's unacceptable by the manufactures of the display systems, and especially damaging CRT TV is too dangerous.
As aforementioned, either CRT or LCD controller, of which conventional PLL receives a fixed input clock, cannot afford the demand of different video sources and DRAM increases the manufacturing cost of display systems. Consequently, there is a need to develop a display controller to provide the display system with rapid adjustment of VSYNC and HSYNC signals for reducing the cost and improving stability thereof.