A gate-array type integrated circuit is a semiconductor device which has basic circuit elements arranged in a pattern on a chip (the "master slice"). The circuit elements can be interconnected during manufacture to achieve a desired functionality. Thus, a gate array can be customized.
Circuit elements typically found in a gate array include storage elements, such as latches, and logic elements, such as AND gates. A "path" is defined as a signal transmission passageway between and including circuit elements. There are various types of paths. For example, there are closed paths between storage elements; open paths from a storage element to an output terminal or from an input terminal to a storage element; and through paths from an input terminal to an output terminal. The "input" and "output" terminals are external terminals (or "leads") of the semiconductor circuit device.
FIG. 11 illustrates sample paths (1) through (4). For example, path (1) includes latches 901 and 902 and gates 909 and 910. Wire portions 917, 918 and 919 connect these elements as illustrated. Each element and wire has an inherent capacitance, which causes a propagation delay as the signal moves from latch 901 to latch 902. These delays are illustrated in the bar graphs of FIGS. 15 and 16. The portion of the propagation delay attributable to each particular element or wire portion is designated in FIGS. 15 and 16 by boxes bearing the reference numeral of the particular element or wire portion.
As shown in FIG. 11, latches 901 and 902 receive timing signals T.sub.0 and T.sub.1, respectively. It is essential that the signal propagate from latch 901 to latch 902 during the interval between timing signals (the "delay reference value"). Otherwise, the signal will not have reached latch 902 by the time latch 902 is strobbed by timing signal T.sub.1. The delay reference value is shown in FIGS. 15 and 16 by a broken line.
As can be seen in FIG. 15, some paths, such as path (4), have propagation delays which exceed the delay reference value. Others, such as path (3), have propagation delays which are less than the delay reference value. As is known, the current between elements can be varied to adjust the propagation delay attributable to the capacitive effects of the wire portions. Specifically, the greater the current, the shorter the propagation delay.
To control flow of current between elements, each element includes at its output an emitter-follower circuit, comprised of a plurality of resistors and transistors. As explained in Japanese Post-Examination Application No. 64-4340, these resistors and transistors are selectively coupled to obtain an emitter-follower circuit having the desired current characteristic. By increasing current, the propagation delays can be shortened, so that the aggregated delays for a given path do not exceed the delay reference value.
The conventional method of varying an emitter-follower current in accordance with the capacitance of a load circuit will be described with reference to FIGS. 11, 15 and 16. As explained above, FIG. 15 shows the delays in the paths (1)-(4) of FIG. 11 before emitter-follower current is adjusted. The delays illustrated in FIG. 15 include delays in elements and delays on signal lines. FIG. 16 shows the delays after the emitter-follower current has been adjusted in accordance with conventional techniques.
For example, consider paths (1) and (2) of FIG. 11. Both paths (1) and (2) have the same number of elements. However, signal line 921 of path (2) is longer than signal lines 917-919 of path (1). Effective capacitance (that is, delay) caused by line 921 is larger than that caused by lines 917-919. Thus, the overall delay of path (2) is greater than the delay of path (1), as shown by the bar graphs of FIG. 15. By increasing the emitter-follower current of a logic element 911, the delay can be shortened, as shown in FIG. 16.
In the conventional method, such an adjustment is conducted to all long signal lines, which sometimes causes an unnecessary increase of power consumption. For example, (3) of FIG. 11 includes a long line 923. However, because path (3) has few elements, its overall delay is less than the delay reference time, as shown in FIG. 3. Nevertheless, in accordance with conventional practice, the emitter-follower current of storage element 905 is increased, thus reducing the overall delay of path (3) further below the delay reference time (as shown in FIG. 16), and resulting in additional unnecessary power consumption.
Path (4) of FIG. 11 includes three elements 914-916 and three short lines 925-928. Because signal lines 925, 926 and 928 are short, their effective capacitances are small. Increasing the emitter-follower current of elements 915 cannot sufficiently reduce the delay of line 927, and it is impracticable to reduce delay on short lines 925, 926 and 928. Therefore, even after adjustment, the delay of path (4) exceeds the delay reference value.
Thus, the conventional technique simply adjusts the emitter-follower current of each element in accordance with the capacitance of the load circuit associated with that element. When the capacitance of the load circuit is large, the element's emitter-follower current is increased, even through the element's path may already have a sufficiently short delay. On the other hand, when the capacitance of the load circuit is small, the current value is not altered, even though the element may be part of a path which has an aggregate delay that exceeds the delay reference value.
As described above, the conventional technique reduces the delay between the elements having large capacitive loads. Therefore, the delay of certain individual elements may be reduced. The conventional technique is not effective, however, for reducing the delay in paths which have a larger number of elements connected by short signal lines. Therefore, the speed of the whole semiconductor circuit is limited by the path having the longest delay, and thus limiting the overall speed of the integrated circuit.
Further, the conventional method does not reduce the delays attributable to the elements, themselves, as opposed to the delay attributable to the lines between elements. Further, the conventional method does not minimize power consumption.