The geometries in integrated circuits have scaled to smaller and smaller dimensions. As the geometries have scaled the alignment tolerance of a pattern level to underlying pattern levels has also become smaller and more critical.
In conventional integrated circuit flows, when a pattern such as active, gate, contact, metal, and via is formed on the integrated circuit wafer, alignment marks for alignment in the x-direction and alignment marks for alignment in the y-direction are formed on each of these layers so that subsequent patterns may be aligned using these alignment marks.
Conventional photolithographic alignment is illustrated in FIGS. 1-3. FIG. 1 shows an integrated circuit wafer with multiple integrated circuit chip 20 patterns formed on the wafer. For example, integrated circuit pattern 20 may be the active pattern etched into the integrated circuit wafer. When the active geometries are etched into the integrated circuit wafer active alignment marks 22, 24, 26, and 28 are also etched into the integrated circuit wafer. Typically the alignment marks consist of vertical 40 and horizontal 42 grids as shown in FIG. 3. When another integrated circuit pattern is to be printed on the integrated circuit wafer, it is critical for the new pattern geometries to be properly aligned to the active geometries already etched into the integrated circuit wafer. The reticle 30 illustrated in FIG. 2 may be an integrated circuit gate reticle, an integrated circuit contact reticle, or an integrated circuit implant pattern reticle. A gate reticle is used for illustration. The gate reticle is loaded into a photolithography stepper and the stepper aligns the gate alignment marks 32, 34, 36, and 38 that are on the gate reticle to the active alignment marks 22,24,26,28 that are etched in the integrated circuit wafer. The stepper aligns the gate reticle alignment marks in the x and y directions to the underlying active pattern alignment marks for each of the integrated circuit chips on the wafer. Vertical alignment grids 40 are used for horizontal alignment. Horizontal alignment grids 42 are used for vertical alignment.
An alignment tree for a typical integrated circuit aligns all photoresist pattern alignment marks prior to the contact level to the active x and y alignment marks, aligns the contact pattern alignment marks to the gate x and y alignment marks, aligns the first interconnect pattern alignment marks to the contact x and y alignment marks, aligns via pattern alignment marks to the underlying interconnect x and y alignment marks and aligns interconnect pattern alignment marks to the underlying via x and y alignment marks.
In addition, in order to pattern geometries with a pitch below about 100 nm while using 193 nm lithography, it has become necessary to use double pattern technology (DPT). Using DPT, one interconnect pattern with a pitch of about 100 nm may be split into two patterns each with a pitch of about 200 nm. The interconnect pattern with a 100 nm pitch may then be formed on an integrated circuit wafer by printing both patterns with the looser pitch into the same layer of photoresist.