This invention relates generally to field effect transistors (FETs), and more particularly the invention relates to use of a stressed capping layer to enhance the performance of complementary metal-oxide-semiconductor (CMOS) integrated-circuit (IC) devices.
CMOS IC devices comprise n-channel (NMOS) and p-channel (PMOS) transistors which toggle on-off in a complementary fashion in response to input voltage signals. The transistors can have a planar structure, in which the surfaces of the source, channel, and drain regions are substantially located in a single plane, as in a conventional bulk-silicon (bulk-Si) MOSFET or silicon-on-insulator (SOI) MOSFET, or the transistors can have a vertical structure such as in the double gate FinFET structure as described in U.S. Pat. No. 6,413,802.
Transistor performance depends on mobile carrier (hole or electron) mobility. Strained-silicon technologies have been widely investigated to enhance the performance of CMOS devices. In particular, strain induced by the use of a stressed SiNx capping layer is advantageous because of its process simplicity and its extendibility from bulk-Si to SOI MOSFETs. However, it is difficult to enhance the performance of both n-channel and p-channel devices simultaneously, because tensile stress is required in the n-channel MOSFET channel, whereas uniaxial compressive stress is required in the p-channel MOSFET channel, to enhance carrier mobility.
The present invention is directed to the fabrication of a CMOS device in which the performance of both n-channel and p-channel transistors can be enhanced with a common capping layer and to the resulting structure.