Recently, non-volatile semiconductor flash memories have come into wide use as data storage memories with excellent portability. The per-bit price of those flash memories has been rapidly dropping just from their miniaturization. This per-bit price reduction has actually been achieved by the element structure improvement or employment of multi-bit storage systems with respect to those flash memories.
Typical methods for forming memory arrays of large capacity flash memories used for files are NAND type and AND type. In the NAND type memory, memory cells are connected serially. In the AND type memory, memory cells are connected in parallel. The AND type memory in which memory cells are disposed in parallel is usually considered to be suitable for multi-bit storage operations, since it enables controlling of the number of electrons stored in a floating gate. Additionally, the AND type memory employs a hot electron writing method, so that its writing is fast. The NAND type is disclosed in “IEEE International Electron Devices Meeting” (pp. 775-778, 2000)” by F. Arai et al., while the AND type is disclosed in “IEEE International Electron Devices Meeting (pp. 29-32, 2001)” by T. Kobayashi et al.
The official gazette of JP-A 156275/2001 illustrates a non-volatile memory technique that achieves both requirements of an array configuration in which memory cells are connected in parallel and a small memory cell region. This gazette further illustrates how to use each inversion layer formed on a semiconductor substrate located under an assist gate as a line. Also illustrated by the official gazette of JP-A No.2001-326288 is a technique for configuring a memory cell array at narrow word line pitches to achieve high density disposition of memory cells.
As described above, the AND type flash memory, which employs the hot electron writing technique, is fast in writing. Because the hot electron writing method employs source side injection, the method is also considered to be suitable for simultaneous writing in many memory cells. Additionally, because memory cells in an array are connected in parallel, each memory cell is not affected by the information stored in other adjacent memory cells so easily. This is why the AND type flash memory is also considered to be suitable for multi-bit storage per cell.
In spite of such advantages, the AND type flash memory continues to present difficulties. Because the AND type flash memory has an array structure in which diffusion layers are disposed in parallel, it is difficult to reduce the line pitches that are parallel to data lines due to the spread of the diffusion layers or existence of isolation regions. To solve this problem, a method for using inversion layers formed under the electrodes disposed in parallel to the data lines as local data lines may enable the subject AND type flash memory to operate without diffusion layers to be formed by impurity injection. This method is illustrated in the official gazette of JP-A No. 156275/2001.
However, each inversion layer usually has a resistance higher than that of the diffusion layer formed by means of high density impurity injection into the object semiconductor substrate. This is why the local data line resistance is different among places in the memory array, so that as the voltage falls, the potential to be applied to each target memory cell changes and the writing characteristic differs among memory cells significantly. This problem is accentuated as local data lines become longer. Another problem to arise from the employment of the above described memory structure is that if the flash memory is structured so that local data lines are connected to a global data line at a short distance through a switch simply, the number of memory cells per local data line is reduced and the area penalty of a selected transistor portion increases.