1. Field of the Invention
The present invention generally relates to floating point units and, more particularly, to a floating point unit having an alternate, or fast, mode of operation which reduces pipeline stalls by issuing instructions regardless of the state of the previously issued instruction.
2. Description of Related Art
Pipelining is a commonly practiced technique by which processing speed is increased by starting the execution of a next instruction sequence before a previous instruction sequence is completed. As the instructions within a pipe are at various stages of execution, correcting an error, commonly referred to as an exception, which occurs during the execution of a pipelined instruction can prove complicated. Accordingly, devices which use piplining are typically equipped to resolve exceptions in a manner which will minimize disruption to instructions flowing through the pipe.
An instruction execution pipeline of a processor typically includes instruction fetch, instruction decode, address calculation, execution and writeback stages. While both integer and floating point instructions are initially handled by the instruction execution pipeline, after completing the address calculation stage, floating point instructions are issued to a floating point unit (FPU) for the execution and writeback stages.
If the instruction execution pipeline has a floating point instruction in the pipe, the instruction will not be issued to the FPU until the previously issued floating point instruction has been checked for error. By delaying issuance of the floating point instruction, in the event that an exception occurs during execution of the previous floating point instruction, the FPU will be able to precisely identify and resolve the exception.
While such a technique greatly simplifies the task of repairing the instruction execution pipeline, it often causes stalls in the flow of instructions through the pipe. More specifically, the address calculation stage will not issue a floating point instruction to the FPU until it is determined that the prior floating point instruction will not generate an exception. Thus, the address calculation stage waits to issue a next floating point instruction until after execution of the prior floating point instruction is complete. However, execution of most floating point instructions require more than one clock cycle. As a result, therefore, the floating point instruction stalls in the address calculation stage while waiting for the prior floating point instruction to finish.
Thus, it can be readily seen from the foregoing that it would be desirable to provide a method of issuing floating point instructions in a manner which reduces stalling of the instruction execution pipeline and a processor uniquely configured to permit operation of the FPU in plural modes. It is, therefore, the object of this invention to provide such a method and processor.