1. Field of the Invention
The present invention relates to a parallel operational processing device, and particularly to a construction of a parallel operational processing device having a semiconductor memory and an ALU (arithmetic and logic unit) integrated together.
2. Description of the Background Art
In a field of portable equipments and in application of image processing, it has been recently demanded, due to improved performances, to process a large amount of audio or video data at a higher speed. For processing a large amount of data, a dedicated DSP (Digital Signal Processor) is generally used in many cases. When the dedicated DSP is used, hardware thereof is fixedly set, and a data bit width and processing contents are restricted. For flexibly accommodating for various applications, it is now required to execute such processing with a programmable processor that can change its functions through software. Particularly, in view of reduction in size, it is important in such a data processing system to achieve fast processing with a small area and low power dissipation.
In the processing of audio and image data, a plurality of sets of data are frequently subject to the same arithmetic or logic operation. For such a processing application, therefore, SIMD (Single Instruction Stream Multiple Data Stream) processor is often used. In such SIMD processor, processor elements each constructed by a register file and an ALU are arranged in parallel, and are operated in parallel by the same instruction. These processor elements in parallel are 256 in number, enabling parallel operational processing on 256 sets of data, as disclosed in Reference 1 (Japanese Patent Laying-Open No. 2003-186854).
In the SIMD processor, each processor element stores multi-bit data in a register file. The ALU receives corresponding multi-bit data from a register in the file, and executes operational processing. The result of the operational processing is stored back into a register of the corresponding register file. Therefore, the bit width of the operation data to be processed depends on a bit width of the ALU or register. As disclosed in Reference 1, the change in bit width of the operation data can be handled by changing the number of the registers used in the operation in the register file. However, when 16-bit operation data is to be stored using, e.g., an 8-bit register, it is necessary to set an upper-bit register and a low-bit register, which in turn are successively switched for performing an operational processing. Therefore, when multiplication processing is performed according to a Booth's algorithm by obtaining a partial product and then adding the partial products to obtain a final product, such a problem arises that switching between the registers is extremely complicated for aligning digit positions of the operation data.
Also, the processing procedure must be changed depending on switching and non-switching of the registers. Accordingly, the processing procedure must be changed according to the bit width of the operation data, and it is impossible to deal with the change in bit width with flexibility.
The SIMD processor performs the parallel arithmetic or logic operation on multi-bit data, and the ALU is a multi-bit ALU and therefore requires a large layout area, which impedes reduction in size.
For overcoming such problem of the SIMD processor as described above, the group of the inventors has already proposed a parallel operational processing device achieving a fast arithmetic/logic operation (e.g., by Japanese Patent Application No. 2004-171658 and Japanese Patent Application No. 2005-143109 (U.S. Ser. No. 11/148,369)), the contents of which are incorporated herein by reference. The parallel operational processing device has a basic construction in which a memory cell array is divided into a plurality of entries, and one-bit ALU is arranged corresponding to each entry. Each entry stores operation data. Each ALU performs arithmetic or logic operation in bit serial manner. For example, data bits are read from corresponding entries in memory cell arrays that are placed on the opposite sides of the ALUs, and are transferred to the corresponding ALU, which in turn execute the operation on the received data bits and stores the result of operation in a predetermined entry.
The arithmetic/logic operation is performed on multiple words in bit serial manner (word parallel and bit serial manner). Therefore, an operation on each data item requires much time, but fast processing can be achieved by increasing the number of entries and increasing the degree of parallelism. For example, in an operation environment requiring one machine cycle for each of read, write and operational processings, one-bit arithmetic/logic operation requires three machine cycles. Therefore, the processing of 8-bit data requires twenty-four (=3·8) machine cycles. However, when the entries are provided, e.g., 1024 in number, operation on 1024 sets of data can be completed in twenty-four machine cycles. The operation data is generally 32 or 64 bits in bit width. Therefore, fast operations can be achieved by increasing the number of entries.
Since the arithmetic/logic operation is performed in a bit serial manner, the change in bit width of the operation data can be accommodated for by changing an accessing address range of the entry. The change in processing procedure such as register switching is not required, and the change in bit width of the operation data can be easily made.
The ALU is a one-bit ALU, and can have a small layout area. When bit lines of a memory cell array are used as entries, the ALUs can be arranged corresponding to the entries, respectively, and it is possible to achieve the parallel operational processing device having a small layout area and an extremely high operation parallelism.
For further increasing the operation parallelism, it is necessary to arrange more efficiently the ALUs and peripheral circuitry of the memory cell array. However, a region where the ALUs and the peripheral circuits are determined depends on a pitch of memory cells. Since a layout rule for the memory cell array and the pitch of memory cells are set in advance, further improvement is required for efficiently arranging the ALUs and the peripheral circuitry with a layout area reduced further.
The memory cell array is formed using, e.g., an SRAM (Static Random Access Memory) not requiring refreshing. Since the arithmetic/logic operation is performed on data in bit serial manner, when read modify operation is executed in which the reading of data and the writing of an operation result are performed in one cycle, in order to speed up the operational processing, the operation frequency of the SRAM that performs reading and writing of data in one machine cycle becomes higher than that of the ALU. Consequently, the operation frequency of the SRAM limits the operation speed of the parallel operational processing device, and therefore the operating manner of the SRAM must be further considered for achieving faster arithmetic/logic operations.
Further, a higher operation frequency increases power consumption. For increasing the operation speed, it is necessary to increase layout area of the elements for increasing a current driving capability, resulting in an increased power consumption. Further, the number of entries must be increased for increasing the parallelism degree of operations. In such case, the circuits operating in parallel increase in number, and the current consumption increases. Therefore, further devising is required also in view of the above for increasing the degree of operation parallelism and the operation speed without increasing the power consumption.