The invention relates to planarization of a semiconductor wafer by polishing the wafer with a polishing pad and a polishing fluid.
An integrated circuit comprises many semiconductor transistors that are electrically connected to one another by circuit interconnects constructed as tiny metal lines. The metal lines transmit electrical signals that operate the transistors. The transistors and circuit interconnects are of miniature size, and are constructed according to semiconductor manufacturing processes that involve formation of the transistors and circuit interconnects by depositing or growing different semiconductor materials on a wafer of silicon, i.e., a semiconductor wafer.
A semiconductor wafer is adapted for manufacture thereon of many circuit interconnects arranged according to a pattern. Circuit interconnects are constructed on a semiconductor wafer, by depositing a dielectric layer on an underlying silicon wafer, followed by recessing tiny trenches in the surface of the dielectric layer, the trenches being arranged in a pattern, followed by applying a known barrier film on the dielectric layer, followed by depositing a layer of metal onto the underlying barrier film and dielectric layer to assure that the trenches are filled with metal. A process known as chemical mechanical planarization, CMP, is performed with a polishing pad and a polishing fluid to remove the layer of metal and the barrier film from the underlying dielectric layer, and to provide a polished surface that is smooth and planar. Thus, the process of CMP is often described as a method of polishing a semiconductor substrate, or as a method of planarizing a semiconductor substrate.
An aim of the process of CMP is to polish the metal in the trenches to a height that is substantially the same height as that of the smooth, planar polished surface. The polished metal in the trenches provides the circuit interconnects. The dielectric layer with the circuit interconnects provides a substrate on which successive dielectric layers are constructed. The successive dielectric layers have additional circuit interconnects to provide successive layers of circuit interconnects for integrated circuits that are constructed in large numbers on the patterned wafer.
Planarizing a semiconductor substrate by CMP is performed with a polishing pad and a polishing fluid, which together remove material from the surface of the substrate. The polishing pad rubs against the surface to remove material by abrasion. Simultaneously, the polishing fluid is dispensed at an interface of the polishing pad and the substrate. The polishing fluid chemically reacts with the surface, and dissolves material that results from chemical reaction of the surface with the polishing fluid. Thus, material is removed from the surface by both mechanical abrasion and chemical reaction.
The surface has a surface topography with high topography features, i.e., high spots, and low topography features, i.e., low spots. The wafer is planarized, by CMP polishing of the surface with a polishing pad and a polishing fluid, which removes material from the topography features, until the topography features become substantially the same height. However, the polishing fluid reacts chemically with both the high spots and the low spots, and removes material from both of them. Thus, polishing the high spots and the low spots to the same height is counteracted by having the polishing fluid react chemically with the low spots.
The metal circuit interconnects in the trenches have corresponding low spots in the metal layer prior to a polishing operation. When such low spots on the circuit interconnects are polished by CMP, too much of the metal can be removed, as indicated by the presence of excessive concavity in the polished surfaces of the circuit interconnects. Dishing is a term that refers to the concavity in the circuit interconnects, as caused by CMP. Dishing is a structural defect of the circuit interconnects that contributes to unwanted attenuation of the signals transmitted by the circuit interconnects. Accordingly, a CMP process must be performed with care to minimize dishing.
Attempts have been undertaken to hasten the process of planarization by CMP, which would lower manufacturing costs. However, increasing the speed of a CMP process to rapidly remove material from the surface of a semiconductor wafer, causes rapid dishing, and causes an uneven polished surface, which is indicative of deficient planarization. Thus, a need exists for an invention that minimizes dishing, while minimizing the time duration for planarizing a surface by polishing with a polishing pad and a polishing fluid.
The invention minimizes the time duration for planarizing a surface on a semiconductor wafer by polishing the surface with a polishing pad and a polishing fluid.
The invention adapts a semiconductor wafer for removal of high topography features at a faster removal rate than for low topography features. The invention further adapts a semiconductor wafer to minimize dishing of circuit interconnects, while the high topography features are removed by polishing with a polishing pad and a polishing fluid.
The invention adapts a semiconductor wafer for minimized removal rate of the low topography features, while the high topography features are removed by polishing with a polishing pad and a polishing fluid.
Further, the invention adapts a semiconductor wafer to minimize dishing, while the high topography features are removed by polishing with a polishing pad and a polishing fluid.
The invention pertains to a process according to which, a resistant film is selectively formed on low topography features on a semiconductor wafer. Further, the invention pertains to a semiconductor wafer adapted for polishing with a polishing pad and a polishing fluid with which high topography features on the wafer chemically react and dissolve, and low topography features on the wafer have a resistant film that resists the polishing fluid. Further, the invention pertains to apparatus for forming a resistant film selectively on low topography features on a semiconductor wafer.