1. Field of the Invention
The present invention relates to a controlling method for use in a data processing device, and more particularly, to a storage controlling method for use in a processor comprising a store port for holding store data, which is transmitted from an arithmetic unit and is to be stored in a cache memory, etc.
2. Description of the Related Art
Mainly in a super scalar processor, etc. adopting an out-of-order method, a process of a store request is performed by assigning the store request, for example, to a store port or a write buffer, which is managed by an instruction processing device and intended to temporarily hold data to be stored in a cache memory or a memory such as a main storage.
As conventional techniques using such a store buffer, the following documents exist.    Document 1) Japanese patent Publication No. H6(1994)-4402 “Data Processing Device”    Document 2) Japanese Patent Publication No. H10(1998)-55303 “Memory System”
Document 1 discloses a technique with which a write buffer for holding at least one write address and data is comprised between a central processing unit and a cache, and write data is first written to the write buffer when a store instruction is executed, and then written to the cache storage device, in a data processing device comprising the cache storage device between the central processing unit and a main storage device.
Document 2 discloses a memory system in which an instruction bus and a data bus are separately arranged, 4 write buffers that are interposed in parallel between a CPU and a main storage device, and do not have an address comparator are comprised, and a data write is made to a memory via a write buffer, so that the speed of the entire system is improved.
Conventionally, a data write was directly made from a write buffer or a store port to a primary cache as described above. Additionally, a dedicated write buffer was sometimes arranged for a secondary cache memory. However, a write to a primary cache was directly made from a write buffer or a store port also in this case.
In recent years, however, the demand for enabling out-of-order execution with much more inflight request has been rising to improve a throughput. For example, the need for increasing the number of store ports (or write buffers) has been arising. If the number of store ports is increased to improve a throughput in correspondence with such a demand, the number of store ports (or write buffers) to be processed increases, which requires a time, for example, to select from which store port data is to be stored in a cache memory. To perform such an operation on one cycle, one cycle time must be made longer, and an improvement in the throughput cannot be expected due to an increase in the number of store ports. Accordingly, a method with which out-of-order execution with much more inflight request is enabled without degrading a throughput is demanded.