The present invention relates in general to electronic memories and in particular to content addressable memory cells and systems and devices using the same.
The most prevalent type of memory in data processing and telecommunications applications is the random access memory (RAM). In a RAM, the memory cells are organized in an array of addressable locations, where each location is comprised of one or more cells each storing a bit of data. During a random access, data are associated with an address and the corresponding location in the array accessed (read from or written to). During burst and page accesses, multiple words of data are stored or retrieved from a commonly addressable set of locations in the array, such as those along a single row when the array is organized in rows and columns.
Random access memories are not ideal in a number of situations. For example, to search for data stored within RAM, a sequence of addresses must be generated and data from the accessed locations sequentially examined until the search is complete. Typically, there is no guarantee that the data will be found within a predetermined number of access cycles, or even that the data will be found at all. This procedure is inefficient in applications such as networking, ATM (asynchronous transfer mode) switching, voice and image recognition, where time constraints on searching are critical.
As a result of the deficiencies of conventional RAM devices, the content addressable memory (CAM) was developed. The CAM is a data associative memory in which data is broadcast to all locations in the cell array at once. A comparison is made in each location between a received piece of data and the data stored in the cells of that location. When a match occurs, a flag is set to an active state based on the associated xe2x80x9cmatchlinexe2x80x9d. The output at the match lines can then be used as data for further processing. For example, the match line output may represent an address in RAM associated with a search target.
Content addressable memories can be either static or dynamic. The static design is very similar to a static RAM (SRAM) cell, essentially acting as a latch to store each bit of data. The Dynamic CAM, similar to a dynamic RAM, stores data as charge on a capacitor, although charge leakage from the capacitor will cause data deterioration and even loss if left unchecked. Consequently, with dynamic CAMs, the charge on the storage data in the cell capacitors must be periodically refreshed. In conventional dynamic CAMs, time must be taken for cell refresh, generally during which no data accesses can be made to the array.
Another problem with conventional dynamic CAMs arises from the fact that during a data access or refresh to the array, match operations cannot normally be performed. This is particularly true with regards to those columns of locations to which data are being read or written during update of the search database. As a result, CAM performance cannot be optimized.
What are needed therefore are CAM cell structures and device architectures which allow simultaneous updates of the stored database while match operations are being performed. Additionally, in the case of dynamic cells, such cells and architectures should retain the reduced power consumption advantage reduced die area a dynamic device provides but appear as a static CAM to an external processing device.
According to one embodiment of the principles of the present invention, a content addressable memory cell is disclosed which includes a first and second storage elements along with first and second transistors for selectively transferring charge between corresponding first and second bitlines and the first and second storage elements. The content addressable memory cell further includes first and second comparelines, each for carrying a corresponding bit of a comparand. A comparator 402 compares first and second bits of the comparand presented on the comparelines with information stored on the first and second storage elements and selectively controls a voltage on a corresponding one of a plurality of matchlines in response.
According to another embodiment of the principles of the present invention, a content addressable memory cell is disclosed which includes first and second pairs of bitlines, along with first and second memory cells. Each memory cell includes a first transistor for coupling the data storage node of that cell to either one of the first pair of bitlines or one of the second pair of bitlines as selected by a signal presented on a corresponding one of first and second wordlines. The memory cell is further associated with a plurality of matchlines for carrying the results of multiple comparisons made against the information stored in the memory cells. Comparator circuitry compares data stored at the first storage node with data presented on a first compareline and data stored at the second storage node with data presented on second compareline and selectively pulls down a precharged matchline in response.
According to an additional embodiment of the principles of the present invention, a multiple matchline content addressable memory is disclosed. This content addressable memory includes a plurality of conductors and a plurality of memory cells, each cell comprising a storage element and a transistor for selectively coupling the storage element to a corresponding one of the plurality of conductors. A plurality of comparator circuits are included, each for comparing a bit of data stored in the storage element of a selected one of the memory cells with a bit of a comparand presented on a corresponding one of the plurality of conductors and selectively controlling an associated one of a plurality of matchlines in response.
The principles of the present invention are also embodied in a telecommunications subsystem including a plurality of input ports for a receiving stream of information and a plurality of output ports, a selected one of the output ports transmitting the stream of information received by the input port to a next node in a telecommunications network. A content addressable memory stores a translation table, the translation table containing information for selecting the selected one of the output ports and includes a plurality of conductors, a plurality of memory cells and comparator circuitry for comparing data presented on a selected one of the plurality of conductors with data stored on storage elements of a corresponding pair of memory cells. In response to the comparison, the comparator circuitry selectively pulls down a voltage on an associated matchline.
The principles of the present invention allow for the construction of and operation of content addressable memory cells with multiple comparelines and/or multiple matchlines. Moreover, in some embodiments, two pairs of bitlines are provided such that one set of bitlines can be used to access the storage elements of the memory cells while the second set of bitlines is being precharged. They are advantageously used for simultaneous updates of the stored data base while match operations are being performed. At the same time, multiple comparelines and matchlines allow for multiple comparisons to be made against multiple comparand bits simultaneously.