1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device suitable for mounting on a portable terminal.
2. Description of the Background Art
Semiconductor memory devices, which are used in portable terminals such as cellular phones, employ pseudo-SRAMs (Static Random Access Memories) for achieving large capacities and easy control. The pseudo-SRAM includes DRAM (Dynamic Random Access Memory) cells as internal memory cells, and also includes an interface, which is asynchronous to a clock similar to that of a SRAM, as an external interface for defining input control signals and address signals. A refresh operation is not controlled by an externally applied signal, but is performed internally and automatically (e.g., see Japanese Patent Laying-Open No. 2002-352577).
For further achieving a high speed operation, a synchronous pseudo-SRAM, which additionally employs a synchronous interface, has been available, e.g., as CellularRAM® disclosed on the Internet Web site (URL: http://www.micron.com/products/psram/cellularram/). This synchronous pseudo-SRAM includes a synchronous interface synchronized with a clock similar to that of a SRAM in addition to an asynchronous interface not synchronized with the clock.
According to the synchronous pseudo-SRAM, a WAIT signal is issued to notify that external access is prohibited, before elapsing of a command latency CL, which is the number of clocks issued until data is output after reception of a read or write request, and while self-refresh is being performed. In a conventional structure, command latency CL is externally applied. However, the synchronous pseudo-SRAM does not require such external application because the WAIT signal can be internally issued to notify that the access is impossible. Command latency CL of a more appropriate value can be determined by internally determining it within the synchronous pseudo-SRAM according to a current state, as compared with the case of externally determining the command latency.
In contrast to the above, Japanese Patent Laying-Open No. 2001-155484 has disclosed a latency determining circuit, which can adjust a latency according to a clock frequency. This latency determining circuit includes a latency determining instruction input unit, which issues an internal start signal in response to activation of a latency determination start signal for starting latency determination in synchronization with a clock signal, a latency section defining circuit, which issues a predetermined latency determination section signal at every edge of the clock signal in response to the latency determination start signal, a delay unit issuing a delay signal to adjust the latency by delaying the internal start signal by a predetermined time, and a latency instructing circuit, which determines a latency number in response to the latency determination start signal and the latency determination section signal at the point in time of activation of the delay signal. The latency determining circuit described above can internally determine the latency without an external instruction.
For example, Japanese Patent Laying-Open No. 07-226077 has disclosed a method, in which self-refresh is performed simultaneously with reading or writing in the case where a pseudo-SRAM has multiple banks. More specifically, according to the paragraph [0020] in Japanese Patent Laying-Open No. 07-226077, even when one of first to fourth cell banks 10-13 is in a refresh mode, first to fourth row address latch circuits and buffers 80-83 can transmit second load address signals A0-An-2 latched by a row address latch circuit 70 to remaining three cell banks to allow access to data even during the refresh mode.
However, the following problems arise in the methods disclosed in the foregoing references.
Although Japanese Patent Laying-Open No. 2001-155484 has disclosed a manner of internally setting the latency, it has not disclosed timing for setting the latency.
Although Japanese Patent Laying-Open No. 07-226077 has disclosed a manner of performing the refresh simultaneously with reading or writing when the bank to be refreshed is different from the bank of a reading or writing target, it has not disclosed a manner of determining the bank to be refreshed such that the bank to be refreshed may not overlap with the bank of the reading or writing target.
Further, in a structure having a plurality of pseudo-SRAMs accommodated in a single package, each pseudo-SRAM performs the refreshing according to timing different from the timing of the others. This results in a conflict of the WAIT signals issued from the respective pseudo-SRAMs.
Further, there is such a problem that data cannot be output according to timing earlier than the timing defined by command latency CL.
In the case where the pseudo-SRAM has multiple modes such as a synchronous mode and an asynchronous mode, and operates in one mode selected from these modes, a preamplifier, which can operate appropriately in a certain mode, may not operate appropriately in another mode, and thus may not correctly perform amplification.
In the case where a processing target changes to a next row during continuous reading or writing, a byte mask signal must be applied after an externally applied WAIT signal notifies of the completion of processing for starting processing of a next row (i.e., deactivation of a word line in the last processed row, activation of a word line in the next target row, amplification by a sense amplifier and others).
For precharging a bit line pair, a chip enable signal must be externally deactivated, and thus external control is required.
Semiconductor memory devices such as a CellularRAM® cannot operate synchronously with a clock of a low frequency.
When a chip is on standby, or is inactive because another chip is being accessed, an input/output buffer continues an operation, and thus wastes a current.