Device shrinking requires scaling down the supply voltage (Vcc) accordingly because of power budget limitations. However, bit cells may require a longer time to reach a stable state after a write operation at lower supply voltages. This presents a trade-off between the minimum supply voltage (Vccmin) and the read/write speed of a memory.
Memories (e.g., cache memories, instruction queues, translation look-aside tables) consume a significant amount of switching power and leakage power in chips. Some bit cell designs that can operate at lower supply voltages incur overhead in terms of delay.