1. Field of the Invention
The present invention relates to an insulated gate field effect semiconductor device (FET) for use in switching devices, integrated circuits (ICs), and display devices such as liquid crystal displays and the like.
2. Description of the Prior Art
Insulated gate FETs heretofore fabricated unexceptionally comprise a semiconductor region in which a source, a channel, and a drain are established. In such insulated gate FETs, the drain is in contact with the channel and the source is in contact with the channel. However, in those types of insulated gate FETs, there have occurred problems such as the reverse current leakage from the drain to the source, and the poor drain voltage resistance.
More specifically, as is illustrated in FIG. 2, an insulated gate FET of the type above often suffers problems ascribed to the reverse current leakage. That is, the current which flows reversely from the drain to the source yields a curve indicated with (B) in the FIGURE; typically, although the gate voltage VG-drain current ID relation should result in a curve indicated with (A).
This phenomenon is ascribed to the occurrence of a punch-through current. That is, even in a gate voltage at which normally no channel forms, i.e., at a condition well below the threshold voltage Vth, an abrupt increase of the drain current occurs if the voltage applied between the source and the drain surpasses a certain value. The generation of this punch-through current is explained by the influence of the reverse bias at the drain junction which also affects the source junction. Since this punch-through current flows between the source and the drain along a path relatively deep with respect to the channel surface, it is possible to cut off the punch-through current by increasing impurity concentration along this path and thereby setting a high resistance between the source and the drain.
The low drain voltage resistance also impairs the output characteristics, as is illustrated in FIG. 3 by the curve (B) which shows the drain current ID against the drain voltage VD. At a voltage below the threshold, typically, the ID-VD curve should have a sharp rise as is shown in FIG. 3, curve (A). The low drain voltage resistance is also ascribed to the punch-through current as explained hereinbefore. If an insulated gate FET having a VD-ID curve (B) in FIG. 3 were to be fabricated, a drain current will flow continuously to result in a throw leakage state even though a voltage well below the threshold voltage were to be applied to the gate electrode. This would result in a switching device having poor reliability and insufficient performance.
As a means to overcome the problem of punch-through current attributed to the low drain voltage resistance, i.e., the poor insulation between the source and the drain, there is proposed, as is shown in FIG. 4, to provide a semiconductor layer having added therein hydrogen as an offset gate 49. Referring to FIG. 4, there is provided an insulated gate FET comprising a quartz substrate 41, a thin film of polycrystalline silicon 42, a silicon oxide film 43, a polycrystalline silicon electrode 44, a source 45, a drain 46, aluminum electrodes 47, and an offset gate 49. The offset gate prevents the electric field from concentrating in this portion. There is proposed another measure which comprises establishing, to the same area as that of the offset gate, a drain having lightly doped with an impurity which imparts one conductivity type thereto. This process, which is known as a light-dope drain (LDD) process, also relaxes concentration of the electric field in the boundary between the channel and the gate or between the channel and the source. In this process, however, the impurity having doped for imparting one conductivity type to a part of the semiconductor layer diffuses from the drain and the source that there still remains a problem to be solved.
This is because the impurity for imparting one conductivity type to the semiconductor layer is the one that is easily diffused by heat. For an insulated gate field effect transistor in which the channel length is not longer than sub-microns, this becomes a major problem. That is, there is a problem that a current flow is continuously formed between the source and the drain in the channel forming region due to diffusion of impurities from the source and the drain to the channel forming region.