(1) Technical Field
The invention relates to electronic circuits, and more particularly to bias circuits for cascode amplifiers, particularly radio frequency cascode amplifiers.
(2) Background
Amplifiers are a common component in radio frequency (RF) transmitters and receivers, and are frequently used for power amplification of transmitted RF signals and for low-noise amplification of received RF signals. For many RF systems, particularly those requiring portability (e.g., cellular telephones, WiFi-connected computers, cameras, and other devices, etc.), it has become common to use complementary metal-oxide semiconductor (CMOS) fabrication technology to create low cost, low power, complex integrated circuits (ICs). CMOS device technology improvements, such as silicon-on-sapphire (SOS) CMOS, silicon-on-insulator (SOI) CMOS, and ever-shrinking field-effect transistor (FET) device channel lengths, are putting the RF performance metrics of silicon-based CMOS transistors on par with rival gallium arsenide (GaAs) technologies.
FIG. 1 is a simplified schematic diagram of a prior art amplifier circuit 100. The illustrated circuit 100 has a cascode common source architecture constructed from two series-connected FETs. An RF input signal, RFIN, is applied through a biasing and coupling circuit 102 to the gate of a FET M1, the drain of which is coupled to (and thus drives) the source of a second FET M2. The source of M1 is coupled thorough a degeneration inductor L to RF ground. The degeneration inductor L, which will also have an inherent resistance R (shown in dotted outline), performs several functions, including obtaining a good dynamic range (e.g., a good noise figure), achieving high sensitivity with low power consumption, helping make input impedance matching easier, and improving linearity.
The second FET M2 has its gate coupled to a voltage source Vgate (which may be VDD in many cases) and provides an amplified RF output signal, RFOUT, at its drain. In some applications, the RF input signal, RFIN, may be processed through an input impedance matching network 104 before being coupled to the gate of M1, and in some applications, the RF output signal, RFOUT, may be processed through an output impedance matching network 106. While the illustrated cascode circuit provides good isolation because there is no direct coupling from the output to the input, the circuit is not well suited to applications in which the DC supply voltage varies, such as applications where the DC supply voltage at the drain is actively modified to optimize operation at different power levels; examples are average power tracking (APT), envelope tracking (ET), and GSM power amplifier power control. In these examples, the supply voltage VDD may have a range that varies by a factor of 10 or more (e.g., from 4.5V to 0.4V, as one example).
One problem area for using silicon-based CMOS transistors in cascode amplifier circuits is creating bias circuits, particularly in cases in which the DC supply voltage varies and in the case of amplifiers with a transistor stack height of 3 or more. In general, a DC bias voltage applied to the gate of a FET sets the gate-source voltage VGS so as to provide a desired drain current. Silicon-based CMOS devices with short channel lengths provide fast RF response—a desirable characteristic in an amplifier—but suffer from poor output resistance characteristics due to the influence of the drain voltage on the gate of a transistor device. As such, they are not amenable to common open-loop bias techniques, such as current mirrors, without suffering from a large and undesirable mismatch between a reference device current and the output device current. In addition, the problem can be further exasperated in SOS and SOI CMOS technologies due to issues associated with the floating body or “kink” effect. In the floating body effect, the body of a transistor may form a capacitor with the insulated substrate; charge accumulation on this capacitor may cause the formation of parasitic transistors consuming unwanted parasitic currents and further degrading the output resistance of devices intended to be used as current sources.
Another challenge in designing bias circuits for silicon-based CMOS cascode amplifiers is to configure such circuits so that they are tolerant of supply and bias voltage variations, and bias current variations. Traditional cascode bias circuits include diode connected devices which do not accommodate a wide range of supply and bias voltages. Bias current variations may be driven by variations in process, temperature, and voltage (i.e., “PVT” effects), the end result of which is to cause fluctuations in bias current leading to fluctuations in RF performance. Another drawback to using silicon-based CMOS devices for amplifier applications, and particularly for power amplifier applications, is a relatively low breakdown voltage per device.
Yet another challenge in designing RF amplifiers is that, in many applications, the RF electrical environment of a transmitter, receiver, or transceiver is constantly changing. The changing characteristics of an RF signal path affects RF circuit performance metrics such as gain, linearity, noise figure, and power consumption. A system performance profile that ideally sets such metrics for one situation (such as high gain, moderate linearity, and low noise in the presence of a small received signal) can be completely inappropriate as the RF environment changes (such as with increasing received signal power). These situation transitions can occur many times during a single usage session of an RF circuit (for example, as a cellular phone moves relative to signal towers), and not adjusting to an appropriate performance profile as the RF environment changes can result in poor or non-functioning RF circuit performance.
Accordingly, there is a need for bias circuits for silicon-based CMOS amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for the poor output resistance characteristics of silicon-based CMOS devices with short channel lengths. There is also a need for amplifier architectures that can rapidly adapt to a changing RF electrical environment. Further, there is a need for improved silicon-based CMOS amplifier architectures having good isolation.