1. Field of the Invention
The present invention relates generally to non-volatile magnetic memory and particularly to non-uniform switching of non-volatile magnetic based memory.
2. Description of the Prior Art
Computers conventionally use rotating magnetic media, such as hard disk drives (HDDs), for data storage. Though widely used and commonly accepted, such media suffer from a variety of deficiencies, such as access latency, higher power dissipation, large physical size and inability to withstand any physical shock. Thus, there is a need for a new type of storage device devoid of such drawbacks.
Other dominant storage devices are dynamic random access memory (DRAM) and static RAM (SRAM) which are volatile and very costly but have fast random read/write access time. Solid state storage, such as solid-state-nonvolatile-memory (SSNVM) devices having memory structures made of NOR/NAND-based Flash memory, providing fast access time, increased input/output (IOP) speed, decreased power dissipation and physical size and increased reliability but at a higher cost which tends to be generally multiple times higher than hard disk drives (HDDs).
Although NAND-based flash memory is more costly than HDD's, it has replaced magnetic hard drives in many applications such as digital cameras, MP3-players, cell phones, and hand held multimedia devices due, at least in part, to its characteristic of being able to retain data even when power is disconnected. However, as memory dimension requirements are dictating decreased sizes, scalability is becoming an issue because the designs of NAND-based Flash memory and DRAM memory are becoming difficult to scale with smaller dimensions. For example, NAND-based flash memory has issues related to capacitive coupling, few electrons/bit, poor error-rate performance and reduced reliability due to decreased read-write endurance. Read-write endurance refers to the number of reading, writing and erase cycles before the memory starts to degrade in performance due primarily to the high voltages required in the program, erase cycles.
It is believed that NAND flash, especially multi-bit designs thereof, would be extremely difficult to scale below 45 nanometers. Likewise, DRAM has issues related to scaling of the trench capacitors leading to very complex designs which are becoming increasingly difficult to manufacture, leading to higher cost.
Currently, applications commonly employ combinations of EEPROM/NOR, NAND, HDD, and DRAM as a part of the memory in a system design. Design of different memory technology in a product adds to design complexity, time to market and increased costs. For example, in hand-held multi-media applications incorporating various memory technologies, such as NAND Flash, DRAM and EEPROM/NOR flash memory, complexity of design is increased as are manufacturing costs and time to market. Another disadvantage is the increase in size of a device that incorporates all of these types of memories therein.
There has been an extensive effort in development of alternative technologies such as Ovanic Ram (or phase-change memory), Ferromagnetic Ram (FeRAM), Magnetic Ram (MRAM), Nanochip, and others to replace memories used in current designs such as DRAM, SRAM, EEPROM/NOR flash, NAND flash and HDD in one form or another. Although these various memory/storage technologies have created many challenges, there have been advances made in this field in recent years. MRAM seems to lead the way in terms of its progress in the past few years to replace all types of memories in the system as a universal memory solution.
A prior art field-switching MRAM structure used in conventional MRAMs is depicted in FIG. 1. In FIG. 1, an MRAM cell 10 is shown to include a bit line 12 and a transistor 14 and formed there between is the memory element 32 and a number of metal lines 20, 22, 24, 26 formed for ease of manufacturing. The word line (WL) 16 is shown formed on top of the gate of the transistor 14 and the digit line (DL) is shown formed on the bottom of the memory element 32. The memory element consists of three key layers namely the fixed layer, the barrier tunneling layer and the free-layer. In operation, the digit line (DL) 14 is used to change the magnetic orientation of the free-layer of the memory element and thereby creating “parallel” (low resistance) and “anti-parallel” (high resistance) states which become the “0” and “1”.
In FIG. 1, M1s 20 and 28, V1 22, M2 24 and V2 26 are examples of how these layers would be processed in order to connect the memory element (or cell) to the transistor 14. The M1 28, on the transistor 14's “drain” side, is connected to a common ground and is deposited, at substantially the same time, as the M1 20 on the “source” side of the transistor 14. The bit line 12 is typically connected through the memory element 32 to the source 30 of the transistor 14. The word-line (WL) 16 is typically connected to the control gate of the transistor 14 for selecting the specific transistor.
The problem with the MRAM cell 10 of FIG. 1 are two-fold namely, the large cell-size and therefore high cost and high-power. The switching of the memory element 32 is made through the magnetic-field generated from the digit-line 18 which limits how closely the neighboring cells can be and thereby leading to larger cell size and thereby higher cost.
One of the problems with prior art memory structures is that the current and power requirements are too high to make a functional memory device. This also poses a key concern regarding the reliability of such device due to likely dielectric break-down of the tunneling barrier layer and thereby making it non-functional.
FIG. 2 shows relevant layers of the memory elements 32 of prior art (MRAMs), such as the cells 10 (FIG. 1) and memory element 32. In FIG. 2, a free layer 60 is shown on top of which is shown formed a tunnel layer 62 on top of which is shown formed a fixed layer 64. The free layer's 60 magnetic moment can change, whereas, the moment of the fixed layer 64, below a known temperature, remains fixed. The tunneling layer 62 is commonly referred to as the “barrier layer”. In some prior art structures, the free layer 60 is made of several free layers. Application of current to the structure of FIG. 2 causes switching between anti-parallel (AP) and parallel (P) states, which, in turn represent two logical states for storing information in memory made from the structure of FIG. 2. The relationship between resistances of the two states depends on the tunneling-magneto-resistance (TMR) is defined as:TMR=(Rh−Rl)/Rl  Eq. (1)
Wherein Rh is resistance at a high state and Rl is resistance at a low state.
Low capacity MRAM memory based on a design relying on magnetic-field to switch the memory elements is another known memory. It has been shown that current can also be used to switch the memory elements. The challenge has been that the switching current is too high to allow the making of a functional device for memory applications due to the memory's high power consumption. Several recent publications, such as those cited below as references 5 and 6(5,6) have shown that the switching current can be reduced by having the memory element pinned by two anti-ferromagnetic (AF)-couple layers resulting in spin oscillations or “pumping” and thereby reducing the switching current.
What is needed is storage memory based on magnetic memory for storage of digital information and having reduced switching current in the magnetic memory thereby decreasing power consumption and reduced cell size thereby reducing costs associated with manufacturing the memory.