1. Field of the Invention
This invention relates to a method for forming a pattern of a film made of a desired material on a side wall of a stepped base, which pattern formation method is appropriately used, for example, for forming a desired film pattern of good precision on a plane which extends orthogonally to the main plane of the base in order to achieve high integration of an LSI.
2. Description of the Related Art
In order to improve the degree of integration of an LSI over a limited substrate area, the reduction of areas over which individual semiconductor elements constituting the LSI are defined on the main plane of the substrate has become more and more necessary. To this end, a technique has been employed wherein a groove is made in the substrate so that the side walls (portions corresponding to wall surfaces) are utilized as regions for forming semiconductor elements in order to provide an increased surface area over which the elements can be formed. However, the side walls defining such grooves have only been used, for example, to accommodate capacitor elements and have never been used to form a wiring pattern or a gate electrode of a transistor. Nevertheless, the necessity for forming a wiring pattern or elements on the side wall will be more and more in demand, and so it is believed to be necessary to establish a method wherein a wiring pattern or a gate electrode can be readily formed.
FIG. 5 illustrates a thin film pattern on a side wall, and is a perspective view of an ideal form of a thin film pattern. In this case, a semiconductor substrate 13 has a groove 11 with a depth l, and the thin film pattern 17 extends on a side wall 15 defining the groove 11 along the depth l of the groove 11.
However, it is very difficult to form such an ideal thin film pattern 17 as shown in FIG. 5.
FIGS. 6(A)-(C) illustrate main steps used to form a film pattern on a side wall according to a pattern forming method using the known single layer resist process. More particularly, FIGS. 6(A) and (C) are, respectively, partial perspective views taken in the direction P shown in FIG. 5, and FIG. 6(B) is a plan view of the sample shown in FIG. 6(A).
When the single resist process is used, a film 21 of material used to form a thin film pattern is formed on the surface of the semiconductor substrate 13 including over the inner surfaces thereof defining the groove 11. Next, the film material 21 is coated over the entire surface thereof, for example, with a positive resist (not shown). Subsequently, a light-shielding mask is provided at such a position that it crosses a boundary 11a of the step established by the groove 11, the resist is exposed to light irradiated from above the light-shielding mask, and the resist is developed to form a resist pattern 25 on a region traversing the boundary 11a of the step (FIG. 6(A)). However, the thus formed resist pattern 25 has a shape which is completely different from the shape of the light-shielding mask 23 as is particularly shown in FIG. 6(B). The reason for this is that the resist which has been applied over the surface of the semiconductor substrate 13 is thicker at the bottom portion of the groove and particularly at the corner portions of the groove 11, so that the exposure light does not reach the lower side of the thicker portion of the resist. Accordingly, a thin film pattern 21a which is obtained by an anisotropic etching technique, such as RIE (Reactive Ion Etching), has a shape which is far different from the shape of the light-shielding mask 23 as is shown in FIG. 6(C). More particularly, a useless region as shown in FIG. 6(C) as hatched is left at the lower portion of the step.
As a measure for overcoming the drawback involved in the known single layer resist process, there was known a so-called double layer resist process disclosed, for example, in "Process Techniques For Next Generation Super LSI," Applications, Apr. 4, 1988, by Realize Co., Ltd., (pp. 297-298). In this process, after the step of the substrate is filled in with a first resist layer, a second resist layer is formed on the first resist layer and is exposed to light and developed to obtain a mask. The first resist layer is subjected to patterning through the mask, thereby precisely controlling the patterned shape at the stepped portion.
FIGS. 7(A)-(F) illustrate the principle of the double layer resist process wherein there are shown steps of forming a film pattern on side walls 31a, 33a of two recesses 31, 33 of a semiconductor substrate 35, respectively. These figures are sectional views, respectively, of the semiconductor substrate 35 taken along the direction orthogonal to the side walls 31a, 33a.
Initially, a film 37 of material is formed on the entire surface of the semiconductor substrate 35 having the recesses 31, 33. A first thick resist layer 39 is then provided to define a flat upper surface (FIG. 7(A)).
Then, a second resist layer 41 is formed on the first resist layer 39 (FIG. 7(B)), after which the second resist layer 41 is subjected to exposure light in a desired pattern and developed to form resist patterns 41a, 41b (FIG. 7(C)).
Subsequently, the first resist layer 39 is subjected to patterning by, for example, dry etching to form the double layer resist patterns 43a, 43b (FIG. 7(D)).
The double layer resist patterns 43a, 43b are used as a mask for patterning the film material 37 so that portions 37a, 37b of the film material 37 are left over the respective side walls 31a, 33a defining the recesses 31, 33 (FIG. 7(E)).
Then, the double layer resist patterns 43a, 43b are removed to expose the desired film patterns 37a, 37b (FIG. 7(F)).
According to the double layer resist process, the flattening layer (first resist layer) and the layer exposed to light and subjected to development (second resist layer) are provided separately, so that a pattern shape corresponding to the shape of the exposure mask can be obtained even at the stepped portion.
However, the double layer resist process is complicated. As will be apparent from the process illustrated with reference to FIGS. 7(A)-(F), the double layer resist process has additional steps, including the step of applying the first resist layer and the step of patterning the first resist layer, compared with the single layer resist process. Moreover, although omitted in the above description, the double layer resist process inevitably requires a baking step after the application of the first resist layer and prior to the application of the second resist layer, wherein heat is applied to dry the first resist layer.
In addition, when the first resist layer is anisotropically etched, the second resist layer should have a satisfactory etching selection ratio to the first resist layer, thus presenting a problem in that the selection of materials is difficult.
The complicated process and the reduction in degree of freedom with respect to the selection of resist materials are not favorable, for example, in view of the fact that they contribute to a direct rise in the production costs of the semiconductor device.
Both the known single layer resist process and the known double layer resist process are disadvantageous in that the film pattern cannot be left only on the side wall or walls of the step (e.g. the ideal film pattern 17 should be left only on the side wall as shown in FIG. 5), i.e. the film pattern also remains on the upper and lower portions of the step. This is because in the prior processes, after the film material has been formed on the entire surface of the substrate including the step, a resist pattern is formed on the film material so as to cover the side wall. More particularly, in order to reliably cover the side wall with the resist pattern, a shift in the alignment between the mask used to form the resist pattern (the light-shielding mask as in FIG. 6(A)) and the side wall has to be taken into account. Accordingly, the light-shielding mask 23 must inevitably extend over the upper and lower portions of the step while covering the step. Since the material film 21 is formed on the entire surface of the substrate, the film pattern 21a will be left on the upper and lower portions of the step as corresponding to the additional regions required for the mask alignment. This phenomenon takes place in the double layer resist process illustrated with reference to FIG. 7.