The present invention relates generally to testing integrated circuits, and more particularly to built-in-test circuits and output response analyzers for integrated circuits.
Integrated circuits are typically tested multiple times while they are manufactured. Often, individual circuits are tested while they are part of a wafer, which contain thousands of integrated circuits. Nonfunctional die are identified, for example with an ink spot, during a test referred to as wafer sort. After wafer sort, the die are separated and packaged. The packaged devices are testing again—this is referred to as final test. Additional testing may be done, for example sample devices may be tested under extreme environmental conditions.
During these tests, test data, also referred to as test vectors, which typically include data and clock signals, are provided to the integrated circuit by a tester. The input test data may be generated by a circuit or software test pattern generator. Conventionally the integrated circuit operates on the input test data and provides output test data back to the tester. An output response analyzer in the tester checks the output test data for errors, and passes or rejects the device.
It is desirable to test each node in an integrated circuit. However, integrated circuits are becoming extremely complicated and may include hundreds of thousands of logic elements. At the same time, it is desirable to reduce the number of pins on the device in order to simplify device packaging and reduce printed circuit board complexity and space. The result is that many internal nodes on integrated circuits are difficult to reach electrically by device pins.
Accordingly, it is desirable to include test circuitry on the integrated circuit itself, such that these internal nodes may be more thoroughly tested. Further, it is desirable to provide an internal test circuit that is capable of testing using test patterns other than simple all ones or all zeros patterns. Also, it is desirable to be able to perform such tests without the addition of complicated circuitry. It is also desirable that the internal circuitry require no or a limited number of pins, such that device pin count may be maintained.