The present invention relates to a bit demultiplexor circuit for demultiplexing a serial data stream, and a delay line circuit/clock multiplying circuit, in particular for use in a multiplexor and/or demultiplexor circuit.
Furthermore the invention also relates to a bit multiplexor circuit, including
an internal clock generator, which by means of a reference clock generates a number of accurately mutually time delayed clock signals,
aligning means arranged to align, by means of one of said clock signals, all incoming parallel data bits with respect to the same clock,
delay means for delaying, by means of another one of said clock signals, a number of said data bits,
multiplexing means for multiplexing the aligned and delayed data bits by means of said time delayed clocks.
Through International Patent application Ser. No. PCT/SE92/00809 a method for clock recovery of a digital data signal is known, wherein a number of mutually phase shifted auxiliary clock signals are used to generate a recovered clock signal for the data signal based upon the result of detection of a phase position error, if any, between the data signal and its recovered clock signal. If the phase position error is different from zero and the phase position of the recovered clock signal is between the phase positions of two auxiliary clock signals, these two auxiliary clock signals are mixed for generating an adjusted recovered clock signal with the same phase position as the data signal.