1. Field of the Invention
The present invention relates to apparatus and method for verifying an integrated circuit pattern formed on a substrate.
2. Description of the Related Art
In the manufacture of semiconductor devices, there is a need of verifying whether an integrated circuit pattern formed on a substrate is formed as designed in individual processes.
FIG. 15 is a view to explain a method of verifying a hole pattern. According to the method, a target data TD of preset hole pattern is overlapped with a contour data CD extracted from hole pattern formed on a substrate. In the overlapped state, distances from several places of the foregoing two patterns are measured. It is determined whether or not the difference between the measured distances is within a predetermined allowable value, and thereby, it is determined whether the formed pattern is non-defective or defective.
The method of evaluating a pattern shape has been proposed (for example, JPN. PAT. APPLN. KOKAI Publication No. 2002-31525). According to the method, the distance between CAD (Computer Aided Design) output data and pattern data measured by SEM (Scanning Electron Microscope) is measured in the same manner as described above. Based on the measured distance, evaluation is made with respect to the pattern shape.
The method of evaluating a pattern defect information has been proposed (for example, JPN. PAT. APPLN. KOKAI Publication No. 2002-93875). According to the method, the error dimension between CAD output data and shape simulation output data is measured. If the measured error dimension is not within a predetermined value, pattern defect information is displayed.
In addition, the following method has been proposed (for example, JPN. PAT. APPLN. KOKAI Publication No. 2000-182912). According to the method, comparison is made between an inspection reference pattern formed based on the design layout pattern and the finished predictive pattern. By doing so, pattern distortion of the finished predictive pattern is detected, and thereafter, the detected pattern distortion is identified in accordance with criticality.
According to the method of measuring the distance between the foregoing two patterns, a great many of places is measured, and thereby, the measurement accuracy is improved. However, if the measured places are too many, long time is spent for measuring these places. According to the method, the difference from the corner of the pattern is not so taken into consideration. For this reason, when verifying a pattern having a complicated shape, it is very difficult to determine whether the pattern is non-defective or defective. Moreover, there exist various patterns requiring to bridge neighboring patterns depending on pattern, or to control only line width of the shorter side of the pattern. In the foregoing patterns, the allowable (variable) range for the target dimension has not been clarified. For this reason, according to the conventional method, it is determined that patterns formed with accuracy having no problem on the device operation are defective.
According to the conventional method, time is taken to verify the pattern, and the features of the pattern are not considered; as a result, the pattern is not properly verified. In addition, according to the conventional method, it is difficult to evaluate a complicated pattern.