More specifically, the invention concerns the production of a circuit comprising MIS transistors and capacitors, especially for amplifier circuits, switched capacity filtering circuits, analog/digital or digital/analog converter circuits and dynamic DRAM memories With these types of circuits, the capacitors are situated on the electric or field oxide insulation zones of the integrated circuit.
In one known analog die, the capacitors are formed by a first film of doped polycrystalline silicon noted poly-1, a thermic oxidation of this silicon film or a CVD oxide deposit and a second film of polycrystalline silicon deposited on the thermic oxide and noted poly-2. In the first polycrystalline silicon film, the gate of the transistors of the integrated circuit is formed. One example of known analog circuits of this type is described in the document FR-A-2 601 817 filed in the name of the Applicant.
In addition, in the document IEEE 1989--Custom Integrated Circuits Conference and entitled "A Submicron Analog, CMOS Technology" by R. W. Gregor and al., 18.5.1-18.5.4, instructions are contained for the embodiment of high value resistors in the poly-1.
The poly-2 used for the embodiment of the capacitors introduces a further level in the structure of the integrated circuits, thus significantly increasing the height of these circuits, which renders it more difficult to embody the stages for levelling (known under the term "planarization") by the dielectric materials used between the various conductive films. This also makes it difficult to reduce the dimensions of the integrated circuits. In fact, the smallest pattern of these circuits, generally constituted by the gate of the transistors, is 1 micrometer.
Moreover, the etching of the poly-2 is delicate, as it is formed from the etching residue at the foot of the poly-1 owing to the abrupt action constituted by the gates of the transistors situated between the lateral electric insulation zones. So as to avoid this residue, a chemical isotropic etching needs to be used, thus resulting in a large dimensional loss on the poly-2.
So as to reduce this dimensional loss, generally a slight thickness of the poly-2 is selected, thus resulting in the embodiment of high value electric resistors for the upper electrodes of the capacitors limiting the operating speed of these circuits.
In one modified method, it is possible to embody the poly-1 of the capacitors before the poly-1 of the gates, the latter then being embodied in the poly-2. In this case, the difficulty of the etching the capacitive elements is to be added to the etching of the gates, the etching residue forming at the foot of the poly-1 capacitors. Now, the etching of the gates is a crucial operation for embodying a submicronic analog die.
In known logic (or digital) dies, on the gates of the transistors and on their source and drain zones, a silicide film of a refractory metal with low resistivity is formed via the reaction of the silicon and a refractory metal. This technique is known as the self-aligned silicide technique and is described in detail in the document IEEE Journal of Solid-State Circuits, vol. SC-20, No 1 February 1985 and entitled "Development of the self-aligned titanium silicide process for VLSI applications" by M. E. Alperin and al., pp. 61-69.
This technique has a certain number of advantages, such as the reduction of the resistance of the gate and the interconnections of these polycrystalline silicon gates (from 25 ohms to 3 ohms/square), thus improving the operating speed of the integrated circuits. In addition, it makes it possible to reduce the resistance of the source and drain zones by embodying silicide bond pads making it then possible to reduce the number of electric contacts on these active zones resulting in an integration density gain.
This silicide film only ensures connections either between the gates or the drains or between the sources, but it does not allow for the embodiment of interconnections between the sources and the drains or between the gates and the active zones (source or drain). In fact, these interconnections are effected after depositing a insulating (dielectric) film on the surface of the circuit and then opening contact openings in this insulating film in a metallic film etched according to the desired patterns; they constitute the first level of interconnections.
This silicide technology is incompatible with known analog dies, as they are unable to correctly oxidize a silicide so as to form silicide/oxide/poly capacitors. Furthermore, if the silicide is formed after the poly-2 is etched, the capacitors would be short-circuited by the silicide.
In addition, there currently exists the technique of producing local interconnection lines (LIL), which is an extension of the silicide technique described above. This technique is described in detail in the document J. Vac. Sci. Technol. B(6), November/December 1988 and entitled "TiSi.sub.2 strap formation by Ti-amorphous-Si reaction" by H. J. W. Van Houtum and al., pp. 1734-1739.
It consists of forming silicide interconnections both on the drains and sources of the transistors to be connected and on the thick dielectric (generally LOCOS). This makes it possible to ensure short distance links between the transistors without any interface being provided between the various films and especially being able to mount the electric contacts on the dielectric. It is then possible to reduce the surface of the sources and drains and thus increase the integration density of the circuits.
In addition, this technique has one significant advantage, namely that the opening of electric contact openings in the dielectric covering the transistors and capacitors is rendered much easier In fact, the contact openings are etched in a thick dielectric which is much more uniform than the one used in the analog die, thus facilitating the levelling of the circuits.
As mentioned previously, this technique is incompatible with known analog dies.