1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a front-end unit having an interface function and a back-end unit including a memory core are integrated on separate semiconductor chips.
2. Description of Related Art
Semiconductor devices such as a DRAM (Dynamic Random Access Memory) are often used in a state where a plurality of the semiconductor devices are mounted on a module substrate. The modularized DRAMs are sometimes classified into a plurality of ranks that are exclusively selected by chip select signals (see Japanese Patent Application Laid-open No. 2010-134904). Because different ranks can be accessed independently of each other unless competition on a data bus does not occur, use efficiency of the data bus can be enhanced by classifying the DRAMs on the module into the plural ranks.
On the other hand, there has recently been proposed a technique in which a so-called front-end unit performing an interface with a memory controller and a back-end unit including a memory core are integrated on separate chips, and these chips are stacked to form a single semiconductor memory device (see Japanese Patent Application Laid-Open No. 2007-158237). According to this technique, in a core chip on which the back-end unit is integrated, a space that can be allocated to the memory core increases, whereby a storage capacity per 1 chip (per 1 core chip) can be increased. On the other hand, the interface chip on which the front-end unit is integrated can be manufactured by a process different from the process for the memory core, whereby a circuit can be formed with a high-speed transistor. Furthermore, plural core chips can be allocated to one interface chip, resulting in that a high-speed semiconductor memory device having extremely large capacity as a whole can be provided.
However, in the stacked semiconductor device, through silicon vias used to transmit commands are commonly connected between the plural core chips. Accordingly, when the plural stacked core chips are classified into plural ranks, a transfer interval of the commands on the through silicon vias is reduced and thus the commands may not be correctly transferred. To prevent this, an issuance interval of the commands needs to be extended to avoid competition of the commands also at the time of accesses to different ranks; however, use efficiency of the bus is lowered in this case.