1. Field of Use
The present invention relates to cache systems and, in particular, to cache systems includable within minicomputer and microprocessing systems.
2. Prior Art
It is well known in the art to provide cache systems within computer systems to improve overall system performance and provide for reliable operation. Examples of such systems are disclosed in U.S. Pat. No. 3,820,078 to John L. Curley, et al. and in IBM Technical Disclosure Bulletin titled "Removal of Failing Buffer Sections in a Buffer Backing Store" by M. W. Bee, et al., Vol. 13, No. 2, dated July 1970. In those systems, reliable operation is achieved by invalidating cache memory locations detected as having bad parity. This requires additional bits to be associated with the cache locations and can add considerably to the cost and complexity of the cache system. More importantly, it requires processing time for carrying out such invalidating operations.
Other prior art cache systems permit the cache to be bypassed upon the detection of fault conditions by the central processing unit (CPU) associated therewith. An example of this type of system is disclosed in U.S. Pat. No. 4,195,343 to Thomas F. Joyce which is assigned to the same assignee as named herein. In general, this type of cache system is designed to report two types of errors to the CPU, a memory "red" error condition indicative of an uncorrectable error and a memory "yellow" condition indicative of a correctable error. Upon the receipt of a "red" error signal or the detection of a byte data parity error in received memory data, the CPU switches the entire cache off-line, reports the error to the operating system and continues processing.
While the above systems allow disconnection of a cache unit as a consequence of a fault condition, it requires the CPU to process such fault conditions. This can prove time consuming and could also result in loss of valuable information since such diagnosis relies in part upon the types of error conditions reported by the cache system itself.
Accordingly, it is a primary object of the present invention to provide a reliable cache system which is low in cost and has minimal complexity.
It is still a further object of the present invention to provide a cache system which has improved maintainability thereby increasing system reliability.