1. Field of the Invention
The present invention relates to the field of computer systems and, in particular, to a method and apparatus for stress testing of a circuit board assembly.
2. Background Information
Manufacturers have long understood that manufacturing processes are not perfect. Manufacturers of printed circuit board assemblies (PCBs), for example, understand that the manufacturing processes used to manufacture PCBs are unable to produce a population of product which performs exactly the same. Therefore, manufacturers determine performance specification limits for each critical operating parameter of a product, generally drawn around an optimum performance level for each critical parameter. For example, the operating frequency of a clock source may be specified at 66 MHz, with a "specification window" of plus or minus 2 MHz. Thus, a clock source that performs within the range of 64-68 MHz will be identified as "acceptable" (or "passing"), while those not performing within this range will be identified as "unacceptable" (or "failing"). The purpose of the specification window is to ensure the proper performance of the PCB assembly when integrated into larger systems, and under the operating conditions of the end-user environment.
Nonetheless, despite this "weeding out" of unacceptable product through the parametric testing which occurs during the manufacturing process, there remains a percentage of the "acceptable" population of product that fails to meet performance specifications when subjected to the actual operating conditions of the end-user environment. One explanation for the variability in performance of the printed circuit board assembly may be attributed to the variability in the components of the PCB. Thus, if a product just barely falls within the specification window for a particular operating parameter, i.e. the product is marginally acceptable, it may well be that under certain operating conditions the product may fail to meet the operating specification.
Consequently, one of the issues faced by manufacturers is how to identify and thus contain the marginally performing population of products produced by the manufacturing process that will fail under the conditions of the end-user operating environment. One prior art solution to this problem is to simply tighten the specification window. This is a very costly solution, however, in that not all of the products tested to perform near the edge of the specification window will actually result in a field failure.
Another prior art solution to the problem is subjecting the population of product, or a sample thereof, to environmental stress testing. Environmental stress testing, as its name implies, subjects the circuit board assembly to a number of environmental stresses such as temperature (both hot and cold), humidity, and shock/vibration testing.
Environmental stress testing, however, has the limitation that it employs a mechanical delivery mechanism. That is, environmental testing applies the stress to the electronic device externally, through the packaging of the devices. The packaging of electronic devices has a property commonly referred to as a "thermal coefficient" which describes the rate at which heat is transferred through the packaging material. Without going into unnecessary details, it is sufficient to say that environmental stress testing incurs a time delay, necessary to allow the inner circuitry of the electronic devices to settle into a steady state operating temperature, before the parametric testing may be completed. Accordingly, environmental testing is also considered a costly solution, both in terms of the time required to complete the testing sequence, as well as the capital equipment associated with conducting such tests (i.e., temperature chambers, humidity chambers, shock/vibration chambers). Therefore, despite manufacturers effort to identify and contain marginally performing printed circuit board assemblies, the prior art solutions have not proven to be effective.
Thus a need exists for a more cost effective method and apparatus for stress testing of a circuit board assembly that is unencumbered by the deficiencies and limitations associated with the prior art.