The present invention relates to a solid state image sensor comprising a plurality of pixels formed by static induction transistors having both a photoelectric converting function and a switching function.
Heretofore, there have been proposed various solid state image sensors comprising a charge transfer device such as CCD and BBD, and MOS transistors. However, such known image sensors have drawbacks in that electric charges are leaked during the charge transfer and the photodetection sensitivity is low. In order to avoid such drawbacks, there has been proposed a solid stage image sensor comprising static induction transistors (hereinafter abbreviated as SIT). For instance, in an European Patent Application No. 83900059.3 (Publication No. 96725), there is described a solid state image sensor comprising SITs each of which serve as a photodetecting element and a switching element. The inventor of the instant application has also proposed in U.S. patent application Ser. No. 647,169 filed on Sept. 4, 1984, a solid state image sensor comprising SITs., which solid state image sensor has a higher sensitivity and is easily manufactured. This solid state image sensor can read out an image signal while stored charges remain undestroyed and can have a high sensitivity by prolonging the time period of accumulating photocarriers.
FIGS. 1A and 1B show an embodiment of the solid state image sensor comprising SITs as proposed in the above mentioned Patent Application. A SIT shown in FIG. 1A comprises an n.sup.+ substrate 1 which serves as a drain of the SIT, a lightly doped n.sup.- epitaxial layer 2 which is grown on the substrate 1 and serves as a channel, an n.sup.+ source region 3 and p.sup.+ gate regions 4 formed in the epitaxial layer 2 by means of, for example, a thermal diffusion, source electrode connected to the source region 3 and gate electrodes 6 arranged above the gate regions 4 via an insulating film 5 such as SiO.sub.2 to form a gate capacitor 7. The SIT is isolated from adjacent SITs by means of an isolation region 9 formed by a burried insulating substance. A number of SITs are arranged in a matrix on the same substrate.
FIG. 1B is a circuit diagram illustrating a whole construction of the solid state image sensor comprising normally-on type SITs shown in FIG. 1A. Drains (substrate) of SITs 10-11 to 10-mn forming pixels arranged in a matrix are commonly connected to ground, and to gate electrodes of SITs 10-11 to 10-1n; . . .; 10-m1 to 10-mn arranged in the X direction, i.e. in a row, are connected row lines 11-1 to 11-m, respectively, which lines are then connected to a vertical scanning circuit 16 to receive row selection signals .phi.G1 to .phi.Gm. Source electrodes of SITs 10-11 to 10-m1; . . .; 10-1n to 10-mn arranged in the Y direction, i.e. in a column are connected to column lines 12-1 to 12-n, respectively, whose first ends are connected to a video voltage source Vs via respective column selection transistors 13-1 . . . 13-n, a common video line 14 and a load resistor 15. To gates of the column selection transistors 14-1 to 14-n are applied column selection signals .phi.S1 to .phi.Sn, respectively from a horizontal scanning circuit 17.
In the SIT having the construction explained above, when a light input is given, electron-hole pairs are induced in the channel region 2 and a gate depletion region. Electrons are conducted away into the drain 1 connected to ground, and holes are stored in the signal storing gate region 4 and thus the gate capacitance 7 connected thereto is charged to vary a gate potential by .alpha.V.sub.G. Now it is assumed that an amount of electrostatic charges stored in the gate region 4 is represented by Q.sub.L and the capacitance of the gate capacitor 7 is denoted by C.sub.G, then .alpha.V.sub.G =Q.sub.L /C.sub.G is obtained. After a certain accumulation time, when a readout pulse V.sub..phi.G is applied to the gate terminal 8, the gate potential is changed into a sum of V.sub..phi.G and .alpha.V.sub.G. Then, a potential difference between the signal storing gate region 4 and source region 3 is lowered to decrease the depletion layer and a drain current having an amplitude corresponding to the light input begins to flow between the source and drain. Due to the amplifying function of SIT, the drain current is multiplied by the amplification factor of the SIT. It should be noted that even if the source and drain of the SIT are exhanged, a similar operation to that explained above may be effected.
FIGS. 2A to 2F illustrate waveforms of the signals applied to the row lines 11-1 to 11-m and column selection transistors 14-1 to 14-n. As illustrated in FIGS. 2A to 2F, in this solid state image sensor, the successive pixels are readout by successively selecting the row lines 11-1 to 11-m as well as by successively selecting the column lines 13-1 to 13-n while a row line has been selected. Each of the signals applied to the row lines has a lower voltage V.sub..phi.G, and a higher voltage V.sub..phi.R. During the line scanning period t.sub.H the row selection signal has the voltage V.sub..phi.G and during a horizontal blanking period t.sub.BL the row selection signal assumes the voltage V.sub..phi.R. Each of the column selection signals .phi.S1, .phi.S2 . . . applied to the gates of the column selection transistors has a low level for cutting off the transistor and a high level for making the transistor conductive.
When the vertical scanning signal .phi.G1 is increased to the high voltage V.sub..phi.G, SITs connected to the first row line 11-1 are selected and the SITs are successively read out while the column selection transistors 13-1, 13-2 . . . 13-n are successively made conductive by means of the horizontal scanning signals .phi.S1, .phi.S2 . . . .phi.Sn. In this manner, a video signal of one line is derived on the video line 14. Then, the SITs in the first row are simultaneously reset when the vertical scanning signal .phi.G1 is increased to the higher level V.sub..phi.R.
Next, when the vertical scanning signal .phi.G.sub.2 is changed to the voltage V.sub..phi.G, all SITs 10-21, 10-22 . . . .phi.-2n connected to the second row line 11-2 are selected and are successively readout by means of the horizontal scanning signals .phi.S1, .phi.S2 . . . .phi.Sn.
In this manner, successive pixels are readout to derive a video signal of one frame.
The inventor has found that the known solid state image sensor mentioned above has the following drawbacks. In the image sensor, the accumulation of photocarriers induced by the incident light is effected in the channel region 2 and gate depletion layer in each SIT. The accumulating regions correspond to portions in the channel region which situated between the gate regions and isolating region, and underneath the gate regions. It is apparent that the portions between the gate regions and isolating region are liable to be small as the dimension of pixels is made smaller. Then, a major portion which serves to accumulate the photocarriers would be the portion in the channel region situated underneath the gate region 4, and thus, the incident light has to transmit through the gate regions 4. In order to obtain a large amplification of the SIT, a depth Xj of the gate region 4 has to be relatively thick such as 2 to 4 .mu.m. Therefore, the incident light, particularly components of short wavelengths (blue light) is abosrbed in the gate region 4 and cannot penetrate to the portion of channel region underneath the gate region.
FIG. 3 is a graph showing a light absorption coefficient .alpha. of silicon in dependence upon wavelength .lambda. of incident light. If it is assumed that .lambda.=0.4 .mu.m and the thickness of the P.sup.+ gate region is 3 .mu.m, then .alpha.=6.times.10.sup.-4 cm.sup.-1, and a light transmittivity becomes a very small value such as e.sup.-6.times.10.spsp.4.sup..times.3.times.10.spsp.4 =1.5.times.10.sup.-8. In this manner, the known solid state image sensor has a very low sensitivity especially for blue light and thus a color camera comprising the solid state image sensor having a high sensitivity over a whole sepectrum of visible light can not be realized.