1. Field of the Invention
The present invention relates to the field of computer systems, and more particularly to a multiprocessor computer system having an input/output bridge coupled to devices external to the multiprocessor computer system.
2. Description of the Relevant Art
Personal computers (PCs) and other types of computer systems have been designed around a shared bus system for accessing memory. One or more processors and one or more input/output (I/O) devices may be coupled to the memory through the shared bus. The I/O devices may be coupled to the shared bus through an I/O bridge which manages the transfer of information between the shared bus and the I/O devices, while processors are typically coupled directly to the shared bus or coupled through a cache hierarchy to the shared bus.
Unfortunately, shared bus systems suffer from several drawbacks. For example, since there are multiple devices attached to the shared bus, the bus is typically operated at a relatively low frequency. The multiple attachments present a high capacitive load to a device driving a signal on the bus, and the multiple attach points present a relatively complicated transmission line model for high frequencies. Accordingly, the frequency remains low, and the bandwidth available of the shared bus is similarly relatively low. A low bandwidth presents a barrier to attaching additional devices to the shared bus, as performance may be limited by available bandwidth.
Another disadvantage of the shared bus system is a lack of scalability to larger numbers of devices. As mentioned above, the amount of bandwidth is fixed and may decrease if additional devices are added. Once the bandwidth requirements of the devices attached to the bus, either directly or indirectly, exceeds the available bandwidth of the bus, devices will frequently be stalled when attempting to access the bus. As a result, overall performance may be decreased.
One or more of the above problems may be addressed using a distributed memory system. A computer system employing a distributed memory system includes multiple nodes. Two or more of these nodes are connected to individual memories, respectively, and the nodes are interconnected using any suitable interconnect. For example, each node may be connected to each other node using dedicated lines. Alternatively, each node may connect to a fixed number of other nodes, and transactions between nodes may be routed from a first node to a second node to which the first node is not directly connected via one or more intervening nodes. A memory address space is assigned across the memories in each node.
Nodes may additionally include a processor. The processor typically includes a cache which stores cache blocks of data read from the memories. Furthermore, a node may include one or more caches external to the processors. Since the processors and/or nodes may be storing cache blocks accessed by other nodes, it is desirable to maintain coherency within the nodes.
The present invention provides a method and circuit for maintaining order of memory requests initiated by I/O devices coupled directly or indirectly to a multiprocessor computer system via an I/O bridge. In one embodiment, the multiprocessor computer system comprises a plurality of processing nodes and a plurality of memories. Each processing node includes at least one microprocessor coupled to a memory controller which, in turn, is coupled to one of the plurality of memories. Each memory defines a portion of the memory address space for the computer system. Each processing node is uniquely identified by a node number. The I/O bridge is coupled to one or more processing nodes and is configured to generate and transmit a non-coherent memory access transaction. The non-coherent memory access transaction is generated in response to a memory access request generated by an I/O device coupled directly or indirectly to the I/O bridge. The I/O bridge transmits the non-coherent memory access transaction to at least one processing node connected thereto where it is transformed into a coherent memory access transaction for transmission to another processing node within the multiprocessor computer system. Each non-coherent memory transaction includes at least one command packet containing a pipe identification and a memory address affected by the memory access transaction. The pipe identification may include information identifying the origin of the memory request. Generally, non-coherent memory transactions having the same pipe identification must complete in order whereas non-coherent memory transactions having different pipe identifications may complete out of order.
The I/O bridge generates first and second non-coherent memory access transactions, the second non-coherent memory access transactions being generated after the first non-coherent memory access transaction. Each of the first and second non-coherent memory access transactions include first and second memory addresses, respectively. Further, each of the first and second non-coherent memory access transactions include first and second pipe identifications, respectively. The first and second memory addresses are mapped to first and second node numbers, respectively, in response to the connected node receiving the first and second non-coherent memory access transactions. Thereafter, the first and second pipe identifications of the received first and second non-coherent memory access transactions, are compared. Additionally, the first and second node numbers are compared if the first and second pipe identifications compare equally. The connected node which receives the first and second non-coherent memory transactions generates and transmits a first coherent memory access transaction corresponding to the first non-coherent memory transaction. This first coherent memory access transaction includes the mapped first node number and the first memory address. The processing node also generates a second coherent memory access transaction corresponding to the second non-coherent memory access transaction. This second coherent memory access transaction includes the second node number and the second memory address. However, in one embodiment, the second coherent memory access transaction is generated only if the first and second pipe identifications do not compare equally or if the first and second node numbers compare equally. In another embodiment, the second coherent memory access translation is generated without delay upon the node circuits receipt of the second non-coherent memory access transaction. However, the second coherent memory access transaction is transmitted from the connected node processing only if the first and second pipe identifications do not compare equally or if the first and second node numbers compare equally.