Switching Mode Power Supplies (SMPS) are used in a variety of portable electronic devices including laptop computers, cellular phones, personal digital assistants, video games, video cameras, etc. They may convert a dc signal at one voltage level to a dc signal at a different voltage level (this is a dc-dc converter), an Alternating Current (ac) signal to a dc signal (this is a an ac-dc converter), a dc signal to an ac signal (this is a dc-ac converter), or an ac signal to an ac signal (this is an ac-ac converter). Generally, switching mode power supplies have included switching power supply controllers or converters that operate in a continuous mode under heavy load conditions, i.e., a load that draws a large current, and under a skip mode or pulse skip mode under light loading conditions, i.e., a load that draws a small current. In the past, semiconductor manufacturers used various methods and structures to form the switching power supply controllers, such as Pulse Width Modulated (PWM) power supply controllers that regulated the value of a voltage supplied by a power supply system. In some cases, the switching power supply controllers were capable of operating in a fixed frequency or continuous operating mode during normal operation. When the current drawn by the load that was receiving power from the power supply system decreased, some of the prior switching power supply controllers operated in a light load mode that skipped some of the PWM cycles. The light load operating mode has been referred to as a skip mode or a burst mode. When the load again required a higher current, the switching regulator circuit exited the skip mode and returned to normal operation.
Usually the converters include a compensation network that is connected to an error amplifier to stabilize the system and to optimize the transient response based on a small signal behavior model. However, when a large signal transient event occurs such as a step load transient from a light load condition to a full load condition, the converter is unable to achieve the desired response due to saturation recovery of the compensation network and the slew rate limitation of an error amplifier.
FIG. 1 is a prior art schematic diagram of a portion of a power supply system 10 that includes a switching power supply controller 12. System 10 receives power between a power input terminal 14 and a power return terminal 16 and forms an output voltage (VOUT) between output 18 and terminal 16. Controller 12 is configured to regulate output voltage VOUT to a desired value or target value within a range of values around the target value. For example, the target value may be five volts (5 v) and the range of values may be plus or minus five percent (5%) around the five volts. System 10 usually includes a power switch such as a power transistor 20 and a rectifier 22 that are connected to control an inductor current I24 that flows through an inductor 24. Rectifier 22 may be a synchronous Metal Oxide Semiconductor Field Effect Transistor, a diode, or the like. A capacitor 26 is connected between output 18 and terminal 16 in order to assist in forming output voltage VOUT. A voltage sense network 28 may be coupled to output 18 to provide a voltage sense signal VS at node 30 that is representative of the instantaneous value of output voltage VOUT. By way of example, voltage sense network 28 is comprised of resistors 32 and 34 having terminals that are commonly connected together to form node 30. In addition resistor 32 has a terminal connected to output 18 and resistor 34 has a terminal connected to power return terminal 16. Voltage sensing network 28 may be any type of sensing network that provides sense signal VS at node 30 that is representative of the value of output voltage VOUT. A load 36 is generally connected between output 18 and terminal 16 in order to receive output voltage VOUT and to receive a load current ILOAD. It should be noted that load current ILOAD is the sum of current I24 and a current I26 that may flow from capacitor 26.
Switching power supply controller 12 receives operating power from a regulator 35 that is connected between a voltage input 38 and a voltage return 40. Input 38 and return 40 typically are connected to respective terminals 14 and 16. It should be noted that regulator 40 may provide reference voltage VREF. Controller 12 is configured to form a switching drive signal on an output 42 that is suitable for driving and operating transistor 20 to regulate the value of output voltage VOUT. Voltage sense signal VS from voltage sense network 28 is received by controller 12 on a voltage sense input 44.
Controller 12 includes a PWM control module 50 suitable for generating a PWM switching signal that is input into a buffer driver or buffer 52. Buffer 52 has an output terminal connected to a gate terminal of power transistor 20. Controller 12 further includes a feedback network 54 that comprises an operational amplifier 56 and a compensation network 58. By way of example, compensation network 58 is a passive voltage compensation network. More particularly, operational amplifier 56 serves as an error amplifier that has an inverting input terminal, a non-inverting input terminal, and an output terminal, where the non-inverting input terminal is coupled for receiving a reference voltage VREF, the inverting input terminal is coupled to its output terminal and to voltage sense node 44 through compensation network 58. By way of example, compensation network 58 is composed of a resistor 60 connected between the inverting input terminal of operational amplifier 56 and voltage sense node 44, and a resistor capacitor network 62 coupled between the inverting input terminal and the output terminal of operational amplifier 56. Resistor capacitor network 62 is comprised of a capacitor 64 coupled in parallel with a resistor 66 and a capacitor 68 which are connected in series. The output terminal of operational amplifier 56 is directly connected to an input terminal of PWM control module 50.
In operation, power supply system 10 typically operates in one of two operating modes: a continuous operating mode or a pulse skip (or burst) operating mode. Under a heavy or non-light load condition, PWM control module 50 operates at its nominal or full operating frequency and inductor current I24 is continuous. Under a light load or a no load condition, load current ILOAD decreases and inductor current I24 becomes discontinuous. If the pulse skip mode is enabled, the operating frequency or switching frequency at the output terminal of PWM control module 50 is reduced in response to the decrease in the loading current, thereby reducing power dissipation.
FIGS. 2a, 2b, 2c, and 2d are plots that illustrate various signals that are generated by controller 12 when it operates in a continuous operating mode. The abscissas of plots 2a, 2b, 2c, and 2d indicate time and the ordinates of plots 2a, 2b, and 2c indicate voltage, whereas the ordinate of plot 2d indicates current. More particularly, plot 2a illustrates the voltage VCOMP transmitted from the output terminal of operational amplifier 56 to the input terminal of PWM control module 50; plot 2b illustrates output voltage VOUT that appears between output 18 and terminal 16; plot 2c illustrates the voltage VSWN appearing at node 25; and plot 2d illustrates inductor current I24. In FIG. 2, controller 12 operates in the continuously pulsing PWM mode, thus inductor current I24 is continuous. Under this condition, operational amplifier 56 does not operate in saturation and there is little change in the DC bias of the capacitors of resistor capacitor network 62, i.e., capacitors 64 and 68. More particularly, in the steady state continuously pulsing mode of operation the DC bias across capacitor 68 is substantially equal to the difference between the average voltage level at the output terminal of error amplifier 56 during the continuously pulsing mode of operation and reference voltage VREF that appears at the non-inverting input terminal of error amplifier 56, i.e., VC68=VCOMP—AVG−VREF. In the pulse skipping mode, when output voltage VOUT is higher than reference voltage VREF, voltage VCOMP remains at its minimum level. Under this condition, the DC bias voltage across capacitor 68 is substantially equal to the difference between the minimum voltage value of voltage VCOMP and reference voltage VREF, i.e., VC68=VCOMP—MIN−VREF.
When there is a step-up load transience, voltage VCOMP increases to a value that is substantially equal to the average voltage level at the output terminal of error amplifier 56. Because the DC bias voltage across capacitor 68 cannot change instantaneously, a voltage difference substantially equal to VCOMP−VC68−VREF is added across resistor 66, which causes a droop current to be injected into node 59 and through resistor 60. Voltage VC68 is the voltage across capacitor 68. The additional droop current results in an additional voltage droop and a longer time for output voltage VOUT to recover.
FIGS. 3a, 3b, 3c, and 3d are plots that illustrate various signals that are generated by controller 12 when there is a step-up load transience, the skip mode is enabled, and controller 12 has been operating in the skip mode. The abscissas of plots 3a, 3b, 3c, and 3d indicate time and the ordinates of plots 3a, 3b, and 3c indicate voltage, whereas the ordinate of plot 3d indicates current. More particularly, plot 3a illustrates the voltage VCOMP transmitted from the output terminal of operational amplifier 56 to the input terminal of PWM control module 50; plot 3b illustrates the output voltage VOUT appearing between output 18 and terminal 16; plot 3c illustrates the voltage VSWN appearing at node 25; and plot 3d illustrates inductor current I24 and load current ILOAD.
Because controller 12 went into the skip mode of operation, the system transient response is degraded due to the DC level deviation in feedback network 54.
Accordingly, it would be advantageous to have a method and a power supply controller with a fast transient response under heavy and light loading conditions. It would be of further advantage for the circuit and method to be cost efficient to implement.