This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
Conventional programmable devices, such as field-programmable gate arrays (FPGAs), are capable of communicating with external devices using different signaling schemes having various voltage levels, e.g., 1.2V, 1.5V, 1.8V, 2.5, and 3.3V. To handle incoming signals at these different voltage levels, conventional FPGAs are implemented with programmable input buffers that can be selectively programmed to operate at different voltage levels. In addition to a core power supply VCC and an input/output (I/O) power supply VCCIO, some FPGAs include an auxiliary power supply VCCAUX of 3.3V or 2.5V. For a programmable device having VCC, VCCIO, and VCCAUX power supplies, an input buffer might have three different buffer stages: a VCC-powered buffer stage designed to be programmably selected to handle low-voltage signaling (e.g., 1.2V), a VCCIO-powered buffer stage designed to be programmably selected to handle mid-voltage signaling (e.g., 1.5V and 1.8V), and a VCCAUX-powered buffer stage designed to be programmably selected to handle high-voltage signaling (e.g., 2.5V and 3.3V).