1. Field
The following description relates to an equal model conservation technique for a pipeline processor.
2. Description of the Related Art
An instruction is processed at several stages in a pipeline processor. For example, an instruction may be processed at a fetch stage, a decoding stage, an execution stage, and a write-back stage. In the pipeline processor, because a plurality of instructions sequentially pass through the individual stages of the pipeline while overlapping each during execution, programs can be processed at high speeds.
Examples of a pipeline processor include an equal model processor and a less-than-or-equal (LTE) processor. In the pipeline processor, a maximum latency may be set for each instruction. For example, a value of maximum latency for each instruction may depend on a processor type.
“Maximum latency” indicates a maximum time period for which an operation corresponding to each instruction is executed and the result of the execution is written in a target register. In the equal model processor, the result of the execution of an instruction is written in the target register after the set maximum latency elapses. Meanwhile, in the LTE model processor, the result of execution of an instruction may be written in the target register before set maximum latency elapses. Accordingly, the equal model processor allows flexible scheduling through multiple assignment of a target register because the result of the execution of an instruction is not written in the target register until maximum latency elapses. Alternatively, in the LTE model processor, because the result of execution of an instruction can be written in a target register before maximum latency elapses, multiple assignment of the target register is limited.