Electronic equipment such as mobile phones containing semiconductor devices has been reduced in size and power consumption in recent years. Accordingly, there is a demand for reduction in power consumption in semiconductor devices.
It is effective for reducing power consumption to decrease power supply voltages. Decreasing power supply voltages also decreases leakage current, which results in reduction in power consumption. However, decreasing power supply voltages uniformly also decreases available clock frequencies and hence the operating speed. Therefore, multi-supply-voltage semiconductor devices operating at multiple voltages are used in which the power supply voltage supplied to blocks can be independently changed in such a manner that blocks that do not require a fast operating speed from among the blocks constituting the semiconductor device are supplied with a low power supply voltage and blocks that require a fast operating speed are supplied with a high power supply voltage.
In a stand-by state, leakage current can be minimized and consequently the power consumption can be reduced by supplying a power supply voltage only to blocks that need to be supplied with the power supply voltage.
The term multi-supply-voltage semiconductor device as used in the following description refers to semiconductor devices that operate on multiple power supplies having different voltage values supplied from multiple power supply systems as well as semiconductor devices that operate on multiple power supplies having the same voltage value supplied from multiple power supply systems and semiconductor devices that operate on a single power supply system whose power supply voltage changes.
In conventional semiconductor devices consisting of multiple blocks, some or all of the blocks have independent clock circuits, each of which drives a clock signal used within each block in accordance with a clock signal provided from a common clock generator circuit provided for the multiple blocks. However, when a clock signal is driven within each block, clock skew can occur within each block due to timing disagreement in driving the clock signals in the blocks. Such clock skew between blocks can cause a problem of disagreement in signaling timing between blocks. Therefore, semiconductor devices consisting of multiple blocks use a delay circuit to adjust the timing of a common clock signal inputted into the blocks to control clock skew between the blocks.
FIG. 1 shows a configuration of a conventional multi-supply-voltage semiconductor device that uses such a delay circuit to inhibit clock skew between blocks. The conventional multi-supply-voltage semiconductor device includes two blocks 31, 32, clock (CLK) generator circuit 10, and delay circuit 120. For simplicity, the multi-supply-voltage semiconductor device consisting of two blocks 31, 32 will be described herein. However, semiconductor devices in practice may consist of more than two blocks.
Clock generating circuit 10 generates a clock signal and supplies it to blocks 31 and 32. The clock signal supplied from clock generator circuit 10 to block 32 is delayed by delay circuit 120 inserted between them, and a clock delayed by a certain amount of time from the clock signal generated by clock generator circuit 10 is provided to block 32 as its clock signal.
Block 31 includes clock circuit 41 and flip-flop (F/F) circuits 51, 52. Block 32 includes clock circuit 42 and flip-flop circuits 62, 63.
Clock circuit 41 of block 31 drives clock signal CLK1 to be supplied to the circuits within block 31 based on a clock signal from clock generator circuit 10. Clock circuit 42 of block 32 drives clock signal CLK2 to be provided to the circuits within block 32 based on a clock signal delayed by a given amount of time by delay circuit 120.
In such a multi-supply-voltage semiconductor device, proper operation must be guaranteed at all operating points even though the device uses a variable power supply which supplies a power supply voltage changing within a certain range as a power supply. That is, the block circuits (clock circuits and arithmetic circuits) must be designed in such a manner that a clock skew is smaller than a signal propagation delay at all power supply voltages, conversely, a signal propagation delay is larger than a clock skew.
Clock skew between blocks 31 and 32 can be suppressed by using delay circuit 120 that provides a certain amount of delay, unless the amount of delays of clock circuits 41, 42 between blocks 31 and 32 changes depending on the voltage value of variable power supply 101.
For example, in the conventional multi-supply-voltage semiconductor device shown in FIG. 1, the clock skew between blocks 31 and 32 can be suppressed by setting the amount of delay of delay circuit 120 such that clock signal CLK1 outputted from clock circuit 41 is in phase with clock signal CLK2 outputted from clock circuit 42.
However, if the amounts of delay of clock circuits 41, 42 of blocks 31, 32 do not agree with each other in power supply voltage dependency, a problem arises that a change in the power supply voltage of variable power supply 101 changes each clock circuit delay, increasing the clock skew between the blocks significantly.
This problem is more considerable especially if a technique called multi-Vt is used in which MOS transistors with different thresholds (Vt) are formed on the same semiconductor device or if a technique called multi-Tox is used in which MOS transistors having different gate oxide thicknesses (Tox) are formed on the same semiconductor device, because the amounts of delay of clock circuits 41, 42 of blocks 31, 32 differ considerably in power supply voltage dependency from each other.
For example, suppose that the power supply voltage dependencies of the amounts of delays of clock circuits 41, 42 shown in FIG. 1 have characteristics as shown in FIG. 2. Even if delay circuit 120 is set so as to prevent clock skew between the blocks at voltage A of variable power supply 101, a delay difference will be produced and therefore clock skew between the blocks will increase when the power supply voltage of variable power supply 101 is changed to voltage B.
The timing chart in FIG. 3 shows the operation of clock circuits 41, 42 in such a conventional multi-supply-voltage semiconductor device. Referring to the timing chart in FIG. 3, it can be seen that the clock skew which is minimal at voltage A of variable power supply 101 becomes substantial after the supply voltage of variable power supply 101 is changed to voltage B.
Further, as mentioned earlier, some multi-supply-voltage semiconductor devices use both of a non-variable power supply and a variable power supply. FIG. 4 shows a multi-supply-voltage semiconductor device including a block into which a non-variable power supply is inputted and a block into which a variable power supply is inputted. In FIG. 4, non-variable power supply 102 is inputted into block 41 and variable power supply 101 is inputted into block 42. If a different power supply voltage is inputted, a signal with a different level is outputted. In order to accommodate the voltage difference, level shifters 71-73 are provided for signals between blocks 31 and 32. In a multi-supply-voltage semiconductor device as shown in FIG. 4, the power supply voltage of clock circuit 42 in block 32 changes as the supply voltage of variable power supply 101 changes, as shown in FIG. 5. Consequently, clock skew between block 32 and block 31 supplied with different power supplies increases significantly.
A variety of methods have been proposed for reducing clock skew. Japanese Patent Laid-Open No. 11-39868 discloses, for example, a method for reducing clock skew in a semiconductor integrated circuit system consisting of multiple IC chips. In the semiconductor integrated circuit system, one IC chip is classified as a master chip and the others as slave chips. The master chip detects a change in conditions such as a power supply voltage change and indicates the detected change to each of the slave chips. Each slave chip then adjusts the phase of its clock according to the indicated information about the detected change.
Since the conventional semiconductor integrated circuit system consists of multiple IC chips, it has a configuration different from that of a multi-supply-voltage semiconductor device in which multiple blocks are formed on a single chip. If the method described above is to be applied to a multi-supply-voltage semiconductor device, a circuit for detecting a change in the power supply voltage and wiring from the circuit to each block are required. In particular, because a multi-supply-voltage semiconductor device has multiple power supply systems, the device requires a circuit for detecting a change in the power supply voltage of each of those power supply systems. Therefore, the number of circuit conductors increases with the number of blocks that are included and power supply voltage systems that are used, which makes it impractical to use this method for high-density semiconductor devices.
The conventional multi-supply-voltage semiconductor devices as described above use a delay circuit to control the amount of delay to reduce clock skew at a particular power supply voltage and therefore have the problem that clock skew between blocks increases as the power supply voltage changes if the amounts of delay of each clock circuit provided in each block have a different power supply voltage dependency.