Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same and, more particularly, to a three-dimensionally (3-D) structured nonvolatile memory device and a method of manufacturing the same.
A nonvolatile memory device retains stored data although the supply of power is blocked. As 2-D structured memory devices including memory cells fabricated in a single layer on a silicon substrate reach the limit in increasing the integration degree thereof, there is proposed a 3-D structured nonvolatile memory device in which memory cells are vertically stacked on a silicon substrate.
The structure and features of a conventional 3-D nonvolatile memory device are described below with reference to FIG. 1.
FIG. 1 is a cross-sectional view illustrating the structure of a conventional 3-D nonvolatile memory device.
As shown in FIG. 1, the conventional 3-D nonvolatile memory device includes channels CH protruding from a substrate 10 and a plurality of memory cells MC vertically stacked along the channels CH. The memory device further includes a lower selection gate LSG formed under the plurality of memory cells MC and an upper selection gate USG formed over the plurality of memory cells MC. Bit lines BL are provided over the upper selection gate USG and coupled to the channels CH. In this structure, a plurality of memory cells MC coupled in series between the lower selection gate LSG and the upper selection gate USG form one a cell string STRING, and the cell strings STRING are arranged on the substrate 10.
In FIG. 1, reference numerals 11, 14, and 17 denote interlayer insulating layers, reference numeral 12 denotes a lower selection line, reference numerals 15 denote word lines, and reference numeral 18 denotes an upper selection line. Furthermore, reference numerals 13 and 19 denote gate insulating layers, reference numeral 16 denotes a charge blocking layer, a charge trap layer, and a tunnel insulating layer.
A method of forming the memory cells MC is described below in short. First, after alternately forming a plurality of conductive layers and a plurality of interlayer insulating layers, trenches are formed by etching the plurality of conductive layers and the plurality of interlayer insulating layers. After forming the charge blocking layer, the charge trap layer, and the tunnel insulating layer 16 on the inner walls of the trenches, a channel layer is filled within the trenches. In this manufacture process, the charge trap layers of the plurality of memory cells MC stacked along each of the channels CH are coupled.
Here, the charge trap layer functions as a substantial data depository for storing data through the injection or discharge of electric charges into or from the data depository. Accordingly, in the conventional structure in which the charge trap layers of the memory cells MC are coupled, data stored in memory cells MC may be lost because electric charges stored in one memory cell MC move to another memory cell MC. For example, if the charge trap layer is formed of a Si-rich nitride layer, stored data may be lost because electric charges stored in the charge trap layer move. In order to prevent the stored data from being lost, the charge trap layer may be made of stoichiometric nitride. If the charge trap layer is made of stoichiometric nitride, however, an erase operation speed may be slow.