To respond a requirement of increase in withstanding voltage and decrease in on-resistance (or decrease in on-voltage) of a semiconductor device, a semiconductor device having the SJ structure has been developed, and in particular a semiconductor device having the SJ structure in both of the cell region and the terminal region is actively developed. The SJ structure is provided in not only in the cell region but also in the terminal region, thereby a depleted region (meaning an expansion area of a depletion layer when the semiconductor device is turned off) can be formed in a wide area of the terminal region, and consequently withstanding voltage of both of the cell region and the terminal region can be improved.
This type of semiconductor device is often formed by using a semiconductor stack in which a semiconductor lower-layer and a semiconductor intermediate-layer are stacked. In the semiconductor intermediate-layer, the SJ structure is formed. In many cases, when the semiconductor stack is seen in a plane view, the cell region in which a vertical semiconductor-switching-cell group is built is provided in a central side of the semiconductor stack, and the terminal region is provided around the periphery of the cell region.
A plurality of vertical switching cells is formed in the cell region. For example, in the case that the vertical semiconductor switching cell is MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the semiconductor lower-layer is called a drain layer, and a drain electrode is connected to the drain layer. When the vertical semiconductor switching cell is IGBT (Insulated Gate Bipolar Transistor), a collector layer in an opposite conduction type is provided on a back of the semiconductor lower-layer, and a collector electrode is connected to the collector layer. When a gate structure of the vertical semiconductor switching cell is in a planar type, a body region is formed in an upper region of the SJ structure, and a planar gate electrode is formed opposite to the body region. Alternatively, when the gate structure of the vertical semiconductor switching cell is in a trench type, a semiconductor upper-layer in a conduction type opposite to the semiconductor lower-layer is formed on a surface of the SJ structure, and a trench gate electrode that penetrates the semiconductor upper-layer is formed.
An avalanche resistance check of a semiconductor device is often carried out by an L-load surge resistance test and the like. In the L-load surge resistance test, excessive energy is supplied to the semiconductor device to forcibly induce breakdown. The breakdown is induced in a region of more than critical electric-field strength. Considering an area ratio between the cell region and the terminal region, breakdown is induced in a side of the cell region having a larger area, thereby avalanche energy per unit area can be reduced compared with a case that breakdown is induced in a side of the terminal region having a smaller area. Therefore, if breakdown is induced in the cell region side, local consumption of excessive avalanche energy can be suppressed, consequently occurrence of breakdown of the semiconductor device can be suppressed. To realize the phenomenon, withstanding voltage of the terminal region must be made high compared with standing voltage of the cell region, so that breakdown is induced dominantly in the cell region.
JP-A-2003-273355, which corresponds to US 2005-0098826-A1 and U.S. Pat. No. 6,844,592, proposes a semiconductor device in which an insulating layer and a field plate are provided on a surface of the SJ structure in the terminal region. Furthermore, it proposes a structure in which thickness of the insulating layer is increased stepwise from the side of the cell region to the side of a region opposite to the cell region.
When a combined structure of an insulating layer and a field plate is provided in the terminal region, an electric field in an upper region of the terminal region can be reduced. While the above prior art does not describe the following operation and effects in detail, when an insulating layer whose thickness is increased stepwise is used, an electric field near a boundary between the cell region and the terminal region, in which the electric field tends to be concentrated, can be reduced. It has been found from study of the inventors that an insulating layer which was adjusted to be thin is formed in the cell region side, thereby a significant effect of reducing the electric field near the boundary between the cell region and the terminal region is obtained. Thus, breakdown of the semiconductor device due to local concentration of the electric field can be avoided.
However, as described before, in this type of semiconductor device, it is important that a relationship of “terminal region>cell region” is established between the withstanding voltage of the cell region and the withstanding voltage of the terminal region. The withstanding voltage of the cell region and that of the terminal region are mainly determined by height in a thickness direction of depleted regions formed in respective regions if the breakdown due to the local concentration of the electric field does not occur. In the semiconductor device of the above prior art, the height in the thickness direction of the depleted regions formed in both the cell region and the terminal region corresponds to height in the thickness direction of SJ structures formed in both. The height in the thickness direction of the cell region is equal to that of the terminal region. Therefore, the semiconductor device of the patent literature 1 has a limitation in that the withstanding voltage of the terminal region can be made equal to the withstanding voltage of the cell region at the maximum, or can not be made high compared with the withstanding voltage of the cell region.