This relates to the protection of integrated circuits from electrostatic discharge (ESD). More particularly, it relates to the protection of differential circuits from ESD.
ESD protection has been a main concern in the reliability of integrated circuit products in various sub-micron technologies. ESD is the transient discharge of static charge that can arise from activities such as human handling, machine contact or field-induced charging of a packaged IC. Specific models have been developed to represent these discharges such as the Human Body Model (HBM), the Machine Model (MM), and the Charged Device Model (CDM), respectively. See, for example, A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, pp. 17-40 (2d Ed., Wiley, 2002), which is incorporated herein by reference.
FIG. 1 is a schematic diagram of an illustrative differential circuit 100 with conventional ESD protection circuitry. Differential circuit 100 comprises first and second transistors 110, 130, a clamp transistor 150 and a diode 170. Illustratively, first and second transistors 110, 130 are a low voltage differential signaling (LVDS) output pair. Each transistor 110, 130, 150 is a MOS transistor with a source and drain formed in a body of the transistor and an insulated gate over the body in the region between the source and drain. In the schematic diagram of FIG. 1, the bodies of transistors 110, 130, and 150 are identified as elements 112, 132, 152; the sources are identified as elements 114, 134, 154; the drains are identified as elements 116, 136, 156; and the gates are identified as elements 118, 138, 158, respectively. Sources 114 and 134 are connected together at a source node 190. Resistors 120, 140, 160 are schematic representations of the circuitry between gates 118, 138, 158, respectively, and a common node 180; and resistor 182 is a schematic representation of the circuitry between source node 190 and common node 180. As is known in the art, the actual circuitry represented by these resistors may be considerably more complicated than a simple resistance. Input terminals 122, 142 are connected to gates 118, 138, respectively; and output terminals 124, 144 are connected to drains 116, 136, respectively. Diode 170 may be implemented as a dedicated diode or as the body diode of a MOSFET clamp transistor similar to transistor 150 or as both devices connected in parallel.
As is known in the art, the differential circuit typically comprises several other circuit elements not shown in FIG. 1. For example, transistor 110 is typically driven by circuitry connected to input terminal 122. Additionally, other circuits are connected to output terminal 124 to pull this node up when transistor 110 is in the off state.
Typically, the transistors of differential circuit 100 are NMOS transistors with a P-type body and N-type source and drain regions. As a result, since the P-type body and the N-type source region of each transistor form a first P-N junction and the P-type body and the N-type drain region form a second P-N junction, a parasitic lateral bipolar transistor is present in each transistor. In the event of a positive voltage ESD event on the output terminal 124, circuit 100 is intended to operate so that the second P-N junction of clamp transistor 150 is driven into breakdown and avalanche and the parasitic transistor is triggered into conduction to discharge the ESD pulse.
However, during the ESD event, the body voltage of transistors 110 and 130 can easily float above the source voltage, also making possible bipolar triggering of transistors 110 and 130. For example, as shown in the voltage vs. time plot of FIG. 2A, in the case of a positive ESD event on output terminal 124, the voltages on nodes 180 and 190 will both rise until the voltage on node 180 reaches the threshold voltage of transistor 130 at time t1. Transistor 130 then begins to pull down the voltage at node 190 while the voltage at node 180 is basically pinned at one Vbe above ground by diode 170. While the voltage on node 190 keeps decreasing, the avalanche current in transistor 110 and the voltage at output terminal 124 keep increasing. Eventually, destructive bipolar triggering will occur in transistor 110 when the body-source junction becomes fully forward biased at time t2 leading to a rapid drop in the output voltage. To prevent this, the clamp transistor 150 must trigger before it happens; but it is difficult to assure consistent, timely triggering without significant additional circuitry.