1. Field of the Invention
The present invention relates to the technical field of integrated circuits and, more particularly, to an engineering change order (ECO) hold time fixing method.
2. Description of Related Art
Due to a wide range of dynamic variations, e.g., supply voltage droops, process variations, temperature fluctuations, soft errors, and transistor aging degradation, the timing characterization is extremely difficult in modern IC designs. Therefore, in conventional design, designers conservatively reserve a timing guardband to ensure correct functionality even under the worst-case circumstance. However, this reserved guardband may severely degrade circuit performance, i.e., limit the clock frequency.
Accordingly, several resilient circuits have been proposed to eliminate the guardband by error detection and correction. For example, a Razor flip-flop (FF) is used as an error detection circuit (See D. Ernst et al., “Razor: a low-power pipeline based on circuit-level timing speculation” MICRO, pp.7-18, 2003). FIG. 1 illustrates a conventional Razor FF used as the error detection circuit. As shown in FIG. 1, the error detection circuit has an extra storage element, i.e., the shadow latch 110, to sample the output of a combinational logic 120 by a delayed clock clk_dly. The output of a main flip-flop 130 is compared with the output of the shadow latch by a comparator 140, i.e., an XNOR gate. When the comparison result indicates a detected timing error, a timing error signal is generated, and the error correction is performed through an instruction replay.
However, these resilient circuits require a significant hold time margin for short paths. Taking the circuit of FIG. 1 as an example, the resilient circuit may detect a false timing error if the result of the next computation is propagated through a short path and sampled by the delayed clock. To avoid such false error detection, the short paths have to exceed an error detection window w, i.e., the phase difference between the normal clock clk and the delayed clock clk_dly. The error detection window w causes an extra hold time margin requirement. This issue also exists in the resilient circuits proposed in other articles. Due to the extra hold time margin requirement, the short path padding or hold timing fixing in the resilient circuits becomes more challenging.
To resolve this padding problem, prior works typically insert buffers to lengthen the short paths.
Among the prior works, the delay padding is combined with a clock skew scheduling to minimize the clock period at the logic re-synthesis stage. The goal is to determine the padding path for each path rather than to decide where to insert the delay.
By contrast, another short path padding method determines the positions to insert the delay. This problem is solved by a linear programming proposed in N. V. Shenoy et al. “Minimum padding to satisfy short path constraints.” ICCAD, pp.156-161, 1993. However, such linear programming is time-consuming and not applicable to large-scale circuits. Hence, another prior art provides greedy heuristics. One greedy rule is to pad the gate with the largest setup slack for trying not to hurt the longest path delay. The other is to pad at the gate passed by the most hold violating paths for trying to reduce the total padding delay.
FIG. 2 shows a flowchart of integrating timing error resilient circuits into a design. Because of considering the timing guardband, based on the logic synthesis and timing analysis of conservative clock period, the target clock period and the error detection window w are determined. Moreover, the invention proposes coarse-grained and fine-grained padding allocation methods to further achieve the derived padding values at physical implementation. Sth/Hth represents a ratio of the target clock period over the conservative clock period. The timing suspicious flip-flops, whose longest path delays exceed the target clock period, can be replaced by the resilient circuits. Before the replacement, the design is re-synthesized where the suspicious flip-flops are assigned with an extra hold time margin to cover the error detection window w. After the replacement, a placement and routing is applied. Because of the significant hold time margin, the hold violations may still exist in a placed and routed design. Finally, the short path padding is performed.
In addition, it is found that the cited greedy heuristics cannot pad the short paths well. FIGS. 3A-3D show typical short path padding. FIG. 3A gives an input design, where gates g1, g2, g3 incur hold violations. After iteratively padding delay on the gate either with the largest setup slack or with the most hold violating paths, the result is shown in FIG. 3B or 3C. From FIGS. 3B and 3C, it is found that the unresolved hold violation at gate g2 exists. However, all the hold violations can be cleaned by the padding way shown in FIG. 3D. Accordingly, it is clear that the padding based only on local views cannot pad all the short paths. Moreover, even an optimal padding solution is found, it may still fail at a physical implementation because the delay offered by buffers is fixed. For example, if one buffer offers either a 0.15-unit or 0.25-unit delay, the padding task still fails on gate g2.
Therefore, it is desirable to provide an improved hold timing fixing method to mitigate and/or obviate the aforementioned problems.