1. Field of the Invention
The present invention relates generally to methods of manufacturing semiconductor devices, and more specifically, to a method of forming a well region having a prescribed impurity concentration distribution in a region positioned under an isolation insulating film.
2. Description Of The Background Art
A typical example of a semiconductor device having MOS transistors formed on a main surface of wells formed on a semiconductor substrate is a complementary MOS device (hereinafter referred to as CMOS device). A CMOS device is characterized in that an n channel MOS transistor and a p channel MOS transistor are formed in a single semiconductor substrate. The power consumption of a CMOS device is advantageously very small, because DC current flowing between power supply terminals is very small. Now, the structure of a conventional CMOS device will be described as the background of the invention in conjunction with the drawings.
FIG. 43 is partly sectional view showing the structure of a conventional CMOS device. An n well 5 and a p well 6 having different conductivity types from each other are formed in a surface region of a p type silicon substrate 1. An isolation oxide film (field oxide film) 2 for element isolation is formed in a prescribed region on surfaces of n well 5 and p well 6. A p channel MOS transistor 50 is formed on a surface of n well 5. An n channel MOS transistor 60 is formed on a surface of p well 6. P channel MOS transistor 50 has a gate electrode 8, and a pair of p.sup.+ impurity regions 9a, 9b spaced apart from each other. N channel MOS transistor 60 has a gate electrode 8, and a pair of n.sup.+ impurity regions 10a, 10b spaced apart from each other. Note that although only one transistor is depicted in each of n well 5 and p well 6 in FIG. 43, a plurality of MOS transistors and other functional elements are formed in practice.
The CMOS structure is however susceptible to a latch up phenomenon in which excessive current flows across power supply terminals to break down elements. The latch up herein indicates a phenomenon in which pnp and npn parasitic bipolar transistors are formed in a CMOS device to constitute a pnp thyristor between power supply potential (V.sub.DD) and ground potential GND (V.sub.SS), and therefore current continues to flow between V.sub.DD and GND once extraneous noise is applied, resulting in breakdown.
FIG. 44 is a cross sectional view schematically showing a parasitic thyristor formed in a CMOS device the same as one described in conjunction with FIG. 43. In FIG. 44, if the impurity concentrations of n well 5 and p well 6 are low, voltage drop down (voltage drop down corresponding to resistors Rn, Rp) increases when some surge is applied and current flows across these well regions. Thus, the emitter-base regions of parasitic pnp bipolar transistor Q1 and parasitic npn bipolar transistor Q2 are biased. As a result, these parasitic transistors operate and the latch up phenomenon described above is likely to occur.
A so-called retrograde well structure with an increased impurity concentration at the bottom of well is employed for the purpose of improving the resistance against the latch up phenomenon. The retrograde well is usually formed by implanting impurity ions with high energy into a semiconductor substrate.
A method of forming a retrograde well by means of implanting impurity ions with a high energy into a semiconductor substrate is, for example, disclosed in John Yuan-Tai Chen, "Quadruple-Well CMOS for VLSI Technology, " IEEE Transactions on Electron Devices, vol. ED-31, No. 7, July 1984 and U.S. Pat. No. 4,633,289. FIGS. 45-49 are cross sectional views showing steps in the manufacture of a conventional retrograde well structure.
Referring to FIG. 45, a thick isolation oxide film 22 is selectively formed on a surface of a p type silicon substrate 1 so as to separate element formation regions. Isolation oxide film 22 is formed by means of LOCOS (Local Oxidation of Silicon). The LOCOS is a process of thermally oxidizing an underlying oxide film 3 having only a prescribed surface region exposed by a patterned nitride film. The formation of isolation oxide film 22 defines an active region in which MOS transistor and the like are to be formed. Underlying oxide film 3 is formed on the element formation region.
Then, as illustrated in FIG. 46, a region to form the p well is covered with patterned resist 41. Using patterned resist 41 as mask, phosphorus ions (P.sup.+) are implanted with high energy into silicon substrate 1 a number of times, changing the energy and the implantation amount. Thus, n type retrograde wells 51, are formed to have a first n type concentration peak position 51a at a deep position in silicon substrate 1 and a second n type impurity concentration peak position 51b under isolation oxide film 22. At the time, low energy ion implantation is not performed to prevent increase of the impurity concentration of the n type well in a shallow region up to about 1000 .ANG. in depth from the surface of silicon substrate 1.
As illustrated in FIG. 47, after removal of patterned resist 41, the n well region is covered with patterned resist 42. Using patterned resist 42 as mask, boron ions (B.sup.+) as p type impurity ions are implanted with high energy a number of times into silicon substrate 1, changing the energy and the implantation amount. Thus, p type retrograde wells 61, are formed to have a first p type impurity concentration peak position 61a at a deep position in silicon substrate 1, and a second p type impurity concentration peak position 61b under isolation oxide film 22. As in the above case, low energy ion implantation is not performed to prevent increase of the impurity concentration of the p type well in the vicinity of the surface of silicon substrate 1. Thereafter, as illustrated in FIG. 48, patterned resist 42 is removed away.
Finally as illustrated in FIG. 49, after removal of underlying oxide film 3, a gate oxide film 7 is formed again in the same region. Gate electrode 8 is formed on gate oxide film 7. A pair of p.sup.+ impurity regions 9a, 9b are formed spaced apart from each other with gate electrode 8 therebetween in n type retrograde well region 51. A pair of n.sup.+ impurity regions 10a, 10b are formed spaced apart from each other with gate electrode 8 therebetween in p type retrograde well region 61. Thus, a p channel MOS transistor 50 is formed in n type retrograde well region 51, while n channel MOS transistor 60 is formed in p type retrograde well region 61.
In the retrograde well regions thus formed, the region having first impurity concentration peak positions 51a, 61a formed at the deep positions of silicon substrate 1 is effective in preventing the latch up phenomenon. The region having second impurity concentration peak positions 51b, 61b functions as a channel stop region for element isolation.
As the size of elements such as a MOS transistor formed in a semiconductor substrate is reduced, the thickness of an isolation oxide film is reduced. More specifically, as the element isolation width is reduced from the order of micron to the order of submicron, the thickness of the isolation oxide film is reduced from about 5000 .ANG. to about 3000 .ANG..
The reason for the thickness of the isolation oxide film being reduced will be described. As the size of elements such as MOS transistor is reduced, the element isolation width should be reduced. More specifically, the element isolation width should be reduced to the order of submicron less than 1 .mu.m and further less than 0.5 .mu.m. In order to achieve such an element isolation width, a field oxidation treatment must be performed after patterning a nitride film to have an opening width less than 1 m.
Now, the relation between the thicknesses of isolation oxide films and the opening widths of nitride films when each isolation oxide film is formed under the same conditions will be described. The relation between the thickness of isolation oxide film and the opening width of nitride film under the same treatment conditions is disclosed in "Oxidation Rate Reduction in the Submicrometer LOCOS Process", IEEE TRANSACTIONS, Vol. ED-34, No. 11, Nov. pp. 2255-2259 1987.
According to this document, when a field oxidation treatment was performed using a nitride film having an opening width less than 1 .mu.m, it was demonstrated the thickness of the isolation oxide film was reduced as the opening width was reduced. This means that the thickness of the isolation oxide film is reduced as the element isolation width is reduced under the same oxidation treatment conditions. However, even in the case of a nitride film having a small opening width, the thickness of an isolation oxide film can be increased by prolonging time for treatment. Thus prolonging the time for treatment is however disadvantageous in view of reducing size, because bird's beaks are increased accordingly. In view of the foregoing, it is pointed that thickness of the isolation oxide film is reduced as the element isolation width is reduced.
FIG. 50 is a cross sectional view showing the state of the retrograde well structure shown in FIG. 49 in which the isolation oxide film is reduced. As illustrated in FIG. 50, isolation oxide film 23 is reduced in thickness as compared to isolation oxide film 22 in FIG. 49. Accordingly, second impurity concentration peak positions 51b, 61b forming the retrograde wells are formed at the positions closer to the surface of silicon substrate 1. This is because impurity ions are implanted into silicon substrate 1 through thin isolation oxide film 23, and second impurity concentration peak positions 51b, 61b formed as a channel stop region for element isolation are formed at the positions closer to the surface of silicon substrate 1. As a result, the impurity is diffused by thermal treatment, etc. in succeeding steps and is likely to reach the vicinity of the surface of silicon substrate 1. This adversely affects the transistor characteristics, especially substrate biasing effect on the surface of silicon substrate 1.
The substrate biasing effect herein indicates the effect in which the threshold voltage of an MOS transistor is changed by applying voltage to the silicon substrate in which the MOS transistor is formed. More specifically, the threshold voltage is proportional to the square root of the substrate bias voltage. The constant of proportion is defined as a substrate effect constant. The adverse effect upon the above-described substrate biasing effect indicates increase of the substrate effect constant.
FIG. 51 is a graph showing the relation between threshold voltage V.sub.th and substrate bias voltage V.sub.BS. When the thickness of an isolation oxide film is 5000 .ANG. and an impurity concentration peak position is present under the isolation oxide film, as illustrated in FIG. 51, the substrate effect constant K will be 0.2. In this case, even if substrate bias voltage V.sub.BS changes from 0 V to -5 V, the degree of change of threshold voltage Vth is relatively small. If, however, thickness of the isolation oxide film is reduced to about 2000 .ANG. as reduction of the size of elements proceeds and a retrograde well is formed to have an impurity concentration peak position under the isolation oxide film, an impurity is implanted to a shallow position from the substrate surface. Accordingly, the impurity diffuses due to thermal treatment in subsequent steps, resulting in increase of the impurity concentration in the vicinity of the substrate surface. As a result, the substrate effect constant K becomes as large as 0.5. Thus, slight change of a substrate bias voltage V.sub.BS results in great change of threshold voltage V.sub.th.
In this case, a bias voltage imposed state is encountered due to extraneous noise, even if bias voltage is not applied to the substrate. Therefore in a CMOS device having a retrograde well structure, when the isolation oxide film is reduced in thickness with reduction of the size of transistors, the threshold voltage of an M0S transistor is likely to change if bias voltage is supplied to the substrate or a bias voltage imposed state is attained due to some extraneous causes. Thus, as the thickness of the isolation oxide film is reduced, the impurity performing the retrograde well structure adversely affects the characteristic of the MOS transistors formed on the substrate surface.
A disadvantage encountered when a retrograde well structure is formed in a shallow portion of the above-described element formation region will be described in more detail in conjunction with FIGS. 52-55. These FIGS. 52-54 are cross sectional views showing manufacturing steps especially in view of the retrograde well structure. FIG. 55 is a view for use in illustration of how the substrate biasing effect is influenced when a retrograde well structure is formed in a relatively shallow portion in an element formation region.
Referring to FIG. 52, an isolation oxide film 102 is selectively formed in a main surface of p type semiconductor substrate 101. A first impurity concentration peak position 105a is formed by implanting impurity ion with a high energy through isolation oxide film 102. Then, referring to FIG. 53, an impurity is implanted into a second impurity concentration peak position 105b by implanting the impurity with energy the same as impurity implantation in the vicinity of the bottom surface of isolation oxide film 102. After the impurity is thus implanted, a prescribed thermal treatment is performed to form a second impurity concentration peak position 105b extending from the vicinity of the bottom surface of isolation oxide film 102 to the bottom of element formation region.
Since second impurity concentration peak position 105b is thus formed, the depth D of second impurity concentration peak position 105b under the element formation region is determined by the thickness t3 of isolation oxide film 102. More specifically, if the thickness t3 of isolation oxide film 102 takes a small value, second impurity concentration peak position 105b will be formed at a relatively shallow position in the element formation region. As a result, the substrate biasing effect in the element formation region is increased.
The reason for the increase of the substrate biasing effect by the formation of the second impurity concentration peak position at such a shallow position from the semiconductor substrate surface will be described. The threshold voltage Vth of a transistor is given by the following equation in Mitsumasa Koyanagi, Electronic Material Series Submicron Device I, MARUZEN KABUSHIKI KAISHA, pp. 4-8. ##EQU1## where V.sub.FB represents flat band voltage, .PHI..sub.F Fermi potential of substrate, V.sub.BS substrate bias voltage, and C.sub.OX oxide film capacitance. In the above equation, (2.multidot..epsilon..sub.S .multidot..epsilon..sub.0 .multidot.q.multidot.N.sub.A).sup./C.sub.OX is a coefficient called substrate effect constant. The substrate effect constant (K) is a coefficient representing the degree of modulation of V.sub.th by the substrate biasing. The dependence of the substrate biasing effect upon the impurity concentration of the substrate is due to acceptor concentration N.sub.A included in the above-described substrate effect constant. More specifically, increase of acceptor concentration N.sub.A in the region in which an inversion layer and a depletion layer are formed increases the value of threshold voltage V.sub.th.
FIG. 55 shows an MOS transistor having a conventional retrograde well structure. Referring to FIG. 55, a source region 114 and a drain region 113 are formed to define a channel region in an element formation region. A gate electrode 111 is formed on the channel region with a gate insulating film 112 therebetween. Voltage V.sub.D is applied to the drain region of the MOS transistor, and voltage V.sub.G is applied to gate electrode 111. Source region 113 is grounded.
Supplying prescribed voltages to drain region 113 and gate electrode 111 forms a depletion layer 110. In the vicinity of the region in which depletion layer 110 is formed, however, as illustrated in FIG. 55, the second impurity concentration peak position 105b of retrograde well structure 105 will be formed. This restricts depletion layer 110 from expanding, and as illustrated in FIG. 55, for example, the depletion region will be formed into a narrow depletion layer 110a. Thus, the depletion layer capacitance is increased, whereby the substrate biasing effect is increased accordingly.
More specifically, the formation of the impurity concentration peak position at a shallow position in the element formation region increases the accepter concentration in the vicinity of the region to form the depletion layer, thus increasing the substrate effect constant. The substrate effect constant takes the value of K shown in FIG. 51, and as the value of the substrate effect constant is larger, change of the threshold voltage V.sub.th is increased by supplying the substrate bias voltage. More specifically, the substrate biasing effect is increased.
Meanwhile, one method of forming a channel cut layer under an isolation oxide film is to previously implant an impurity for forming the channel cut layer into the isolation oxide film formation region and then to form the isolation oxide film. According to this method, the problem associated with the substrate biasing effect described above can be alleviated, but the problem of narrow channel effect is encountered. This will be described in conjunction with FIGS. 56-62. FIGS. 56-60 are cross sectional views showing manufacturing steps for forming an element isolation structure by which a channel cut layer is previously implanted with an impurity, and then an isolation oxide film is formed.
Referring to FIG. 56, an impurity is implanted to form a well in a p type semiconductor substrate 101, and a first impurity concentration peak 105a iis formed at a deep position in p type silicon substrate 101. Then, an oxide film 102a and a nitride film 103 are sequentially formed on a surface of p type silicon substrate 101. As illustrated in FIG. 57, resist 106 which is patterned into a prescribed form is formed on nitride film 103, and nitride film 103 is patterned into a prescribed form using resist 106 as mask.
Referring to FIG. 58, an impurity 104a is implanted to form a channel cut layer using the above-described resist 106 as mask. Then, referring to FIG. 59, after removal of resist 106, an isolation oxide film 102 is selectively formed by means of thermal oxidation treatment. Thus, channel cut layer 104 is formed under isolation oxide film 102. Subsequently, as illustrated in FIG. 60, nitride film 103 is removed away.
Now, referring to FIGS. 61 and 62, the problem of the narrow channel effect associated with the above-described structure will be described. FIG. 61 is a cross sectional view showing an MOS transistor having the above-described element isolation structure. FIG. 62 is a plan view showing the MOS transistor including the above-described element isolation structure. A cross section taken along line A--A in FIG. 62 corresponds to FIG. 61.
Referring to FIG. 61, an element formation region 109 is defined by isolation oxide film 102. channel cut layer 104 is formed to extend to the vicinity of the surface of element formation region 109. In this case, a substantial element formation region width W2 is smaller than a desired element formation region width W3 by the function of channel cut layer 104. More specifically, channel cut layer 104 is formed to enter element formation region 109 by the width of 2S, and the width of element formation region is reduced by the amount. The narrow channel effect is thus enhanced. When viewed two-dimensionally, this is as illustrated in FIG. 62. More specifically, channel cut layer 104 is formed around element formation region 109 to stick out from isolation oxide film 102. This narrows the substantial width of element formation region 109. The narrow channel effect thus become remarkable. In contrast, in the above-described retrograde well structure, the narrow channel effect described above is hardly encountered.