1. Field of the Invention
The present invention relates to a method of forming a single crystalline silicon layer, a structure including the same, and a method of fabricating a thin film transistor (“TFT”) using the same. More particularly, the present invention relates to a method of forming a single crystalline silicon layer with high crystallinity, a structure including the same, and a method of fabricating a TFT using the same.
2. Description of the Related Art
Since poly crystalline silicon (“poly-Si”) has higher mobility than amorphous silicon (“a-Si”), poly-Si is applied not only to flat panel displays (“FPDs”) but also to various electronic devices, such as solar batteries. However, poly-Si is inferior in mobility and uniformity to single crystalline silicon.
In particular, single crystalline silicon is useful to a system on panel (“SOP”) structure in which a system is disposed on a display panel. The single crystalline silicon has a mobility of 300 cm2/Vs or higher. The use of single crystalline silicon with a high mobility is advantageous to formation of a high-quality switching device for a display device.
However, formation of single crystalline silicon is not free from temperature limitations. That is, a process of forming single crystalline silicon cannot be performed at a temperature higher than a temperature which a base substrate, for example, a plastic substrate or a glass substrate, can resist.
A process of forming a silicon-on-insulator (“SOI”) wafer, which is called a “smart-cut process,” includes a high-temperature annealing process that reaches a temperature of about 1000° C. Specifically, the smart-cut process includes thermally oxidizing a bare wafer with a predetermined thickness, forming a boundary layer by implanting H+ ions beneath the surface of the wafer, bonding the wafer to an additional substrate and separating the boundary layer to leave silicon on the substrate to a predetermined thickness, and performing an annealing process at a high temperature.
In this smart-cut process, the thermal oxidization process is performed at a temperature of 900° C. or higher, and the annealing process is performed at a temperature of up to 1100° C. Thus, there is a strong likelihood that these high-temperature processes inflict great damage on the substrate. Accordingly, the conventional method of forming an SOI wafer places a limitation on materials of the substrate and applies thermal shock even to a selected material of the substrate, thus adversely affecting the performance of a device obtained from silicon.
Another method of directly forming single crystalline silicon on a substrate is disclosed in “Formation of Location-controlled Crystalline Silicon” by Paul Ch. van der Wilt et al, Applied physics letters 72(12), p. 1819, 2001. This method is directed at forming single crystalline silicon on a desired location.
Specifically, as shown in FIG. 1, an insulating layer 2 having a hole 2a with a predetermined pattern is formed on a glass substrate (or a plastic substrate) 1, and a silicon seed layer is formed in the hole 2a. However, according to this conventional method, the surface of a silicon layer 3 is not flattened around the hole 2a. Since the silicon layer 3 has an uneven surface, it is difficult to obtain single crystalline silicon with high crystallinity.