1. Field of the Invention
The present invention relates to a semiconductor memory device and a refresh method thereof.
2. Description of the Related Art
A dynamic random access memory (hereinafter, referred to as DRAM) is configured as one of semiconductor memory devices. A memory cell used in the DRAM is ordinarily composed of a charge storage capacitor and a MOSFET for controlling input/output to/from the capacitor. Although the information stored in the memory cell is represented by a form of charges stored in the capacitor, since the charges decrease as a time elapses, a refresh operation is necessary to update the stored information at every predetermined time (refresh cycle).
To effectively execute the refresh operation, the semiconductor memory device has a plurality of types of refresh operation modes. The refresh operation modes are, for example, a CBR (CAS before RAS refresh) mode for starting a refresh operation by inputting signals of CAS (column-address strobe) and RAS (row-address strobe), which are supplied from the outside, at a predetermined timing, a self-refresh mode for automatically executing a refresh operation to all the memory cells at a regular interval when the memory device is continuously placed in a waiting state during at least a predetermined period of time, and the like.
In addition to above mentioned refresh operations, a kind of refresh operation is also executed when an ordinary read/write operation is executed. That is, the contents, which are stored in all the memory cells connected to a word line selected to execute the read/write operation, are supplied to the bit lines connected to the memory cells, respectively, and, after the potentials of the bit lines are amplified by a sense amplifier, respectively, the stored contents are restored in the respective memory cells.
A current consumed in these refresh operations depends on time intervals (refresh cycle) of the refresh operations, and the refresh cycle must be increased to reduce the current to be consumed. However, when the refresh cycle is increased, the charges stored in each memory cell are reduced and written information may be lost. Further, a reduction rate of the charges stored in the memory cell depend on the temperature of the memory cell, and the charges tend to decrease faster at a higher temperature.
Accordingly, various countermeasures are employed to effectively execute the refresh operation at a low current consumption. For example, Japanese Unexamined Patent Application Publication No. 05-036274 discloses a technology of a self-refresh mode for executing a first refresh operation at a short refresh cycle and thereafter executing it at a long refresh cycle. Further, Japanese Unexamined Patent Application Publication No. 2002-373489 discloses a technology for setting a different refresh cycle in an automatic refresh operation and in a self-refresh operation in response to a command input to a memory device. Further, Japanese Unexamined Patent Application Publication No. 2002-343079 discloses a technology for measuring a temperature of a semiconductor chip and changing a refresh cycle according to the temperature of the chip.
As described above, a reduction rate of charges stored in a memory cell of a semiconductor memory device depends on temperature. Accordingly, to effectively execute a refresh operation at a low current consumption, it is preferable to execute a refresh operation at a short refresh cycle when a semiconductor device has a high temperature and at a long refresh cycle when it has a low temperature.
However, neither Japanese Unexamined Patent Application Publication Nos. 05-036274 nor 2002-373489 discloses an effective refresh method in consideration of a temperature change of a semiconductor memory device. Therefore, the problem of the effective refresh method in consideration of the temperature change of the semiconductor memory device remains unsolved. Further, the technology disclosed in Japanese Unexamined Patent Application Publication No. 2002-343079 copes with the temperature change of the semiconductor memory device. However, a temperature measuring unit must be newly provided to measure a temperature of a semiconductor chip, from which a new problem arises in that the configuration of the semiconductor memory device is made complex. Thus, a further improvement is desired to execute the refresh operation at a low current consumption in consideration of a temperature change of a semiconductor device.