With the recent digitization of communications, performance improvement such as enhancement in bit resolution and increase in conversion speed has been increasingly demanded of A/D converters (ADCs) used in the field of digital communications. With improvement in the performance of ADCs, however, the power consumption thereof often increases. For example, when it is attempted to increase the conversion speed of a sampling ADC, a large current must be fed to permit high-speed charge/discharge of capacitance elements for sampling of an input signal. Considering application of ADCs to mobile equipment such as cellular phones, power reduction will also be necessary in ADCs as well as the performance improvement.
As a high-performance, low-power ADC, a column parallel ADC (column ADC) composed of super-many sampling ADCs is known (see Non-Patent Document 1, for example). In a column ADC, in which hundreds to thousands of sampling ADCs operate in parallel, very high-speed A/D conversion capability can be attained as a whole even though a single sampling ADC is slow in operation.    Non-Patent Document 1: Yoshikazu Nitta et al., “High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor”, ISSCC 2006/SESSION 27/IMAGE SENSORS/27.5