1. Technical Field
This disclosure relates to a semiconductor memory device, and more particularly, to a multi path accessible semiconductor memory device for use in a portable communication system.
2. Description of the Related Art
In general, a semiconductor memory device having multiple access ports is called a multi port memory, and in particular, a memory device having two access ports is called a dual port memory. A typical dual port memory is an image processing video memory having a RAM (Random Access Memory) port accessible by a random sequence and an SAM port accessible only by a serial sequence.
Today, electronic systems are becoming ubiquitous in human life. For example, handheld phone or PDA (Personal Digital Assistant), etc., manufacturers have been produced multi processor systems having multiple processors as shown in FIG. 1 so as to obtain high speed functionality and smooth system operation.
Referring to FIG. 1, a first processor 10 is connected to a second processor 26 through a connection line L10. A NOR memory 14 and a DRAM 40 are connected to the first processor 10 through buses B1-B3. A DRAM 18 and a NAND memory 20 are connected to the second processor 26 through determined buses B4-B6. The first processor 10 may have a base band processing function or may perform a modulation and/or demodulation of communication signal. The second processor 26 may have an application function of processing communication data or performing play activity known as a game, etc. The NOR memory 14 has a NOR structure cell array configuration and the NAND memory 20 has a NAND structure cell array configuration. Both are nonvolatile memories having transistor memory cells that have floating gates, and are equipped to preserve and store data that should not be lost if power is removed. For example, such data includes device specific code of handheld instruments or configuration data. The DRAMs 40 and 18 function as main memories of processing data of processors 10 and 26.
However, in a multi processor system as shown in FIG. 1, DRAMs are each allocated to each processor. In addition, an interface, such as a UART (Universal Asynchronous Receiver/Transmitter), SPI (Serial Peripheral Interface), and SRAM (Static Random Access Memory), having a relatively low speed are used to access the DRAMs. Thus, it is difficult to obtain a satisfactory data transmission speed and complexity due to size is increased. Furthermore, cost increases because of configuring the memories. In addition, data needed by both processors 10 and 26 is transmitted through a data transmission channel L12, adding a delay of data transmission.
A scheme to reduce an occupied size, increase a transmission speed and reduce the employed number of memories is shown in FIG. 2. In FIG. 2, one DRAM 42 is connected with first and second processors 10 and 26 through buses B1 and B2, in contrast to the system of FIG. 1. In the structure of multi processor system of FIG. 2, to access to one DRAM 42 by both processors through two respective paths, two ports are required on the DRAM to be connected corresponding to the buses B1 and B2.
However, a DRAM according to a conventional art is a memory 1 having a single port PO as shown in FIG. 3. FIG. 3 illustrating a conventional structure of DRAM, a memory cell array includes first to fourth banks 3, 4, 5 and 6 each having a row decoder and a column decoder. An upper input/output sense amplifier and driver 13 is operatively connected to first bank 3 or third bank 5 through a multiplexer 11, 12. A lower input/output sense amplifier and driver 15 is operatively connected to a second bank 4 or fourth bank 6 through a multiplexer 13 or 28.
For example, when a memory cell within the first bank 3 is selected and data stored in the selected memory cell is read, an output operation of the read data is described as follows. First, a selected word line is activated, then data of a memory cell sensed and amplified by a bit line sense amplifier is transferred to a local input/output line pair 9 by an activation of corresponding column selection line CSL. Data transferred to the local input/output line pair 9 is transferred to a global input/output line pair 10 by a switching operation of first multiplexer 21. The second multiplexer 11, connected to a global input/output line pair 10, transfers data of the global input/output line pair 10 to the upper input/output sense amplifier and driver 13. Data sensed and amplified by the input/output sense amplifier and driver 13 is output to a data output line L5 through a path part 16.
However, when data stored in a memory cell of the fourth bank 6 is read, the data is output to an output terminal DQ, sequentially passing through multiplexer 24, multiplexer 28, lower input/output sense amplifier and driver 15, path part 16 and data output line L5. That is, DRAM of FIG. 3 has the structure that two banks share an input/output sense amplifier and driver, and is a single port memory in which the input/output of data is performed through one port PO. The DRAM 1 of FIG. 3 can be used in the system of FIG. 1, but it may be difficult or impossible to use in the multi processor system referred to in FIG. 2.
Referring to FIG. 4, illustrating a multi processor system 50, a memory array 35 is constructed of first, second and third portions. The first portion 33 of the memory array 35 is accessible only by a first processor 70 through a port 37. The second portion 31 is accessible only by a second processor 80 through a port 38. The third portion 32 is accessible by both of the first and second processors 70 and 80. The size of first and second portions 33 and 31 of the memory array 35 can be variously changed according to an operating load of the first and second processors 70 and 80. Furthermore, the memory array 35 may be a memory type or disk storage type.
To realize third portion 32 shared by the first and second processors 70 and 80 within the memory array 35 in the structure of DRAM, several difficulties arise. For example, a layout of memory regions and input/output sense amplifiers within the memory array 35, and a proper read/write path control technique require attention. In the read/write operation through respective ports an operating time interval must be shortened to obtain efficient port use permissions and a high data transmission speed.
As a result, there remains a need for an improved method and apparatus for sharing a shared memory region allocated within a DRAM memory cell array in a multi processor system having two or more processors, and to enable transmission of data between ports.