Microprocessors include one or more execution units that perform the actual execution of instructions. Superscalar processors include the ability to issue multiple instructions per clock cycle to the various execution units to improve the throughput, or average instructions per clock cycle, of the processor. However, the instruction fetch and decoding functions at the top of the microprocessor pipeline must provide an instruction stream to the execution units at a sufficient rate in order to utilize the additional execution units and actually improve the throughput. The x86 architecture makes this task more difficult because the instructions of the instruction set are not fixed length; rather, the length of each instruction may vary, as discussed in more detail below. Thus, an x86 microprocessor must include an extensive amount of logic to process the incoming stream of instruction bytes to determine where each instruction starts and ends. Therefore, ways are needed to improve the rate at which an x86 microprocessor can parse a stream of indistinct instruction bytes into distinct instructions.