The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to a dual channel complementary metal-oxide-semiconductor (CMOS) having common gate stacks.
In contemporary semiconductor device fabrication processes, a large number of semiconductor devices, such as n-type metal-oxide-semiconductors (NMOS) and p-type metal-oxide-semiconductors (PMOS), are fabricated on a single wafer. In a CMOS integrated circuit (IC), complementary and symmetrical pairs of these NMOS and CMOS transistors are used for logic functions. Complementing every NMOS with a PMOS and connecting both gates and both drains together greatly reduces power consumption and heat generation relative to other logic families. For example, in a CMOS IC a high voltage on the gates will only cause the NMOS to conduct, while a low voltage on the gates causes only the PMOS to conduct.