The fabrication of integrated circuits (ICs) involves the formation of features on a substrate that make up circuit components, such as transistors, resistors and capacitors. The devices are interconnected, enabling the IC to perform the desired functions. Interconnections are formed by forming contacts and conductive lines in a dielectric layer using, for example, damascene techniques. A damascene structure, for example, includes a via or contact hole in a lower portion and a trench in an upper portion. The via serves as a contact to a device while the trench contains the conductive line for connecting the device to, for example, other devices.
It is important for via contacts in an upper interconnect level to be coupled properly with the underlying conductive lines of a lower interconnect level. However, lithographic errors, such as via misalignment or develop critical dimension (DCD) which is larger than the desired CD, may result in via contacts being extended beyond or displaced from the underlying conductive lines. As a result, the separation distance between the via contact and the adjacent lower conductive line is reduced. This may lead to electrical shorts between the via contact above and the adjacent conductive line below. Moreover, via contacts which extend beyond or fails to land on the underlying conductive lines may cause electrical shorts to the layer beneath the lower conductive layer due to punch through. These phenomena adversely render the IC malfunction.
From the foregoing discussion, it is desirable to provide a device which is devoid of the above-mentioned problem, thus increasing the reliability of the IC. It is also desirable to provide a cost effective process for forming the device.