1. Field of the Invention
The present invention relates to a method for fabricating a dynamic random access memory (DRAM) cells and, more particularly, to a DRAM cells provided with a word line on bit line (WOB) type memory cell including a buried bit line structure.
2. Discussion of Related Art
A metal-oxide-semiconductor (MOS) type DRAM has a memory cell comprising one MOS transistor and one capacitor connected thereto. As developments have been made in DRAM device technique to achieve high integration and high speed response, each capacitor is shrunken to be of such a reduced size that the amount of charges stored in the capacitor is decreased. The decrease in the amount of charges results in soft errors that may destroy the content of memories. To overcome this problem, a method for increasing the occupied area of each capacitor has been proposed, in which storage nodes composed of polysilicon are formed in a semiconductor substrate in order to increase capacitance of the capacitor. The stacked capacitor according to this method is disposed on a transfer gate transistor and connected to a source or drain of the transfer gate transistor. Bit lines of the DRAM cell are normally composed of metal lines and disposed on an interlayer insulation layer over the word lines. The bit lines are connected to the source and drain regions of the transfer gate transistor through contact holes in the interlayer insulation layer (or a passivating insulation layer).
FIG. 1 is a plan view of a memory cell array of a DRAM according to a related art.
Referring to FIG. 1, in the surface of a semiconductor substrate 1 are formed a plurality of word lines 17a, 17b, 17c and 17d which run parallel with one another in rows, a plurality of bit lines 55 which run parallel with one another in columns, and a plurality of memory cells (MC) arranged at the respective intersections of the word lines and the bit lines. Each memory cell comprises one transfer gate transistor 53 and one capacitor 64. The transfer gate transistor 53 comprises a pair of source/drain regions 46 and 46 formed in the surface of the semiconductor substrate 1, and gate electrodes (word lines) 17b and 17c formed between the source/drain regions 46 and 46 with a gate insulation layer 15 interposed therebetween. A thick insulation layer is formed on the gate electrodes 17b and 17c. Subsequently, contact holes 29, 28 and 29 are formed in a predetermined portion of the insulation layer so as to reach the source/drain regions 46 and 46 of the transfer gate transistor 53.
Reference numerals 29 and 29 denote capacitor node contact portions and reference numeral 28 denotes a bit line contact portion. The contact holes 29, 28 and 29 formed by photolithography and the etching method are gap-filled with the plug of a conductive layer such as a doped polysilicon layer. The plug of the conductive layer is brought in contact with the semiconductor substrate 1 in the source and drain regions 46 and 46. A bit line contact hole 91 located over an element isolating insulation layer. In the memory cell array, the word lines have a predetermined width and arranged in parallel with a predetermined spacing from one another. The plural bit lines 55 running in parallel with one another in columns are isolated with an interlayer insulation layer or the like on the plural word lines 17a, 17b, 17c and 17d.
Now, manufacturing steps of the DRAM memory cell shown in FIG. 1 will be described with reference to sectional views of FIGS. 2A to 2L.
FIGS. 2A to 2L are cross-sectional views taken along the line A-A' of FIG. 1 showing the manufacturing steps of the DRAM memory cell.
Referring to FIG. 2A, an element isolating insulation layer 11 and a channel stopper region (not shown) are formed in predetermined regions on the main surface of a P-type semiconductor substrate 1. A gate insulation layer 15, a polysilicon layer 17 and an interlayer insulation layer 19a are sequentially formed on the surface of the semiconductor substrate 1.
The element isolating insulation layer 11 may be formed by a selective oxidation method such as a LOCOS (Local Oxidation of Silicon) method or other methods including STI (Shallow Trench Isolation). The gate insulation layer 15 is formed by the thermal oxidation method. The polysilicon layer 17 and the interlayer insulation layer 19a are each deposited to a thickness of 1000-2000 .ANG. by the CVD method.
Referring to FIG. 2B, word lines 17a, 17b, 17c and 17d are formed by photolithography and the etching method. The interlayer insulation layer 19a of the patterned oxide film is left on the surface of the word lines 17a-17d.
Referring to FIG. 2C, an insulation layer is formed on the whole surface of the semiconductor substrate 1 by the CVD method, and is etched by an anisotropic reactive ion etching (RIE) to form a sidewall spacer 20 on the peripheries of the word lines 17a-17d. Impurity ions 40, arsenic are implanted under an implantation energy 30 KeV, a dose of 4.0.times.10.sup.15 /cm.sup.2 in the surface of the silicon substrate 1 by using the word lines 17a-17d covered with the insulation layer 19a and the spacer 20 as masks to form the source and drain regions 46 and 46 of the transfer gate transistor.
Referring to FIG. 2D, the surface of the semiconductor substrate 1 is planarized with an interlayer insulation layer 26a e.g., a BPSG (Borophosphorosilicate Glass) film. Contact holes 31 and 33 are formed in the bit line contact portion 28 and the capacitor node contact portion 29 by photolithography and the etching method, which is followed by deposition of doped polysilicon. Then, polysilicon plugs 28 and 29 are formed in the contact holes by an etch-back method.
The plugs may be formed not only by the etch-back technique using the RIE but also by other methods including CMP (Chemical Mechanical Polishing).
Referring to FIG. 2E, an insulation layer 61 is deposited on the whole surface of the semiconductor substrate 1, isolating the plugs 28 and 29. Contact holes (not shown) are formed over the bit line contact portion 28. A conductive layer such as a doped polysilicon layer or a metal layer, and a metal suicide layer, etc. are formed on the surface of the semiconductor substrate 1, which are patterned by photolithography and the etching method. As a result, the bit lines (not shown) are formed.
Subsequently, an etching stopping layer 63 such as a nitride (Si.sub.3 N.sub.4) film having a thickness of more than 100 .ANG. is formed and then a silicon oxide (SiO.sub.2) film 65a having a thickness of more than 5000 .ANG. is formed on the surface of the nitride film 63.
Here, the bit lines are disposed above the element isolating insulation layer of the memory cell array and, in the perpendicular direction to the word lines, arranged in parallel with the active region of the memory cell array having two transfer gate transistors as MOS transistors formed thereon.
Referring to FIG. 2F, a capacitor isolating layer 65 for isolating the adjacent capacitors is formed by patterning the oxide film 65a by the etching method. The selective ratio of the etching of the nitride film 63 which is an etching stopping layer to the oxide film 65a is extremely high. Therefore, in this etching step, the nitride film 63 is etched at a rate different from that of the oxide film 65a.
Referring to FIG. 2G, contact holes 70 and 70 are formed so as to reach the plug of the capacitor node contact portion 29 on the source and drain regions 46 and 46 by photolithography and the etching method.
Referring to FIG. 2H, a polysilicon layer 72 of a thickness of 500-1500 .ANG. is deposited on an inner surface of the contact hole 70, on the surface of the nitride film 63 and on the surface of the capacitor isolating layer 65 by the CVD method. Then, a thick resist 75 is applied over a surface of the polysilicon layer 72.
Referring to FIG. 2I, the resist 75 is etched back to expose a part of the polysilicon layer 72.
Referring to FIG. 2J, the exposed surface of the polysilicon layer 72 is selectively removed by anisotropic etch or the like. As a result, the polysilicon layer 72 is isolated on the surface of the capacitor isolating layer 65 to form a lower electrode 80 of the capacitor.
Referring to FIG. 2K, the resist 75 is removed by the etching method and furthermore the capacitor isolating layer 65 is removed by a plasma etching method. Then, a dielectric layer 84 such as a nitride film is formed on the surface of the lower electrode 80.
Referring to FIG. 2L, an upper electrode 85 at a thickness of 2000-3000 .ANG. of a polysilicon layer is formed on the surface of the dielectric layer 84 by the CVD method. Thereafter, an insulation layer 88 and an interconnection layer 90 are formed to complete the manufacturing steps of the memory cell of the DRAM.
The memory cell of the DRAM according to the related art has the arrangement in which the plugs used as the capacitor node contact portion and the bit line contact portion are formed in the source and drain regions of the transfer gate transistor by photolithography and the etching method after the word lines are formed. These patterns in a linear arrangement are aligned to dispose between the transfer gates. This requires that the transfer gates be spaced farther apart than is otherwise desired to provide ample room between transfer gates for making desired contacts to active areas. Such increase in transfer gate pitch works against the integration of the memory cell. Another problem lies in that soft errors occur due to a parasitic capacitance, since the capacitor of memory cell adjoins the peripheries and the top portion of the bit lines.