The power FET has become a limiting component in many power management circuits used to regulate voltage and/or current in DC-DC converters, AC-DC inverters, or AC transformers. In recent decades, significant efforts have been made to boost the power FET's output currents and switching speeds to keep pace with the integrated circuit “transistor shrinks”. The smaller transistors increase system switching speeds and the transistor densities within an integrated circuit. Higher densities allow vastly more transistors to be incorporated into a single semiconductor chip, causing it to require larger operational currents. Similarly, smaller transistor dimensions also increase operational system speeds. Any inability to supply a combination of larger currents at higher switching speeds leaves many systems “under powered”. This is particularly the case in multi-core microprocessors where the inability to supply required current at suitably higher speed impairs reliable data transfer with external memory circuits. As a result of this deficiency, processor cores will typically operate at 25%-30% utilization rates. This problem becomes more acute when processor cores are configured in parallel. For instance, a 16 core microprocessor array will function slower than a 4 core microprocessor array due to in adequate power refresh cycling. Therefore, it is desirable to increase power efficiencies by developing power FETs that enable arbitrarily high currents to be switched at arbitrarily high switching speeds. While higher switching speed and current levels are of specific benefit to power FETs, methods that enable switching speeds above 400 MHz or over a distinct band of frequencies could be usefully applied to many other FET applications. Therefore, generalized methods to tune a FET's switching speed and/or current output is also desirable.
Co-location of high efficiency switched-mode power management devices with one or more processor cells also reduces the overall system power losses through much shorter interconnect circuitry. Methods and apparatus that improve the efficiency of supplied power to a processor core by co-locating power management in immediate proximity to computational die are therefore enabling and desirable to the enhanced utilization of microprocessor arrays and the improved operational efficiency of high-speed computational systems.
Most approaches to increase power FET switching speeds have focused on reducing the transistor gate capacitance. This is done generally by making the gate electrode smaller, and by using more sophisticated electronic doping configurations within the transistor junction. A significant drawback to these elements of the prior art is the generation of larger quantities of heat, which is undesirable and must be properly managed to safeguard the performance of neighboring semiconductor devices. While smaller gate structures lower capacitance, they also increase current densities flowing through the transistor junction to attain high currents, which, in-turn, increases generated heat to levels that prevent co-location of power management in close proximity to computational semiconductor die. Higher current levels often require thermal management mechanisms to be added to the system to drain the excess heat generated by the higher levels of resistive loss. Additional or more sophisticated thermal management requirements increase the cost and design complexity of the overall system. Prior art solutions advance improved doping topologies to reduce the ON-resistance of the power FET's transistor junction. However, the proposed solutions alone do not reduce ON-resistance to sufficiently low levels that allow power management systems to be monolithically integrated with or placed in close proximity to the active system devices, or to mitigate or eliminate thermal management devices from the power management system. This is a particular problem in power management systems that are assembled from discrete components. Therefore, it is also desirable to reduce the ON-resistance of a power FET by orders of magnitude to levels that mitigate or eliminate thermal management systems in a power management device.
Many power management systems are utilized in mobile platforms that are subject to frequent or unpredictable mechanical shock. Solder joints are used to electrically interconnect surface mounted passive components (resistors, capacitors, inductors) on a printed circuit board in electrical communication with one or more semiconductor die. Lead-free solders used to achieve modern environmental standards do not have the mechanical integrity of the lead-based solders they are replacing. Fractures in solder joints are the dominant cause for field failures in mobile systems. Additionally, solder joint failures in power management devices are the leading cause for grounding aircraft due to unscheduled maintenance. Therefore, methods that eliminate solder joints from a power management system by monolithically integrating all components on to a semiconductor die are also beneficial and a desirable objective of the present invention.