The present invention relates to semiconductor devices and, more specifically, to MOS gate controlled reference (MOS-gated) semiconductor devices formed using a reduced number of masking steps with no critical alignment.
MOS-gated devices are well-known in the art and include devices such as the MOS-gated devices described in U.S. patent application Ser. No. 08/299,533, filed Sep. 1, 1994 (IR-1113) U.S. Pat. No. 5,795,793, which is incorporated herein by reference. These devices include power MOSFETs, MOS-gated thyristors, insulated gate bipolar transistors (IGBTs), gate turn-off devices and the like.
The manufacturing processes for such devices typically include a number of lithographic masking steps which include critical mask alignment steps. Each of these critical alignment steps add manufacturing time and expense as well as provide possible sources of device defects.
It is therefore desirable to minimize or eliminate the number of critical alignments necessary as well as reduce the number of masking steps to improve the manufacturing yield and reduce the manufacturing cost.