1. Field of the Invention
The present invention generally relates to a semiconductor device structure and to a method of manufacturing the same, and more particularly, the present invention relates to a transistor having a hetero grain stack gate structure, and to a method of manufacturing the same.
2. Description of Related Art
Semiconductor devices such as field effect transistors (FETs) are becoming increasingly important in low voltage applications. As semiconductor devices are fabricated to have a higher degree of integration, a faster operating speed, and a lower power consumption, the magnitude or size of a complementary metal-on-semiconductor field effect transistor (CMOSFET) included in the device is rapidly reduced. As FET devices are scaled to smaller and smaller dimensions, manufacturers must refine transistor designs to maintain optimum device performance.
To control problems associated with a short-channel-effect (SCE) in a deep-submicron MOS transistor, a dual gate type CMOSFET design is widely used. The dual gate type CMOSFET has a surface channel in each of the NMOS and PMOS transistors, and a symmetric low threshold voltage (Vth). For example, with a currently-available conventional dual gate device, when the threshold voltage of the NMOS device is 0.5V, then the threshold voltage of the PMOS device is −0.5V. The dual gate type CMOSFET uses N+ and P+ polycrystalline (polysilicon) gate electrodes in the NMOS and PMOS transistors, respectively.
A conventional CMOSFET structure, and relevant steps of a method of manufacturing such a device, will be described with reference to FIGS. 1A-C as follows.
Referring to FIGS. 1A and B, a standard twin retrograded-well process is used to form an N-well 2n and a P-well 2p in the substrate 2 via a conventional photoresist masking and ion implantation process. In the N-well 2n and P-well 2p are formed lightly doped drain regions 16a and 74a, including halo doping profiles 16b and 74b respectively. On each of the N-well 2n and P-well 2p is formed a gate oxide layer 6p and a stacked gate electrode on top of the gate oxide layer 6p, including a thin polysilicon layer 8p and stacked polysilicon structure 73. Laterally adjacent to the gate electrode is a liquid phase deposition (LPD) oxide layer 18 and stacked polysilicon layers 72. Such a structure is then subjected to a heavy ion implantation using, for example, BF2+.
As shown in FIG. 1B, after doping for both the PMOS and NMOS transistors is complete, a thermal treatment is performed to condense then LPD oxide 18 and to activate the S/D implants. The thermal treatment diffuses the heavy implants in the polysilicon stack layers 72 into the substrate 2 to form the buried contacts and ultra-shallow junctions. Then a refractory metal layer 28, such as Ti, Co, W etc., is sputtered on the polysilicon stack layers 72 and the LPD oxide 18.
Turning to FIG. 1C, next a standard two-step silicidation process is performed, consisting of a rapid thermal annealing (RTA) to react the metal layer 28 with the polysilicon stack layer 72 to form a thin silicide layer 28a on the polysilicon stack layers 72. Then the unreacted metal is removed from the oxide using a standard wet etching process. A second RTA process is performed to transform the silicide's phase to a less resistive phase.
However, there are some problems with this conventional CMOSFET device.
In the PMOS transistor, when the thickness of the gate oxide layer 6p is less than 50 Å, boron implanted into the polysilicon gate electrode diffuses into the gate oxide layer 6p (Boron penetration). When this happens, the boron diffuses into the semiconductor substrate 2 and decreases the carrier mobility which causes a threshold voltage fluctuation. Due to the threshold voltage fluctuation, the threshold voltage Vth of the gate cannot be controlled, thereby degrading the characteristics of the PMOS transistor.
Also, even though the polysilicon gate electrode is over-implanted by ions, it is not a complete conductor. Therefore, during the operation of the MOS transistor, a depletion region may arise due to a depletion of the electric charges at an interface between the gate oxide layer and substrate. The depletion region of the polysilicon gate has a magnitude of several angstroms (Å) and acts as a connected gate oxide layer capacitor. If the thickness of gate oxide layer is small, the characteristics of the transistor are poor due to the polysilicon-gate-depletion region.
To address the boron penetration and the polysilicon-gate-depletion effect (PDE) problems, a method of replacing a conventional polycrystalline silicon (poly-Si) gate with a polycrystalline silicon germanium (poly-SiGe) gate has been proposed (see, e.g., IEDM Tech. Dig. 1990 pp. 253-256). The poly-SiGe gate structure can be manufactured by the conventional CMOS process and can control the boron penetration and the PDE problems discussed above.
Also, the work function of poly-SiGe is different from that of poly-Si, thereby increasing the threshold voltage of the device. Therefore, the amount of channel doping can be decreased, increasing the carrier mobility.
However, when the metal silicide layer of Ti or Co is formed on the gate structure (as described above with respect to FIGS. 1A-C), it is difficult to form it on the poly-SiGe layer compared with forming it on the poly-Si layer. Also, due to the penetration of Ge into the silicide layer, the resistivity of the poly-Si layer is rapidly increased, which is undesirable.
Therefore, in the CMOS device with the conventional poly-SiGe gate, a single poly-SiGe layer is not used, but instead a stacked gate structure having a lower polySiGe layer and an upper poly-Si layer is used. The upper poly-Si layer of the stacked gate structure facilitates the silicide process carried out during the CMOS fabrication to thereby increase the conductivity.
Generally, the poly-SiGe layer is formed by a CVD method using a source gas of SiH4 and GeH4. To improve the PDE and the boron penetration characteristics of the poly-SiGe PMOS transistor, it is desirable to form the poly-SiGe layer to have a Ge concentration of at least 20% (see IEEE Electron Device Letters, 10(7), 1998, p.247, by W. C. Lee et. al.). However, when the Ge concentration is more than 30% and is deposited by a chemical vapor deposition (CVD) method, the surface roughness abruptly deteriorates. If the concentration of GeH4 gas is increased to thereby increase the Ge concentration in the poly-SiGe layer, the roughness of the surface deteriorates proportionally to the increase in the GeH4 concentration. Therefore, it is difficult to carry out a subsequent photolithography process, and pits are generated in the substrate during a subsequent etching processes. Accordingly, it is known in the art that the Ge concentration of the poly-SiGe layer for use in the gate is preferably in the range of 20-30%.
After the sequentially stacked poly-SiGe and poly-Si layers are formed as a gate electrode, thermal processes such as gate re-oxidation, silicon nitride deposition, and activation annealing (described above with respect to FIGS. 1A-C) are carried out.
However, at this time Ge diffuses from the lower poly-SiGe layer into the upper poly-Si layer. Accordingly, the Ge concentration of the poly-SiGe layer is reduced from the original Ge concentration (see IEEE Electron Device, 47(4), 2000 p.848 by Y. V. Ponomarev). To account for the Ge diffusion, the Ge concentration in the poly-SiGe layer when it is formed may be set to more than 30%. However, as stated above, this undesirably increases the surface roughness. On the other hand, if the poly-SiGe layer is formed with a Ge concentration of 20-30%, the Ge concentration in the resultant PMOS transistor is reduced to less than 20% after the final CMOS process, thus having little or no effect in controlling the PDE or the boron penetration.
Therefore, there is a shortcoming in the conventional semiconductor device wherein the gate electrode has the stacked poly-SiGe and poly-Si layers.
Accordingly, it would be desirable to provide an improved semiconductor device having a stacked poly-SiGe and the poly-Si layer with reduced Ge diffusion. It would further be desirable to provide a method of manufacturing a semiconductor device having a stacked poly-SiGe and the poly-Si layer with reduced Ge diffusion.