Programmable logic arrays are well known. U.S. Pat. No. 4,124,899, for example, describes both the background and the uses of programmable logic arrays and field programmable logic arrays. U.S. Pat. No. 4,717,912 discloses an improved version of the programmable logic array described in U.S. Pat. No. 4,124,899 wherein an output cell is provided to allow a single circuit to be configured to simulate a programmable logic array having a combinatorial unregistered output lead or a registered output lead.
As is known in the programmable logic array art, one type of programmable logic array uses what is called an "X-type" output structure where the output signal is passed through an exclusive OR gate and stored in a register (See FIG. 2). Another type of programmable logic circuit uses what is called an "L-type" output structure and has a combinatorial unregistered output (See FIG. 1).
A typical logic output cell for a programmable logic array of the "L-type" is shown in FIG. 1. In FIG. 1, the seven logic signals PT0-PT6 are applied to OR gate 10. The output signal from OR gate 10 optionally is passed through an exclusive OR gate (not shown in FIG. 1) which acts as either a buffer or a programmable invertor for the signal before it reaches tristate output buffer 12. The output signal from buffer 12 is sent to terminal 14. Terminal 14 can be used either as an input path or an output path depending upon the state of tristate buffer 12. If tristate buffer 12 presents a high impedance in response to logic signal PT7 being low level, then terminal 14 functions as an input terminal and the input signal on terminal 14 is transmitted on leads 19 and 17 to buffer 13. Buffer 13 provides on output leads 18b and 18a, true and complemented versions, respectively, of the signal on lead 17 and terminal 14. The structure shown in FIG. 1 provides a logical combinatorial unregistered output signal on lead 19 when buffer 12 acts as a transmission gate for passing the output signal from OR gate 10 to output terminal 14. In this context, lead 17 and buffer 13 are part of a feedback path capable of providing the true and complement of the output signal on terminal 14 to selected points within the programmable logic array.
FIG. 2 illustrates an X-type output structure from a programmable logic array. As shown in FIG. 2, four input logic signals PT0-PT3 are applied in pairs to OR gates 31a and 31b. Logic signals PT0 and PT1 are applied to the two input leads to OR gate 31a and logic signals PT2 and PT3 are applied to the two input leads to OR gate 31b. The output leads from OR gates 31a and 31b are applied to the two input leads to exclusive OR gate 32. The output signal from exclusive OR gate 32 is applied to register 33 (typically a D-type flip-flop). The Q output signal from register 33 is passed through invertor 34 to the output terminal 36. The Q output lead from register 33 is fed back through buffer 35 which provides on output leads 37a and 37b, true and complementary versions of the signal on lead 33b, respectively.
The architectures of the output logic circuits with existing programmable logic arrays provide a number of different options to the designer. However, in many cases the use of one option as opposed to another requires the use of a different part or product. This can be a disadvantage if the user wishes to change the design after acquiring a substantial inventory of one type of product.