1. Field of the Invention
This invention relates to a multiple input restrictive logic OR circuit and more particularly to a high speed fully differential logic OR circuit with multiple non-overlapping inputs.
2. Description of the Related Art
When designing systems such as automated test equipment it is desirable to provide a high speed logic circuit which accepts numerous inputs and provides a single output, where only one input at a time is active and the output is active when one of the inputs is active. In such high speed applications, input-to-output propagation delays must be minimized while remaining uniform for each input. It is also desirable to minimize signal noise and interaction between circuit devices that may degrade the signal.
Differential logic OR circuits have been developed using known ECL technology such as the differential two input Motorola MC10EL05. However, these circuits commonly have only 2 or 3 inputs which suffer from different input-to-output propagation delays. In addition, to construct a logic OR circuit with more inputs, for example 8, several 2 or 3 input OR circuits must be coupled together in a tree structure. Such tree structures have different input to output propagation delays for the different inputs depending on the path taken through the logic tree. They also result in undesirable interaction between the multiple logic gates, which can degrade the signals.
A multi-input logic OR circuit could also be implemented with a "Wired-OR" circuit, in which single-ended input lines are combined to produce an "OR" output. An example of this approach is embodied in the Motorola MECL 10K 4 input wired-OR logic gate. This circuit has relatively low propagation delay and is generally symmetric with respect to propagation delay between input and output. However, its single-ended inputs make the circuit susceptible to jitter and makes propagation delay sensitive to environmental changes.
A multi-input logic OR circuit could also be implemented with a multiplexer that selects data from one of the multiple input lines and directs the data to a single output line. An example of this approach is embodied in the Motorola MC10H164 8-line multiplexer. The selected input line is activated by control lines and the number of control lines increases as the number of inputs increase. A four input multiplexer requires two control lines, while an eight input multiplexer requires three control lines. These circuits suffer from undesirable input-to-output propagation delays and experience an additional delay in the settling time of the control lines. The necessity for control lines makes this approach significantly more complex.