1. FIELD OF THE INVENTION
The present invention relates to an automatic layout apparatus and method of automatically selecting and laying out layout candidate elements in an analog LSI.
2. DESCRIPTION OF THE PRIOR ART
In an analog LSI layout design, a differential pair or current-mirror-connected bipolar transistors are laid out close to each other in consideration of the layout direction so as to satisfy the relative precision of element characteristics in order to satisfy the electrical characteristics of a circuit.
The feature in this case is common connection of emitters or bases. When a measure against crosstalk must be taken depending on a circuit arrangement, a layout in which lines need not be crossed is performed in a line design upon a layout design. When a measure against a heat source is necessary, a power transistor serving as the heat source and a signal system transistor having electrical characteristics changed by the heat must be laid out apart from each other.
Since the analog LSI layout design has many limitations including these items on the electrical characteristics of the circuit, it has manually been performed. However, as the analog LSI becomes larger in scale year by year, the design becomes more difficult to perform by the method of manually selecting layout candidate elements one by one such that the development period becomes longer. For this reason, the design period is tried to be shortened by, e.g., using the layout candidate element automatic selection function of an automatic layout/wiring apparatus used for a MOS or the like. Although layout candidate elements can be automatically selected by using the automatic layout/wiring apparatus, automatic selection is independent of the electrical characteristics and the intention of the layout designer because the automatic selection method is selection based on the element number order and selection based on the description order in a circuit information file. Accordingly, the layout designer must manually select elements again, so the design efficiency cannot be improved.
An example of a conventional layout flow in the use of the automatic layout/wiring apparatus will be described with reference to a flow chart shown in FIG. 1 and a circuit example shown in FIG. 6.
In the first step, connection information of a circuit shown in FIG. 6 is input (F-1). In the second step, an arbitrary element is manually selected and laid out (F-2). In this case, a transistor Q1 is selected and laid out. In the third step, a transistor Q2 is selected as a next layout candidate element in a tool of selecting elements in the element number order (F-3). Finally, in the fourth step, whether the transistor Q2 selected in the third step is proper is checked (F-4).
Since a transistor Q6 constituting a differential pair with the transistor Q1 is wanted to be laid out in an original analog LSI layout, the layout designer selects either of
1 selection is canceled, and the flow returns to the second step to manually select the transistor Q6; and PA1 2 the transistor Q2 is tentatively laid out in the fifth step (F-5), and the flow returns to the third step to automatically, newly select a next layout candidate element. When tentative layout is performed, manual selection and re-layout must be performed at a proper time. In this manner, the processing from the second step to the fifth step is repeatedly executed until all elements are laid out.
As described above, the conventional operation is very cumbersome such that an automatically selected element is canceled to manually repeat selection/layout, or re-layout is performed at a proper time upon temporary tentative layout. Various automatic layout methods using an automatic layout/wiring apparatus are examined. In these methods, constraint items are registered in a database by, e.g., designating a relative layout definition or the like serving as a constraint item based on electrical characteristics unique to an analog circuit for a group in units of blocks, and automatic layout is performed on the basis of the database. This database has no versatility, and must be prepared for each product, resulting in a low efficiency.
The first problem of the prior art is therefore a low design efficiency. In the conventional manual layout method, layout candidate elements must be selected one by one, or when the layout candidate element automatic selection function of the automatic layout/wiring apparatus is used, layout candidate elements are automatically selected from elements which are not laid out yet. However, an element intended by the layout designer in consideration of a layout that satisfies the electrical characteristics such as the relative or absolute precision is not always selected as a layout candidate because the selection method is executed in the element number order or the description order in a connection information file. For this reason, an element must be manually selected again, or an optimal layout must be performed by temporarily performing tentative layout and selecting an element again at proper time.
The second problem of the prior art is that a database (limitation item) used in performing automatic layout by the conventional automatic layout/wiring apparatus has no versatility, and must be prepared for each product because the database is formed mainly using the element numbers or the element numbers of groups. That is, since the element numbers of respective products are different from each other, the database must be prepared for each product. Even in the same product, the database must be constructed again upon changing the circuit.