1. Field of the Invention
The present invention relates to a MIS device, and particularly to an improvement of so-called LDD (Lightly Doped Drain) structure of a PMOS transistor and a NMOS transistor formed on the same substrate and a method of manufacturing the improved LDD structure.
2. Description of the Background Art
A device provided with multi-layered structure of metal-insulator-semiconductor is generally referred to as an MIS device. An MOS device is a kind of MIS device, in which an oxide film is used for an insulator of the MIS device.
Semiconductor devices in which a p-channel MOS field effect transistor (referred to as a pMOS transistor hereinafter) and a n-channel MOS field effect transistor (referred to as a NMOS transistor hereinafter) are formed on a single semiconductor substrate include a CMOS semiconductor device, for example. FIG. 6 is a sectional structure view of a conventional CMOS semiconductor device. A p well region 8a and a n well region 8b in contact with each other are formed on a surface of a silicon substrate 6. Thick field oxide films 7 are formed at given positions on the main surface of the silicon substrate 6. The p well region 8a surface surrounded by the field oxide film 7 forms a n MOS transistor forming region, and the n well region 8b surface surrounded by the field oxide film 7 forms a pMOS transistor forming region.
The nMOS transistor 20 has a gate electrode 1a on the surface of the p well region 8a with a thin gate insulating film 9 disposed therebetween. Sidewall spacers 3a and 3a composed of insulating films are formed on sidewalls of the gate electrode 1a. Also, a pair of source/drain regions including n.sup.- impurity regions 2a, 2a of relatively low concentration and n.sup.+ impurity regions 5a, 5a of relatively high concentration are formed in the p well region 8a surface. Such structure of source/drain regions is referred to as LDD structure. Source/drain interconnection layers 11, 11 are respectively connected to the surfaces of the n.sup.+ impurity regions 5a, 5a of the source/drain region.
Also, the pMOS transistor 30 includes a gate electrode 1b on the surface of the n well region 8b with a thin gate insulating film 9 disposed therebetween. Sidewall spacers 3b, 3b formed of insulating films are formed on the sidewalls of the gate electrode 1b. Furthermore, source/drain region composed of p.sup.- impurity regions 2b, 2b of relatively low concentration and p.sup.+ impurity regions 5b, 5b of relatively high concentration are formed at the surface of the n well region 8b. This source/drain region forms the so-called LDD structure. Moreover, source/drain interconnection layers 11, 11 are respectively connected to the p.sup.+ impurity regions 5b, 5b of the source/drain region. The silicon substrate 6 surface in which a transistor is formed is covered with a thick interlayer insulating layer 10.
Next, a method of manufacturing the above-described CMOS semiconductor device will be described referring to FIGS. 7A-7H.
First, referring to FIG. 7A, a p well region 8a and an n well region 8b are formed on a silicon substrate 6 surface, and thick field oxide films 7 are formed at given regions on the silicon substrate 6 surface. Furthermore, gate insulating films 9 are formed on the surfaces of the p well region 8a and the n well region 8b. A polysilicon layer 12 is deposited on the surface of the gate insulating film 9.
Next, referring to FIG. 7B, the polysilicon layer 12 is patterned into a rectangular form using the photolithography method and the anisotropic etching method to form the gate electrode 1a of the nMOS transistor and the gate electrode 1b of the pMOS transistor.
Moreover, referring to FIG. 7C, after covering the surface of the p well region 8a with a resist pattern 4a, p type impurity ions 15 such as boron (B) are implanted into the n well region 8b using the gate electrode 1b as a mask. By this ion implantation, p.sup.- impurity regions 2b, 2b of low concentration are formed on the n well region 8b surface.
Furthermore, as shown in FIG. 7D, after removing the resist pattern 4a on the p well region 8a surface, a resist pattern 4b is now formed covering the surface of the n well region 8b. Subsequently, n type impurity ions 16 such as phosphorus (P) or arsenic (As) are directed on the p well region 8a surface using the gate electrode 1a as a mask to form n.sup.- impurity regions 2a, 2a of low concentration.
Furthermore, as shown in FIG. 7E, after removing the resist pattern 4b, an oxide film 13 is deposited all over the surface of the silicon substrate 6 using the low pressure CVD (Chemical Vapor Deposition) method.
Subsequently, referring to FIG. 7F, the oxide film 13 is anisotropically etched to form sidewall spacers 3a, 3b having the same film thickness on the sidewalls of the gate electrodes 1a and 1b.
Next, referring to FIG. 7G, after forming a resist pattern 4c covering the surface of the n well region 8b again, n type impurity ions 17 such as arsenic are implanted using the gate electrode 1a and the sidewall spacers 3a as masks. Subsequently, after removing the resist pattern 4c, thermal treatment is applied for activating the implanted ions. Thus, n.sup.+ impurity regions 5a, 5a of high concentration are formed in the p well region 8a surface. The LDD structure of the source/drain region of a nMOS transistor is then completed.
Furthermore, referring to FIG. 7H, a new resist pattern 4d is formed covering the surface of the p well region 8a. P type impurity ions 18 are directed on the n well region 8b surface using the gate electrode 1b and the sidewall spacers 3b as masks. Next, after removing the resist pattern 4d, applying thermal treatment, the ions implanted into the n well region 8b are activated. In this way, the p.sup.+ impurity regions 5b, 5b are formed. Thus, the LDD structure of source/drain region of a pMOS transistor is completed in the above steps.
Subsequently, an interlayer insulating film 10 is formed on the surface of the silicon substrate 6, and a contact hole is formed at a given position. An interconnection layer 11 is then formed at a given position through the contact hole to finish the process of manufacturing a CMOS semiconductor device (not shown).
The progress of fine processing technique of element structure is pointed out as technical background of a CMOS semiconductor device with such LDD structure as described above. The tendency of element structure miniaturization is seen in the aspects such as shortening of the gate length according to the scale down rule and forming of shallow junction region in a MOS transistor. The "scale down rule" is described in VLSI Electronics Microstructure Science, Volume 18, "Advanced MOS Device Physics", Academic Press. Inc. 1989. Also, it means shortening of the gate length of a MOS transistor, that is, shortening of a channel, which causes various problems so-called short channel effect. That is to say, for example, hot carriers are generated due to the high electric field produced in the vicinity of a drain in a short channel MOS transistor, and a portion of the hot carriers are captured in a trap in the gate insulating film to form a new level. As a result, characteristic degradation such as shift of a threshold value voltage of a MOS transistor and a decrease of mutual transconductance are caused. The high electric field produced in the vicinity of a drain also caused degradation of the drain breakdown voltage due to the avalanche breakdown. The LDD structure of a MOS transistor is a device proposed to solve such problems. Especially, it restrains generation of the high electric field by forming an impurity region with moderately changing concentration distribution in the vicinity of the drain to obtain high avalanche breakdown voltage and a decrease of reliability degradation due to hot carriers.
In a miniaturization method of CMOS semiconductor devices, it is needed to reduce the gate length L.sub.Gp of pMOS transistor 30 and the gate length L.sub.Gn of nMOS transistor 20 and make the lengths equal. As the gate lengths L.sub.Gp, L.sub.Gn of pMOS transistor 30 and nMOS transistor 20 get longer, the gate capacitance increases to increase the RC constant, with the result that operation of transistors are delayed. Accordingly, the channel lengths Ln and Lp defined in a self aligning manner utilizing gate electrodes 1b and 1a are also preferably reduced to have the equal lengths.
However, turning to FIG. 6 again, the pMOS transistor 30 and the nMOS transistor 20 are provided with low concentration impurity regions 2a, 2b of the LDD structure having different shapes in a CMOS semiconductor device manufactured through the manufacturing steps described-above. That is to say, in the pMOS transistor 30, the diffusion length of the low concentration p.sup.- impurity region 2b is extremely small as compared to that of the nMOS transistor 20. Also, the channel length L.sub.p between the high concentration p.sup.+ impurity regions 5b, 5b are shorter than the channel length L.sub.n of the nMOS transistor 20. This is because, boron (B), impurity forming the source/drain region of the pMOS transistor 30, has a larger diffusion coefficient as compared to that of phosphorus and arsenic forming the source/drain region of the nMOS transistor 20. This is understood by comparing the steps shown in the above FIGS. 7G and 7H. In other words, in the nMOS transistor 20, the high concentration n.sup.+ impurity regions 5a, 5a formed in a self-align manner with respect to the sidewall spacers 3a slightly diffuse under the sidewall spacers 3a by the thermal treatment for activation. On the other hand, in the pMOS transistor, the high concentration p.sup.+ impurity regions 5b, 5b formed in a self-align manner with respect to the sidewall spacers 3b widely diffuse under the sidewall spacers 3b in the thermal treatment for activating. In this way, the diffused high concentration p.sup.+ impurity regions 5b, 5b cover the low concentration p.sup.- impurity regions 2b, 2b regions, so that the diffusion length of the low concentration p.sup.- impurity region 2b is decreased. Thus, punch through phenomena easily occurs between the pair of high concentration p.sup.+ impurity regions 5b, 5b narrowed due to diffusion of impurity of large diffusion coefficient. This punch through phenomena is further facilitated as the gate length becomes shorter while the device is refined.
As described above, the LDD structure of the pMOS transistor and the nMOS transistor composed of impurities of different diffusion coefficients are manufactured employing the sidewall spacers 3a, 3b having the same film thickness. Accordingly, if the film thickness of the sidewall spacers 3a, 3b is selected to be suitable for the LDD structure of the nMOS transistor, for example, resistance to the punch through between the high concentration p.sup.+ impurity regions 5b, 5b is easily degraded in a pMOS transistor. On the other hand, if the sidewall spacers are formed with film thickness suitable for the LDD structure of the pMOS transistor, the drain current between the source and the drain is degraded in the nMOS transistor 20. This is because, as the film thickness of the sidewall spacers 3a is increased, the diffusion length of the low concentration n.sup.- impurity regions 2a, 2a is increased, and the low concentration n.sup.- impurity diffusion layers 2a act as parasitic resistance between the source and the drain to degrade the drain current. In this way, in a conventional CMOS semiconductor device, the sidewall spacers 3a, 3b defining the low concentration impurity regions of the LDD structure are formed with the same film thickness in the pMOS transistor and the nMOS transistor, so that a LDD structure which can satisfy requirements of both of the pMOS transistor 30 and the nMOS transistor 20 could not be obtained. Conventionally, by the sacrifice of source-drain current degradation of the nMOS transistor 20 to some extent to prevent the punch through phenomena of the pMOS transistor 30, the film thickness of the sidewall spacers 3a, 3b has been determined focusing on the operational reliability.