1. Field of the Invention
The present invention generally relates to a semiconductor memory circuit and, more particularly, to a semiconductor memory circuit having dummy cells which are connected to twisted bit lines.
2. Description of the Prior Art
The current trend in the semiconductor memories art is toward higher integration density, as typified by DRAMs. The higher integration density, however, brings about a problem that the operation characteristics of a semiconductor memory circuit are adversely influenced by the coupling capacitance between bit lines which are included in the memory circuit, especially the coupling capacitance between the individual bit lines of a certain bit line pair and the adjoining bit line pairs. One approach for eliminating this problem has been reported by Yoshihara et al in a paper entitled "Twisted Bit Line Technique for Multi-Mb DRAMs", IEEE International Solid State Circuit Conference (1988), pp. 238-239. Specifically, in a semiconductor memory circuit having a number of bit line pairs, a number of word lines, and a number of memory cells, a twisted bit line system disclosed in the above paper is such that individual bit lines constituting a bit line pair intersect each other in places while being electrically isolated from each other. Such a configuration is successful in equalizing the coupling capacitances between the individual bit lines of a bit line pair and the adjoining bit line pairs. The paper, however, does not show how memory cells and dummy cells are arranged in the semiconductor memory circuit. A specific configuration achievable by installing dummy cells in a twisted bit line type semiconductor memory circuit on the basis of the traditional dummy cell principle would be as follows.
FIG. 4 indicates in a schematic block diagram a part of the above-mentioned assumptive configuration, i.e., three of a number of bit line pairs and their associated elements. In the figure, the three bit line pairs are labeled OA, EA and OB. It should be noted that the structure shown in FIG. 4 is not an actual structure heretofore proposed, but it is merely an assumptive structure which would be derived from the technology disclosed in the above paper if the traditional dummy cell concept were applied thereto. In FIG. 4, the individual bit lines of each bit line pair intersect each other at places to form intersections as represented by an intersection 11, as shown and described in the paper. As used in this specification and in the appended claims, any reference to "intersection" or to "intersecting" lines or the like is not meant to denote electrical interconnection, but rather to denote a place where two lines cross one another. This is evident from the drawings which show that at these crossings, electrical contact is avoided. More specifically, assume that the entire length of bit lines is divided into four segments I, II, III and IV. Bit lines OA.sub.1 and OA.sub.2 constituting an odd bit line pair OA, bit lines OB.sub.1 and OB.sub.2 constituting an odd bit line pair OB, and so forth intersect each other in the individual odd bit line pairs at the border between the nearby segments or sections I and II and the border between the nearby sections III and IV. On the other hand, bit lines EA.sub.1 and EA.sub.2 forming an even bit line pair EA as well as bit lines forming other even bit line pairs intersect each other at the border between the sections II and III. A plurality of word lines are provided in each of the sections I to IV. In FIG. 4, two word lines a and b are shown as being laid in each of the sections I to IV for simplicity. Memory cells MC.sub.1, MC.sub.2, MC.sub.3 and so forth are individually connected to the bit lines and word lines in the junctions of the bit lines and word lines.
In a semiconductor memory circuit typical of which is a DRAM, dummy cells are implemented with either one of an inverted phase dummy cell method or an in-phase dummy cell method. This is to minimize the influence of the wordline-bitline coupling capacitance and to balance the individual bit lines of each bit line pair. The inverted phase dummy cell method is such that a dummy cell on a particular bit line connecting to a designated memory cell is selected by a dummy word line to which a signal whose phase is opposite to the phase of the word line is selected. On the other hand, the in-phase dummy cell method is such that a dummy cell on a particular bit line forming a pair with the other bit line which connects to a designated memory cell is selected by a dummy word line to which a signal whose phase is the same as the word line is selected.
In the memory circuit configuration shown in FIG. 4, the memory cells connected to the same word line are connected to those bit lines of the individual bit line pairs which correspond to each other with respect to the position in the pair. For example, the memory cells MC.sub.1, MC.sub.2 and MC.sub.3 connected to the same word line a in the section I are connected at one terminal thereof to the upper bit lines OA.sub.1, EA.sub.1 and OB.sub.1 of the bit line pairs OA, EA and OB, respectively. Then, as shown in FIG. 4, this kind of configuration would need dummy cells DC.sub.1 and DC.sub.3 and in the case of the inverted phase dummy cell method DC.sub.6 or would need dummy cells DC.sub.2, DC.sub.4 and DC.sub.5 in case of the in-phase dummy cell method having at least two of four dummy word lines A, B, C and D.
FIG. 5 tabulates memory cells and dummy cells which are selected in the above-described semiconductor memory circuit by the in-phase dummy cell system and the anti-phase dummy cell system. Assume that the word line a existing in the section I is selected to access the memory cells MC.sub.1, MC.sub.2 and MC.sub.3 for data being stored therein. Then, the data associated with the memory cells MC.sub.1, MC.sub.2 and MC.sub.3 exist on the bit lines OA.sub.1, EA.sub.1 and OB.sub.1, respectively. It follows that in the in-phase dummy system the dummy word lines B and C are selected by a signal having the same phase as the word lines to in turn select the dummy cells DC.sub.2, DC.sub.5 and DC.sub.4, while in the antiphase dummy cell system the dummy word lines A and D are selected by a signal opposite in phase to the word lines to in turn select the dummy cells DC.sub.1, DC.sub.6 and DC.sub.3.
In the semiconductor memory circuit shown in FIG. 4, the region (sections I to IV) where the bit lines intersect each other and the region (indicated by a dash-and-dot line in the figure) where the dummy cells are provided are independent of each other. The circuit, therefore, cannot be integrated unless it is provided with exclusive areas for accommodating the two different kinds of regions. This obstructs efficient circuit design which is desirable for higher integration density.
That only a single pair of dummy cells is provided on each bit line pair as shown and described gives rise to another problem. Specifically, in each bit line pair, the time constants of the individual bit lines with respect to their associated sense amplifier are not the same as each other and, therefore, unbalanced. For example, assuming that the word line a in the section I is selected, then the dummy word lines B and C are selected in the in-phase dummy cell system and, as a result, the memory cells and the dummy cells selected are located at opposite remote ends of the bit lines. In this condition, the distance to the memory cells and the distance to the dummy cells as measured from a sense amplifier which is associated with the bit lines greatly differ from each other, resulting in the bit lines of the bit line pair differing from each other in time constant. To promote efficient sense amplification in a bit line pair, it is preferable that paired bit lines have time constants which are as close to each other as possible.