1. Field of the Invention
The present invention relates to substrate processing, and more particularly to improving the substrate processing using optimized Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models, procedures, and subsystems.
2. Description of the Related Art
Etch process behavior is inherently non-linear and interacting step-to-step (layers) or as process stacks are compiled (etch/cvd/implant). With the knowledge of the process interactions based on physical modeling of Tokyo Electron Limited (TEL) chambers and base processes and imperial data and measurements from process refinement and tuning the control of Critical Dimension (CD), Sidewall Angle (SWA), depths, film thicknesses, over etching, undercuts, surface cleaning and damage control can be recursively calculated and optimized using multi-input multi-output non-linear models. Current low cost products use a bulk silicon technology. As the transistor continues to shrink, the impact of the channel depth is becoming critical (ultra-shallow source/drain extensions). As the SOI film shrinks, smaller variations in the gate and/or spacer thickness and thickness of the SOI [define SOI] film can affect the transistor's performance. When etch procedures are not controlled, the removal of the material near the gate affects the electrical performance.
Current high performance microprocessors use PD SOI (partially depleted Silicon-on-Insulator film—giving a threshold voltage 0.2 volts. PD SOI films are around 50 nm while the gate and/or spacer reduction amount can be a large percentage (10%) of the total gate and/or spacer thickness. Future generations of SOI films are called FD SOI (fully depleted giving a threshold voltage 0.08 volts and a thickness of ˜25 nm). Currently theses films are not in production due to limitations in thickness control uniformity and defects. Channel mobility degrades with decreasing SOI thickness. With thinner SOI film, the control of the gate and/or spacer sidewall thickness becomes more critical.