Integrated circuits are made up of millions of active devices formed in or on a substrate, such as a silicon wafer. The active devices are chemically and physically connected into a substrate and are interconnected through the use of multilevel interconnects to form functional circuits. Typical multilevel interconnects comprise a first metal layer, an interlevel dielectric layer, and sometimes a third and subsequent metal layer. Interlevel dielectrics, such as doped and undoped silicon dioxide (SiO2) and/or low-κ dielectrics, are used to electrically isolate the different metal layers.
The electrical connections between different interconnection levels are made through the use of metal vias. U.S. Pat. No. 5,741,626, for example, describes a method for preparing dielectric TaN layers. Moreover, U.S. Pat. No. 4,789,648 describes a method for preparing multiple metallized layers and metallized vias in insulator films. In a similar manner, metal contacts are used to form electrical connections between interconnection levels and devices formed in a well. The metal vias and contacts may be filled with various metals and alloys, such as, for example, titanium (Ti), titanium nitride (TiN), aluminum copper (Al—Cu), aluminum silicon (Al—Si), copper (Cu), tungsten (W), platinum (Pt), ruthenium (Ru), iridium (Ir), and combinations thereof (hereinafter referred to as “via metals”).
The via metals generally employ an adhesion layer (i.e., a barrier film), such as a titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), or tungsten nitride (WN) barrier film, to adhere the via metals to the SiO2 substrate. At the contact level, the barrier film acts as a diffusion barrier to prevent the via metals from reacting with SiO2.
In one semiconductor manufacturing process, metal vias and/or contacts are formed by a blanket metal deposition followed by a chemical-mechanical polishing (CMP) step. In a typical process, via holes are etched through an interlevel dielectric (ILD) to interconnection lines or to a semiconductor substrate. Next, a barrier film is formed over the ILD and is directed into the etched via hole. Then, a via metal is blanket-deposited over the barrier film and into the via hole. Deposition is continued until the via hole is filled with the blanket-deposited metal. Finally, the excess metal is removed by a CMP process to form metal vias. Processes for the manufacturing and/or CMP of vias are disclosed in U.S. Pat. Nos. 4,671,851, 4,910,155, and 4,944,836.
Typical metal CMP systems contain an abrasive material, such as silica or alumina, suspended in an oxidizing, aqueous medium. U.S. Pat. No. 5,244,534, for example, discloses a system containing alumina, hydrogen peroxide, and either potassium or ammonium hydroxide, which is useful in removing tungsten with little removal of the underlying insulating layer. U.S. Pat. No. 5,209,816 discloses a system useful for polishing aluminum that comprises perchloric acid, hydrogen peroxide, and a solid abrasive material in an aqueous medium. U.S. Pat. No. 5,340,370 discloses a tungsten polishing system comprising potassium ferricyanide, potassium acetate, acetic acid, and silica. U.S. Pat. Nos. 5,391,258 and 5,476,606 disclose systems for polishing a composite of metal and silica including an aqueous medium, abrasive particles, and an anion, which controls the rate of silica removal. U.S. Pat. No. 5,770,095 discloses polishing systems comprising an oxidizing agent, a chemical agent, and an etching agent selected from aminoacetic acid and amidosulfuric acid. U.S. Pat. No. 6,290,736 discloses a polishing composition for polishing a noble metal surface comprising an abrasive, a halogen compound, and an aqueous basic solution. Other polishing systems for use in CMP processes are described in U.S. Pat. Nos. 4,956,313, 5,137,544, 5,157,876, 5,354,490, and 5,527,423.
Barrier films of titanium, titanium nitride, and like metals, such as tungsten, have a chemical activity similar to that of the via metals. Consequently, a single system can be used effectively to polish both Ti/TiN barrier films and via metals at similar rates. Ta and TaN barrier films, however, are significantly different from Ti, TiN, and like barrier films. Ta and TaN are relatively inert in chemical nature as compared to Ti and TiN. Accordingly, the aforementioned systems are significantly less effective at polishing tantalum layers than they are at polishing titanium layers (e.g., the tantalum removal rate is significantly lower than the titanium removal rate). While via metals and barrier metals are conventionally polished with a single system due to their similarly high removal rates, joint polishing of via metals and tantalum and similar materials using conventional polishing systems results in undesirable effects, such as oxide erosion and via metal dishing.
Similar problems with oxide erosion are observed when noble metals are used as the via metal. Noble metals have significantly lower chemical activity and are not adequately polished by conventional CMP compositions. Efficient planarization of noble metals often requires a CMP composition with an alkaline pH, resulting in undesirably higher removal rates of the oxide layer.
Consequently, there remains a need for a system, composition, and/or method of polishing a substrate comprising a first metal layer and a second layer in a manner such that planarization efficiency, uniformity, and removal rate of the first metal layer are maximized and planarization of the second layer is minimized, thereby minimizing undesirable effects, such as first metal layer dishing, surface imperfections, and damage to underlying topography. The invention provides such a system, composition, and method. These and other characteristics and advantages of the invention will be apparent from the description of the invention provided herein.