The present invention relates to a method of mounting chips, and particularly to a method of mounting a large number of fine chips, for example, fine semiconductor chips having sizes of the order of m on boards.
Functional devices formed of semiconductor chips such as LEDs and ICs having fine structures have been mounted on boards by forming the semiconductor chips into shapes such as trapezoidal shapes by etching while providing recesses corresponding thereto on the board side, wherein the semiconductor chips are mounted in the recesses.
The above method, however, has the following problem: namely, in the case of using semiconductor chips made from materials not easy to be formed into trapezoidal shapes by etching or of fine dimensions, the mounting of these semiconductor chips becomes difficult, or the accuracy in shape of the chips and/or the positional accuracy in mounting of the chips are lowered, thereby degrading the mounting yield.
In mounting semiconductor chips such as light emitting devices used for a display on a board, the semiconductor chips have been required to be mounted on a board surface having a specific area with a high efficiency and a high yield, and further, in consideration of the cost. Further, along with the tendency toward miniaturization of semiconductor chips, the handling of the semiconductor chips at the time of mounting have come to be difficult. Accordingly, it has been expected to develop the semiconductor chip structures capable of effectively coping with the above terms, that is, the efficiency, yield, cost, and handling at the time of mounting, and to develop the method of desirably mounting these semiconductor chip structures on boards.
One method of mounting fine chips such as fine semiconductor chips has been disclosed, for example, in U.S. Pat. Nos. 5,545,291, 5,824,186, and 5,904,545, Japanese Patent Laid-open (Translation of PCT International Publication) No. Hei 9-506742, and Japanese Patent Laid-open No. Hei 9-120943. In this mounting method, each chip is tapered to be determined in its vertical direction, and buried in the corresponding recess formed on a board. In this case, the chips are mixed in a solution such as water or alcohol into a slurry, and the slurry is made to flow on the board.
Another method of mounting fine chips, such as IC chips, using static electricity for mounting the IC chips on a board has been described in U.S. patent application Ser. No. 07/902,986. In this mounting method, the chips are vibrated by static electricity and are arranged in a state in which the positional energy of the chips is minimized.
According to the former mounting method characterized by tapering semiconductor chips, although a sufficiently large yield can be kept for semiconductor chips whose sizes are in the range of several hundreds μm or more; however, the yield is lowered for semiconductor chips whose sizes are in the range of several tens μm or less. Accordingly, this method has a problem from the practical utilization.
The latter mounting method characterized by using static electricity requires an apparatus for vibrating fine chips with static electricity. Further, according to this method, since fine chips collide with each other by mechanical vibration, there may occur an inconvenience that part of each chip be damaged. From this viewpoint, this method is unsuitable to practical use.