The present invention relates to semiconductor device manufacturing, and more particularly to a method for introducing an impurity gettering layer or region into a top Si-containing layer of a silicon-on-insulator (SOI) wafer.
In the semiconductor industry, SOI technology is becoming increasingly important since it permits the formation of high-speed circuits. Moreover, SOI devices offer many more advantages over their bulk counterparts including, for example, higher performance, absence of latch-up, higher packing density and low voltage applications.
In a typical SOI wafer, a buried oxide layer is sandwiched between a bottom Si-containing layer, e.g., a Si-containing substrate, and a top Si-containing layer. The buried oxide layer is used to electrically isolate an integrated circuit (IC) fabricated in the top Si-containing layer from the Si-containing substrate. This improves device performance because the buried oxide layer eliminates parasitic capacitance and it allows strong gate to body coupling to improve drive-on current.
Despite the above advantages, SOI wafers have some problems associated therewith. One problem is that there is an absence of a good gettering layer which removes metallic contamination or impurities in the IC. In a typical bulk semiconductor wafer, the backside of the wafer is typically designed to act as a metal gettering layer. Methods such as providing a heavily doped polysilicon layer on the backside of the wafer or providing a rough backside surface are typically used in bulk semiconductor technology to introduce a gettering layer to the backside of the wafer. In SOI technology, the buried oxide layer blocks metal from getting into the back of the wafer. Thus, an SOI wafer is more sensitive to top silicon metal contamination. Hence, once metal is able to diffuse in the top Si-containing layer of an SOI wafer it has nowhere to go and the metal contamination will damage the device gate dielectric.
U.S. Pat. No. 5,244,819 to Yue describes a method of providing a frontside gettering layer in an SOI wafer. The gettering layer in Yue is formed by ion implanting species such as Ar, He and Ge into the top Si layer of an SOI substrate. In order to ensure that the gettering layer is not formed in the active device area (i.e., the device channel region) of the top Si layer, a masking layer is used to define the active area. The masking layer is applied to the SOI substrate prior to implantation and a lithographic process is used in defining the masking layer. In accordance with the disclosure of Yue, the non-active device areas (i.e., source/drain regions) of the top Si layer are left exposed and the active device areas are protected by the patterned masking layer.
U.S. Pat. No. 5,753,560 to Hong, et al. disclose another method of introducing a gettering layer into the top Si layer of an SOI substrate. As was the case in Yue, Hong, et al. use a masking level to ensure that the gettering layer is not introduced into the active device areas.
Although the methods used in Yue and Hong, et al. are capable of providing a gettering layer into the top Si layer of an SOI substrate, the Yue and Hong, et al. processes are not self-aligned, and a costly lithographic process is required in these prior art processes to ensure that the gettering layer is not implanted into the active device regions of the SOI substrate.
In view of the above, there is still a need for providing a new and improved method of forming a gettering layer (or region) into non-active device areas of a top Si-containing layer of an SOI substrate that is self-aligned, and which avoids the use of a mask to define the gettering region. A method which eliminates the mask to define the gettering region is beneficial since such a method would also eliminate the costly lithographic process required in prior art methods.
One object of the present invention is to provide a method of introducing a gettering region into the non-active device areas of a top Si-containing layer of an SOI substrate.
Another object of the present invention is to provide a method of introducing a gettering region into the non-active device areas of a top Si-containing layer of an SOI substrate which is self-aligned.
A still further object of the present invention is to provide a method of introducing a gettering region into the non-active device areas of a top Si-containing layer of an SOI substrate wherein a mask (i.e., litho level) is not required to define the gettering region.
These and other objects and advantages are achieved in the present invention by forming a disposable spacer on each vertical sidewall of a patterned gate stack region prior to forming the gettering region. Because of the spacer, the gettering region will be automatically self-aligned to the patterned gate stack region and it will not impact the active device region, i.e., device channel region. The disposable spacer can then be removed after formation of the gettering region and normal complementary metal oxide semiconductor (CMOS) device processing may be resumed.
It noted that in the inventive method the gettering region is introduced into the top Si-containing layer of an SOI substrate after the gate dielectric has been formed thereon. The benefit of such a method is that it does not impact the formation of the gate dielectric. In addition, any metal contamination that is introduced before the gate dielectric is formed could be gettered away using an acid such as HCl immediately before formation of the gate dielectric.
Another feature of the present invention is that the gettering region is introduced into the SOI substrate prior to any high temperature processes are performed. Thus, if any metal is present during the high temperature processes no damage to the gate region occurs in the present invention.
Specifically, the method of the present invention comprises the steps of:
(a) forming a disposable spacer on each vertical sidewall of a patterned gate stack region, said patterned gate stack region is formed on a top Si-containing layer of an SOI substrate;
(b) implanting gettering species into said top Si-containing layer not protected by said disposable spacer and said patterned gate stack region; and
(c) removing said disposable spacer and annealing the implanted gettering species so as to convert said gettering species into a gettering region.