Generally, a DRAM (Dynamic Random Access Memory) device includes a plurality of unit cells, each of which comprises a MOS transistor and a storage capacitor. In continuing the trend of higher memory capacity, the size of the unit cell has been continuously decreased in order to increase the packing density of the DRAM device. The reduced cell size results in a decrease in capacitor area of the unit cell. The decreased capacitor area means low cell capacitance, which often induces problems like as low read-out capability and soft error.
One proposal to solve the above-mentioned problems is to use high dielectric constant material as a capacitor dielectric layer, which constitute a capacitor together with a lower electrode and an upper electrode. Typical examples of the high dielectric constant material are tantalum oxide (Ta2O5) and BST ((Ba,Sr)TiO3). The material of the lower electrode or the upper electrode is required to have a high work function value and not to be reactive with the capacitor dielectric layer. A typical example of the material of the lower and the upper electrodes is a noble metal, which includes platinum, ruthenium, iridium, rhodium and osmium.
FIG. 1 is cross-sectional views illustrating a conventional method for forming a capacitor using tantalum oxide layer as a capacitor dialectic layer. Referring to FIG. 1, a lower electrode 20 is formed on a substrate 10. The material of the lower electrode 20 is ruthenium. A capacitor dielectric layer 25 is deposited on the lower electrode 20. The material of the dielectric layer 25 is tantalum oxide. The thickness of the dielectric layer 25 is 140˜160 Å. The dielectric layer 25 is crystallized by a thermal treatment at 700° C. or more. Subsequently, an upper electrode 30 is formed on the crystallized dielectric layer 25, thereby completing a capacitor 30 on the substrate 10. The material of the upper electrode 30 is ruthenium.
FIG. 2 is a graph showing a change in equivalent oxide thickness value by the crystallization process. The equivalent oxide thickness value represents an effective thickness of a capacitor dielectric layer of a capacitor on the assumption that the capacitor dielectric layer was made of silicon oxide. Therefore, in general, higher equivalent oxide thickness value means lower capacitance per unit capacitor area. Referring to FIG. 2, the vertical axis represents equivalent oxide thickness value. On the horizontal axis of the graph, the reference “NO” means that the crystallization is not performed, and the reference “700° C.” means that the crystallization is performed at 700° C. As shown in the graph, the equivalent oxide thickness value is favorably decreased by performing the crystallization process.
However, the crystallization process has also problems. That is to say, the crystallization process is usually performed at relatively high temperature, thereby generating a lot of grain boundary in the tantalum oxide layer. The grain boundary often acts as a path of leakage current and may induce unfavorable leakage current in the capacitor. Moreover, the crystallization process under relatively high temperature may induce unfavorable deformation of the lower electrode and damage on the tantalum oxide layer.
Meanwhile, it is thought to be difficult to decrease the equivalent oxide thickness value into 10 Å or less in the conventional method, because both nuclear generation and crystal growth occur simultaneously during the crystallization process.
Accordingly, the need remains for a method for forming a capacitor having low leakage current as well as low equivalent oxide thickness.