The present invention relates generally to chopper stabilized amplifiers, and more particularly to circuitry and techniques for reducing the amount chip area occupied by capacitors used for Miller compensation and notch filtering.
Chopper stabilization is frequently used to improve offset and drift of amplifiers because it provides low in-band noise and avoids noise folding problems. A known technique for notch filtering can be used in chopper stabilized amplifiers to nearly eliminate the substantial output ripple voltage that otherwise occurs, and preserves the low offset, drift, and noise that are characteristic of the basic chopper stabilized amplifier topology. This known technique is described in the commonly assigned pending patent application Ser. No. 11/340,223 filed Jan. 26, 2006, entitled “Notch Filter for Ripple Reduction and Chopper Stabilized Amplifiers” by Rodney T. Burt and Joy Y. Zhang, incorporated herein by reference. However, increases bandwidth of a notch filtered chopper stabilized amplifier requires higher transconductance Gm in the chopping circuitry and accordingly requires larger compensation capacitors and larger capacitors in the notch filter. At higher bandwidths, the physical size of the compensation capacitors and notch filter capacitors causes them to occupy an unacceptably large amount of integrated circuit chip area, which unacceptably increases the cost of the chopper stabilized amplifier. This limits the usability of the otherwise highly desirable notch filtered chopper stabilized amplifier architecture in complex mixed signal systems in which it would be highly desirable to include a number of such amplifiers on a single integrated circuit chip.
“Prior Art” FIG. 1 herein shows a somewhat simplified block diagram representation 1A of the same notch filtered chopper stabilized amplifier circuit shown in FIG. 3A of above mentioned pending application Ser. No. 11/340,223, including chopping circuitry, a notch filter and a feed forward stage. In Prior Art FIG. 1, feed-forward transconductance stage 5 is shown having a differential output between conductors 23A and 23B. Block 35 contains the input chopping switches 9, which are the same as switches 9-1,2,3,4 as shown in FIG. 3A of Ser. No. 11/340,223, coupled between the input voltage Vin and the inputs of a transconductance stage 2. Block 40 contains the output chopping switches 10, which are the same as switches 10-1,2,3,4 as shown in FIG. 3A of Ser. No. 11/340,223.
In Prior Art FIG. 1, chopping clock signal CHOPCLK on conductor 43 is applied to the control (CTL) inputs (not shown) of various input chopping switches 9 and various output chopping switches 10 and also is applied to the input of an inverter 41 which produces the logical complement of CHOPCLK and applies it to the CTL inputs (not shown) of various other input chopping switches 9 and the various other output chopping switches 10. CHOPCLK is the same as the “Phase1” clock signal shown in FIG. 3B of Ser. No. 11/340,223, and the logical complement of CHOPCLK is the same as the “Phase2” clock signal in FIG. 3B of co-pending Ser. No. 11/340,223. The input chopping switches 9 and output chopping switches 10 typically are implemented by means of individual MOS transistors or CMOS transmission gates. Similarly, filter clock signal FILTERCLK on conductor 51 is applied to the CTL inputs (not shown) of various switches 16 and 21 in notch filter 15 and also is applied to the input of an inverter 52 which produces the logical complement of FILTERCLK and applies it to the CTL inputs (not shown) of various switches 16 and 21 in notch filter 15, which can be the same as shown in FIG. 3A of Ser. No. 11/340,223.
FILTERCLK is the same as “Phase3” in FIG. 3B of the above mentioned Ser. No. 11/340,223, and the logical complement of FILTERCLK is the same as “Phase4” in FIG. 3B of co-pending Ser. No. 11/340,223. Transconductance stage 3 (of transconductance gm2) and transconductance stage 4 (of transconductance gm3) in FIG. 3A of Ser. No. 11/340,223 are combined in block 3,4 in Prior Art FIG. 1 herein, wherein the two inputs IN1(+) and IN1(−) are the inputs of the “gm3” transconductance stage and the two inputs IN2(+) and IN2(−) are the inputs of the “gm2” transconductance stage. Output conductor 25 is connected to the output of the circuitry in block 3,4. Specifically, in block 3,4 the output of transconductance amplifier 4, referred to herein as “transconductance amplifier gm3”, in FIG. 3A of Ser. No. 11/340,223 is connected to Vout conductor 25. The (−) input of transconductance amplifier gm3 is connected by conductor 23 shown in FIG. 3A of Ser. No. 11/340,223 to the output of transconductance amplifier 5, to the output of transconductance amplifier 3, referred to herein as “transconductance amplifier gm2”, shown in FIG. 3A of Ser. No. 11/340,223 and also to one terminal of capacitor C1 shown in FIG. 3A of Ser. No. 11/340,223, the other terminal of which is connected to Vout conductor 25. The (−) and (+) inputs of transconductance amplifier gm2 are connected to conductors 22A and 22B, respectively.
In Prior Art FIG. 1, capacitors C0 and C1 are balancing capacitors, also referred to herein as “symmetrical counterpart capacitors”, to Miller compensation capacitors C2 and C3, respectively, and are provided to balance charge injection effects, to cancel a “zero” that would otherwise occur in the amplifier transfer characteristic, and also to provide good common mode rejection.
FIG. 2 shows an implementation of the notch filter 15 shown in Prior Art FIG. 1, wherein the switches 16A-D and the switches 21A-D in FIG. 3A of Ser. No. 11/340,223 are implemented using N-channel MOS transistors.
Thus, there is an unmet need for circuitry in a chopper stabilized amplifier which substantially reduces the amount of integrated circuit chip area required for the various capacitors associated with notch filtering and Miller compensation within the chopper stabilized amplifier.