Computer microchips permeate almost all aspects of modern life. From the single microchips embedded into our pets to the myriad of microchips “flying” our aircraft and keeping our cars running, our reliance on semiconductor device technology cannot be minimized. A topic of great importance, considering all of the critical operations controlled by semiconductor devices, is the durability and reliability of those devices. One issue that has been at the forefront of semiconductor device design is protecting devices from electrostatic discharge (ESD). ESD is defined as the transfer of charge between bodies at different electrical potentials. ESD is a serious issue in solid state electronics. Integrated circuits are made from semiconductor materials such as silicon and insulating materials such as silicon dioxide. When subjected to high voltages, many semiconductor materials can suffer permanent damage, changing the electrical characteristics, degrading, or destroying it. It may also upset the normal operation of an electronic system, causing equipment malfunction or failure.
Damage to electronic devices from ESD can occur at any point from manufacture to field service. Damage may result from improperly handling the devices in uncontrolled surroundings or when substandard ESD control practices are used. Generally, ESD damage is classified as either a catastrophic failure or a latent defect.
A catastrophic failure occurs when an electronic device no longer functions after exposure to an ESD event. An ESD event may cause a metal melt, junction breakdown, or even oxide failure. A device's circuitry can, therefore, be permanently damaged causing the device to fail. Such failures can usually be detected when a device is tested before shipment. However, if the ESD event occurs after testing, the damage may go undetected until the device fails in operation.
A latent defect, on the other hand, is typically more difficult to identify. A device that is exposed to an ESD event may be partially degraded, yet continue to perform its intended function. However, this degradation generally reduces the operating life of the device dramatically. A product or system that incorporates a device with latent defects may experience premature failure after the user places the device into service. Such failures are usually costly to repair and in some applications may create personnel hazards.
Various external solutions and procedures have been developed for preventing ESD damage during fabrication and device manufacturing. Manufacturers often implement electrostatic protective areas (EPAs). An EPA can be a small working station or a large manufacturing area. The main principles of an EPA are: (1) there are no highly charging materials in the vicinity of ESD sensitive electronics; (2) all conductive materials are grounded; and (3) workers are grounded. Adherence to these principles may prevent charge build-up on ESD sensitive electronics. International standards are used to define typical EPA and can be found, for example, from International Electrotechnical Commission (IEC) or American National Standards Institute (ANSI).
ESD prevention within an EPA may include: using appropriate ESD-safe packing material, using conductive filaments on garments worn by assembly workers, using conducting wrist straps and foot-straps to prevent high voltages from accumulating on workers' bodies, using anti-static mats or conductive flooring materials to conduct harmful electric charges away from the work area, and using humidity control. Humid conditions prevent electrostatic charge generation because the thin layer of moisture that accumulates on most surfaces serves to dissipate electric charges. Ion generators are also sometimes used to inject ions into the ambient airstream. Ionization systems help to neutralize charged surface regions on insulating or dielectric materials.
In addition to such external ESD prevention mechanisms, chip designers have also incorporated ESD protection internally into the design of the device. Various methods and configurations for adding N+ or P+ doped regions have been implemented in field effect transistor (FET) devices in association with source/drain (S/D) and gate regions. One common method is to provide a zero-space N+ S/D implant region between contacts.
A disadvantage of the zero-space N+ S/D implant region and similar configurations is that they do not typically provide good and qualified ESD protection for high voltage applications.