Coplanar waveguides (CPW) generally comprise a conductive line placed between two ground lines, and allow components such as antennas operating at frequencies of, for example, about several tens of gigahertz, to be electrically connected. When a high-frequency signal is passed through such a waveguide, losses can lead to the signal being attenuated. These losses are in particular due to the resistance and inductance of the line, to capacitive coupling to the substrate, and to conductance allowing ground return.
In order to reduce these losses, it has been suggested, by Gamble, “Low-loss CPW lines on surface stabilized high-resistivity silicon,” IEEE Microwave and Guided Wave Letters, Vol. 9, No. 10, October 1999, that these coplanar waveguides be fabricated using metal lines on high-resistivity silicon substrates. Thus low conductance is obtained between the conductive line and the ground lines. The diffusion of metals, for example gold or copper, into the silicon, and the possibility that charge trapped in a passivation layer placed in contact with the conductive lines will induce a conductive channel in the substrate, between the signal and ground, are the drawbacks of this solution.
Superposing the conductive lines of the coplanar waveguides on insulating lines, for example silicon-dioxide (SiO2) lines, on a high-resistivity silicon substrate has also been suggested. This solution has the drawback of forming capacitive coupling between the conductive lines and the substrate. Moreover, charge trapped in a passivation layer, placed in contact with the conductive lines, can also induce a conductive channel in the high-resistivity silicon substrate, between the regions under the conductive lines.
It has also been suggested that the conductive lines of the coplanar waveguides be formed on an insulating layer, placed on a polycrystalline-silicon layer, itself placed on a high-resistivity silicon substrate. This solution allows current flowing under the insulating layer to be captured in the polycrystalline-silicon layer.
The reader may also refer to Ojefors, “Micromachined loop antennas on low resistivity silicon,” IEEE Transactions on Antennas and Propagation, 2006, Vol. 54, No. 12, pages 3593-3601, describing the formation of trenches in the silicon substrate under the oxide layer and located substantially between the conductive lines of an antenna and a ground plane. This solution in particular has the drawback of being complicated to implement.
Finally, Wojnowski, “Package Trends for Today's and Future mm-Wave Applications,” Infineon, 38th European Microwave Conference, 2008, describes the formation of a cavity matrix under the coplanar waveguides. This solution does not sufficiently limit losses, in particular because of parasitic conductivity in the silicon. The formation of the cavities described in this document also has the drawback of being implemented before metal lines have been formed on the frontside of the integrated circuits.
Moreover, it may be necessary to use through-silicon vias in integrated circuits, for example in order to form three-dimensional stacks or in order to form electrical contacts on a side opposed to that comprising the metal lines of the integrated circuit.