1. Technical Field
The present invention relates to semiconductor circuits in general, and in particular to domino type logic circuits. Still more particularly, the present invention relates to a domino logic circuit having a clocked precharge.
2. Description of the Prior Art
A domino type of logic circuit simplifies digital logic by connecting a number of transistors together in series to implement digital combination logic. For example, a domino logic circuit implements a logic AND function by cascading a P-channel transistor with several N-channel input transistors in series. During operation, the P-channel transistor is clocked to precharge an output node of the circuit to a predetermined logic state. Depending on the logic state at the inputs of the N-channel input transistors, the output node either remains at its pre-charged state or is pulled low through the series of N-channel input transistors by a clocked N-channel transistor connected to ground.
In accordance with the logic AND function, if all of the N-channel input transistors are driven by a logic high signal, the output node of the domino logic circuit will be a logic low. Conversely, if any one of the N-channel input transistors is driven by a logic low signal, the output node of the domino logic circuit will remain at its precharged logic high state. Because no inversion function is performed with this conventional arrangement, an inverter is generally employed at the output of the domino logic circuit to perform a logic inversion function such that an overall logic AND function is realized.
The present disclosure describes an improved domino logic circuit that is able to provide an output signal faster than the conventional domino logic circuit described above.