DC to DC converters are electronic circuits that convert a source of direct current from one voltage to another. Switching DC to DC converters are commonly used because of their higher efficiency, which is especially important when the electronic device connected to the DC to DC converter is a battery-powered portable device.
FIG. 1 illustrates an example DC-DC converter 100 based on a step-down switching circuit particularly suitable for meeting many of the general goals for supplying power to advanced digital circuits. Circuit 100 in FIG. 1 (simplified to facilitate illustration and discussion) is called a DE-DRC (Differentially Enhanced-Duty Ripple Control) circuit. The DE-DRC design has been previously published by the present inventor and others. See, for example, J. Fan, X. Li, S. Lim, and A. Huang, “Design and Characterization of Differentially Enhanced Duty Ripple Control (DE-DRC) for Step-Down Converter,” IEEE Trans. Power Electron., vol. 24, no. 12, pp 2714-2725, December 2009. In FIG. 1, a power source 102 provides direct current at an input voltage VIN.
The circuit 100 provides direct current to a load (RLOAD) at an output voltage VOUT. Two electronic switches (SW1, SW2) are controlled by a switch control circuit 110 and driver 112. At most only one switch is closed at any one time. A comparator 108 controls the switch control circuit 110. There are two feedback paths. In a first feedback path, the voltage VSW on the switched side of the inductor LO is coupled to the comparator 108 through a low pass filter (RR, CR). In a second feedback path, two differential difference amplifiers (104, 106) generate a differential pair of feedback signals, VP and VN. These two differential signals are coupled to comparator 108, where VN is directly coupled, and VP is coupled through a high pass filter (CR, RR).
VP and VN are as follows:VP=KP(HVOUT−VREF)+VOUT VN=−KN(HVOUT−VREF)+VOUT Where H=RS2/(RS1+RS2), KP=gain of positive differential circuit 104, and KN=gain of negative differential circuit 106, and VREF is a constant reference voltage.
The first feedback path coupling VSW to the comparator 108 is fast because there are only passive components between VSW and the comparator. The feedback path coupling VOUT to the comparator 108 is slower, because VOUT is proportional to the integral of current in COUT, and there are active amplifiers between VOUT and the comparator. The second loop can adjust the control bandwidth. Both loops have a big influence on the transient response. The two feedback loops combined provide a stable system with high bandwidth control.
To simplify the discussion, assume H=1 and VIN is constant. First, consider the steady state (constant load). In the steady state, with H=1, VCONTROL (the positive input of the comparator 108) is approximately VOUT. VSW is a square wave, having an average value of approximately VOUT, and low-pass filtered VSW contributes a sawtooth waveform having an average value of approximately the average value of VSW to VRIPPLE (the negative input of the comparator 108). When VRIPPLE drops below VCONTROL, comparator 108 causes switch control circuit 110 to close SW1 for a constant on-time. VSW is driven higher while SW1 is closed, and VOUT is controlled to be approximately equal to the average value of VSW. If the load current increases, the average value of VSW increases rapidly (because of increasing current through LO), VP has a transient decrease (VOUT decreases due to an increased current draw from COUT), VN has a transient increase, and the duty cycle of SW1 is increased (switching frequency increases). If the load current decreases, the average value of VSW rapidly decreases, VP has a transient increase, VN has a transient decrease, and the duty cycle of SW1 is decreased. The magnitude of VRIPPLE at the negative input of the comparator 108 is relatively large compared to the ripple voltage on VOUT, which provides good noise immunity in the feedback signal. In addition, the circuit provides a fast response to load transients over a wide input and output range.
FIG. 2 shows an improved controller disclosed in co-pending commonly-assigned application Ser. No. 13/171,283 having common inventorship with the present application (see FIG. 3). This application is incorporated herein by reference in its entirety and for all purposes.
In FIG. 2, there are three feedback paths. In a first feedback path, the voltage VSW on the switched side of the inductor LO is AC coupled to the comparator 208. In a second feedback path, two differential difference amplifiers (204, 206) generate a differential pair of feedback signals, VP and VN. These two differential signals are coupled to comparator 208, where VN is directly coupled, and VP is coupled through a high pass filter network (CR1, RR)(CR2, RDC). In a third feedback loop, the reference voltage is adjusted by a reference adjust circuit 214.
VP and VN are as follows:VP=KP(HVOUT−VREF adjusted)+VBIAS VN=−KN(HVOUT−VREF adjusted)+VBIAS Where H=RS2/(RS1+RS2), KP=gain of positive differential circuit 204, and KN=gain of negative differential circuit 206, VREF adjusted is a variable reference voltage, and VBIAS is a fixed reference voltage.
The first feedback path coupling VSW to the comparator 208 is fast, because VRIPPLE is proportional to AC current in inductor LO, and there are only passive components between VSW and the comparator. The feedback path coupling VOUT to the comparator 208 is slower, because VOUT change is proportional to the integral of AC current in COUT, and there are active amplifiers between VOUT and the comparator. The feedback path adjusting VREF is intentionally very slow to avoid interference with the first two feedback paths. The third feedback path provides better output voltage accuracy. The three feedback paths combined provide a stable system with high bandwidth control and accurate output voltage.
These two control circuits are well-suited for controlling a single phase DC to DC converter power supply. However, there is a growing need for high amperage power supplies. For example, if one needs a 180 amp power supply and has an existing design for a 30 amp power supply, this need may be met by combining 6 of the 30 amp power supplies in parallel. This saves the cost of redesigning the power supply for higher amperage but it creates a problem which will be illustrated below in connection with FIGS. 3 and 4.
This problem is most easily explained utilizing a multiphase power supply comprising two DC to DC converters connected in parallel (phases 1 and 2, respectively) and having a single output terminal connected to a load. FIG. 3 illustrates the waveforms, generally indicated as 300, for the case where this two-phase system is operating at a 20% duty cycle. The current signal sensed for phase 1 is shown in FIG. 3A as 302. The current signal sensed for phase 2 is shown as 304 in FIG. 3B. The current sense signals 302, 304 are combined in FIG. 3C to yield ripple signal 306. In FIG. 3D, the ripple signal 306 is compared against a comp signal 308. When the ripple signal falls below the comp signal 308 (which is the output voltage of an error amplifier which compares a feedback voltage with a reference voltage), an ON pulse trigger signal such as 310, 312, 314, 316, 318 and 320 illustrated in FIG. 3F, is generated. The first ON pulse trigger signal 310 triggers the generation of a PWM signal 322 for phase 1, as shown in FIG. 3G. The second pulse trigger signal 312 triggers the generation of a PWM signal 324 for phase 2, as shown in FIG. 3H. The third ON pulse trigger signal 314 triggers the generation of PWM signal 326 for phase 1 (FIG. 3G). The fourth ON pulse trigger signal 316 triggers the generation of PWM signal 328 for phase 2 (FIG. 3H), and so on.
FIG. 4 illustrates the waveforms of the same circuit as FIG. 3, generally indicated as 400, except that the duty cycle has been increased to 50%. The current signal sensed for phase 1 is shown in FIG. 4A as 402. The current signal sensed for phase 2 is shown as 404 in FIG. 4B. The current sense signals 402, 404 are combined in FIG. 4C to yield ripple signal 406. The problem is that if both phases have equal currents and are exactly 180° out of phase, the current signals 402, 404 will cancel out and no ripple signal would be available to control the converters. Therefore, when the signal 406 is compared to the signal comp, no ON pulse trigger signals are generated as shown at 408 in FIG. 4E. Therefore, no PWM signals are generated for both phases 1 or 2 as shown in FIGS. 4F and 4G. Thus, the multiphase power converter is out of control. Even if the currents to each of the DC to DC converters were not the same and/or were not exactly out of phase, the ripple signal that results would be very small so that noise signals in the millivolt range could cause erratic operation of the multiphase power converter
Although the problem is most easily illustrated with a 2 phase multiphase power converter, the problem is common to any multiphase power converter system using combined current information for control. For a 3 phase system, the maximum duty cycle before this problem appears is 33.3%. For a 4 phase converter the maximum duty cycle before this problem appears is 25%. For the 6 phase converter discussed above, the maximum duty cycle before this problem appears is an unacceptable 16.6%. In general, the maximum duty cycle allowable before this problem appears is 1/n*100%, where n is the number of phases in the multiphase power converter system.
Therefore, there is a need for a controller for a multiphase power converter in which the duty cycle is not so limited.