1. Field of the Invention
The present invention relates to a semiconductor substrate and a method of manufacturing the same, and a semiconductor device utilizing such semiconductor substrate. More particularly, it relates to a semiconductor substrate for bipolar IC and BiCMOS and a manufacturing method thereof, and a semiconductor device utilizing such semiconductor substrate.
2. Description of the Background Art
FIG. 7 is a cross sectional view showing a buried diffusion epitaxial wafer formed by utilizing a conventional silicon substrate for bipolar IC and BiCMOS. Referring to FIG. 7, in the conventional buried diffusion epitaxial wafer, a buried diffusion layer 12 is formed on a top surface of a single crystal silicon substrate 13 at a predetermined interval. An epitaxial layer 11 of silicon is formed on the top surface of single crystal silicon substrate 13 and buried diffusion layer 12. A polycrystalline silicon layer 14 having a thickness of 1.0-2.5 .mu.m is formed on a rear surface of single crystal silicon substrate 13.
Buried diffusion layer 12 is formed for decreasing collector resistance of bipolar IC or BiCMOS formed in epitaxial layer 11. Polycrystalline silicon layer 14 is formed for conducting gettering utilizing crystal defects included therein. Heavy metals such as Cu, Fe, and Au entered during manufacturing process are removed from electrically active regions of semiconductor elements by gettering.
A method of manufacturing a conventional buried diffusion epitaxial wafer shown in FIG. 7 will be described.
Single crystal silicon substrate 13 is grown by Czochralski method. Czochralski method is disclosed, for example, in Semiconductor Silicon Crystal Technology (1989), Academic Press, Inc., by Fumio Shimura, pp. 129-131. FIG. 8 is an illustration of manufacturing of a single crystal by Czochralski method. Referring to FIG. 8, polycrystalline silicon (not shown) is put in a quartz crucible 51 and heated by a heater 50 to be turned to melted silicon 52.
Then, the melted silicon 52 is brought into contact with a seed crystal 200 which is pulled up while being rotated. Accordingly, a single crystal silicon (silicon ingot) 100 having the same crystal axis as seed crystal 200 is grown. The pulling up speed of the conventional single crystal silicon 100 is about 1.0 mm/min. The interstitial oxygen concentration of single crystal silicon 100 has been controlled to 9-16.times.10.sup.17 (atoms/cm.sup.3) according to the old ASTM (old American Society for Testing and Materials).
Then, single crystal silicon 100 formed as described above is sliced thin so as to form single crystal silicon substrate 13 as shown in FIG. 7.
Thereafter, polycrystalline silicon layer 14 is formed on the rear surface of single crystal silicon substrate 13 by the CVD method at the temperature of 650.degree. C. Buried diffusion layer 12 serving as a floating collector of the bipolar element is formed in a predetermined region on the top surface of single crystal silicon substrate 13 at a predetermined interval by, for example, the ion implantation method. Epitaxial layer 11 is grown on single crystal silicon substrate 13 and buried diffusion layer 12 at the temperature of about 1100.degree. C.
Conventionally, the buried diffusion epitaxial wafer is formed as described above. Bipolar IC or BiCMOS is formed in epitaxial layer 11 of such buried diffusion epitaxial wafer. For example, as shown in FIG. 7, a bipolar transistor including a base layer 16, an emitter layer 17, and a collector layer 18 has been formed on the main surface of epitaxial layer 11. An isolation layer 15 has been provided in order to isolate such bipolar transistors.
Conventionally, as described above, the interstitial oxygen concentration of single crystal silicon substrate 13 is controlled to 9-16.times.10.sup.17 (atoms/cm.sup.3) according to the old ASTM specification.
However, in the conventional buried diffusion epitaxial wafer shown in FIG. 7, heat treatment is conducted at the temperature of 650.degree. C. at the time of formation of polycrystal silicon layer 14, and in addition, heat treatment at the temperature of 1100.degree. C. is conducted during the growth of epitaxial layer 11.
In this case, if interstitial oxygen concentration is as high as 15.0.times.10.sup.17 (atoms/cm.sup.3), generation of internal precipitation defects is accelerated because of heat hysteresis of the above-mentioned heat treatments. This results in crystal defects even in the element formation region of epitaxial layer 11 (a region up to a few .mu.m from the surface of epitaxial layer 11).
When there is such a large amount of internal precipitation defects as to form crystal defects even in the element formation region, electrical characteristics of elements are deteriorated and warp of the buried diffusion epitaxial wafer is increased. Further, if crystal defects are precipitated even in the element formation region, crystal layers are slipped with each other. Such slipping is disclosed in, for example, Semiconductor Silicon Crystal Technology (1989), Academic Press, Inc., by Fumio Shimura, pp. 60-63, and pp. 286-289.
In the conventional buried diffusion epitaxial wafer shown in FIG. 7, gettering of heavy metal impurity is conducted by using crystal defects in polycrystalline silicon layer 14 and internal precipitation defects in single crystal silicon substrate 13. In this case, if single crystal silicon substrate 13 having a low interstitial oxygen concentration such as 10.times.10.sup.17 (atoms/cm.sup.3) is used, there is not provided enough internal precipitation defects to carry out gettering of the heavy metal impurity generated during formation of elements.
When gettering is not sufficient, the heavy metal impurity is precipitated up to the surface of epitaxial layer 11 so that OSF (Oxidation Induced Stacking Fault) is formed on the surface of epitaxial layer 11 with the heavy metal impurity serving as a carnal. Such OSF deteriorates electrical characteristics of elements.
Conventionally, various problems as described above have occurred, because the range of the interstitial oxygen concentration of single crystal silicon substrate 13 is set rather wide without considering heat treatment and gettering effect during formation of polycrystalline silicon layer 14 and epitaxial layer 11.
When forming single crystal silicon substrate 13 by Czochralski method, if the speed of cooling the single crystal silicon 100 which is pulled up is too fast, point defects generated during the growth of crystals are combined to form a large crystal defect.
If single crystal silicon substrate 13 shown in FIG. 7 is cut away from single crystal silicon 100 having such a large defect an inconvenience is generated. If there is a large defect in single crystal silicon substrate 13, many crystal defects are generated also on the surface of epitaxial layer 11 grown up on the top surface of single crystal silicon substrate 13. Thus, if elements are formed on the surface of epitaxial layer 11 including many crystal defects, the electrical characteristics of elements are deteriorated.