The present invention relates to a semiconductor device comprising a chip size package of the type used for a high density mounting module, a multichip module, and the like, a method of manufacturing the same, and to a semiconductor wafer used for manufacturing the semiconductor device.
Currently, in accordance with the current trend toward making electronic devices small, while retaining a high performance, semiconductor devices used therein are required to have a high integration, a high density, and to have a fast processing speed.
Corresponding to such a requirement, the methods of manufacture of semiconductor devices have been changed from the pin insertion type to a surface implementing method for increasing the implementing density; and, in order to accommodate an increasing number of pins, packages, such as a DIP (Dual Inline Package),a QFP (Quad Flat Package), a PGA (Pin Grid Array), and the like, have been developed.
However, implementation of the QFP is becoming difficult because of the increasing number of pins, since the connecting leads with the implementing substrate are concentrated at the periphery of the package, and the lead itself is thin and can be readily deformed. The PGA is disadvantageous in a high density implementation, because the increasing processing velocity is difficult to attain electrically, since terminals of the PGA for connecting with the implementing substrate are slender and are concentrated so as to be extremely close to each other, and surface implementation is impossible, since the PGA package is a pin insertion type.
Recently, in order to solve the above problems and to realize a semiconductor device having an increased processing velocity, a BGA (Ball Grid Array) package has been developed. The BGA package comprises a stress buffer layer between semiconductor chips and a substrate whereon circuits are formed, and bump electrodes, which are external terminals, on the implementing substrate side of the substrate whereon circuits are formed (U.S. Pat. No. 5,148,265). A package having a BGA structure is readily implemented on the surface, because deformation of the leads, such as occurs in a QFP does not occur, since the terminals for connection with the implementation substrate are provided in the form of ball-shaped solders, and the pitch between the terminals can be wide, since the terminals are dispersed all through the implementing plane. Furthermore, because the length of the bump electrode, i.e. the external terminal, is short in comparison with the PGA package, the inductance component is small, the signal velocity is fast, and it is possible to accommodate the requirement to increase the processing velocity.
On the other hand, JP-A-8-172,159 (1996) discloses a LOC (Lead On Chip) package, which comprises a cross sectional composition formed of sealing material/chip/protecting film/sealing material, as a chip provided with a protecting film. The protecting film increases the adhesion of the chip with the sealing material, and, at the same time, protects the chip from damage by a pick up pin.
JP-A-7-135189 (1995) discloses an invention relating to a wafer adhesion sheet for manufacturing semiconductor devices having a LOC structure. The wafer adhesion sheet is used as a protecting film until the chip is mounted in a package during the process for manufacturing the semiconductor.
Recently, in accordance with widespread use of portable information terminals, a decrease in size and a high density mounting of semiconductor devices are required. Therefore, a CSP (Chip Scale Package), the package size of which is almost the same as chip, has been developed. A CSP of various types has been disclosed in “Nikkei Micro Device” p38–p64, published by Nikkei BP Co. (February, 1998). A CSP is typically manufactured by the steps of: adhering semiconductor chips, which has been cut into respective pieces, onto a polyimide substrate or ceramic substrate, whereon a circuit layer is formed; electrically connecting the circuit layer with the semiconductor chip by a method such as wire bonding, single point bonding, gag bonding, bump bonding, and the like; sealing the connecting portion with a resin; and forming external terminals, such as solder bumps.
JP-A-9-232256 (1997) and JP-A-10-27827 (1998) disclose methods of mass production of a CSP. In accordance with these methods, the semiconductor device is manufactured by the steps of: forming bumps on the semiconductor wafer; connecting the circuit substrate electrically via the bumps; sealing the connecting portions with a resin; forming the external electrodes on the circuit substrate; and cutting the wafer into respective pieces. The “Nikkei Micro Device” p164–p167, published by Nikkei BP Co. (April, 1998), discloses another mass production method for the CSP. In accordance with the disclosed method, the semiconductor device is manufactured by the steps of: forming bumps on the semiconductor wafer by soldering; sealing portions other than the bumps with a resin; forming external electrodes at the bump portions; and cutting the wafer into respective pieces.
Among the CSP which are assembled by adhering the semiconductor chips cut in pieces to a polyimide substrate or a ceramic substrate, a CSP wherein a circuit layer is connected to the chip by wire bonding becomes larger than the chip size, naturally, because the bonding area of the circuit layer is located outside of the chip. In the case of a CSP connected by bump bonding, the substrate becomes larger than the chip in order to prevent resin from flowing down at the time of potting, because the interval between the chip and the substrate is sealed with resin after bonding. Accordingly, a problem occurred in that the package size of such a CSP became larger than the chip.
A CSP using chips cut in pieces experienced a problem in that it took a long time to manufacture the semiconductor device, because, after dicing the chips, each respective chip must be located correctly on the substrate, adhered thereon, connected electrically, and sealed.
A CSP using a resin substrate, such as a substrate made of polyimide and the like, as the circuit layer had a problem in that water, absorbed in the package at re-flowing when the package was provided onto the mounting substrate, was expanded and failures, such as bubble formation and peeling off, were generated, because the chip was adhered with an adhering agent.
A CSP, which was manufactured by the steps of: forming bumps on the semiconductor wafer; connecting the semiconductor wafer with the substrate; sealing the interval between the substrate and the semiconductor wafer with a resin; forming the external electrodes; and cutting the semiconductor wafer into respective pieces; had a problem of warping of the semiconductor wafer and the semiconductor device due to curing shrinkage, because the resin layer was formed on only one side of the wafer.
Additionally, except for the wire bonding type CSP, many of the CSP have an exposed plane, which is opposite to the plane whereon the circuits are formed on the chip. Therefore, there was a problem in that failures, such as cracks, were generated at the edge of the chip, and damage to the rear plane occurred due to the package falling down during transportation and handling thereof, such as when the package is picked up during a mounting operation.