The present invention relates to a clock signal generator using fractional division of frequency and to means for keeping said clock signal generator under the control of a synchronization signal.
The majority of electronic circuits are now designed to operate using a determined frequency clock signal produced by an oscillator. When a piece of equipment includes circuits that are designed to operate on different clock signals, a first solution consists in using a specific oscillator circuit for each clock signal. This solution is clearly not an economical way of solving the problem. Use is often made, when the frequency of a first clock signal is not a multiple of the frequency of a second one, of a clock signal generator employing fractional division of its frequency. Such a clock signal generator, when it is fully implemented in digital technology produces a signal the average frequency of which over one full period is the frequency of the signal it is receiving divided by a division ratio.
The use is known of a programmable counter receiving a signal at a steady rhythm and adapted to periodically output, depending on the period of recurrency, a successive first and second series of pulses the frequencies of repetition of which are submultiples of the frequency of the steady rhythm signal. Such a device, apart from the programmable counter, requires two additional counters in order to determine the number of pulses in each series, together with control means. It hence occupies, where it is implemented in integrated form, a fairly large substrate surface area which is an obstacle to the miniaturization of the equipment in which it is incorporated.
European Patent 0 019 412 disclosed the use of a counter that is preceded by a pulse absorber or subtractor for fulfilling the function of a programmable counter. The pulse subtractor in effect eliminates pulses from the rhythm signal when commanded so to do thus modifying the frequency of the output signal from the counter.
Nevertheless, the phase shift between the output signal and a signal the frequency of which is exactly at the division ratio of the rhythm signal frequency is highly variable and can have an appreciable amplitude.
A first object of the present invention is to provide a clock signal generator using fractional division of frequency of reduced size made possible by the use of individual circuits that are more simple and the output signal of which only suffers from limited phase shifting relative to the desired frequency. This phase shift, in a preferred embodiment, is less than one period of the steady rhythm signal.
In certain fields of application, particularly in telecommunications systems receiving equipment, it is necessary to set the output signal from the clock signal generator under the control of a synchronization signal.
The present invention hence also has the object of providing control means that are specially suitable for this type of clock signal generator using fractional division of frequency.
Although one should not attempt to see a limitation of the invention in this, the provisions of the invention can advantageously be used in the Pan-European digital cellular radiocommunications system. In this system, a mobile terminal comprises a speech coding and decoding unit which can be implemented using a standard component working with 8 kHz and 2048 kHz clock signals. The terminal further includes an internal clock signal generator producing a 13 MHz steady rhythm signal, and produces a 50 Hz synchronization signal onto which the coding and decoding units require to be synchronized. The invention hence makes it possible, starting from this steady rhythm signal, to produce clock signals that are synchronized onto this synchronization signal.