1. Field of the Invention
The present invention relates to a load drive circuit and a display device, and in particular to a drive circuit and a display device successfully reduced in unnecessary radiation in operation of any display panel, which acts as a load, such as plasma display electro-luminescence display and liquid crystal display (LCD).
2. Description of the Related Art
FIG. 10 is a schematic drawing of a three electrode surface discharge AC-driven plasma display panel, and FIG. 11 is a sectional view for explaining the electrode structure of the plasma display panel shown in FIG. 10. In FIGS. 10 and 11, reference numeral 207 denotes a discharge cell (display cell), 210 denotes a rear glass substrate, 211 and 221 denote dielectric layers, 212 denotes a fluorescent material, 213 denotes a diaphragm, 214 denotes address electrodes (A1 to Ad), 220 denotes a front glass substrate, and 222 denotes X electrodes (X1 to XL) or Y electrodes (Y1 to YL). Reference symbol Ca denotes capacitance between the adjacent address electrodes, and Cg denotes capacitance between the opposing address electrodes (X electrode and Y electrode).
A plasma display panel 201 comprises two glass substrates of the rear glass substrate 210 and the front glass substrate 220, and the front glass substrate 220 has the X electrodes (X1, X2, . . . , XL) and the Y electrodes (scanning electrodes: Y1, Y2, to YL) disposed thereon as sustaining electrodes (including bus electrode and transparent electrode).
The rear glass substrate 210 has the address electrodes (A1, A2, . . . , Ad) 214 disposed thereon so as to cross normal to the sustaining electrodes (X electrodes and Y electrodes) 222, and the display cell 207 causing discharge light emission with the aid of these electrodes is formed in each area which falls between the X electrode and Y electrode having the same number (Y1-X1, Y2-X2, . . . ), and on the intersection with the address electrode.
FIG. 12 is a block diagram showing an entire configuration of a plasma display device using the plasma display panel shown in FIG. 10, and more specifically showing an essential portion of a drive circuit for the display panel.
As shown in FIG. 12, the three electrode surface discharge, AC-driven plasma display device comprises the display panel 201, a control circuit 205 for generating a control signal for controlling the drive circuit of the display panel in response to an externally-input interface signal, an X common driver (X electrode drive circuit) 206 for driving the panel electrodes using the control signal from the control circuit 205, a scanning electrode drive circuit (scan driver) 203 and Y common driver 204, and an address electrode drive circuit (address driver) 202.
The X common driver 206 generates sustaining voltage pulse, the Y common driver 204 similarly generates sustaining voltage pulse, and the scan driver 203 effects scanning by independently driving the individual scan electrodes (Y1 to YL). The address driver 202 applies an address voltage pulse to the individual address electrodes (A1 to Ad) corresponding to display data.
The control circuit 205 has a display data control section 251 for supplying an address control signal to the address driver 202 upon receiving of clock CLK and display data DATA, a scan driver control section 253 for controlling the scan driver 203 upon receiving of vertical synchronizing signal Vsync and horizontal synchronizing signal Hsync, and a common driver control section 254 for controlling common drivers (X common driver 206 and Y common driver 204). The display data control section 251 has a frame memory 252.
FIG. 13 is a drawing showing an exemplary drive waveform of the plasma display device shown in FIG. 12, and shows outlines of voltage waveforms applied to the individual electrodes in the all-write period (AW), all-erasure period (AE), address period (ADD) and sustaining period (sustained discharge period: SUS).
In FIG. 13, drive periods directly related to image display are the address period ADD and sustaining period SUS, where a pixel to be displayed is selected in the address period ADD, and the selected pixel is then kept in an emission state so as to allow image display in a predetermined brightness. It is to be noted that FIG. 13 shows drive waveforms of the individual sub-frames for the case where one frame is composed of a plurality of subframes (sub-field).
First, in the address period ADD, all of the Y electrodes (Y1 to YL), which are scanning electrodes, are applied with an intermediate potential −Vmy en bloc, and then sequentially applied with a scanning voltage pulse of −Vy level as being switched from −Vmy. In this process, pixels on the individual scanning lines can be selected by applying an address voltage pulse of +Va level to the individual address electrodes (electrode A: A1 to Ad) in synchronization with the application of the scanning pulses to the individual Y electrodes.
In the succeeding sustaining period SUS, all of the scanning electrodes (Y1 to YL) and X electrodes (X1 to XL) are alternately applied with a sustaining voltage pulse of +Vs level, so as to induce sustained emission at the previously selected pixels, and to allow display at a predetermined luminance through such successive application. It is also made possible to effect gradation display by controlling the number of times of light emission by combining basic operations expressed by such series of operation waveforms.
The all-write period AW is provided for applying a write voltage pulse to all of the display cells in the panel so as to activate the individual display cells and to keep the display characteristics uniform, and is inserted at certain constant intervals. The all-erasure period AE is provided for erasing previous display contents before the address operation and sustaining operation for image display are newly commenced, through application of an erasure voltage pulse to all of the display cells on the panel.
FIG. 14 shows an exemplary circuit diagram of the address drive circuit used for the address driver 202 of the plasma display device shown in FIG. 12. The address electrode drive circuit shown in FIG. 14 is disclosed typically in Patent Document 1 below. The address electrode can be assumed as a capacitive load 100 as shown in the drawing, because most of the current components flow through the address electrodes (A1 to Ad) are charge-discharge current for parasitic capacitance of the electrodes.
[Patent Document 1] Japanese Patent Application Laid-Open No. 5-249916
Assuming now that the number of the address electrodes (A1 to Ad) of the display panel reaches as much as 3072 (1024 pixels×RGB), the circuit is configured so that the outputs of 24 drive ICs, each having 128 address electrode drive circuit shown in FIG. 14 integrated therein, are connected to the address electrodes. The connection to the address electrodes is made typically through a flexible substrate on which the drive ICs are mounted in a unit of a single chip or two or more chips.
In the circuit diagram shown in FIG. 14, a single address electrode corresponds to the capacitive load 100. A low-side output element (N-channel MOSFET) 101 is connected between the ground, which is a low-voltage-side reference potential, and the capacitive load 100. A high-side output element (P-channel MOSFET) 102 is connected between a drive power source 107, capable of supplying high-voltage potential Va which corresponds to high-level of the address drive voltage, and the capacitive load 100.
As an exemplary circuit for driving the high-side output element 102, FIG. 14 shows a level shift circuit 108. The level shift circuit 108 drives the high-side output element 102 with the aid of an inverter circuit which comprises a P-channel MOSFET 103 and an N-channel MOSFET 104. The P-channel MOSFET 103 is driven by flip-flop operation of another inverter circuit which comprises a P-channel MOSFET 105 and an N-channel MOSFET 106.
Operation in the address period ADD (FIG. 13) will be explained referring to a timing chart shown in FIG. 15. FIG. 15 shows timing relations between output voltage Vo of the address electrode drive circuit and input voltages VG1 to VG6 of the individual drive elements 101 to 106. In a rise-up period AT of output voltage Vo, the low-side output element 101 is cut off by inverting input voltage VG1 from high level to the low level, and the high-side output element 102 is turned on by inverting input voltage VG4 into the high level and input voltage VG6 into the low level. This adjusts output voltage Vo to high voltage potential Va. On the contrary, in the decay period TB of output voltage Vo, the high-side output element 102 is cut off by inverting input voltage VG4 into the low level and input voltage VG6 into the high level, and the low-side output element 101 is turned on by inverting input voltage VG1 into the high level. This adjusts output voltage Vo to the ground level (0V).
The rise-up time and decay time as seen in the waveform of output voltage Vo shown in FIG. 15 refer to times for charging and discharging the load capacitance 100 with the output currents from the high-side output element 102 and low-side output element 101. It is to be noted herein that the adjacent address electrodes on the display panel 201 shown in FIG. 11 are switched between high-voltage potential Va and the ground level depending on image to be displayed. The load capacitance 100 in this case therefore can largely vary and affect as follows. For the case where the adjacent electrodes placed on the left and right sides of a target address electrode are switched at the same time in the same direction (i.e., together from the ground level to high-voltage potential Va), the load capacitance 100 will have a minimum value as being contributed only by capacitance Cg without including capacitance Ca between the adjacent electrodes which are in no need of charge nor discharge. On the contrary, for the case where the left and right adjacent electrodes are switched at the same time in the opposite directions (i.e., one varies from the ground level to high-voltage potential Va, and the other varies from high-voltage potential Va to the ground level), the capacitive load 100 will have a maximum value of Cg+4Ca because both capacitances Ca between the adjacent electrodes will be supplied with doubled electric charge. Ratio of variation in the load capacitance 100 therefore reaches three times or more in general. Output currents from the high-side output element 102 and low-side output element 101 must be designed as being sufficiently large so as to successfully obtain a drive speed necessary for the display panel 201. This, however, results in a sharp change in the waveform of output voltage Vo under the minimum load and consequently in a drastic decrease in the transition time, and therefore raises a problem of increase in unnecessary electromagnetic radiation ascribable thereto. Interference of any other electronic instruments caused by unnecessary electromagnetic wave is known as EMI (electromagnetic interference), and is necessarily suppressed to a level allowable by any specified standards. In general procedures for suppressing unnecessary radiation, lack of suppressive measures in the initial stage of the design will unfortunately increase costs for any additional electromagnetic shield or filter elements.