1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, to a semiconductor device capable of increasing an effective channel length and width, which has a plurality of grooves and a method of fabricating the same.
2. Description of the Related Art
As semiconductor memory devices are highly integrated, a width of a gate electrode of a MOS transistor is reduced to about 0.1 μm and a channel length of the MOS transistor must be reduced. With reduced channel length, electrons can easily pass a gate insulating layer of the MOS transistor, and the so called “hot carrier effect” occurs because an electric field between a source and a drain of the MOS transistor is strengthen by the reduced channel length, causing flow of leakage current. Thus, the short channel effect from a reduced channel length of the MOS transistor adversely affects characteristics of the MOS transistor.
One way to alleviate the short channel effect is by elongating the channel length without changing a design rule of the gate electrode.
FIGS. 1A to 1C are cross-sectional views of structures illustrating a conventional fabricating method of a semiconductor device having grooves for elongation of effective channel length.
Referring to FIG. 1A, nitride layer patterns 12 are formed on a semiconductor substrate 10 having a device isolation layer (not shown) to expose a channel region of a MOS transistor. Next, insulating layer spacers 14 are formed on both lateral sides of the nitride layer patterns 12. Then, a thermal oxide layer 16 is formed on an exposed semiconductor substrate 10 by a thermal oxidation process.
Referring to FIG. 1B, the thermal oxide layer 16 and the insulating spacers 14 are removed by a wet etching process to form a groove 18. Next, ions 20 are implanted on the semiconductor substrate 10 adjacent to the groove 18 for controlling a threshold voltage. Next, a gate insulating layer 22 is deposited on the semiconductor substrate 10 having the groove 18 at a predetermined thickness, and a polysilicon layer 24 is deposited on the semiconductor substrate 10 having the gate insulating layer 22 to fully fill the groove 18 between the nitride layer patterns 12. The polysilicon layer 24 is planarized to form a gate electrode 24 by a chemical mechanical polishing (CMP) process until the nitride layer pattern 12 is exposed.
Referring to FIG. 1C, the nitride layer pattern 12 formed on both lateral sides of the gate electrode 24 is removed, and spacers 28 are formed on both lateral sides of the gate electrode 24. Conjunction regions 26 and 30 having a lightly doped drain (LDD) are formed beneath the spacers 28 and adjacent to the bottom of the spacers 28. As a result, a channel is formed under the gate electrode 24. The channel is formed to be elongated since the bottom surface of the gate electrode has a groove.
However, as design rule of the gate electrode 24 is about 0.1 μm, the distance between the nitride patterns 12 should be within the design rule. During the thermal oxidation process for forming the thermal oxide layer 16, the semiconductor substrate 10 is subject to severe stress because of the nitride layer pattern 12, even if the spacers 14 are formed. Further, when the thermal oxidation process is partially performed, a bird's beak can be easily formed, thereby making difficult the forming of a delicate groove. Thus, there still continues to be a need for an improved fabricating method for elongating an effective channel length and width to improve current characteristics of a semiconductor device.