This invention relates generally to shift registers and particularly to a shift register stage useful as a select line scanner for liquid crystal displays.
Liquid crystal television and computer displays (LCDs) are known in the art. For example, see U.S. Pat. Nos. 4,742,346 and 4,766,430, both issued to G. G. Gillette et al. Displays of the type described in the Gillette patents include a matrix of liquid crystal cells which are arranged at the crossovers of data lines and select lines. The select lines are sequentially selected by a select line scanner to produce the horizontal lines of the display. The data lines apply the brightness (gray scale) signals to the columns of liquid crystal cells as the select lines are sequentially selected.
Preferably, the drive circuitry, which drives the select line scanner, which selects the horizontal lines to be displayed, is fabricated directly onto the same substrate and at the same time as the liquid crystal cells are fabricated. Also, because a large number of data lines and select lines are required for a television or computer display, and because the small pixel pitch limits the space available for laying out the driver circuitry, it is essential to keep the circuitry as simple as possible.
FIG. 1 illustrates an example of a known scan register described in U.S. Pat. No. 5,222,082, which may be integrated with a liquid crystal display device. This register is driven with multiphase clocking signals C1, C2, C3, with different ones of the clock phases applied to different ones of the scan register stages 11.
FIG. 2 illustrates one of the scan register stages in detail. The scan register stage includes an input section including transistors 18 and 19, an intermediate section including transistors 20 and 21 and an output section including transistors 16 and 17.
The output section is arranged as a push-pull amplifier, with a clocked supply potential connected to its supply connection 14. An output is accessed at the interconnection of the transistors 16 and 17.
The input section is arranged as a switched amplifier to exhibit a predetermined potential during the clock phase applied to the supply terminal of the output section. The output signal, P1, of the input stage, is coupled to drive the output transistor 16. More particularly the output, P1, follows the input signal applied to the gate electrode of transistor 18. The output of the input section will be high when the clock phase applied to terminal 14 goes high, and a high level is translated to the output terminal 13. The high level at node P1 is retained at node P1 until the occurrence of a clock phase C3 when the input signal is low. Thus the gate of the output transistor 16 will be at a high level when the clock C1 goes high providing a charging path to output 13 and when clock C1 goes low, providing a path to discharge the output node 13.
The intermediate section is arranged as a clocked inverting amplifier responsive to the input signal. The output of the intermediate stage is coupled to the gate electrode of the pull down transistor 17 of the output stage. The intermediate stage includes pull up and pull down transistors 20 and 21 respectively. The conductance of transistor 21 is greater than that of transistor 20 so that if both transistors 20 and 21 are conducting concurrently, the output potential at node P2 will remain low. Thus if the clock applied to transistor 20 is high when the input signal is high, the output transistor 17 will be maintained in a non-conducting state. However since the application of the stage is as a scan register, input signal pulses occur relatively infrequently. As a result node P2 will normally be charged high for every clock pulse of clock phase C3 and output transistor 17 will normally be conducting.
The drains of transistors 18 and 20 receive a relatively positive biasing voltage V.sub.DD of about 16 volts. Thus node P2 is normally biased at about 16 volts. This places excessive stress on the gate electrodes of transistors 19 and 17 which tends to cause a considerable rise in their respective threshold voltages over time. As the threshold of transistor 19 increases, its ability to discharge node P1 decreases, and more time is required to turn off transistor 16. The result is that some of the clock C1 voltage may leak onto the output node 13 and undesirably affect subsequent register stages as well as erroneously addressing an LCD row of pixels.
The present invention addresses these problems and provides a shift register stage which not only precludes false output values, but also consumes less power.