1. Field of the Invention
The present invention relates to a differential amplifier circuit and, more particularly to, a differential amplifier circuit wherein the offset voltage is compensated for.
2. Description of the Related Art
FIG. 10 shows a conventional differential amplifier circuit comprising NPN transistors Q1 and Q2, current source A, and PNP transistors Q3 and Q4. Input signals V1 and V2 are supplied to the base of transistor Q1 and the base of transistor Q2, respectively. Current source A is connected between the common emitter of transistors Q1 and Q2 and the ground GND. PNP transistors Q3 and Q4 function as active loads of transistors Q1 and Q2, respectively. The offset voltage of this differential amplifier circuit will be discussed.
The bases of PNP transistors Q3 and Q4 are mutually connected, and the emitters of these transistors are coupled to power-supply Vcc terminal. Therefore, the base-emitter voltage Vbe3 of transistor Q3 is equal to the base-emitter voltage of transistor Q4. Hence: EQU (Ic3/Is3)=(Ic4/Is4)
where Ic3 is the collector current of transistor Q3, Ic4 is the collector current of transistor Q4, Is3 is the reverse saturation current of transistor Q3, and Is4 is the reverse saturation current of transistor Q4.
The collector current Ic2 of transistor Q2 is given: EQU Ic2=Ic4=Ic3(Is4/Is3)
The collector current Ic1 of transistor Q1 is given: EQU Ic1=Ic3(1+2/.beta.p)
where .beta.p is the current-amplification factor of PNP transistors Q3 and Q4.
Thus, the offset voltage Vos of the differential amplifier circuit shown in FIG. 10 is: ##EQU1## Here, let us assume that: ##EQU2## Then, the offset voltage Vos can be represented as follows: ##EQU3## Since .DELTA.Isp&lt;&lt;Isp, and .DELTA.Isn&lt;&lt;Isn, this equation reduces to: ##EQU4## Here is the relationship: EQU ln(1+x)=x-(x.sup.2 /2)+(x.sup.3 /3) . . .
And .DELTA.Isp/Isp&lt;&lt;1, .DELTA.Isn/Isn&lt;&lt;1, and 2/.beta.p&lt;&lt;1. Therefore, the second term et seq. of the above equation can be neglected. Hence: ##EQU5## The values of .DELTA.Isp/Isp and .DELTA.Isn/Isn, both included in equation (1), are determined by the characteristics of the transistors used in the differential amplifier circuit. The third term in the right side, i.e., 2/.beta.p, is a factor which is determined by the structure of the circuit and the characteristics of the transistors used therein.
Assuming that V.sub.T =26 mV, .DELTA.Isp/Isp=5%, .DELTA.Isn/Isn=5%, and .beta.p=10, then the worst value for Vos will be: EQU Vos=26 (0.05+0.05+0.1)=7.8 mV
Hence that portion of the offset voltage which is determined by the their term in the right side of equation (1) is 2.6 mV (=26.times.0.1).
As has been pointed, the third term in the right side of equation (1) is determined by the structure of the circuit and the characteristics of the transistors used in this circuit. When PNP transistor Q5 is added to the circuit shown in FIG. 10, with its base coupled to the collector of transistor Q3 its emitter connected to the common base of transistors Q3 and Q4, and its collector connected to the ground, as is illustrated in FIG. 11, then, equation (1) changes to: ##EQU6##
When factors which are similar to those mentioned above, is applied, then: EQU Vos=26 (0.05+0.05+0.0182)=3.07 mV
In the circuit shown in FIG. 11, that portion of the offset voltage which is determined by the third term in the right side of equation (2) is 0.47 mV (=26.times.0.0182), far lower than the corresponding portion of the offset voltage of the differential amplifier circuit shown in FIG. 10. Nonetheless, the offset voltage (i.e., 2.6 mV) of the circuit is still too high.