1. Field of the Invention
The present invention relates to demodulation circuits for use in direct sequence modulation systems and, more specifically, to demodulation circuits for use in biphase balanced modulation systems.
2. Description of the Prior Art
Direct sequence modulation systems are known in the art. In such systems, an RF carrier signal is modulated by a digital code sequence whose bit rate is much higher than the information signal bandwidth. One of the preferred modulation formats for such systems is the biphase balanced modulation scheme in which the carrier is transmitted with one phase when the code sequence is a binary ONE and with a 180.degree. phase shift when the code is a binary ZERO.
Various techniques for detecting biphase modulated signals are known. In general, such techniques are coherent processes requiring that the receiver include a local code reference that is an accurate estimate of the received code modulation. Prior art techniques for providing this local code reference are effective but require relatively complex circuitry.
One of the better known demodulators for this type of system, for instance, is the Costas loop, as described in the book: "Spread Spectrum Systems" by R. C. Dixon and published by John Wiley & Sons, New York, in 1976. However, Costas loops are relatively complicated in that they require a pair of demodulators in phase quadrature with each other. When the loop is phase locked, one of the demodulators will be in quadrature with the incoming signal and its output will be basically zero. The reference associated with the other demodulator will demodulate the signals at the maximum value, which may be either positive or negative, depending upon the instantaneous phase of the modulation. Typically, the incoming signal is integrated for a period of one bit, after which time the output of the demodulator which is in phase with the signal is sensed to determine if it is positive or negative, whereupon either the direct or inverted error signal may be used. Thus the Costas loop typically requires integrated dump circuitry, decision making circuitry, and means for inverting the error signal.
In contrast, the circuit of the present invention typically requires only a phase-lock loop, a flip-flop, and an exclusive OR gate.