Lithographic projection apparatus (tools) can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask contains a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (for example, but not limited to a silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole array of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire reticle pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus—commonly referred to as a step-and-scan apparatus—each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction; since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic apparatus as here described can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing. Thereafter, the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing”, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
The lithographic tool may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic tools are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
The photolithography masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). Another goal is to use as much of the semiconductor wafer real estate as possible. As the size of an integrated circuit is reduced and its density increases, however, the CD (critical dimension) of its corresponding mask pattern approaches the resolution limit of the optical exposure tool. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose on the wafer. The resolution value of present exposure equipment often constrains the CD for many advanced IC circuit designs.
Furthermore, the constant improvements in microprocessor speed, memory packing density and low power consumption for micro-electronic components are directly related to the ability of lithography techniques to transfer and form patterns onto the various layers of a semiconductor device. The current state of the art requires patterning of CD's well below the available light source wavelengths. For instance the current production wavelength of 248 nm is being pushed towards patterning of CD's smaller than 100 nm. This industry trend will continue and possibly accelerate in the next 5-10 years, as described in the International Technology Roadmap for Semiconductors (ITRS 2000).
This continued demand for improved performance has resulted in the development of various techniques aimed at improving resolution. Such techniques are typically referred to as Resolution Enhancement Techniques (RET's) and comprise a very wide range of applications. Examples include: light source modifications (e.g. Off-Axis Illumination), use of special masks, which exploit light interference phenomena (e.g. Attenuated Phase Shift Masks, Alternating Phase Shift Masks, Chromeless Masks, etc.), and mask layout modifications (e.g. Optical Proximity Corrections).
Of the foregoing techniques, dipole illumination is one of the most attractive RET candidates due to its high image contrast for dense pitches and superior resolution capabilities. As is known, dipole illumination is an extreme case of OAI and is capable of providing enhanced imaging contrast with improved process latitude for very low K1 imaging.
However, one of the limitations associated with dipole illumination is that a single illumination only enhances resolution for features that are orthogonal to the illumination pole axis. As a result, in order to take full advantage of dipole illumination during wafer printing, the mask pattern must be decomposed into horizontal and vertical orientations. Once the mask pattern is converted in this manner, a Y-pole exposure is utilized to image the horizontally oriented features, and a X-pole exposure is utilized to image the vertically oriented features. One important aspect of dipole illumination is that when imaging the horizontally oriented features, the vertically oriented features must be protected (i.e., shielded) so the vertically oriented features are not degraded. The opposite is true when vertically oriented features are imaged (i.e., the horizontally oriented features must be protected).
FIG. 1 illustrates the basic concepts of double dipole imaging. As stated, typically there are at least two exposures when utilizing dipole illumination. In the first exposure, the X dipole aperture 10 provides a maximum aerial image intensity (i.e., maximum modulation) for the vertical portion of the lines 12 to be printed. The resulting image profile is illustrated by line 24 in FIG. 1. In the second exposure, which utilizes the Y-dipole aperture 16, there is no image modulation for lines 12. It is noted, however, that during the second exposure using the Y-dipole aperture, the vertical portions of the lines 12 need to be shielded so that the vertical features formed during the first exposure are not degraded during the second exposure. FIG. 1 illustrates shielding the lines 12 with shields 15, each of which is 20 nm wide in the horizontal direction. As a result, when exposing the horizontal lines using the Y dipole aperture, there is substantially no imaging (i.e., modulation) of the vertical features 12. The aerial image is a DC modulation as shown by line 17 in FIG. 1, which corresponds to the 20 nm shielding. The final aerial image intensity, which is represented by line 14 in FIG. 1, corresponds to the sum of the first exposure using the X dipole aperture and the second exposure using the Y dipole aperture.
It is further noted that, assuming the exposure energy is constant, increasing the width of the shielding from a 20 nm shield 15 to a 40 nm shield 20 for the vertical lines 12 causes the minimal intensity level of the resulting image to shift to a lower level. This is represented by line 22 in FIG. 1, which represents the aerial image associated with the vertical portions of the features. As shown, the aerial image 22 is just a DC modulation. However, it is lower than the DC modulation 17 associated with the 20 nm shield. As a result, the composite image 19 formed utilizing the 40 nm shielding provides better imaging results than the composite image 14 formed utilizing the 20 nm shielding.
As a result of the need to separate the horizontally and vertically oriented features, one of the challenges for the lithographer, when utilizing dipole illumination, is determining how to convert the original IC design data into its horizontal or vertical pattern components and generate two masks for the dual exposure process that can take full advantage of the dipole imaging performance. One factor that reduces performance and which should be considered when generating the mask patterns is background light due to lens flare or scattering. As is known, lens flare results in unwanted background light (i.e., noise) that degrades the image contrast at the image plane. Thus, it is desirable to reduce “flare” as much as possible. This is especially true when utilizing dipole illumination techniques due to the multiple exposures associated therewith.
The “aerial image with flare” is equal to the “aerial image without flare” convolved with a point-spread function (PSF) plus the scattering. The foregoing can be expressed as:Iflare(x,y)=InoflarePSFflare+Inoflare(I−TIS)  (1)
where TIS is the total integrated scattering (TIS) for lens having a surface roughness with a Gaussian-like distribution. Under such conditions, TIS can be expressed as:TIS=[(4πσ cos θ)/λ]2  (2)
where λ is the wavelength of the exposure tool, σ is the rms roughness of the lens, and θ is the scattering angle. As a result of current lens making capabilities, which result in lens exhibiting extremely low surface roughness, the foregoing equation can be approximated as:TIS˜1/λ2  (3)
Equation (3) makes clear that as the wavelength of the exposure tool is reduced, the amount of scattered light increases significantly. For example, the total integrated scattering (TIS) of light for an exposure tool having a wavelength of 193 nm is approximately 1.65 times greater that the TIS associated with an exposure tool having a wavelength of 248 nm.
It is noted that the first term is equation (1) is the “diffuse halo” which causes the focused image to spread out. The second term in equation (1) is the contribution due to scattering. The overall effect is an unwanted DC background light that reduces the aerial image contrast. Furthermore, besides the negative impact on image contrast, flare is also unevenly distributed across the scanning slit and is not uniform with the exposure field, which can cause intrafield CD variations. Therefore, protecting features and reducing background stray light becomes increasingly critical. The issue of how to reduce or negate the effects of background stray light becomes even more important as the wavelengths of the exposure tools are reduced.
Currently, one known technique for reducing the negative effects of flare comprises the step of adding solid chrome shielding on the large areas of the mask pattern (i.e., background portions) that do not contain any geometry (i.e., features). As shown in FIGS. 2a and 2b, when utilizing dipole illumination, the solid chrome shielding, referred to as background light shielding (BLS), is applied to the background areas in both the horizontal mask and the vertical mask. The solid chrome shield functions to protect the background area during both exposures. FIG. 2a illustrates an example of the use of this shielding technique in conjunction with the printing of horizontally oriented features 29 utilizing the Y dipole 16. As shown in FIG. 2a, each of the vertical features 27 are provided with shielding 210 (i.e., main feature shielding) in the manner discussed above in conjunction with FIG. 1. In addition, the solid chrome shield 220 is provided in the background area where there are no features to be imaged on the wafer. In a similar manner, FIG. 2b illustrates the vertical mask, in which the horizontal oriented features are shielded, while the vertical features are printed. As shown, the vertical mask also includes a solid chrome shield 220 disposed in the background area. It is further noted that both the horizontal mask and the vertical mask contain assist features 103 (e.g., scatter bars).
However, as a result of such background shielding 220, when utilizing a positive resist, the intensity in the background areas becomes too low to completely clear the resist. FIGS. 3a and 3b illustrate a simulated resist pattern corresponding to the portion of the masks of FIGS. 2a and 2b defined by area 30, which includes the solid chrome shielding 220. The simulation was performed assuming NA (numerical aperture)=0.75, ArF double exposure x-pole, y-pole, σouter/σinner=0.89/0.65. As is shown by FIGS. 3a and 3b, portions of the resist 221 in the background areas remain after illumination using the vertical and horizontal masks. As a result, a third exposure utilizing a trim mask is necessary in order to completely remove the resist from the background shielded areas. Thus, such a solution for reducing the effects of flare is undesirable as it results in an increase in the number of exposures and masks required for imaging the wafer. Referring to FIG. 3a, the areas indicated by reference numeral 51 correspond to the areas where resist remains after the double exposures, and these areas are contrasted against areas of either the vertical or horizontal mask that had chrome disposed thereon (i.e., either feature or shielding).
Furthermore, the foregoing solid chrome shielding technique can also negatively interfere with assist features, such as scatter bars, and cause the assist features to print underneath the shielding of either the horizontal or vertical mask, as also illustrated in FIGS. 3a and 3b. For example, referring to FIG. 3b, as shown in the resist simulation, the assist features 103, which are intended to be sub-resolution, are printed as a result of the BLS 220. This problem imposes an additional constraint on the placement of assist features, which can prevent the assist features from being placed in the optimal position, thereby causing a reduction in printing performance.
Accordingly, there exists a need for a method for negating the effects of flare in the exposure process which does not result in an increase in the number of exposures and masks required for imaging the wafer, and which does not impact the use and/or placement of assist features in the mask.