1. Field of the Invention
The present invention relates to a circuit structure for use in an electronic circuit such as a logical circuit operating at a high speed and a memory, and in particular to a circuit structure of a semiconductor integrated circuit.
2. Related Background Art
A semiconductor integrated circuit of the type described generally includes a logical circuit or a memory formed in a semiconductor chip. With a demand for digitalization in recent years, a request is increased for digital semiconductor integrated circuit operating at a high speed in a GHz band. The digital semiconductor integrated circuit generally includes a large number of transistors. In this event, each transistor is connected to a power supply for supplying electric energy and to a ground which discharges the supplied energy, thereby forming a transistor circuit.
While such a transistor circuit operates as an on-off switch or a gate circuit, no signal is sent from the transistor even if the transistor is turned on unless the power source supplies the electric energy.
Considering the transistor gate circuit here, the gate circuit is instantly put into the on-state. If the on-resistance is low, such a phenomenon that the wiring is incapable of supplying electric charges occurs when the connected power supply attempts to supply electric energy (electric charges). It will be described later in detail why the wiring is incapable of supplying the electric energy. Likening the power/ground wiring to a transmission line and assuming its characteristic impedance is 50 Ω, if the on-resistance of the transistor gate circuit is lower than the characteristic impedance such as 15 Ω, the wiring is incapable of supplying the electric charges. Fortunately, the characteristic impedance of a signal line is 50 Ω or higher in many cases. Consequently, a problem of failure in supply can be avoided. It is necessary, however, to cope with an instant change for supplying charges to a transistor parasitic capacitor. At any rate, it is required to make a pipe for supplying charges thick, namely, to adopt a method and a structure for lowering the power/ground characteristic impedance. Therefore, the inventors of the present invention has proposed a method and a circuit structure for lowering the power/ground characteristic impedance in Japanese Unexamined Patent Publication (JP-A) No. 2000-174505.
Further, if a switching operation of the transistor circuit becomes faster, an inductance against a sharp increase of current can not be ignored with the above-mentioned problem. Even if the power/ground characteristic impedance is lower than that of the signal line, it cannot catch up with rapid opening of a transistor gate circuit and a parasitic capacitance charge due to the parasitic inductance of the power/ground wiring. Therefore, a method and a structure for lowering the parasitic inductance are necessary.
Moreover, signal energy (charge quantity) determining a reception is insufficient until charging all the capacitors in the receiving transistor gate is completed with the current controlled by on-resistance. This causes an operation delay of the receiving transistor itself. As a result, current of the power supply continues to flow during the time.
In this manner, a state of disabled smooth control of switching in the transistor gate circuit becomes prominent in a digital circuit of the GHz band due to rate controlling caused by a supply capacity of the power/ground.