The present invention relates to a semiconductor memory device having dynamic type RAM (DRAM) cells integrated and arranged, more specifically, to a semiconductor memory device capable of realizing a low power consumption, an enlarged operation margin and a high speed operation of a sense amplifier, a high reliability and a high current driving ability of a transistor by a transmission gate comprising a P-type MOS transistor.
Recently, according to the increase of the demand for portable apparatus, smaller appliances mounted with a semiconductor device are demanded. Therefore, the mounted semiconductor device is required to be highly integrated and to consume low power so as to prolong the time to be used with a battery.
Among semiconductor memory devices, since a memory cell has a comparatively simple structure in a semiconductor memory device such as DRAM, a high integration has been achieved. According to the high integration, patterns and elements have been even minute to deteriorate the pressure resistance, and the like so that a lower voltage is needed for the power source voltage for driving according to the scaling rule so as to ensure the reliability and a lower power consumption.
For example, in a 16 M bit DRAM, the power source voltage is being shifted from the conventional Vcc=5V to Vcc=3.3V. Further, in a 256 M bit DRAM, the power source voltage to be supplied is considered to become Vcc=2.5V.
Furthermore, as a minimum processing size, about 0.15 .mu.m is considered to be necessary. In a 1 G bit DRAM, a low power source voltage of about Vcc=1.8V is expected.
In these DRAMs, since a signal charge amount stored in a memory cell as data is minute, a highly sensitive bit line sense amplifier is needed for detecting, amplifying and reading it to the outside. Since the signal amount read out from the memory cell to be detected and amplified by the bit line sense amplifier is proportional to the power source voltage, when the power source voltage is scaled and lowered as mentioned above, the read signal amount decreases proportionally.
In general, as the bit line sense amplifier, a dynamic type differential amplifying circuit comprising an N-type sense amplifier where two sets of NMOS transistors (hereinafter NMOS is referred to as N-type) are connected by cross-coupling, and a P-type sense amplifier where two sets of PMOS transistors (hereinafter PMOS is referred to as P-type) are similarly connected by cross-coupling is used.
As shown in FIG. 28, as a precharge voltage of a bit line, which serves as the input terminal to the sense amplifier, the Vcc/2 precharge method, which is 1/2 of the power source voltage is used.
To explain the Vcc/2 precharge method simply, in a precharge cycle where the outside control signal RAS bar (hereinafter bar represents a reverse signal .sup.-) is at the "H" level, a bit line pair is precharged to Vcc/2. When the RAS bar signal shifts from the "H" to the "L" level to be in a state where the DRAM can read and write (active mode), the bit line precharge/equalize circuit is shut off so that the bit line precharged to be Vcc/2 becomes floating so that the word line WL selected by the external input address is driven, and data are read from the memory cell to the bit line.
The bit line sense amplifier is activated so that a minute signal read out to the bit line is detected and amplified.
More specifically, the "L" level side of the bit line pair is discharged to a ground voltage (Vss) by the above-mentioned N-type sense amplifier. On the other hand, the "H" level side of the bit line pair is charged to the power source voltage (Vcc) by the P-type sense amplifier. After completing the reading operation, the bit line is equalized and precharged to the Vcc/2 voltage again.
As a method for achieving a low power source voltage in a semiconductor memory device such as the above-mentioned DRAM, a method of reducing the bit line discharge current by having a smaller bit line voltage amplitude has been advocated conventionally.
However, in the case with a small amplitude for the bit line voltage amplitude, since the voltage difference between a gate and a source of the transistor comprising the flip flop type sense amplifier becomes small, a problem of deterioration of the operation speed of the sense amplifier is involved. In a semiconductor memory device having a memory capacity of the G bit level, since the power source voltage Vcc becomes extremely small as 1.8V or less, a voltage between the gate and the source necessary for the sense amplifier transistor operation, that is, a voltage not less than the threshold voltage of the sense amplifier transistor cannot be obtained between the gate and the source of the sense amplifier transistor to disable the sense operation, and thus it is problematic.
That is, in the case of a DRAM using the above-mentioned Vcc/2 precharge method, due to the lower source voltage, in the sense amplifier operation, the voltage between the gate and the source (Vcc/2) to be applied to the transistor comprising the sense amplifier itself inevitably lowers. As a consequence, there is a risk that the sense operation is drastically delayed or the sense operation cannot be implemented.
For example, in the case of the source voltage Vcc=1.8V, only Vcc=0.9V is applied between the gate and the source of the sense amplifier transistor. Actually, the voltage is lowered by the resistance of the common source wiring of the sense amplifier transistor, in particular, in the initial sensing time, the value can be further smaller.
On the other hand, the absolute value .vertline.Vth.vertline. of the threshold voltage of the sense amplifier transistor (it is a positive voltage in an N-type sense amplifier, but a negative voltage in a P-type sense amplifier) needs to be at least 0.3V to 0.5V in order to guarantee the threshold value irregularity and the cut off characteristic.
At the time of the initial sensing, the substantial .vertline.Vth.vertline. is further raised in combination with the back gate effect of the sense amplifier transistor. Therefore, the voltage between the gate and the source of the sense amplifier transistor and the threshold voltage are extremely close at the time of the initial sensing so that the initial sensing is drastically delayed. And thus a serious problem is involved in terms of the high speed operation of the DRAM.
Among the transistors used in the DRAM, a highest voltage (boosting voltage) is applied to the gate electrode of the memory cell transistor. This is because the "H" level needs to be written in the memory cell. The gate voltage needed therefor is represented by VBLH+Vth'. Herein VBLH represents the "H" level voltage, and Vth' represents the threshold voltage of the memory cell transistor where a negative voltage is applied to the back gate (substrate) of the memory cell transistor and the source voltage is VBLH.
In order to maximize the charge to be accumulated in the memory cell capacitor in general, VBLH is equal to the source voltage in the chip (Vdd).
In general, since the gate oxide film of the same thickness is used for all the transistors in the chip for the production cost reduction, a transistor, of which gate electrode is not applied with the boosting voltage inevitably uses the thick gate oxide film the same as the memory cell transistor. Therefore, the transistors used in the DRAM have a problem in that their performance such as the current driving ability is low compared with a transistor of a logical semiconductor, and the like.
In order to improve the transistor performance by having a thinner gate oxide film, the boosting voltage can be lowered to reduce the voltage to be applied to the gate oxide film of the memory cell transistor. However, in that case, the source voltage in the chip inevitably becomes low so that since only 1/2 Vdd can be applied between the gate and the source of the transistor comprising the sense amplifier at most in the general 1/2 Vdd precharge method, a problem is involved in that the sense amplifier cannot function.
In general, an equalize circuit is provided in a bit line pair, a data line pair, a sense amplifier driving line, and the like. For example, a bit line equalize circuit conventionally comprises only N-type transistors as shown in FIG. 29.
Since a large capacity is aimed at in a semiconductor memory these days, the redundancy technique for saving a defect memory cell generated in the production is in dispensable. However, even if it is saved, the defect cannot be eliminated.
For example, in the case a defect is generated in the short circuit between the bit line and the word line shown in FIG. 30, the memory cell is replaced (saved) by the redundancy technique. However, as mentioned above, since the defect remains as it is, at the time of operating the equalize circuit, through current flows in the route shown by the dot line in the figure, that is, VBL.fwdarw.PRCH.fwdarw.bit line.fwdarw.word line.fwdarw.row decoder.
When the through current is large, or a large number of short circuit defects are generated between the bit line and the word line, although the memory cell can be saved with the redundancy technique, since the current consumption becomes larger than the standard range, the chip becomes "defect".
In order to restrain the through current, a method of inserting a current limiting circuit between the precharge circuit and the precharge voltage supply line as shown in FIG. 31 is proposed. It is preferable that the current limiting circuit comprises a P-type transistor. At the time, problems are involved in that (1) the sense amplifying area is enlarged due to the necessity of the well separation with respect to the equalize/precharge circuit portion, and (2) a wiring is required for connecting the precharge circuit and the current limiting circuit.