1. Technical Field
This disclosure relates to electronic design automation (EDA). More specifically, this disclosure relates to creating and using a netlist abstraction.
2. Related Art
Advances in process technology and a practically unlimited appetite for consumer electronics have fueled a rapid increase in the size and complexity of integrated circuit (IC) designs. The performance of EDA tools is very important because it reduces the time to market for IC designs. Floorplanning is an important stage in an EDA design flow that involves determining locations for various objects (blocks, modules, circuit elements, etc.) in the IC layout. The quality of the floorplan can significantly impact the overall quality of the final IC layout.
Unfortunately, due to the rapid increase in the size and complexity of IC designs, conventional floorplanning tools can take a very long time to generate floorplans and/or generate poor quality floorplans.