It is known that electrical noise occurs in large scale integration (LSI) semiconductor circuits because of, for example, the presence of alpha (α) rays or neutron beams that cause the semiconductor circuits to malfunction. The a rays are emitted when radioisotopes included in the packages, wiring, etc. of the LSI semiconductor circuits have decayed, and the neutron beams originate from cosmic rays. The above malfunction is called a soft error in contrast to a hard error caused by a failure of hardware in a semiconductor circuit or the like. Accordingly, the soft error differs from the hard error in that the soft error causes transient malfunction in which the operation of the semiconductor circuit can be recovered while the hard error causes permanent destruction at a specific part in the circuit.
However, if the transient malfunction caused by the soft error is stored in a latch circuit making up the LSI semiconductor circuit, the malfunction caused by the soft error may cause a fixed error in the semiconductor circuit.
The increasing integration and decrease in size of LSI semiconductor circuits reduce the charge capacities of storage nodes of latch circuits included in the LSI semiconductor circuits to increase the probability of soft errors caused by occurrences of electrical noises becoming fixed errors. This is because the logical states of the storage nodes of the latch circuits are apt to reverse due to the electrical noise to increase the frequency of the malfunction states.
Under such situations, approaches to improve the soft-error resistance of logic LSI circuits including latch circuits have been proposed in recent years. For example, a method of determining the output by a decision of the majority of signals output from three or more latch circuits receiving the same data is proposed. However, with this method of avoiding errors, the number and area of circuits are increased because of the three or more latch circuits, a majority circuit, and so on to cause a reduction in the circuit performance. In addition, such a latch circuit in the related art can keep the normal output if a soft error occurs at a single node but cannot keep the normal output if soft errors continuously occur before new data is input. This is because the output is determined on the basis of the majority rule.
In order to reduce the effects of the above problems, a latch circuit including multiple circuit units and feedback paths through which and the multiple circuit units the input is fed back to the input is known. Complementary metal oxide semiconductor (CMOS) inverter circuits are generally used as the circuit units. In each of the CMOS inverter circuits, inverter circuits, particularly, P-channel transistor (PTr) and N-channel transistor (NTr) are coupled in series to each other.
Accordingly, it is desired to realize a latch circuit having an improved soft-error resistance.