The ultimate goal for a NVSRAM memory design is to work like a regular SRAM memory but with a non-volatilability to store the data after power is removed. This is called the Store operation. There are three kinds of Store operations and each time is performed to write SRAM cell's data into each corresponding Flash cell.
In a traditional 12T NVSRAM cell, the Write operation is a 2-step operation that uses Erase as a first step to either increase or decrease Flash cell Vt and is followed Program as a second step to conversely decrease and increase Flash cell's Vt to get the final desired Vts of Vt1 (≧2V) and Vt0 (≦−2V) on a single Flash cell. As a result, for traditional 12T NVSRAM cells a Recall operation is based on a method to detect a wide ΔVt (Vt1−Vt0=4V) between one paired flash transistors. But after a long P/E endurance cycle, the distance of the gap of ΔVt of Erase and Program Vt becomes smaller, thus the 12T NVSRAM cell operation becomes critical.
Therefore, an improved NVSRAM cell design with reduced cell size and proper write operation and recall operation are desired and become objectives of the present invention.