1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device that can have power consumption reduced.
2. Description of the Background Art
Semiconductor devices incorporated in various equipments have the scale of integration increased in order to reduce the size of the device and to integrate much more powerful logic. Increase in the integration density will result in a great number of elements operating inside to raise the heat. Therefore, reducing power consumption is an important factor. For example, in a DRAM (Dynamic Random Access Memory), there is a great demand for reducing the power consumption as a result of increase in the number of elements according to increase in the storage capacity.
A DRAM as a conventional semiconductor memory device will be described in detail hereinafter. A DRAM includes an intermediate potential generation circuit for generating precharge potential for a bit line, a timer circuit for carrying out a self refresh operation, and an internal high voltage circuit for generating high potential to be provided to a word line drive circuit.
An intermediate potential generation circuit will first be described. An example of an intermediate potential generation circuit is disclosed in IEEE Journal of Solid-State Circuit, Vol. SC-22, No. 5, October 1987, pp. 861-867. FIG. 25 is a circuit diagram showing a structure of a conventional intermediate potential generation circuit thereof.
Referring to FIG. 25, an intermediate potential generation circuit includes transistors Q101-Q103 which are n type MOSFETS, transistors Q104-Q106 which are p type MOSFETs, and resistors R101-R104.
FIG. 26 schematically shows a structure of the intermediate potential generation circuit of FIG. 25 on a p type substrate. Referring to FIG. 26, the intermediate potential generation circuit includes a p type substrate 111, an n type well 112, transistors Q11-Q106, and resistors R101-R104. In FIG. 26, components corresponding to those of FIG. 25 have the same reference characters denoted.
An operation of the intermediate potential generation circuit will be described hereinafter with reference to FIGS. 25 and 26.
The resistance of resistors R101 and R102 equal each other. Also, the resistance of resistors R103 and R104 equal each other. The resistance of resistors R101-R104 is several m.OMEGA., which is high resistance. Therefore, the current flowing in transistors Q101, Q102, Q104 and Q105 is reduced, and these transistors conduct lightly. Therefore, the gate-source potential of transistor Q101, Q102, Q104 and Q105 is equal to the threshold voltage of each transistor.
According to the above-described structure, the potential of nodes N1 and N3 is approximately V.sub.CC /2 (V.sub.CC is the power supply voltage). Therefore, the potential of node N2 becomes V.sub.CC /2+V.sub.TH101 (V.sub.TH101 is the threshold voltage of transistor Q101), and the potential of node N4 is approximately V.sub.CC /2-.vertline.V.sub.TH105 .vertline. (V.sub.TH105 is the threshold voltage of transistor Q105). When the potential of an output signal V.sub.sg is lower than V.sub.CC /2+V.sub.TH101 -V.sub.TH103 (V.sub.TH103 is the threshold voltage of transistor Q103), transistor Q103 conducts, whereby the potential of output signal V.sub.sg rises. When the potential of output signal V.sub.sg is higher than V.sub.CC /2-.vertline.V.sub.TH105 .vertline.+.vertline.V.sub.TH106 .vertline. (V.sub.TH106 is the threshold voltage of transistor Q106), transistor Q106 conducts, whereby the potential of output signal V.sub.sg falls. By the above-described operation, the potential of output signal V.sub.sg becomes approximately V.sub.CC /2.
A timer circuit for a self refresh operation will be described hereinafter. A refresh operation must be carried out periodically since a DRAM is a volatile memory. Lengthening the period of a refresh operation will reduce power consumption thereof, to allow reduction of power consumption in the device. In a conventional timer circuit, a refresh operation is carried out when the potential held in a memory cell becomes lower than a predetermined level. An example of such a timer circuit is disclosed in IEEE Journal of Solid-State Circuits, Vol. 26, No. 11, November 1991, pp. 1556-1562. FIG. 27 shows a structure of this conventional timer circuit.
Referring to FIG. 27, a timer circuit includes a differential amplifier 121, an S-R flipflop 122, a delay circuit 123, a transistor Q111 which is an n type MOSFET, a capacitor 124 of a memory cell, and an n type diffusion layer 125.
FIGS. 28A(1) to 28B(B) are timing chart showing the operation of the timer circuit of FIG. 27.
An operation of the timer circuit will be described hereinafter with reference to FIGS. 27 and 28A(1) to 28B(B). When the potential V.sub.N in capacitor 124 becomes lower than a reference potential V.sub.REF at time t.sub.1, S-R flipflop 122 is set to render the level of an output signal .phi..sub.E to a H level (logical high). Output signal .phi..sub.E of S-R flipflop 122 is delayed for a predetermined time, and then applied to a reset terminal R of S-R flipflop 122. As a result, a reset signal R attains a H level. This causes S-R flipflop 122 to be reset, whereby output signal .phi..sub.E attains a L level (logical low). A refresh operation is carried while output signal .phi..sub.E attains a H level, whereby transistor Q111 attains a conductive state, and the potential of capacitor 124 of a memory cell is maintained at V.sub.CC. Then, when output signal .phi..sub.E attains a L level, transistor Q111 is rendered non-conductive, whereby the holding voltage V.sub.N of capacitor 124 is gradually reduced by leakage current. When holding voltage V.sub.N of capacitor 124 becomes lower than reference voltage V.sub.REF, an operation similar to that of the above-described operation is repeated. Thus, a refresh operation is carried out at a predetermined period.
An internal high voltage circuit will be described. FIG. 29 is a block diagram showing a structure of a conventional internal high voltage circuit. Referring to FIG. 29, an internal high voltage circuit includes a first detector 132, a second detector 132, a third detector 133, a first oscillator 134, a second oscillator 135, a small pump 136, a large pump 137, a RAS pump 138, and an AND gate G101 and an inverter G102.
When high voltage V.sub.PP supplied to a word line driver 139 becomes lower than a predetermined potential, first detector 131 provides an output signal .phi..sub.E1 of a H level to first oscillator 134. First oscillator 134 oscillates while output signal .phi..sub.E1, attains a H level, and provides an oscillation signal to small pump 136. Small pump 136 responds to this oscillation signal to provide high voltage V.sub.PP to word line driver 139 at a standby state.
When the high voltage supplied to word line driver 139 becomes lower than a predetermined potential, second detector 132 provides an output signal .phi..sub.E2 of H level to second oscillator 135. Second oscillator 135 oscillates when output signal .phi..sub.E2 attains a H level, and provides an oscillation signal to large pump 137. Large pump 137 responds to this oscillation signal to rapidly increase high voltage V.sub.PP supplied to word line driver 139.
When high voltage V.sub.PP supplied to word line driver 139 becomes lower than a predetermined potential, third detector 133 provides an output signal .phi..sub.E3 of a H level to AND gate G101. AND gate G101 takes the logical product of output signal .phi..sub.E3 and an inverted signal of a row address strobe signal /RAS ("/" implies a low-active signal) to provide an output signal to RAS pump 138. AND gate G101 provides an output signal when row address strobe signal /RAS attains a L level, whereby the semiconductor device operates to raise the word line to high voltage V.sub.PP.
The first detector shown in FIG. 29 will be described with reference to FIG. 30 showing a circuit diagram thereof.
Referring to FIG. 30, a first detector includes transistors Q121-Q124 which are p type MOSFETs, and transistors Q125 and Q126 which are n type MOSFETs.
High voltage V.sub.PP provided to the first detector is reduced by a threshold voltage .sub.TH of each transistor, i.e., by 3V.sup.TH, by transistors Q121-Q123. Therefore, an output signal .phi..sub.E1 of a H level is output when high voltage V.sub.PP becomes lower than V.sub.CC +3V.sub.TH.
The second detector of FIG. 29 will be described hereinafter with reference to FIG. 31 showing a circuit diagram thereof.
Referring to FIG. 31, a second detector includes transistors Q131-Q133 which are p type MOSFETs, and transistors Q134 and Q135 which are n type MOSFETs.
High voltage V.sub.PP provided to the second detector is reduced by a threshold voltage V.sub.TH of each transistor, i.e. 2V.sup.TH, by transistors Q131 and Q132. Therefore, the second detector provides an output signal .phi..sub.E2 of a H level when high voltage V.sub.PP becomes lower than V.sub.CC +2V.sub.TH. The third detector of FIG. 29 has a structure similar to that of the second detector of FIG. 31, and also operates in a similar manner thereof.
The first oscillator of FIG. 29 will be described hereinafter with reference to FIG. 32 showing a circuit diagram thereof.
Referring to FIG. 32, a first oscillator includes transistors Q141-Q148 which are p type MOSFETs, and transistors Q149-Q156 which are n type MOSFETs. C101-C103 shown in FIG. 20 are the parasitic capacitance of each portion.
Because transistor Q141 has a long channel length, current flowing in transistor Q149 is limited to a current value of I.sub.1. Transistor Q149 and transistors Q150, Q152, Q154 and Q156 form a current mirror, so that current flowing through transistors Q143, Q145, Q147, Q152, Q154 and Q156 is limited to the value of I.sub.1. Therefore, the delay time of each inverter formed by each of these transistors becomes 3C/I.sub.1 where each capacitance of parasitic capacitances C101-C103 is C.
When V.sub.CC /2+V.sub.TH101 -V.sub.TH103 &gt;V.sub.sg =V.sub.CC /2, and V.sub.CC /2-.vertline.V.sub.TH105 .vertline.+.vertline.V.sub.TH106 .vertline.&lt;V.sub.sg =V.sub.CC /2, i.e. V.sub.TH101 &gt;V.sub.H103, and .vertline.V.sub.TH105 .vertline.&gt;.vertline.V.sub.TH106 .vertline. in the intermediate potential generation circuit of FIG. 25, a through current flows in transistors Q103 and Q106 at the time of standby since transistors Q103 and Q106 both conduct when the potential of output signal V.sub.sg is stable at V.sub.CC /2. There was a problem that the power consumption of the device was increased due to this through current.
In the timer circuit of FIG. 27, the period of a refresh operation is T.sub.1, at low temperature as shown in FIG. 28(a), and is T.sub.2 at high temperature as shown in FIG. 28(b) because leakage current of capacitor 124 increases at high temperature.
The timer circuit shown in FIG. 27 had problems set forth in the following. A phenomenon called soft error is seen in a DRAM. More specifically, .alpha. particles emitted from the package or the like cause the generated electrons to be captured in an n type diffusion layer 125 of a memory cell, whereby information in the memory cell is destroyed. Therefore, soft error easily occurs when the holding voltage V.sub.N becomes not higher than the lowest holding voltage V.sub.REF required for proper operation of a readout circuit of a memory cell by a predetermined value of .DELTA.V. As a result, when the level of holding voltage V.sub.REF is equal at both the high and low temperature, the time period having a high probability of generating soft error is d.sub.1, and d.sub.2 at a low temperature and a high temperature, respectively, as shown in FIGS. 28A and 28B. Therefore, there was a problem that the possibility of soft error occurrence is increased at low temperature.
In the first and second detectors shown in FIGS. 30 and 31, a through current is conducted to increase power consumption since all transistors Q124, Q126, Q133 and Q135 become conductive when the level of output signals .phi..sup.E1 and .phi..sub.E2 change.
In the third detector shown in FIG. 31, the time required for pulling the potential of the node between transistorS Q132 and Q134 from a H level to a L level is several .mu.s. An operation of a DRAM occurs at the minimum of every 90 ns, for example. Therefore, a word line is driven several ten times during the transition of the third director from an off state to an on state, resulting in reduction of the level of high voltage V.sub.PP of word line driver 139. FIGS. 33(a) to 33(b) are diagrams for describing the change in the level of high voltage V.sub.PP, with respect to output signal .phi..sub.E3 of the third director. It is appreciated from FIG. 33(a) to 33(b) that the level of high voltage V.sub.PP is gradually reduced according to each transition of row address strobe signal /RAS when output signal .phi..sub.E3 attains a L level. Therefore, a conventional third detector is set so that sufficient current is conducted to transistor Q134 in order to rapidly pull down the potential of the node between transistors Q132 and Q134 rapidly to a L level from a H level. Thus, there was a problem that power consumption is increased during standby.
In the first oscillator of FIG. 32, the delay time of 3C/I.sub.1 is reduced due to increase of current I.sub.1 flowing in transistor Q141 in response to increase of power supply potential V.sub.CC. This causes the oscillation frequency of the first oscillator to be increased to shorten the operation cycle. Thus, there was a problem that power consumption of the device is increased.