The present invention relates to a semiconductor device and a method of manufacturing the same, more specifically, a semiconductor device comprising a nonvolatile memory of the stacked gate structure and a transistor of the single-layer gate structure, and a method of manufacturing the semiconductor device.
The logic semiconductor device combined with a nonvolatile semiconductor memory forms product fields, as of CPLD (Complex Programmable Logic Device) and FPGA (Field Programmable Gate Array), and because of their characteristic of programmability, so far have formed large markets because of their characteristic, programmability.
The logic semiconductor device combined with a nonvolatile memory has, in addition to flash memory cells, a high-voltage transistors for controlling the flash memory and low-voltage transistors of high-performance logic circuit integrated on the same semiconductor chip. The flash memory cells have gate electrode of the stacked structure of a floating gate and a control gate laid one on the other which is different from the single-layer structure of the high-voltage transistors and the low-voltage transistors. Accordingly, the process of manufacturing the logic semiconductor device combined with the nonvolatile memory requires the process specialized in forming the nonvolatile memory transistors of the stacked gate structure without changing characteristics of the peripheral circuits, especially the logic transistors.
In the usual combined process, the floating gates of the nonvolatile memory transistors are formed of the first-level conductive film (the first conductive film), and the control gates of the nonvolatile memory transistors and the gate electrodes of the peripheral transistors are formed of the second-level conductive film (the second conductive film). Then, the peripheral transistors are formed after the nonvolatile memory transistors have been formed, so as to prevent the process of manufacturing the nonvolatile memory transistors from influencing characteristics of the logic transistors. In terms of the process of forming the gate electrodes, after the second conductive film in the memory cell region have been patterned to form the control gates, the second conductive film in the peripheral circuit region is patterned to form the gate electrodes of the peripheral transistors.
The related arts are described in, e.g., Reference 1 (Japanese published unexamined patent application No. Hei 10-209390).
However, the inventors of the present application have examined the process of fabricating the logic semiconductor device combined with the nonvolatile memory and found that the process causes the disadvantage that the second conductive film in the memory cell region is etched when the second conductive film is patterned to form the gate electrodes of the peripheral transistors.