1. Field of the Invention
The present invention relates to a chip-packaging structure, and more particularly to a stacked chip-packaging structure.
2. Description of the Related Art
With the progress of highly developed integrated circuit (IC) technologies, integration of internal circuits of IC chips steadily increases. As a result, number of transistors held in internal circuits of IC chips increases relatively, and sectional area of wires in the internal circuits of IC chips reduces accordingly. As the packaging technologies being continuously improved, various chip-packaging structures have been developed, including chip-packaging structures of ball grid array (BGA) structure and of multi-chip packaging module. Wherein, the BGA structure has advantages of high pin count and high reliability, while the multi-chip packaging module has shorter transfer route and better electronic properties. Such technical features make it possible to further reduce the space that the chip-packaging structure occupies, and therefore these packaging technologies could be widely applied in production of electronic devices.
FIG. 1 is a schematic view of a conventional chip-packaging structure. The chip-packaging structure 100, through wire bonding for example, consists essentially of a substrate 110, a chip 120, a plurality of wires 130, a molding compound 140, and a plurality of solder balls 150. The substrate 110 is made of, for example, ceramic, glass, or plastics. The substrate 110 contains alternately stacked multiple conducting layers (not shown) and multiple insulating layers (not shown), while two adjacent conducting layers are separated by an insulating layer, and the conducting layers are electrically connected one another through conductive via or plating through hole. In addition, the top surface 110a and the bottom surface 110b of the substrate 110 have respectively a plurality of upper contacts 112 and a plurality of lower contacts 114, while the upper contact 112 is electrically connected to the lower contact 114 through the conducting layers in the substrate 110. Moreover, a chip 120 is disposed on the top surface 110a of the substrate 110, while the chip 120 has an active surface 122, and a plurality of bonding pads 124 (usually aluminum pads) are disposed on the periphery of the active surface 122. The bonding pads 124 are connected, through wire bonding by the wires 130, to the contacts 112 on the substrate 110, wherein the wires 130 are made of gold, for example.
The wires 130, the chip 120, and the upper contacts 112 on the substrate 110 are enclosed by the molding compound 140 for the protection of the chip 120 and the wires 130. The solder balls 150, made of Sn/Pb alloy for example, are disposed on the lower contacts 114. Wherein, the solder balls 150 serve as contact points of the chip-packaging structure 110 to contact with external electronic devices (e.g., printed circuits or motherboards). The solder balls 150 are disposed in a surface array distribution on the bottom surface 110b of the substrate 110, so that the chip-packaging structure 100 becomes a BGA packaging structure with high pin count.
FIG. 2 shows a conventional multi-chip packaging module. In the packaging structure, a plurality of chip-packaging units, 200(a) and (b) (only two units are shown), are disposed on the same carrier 210, wherein the chip-packaging units 200 are of a BGA type for example, and are sequentially disposed on the carrier 210. Therefore, the chip-packaging units 200(a) and (b) can be electrically connected by internal wires (not shown) of the carrier 210, so as to construct a packaging structure of multi-chip module, such as a dynamic random access memory (DRAM) module.
It is worthy of notice that, when the number of the chip-packaging units increases, the requisite supporting area on the carrier increase accordingly, which makes, for example, the assembled multi-chip packaging module to have a long bar or a flat plate structure. Therefore, it is a challenge to develop appropriate chip-packaging technologies to create certain chip-packaging structures containing more chip-packaging to meet the needs for fabricating a chip-packaging structure with high pin count and a structure of multi-chip packaging module.