The present invention relates in general to semiconductor memories and in particular to a non-volatile memory array architecture and a method of operation of the same.
The most common variety of non-volatile memories, such as EPROM, flash memory, and some EEPROMs, today employs channel hot electron (CHE) for programming and negative gated Fowler-Nordheim (FN) tunneling for erase. FIG. 1 shows a conventional n-channel stack gate flash memory cell 100. Memory cell 100 includes N+ source 102 and drain 103 regions spaced apart in a P-type silicon substrate 101 to form a channel region 104 therebetween. A floating gate 105 of polycrystalline silicon material is laid on top of a tunneling dielectric 106, which extends over the channel region 104 and overlaps the source 102 and drain 103 regions. Stacked on top of, but insulated from, floating gate 105 is a gate 107 of polycrystalline material. Junction 102 is made deeper than normal in order to minimize the adverse reliability effects of tunnel oxide hot hole trapping during erase operation.
Cell 100 is programmed, i.e., its threshold voltage is raised higher, by applying 10V to gate 107, 5V to drain 103, and grounding source 102. The memory cell is thus strongly turned on, and the cell""s threshold voltage is raised due to injection of hot electrons from the channel region near the drain 103 to floating gate 106, as indicated by the arrow labeled as xe2x80x9cPxe2x80x9d. Cell 100 is erased, i.e., its threshold voltage is lowered, by applying xe2x88x9210V to gate 107, 5V to source 102, and floating drain 103. The cell""s threshold voltage is thus lowered due to tunneling of electrons from the floating gate 105 to source 102, as indicated by the arrow labeled as xe2x80x9cExe2x80x9d.
Conventional memory arrays include a matrix of memory cells arranged along rows and columns. The gates of the cells along each row are connected together forming a wordline. In one array architecture, the cells along each column are grouped in a number of segments, and the drains of the cells in each segment are coupled to a corresponding segment line. The segment lines along each column are coupled to a corresponding data line through one or more segment select transistors. The segmentation of the cells in each column helps reduce the bitline capacitance to that of the metal bitline plus the small capacitance of a selected segment line. Performance of the memory is thus improved.
During programming or read operations, one or more bitlines are selected through a column select circuit for transferring data to or from the selected memory cells. The column select circuit typically has a multiplexer configuration in that a group of serially-connected NMOS pass transistors controlled by column decoding signals selectively couple one or more bitlines to either sense amplifiers (read operation) or data-in buffers (programming operation). Depending on the total number of bitlines in the array and the number of bitlines to be selected, two or more levels of column selection need to be implemented in the column select circuit. The number of levels of column selection correspond to the number of serially-connected pass transistors that couple the selected bitlines to the sense amplifier or data-in buffer. For example, if two levels of column selection are implemented, a selected bitline will be coupled to the sense amplifier or data-in buffer through two serially-connected column select transistors.
The sizes of the column select transistors and the segment select transistors need to be made large enough so that the required cell programming voltage and current can be provided to the selected cell. Because of the programming biasing conditions, the serially connected segment select transistor and column select transistors result in a rather resistive path, which can be compensated for by increasing the transistor sizes. This can be more clearly understood with the help of FIG. 2.
FIG. 2 shows a portion 201 of an array along with a portion 202 of a column select circuit. The array portion 201 includes a memory cell 100 with its gate coupled to wordline WL and its drain coupled to a segment line S0. The source of cell 100 is shown as being connected to ground for simplicity, although, the source is typically connected to a source line which may be decoded to provide ground only to selected memory cells. A segment select transistor MS is coupled between segment line S0 and bitline BL, with its gate coupled to segment select signal SS. Bit line BL is coupled to the data-in block 204 through two serially connected column select transistors MYa and MYb. Column select transistors MYa and MYb are controlled by column decode signals Ya and Yb, respectively. As indicated in FIG. 2, the deeper source junction 102 of the FIG. 1 cell is connected to ground, while the shallower drain junction 103 is connected to segment line S0.
As can be seen, cell 100, and transistors MS, MYa, and MYb are serially-connected to data-in block 204. To program cell 100, 10V is supplied to wordline WL, while 5V needs to be supplied to its drain, i.e., to segment line S0. To supply 5V to segment line S0, data-in block 204 outputs 5V on line 206, and column select signals Ya and Yb as well as segment select signal SS are raised to 10V. Thus, the 5V on line 206 is transferred through transistors MYa, MYb, and MS to segment line S0. The drive capability of each transistor MYa, MYb, MS is, to a first order approximation, equal to its Vgsxe2x88x92Vt, wherein Vgs represents the transistor gate to source voltage, and Vt represents the transistor threshold voltage. For each of transistors MYa, MYb, MS, Vgs=Vgxe2x88x92Vs=10Vxe2x88x925V=5V, and the Vt is approximately 2V because of the back bias effect. Thus, for each transistor MYa, MYb, MS, Vgsxe2x88x92Vt=5Vxe2x88x922V=3V. Because of the small Vgsxe2x88x92Vt of 3V, the sizes of these transistors need to be made large so that sufficient current can be supplied to the cell during programming.
In higher density memories, where the number of levels in the column select circuit increases, the sizes of the column select transistors increase proportionally. This increases the die size. More importantly, as higher performance is required of memory devices, the need for further segmentation of the bitlines increases, resulting in a larger number of segment select transistors in the array. The adverse impact of a larger size segment select transistor and a larger number of segment select transistors on the overall die size can be rather substantial.
FIG. 3 illustrates another draw back of conventional memory arrays, namely, the non-uniform programming characteristic of memory cells in the array due to the source resistance. A portion 300 of a memory array is shown as including 16 memory cells 100-0 to 100-15 along a row. The drain of each cell is coupled to a corresponding segment line S0 to S15, and the gates of the cells are connected to a wordline WL. The sources of the cells are connected together and to metal source lines SLn and SLn+1 through a diffusion strip 310. Resistors R0 to R16 depict the resistance associated with the diffusion strip 310. The cell configuration of FIG. 3 is repeated as many times as required to form the entire array.
For the above-indicated cell biasing during programming, the cell programming performance is dependent primarily upon the gate to source voltage Vgs of the cell. For example, with the wordline WL at 10V, and the source fully grounded, the cell Vgs equals a full 10V. However, because of the presence of the resistive diffusion strip 310, depending on the location of the cells along the diffusion strip 310, the effective Vgs of the cells vary. For example, of the 16 cells, the cells closest to the center of the diffusion strip will have the maximum source resistance, and thus poorer programming characteristics, while the cells closest to the ends of the diffusion strip 310 have minimum source resistance, and thus the best programming characteristics. This leads to the undesirable non-uniform programming characteristics of the cells across the array.
Thus, an array architecture and method of operation are needed whereby the adverse effect of column select and segment select transistor sizes on the die size can be minimized, while a more uniform programming characteristic across the array cells can be obtained.
In accordance with an embodiment of the present invention, an array of non-volatile memory cells are arranged along rows and columns. Each memory cell has a drain region spaced apart from a source region to form a channel region therebetween. The drain region has a greater depth than the source region. Each memory cell further has a stack of floating gate and select gate extending over the channel region, the select gate of the cells along each row being connected together to form a wordline. Each of a plurality of data lines is coupled to the drain region of at least a portion of a column of cells. Each of a plurality of source lines is coupled to a source region of a plurality of cells along at least a portion of a row of cells, wherein injection of hot electrons from a portion of the channel region near the source region to the floating gate is induced in a selected memory cell in the array by applying a first voltage to a selected data line to which the drain of the selected memory cell is coupled, a second positive voltage to a word line to which the selected gate of the selected memory cell is coupled, and a third positive voltage to a source line to which the source of the selected memory cell is coupled, wherein the injection of hot electrons increases a threshold voltage of the selected cell.
In one embodiment, the first voltage is in the range of xe2x88x920.5 to +0.5V, the second positive voltage is in the range of 8V to 12V, and the third positive voltage is in the range of 4.0V to 6.0V.
In accordance with another embodiment of the present invention, a method of operating a memory array is provided. The memory array has a plurality of memory cells arranged along rows and columns. Each memory cell has a source region spaced apart from a drain region to form a channel region therebetween, and a floating gate and select gate stack extending over the channel region. The select gates of the memory cells along each row are coupled together to form a plurality of wordlines. Each of a plurality of data lines is coupled to a drain region of each of a plurality of non-volatile memory cells along a column. Each of a plurality of source lines is coupled to a source region of each of a plurality of memory cells along a row. The method of operation of the memory array is as follows. A first voltage is applied to a selected data line coupled to the selected cell. A second positive voltage is applied to a selected word line coupled to the selected cell. A third positive voltage is applied to a source line coupled to the selected cell, wherein upon applying the first voltage and the second and third positive voltages an injection of hot electrons from a portion of the selected cell""s channel region substantially near the source region to the selected cell""s floating gate is induced whereby a threshold voltage of the selected memory cell is increased.
In one embodiment, the first voltage is in the range of xe2x88x920.5 to +0.5V, the second positive voltage is in the range of 8V to 12V, and the third positive voltage is in the range of 4.0V to 6.0V.
Other advantages and features of the present invention will be apparent from the accompanying drawings and the description thereof.