1. Field of the Invention
This invention relates to electronic circuits and, more particularly, to clock generation and timing circuits.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Phase locked loops (PLLs) are commonly used for data and telecommunications, frequency synthesis, clock recovery, and similar applications. In some cases, a PLL may be used in the I/O interfaces of digital integrated circuits to hide clock distribution delays and to improve overall system timing. In other cases, a PLL may be used as a clock multiplier for downstream circuit components. In one example application, an input clock of 10 Mhz can be multiplied by the PLL to yield a 1000 Mhz output signal, which may then be used for clocking internal circuit components. Ideally, this input (or source) clock multiplication could result in an output that is in perfect phase alignment with the input clock. However, in practice this is often not the case.
A typical PLL device 100 is shown in FIG. 1 as including an optional reference divider (div M) 120, a phase frequency detector (PFD) 130, a charge pump 140, a low pass filter 150, a voltage controlled oscillator (VCO) 160, and an optional frequency divider (div N) 170.
During operation, PLL circuit 100 receives a reference clock signal (FREF) from an external source (e.g., a crystal oscillator) 110. The phase frequency detector compares the reference signal (FREF) to a feedback signal (FVCO) generated by components within the PLL circuit. More specifically, PFD 130 detects differences in frequency and/or phase between the reference and feedback clock signals, and generates compensating “up” and “down” signals in response thereto. The particular control signals generated depend on whether the feedback clock signal is lagging or leading the reference clock signal in frequency or phase. The up/down control signals are passed through charge pump 140 and filter 150 to integrate the control signals into a control voltage, which is sent to the VCO. The voltage-controlled oscillator converts the voltage information into one or more output frequencies (FVCO). One of these output frequencies may then be sent back to the PFD via a feedback loop.
In some cases, frequency divider 170 and reference divider 120 may be included for adjusting the frequencies of the feedback and reference clock signals, respectively. For example, frequency divider 170 may be used for dividing the frequency of a VCO output signal (FOUT) to produce a divided down feedback signal (FOUT/N), while reference divider 120 is used for dividing the frequency of the external clocking signal to produce a divided down reference signal (FREF/M), which is similar or dissimilar to the divided down feedback signal. In such cases, PLL 100 may function as a clock or frequency multiplier. However, dividers 120 and/or 170 may not be included in all cases.
In conventional PLL devices, high-performance inductor-capacitor (LC) VCOs are often used to create low-noise, high-speed PLLs. For example, LC-type oscillators are often used in PLL designs tailored for wireless and low power applications, as well as other applications requiring precise timing. Unfortunately, LC-type oscillators have a tight frequency range, which is sensitive to variations in process, voltage and temperature (PVT). In some cases, variations in PVT may cause the VCO frequency range to shift outside of a target range, thereby limiting the usable frequency range of the PLL device. For this reason, various solutions have been proposed for extending the usable frequency range of a PLL device employing an LC-type oscillator.
One solution to the above-mentioned problem is to create or use a VCO with a wide frequency range. For example, a wider frequency range can be obtained by increasing the gain of an LC-type oscillator, or by using a completely different oscillator (e.g., a ring oscillator) with an inherently wider frequency range. Unfortunately, large VCO gains are undesirable because of their sensitivity to noise. In addition, although a wide frequency range may be easily obtained when the ring oscillator is employed as a VCO, the ring oscillator is not without limitations and usually demonstrates poorer phase-noise performance than the LC-type oscillator.
Another solution is to use multiple LC-type oscillators within the PLL device. For example, a first VCO may be used for generating frequencies within a 2-2.45 GHz range, while a second VCO is used for generating frequencies within a 2.45-2.5 Ghz range. Additional or alternative VCOs may be used for generating frequencies within other ranges. Unfortunately, the second solution may be undesirable in many applications, due to the relatively large die area consumed by the additional VCO(s).
In yet another solution, an LC-type VCO may be calibrated during the manufacturing test process to shift the VCO operating frequency into a desired range. For example, test circuitry may be used for measuring the max VCO frequency, measuring the min VCO frequency and calculating an average of the two. The test circuitry may then be used for adjusting the programmable bits supplied the LC-type VCO until the measured value(s) equal a set of target value(s). Unfortunately, the third conventional solution is too slow (i.e., adds additional test time) and does not compensate for the environmental conditions that the device will actually be used in (i.e., the method does not account for power supply and temperature variations, only for process variations).
In yet another solution, an LC-type VCO may be calibrated during operation of the PLL device to shift the VCO operating frequency into a desired range. One such solution is described in a paper entitled “A Delta-Sigma Fractional-N Synthesizer using a Wide-Band Integrated VCO and a Fast AFC Technique for GSM/GPRS/WCDMA Applications,” and published in the July 2004 issue of IEEE Journal of Solid-State Circuits (JSSCC), vol. 39, no. 7, pgs. 1164-1169. In this solution, a pair of switches are used for disconnecting the low pass filter from the VCO (i.e., opening the loop) to enter a VCO calibration mode. To achieve calibration, digital frequency counters are used for counting the number of reference and feedback clock pulses supplied thereto. A comparator is then used to determine the proper VCO frequency by comparing the number of feedback pulses to the number of reference pulses, while a state machine is used for adjusting the programmable bits supplied to the VCO. Unfortunately, the frequency counters and state machine used in the fourth solution are too slow for many high-speed applications (e.g., it may take about 650 clock cycles to complete the calibration using the method describe above). In addition, the switches used for disconnecting the low pass filter from the VCO introduce a series resistance into the PLL signal path. This is undesirable because it tends to alter the behavior of the filter.
Therefore, a need remains for an improved calibration solution that may be used for extending the usable frequency range of a PLL device. Preferably, the improved solution would allow frequency calibration and compensation of a narrow band PLL over a wide range of actual environmental conditions, including process, voltage, and temperature. Even more preferably, the improved solution would provide a circuit and method for calibrating an LC-type oscillator during operation of a PLL device, wherein said calibration is performed without opening the loop and with much greater speed than possible with conventional solutions.