Exemplary embodiments of the present invention relate to a system including a slave device and a master device.
Packaging technology of semiconductor elements has been continuously developed according to a demand for miniaturization and high capacity. Recently, a variety of technologies for a stacked semiconductor package capable of satisfying mounting efficiency as well as the miniaturization and high capacity are being developed.
The stacked semiconductor package may be fabricated by the following methods. First, individual semiconductor chips may be stacked, and then packaged at once. Second, individual semiconductor packages may be stacked. The individual semiconductor chips of the stacked semiconductor package are electrically coupled through metallic wires or through silicon vias (TSV).
However, in the conventional stacked semiconductor package using metallic wires, since the electrical signal exchange is performed through the metallic wires, the speed is low. Furthermore, since a large number of wires are used, electrical characteristic degradation may occur. Furthermore, since an additional area for forming the metallic wires is required in a substrate, the size of the package may increase. Furthermore, since a cap for wire bonding is required between the semiconductor chips, the height of the package may increase.
Recently, a stacked semiconductor package using a TSV has been proposed. In general, the stacked semiconductor package is fabricated by the following method. First, a via hole is formed in a semiconductor chip so as to pass through the semiconductor chip, and a through electrode called a TSV is formed by filling the via hole with a conductive material. Then, an upper semiconductor chip and a lower semiconductor chip are electrically coupled through the through electrode.
FIG. 1A is a block diagram illustrating a coupling state between a master device and slave devices. FIG. 1B is a diagram illustrating a state in which the slave devices are stacked and coupled to the master device.
The master device 100 refers to a device which controls the slave devices, and the slave devices DEV(1), DEV(2), . . . , DEV(i), DEV(j), and DEV(k) refer to devices which are controlled by the master device 100. An example of the master device 100 and the slave devices DEV(1), DEV(2), . . . , DEV(i), DEV(j), and DEV(k) is a memory controller and memory devices such as DRAMs and flash memories. FIGS. 1A and 1B illustrate a memory controller as the master device 100 and memory devices as the slave devices DEV(1), DEV(2), . . . , DEV(i), DEV(j), and DEV(k).
Referring to FIG. 1B, the respective slave devices DEV(1), DEV(2), . . . , DEV(i), DEV(j), and DEV(k) are stacked and formed, and are coupled to the master device 100 through an interposer 110. Pillars formed through the stacked slave devices DEV(1), DEV(2), . . . , DEV(i), DEV(j), and DEV(k) include TSVs through which signals (data) are transmitted, that is, which form channels. The entire system illustrated in FIG. 1B may be implemented in one semiconductor chip package, and only the stacked slave devices may be implemented in one semiconductor chip package.
FIG. 2 is a diagram illustrating the channels formed as the TSVs between the master device 100 and the slave devices DEV(i), DEV(j), and DEV(k) and RLC (resistance, inductance, and capacitance) components of the channels.
Referring to FIG. 2, the respective channels have the RLC components. Therefore, the signals (data) transmitted through the channels may be delayed. The delay increases in proportional to the distance between the devices. That is, a flight time of a signal between the master device 100 and the slave device DEV(i) is longer than a flight time of a signal between the master device 100 and the slave device DEV(k). For reference, in FIG. 2, Tx represents transmission terminals provided in the master device 100 and the slave devices DEV(i), DEV(j), and DEV(k), and Rx represents reception terminals provided in the master device 100 and the slave devices DEV(i), DEV(j), and DEV(k).
FIG. 3 is a diagram showing timing variations in signal transmission between the master device 100 and the slave devices DEV(i), DEV(j), and DEV(k), which occur depending on differences in channel length.
In FIG. 3, CMD represents a command applied from the master device 100 to the slave devices DEV(i), DEV(j), and DEV(k), D represents data which the master device 100 transfers to the slave devices DEV(i), DEV(j), and DEV(k), and Q represents data which the slave devices DEV(i), DEV(j), and DEV(k) transfer to the master device 100. The data Q are generated when the slave devices DEV(i), DEV(j), and DEV(k) processes the data D according to the command D.
Referring to FIG. 3, the command and the data D transferred from the master device 100 to the slave device DEV(i) have a flight time of X(i). When the slave device DEV(i) transfers the data Q to the master device 100 in response to the command CMD and the data D, the data Q has a flight time of X(i). Therefore, while the data are exchanged between the master device 100 and the slave device DEV(i), the flight time is 2*X(i). Similarly, a flight time between the master device 100 and the slave device DEV(j) is 2*X(j), and a flight time between the master device 100 and the slave device DEV(k) is 2*X(k).
That is, the flight time of the signal may differ depending on with which device the master device 100 communicates among the slave devices DEV(i), DEV(j), and DEV(k), and the timing of transmission or reception of a specific signal (data) may be significantly varied.