1. Field of the Invention
The present invention relates to a method for the selective growth of an epitaxial layer on source/drain areas.
2. Description of the Related Technology
In semiconductor fabrication a hard mask (HM) is applied in order to protect part of the wafer from etching the other part of the wafer. The hardmask usually has to be removed afterwards. Typically an etch resistant material is employed for the hardmask.
When considering a process flow for fabricating a CMOS FET transistor, a gate stack is formed, which is capped with a silicon oxide (2) and with spacers (4)(see FIG. 1(A)). Spacers (4) around the gate are typically in Si nitride. The full encapsulation is of vital importance, as it protects the gate during epitaxial growth. Further processing steps are depicted in FIG. 1. In a first step either a single layer hardmask (5) is deposited (FIG. 1(B.1)) or a hardmask stack, which cannot be etched during source/drain etching (in FIG. 1(B.2) a two-layer stack (5, 6) is shown). Next a first area is opened up comprising a source and drain (S/D) and a gate stack (FIG. 1(C)). The hardmask (5) is etched selectively towards Si oxide (used to cap the gate) and Si nitride (used for the spacers) of the first area and also selectively to the hardmask on top of a second area of the substrate (1). If the hardmask etching is not performed in a sufficiently selective way, an accurate control of the lost amount of Si oxide/Si nitride is required. In the following step (FIG. 1(D)) a source/drain (S/D) silicon etch is performed selectively towards Si oxide and Si nitride. The etch rate depends on the amount of exposed Si. A part of the hardmask (5) is consumed by a break through (BT) etch. Next an epitaxial layer is grown. During the epitaxial growth a selective growth towards the hardmask in the second area is required. The epitaxial growth is only selective towards Si oxide and Si nitride. Finally the hardmask is removed on the second area (FIG. 1(E)). Note that the hardmask cannot be removed before the epitaxial layer has grown as it should protect (at least the second area on) the wafer. In the state of the art approach the hardmask on the second area is removed afterwards by an etching step, which causes field oxide loss. A possible solution exists in providing an additional protective mask on the first area, which clearly would increase the complexity.
Silicon nitride is the typical material for spacers (4). Si nitride cannot be applied for the hardmask (5), as during hardmask removal it would remove the spacers (4) as well. An alternative would be the use of Si oxide. However, Si oxide is not an appropriate material either, as Si oxide may be used on top of the gate. When using a Si oxide hardmask, one would have to remove the hardmask very carefully in order not to damage the oxide capping layer on top of the gate (in order to protect the gate during the epitaxial growth). Using a Si oxide hardmask, the extra oxide on top of the second area must be removed, which increases field loss on the first area, as the latter ‘sees’ the double removal of the oxide layer. An option would be to use lithography and etch only on the second area, which increases complexity.
In the state of the art solutions it is neither possible to use poly-silicon as the hardmask material. The poly-Si hardmask would have to be removed before the epitaxial growth, as it does not allow such epitaxial growth in a selective way. The epitaxial layer will cover the whole wafer and not only fill the S/D areas of the first area. However, it would be desirable and advantageous to have a poly-Si hardmask, as it would allow etching selectively towards nitride and oxide (e.g. towards an oxide gate capping layer or towards the field oxide), which would put less strain.
It is thus desirable to provide a method for selective epitaxial growth of S/D areas that overcomes the drawbacks of the prior art solutions.