1. Field of the Invention
The present invention relates to electronic circuits and systems. More specifically, the present invention relates to electronic sensor systems.
2. Description of the Related Art
For systems having unknown delay variables in the control and/or data paths, data-capture clocks are often used to compensate for the variable delays. For instance, in a video imaging system having a detector and a signal processor, the signal coming into the processor from the detector may not be aligned with the system clock of the processor. A data-capture clock, which is typically a phase shifted version of the signal-processing clock, is used to capture the detector data at its optimum sampling time. However, this can result in data path uncertainty if the sampling edge of the data-capture clock causes the captured data to change during the setup and hold time region of the signal-processing clock. The relative position of the data-capture clock also causes undesirable timing shifts to the signal processing module. These shortcomings limit the adjustment range of the data-capture clock, which, for some applications (especially high speed applications), is critical to the system.
Moreover, signal processing modules in a digital system are often synchronized to a common system clock. This implies that the optimum data-sampling time of all data entry paths all must fall within a certain region of the signal-processing clock. Costly custom tailored add-ons (i.e. delay lines) for an individual system may be needed to guarantee this timing condition.
One prior art solution to these data path uncertainty and timing shift issues includes separating the signal processing module into control and processing sections, each running its own tailored timing. This assumes that there cannot be much correlation between the two sections within the module because of possible clock alignment in the forbidden zone. For multi-module systems, it is hard to pass data among different sections because the processing sections in each module may have a different clock phase.
A second prior art solution delays the detector controls to align the detector video with the signal-processing clock. This approach requires expensive, power hungry, and space consuming variable delay lines to obtain the desired delay adjustment resolution.
Another solution includes adding an intermediate data buffer stage to allow independent access to the data at pixel level timing. This requires large memory buffers, and the signal processing may not start at a dedicated clock cycle due to clock phasing issues. For systems having multiple parallel signal processing modules, signal processing can only begin when all the buffers are not empty because the clock phasing may not be the same for all modules.
Another prior art approach involves supplying the detector with fixed controls and having the detector electronics provide the data clock associated with its outputs. Sections in the signal processing module must run its own tailored timing. Data exchanges and communications among sections may be difficult, especially for multi-module systems, due to clock phasing issues.
Hence, there is a need in the art for an improved system or method for aligning an input data signal with the system clock of a signal processor, which overcomes the shortcomings of prior systems.