The present invention generally relates to semiconductor devices (here, the invention chiefly relates to semiconductor memory devices, and a semiconductor memory device will hereinafter be described), and particularly to the redundancy technique for relieving defects by replacing defective memory cells by spare memory cells.
High-density integration of semiconductor memory has been highly advanced up to the mass production of dynamic random access memories (DRAM) of 256 mega bits. This high-density integration advancement involves extreme reduction of element size and great increase of the number of elements, thus causing a problem of low yield due to defects. As a countermeasure against this problem, the so-called redundancy technique is known, in which the defective memory cells are replaced, or repaired by redundant memory cells as the spare, or back-up memory cells that are previously provided on a memory chip. Efforts to enhance the efficiency of the defect repair have been made in this technical field. An example of the defect repair technology for DRAM is disclosed in JP-A-2-192100 (laid open Jul. 27, 1990) in which the decision for column-side repair performed according to a row address, and column selection lines are replaced by redundant column selection lines so that block repair can be made. This method is powerful because a large number of defective memory cells can be replaced by a small number of redundant column selection lines.
FIG. 2 is a schematic diagram of a conventional logic construction for block redundancy. Here, a memory cell group of two regions including defects is replaced by a redundant memory cell group. A memory cell array NMCA and a redundant cell array RMCA are provided and controlled by a repair decision circuit YRC. The memory cell array NMCA has memory cells provided at the intersections of N word lines WLs and M data lines DLs, and the memory cells are selected by a row decoder XDEC and a column decoder YDEC. The redundant cell array RMCA has redundant memory cells provided at the intersections of N word lines WLs and P data lines RDLs, and the redundant memory cells are selected by the row decoder XDEC and a redundant column decoder RYD. The row decoder XDEC decodes a row address AX of n bits and selectively drives one of the 2n, or N word lines. The column decoder YDEC decodes a column address AY of m bits and selects one of the 2m, or M data lines DLs. The redundant column decoder RYD decodes p bits of the column address AY, and selects one of the 2p, or P redundant data lines RDLs. A repair decision result RYH from the repair decision circuit YRC controls the column decoder YDEC and the redundant column decoder RYD. If the repair decision result RYH is xe2x80x980xe2x80x99, the column decoder YDEC is activated to select memory cells within the memory cell array NMCA. If the repair decision result RYH is xe2x80x981xe2x80x99, the redundant column decoder RYD is activated to select redundant memory cells within the redundant cell array RMCA. Thus, the memory cell group of defects DF1, DF2 can be replaced by a redundant memory cell group. A unit of memory cells to be replaced is the area selected by Q word lines and P data lines.
The repair decision circuit YRC is formed by two row address comparators AXC, two column address comparators AYC, two dual-input AND gates AND2, and an dual-input OR gate OR2. A pair of one row address comparator AXC and one column address comparator AYC stores one region to be repaired, or replaced. Each row address comparator AXC includes address storage means for storing a repair address of (nxe2x88x92q) bits, and compares it with the (nxe2x88x92q) bits of the row address AX. Each column address comparator AYC includes address storage means for storing a repair address of (mxe2x88x92p) bits, and compares it with the (mxe2x88x92p) bits of the column address AY. The dual-input AND gates AND2 take logic products of coincidence decision results XHC1, XHC2 from the row address comparators AXC and coincidence decision results YH1, YH2 from the column address comparators AYC to produce decision results HC1, HC2 for the two, first and second replacements. The dual-input OR gate OR2 takes a logical sum of these decision results to produce the repair decision result RYH. Since the repair decision circuit is constructed as above, defects at separate column addresses can be repaired according to the row addresses, or replaced by redundant memory cells on the same redundant data line.
In the column block redundancy shown in FIG. 2, the row addresses in the first replacement must be different from those in the second replacement. In other words, the repair row address stored in one of the two row address comparators AXC must be different from that of the other. If the same row address were stored in the two comparators, the replacing regions RPD would be one region, or the replaced regions would compete with each other for acquiring the one region irrespective of whether the column addresses of the replaced regions RPO are different or not. Therefore, even though two repair addresses can be stored, it is impossible to repair the case in which two defects occur in different-column-address regions but in the same-row-address regions each of which is selected by Q word lines and P data lines. In order to reduce the probability of that case in which both defects cannot be relieved because the replaced regions RPO compete with each other about taking one replacing region RPD, it can be considered to decrease the number, Q of word lines that are one replacement unit. However, if the number Q is decreased, it is necessary to increase the number of bits, (nxe2x88x92q) of the row address that the row address comparator AXC compares with, so that the circuit scale of the row address comparator becomes large.
Accordingly, it is desired to contrive a method of effectively repairing a plurality of defects at the same time. That is, it is an object of the invention to provide a semiconductor memory device having a redundancy circuit capable of effectively repairing defects by use of small-circuit-scale address comparators that compare with a smaller number of bits, and by controlling the replacement operation so that the competition between the replaced regions can be avoided.
According to one aspect of the invention, there is provided a semiconductor memory device having a plurality of word lines, a plurality of bit lines arranged to intersect the plurality of word lines, a large number of memory cells arranged at necessary intersections between the plurality of word lines and the plurality of bit lines, a plurality of spare bit lines arranged to intersect the plurality of word lines, a plurality of spare memory cells arranged at necessary intersections between the plurality of word lines and the plurality of spare bit lines, and a redundancy circuit for replacing memory cell groups, including defects, of the large number of memory cells by spare memory cell groups of the spare memory cells, wherein the redundancy circuit has functions to control a first replacement to be made by a first replacing unit, and a second replacement to be made by a second replacing unit that is smaller than the first replacing unit, and to give the second replacement priority when the first and second replacements compete with each other about taking the replacing spare memory cell groups.
In other words, the redundancy circuit controls the first replacement to be made by the first replacing unit and the second replacement to be made by the second replacing unit that is smaller than the first replacing unit, and it includes a first decision circuit for deciding about at least a first part of an address provided to select the large number of memory cells, a second address decision circuit for deciding about a second part of the address, and a third address decision circuit for deciding about at least a third part of the address except the second part, whereby when the second address decision circuit produces a miss, the second replacement is not performed but the first replacement is made according to the output from the first address decision circuit, and when the second address decision circuit produces a hit, the first replacement is not performed but the second replacement is made according to the output from the third address decision circuit.