Two interconnected PCI Express components are required to form at least one PCI Express link per port. Ports with more than a single lane may form a single link, which uses all available lanes or may optionally be sub-divided into multiple links with each link connected to a different PCI Express component. However, all traffic between any two PCI Express components travels on the same link, which can inefficiently use bandwidth and power as small data packets with low priority travel on the same link and at the same data rate as large data packets with high priority. Therefore, there is a need for a method to more efficiently utilize bandwidth and power.