In the manufacture of microelectronic devices, integrated circuits are formed on a semiconductor substrate, which generally includes silicon or other materials such as gallium arsenide, and a plurality of interconnect layers such as copper layers, aluminum layers, and the like. With the development of semiconductor technology and integrated circuits, semiconductor technology continues to advance to smaller technology nodes, a semiconductor substrate may include an increased number of integrated circuits. The processed semiconductor substrate is then cut into a number of finished integrated circuits that can be individually packaged.
However, with the continuous shrinking of the size of the semiconductor devices, in processing semiconductor devices with technology nodes of 40 nm and below, the finished products after the laser grooving and diamond cutting processes suffer cracking, peeling, and delamination defects.
Two methods are currently available to solve delamination problems: the first one is to form an opening in the top layer of the passivation layer in the scribe line region; and the second one is to reduce the size of the test pad and copper metal layer in the scribe line to avoid stress due to laser cutting. However, the conventional methods cannot prevent delamination from occurring.
FIG. 1 is a cross-sectional view of a semiconductor device containing a sealing ring, as known in the prior art. A semiconductor device (alternatively referred to as integrated circuit or chip) 10 includes semiconductor substrate 100, a chip edge 110, a cutting region disposed at an outer periphery of the semiconductor device, and a seal ring 120 disposed between the cutting region and a chip region to effectively prevent cracking and peeling in the chip caused by dicing of the semiconductor substrate. The seal ring is formed in the metal layer and the dielectric layer of a semiconductor substrate. The seal ring may be a stacked structure of several metal layers connected together through the through-holes (vias) in the interlayer dielectric layers or other mechanical stress buffering structures.
Delamination occurs because stress is generated when a metal pad is cut during the laser scribing process, the stress is released after transmitting to the chip. Conventional seal rings cannot stop delamination, low dielectric constant materials are used in next-generation semiconductor processes, which greatly reduce the fracture toughness and adhesion between the layers made of different materials, thus expanding the range of the delamination and cracking in the dielectric layers. Delamination and cracking are generally generated at the edge of the chip and extend to the middle of the chip, adversely affecting the functional integrity and yield of the chip.
Thus, there is a need to provide a new semiconductor device that overcomes the disadvantages associated with prior art.