1. Field of the Invention
The present invention relates to a frequency divider circuit and a digital phase locked loop (PLL) circuit including the same.
2. Description of the Related Art
FIG. 1 is a block diagram of a general programmable digital PLL circuit.
As shown in FIG. 1, a digital PLL circuit 6 comprises, for example, a phase comparator 2, a digital counter 8, a frequency multiplier 4, and a frequency divider 5.
The phase comparator 2 compares a phase of a reference clock signal of a frequency f.sub.ref with that of an oscillation output f5 from the frequency divider 5 and outputs an up/down signal to a digital counter 8 in accordance with the result of the comparison. For example, when the frequency of the oscillation output f5 is lower than the reference clock signal, it outputs an up signal to the digital counter 8, while in the opposite case, it outputs a down signal to the digital counter 8.
The digital counter 8 counts up or counts down the count value from the least significant bit toward the most significant bit based on the up/down signal from the phase comparator 2 and outputs an n-bit count value to the frequency multiplier 4.
The frequency multiplier 4 has the same function as a voltage controlled oscillator (VCO), determines an oscillation frequency in accordance with an input count value S3, and finally outputs the target clock S4 of the frequency f.sub.0.
The frequency divider 5 outputs an oscillation output f5 obtained by dividing the output signal S4 from the frequency multiplier 4 to the phase comparator 2.
The digital PLL circuit 6 shown in FIG. 1 requires an operation time of as much as 2.sup.n /f.sub.ref to reach a locked status shown in FIG. 2 when the digital counter 8 is an n-bit counter.
In the digital PLL counter 6, the digital counter 8 is provided with a 32/33 frequency divider which selectively performs frequency division by 32 or 33 and uses this 32/33 frequency divider to count up or count down.
FIG. 3 is a circuit diagram of a frequency divider 1 of the related art which is provided in the digital counter 8 in FIG. 1.
FIGS. 7A to 7N and FIGS. 8A to 8N are timing charts of input signals S0, S7, S9, S11, and S14, and frequency division ratio determining signals S21, S14, S17, and S19.
FIGS. 7A to 7N are timing charts in the case where a 4/5 selecting signal S24 shown in FIG. 3 is a high level (when 4 is selected as a frequency division ratio in the circuit module 3). FIGS. 8A to 8N are timing charts in the case where the 4/5 selecting signal S24 shown in FIG. 3 is a low level (when 5 is selected as a frequency division ratio in the circuit module 3).
The frequency divider 1 divides the frequency of an input signal S0 by 32 or 33 in accordance with the 4/5 selecting signal S24.
As shown in FIG. 3, the frequency divider 1 comprises the circuit modules 3 and 5.
The circuit module 3 comprises D-type flip-flops (D-FFs) 7, 9, and 11, an AND circuit 13, and an OR circuit 14.
The D-FFs 7, 9, and 11 are driven using the input signal S0 as a reference clock.
The circuit module 3 divides the input signal S0 by 4 or 5 based on the frequency division ratio determining signal S21, shown in FIG. 7J and FIG. 8J, input from the circuit module 5 and outputs the divided signal S7 from a Q.sup.-- terminal of the D-FF 7 to the circuit module 5. Specifically, the circuit module 3 produces the signal S7 shown in FIG. 8B obtained by dividing the input signal S0 by 5 when the frequency division ratio determining signal S21 is a high level, and produces the signal S7 shown in FIG. 7B obtained by dividing the input signal S0 by 4 when the frequency division ratio determining signal S21 is a low level.
The circuit module 5 comprises D-FFs 15, 17, and 19, a 4-input NOR circuit 21, and a buffer 23.
In the circuit module 5, a CLK terminal of the D-FF 15 is connected to a Q.sup.-- terminal of the D-FF 7 in the circuit module 3, a Q terminal of the D-FF 15 is connected to a CLK terminal of the D-FF 17, and a Q terminal of the D-FF 17 is connected to a CLK terminal of the D-FF 19. Also, in the D-FFs 15, 17, and 19, the D terminals and Q.sup.-- terminals are connected.
Here, the D-FFs 15, 17, and 19 are connected in series and each D-FF can divide a signal into two. Accordingly, a signal S19 shown in FIGS. 7N and 8N obtained by dividing the signal S7 by 8 (=2.sup.3) is output at the Q terminal of the D-FF 19.
The signal S19 is output as an output signal S1 via the buffer 23.
A signal S15 shown in FIGS. 7L and 8L obtained by dividing the signal S7 by 2 (.dbd.2.sup.1) is output from the Q terminal of the D-FF 15, and a signal S17 shown in FIGS. 7M and 8M obtained by dividing the signal S7 by 4(=22) is output from the Q terminal of the D-FF 17.
The NOR circuit 21 receives as input four signals, that is, the signals S15, S17, and S19 from the Q terminals of the D-FFs 15, 17, and 19 and the 4/5 selecting signal S24, and outputs the result of the NOR operation to the AND circuit 13 in the circuit module 13 as a frequency division ratio determining signal S21. Here, the frequency division ratio determining signal S21 becomes a high level, as shown in FIGS. 7J and 8J, when all of the signals S15, S17, and S19 and the 4/5 selecting signal S24 are a low level, while becomes a low level in other cases.
In the case of dividing a signal by 32 in the frequency divider 1, the 4/5 selecting signal S24 is held at a high level and the signal S7 obtained by dividing the input signal S0 by 4 is divided by 8 in the circuit module 5. As a result, an output signal S1 obtained by dividing the input signal S0 by 32 is produced.
On the other hand, when the frequency divider 1 divides a signal by 33, it makes the circuit module 3 act as a 1/4 frequency divider for seven cycles out of 8 cycles of the signal S7 and act as a 1/5 frequency divider for one cycle out of eight cycles. Due to this, the operation becomes (4.times.7/8+5.times.1/8).times.8, so the frequency divider 1 produces the output signal S1 obtained by dividing the input signal S0 by 33.
The problem in the related art was, however, that the PLL circuits used in the cellular phone and other communications fields mainly use frequency dividers containing bipolar, not MOS logic, since the local frequencies have high frequency bandwidths of 1 GHz or more.
Also, the power source voltage of PLL circuits used in such communications fields is 3V in most cases, and a basic type of a D-FF has the configuration shown in FIG. 4.
Namely, the D-FF comprises differential amplifier circuits 200 and 201, emitter-coupled logic (ECL) circuits 202 and 203, and latch circuits 204 and 205.
The differential amplifier circuit 200 comprises emitter-coupled npn-type transistors Q1 and Q2 and a constant current source I0 provided at the coupling point. The differential amplifier circuit 201 comprises emitter-coupled npn-type transistors Q3 and Q4 and a constant current source I1 provided at the coupling point.
The ECL circuit 202 comprises emitter-coupled npn-type transistors Q5 and Q6. The ECL circuit 203 comprises emitter-coupled npn-type transistors Q9 and Q10.
The latch circuit 204 comprises collector-, base-, and emitter-coupled npn-type transistors Q7 and Q8. The latch circuit 205 comprises collector-, base-, and emitter-coupled npn-type transistors Q11 and Q12.
In this circuit configuration, the output amplitude of the D-FF can only be about 0.3V or less. It is necessary to reduce the load resistance to improve the through rate.
However, recent cellular phones are expected to provide longer call times, therefore if the load resistance is made small as mentioned above, this will result in an increase of the current consumption and the power consumption.
Also, when the through rate is poor, the jitter increases in the output of a bipolar ECL circuit and noise increases in the VCO output signal of the PLL circuit. As a result, the bit error rate of the digital communications signal becomes Inferior.
For example, in the D-FF in FIG. 4, when the waveforms of an E input signal and an F input signal produced by an input signal from the D terminal are as shown in FIG. 5A, jitter Ax shown in FIG. 5B is generated in the output signals G and H.
Note that in the frequency divider 1 shown in FIG. 3, the D-FFs 15, 17, and 19 are serially connected in an asynchronous mode in the circuit module 5.
Accordingly, the jitter occurring at the D-FF 15 is transmitted to the D-FFs 17 and 19, and jitter .DELTA.Y, which is three times the jitter AX, occurs in the output signals G and H output from the final stage D-FF 19 as shown in FIG. 5C.
Consequently, in the frequency divider 1 shown in FIG. 3, the jitter becomes large in the finally obtained output signal S1. If the frequency divider 1 is used in a PLL circuit, the phase noise of the VCO output signal of the PLL circuit will increase and the bit error rate of the digital communications signal will end up becoming inferior.