Embodiments of the present invention relate to a non-volatile memory device and method for controlling the same, and more specifically, to a technology for increasing the operation reliability of a non-volatile memory device in such a manner that the sensing and transmitting of data can be stably achieved during a read operation in which data stored in a unit cell is output externally.
Semiconductor memory devices have been rapidly developed to temporarily or permanently store data therein. The semiconductor memory devices have been widely used in a variety of electronic appliances, electronic devices, and personal portable devices. General semiconductor memory devices can freely read and/or write data, and can also easily update old data with new data.
The semiconductor memory device has been increasingly developed such that it can store much more data therein, can be operated with a smaller amount of power, and can have an increased or expedited operating speed. Although a NOR flash memory device or a NAND flash memory device has been widely used as non-volatile memory, a conventional flash memory device has a disadvantage in that it has a slow operating speed. In order to overcome the above-mentioned disadvantage, a non-volatile solid status memory device, generally called a magnetic random access memory (RAM) device or a magnetic memory device, has been recently proposed and developed.
A non-volatile memory device formed of a magnetic material has not only characteristics of a dynamic RAM (DRAM) device which has a high data processing speed, a high integration degree, and low power consumption, but also characteristics of a flash memory device capable of preserving data even when not powered. Unlike a DRAM device for storing information according to an electrical charging scheme, the non-volatile memory device formed of the magnetic material stores information or data using a magneto resistive effect, and may be implemented with a Giant Magneto Resistive (GMR) element or a Tunneling Magneto Resistance (TMR) element.
FIG. 1 is a circuit diagram illustrating a read operation of a general non-volatile memory device.
Referring to FIG. 1, the general non-volatile memory device includes a unit cell 110, a bit line 120, a source line 130, a sense-amplifier (also called a sense-amp) 140, a first switching unit 150, a second switching unit 160, a third switching unit 170, and a fourth switching unit 180.
In this case, the unit cell 100 includes a Magnetic Tunneling Junction (MTJ) element 112 and a cell transistor 114. The MTJ element 112 has a resistive MTJ (RMTJ) value, and the cell transistor 114 is controlled by a voltage of a word line WL.
The bit line 120 is coupled to the MTJ element 112, such that it has a bit line resistance (RBL) value. The source line 130 is coupled between one end of the cell transistor 114 and the second switching unit 160, such that it has a source line resistance (RSL) value.
The sense-amp 140 includes a current source IREF, a switching element, and an amplifier, such that it senses and amplifies data stored in the unit cell 110. In this case, the current source IREF generates a bit line current IBIT in response to a core voltage VCORE. The amplifier compares a voltage generated by the current source IREF with a reference voltage VREF, such that it outputs an output voltage VOUT. The switching element is controlled by a voltage suppression signal (also called a voltage clamping control signal) VCMP, such that it restricts a level of a bit line current IBIT generated by the current source IREF.
Generally, a memory is configured in the form of an array which is composed of a plurality of cells. Therefore, on a current path to obtain data stored in the specific unit cell 110, there are parasitic resistances of common signal lines 120 and 130 and the first switching unit 150, the second switching unit 160, the third switching unit 170, and the fourth switching unit 180 for selecting the specific unit cell 110.
The first switching unit 150 controls a connection between the bit line 120 and the third switching unit 170 when selecting the unit cell 110 in response to a selection signal SEL serving as an output signal of a decoder. In addition, the second switching unit 160 controls a connection between the source line 130 and the fourth switching unit 180 when selecting the unit cell 110 in response to the selection signal SEL. The third and fourth switching units 170 and 180 control a read operation in response to a read control signal RDE from an external part.
In order to show how the current IBIT flows in a path including the unit cell 110 when the non-volatile memory device performs the read operation, FIG. 1 illustrates resistance values belonging to all constituent elements.
In the non-volatile memory device such as a magnetic memory, data is stored as a resistance value in the MTJ element 112. Generally, the MTJ element 112 has a three-layered structure in which one insulation layer is located between two ferromagnetic layers. In the non-volatile memory device, a magnetization direction of the ferromagnetic layer is determined depending on a direction of a current applied to the MTJ element 112, such that a resistance value is determined depending on the current direction.
In order to obtain the data stored in the magnetic memory, a given voltage is applied to both ends of the MTJ element 112, and the current flowing in the MTJ element 112 is measured, so that it is determined whether the MTJ element 112 is in a high resistance (RH) state or a low resistance (RL) state.
For example, digital data of ‘0’ or ‘1’ may be determined in response to a resistance value of the MTJ element 112. Such digital data ‘0’ and ‘1’ may respectively represent a case in which the resistance value of the MTJ element 112 is higher than a reference resistance value and the other case in which the resistance value of the MTJ element 112 is equal to or lower than the reference resistance value. This allows a user to recognize which data is stored in the MTJ element 112.
In other words, the first case in which the MTJ element 112 has a high resistance RMTJ value means that two magnetic substances constructing the MTJ element 112 have opposite magnetization directions. On the other hand, the second case in which the MTJ element 112 has a low resistance RMTJ value means that the two magnetic substances have parallel magnetization directions.
In this case, although the resistance RMTJ value of the MTJ element 112 contained in the unit cell 110 is changed according to data, resistance values of constituent elements other than the resistor RMTJ are not changed depending on data. That is, resistance values of the first to fourth switching units 150-180 for selecting the unit cell 110 or performing the read operation, a resistance value of the bit line 120, and a resistance value of the source line 130 have fixed values that are not changed depending on data.
In the case of performing the read operation, a sensing voltage VRD for detecting data is applied to one end of the unit cell 110 and a ground voltage is applied to the other end of the unit cell 110, such that the current IBIT flowing in the unit cell 110 is measured. In this case, the sense-amp 140 compares the measured current IBIT with a reference value VREF, such that it determines whether a resistance value of the MTJ element 112 is higher or lower than the reference value VREF.
In a general non-volatile memory device, the sense-amp 140 is not individually coupled to one unit cell 110, and is coupled to a cell array including a plurality of unit cells.
In addition, during the read operation, the sensing voltage VRD passes through not only one unit cell 110 but also a plurality of constituent elements having unique resistance values, such that the current IBIT flowing in the unit cell 110 is very small when the read operation is performed.
The small current IBIT means that the intensity of a signal to be output in response to data is very low. A TMR value is used to define the signal intensity. The TMR value is defined as a specific value obtained when a difference between resistance values of two states of the MTJ element 112 is divided by a smaller one of the two resistance values. The TMR value may be represented by “TMR=(RH−RL)/RL*100[%]”.
However, assuming that one MTJ element 112 in the non-volatile memory device has a TMR value of about 100%, when measuring the TMR value of the MTJ element 112 along a read path of a cell array contained in an actual non-volatile memory device, the TMR value of about 100% is reduced to a TMR value of about 30% due to parasitic resistance of other constituent elements.
In response to the voltage clamping control signal VCMP, the sense-amp 140 may apply the core voltage VCORE to the read path so as to restrict the sensing voltage VRD to a predetermined level or less, such that it substantially prevents an excessive current from being applied to the MTJ element 112 and thus physical properties of the MTJ element 112 are not broken or deteriorated.
FIG. 2 is a graph illustrating the current IBIT flowing in the read operation of the non-volatile memory device shown in FIG. 1.
Referring to FIG. 2, the sensing voltage VRD is controlled to be a predetermined level or less in response to the voltage clamping control signal VCMP. And, when the read control signal RDE, the selection signal SEL for selecting the unit cell 110, and the word line WL are activated, the current IBIT flows along the read path in response to data stored in the unit cell 110.
Thus, the current is changed depending on information stored in the MTJ element 112. That is, if the MTJ element 112 has high resistance, the current IBIT flowing in response to data is changed to a low current IH smaller than a reference current IREF. Otherwise, if the MTJ element 112 has low resistance, the current IBIT flowing in response to data is changed to a high current IL greater than the reference current IREF. In this case, the low current IH and the high current IL are not always set to a fixed value, and may change according to an operation environment.
In FIG. 2, the horizontal axis represents data current IBIT, and a vertical axis represents a relative frequency P(I) of a cell having the data current IBIT.
As shown in FIG. 2, the sense-amp 140 determines whether or not the current IBIT is greater than the reference current IREF, such that it recognizes data stored in the unit cell 110. In this case, in order to substantially prevent an error from being generated in the read operation, it is necessary for the reference current IREF to maintain the range from the low current IH to the high current IL. In order to maximize an operation margin of the sense-amp 140, it is necessary for the reference current IREF to have an intermediate value between the low current IH and the high current IL.
In the case of using an absolute reference current scheme shown in FIG. 2, the reference current IREF maintains a predetermined value, such that a circuit for generating the reference current IREF can be simplified in structure. In this case, in order to maximize the operation margin of the sense-amp 140, the cell array needs to be designed in such a manner that the relative frequency P(I) of the current IBIT is maximized.
However, it should be noted that the P(I) distribution is not always maintained in an invariable shape. The data current distribution (i.e., variation of a position of P(I) and shape variation) may be generated by a variety of reasons. A representative one of such reasons is variation in resistance existing on the read path illustrated in FIG. 1.
Specifically, the relative frequency P(I) may be affected by where the specific unit cell 110 selected in the read operation is in the cell array. That is, the bit line resistor RBL, the source line resistor RSL, resistance of transistors in the first to fourth switching units 150˜180 serving as various kinds of switches, and resistance generated when the sensing voltage VRD is provided may affect the selected unit cell 110. In addition, in the process for manufacturing the non-volatile memory device, resistance variation caused by process variations of the MTJ element 112 may also encounter the variation of the P(I) position and shape.
In the case where data is sensed and amplified using the reference current IREF having an invariable value on the condition that the P(I) position and shape are changed due to the aforementioned reasons, the operation margin of the sense-amp 140 may be reduced. If worst comes to worst, a faulty operation in which data is incorrectly sensed may be generated.
FIG. 3 is a graph illustrating the current IBIT in the read operation of the non-volatile memory device so as to solve the problems shown in FIG. 2.
In order to increase the operation margin of the sense-amp 140 capable of sensing and amplifying the current IBIT flowing in the unit cell 110 during the read operation, a relative reference current scheme is used, instead of the absolute reference current scheme in which the reference current IREF has a predetermined value. The relative reference current scheme may also change the value of the reference current IREF in response to the variation of the relative frequency P(I) of the current IBIT.
The relative reference current scheme can maintain the sensing margin, such that it can readily read low-intensity information of the unit cell 110. However, in the relative reference current scheme, both the area of a circuit generating the reference current IREF and power consumption are increased so as to change the reference current IREF.