The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for providing a packaging for an eight-socket one-hop symmetric multiprocessing topology.
Symmetric multiprocessing (SMP) involves a multiprocessor computer hardware and software architecture where two or more identical processors are connected to a single shared main memory. The processors have full access to all I/O devices. All processors are treated equally, with none being reserved for special purposes. Most common multiprocessor systems today use SMP architecture. In the case of multi-core processors, the SMP architecture may apply to the cores, treating them as separate processors.
SMP systems are tightly coupled multiprocessor systems with a pool of processors running independently. The processors execute different programs and work on different data. The processors have a capability of sharing common resources (memory, I/O device, interrupt system, etc.). Processors may be interconnected using buses, crossbar switches, or on-chip mesh networks. The bottleneck in the scalability of SMP using buses or crossbar switches is the bandwidth and power consumption of the interconnect between the various processors, the memory, and the disk arrays.