1. Field of the Invention
The present invention relates to a semiconductor fabrication. More particularly, the invention relates to a salicided MOS device and a one-sided salicided MOS device on a semiconductor substrate and a simultaneous fabrication method thereof.
2. Description of the Related Art
Complimentary metal oxide semiconductor, (CMOS), devices, for both logic and memory applications, fabricated on the same semiconductor chip, have been commonly used. For example, an embedded dynamic random access memory (DRAM) device includes a memory array and a logic circuit array formed together in a single integrated circuit (IC) chip. This embedded DRAM can thus access a large amount of data at much higher speeds. The embedded DRAM is thus widely used in logic circuitry, to process large amounts of data, such as in a graphic or an image microprocessor. An accomplished embedded DRAM typically includes a logic circuit, a transfer field effect transistor (transfer FET, MOSFET) array, and a capacitor coupled to the transfer FET, wherein the transfer FET serves as a electrode of the capacitor and a selective switch when the transfer FET is selected by a bit line. The voltage status of the capacitor can therefore be read or changed through the transfer FET. One transfer FET typically includes a gate structure and an interchangeable source/drain region on each side of the gate structure. The capacitor is coupled to the interchangeable source/drain region on one side of the gate structure, typically is the source region.
In order to obtain lower resistance and increase device speed, a method of performing a self-aligned silicide (salicide) process to form a salicided layer on all exposed silicon surfaces of the gate and source/drain region is proposed. However, the salicide process usually consumes junction depth, causing a shallow junction (also silicide junction), which may cause a charge leakage of the capacitor. For some leakage-concerned products, such as DRAM and CMOS image sensor, non-silicide junction is required for partial positions, for example, the position(s) of source/drain region of MOS connecting capacitor in DRAM and the position(s) of source/drain region of MOS connecting photodiode region in CMOS image sensor.
FIGS. 1-3 are sectional views of a portion of a semiconductor substrate, schematically illustrating a conventional fabrication process for forming an embedded DRAM. In FIG. 1, an isolation structure 110, such as STI (shallow trench isolation) or FOX (field oxide isolation), is formed in/on a semiconductor substrate 100 so as to create a DRAM active region 102 and a logic active region 104 on the substrate 100. An oxide layer (not shown) and a polysilicon layer (not shown) are sequentially formed on the substrate 100. Then, the oxide layer and the polysilicon layer are patterned to form a first gate structure 116 in the DRAM active region 102 and a second gate structure 118 in the logic active region 104. The gate structure 116 includes a gate 120a and a gate oxide layer 120b; and the gate structure 118 includes a gate 130a and a gate oxide layer 130b. 
In FIG. 1, using the gate structures 116, 118 as a mask, lightly doped (LDD) regions 140 are respectively formed in the substrate 100 on each side of the gate structures 116, 118 by implantation. Then, a spacer 150 is formed on each sidewall of the first gate structure 116 and a spacer 155 is formed on each sidewall of the second gate structure 118. Then, interchangeable source/drain regions 160, 162, 164, 166 are respectively formed in the substrate 100 on each side of the gate structures 116, 118 by another implantation.
In FIG. 2, a photoresist layer 210 is formed on part of the substrate 100 to cover the interchangeable source/drain region 160 which will couple with a capacitor in subsequent process. Then, a self-aligned suicide (salicide) process is performed to form a silicide layer 220 on the gates 120a, 130a and the interchangeable source/drain regions 162, 164, 166.
In FIG. 3, the photoresist layer 210 is removed. Then, a capacitor 310 abutting the interchangeable source/drain region 160, such as a trench-type capacitor, is formed in the substrate 100. Number 320 denotes a dielectric film layer, conformal to an inner trench. Number 330 denotes an electrode coupled with the interchangeable source/drain region 160. The substrate 100 serves as another electrode of the capacitor 310.
According to the conventional method, however, since misalignment of the photoresist layer 210 easily occurs in submicron process, the DRAM cell performance cannot be precisely controlled. For example, when the misaligned photoresist layer 210′ covers part of the gate 120a, the silicide layer 220 cannot thoroughly form on the gate 120a, as shown in FIG. 4A. This affects the conductivity of the gate 120a. In addition, when the misaligned photoresist layer 210″ covers part of the interchangeable source/drain region 160, the silicide layer 220 partially forms on the interchangeable source/drain region 160, as shown in FIG. 4B. This may cause junction leakage (silicide junction), thereby decreasing device reliability.
U.S. Pat. No. 6,277,683 discloses a process for forming a salicided CMOS device and a non-salicided CMOS device on a semiconductor substrate. The method uses only one silicon nitride layer to provide a component for a composite spacer on the sides of the salicided CMOS device, and to provide a blocking shape for the non-salicided CMOS device during metal silicide formation. Nevertheless, this conventional method does not describe the process for forming a one-sided salicided CMOS device.
U.S. Pat. No. 6,063,706 discloses a process for forming a salicided device and an ESD protective device having no salicide on a semiconductor substrate. The method uses a pad silicon nitride to cover the ESD protective device, and then two-step salicide process is performed on the substrate to form a silicide layer on the surface of a functional region. Nevertheless, this conventional method does not describe the process for forming a one-sided salicided CMOS device.
U.S. Pat. No. 6,337,240 discloses a process for forming an embedded DRAM. The method implants ions onto a substrate with different dopant concentration to form different thickness gate oxide layers. An insulation layer serving as a mask is formed to cover the DRAM memory region. Then, a salicide process is performed to form a salicided layer on the surface of a logic region. Nevertheless, this conventional method does not describe the process for forming a one-sided salicided CMOS device.