In current technologies, the threshold voltage of semiconductor devices does not scale with the power supply voltage and ground rules because of the non-scalability of the sub-threshold slope. Thus, the minimum gate oxide thickness and/or maximum wordline boost voltage of the array MOSFET is constrained by reliability considerations.
When used for the support MOSFET, the relatively thick gate oxide (having a thickness of greater than ≈6 nm for deep sub-μm technology) required by the array MOSFET results in degradation in the performance of the MOSFET device. Furthermore, if a thinner gate oxide is used to improve the performance of the support circuitry, charge transfer efficiency in the device array is compromised as a result of the reliability limitation of the wordline boost voltage.
Ideally, in such technology, a dual gate oxide thickness is desired. In the prior art, it is known to subject the array transistor to a dual gate oxidation process or an alternative gate oxidation process as compared to the support circuitry. These additional gate oxidation processing steps are costly, and they are also yield limiting since one must utilize additional processing steps such as, but not limited to: masking, exposure, etching, oxidizing and strip masking, which grow a second oxide on the entire structure of the MOSFET device. As such, prior art gate oxidation processes are not reliable nor cost efficient.
In view of the drawbacks mentioned above with prior art processes of fabricating MOSFETs, there is a continued need for providing a new and improved method of fabricating a MOSFET and other devices in which a dielectric layer, e.g., gate oxide, having a dual thickness can be formed without adding extra processing steps and costs to the overall manufacturing process.