As semiconductor designs continue marching towards smaller geometry, back end of line (BEOL) copper wire formation with lower dielectric constant material becomes a significant challenge. Damascene integration techniques are commonly used to form copper wires and vias. Conventional damascene integration methods involve forming trenches in an insulator layer, depositing a thin diffusion barrier layer and seed layer on surfaces of the trenches, electroplating to fill the trenches in the insulator layer, and planarizing, e.g., with chemical mechanical polish (CMP). As geometry becomes increasingly smaller, e.g., sub-micron, it is very difficult to sputter and plate copper material into tiny damascene trenches. Moreover, a significant amount of copper (Cu) wire thickness variation exists when Cu-CMP is employed.