When making a CMOS device that includes metal gate electrodes, it may be necessary to make the NMOS and PMOS gate electrodes from different materials. A replacement gate process may be used to form gate electrodes from different metals. In that process, a polysilicon layer, bracketed by a pair of spacers, is removed to create a trench between the spacers on both NMOS and PMOS gate areas simultaneously. The trench is filled with a first metal. Then, the first metal layer is removed from either the NMOS or PMOS gate area and replaced with a second metal that differs from the first metal.
The replacement gate process requires the polysilicon and metal layers to be formed on a dielectric layer. The dielectric layer serves as an etch stop layer and prevents significant numbers of ions from reaching the channel when ions are implanted into the polysilicon layers. The dielectric layer may, for example, comprise silicon dioxide or a high-k dielectric layer.
U.S. Pat. No. 7,160,767 to Brask, et al. (“Brask”), provides a method for making a semiconductor device that includes metal gate electrodes, wherein such method includes replacing polysilicon layers with metal layers without damaging the channel region. However, Brask also has disadvantages. For example, the Brask method includes a large number of steps and is otherwise complex, such as its required removal of two different dummy gates, its deposition of two different high-K dielectric layers, and its performance of two different CMP processes. The Brask method is also disadvantageous in that gate height is lost due to the requirement for two different CMP processes. The complex and lengthy method taught by Brask is also very expensive. Brask also requires thick layers of precious metals, which are expensive to obtain. Moreover, the Brask method results in a metal gate plagued by internal seams, gaps or voids which, when not sufficiently filled, results in excessively high gate resistance.