1. Field of the Invention
The present invention relates to a power semiconductor device and a manufacturing method thereof, and more particularly to a power semiconductor device having adjustable output capacitance and a manufacturing method thereof.
2. Description of the Prior Art
Power semiconductor devices are typical semiconductor devices in power management applications, such as a switching power supply, a power control IC of a computer system or peripherals, a power supply of a backlight, motor controller, etc. Power semiconductor devices can include various kinds of transistors, such as an insulated gate bipolar transistor (IGBT) and a metal-oxide-semiconductor field effect transistor (MOSFET).
Please refer to FIG. 1, which is a schematic diagram illustrating a cross-sectional view of a trench MOSFET device according to the prior art. As shown in FIG. 1, the conventional trench MOSFET device 10 of the prior art includes a drain metal layer 12, an N-type substrate disposed on the drain metal layer 12, an N-type epitaxial layer 16 disposed on the N-type substrate 14, two P-type doped base regions 18 disposed in the N-type epitaxial layer 16, two N-type doped source regions disposed in the P-type doped base regions 18, an inter-layer dielectric (ILD) layer 22 and a source metal layer 24. The N-type epitaxial layer 16 has a trench 26, and an insulating layer 28 and a gate conductive layer 30 are sequentially disposed in the trench. The gate conductive layer 30 serves as a gate of the trench MOSFET device 10. In addition, each N-type doped source region 20 and each P-type doped base region are disposed at a side of the trench 26. The N-type doped source region 20 is regarded as a source of the trench MOSFET device 10, and each P-type doped base region 18 adjacent to the insulating layer 28 serves as a channel of the trench MOSFET device 10. The N-type epitaxial layer 16 serves as a drain of the trench MOSFET device 10. The ILD layer 22 is disposed on the gate conductive layer 30 and a part of the N-type doped source region 20, and the source metal layer 24 covers the ILD layer 22, each N-type doped source region 20 and each P-type doped base region 18, so that the source metal layer 24 is electrically connected to the each N-type doped source region 20 and each doped base region 18. The gate conductive layer 30, the ILD layer 22 and the source metal layer 24 form a first gate-source capacitor Cgs1, and the gate conductive layer 30, the insulating layer 28 and each P-type doped base region 18 form a second gate-source capacitor Cgs2. In addition, the gate conductive layer 30, the insulating layer 28 and the N-type epitaxial layer 16 form a gate-drain capacitor Cgd, and a depletion region between the P-type doped base region 18 and the N-type epitaxial layer 16 forms a drain-source capacitor Cds.
The desire for ever more compact electronic devices has pushed for size reductions in integrated circuits. Therefore, higher integrations and higher densities are developed continuously. The layout design for the conventional trench MOSFET device 10 has been investigated to reduce the trench width and the trench pitch. However, when the width of the trench 26 is reduced, the coupled area between the gate conductive layer 30 and the N-type epitaxial layer 16 is also reduced, and the contact area of the P-type doped base region 18 and the N-type epitaxial layer 16 is also reduced. Thus a capacitance of the gate-drain capacitor Cgd and a capacitance of the drain-source capacitor Cds are reduced, and an output capacitance of the trench MOSFET device 10 formed by the capacitance of the gate-drain capacitor Cgd and the capacitance of the drain-source capacitor Cds is reduced accordingly. In addition, the capacitance of the drain-source capacitor Cds is far larger than the capacitance of the gate-drain capacitor Cgd.
Generally speaking, the conventional trench MOSFET device is usually used in the converter, such as synchronous buck converter, of power management circuit, and is used to be a switching element of the converter, so that the conventional trench MOSFET device usually needs to perform an action of turning on or turning off. When the conventional trench MOSFET device is turned off, the output capacitance of the conventional trench MOSFET device is charged to a same voltage as an outside transformer. However, the converter further includes an inductor device, and the output capacitor and the inductor device form an LC oscillating circuit. Voltage spikes are generated accordingly, and the output capacitance of the conventional trench MOSFET device is reduced with decrease of the total device size and the trench width. Therefore, the voltage spikes caused by turning off the conventional trench MOSFET device are increased, and higher power loss is generated.
Please refer to FIG. 2, which is a schematic diagram illustrating a conventional circuit for reducing the voltage spikes. As shown in FIG. 2, a conventional method for reducing the voltage spikes is to electrically connect a snubber circuit 12 in parallel between the source S and the drain D of the conventional trench MOSFET device 10, and the snubber circuit 12 is formed by connecting a capacitor C and a resistor R in series. The capacitor C outside the conventional trench MOSFET device can be used to increase the output capacitance of the conventional trench MOSFET device 10 and reduce the voltage spikes. However, the extra electronic device generates extra circuit cost, and increases extra manufacturing process of welding. Thus the manufacturing cost is increased.
Accordingly, it is still needed for a novel manufacturing method of power semiconductor device to conveniently and economically resolve or mitigate the problem of the voltage spikes as aforesaid.