1. Field of the Invention
The present invention relates to an apparatus and method for determining variation in a predetermined physical property of a circuit.
2. Description of the Prior Art
In modern data processing systems, the individual components of data processing circuits are becoming smaller and smaller. As process geometries shrink, the variations in certain physical properties of the individual circuit components is becoming more significant, and techniques are required to enable those variations to be determined.
One physical property that may vary significantly between circuit components is referred to as an ageing effect, a variation in the ageing effect amongst components resulting from a variation in performance degradation of individual transistors over time. Examples of articles that describe monitoring techniques for the ageing effect are “An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization” by John Keane et al, IEEE Journal of Solid-State Circuits, Volume 46, No. 10, October 2011, and the article “A Precise-Tracking NBTI-Degradation Monitor Independent of NBTI Recovery Effect” by E Saneyoshi et al, 2010 IEEE International Solid-State Circuits Conference, Session 9, Digital Circuits and Sensors. However, both of these techniques are invasive, requiring an external tester to be used.
Another type of physical property that may vary between components within a circuit is a history effect that can occur in transistors that have a body region insulated from the substrate, the body region comprising the channel material in which a channel is established between a source and drain of the transistor below the gate of the transistor. One known technology that can be used to produce transistors having a body region insulated from the substrate is referred to as Silicon-On-Insulator (SOI) technology, where the SOI channel material is formed within a region of a thin superficial silicon layer above an oxide insulating layer and located under the gate of the transistor, reducing resistive leakage to the substrate and capacitive loading by the substrate. However, it has been found that the voltage on the body region becomes dependent on the previous circuit activity, this typically being referred to as the history effect. This variation in voltage on the body region can have an impact on the behaviour of components constructed using such transistors. The article “A New Structure for In-Depth History Effect Characterization on Partially Depleted SOI Transistors” by O Faynot et al, 2002 IEEE International SOI Conference, 10/02, pages 35 to 36, describes a technique for measuring the history effect, but similarly to the earlier described articles is invasive, and requires use of an external test probe.
Whilst techniques that use external testing equipment can be useful during the design and manufacture of components, for example to allow suitable margins to be set, it is still desirable to provide mechanisms that allow variations in certain physical properties to be monitored “on the fly” whilst circuits are in use, since if accurate information about such variations can be obtained in real time during use of the circuit, it may be possible to take certain actions in order to reduce or at least constrain such variations. The article “Run-Time Adaptive Performance Compensation using On-Chip Sensors” by M Hashimoto, Department of Information Systems Engineering, Osaka University and JST, CREST, ASPDAC '11 Proceedings of the 16th Asia and South Pacific Design Automation Conference, pages 285-290, describes a run-time performance adaptation technique using on-chip sensors for capturing delay variations, with circuit performance then being compensated according to the sensor outputs. The described technique does not provide any quantitive information as to the variations being observed.
A number of articles have been published that discuss techniques for monitoring the ageing effect of transistors on the fly during operation of integrated circuits. Examples of such articles include the article “A Compact Monitoring Circuit for Real-Time On-Chip Diagnosis of Hot-Carrier Induced Degradation” by H Oner et al, Proceedings of the IEEE 1997 International Conference on Microelectronic Test Structures, Volume 10, March 1997, the article “A TDC-Based Test Platform for Dynamic Circuit Ageing Characterisation” by M Chen et al, 2011 IEEE International Reliability Physics Symposium (IRPS), 10-14 Apr. 2011, 2B.2.1-2B.2.5, the article “On-Chip Circuit For Monitoring Frequency Degradation due to NBTI” by K Stawiasz et al, IEEE CFP08RPS-CDR 46th Annual International Reliability Physics Symposium, Phoenix, 2008, Pages 532 to 535, and the article “An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI and TDBD” by J Keane et al, IEEE Journal of Solid-State Circuits, Volume 45, No. 4, April 2010, Pages 817 to 829. Each of these techniques uses a ring oscillator as the circuitry to be monitored, and as such lacks flexibility in that the circuitry being monitored is somewhat artificial and cannot directly represent an actual circuit portion of a real data processing apparatus, for example a critical path within a processor. In addition, such techniques using ring oscillators as the monitored circuit cannot measure certain physical properties such as the earlier-mentioned history effect, since the history effect occurs primarily due to static data and hence the continual dynamic changes that occur within an oscillator will mask the history effect.
In the article “A Test Concept For Circuit Level Aging Demonstrated By A Differential Amplifier” by F. Chouard et al, 2010 IEEE International Reliability Physics Symposium, (IRPS), 2-6 May 2010, pages 826-829, the authors propose applying an accelerated aging technique to an analogue circuit, thereby allowing measurements to be taken from a tester after forced aging of the circuit to model the aging effects. This approach hence seeks to take aging into account by modeling/simulating aging rather than by measuring actual aging in a live circuit.
Accordingly, it would be desirable to provide a more flexible approach for determining variation in a predetermined physical property of a circuit, that can be used on the fly as and when required during the lifetime of the circuit.