In general, semiconductor device manufacturers conduct testing for device reliability in the evaluation of new products, design changes, and process changes. Most manufacturers subject their parts to a short period of accelerated stress testing prior to shipment in an effort to eliminate infant mortality failures. There is also a serious effort with many manufacturers to eliminate the infant mortality phenomena by some form of stress testing during wafer sorting. Even after the introduction of a new product or package, on-going monitoring of reliability and quality normally continues throughout the production life cycle. On-going reliability testing is normally performed both in order to monitor device performance and to accumulate statistical information.
As a result of such testing, possible wear-out mechanisms are identified and eliminated, either through modifications in the process or in the design. However, the manufactured devices may continue to exhibit early life failures or infant mortality failures. Examples of such defects includes oxide pinholes, photoresist or etching defects that cause near-opens or shorts, and contamination on the chip or in the package. A number of stress tests have been developed to accelerate the effects of various failure mechanisms. By subjecting a device to extreme operating conditions for a short period of time, such as for example, putting a device into a condition of abnormally high temperature and high voltage (such a test is called "burn-in test"), one can with some specified confidence level predict life and device performance under more normal conditions. In such a burn-in test, a static super voltage (about 7.0 to 8.5 volts) is applied to one or more pins of a device. Integrated semiconductor memory devices such as DRAMs and SRAMs typically include various input buffers for receiving externally provided address signals, data signals, and control signals via their pins (or pads). Each buffer acts as an input stage to circuits within the memory devices.
FIGS. 1 and 2 illustrate examples of the most widely used MOS input buffers for semiconductor devices. Referring first to FIG. 1, the CMOS input buffer 50 includes two serially-connected inverters 6 and 12. The inverter 6 is composed of a p-channel MOS (hereinafter abbreviated as PMOS) transistor 10 and an n-channel MOS (abbreviated as NMOS) transistor 11. The complementary MOS (abbreviated as CMOS) buffer 50 receives an externally applied input signal INE and converts the external signal into a compatible internal signal INI (or INI). The gates of the CMOS transistor pair 10 and 11 are supplied with the input signal INE. At the drain junction of the CMOS transistor pair 10 and 11, the internal signal INI compatible with the external signal INE is produced.
Referring now to FIG. 2, the CMOS input buffer circuit 60 includes a NOR gate 8 and an inverter 17. The NOR gate 8 is formed of PMOS transistors 13 and 14, and NMOS transistors 15 and 16. An input signal INE is externally applied to the gates of the transistors 14 and 15. An external control signal such as chip select signal CS is applied to the gates of the transistors 13 and 16.
Gate oxide is an important element of MOS transistors. This thin dielectric layer can break down, resulting in gate shorts, during a long or very strong application of electric field across the oxide. Oxide breakdown is generally believed to be caused by positive charge buildup. Therefore, in a reliability test mode such as burn-in test, input buffer oxide breakdown of the targeted device may occur due to the high voltage which is applied to the device for reliability evaluation. More specifically, in the input buffer 50 of FIG. 1, the NMOS transistor 11 is turned on when a super voltage input signal is applied to the input terminal of the CMOS inverter 6, but the PMOS transistor 10 is turned off. The drain voltage of the PMOS transistor 10 is then about Vss (i.e., 0 volt) while the source voltage thereof is Vdd. The difference of gate-source and gate-drain voltages of the PMOS transistor 10 may exert stress on its gate oxide and cause gate oxide breakdown. Similarly, in such an input buffer 60 of FIG. 2, there is a high probability that the gate oxide of the PMOS transistor 14 will be broken down by the stress due to the large difference between its gate-drain and gate-source voltages.