The proliferation of mobile communication devices including smart phones, notepads and laptops has resulted in significant efforts for efficient wireless transmission through adoption of new standards, hardware improvements and more sophisticated network management. As a result, there has been an ever increasing pressure to reduce cost, size and power consumption of such systems. This has driven designers to develop transceivers with higher levels of integration with much of the work focused on replacing the external components with integrated counterparts. This is not a trivial matter and often necessitates design of completely new transceiver architectures to achieve fewer off chip components.
On the other hand, there is a very high demand for performance from the modern integrated transceivers in order to achieve high modulation orders and hence to fulfill the high data rates driven by today's wireless and mobile applications. In this respect, the transceivers are required to provide an exceptionally good noise figure performance, linearity, matching, IQ (in-phase/quadrature) phase/gain balance and radio frequency (RF) local oscillator (LO) phase noise performance. While the latter is determined by the performance of the synthesizer circuit, the rest of the parameters are dependent on the components used within the transmit and receive chains.
Given the emphasis on integration and low cost, there is a major push for the adoption of, for example, sub-micron CMOS technology for the implementation of transceiver technology. The key characteristic of the technology is the low cost for implementing the digital functions but poor analogue and RF performance compared with other specialized technologies. Hence any use of digital functions in CMOS for improving the transceiver performance is very desirable and enables the use of the technology in high data rate wireless communication systems.