1. Field of the Invention
The present invention relates to a microcomputer and an electronic timepiece utilizing a microcomputer. More specifically, the present invention relates to a microcomputer employing an improved addressing system of a random access memory and an electronic timepiece utilizing such a microcomputer.
2. Description of the Prior Art
A conventional electronic timepiece employs frequency division utilizing counters. However, such conventional electronic timepiece involves an inconvenience in which the electronic circuit need be redesigned from the beginning in making modifications of the particulars of a timepiece circuit. In order to eliminate such inconvenience, an electronic timepiece utilizing a microcomputer has also been proposed and put into practical use. Such electronic timepiece utilizing a microcomputer is referred to as a microcomputer type timepiece in the present application for simplicity of description. Generally, a microcomputer type timepiece has an advantage that modifications of the particulars can be made by simply changing masks for use in fabricating a read only memory for storing a program.
FIG. 1 is a block diagram of a conventional microcomputer type timepiece. The timepiece shown comprises a reference signal generating circuit 1, a clock generator 2, a switch input circuit 3, a state control circuit 4, a timer counter 5, a chronograph counter 6, a read only memory 7, a program counter 8, a stack 9, an instruction register 10, a control circuit 11, an arithmetic logic unit 12, an accumulator 13, a random access memory 14, a decoder 15, and a latch circuit 16.
The reference signal generating circuit 1 is connected to a quartz resonator 17 and makes oscillation to provide an oscillating signal the frequency of which is determined by the quartz resonator 17. The oscillating signal is frequency divided and a predetermined frequency divided signal is applied to the clock generator 2, the switch input circuit 3, the timer counter 5, the chronograph counter 6 and the like. The reference frequency generating circuit 1 is also adapted to provide an interrupt signal INT2 for the purpose of causing a time count operation at each predetermined period of time, say for every 0.5 second.
The clock generator 2 generates a system clock signal for performing an operation as a central processing unit by the use of a frequency divided signal obtained from the reference frequency generating circuit 1 and the system clock signal is applied to various portions of the circuit. The clock generator 2 is supplied with a stop signal CLKSTOP for stopping generation of the clock signal from the state control circuit 4, so that the clock generator 2 is responsive to the stop signal CLKSTOP to stop the operation. The clock generator 2 is also connected to receive from the reference signal generating circuit 1, the chronograph counter 6 and the like the interrupt signals INT0, INT1, INT2 and INT3 and the timer output TIMEROUT and to receive an operation start signal CLKSTART, so that the clock generator is responsive to these signals to restart the operation which has been stopped.
The switch input circuit 3 comprises external terminals M1 to M4 and S1 to S4 for preventing a chattering phenomenon of the switches connected thereto and for receiving the on/off data of the switches connected thereto, while the data is transferred to the data bus DB. The on/off control of the switches connected to the external terminals S1 to S4 can be designated by the switch control signal SWCON of the state control circuit 4 and can provide an operation start signal CLKSTART in response to the on/off of the designated switch. Furthermore an interrupt signal INT3 can also be obtained in response to the on/off of the switches connected to the external terminals S1 to S4. In the chronograph mode a chronograph control signal CHRCON for controlling start, lap and stop of the chronograph counter 6 is obtained in response to the on/off of the switches connected to the terminals S1 and S2.
The state control circuit 4 is controlled in accordance with the program obtained over the instruction bus IB so that the states of the various circuits are controlled in various modes and provides the switch control signal SWCON for controlling the switch input circuit 3, the timer control signal TIMCON for performing selection of the reset, start and timer time period of the timer counter 5 and the stop signal CLKSTOP for stopping the operation of the clock generator 2. Furthermore there are provided an external terminal LAMP for connection of a lamp and an external terminal ALM connected to an alarm tone generator.
The timer counter 5 can allow for setting of a timer time period in accordance with the program sent over the instruction bus IB and provides a signal TIMEROUT for starting the operation of the clock generator 2 after the lapse of the timer time period.
The chronograph counter 6 comprises a counter for counting up to 1/100 second and 1/10 second and provides an interrupt signal INT1 at every 1/10 second. The count value in the chronograph counter 6 is applied through the chronograph data bus CDB to the decoder 15.
The read only memory 7 comprises 1390.times.14 bits and stores in a fixed manner a program for performing a timing operation and various controls. To that end the read only memory 7 provides to the instruction register 10 an instruction code of 14 bits stored in the address designated by the program counter 8 of 11 bits.
The instruction register 10 stores an instruction code obtained from the read only memory 7 and provides the same on the instruction bus IB.
The program counter 8 receives the next address or jump control signal after processing of one instruction to provide to the read only memory 7 an address signal of the address to which jump is to be made.
The stack 9 has the capacity of eight levels and stores the sum of the count value in the program counter 8 plus one in the case where the operation should shift to the interrupt processing or subroutine. However, an interrupt processing is to be made after the instruction "SCP" for stopping the operation of the clock generator 2 is executed, the count value of the program counter 8 is as such stored in the stack 9 and, after the end of the interrupt processing, again the stop instruction "SCP" of the clock is addressed and the same is executed.
The random access memory 14 stores in appropriate regions the data concerning the current time, an alarm time, a timer time period and the like. The addresses of the random access memory 14 are designated by the instructions obtained from the instruction register 10 and the data stored in the designated addresses is sent to the data bus DB in response to the read/write control signal R/W obtained from the control circuit 11 or the data sent to the data bus DB is stored in the designated addresses.
The arithmetic logic unit 12 receives data sent onto the data bus DB and makes an arithmetic operation such as addition, subtraction and the like and the result is stored in the accumulator 13 and is sent again onto the data bus DB.
The decoder 15 and the latch circuit 16 constitute a display circuit. The decoder 15 converts the applied data of four bits to seven segment signals for display and provides the same to the segment bus SB. The latch circuit 16 holds the segment signals sent to the segment bus SB and provides the same to the external terminals a to g and to that end the external terminals of the number corresponding to that of the segments are provided. Which latch circuit should store the converted segment signals is determined in accordance with the program and, in the case where the data of the first digit of the current time is converted, for example, the latch circuit 16 corresponding to the display unit for displaying the first digit of the current time is designated by the program. On the other hand, the decoder 15 is also connected to the chronograph data bus CDB for supply of the output from the chronograph counter 6 as well as the data bus DB and the decoder 15 is selectively connected to either the data bus DB or the chronograph data bus in accordance with the program.
The control circuit 11 deciphers the instructions of the read only memory 7 sent over the instruction bus IB and controls the respective circuits as a function of the system clock obtained from the clock generator 2 for the purpose of performing the operation corresponding to the instructions. Furthermore, the program counter 8 and the read only memory 7 are controlled to execute the processing corresponding to the interrupt when the interrupt signals INT0, INT1, INT2 and INT3 are provided.
Now a principal operation of the FIG. 1 timepiece will be described. When a power supply is turned on, an initial clear is rendered effective and the respective circuits are reset, while the program counter 8 designates the address zero of the read only memory 7. The address zero of the read only memory 7 stores the program for initial setting and therefore "0" or predetermined data is stored in the random access memory 14 through execution of the program, whereby initial setting is performed. Then the program of mode change is executed. This program serves to determine which mode, the current time mode, the alarm mode, the timer mode or the chronograph mode, or if another function has been employed, an additional mode, has been selected in accordance with the contents of the data representing the on/off of the switch applied to the data bus DB from the switch input circuit 3.
In the case where the current time mode is selected, for example, the current time is displayed. More specifically, the minute digit, the ten-minute digit, the hour digit, and the ten-hour digit stored in the predetermined address of the random access memory 14 are in succession addressed in accordance with the display instructions of the addressable random access memory 14 and the data is sent to the data bus DB. The segment signals as converted by the decoder 15 are stored in the latch circuit 16. The decoder 15 is in advance controlled by the instructions so that the data bus DB may be connected to the decoder 15. The latch circuit 16 serves to keep providing the stored segment signals to the external terminals a to g until the new segment data is renewed.
Then a coincidence detection program for detecting coincidence of the data concerning the current time stored in the predetermined address of the random access memory 14 and the data concerning the alarm time is executed in the case where the alarm mode is selected, for example. Coincidence detection is performed in succession for the ten-hour digit, the hour digit, the ten-minute digit and the minute digit and, upon detection of coincidence in all digits, the alarm signal is obtained at the output terminal ALM of the state control circuit 4.
Meanwhile, some type of electronic timepiece is adapted to have a so-called multialarm function. By multialarm function is meant a function capable of setting a plurality of alarm times per day. For example, a plurality of alarm times such as in the morning, day and evening may be set with such electronic timepiece and thus a multialarm function is of much convenience.
A typical conventional microcomputer type timepiece having a multialarm function is adapted such that a plurality of alarm times are stored in different addresses of the random access memory and coincidence of the same with the current time is detected for each of the stored data. Accordingly, a coincidence detection program for detecting coincidence of the current time and the alarm times requires two or more programs of different addressing data, with the resultant disadvantage that the program becomes complicated and lengthy. However, coincidence detection of the current time with alarm times is common to any of the alarm times. Therefore, if an addressing scheme for different alarm times could be simplified, the coincidence detection program could be accordingly simplified.