Field
The disclosed technology relates generally to semiconductor devices and more particularly to three dimensional semiconductor memory devices, such as vertical three dimensional non-volatile memory devices.
Description of the Related Technology
Recently, ultra-high density storage devices have been proposed. Some of the proposed devices are formed using a process architecture comprising a vertical channel three-dimensional (3D) stacked memory structure. One of the process architectures is referred to in the relevant industry as Bit Cost Scalable (BiCS) architecture. Some 3D NAND stacked memory devices are formed using a process architecture comprising a stack of alternating conductive and dielectric layers.
However, various process architectures for forming 3D NAND stacked memory devices take into account a fundamental trade-off: in order to maximize the density, one should share as many gates of memory cells in a given word plane as possible. In this regard, some process architectures use a stack of alternating polysilicon layers and dielectric layers, which are sometimes referred to as a polysilicon-oxide-polysilicon-oxide (POPO) approach, where P stands for polysilicon and O stands for silicon oxide (e.g., SiO2). However, one of the main drawbacks of the POPO approach is the relatively high resistance of the word lines formed by the alternating polysilicon layers. Alternatively, some process architectures contemplate using a metal gate electrode instead of a polysilicon gate electrode. This approach is sometimes referred to as a metal-oxide-metal-oxide (MOMO) approach, where M stands for metal and O for silicon oxide (e.g., SiO2). However, the MOMO approach has been hampered because of the relatively high stress in the stack.
Another approach is to apply replacement gate processes in which a sacrificial gate layer, e.g., a layer of silicon nitride, is used to form the alternating stack. Afterwards this sacrificial gate layer is replaced with the desired gate electrode material. This so-called nitride-oxide-nitride-oxide (NONO) approach however, where N stands for silicon nitride (e.g., Si3N4) and O for silicon oxide (e.g., SiO2), sometimes limits the width of the word plane to a few, e.g., four, cell strings. Such replacement gate processes have limited capability in filling the cavities of the removed replacement gate layer. This limited filling capacity can decrease the memory density because slits, through which the desired gate electrode material is provided, are formed every few rows. In addition, these slits have to go all the way down to the substrate which results in a large area. US2015/0079742 (see FIG. 6) discloses such a vertical channel-type three-dimensional semiconductor devices having replacement gates.
Thus, there is a need for novel and improved three-dimensional non-volatile memory devices, and fabrication methods thereof, with a reduced resistance-capacitor time constant of the word line, but still having a high memory density.