1. Field of the Invention
The present invention is related to dynamic random access memory (DRAM) devices. In particular, it relates to a system and method for improving a DRAM""s ability to capture data correctly on all data paths (DQs).
2. Description of Related Art
When double data rate (DDR) is applied to a memory device, the data is input/output to/from the memory device on both edges (i.e., rising and falling) of an external system clock CLK. That is, the memory device (e.g., a DRAM) receives/outputs two bits of data per whole CLK cycle, called 2-bit (or 2n) prefetch. A DDR II memory device is similar to a DDR device but runs off an external clock CLK which is twice as fast (e.g., 200 MHz) as a DDR external clock. DDR II uses a 4-bit (or 4n) prefetch such that 4-bits are transferred in/out of a data path then handled as one 4-bit-wide piece of data inside the memory.
Double data rate memory is one key element for boosting memory device throughput to keep pace with the ever-increasing throughput performance of microprocessors. By doubling the memory bandwidth over current generation synchronous DRAM devices, DDR II can provide a cost-effective, high-performance main memory solution that does not require a significant development or manufacturing investment, while maintaining a cost structure consistent with synchronous DRAMs. DDR II memory devices and modules are well-suited for a broad range of applications, especially the workstation and server markets, where the high module density and device architecture can meet the performance and reliability demands of these products.
DDR II memory technology has been defined and standardized by the Joint Electron Devices Engineering Council (JEDEC) as a next-generation memory solution. This technology is intended to facilitate adoption in a wide range of products, and to be offered in both device and module form from all major suppliers.
The DDR II standard proposes to have a minimum respective data setup and hold times of approximately 0.25 ns. Referring to FIG. 1, the data setup time is defined as the time the data is at the data input/output pin (DQ) before the next external system clock CLK edge arrives. The hold time is defined as the time the data stays valid after the clock edge. The entire window of data (setup and hold) is referred to as the xe2x80x9cdata eye.xe2x80x9d A data eye of approximately 1.5 ns is required in order for the DRAM to reliably capture the data (i.e., the DQ input pulse width (DIPW)). Moreover, in order for the DRAM to reliably capture the data, the clock CLK edge (either rising or falling) must be centered on the data eye. If the clock edge is not centered on the data eye, either one of the setup or hold times will be in danger of being of an insuffliciently short duration, which may prevent the DRAM from properly capturing the data.
There are many reasons why the clock edge may not be centered on the data eye. Some of those reasons include clock jitter, noise on the board, different lengths of data traces on the board, etc., which cause a clock skew to occur. The problem is exacerbated with higher clock frequencies since the setup and hold time is reduced in those cases, thus, leaving less room for error when attempting to locate the clock edge on the center of the data eye.
One overly complex solution to maintaining the clock edge near the center of the data eye that has been proposed is known as xe2x80x9cSyncLink.xe2x80x9d The SyncLink approach actually builds a mathematical model of the entire data eye and determines the exact location of the leading and trailing edges of the data. Once the system has calculated the location of the leading and trailing edges, the center of the data eye is calculated and the clock edge is located at the center of the data eye. While this method has proven to be accurate, it has also proven to be unnecessarily complex for most DDR II operating environments. This complexity results in greater chip complexity and cost. Thus, a simplified system and method are required to ensure that data which is input to a DRAM is properly timed relative to the external DRAM clock CLK such that the data is driven by a clock edge located on the center of the data eye and is, thereby, properly captured by the DRAM.
The present invention provides a simple system and method for controlling the rate with which data is input to a DRAM relative to the external DRAM clock CLK such that its clock edges are always centered on the data eye of input data to the DRAM, thus, ensuring that the data may always be properly captured by the DRAM.
In accordance with an exemplary embodiment of the invention, upon power-up or reset, during the existing initialization cycle time of the DRAM (i.e., 200 cycles under the DDR II standard), the write data capture calibration method of the invention is performed. A write command is issued by a memory controller and a simple repetitive string of data such as e.g., xe2x80x9c110011001100 . . . xe2x80x9d is sent by the memory controller to all the write data input paths (DQs) of the memory device, along with a bi-directional strobe (DQS) that is essentially a data clock aligned with data when it leaves the controller. The DRAM captures the data and performs a DQ to DQS delay adjustment to center the clock edge on the data eye for each DQ path. In the meantime, a delay lock loop (DLL) compares an internal data clock with the external clock to ensure they are both in phase. If they are out of phase, the DLL delays the internal clock until the two clocks are in phase. An auto-refresh automatically cancels the write data capture calibration method upon completion of the initial 200 cycles and the DRAM is returned to normal operation.