Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
A Fin field-effect transistor (FinFET) is a type of transistor that lends itself to the dual goals of reducing transistor size while maintaining transistor performance. The FinFET is a three dimensional transistor formed using a thin fin that extends upwardly from a semiconductor substrate. Transistor performance, often measured by its transconductance, is proportional to the width of the transistor channel. In a FinFET the transistor channel is formed along the vertical sidewall surfaces of the fin or on both vertical sidewall surfaces and the top horizontal plane of the fin, so a wide channel, and hence high performance, can be achieved without substantially increasing the area of the substrate surface required by the transistor.
FinFETs provide a promising candidate for small line width technology (e.g., approximately 22 nm and below) because of their excellent short channel effect control and scalability. However, FinFETs are often formed as an array on a bulk substrate or a silicon-on-insulator (SOI) substrate in an integrated circuit, with the FinFETs densely formed on the substrates and with the substrates including a base that connects the fins. The integrate circuits that include the FinFETs often suffer from sub-fin current leakage, especially when the FinFETs are formed on a bulk substrate, whereby some of the current that is passed between a source and drain for one FinFET passes through a body of the fin to other FinFETs that are formed on the fin, thereby affecting operation of the FinFETs on the fin.
Various solutions to minimize or prevent current leakage have been proposed. For example, silicon-on-insulator configurations have been employed to hinder current leakage between fins. Dopant implantation has also been applied to hinder current leakage in configurations where the fins are formed in bulk semiconductor material. In particular, with dopant implantation to hinder current leakage, bulk semiconductor material between fins and at a bottom of the fins, where the fins attach to the bulk substrate, is doped with a dopant that hinders flow of current therethrough. However, dopant implantation to hinder current leakage is difficult to accurately control and may adversely impact desired operation of the FinFETs.
Accordingly, it is desirable to provide integrated circuits that have FinFETs and methods of fabricating the integrated circuits that have FinFETs that resist sub-fin current leakage without adversely impacting desired operation of the FinFETs in the integrated circuits. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.