Memory devices are typically provided as internal storage areas in a computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM (read-only memory), which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents.
Computers almost always contain a small amount of ROM that holds instructions for starting up the computer, typically called a basic input output system (BIOS). Unlike RAM, ROM generally cannot be written to by a user. An EEPROM (electrically erasable programmable read-only memory) is a special type of non-volatile ROM that can be erased and programmed by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by specialized programming and erase operations.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called “erase blocks.” The memory cells of a Flash memory array are typically arranged into a “NOR” architecture (each cell directly coupled to a bitline) or a “NAND” architecture (cells coupled into “strings” of cells, such that each cell is coupled indirectly to a bitline and requires activating the other cells of the string for access, but allowing for a higher cell density). Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation. It is noted that other types of non-volatile memory exist which include, but not limited to, Polymer Memory, Ferroelectric Random Access Memory (FeRAM), Ovionics Unified Memory (OUM), Magnetoresistive Random Access Memory (MRAM), Molecular Memory, Nitride Read Only Memory (NROM), and Carbon Nanotube Memory.
Each erase block of a Flash memory device contains a series of physical pages that are typically each written to a single row of the Flash memory array and include one or more user data areas and associated control or overhead data areas. The control/overhead data areas contain overhead information for operation of physical row page and the user data area each overhead data space is associated with. Such overhead information typically includes, but is not limited to, erase block management (EBM) data, sector status information, or an error correction code (ECC). ECC's allow the Flash memory and/or an associated memory controller to detect data errors in the user data area and attempt to recover the user data if possible.
Many of the internal operations of volatile and non-volatile memories require that the memory perform data comparisons. Typically this data comparison is performed in the context of comparing data that has been read from the memory array with the data that was expected to be read in order to find discrepancies. The internal operations requiring data comparison include, but are not limited to, data write, block erasure, and memory testing. A problem with many modern memory devices and arrays is that, because of their increasing storage density levels and increasing size of each physical page/row of data of the array, this data comparison within the memory device has become a time consuming task and can affect the speed of operation, data throughput, and testing time required.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for circuits and methods to allow fast and efficient comparison of large amounts of data within memory devices.