Single crystal photovoltaic devices have been utilized for some time as sources of electrical power because they are inherently non-polluting, silent, and consume no expendable natural resources in their operation. However, the utility of such devices is limited by problems associated with the manufacture thereof. More particularly, single crystal materials (1) are difficult to produce in sizes substantially larger than several inches in diameter, (2) are thicker and heavier than their amorphous counterparts, and (3) are expensive and time consuming to fabricate.
Recently, considerable efforts have been made to develop systems for depositing amorphous semiconductor materials, each of which can encompass relatively large areas, and which can be doped to form p-type and n-type materials for the production of p-i-n type photovoltaic devices which are, in operation, substantially equivalent to their crystalline counterparts. It is to be noted that the term "amorphous," as used herein, includes all materials or alloys which have long range disorder, although they may have short or intermediate range order or even contain, at times, crystalline inclusions.
It is now possible to prepare amorphous silicon alloy material by glow discharge chemical vapor deposition. The silicon alloy material possesses (1) acceptably reduced concentrations of localized states in the energy gaps thereof, and (2) high quality electronic properties. Such techniques have been fully described in U.S. Pat. No. 4,226,898, entitled Amorphous Semiconductors Equivalent To Crystalline Semiconductors, issued to Stanford R. Ovshinsky and Arun Madan on Oct. 7, 1980, the disclosure of which is incorporated herein by reference. As disclosed in this patent, fluorine introduced into the discrete layers of amorphous silicon alloy material operates to substantially reduce the density of the localized states therein and facilitates the addition of other alloying materials, such as germanium.
Unlike crystallize silicon which is limited to batch processing for the manufacture of solar cells, amorphous silicon alloys can be deposited in multiple layers over large area substrates to form solar cells in a high volume, continuous processing system. Such continuous processing systems are disclosed in U.S. Pat. No. 4,400,409 entitled "A Method Of Making P-Doped Silicon Films And Devices Made Therefrom"; U.S. Pat. No. 4,410,558 entitled "Continuous Amorphous Solar Cell Production System"; U.S. Pat. No. 4,438,723, entitled "Multiple Chamber Deposition And Isolation System And Method"; U.S. Pat. No. 4,492,181 entitled "Method and Apparatus For Continuously Producing Tandem Amorphous Photovoltaic Cells"; and U.S. Pat. No. 4,485,125 entitled "Method and Apparatus For Continuously Producing Tandem Amorphous Photovoltaic Cells", the disclosures of which are incorporated herein by reference. As disclosed in these patents, a substrate may be continuously advanced through a succession of interconnected deposition chambers, wherein each chamber is dedicated to the deposition of a specific semiconductor material. In making a photovoltaic device of p-i-n type configuration, the first chamber is dedicated for depositing a p-type layer of silicon alloy material, the second chamber is dedicated for depositing an intrinsic layer of amorphous silicon alloy material, and the third chamber is dedicated for depositing a layer of n-type silicon alloy material.
Since each deposited layer of silicon alloy material, and especially the intrinsic layer, must be of high purity, (1) the deposition environment in the intrinsic deposition chamber is isolated, by specially designed gas gates, from the doping constituents introduced into the constituents into the intrinsic chamber, (2) the substrate is carefully cleansed prior to initiation of the deposition process to remove contaminants from the surface thereof, (3) all of the chambers which combine to form the deposition apparatus are sealed and leak checked to prevent the influx of environmental contaminants, (4) the deposition apparatus is evacuated and flushed with a sweep gas to remove contaminants from the interior walls thereof, and (5) only the purest reaction gases are employed from which to form the layers of silicon alloy material. In other words, every possible precaution is taken to insure that the sanctity of the vacuum envelope formed by the plurality of interconnected chambers of the deposition apparatus remains uncontaminated by impurities, regardless of origin.
The layers of silicon alloy thus deposited in the vacuum envelope of the deposition apparatus may be utilized to form a photovoltaic device including one or more p-i-n cells, one or more n-i-p cells, Schottky barrier devices, photodiodes, phototransistors, or the like. Additionally, by making multiple passes through the succession of deposition chambers, or by providing an additional array of deposition chambers, multiple stacked cells of various configurations may be obtained.
Most photovoltaic devices, having either single cell or multiple cell structures, preferably include a light reflecting back reflector for increasing the percentage of incident light reflected from the substrate back through the active layer of silicon alloy material of the cells. It should be obvious that the use of a back reflector increases the amount of light which passes through the active layer of silicon alloy material, thus increasing the amount of incident light which is converted to electricity, and increasing the operational efficiency of the photovoltaic device. However, all layers, other than the photoactive layers of silicon alloy material, deposited atop the light incident surface of the substrate must be substantially transparent (to 35 nanometers to one micron wavelength light) so as to pass a high percentage of incident light from the anti-reflective coating atop the photovoltaic cell to the highly reflective surface of the back reflector from which it is redirected through and absorbed by the photoactive layer of silicon alloy material.
The back reflector may be formed atop the deposition surface of the substrate if an opaque substrate is employed. The back reflector may be either specular or diffuse. With either type of back reflector, light which has initially passed through the layers of silicon alloy material from which the photovoltaic device is fabricated without being absorbed, is redirected by the highly reflective material of the back reflector to pass, once again, through the photoactive layers. The additional pass results in increased photon absorption and charge carrier generation, thereby providing increased short circuit current.
The aforedescribed thin film amorphous silicon alloy materials offer several distinct advantages over crystalline materials, insofar as they can be easily and economically fabricated to cover large areas by the newly developed mass production processes. However, in the fabrication of said silicon alloy materials by the aforementioned processes, the presence of current-shunting defects has been noted. These defects have (1) seriously impaired the performance of the photovoltaic devices fabricated therefrom and (2) detrimentally affected production yield. These process-related defects are thought to either (1) be present in the morphology of the substrate electrode, or (2) develop during the deposition of the multiple layers of silicon alloy material. The instant invention is directed toward eliminating, or at least substantially reducing, the effects of these current-shunting defects.
The most important of these defects may be characterized as "shunts," "short-circuits," defect regions, or low resistance current paths. Before the suspected causes of these defects are explained, it is helpful to note the thicknesses of the deposited of silicon alloy material layers. In a typical p-i-n type photovoltaic device, the "p" layer is on the order of 75-200 Angstroms thick, the intrinsic layer is on the order of 3,500 Angstroms thick, and the "n" layer is on the order of 75-200 Angstroms thick, thereby providing a total semiconductor body thickness of only about 4,000 Angstroms. It should therefore be appreciated that irregularities disposed on the deposition surface, however small, may not be fully covered by the conformally deposited layers of silicon alloy material.
Shunt defects are present when one or more low resistance current paths develop between the upper and lower electrodes of the photovoltaic device. Under operating conditions, a photovoltaic device in which a shunt defect has developed, exhibits either (1) low power output, since electrical current collected at the electrodes flows through the defect region (the path of least resistance) in preference to an external load, or (2) complete failure where sufficient current is shunted through the defect region to "burn out" the device.
While shunt-type defects always deleteriously affect the performance of photovoltaic devices, their effect is greatest when the devices in which they are incorporated are operated under relatively low illumination such as room light, vis-a-vis, high intensity illumination such as AM-1. Under room light illumination, the load resistance of the cell (i.e., the resistance under which the cell is designed to operate most efficiently) is comparable to the shunt resistance (i.e., the internal resistance imposed by the defect region), whereas under AM-1 illumination, the load resistance is much lower by comparison. This occurs because, in a photovoltaic device, photogenerated current increases linearly with increasing illumination, while the resulting voltage increases exponentially. In other words, voltage attains a relatively high value under low illumination, the value increasing only slightly as the intensity of the illumination is increased. Therefore, under low intensity illumination the relatively high voltage potential present preferentially drives the relatively small number of photogenerated current carriers through the path of least resistance, i.e., the low resistance defect regions. In contrast thereto, under high intensity illumination, a large number of current carriers are present and are driven by a potential of about the same magnitude as the potential which exists under low illumination. This larger number of current carriers compete for a limited number of least resistance paths (through the defect regions). The result is that under high intensity illumination, while more power may be lost to the defect region, the power lost is a smaller percentage of the total photogenerated power than under low intensity illumination.
Defects or defect regions, the terms being interchangeably used herein, are not limited to "overt" or "patent" short circuit current paths. In some cases, the adverse effects of a defect are latent and do not immediately manifest themselves. Latent defects can give rise to what will be referred to hereinafter as an "operational mode failure," wherein a photovoltaic device, initially exhibiting satisfactory electrical performance, suddenly fails. The failures will be referred to herein as operational mode failures regardless of whether the device was previously connected to a load for the photogeneration of power, it only being necessary that the device was, at some time subjected to illumination, thereby initiating the photogeneration of charge carriers. It is believed the shunt defects, both latent and patent, arise from one or more irregularities in the (1) morphology of the exposed surface of the substrate material, or (2) in the growth of the layers of silicon alloy material thereupon.
The first, and perhaps most important, source of the defects, i.e., the aforementioned morphological irregularities existing on the deposition surface of the substrate material, will now be discussed. Even though the highest quality, for example, stainless steel is employed as the substrate upon which the layers of silicon alloy material are successively deposited, it has been calculated that from 10,000 to 100,000 irregularities per square centimeter are present on the deposition surface thereof. Such irregularities take the form of projections, craters, or other deviations from a smooth finish and may be under a micron in (1) depth below the surface, (2) height above the surface, or (3) diameter. Regardless of their configuration or size, the defects may establish a low resistance current path through the layers of silicon alloy material, thereby effectively short-circuiting the two electrodes. This may occur in numerous ways. For instance, a spike projecting from the surface of the substrate electrode may be of too great a height to be covered by the subsequent deposition of the thin film layers of silicon alloy material, and therefore, be in direct electrical contact with the other light incident electrode when that upper electrode is deposited atop the layers of silicon alloy material. Likewise, a crater formed in the surface of the substrate electrode may be of too large a size to be filled by the subsequent deposition of the silicon alloy material. In such an instance: (1) electrical current may bridge the gap which exists between the electrodes, or (2) during actual use (the photoinduced generation of electrical current) of the photovoltaic device, the material of one of the electrodes may, under the influence of the electrical field, migrate toward and contact the other of the electrodes, and thereby pass electrical current therebetween. It is also possible that in some cases the layers of silicon alloy material deposited onto the substrate include regions of irregular composition which can provide low resistance paths for the flow of electrical current between the electrodes of the photovoltaic device.
Further, despite all the previously described efforts to maintain the vacuum envelope free of external contaminants, dust or other particulate matter, which somehow either (1) invades the vacuum envelope during the deposition of the silicon alloy material, or (2) forms as a by-product of the deposition process, may be deposited over the substrate electrode along with the silicon alloy material. The contaminants interfere with the uniform deposition of the layers of silicon alloy material and may establish low resistance current paths therethrough.
Additionally, it is suspected that in some case, the silicon alloy material may form micro-craters or micro-projections during the deposition thereof, even absent the presence of contaminants or pollutants from external sources. Such morphological deviations from a perfectly smooth and even surface means that the substrate is covered by silicon alloy material either (1) in an "ultra thin layer" (consider again that the total thickness of all layers is only on the order of 4,000 Angstroms and any reduction in coverage is indeed an ultra thin layer) or (2) not at all. Obviously, when the upper electrode material (typically a conductive transparent oxide) is deposited across the entire surface of the body of silicon alloy material, the defect regions cause the low resistance current path to develop, and electrical current is shunted therethrough. In still other cases involving defect regions, the presence of such defect regions is only detectable due to their deleterious effect upon the electrical and photoelectric properties of the resultant photovoltaic device. Finally, note that the defects described hereinabove may not be sufficiently severe to divert all electrical current through the low resistance path. However, the diversion or shunting of any current therethrough represents a loss in operational efficiency of the photovoltaic device and should therefore be eliminated. Moreover, the shunting of even small amounts of current through each of thousands of defect regions may combine to cause major losses in efficiency. Based upon the foregoing, it should be apparent to one ordinarily skilled in the art that a reduction in current flow through these defects and defect regions is critical to the fabrication of high-yield, high efficiency, large area thin film photovoltaic devices.
Several approaches with which to cope with gross amplifications of this problem have been implemented by the instant inventors and their colleagues. As described in U.S. Pat. No. 4,451,970 of Masatsugu Izu and Vincent Cannella, entitled "System and Method for Eliminating Short Circuit Current Paths In Photovoltaic Devices", the disclosure of which is incorporated herein by reference, the shunting of current through defect regions is treated by substantially eliminating those defect regions as an operative area of the semiconductor device. This is accomplished in an electrolytic process where electrode material is removed from the periphery of the defect site, effectively isolating the defect regions and preventing the flow of electrical current therethrough. However, the process described in the '970 patent is current dependent, i.e., the greater the amount of current flowing through a particular area of the device, such as a defect region, the greater the amount of electrode material (in the preferred embodiment indium tin oxide) removed. Consequently, said short circuit eliminating process performs admirably in removing the electrode material from the periphery of a large defect, and thereby preventing all current flow therethrough. However, since the method is current dependent, it is not as successful in eliminating the flow of current between the electrodes in the thousands of defect regions which are relatively small. And as previously mentioned, since a great many relatively small current shunting paths, taken in toto, divert a substantial amount of current from its desired path of travel, the low resistance current paths created by such small defect regions must also be eliminated or at least substantially reduced. Further, the electrolytic process described in the '970 patent neither detects nor helps in preventing the formation of current-shunting paths in the case of operational mode failures.
In U.S. Pat. No. 4,419,530 of Prem Nath, entitled "Improved Solar Cell and Method For Producing Same", the disclosure of which is incorporated herein by reference, there is described a method for electrically isolating small area segments of amorphous, thin film, large area photovoltaic devices. This isolation of defects is accomplished by (1) dividing the large area device into a plurality of small area segments, (2) testing the small area segments for electrical operability, and (3) electrically connecting only those small area segments of the large area device exhibiting a predetermined level of electrical operability, whereby a large area photovoltaic device comprising only electrically operative small area segments is formed. While this method effectively reduces or eliminates the effect of defects, it is not completely satisfactory for several reasons.
The step of dividing the large area solar cell into electrically isolated small area segments requires several production steps and also reduces the total area of the solar cell that is available for producing electrical energy. Further, the method can be time and cost intensive since the electrical output of each isolated portion must be tested and separate electrical connections must be made to provide electrical contact to each small area segment. Also, since entire small area segments are effectively eliminated from the final cell if they manifest a defect, proportional losses of efficiency are greater than they would be if only the precise area of the particular defect were eliminated. In addition, it is possible that defects (shorts) in a solar cell can develop after the cell has been in use, and the concept of dividing the surface of the large area cell into small area segments does not correct this type of latent defect.
Further, both of the foregoing patent applications relate to "after market" techniques which are applicable to (1) isolate only gross defect-containing regions, and (2) prevent any and all current flow through those defect containing regions. Accordingly, a need still exists for a photovoltaic device which substantially eliminates the deleterious effects of shunts and other defects, both large and small, whatever their origin, without operatively removing large portions of the active body of silicon alloy material or the electrode disposed thereupon, while maintaining an acceptable level of current flow across the entire surface of the device.
Another such method and device is disclosed in
U.S. Pat. No. 4,590,327, of Nath, et al, entitled "Photovoltaic Device and Method", the disclosure which is incorporated herein by reference. Disclosed therein are several configurations of current collecting bus grid structures for photovoltaic devices designed to minimize the effects of shorts, shunts, and other defects upon the performance of the devices. The structures for reducing the degrading effect of a low resistance current disclosed therein can be (1) a specifically designed layer of transparent electrically conductive material, (2) electrical isolation of the current carrying portions of the bus grid structure from the conductive layer, (3) resistive connections of the current collecting fingers to the remainder of the bus grid structure, (4) a buffered bus grid structure or a fuse-type connection, or (5) the grid or current collecting fingers which terminate when the current reaches a predetermined amount. While these solutions effectively reduce or eliminate the effect of defects, they are not completely satisfactory for several reasons. The specifically designed layers of transparent electrically conductive material are difficult to manufacture. Further, devices having terminable or otherwise destructible current collecting fingers reduce surface area otherwise available to photogenerate current as the fingers are terminated.
A differently configured photovoltaic device and method for eliminating the problems of shorts and shunts is disclosed in U.S. Pat. No. 4,633,034 of Nath, et al, entitled "Photovoltaic Device and Method", the disclosure of which is incorporated herein by reference. That application concerns a photovoltaic device having the current collecting bus grid structure disposed above the upper, transparent conductive electrode thereof. A pattern of electrical current flow restricting material is disposed between the layer of transparent conductive material and the substrate of the device, corresponding to, and disposed beneath, at least a portion of the superjacent current collection means. The pattern restricts the flow of electrical current between the portions of the current collection means and the substrate positioned beneath the body of amorphous silicon alloy material. However, it has been determined from actual manufacturing experience that such an internal current restricting material must be aligned with the current collection means to operate effectively, which requires exacting manufacturing techniques.
Accordingly, there exists a need for a defect tolerant photovoltaic device manufactured by a process which does not require exacting manufacturing techniques such as those required to align subjacent components thereof or to prepare specifically designed layers of transparent electrically conductive material.
Additionally, it must be pointed out that as much as 10% of the surface of a photovoltaic cell is occupied by a bus grid structure. Any reduction in this area, dedicated for use by the bus grid structure, would be welcomed because radiation incident thereupon is lost. More particularly, due to "shadowing," radiation incident upon said structure cannot pass to the photoactive region of the cell for the photogeneration of electron-hole pairs therein. If the thin grid fingers could be made longer, at least some of the wide bus bars could be eliminated, thereby increasing the active area of the photovoltaic cell available to photogenerate electron-hole pairs. However, in order to be able to elongate the grid fingers, the cell must be made more tolerant of short circuit defects than is currently the case.
Disclosed herein as the innovative features of the instant invention are configurations of photovoltaic devices which exhibit a high degree of operational tolerance to defects therein, and which utilize a novel current collecting bus grid structure disposed above the transparent conductive top electrode of the photovoltaic device, which bus grid structure can be optimized to maximize the active area of a photovoltaic device.