FIG. 1 shows a portion of a semiconductor memory comprising memory cells MC arranged in a so called “virtual ground array.” The gates G of memory cells MC arranged along rows are connected by the same wordline WL. The source/drain regions SD of memory cells MC arranged along columns are connected to the same local bitlines LB, with each local bitline LB being shared by memory cells MC in two adjacent columns of the array in order to reduce chip area. Each local bitline LB is connected to a total of 512 memory cells MC while each wordline WL is connected to the gates G of 512 memory cells MC. The memory cells MC are nitride read-only memory (NROM) cells, which are non-volatile. NROM cells can store two bits per cell in a nitride layer. The ability to store two bits per cell is indicated in the schematic of each memory cell MC by two “x”. The combination of NROM cells with virtual ground arrays allows the design of memories with high storage densities.
In order to select memory cells MC for reading, each local bitline LB can be connected to one of the global bitlines GB by means of a respective switching element S1. The global bitlines GB are connected to column decoders (not shown) and the wordlines WL to row decoders (not shown). Potentials applied to the global bitline GB selected by the column decoder and to the wordline WL selected by the row decoder are then passed on to the source/drain regions SD and the gate G of the memory cell MC to be read. The state stored in the memory cell MC can be determined by sensing the current flowing through the memory cell MC in a sense amplifier.
To minimize the chip area required for the semiconductor memory, the local bitlines LB are alternately connected to top and bottom global bitlines GB, with six local bitlines LB being connectable to each global bitline GB. For ready reference, a switching unit SU comprising switching elements S1, part of a global bitline GB and parts of local bitlines LB is shown.
FIG. 2 shows the layout of a switching unit SU. Six local bitlines LB are connected by means of local bitline contacts CL to diffusion zones in a semiconductor substrate SB. Further shown is a global bitline GB which is connected to further diffusion zones in the semiconductor substrate SB by means of global bitline contacts CG. Global bitline select lines SG are arranged between each local bitline contact CL and the global bitline contact CG, which is closest to the respective local bitline contact CL.
Each combination of a local bitline contact CL, its closest global bitline contact CG and the global bitline select line SG between the two contacts forms a transistor. The gate of the transistor is connected by the global bitline select line SG and the source/drain regions of the transistor are connected by the local bitline contact CL and the global bitline contact CG, respectively. If a potential greater than the threshold potential of the transistor formed is applied to the global bitline select line SG, then the local bitline LB connected by the local bitline contact CL is connected to the global bitline GB connected by the global bitline contact CG. The transistor is thus an implementation of one of the switching elements S1 shown in FIG. 1 and, because it is used to select a bitline, is commonly known as select transistor.
The technology that is used to manufacture the semiconductor memory determines the smallest pitch, that is, the smallest distance between lines, that is possible. The size of the memory cells MC determines the pitch of the layout, and as each memory cell MC is directly connected by the respective local bitlines LB, this pitch is also the pitch for the local bitlines LB.
The local bitlines LB cannot be directly connected to the sense amplifier as they are too small and too resistive. Therefore, another metallization layer with global bitlines GB is introduced. The global bitlines GB are thick metal layers of low resistance and are used to connect the local bitlines to the sense amplifier. However, because of the larger pitch of the global bitlines GB, it is not possible to connect all of the local bitlines LB to different global bitlines GB. Rather, each of the global bitlines GB has to be shared by six local bitlines LB, so that it is not possible to control each of the local bitlines LB individually without using complicated architectures or decoding mechanisms.
FIG. 3 is used to illustrate an effect known as “neighbor effect” which occurs when a local bitline LB is shared between two memory cells connected by the same wordline WL. For the sake of clarity, only one row having three memory cells is shown. However, it is clear that the cells can be extended to the left and right as well as to the top and bottom as shown in FIG. 1. In addition to the elements already described in conjunction with FIG. 1, a sense amplifier SA connected to the first global bitline GB1 and to the second global bitline GB2, is shown.
In FIG. 3, memory cell MC is selected for reading by closing the switching elements S1 of the local bitlines LB connecting the source S and drain D of the memory cell MC. As a result, these local bitlines LB are connected to the first global bitline GB1 and the second global bitline GB2, respectively. The local bitlines LB of the neighboring memory cell NC and the further memory cell FC, which are not shared with the memory cell MC, are not connected to the global bitlines GB1 and GB2. A current IS will flow through the memory cell MC if suitable potentials VS and VD are applied to the first global bitline GB1 and to the second global bitline GB2, respectively. An erased memory cell MC allows a higher current IS to flow than a programmed cell, so that the state stored in the memory cell MC can be determined by measuring the current IS flowing through it.
Ideally, the current IM flowing into the sense amplifier SA is equal to the current IS flowing through the memory cell MC. However, if a neighboring cell NC is connected to the same local bitline LB as the memory cell MC, some of the current IS flowing through the memory cell MC will leak through the neighboring memory cell NC. This current IN will depend on the state stored in the neighboring cell MC and may flow even when no potential is applied to the gate of the neighboring cell NC. Current may, therefore, leak through all the memory cells that are connected to the same local bitline LB, so that the total leakage current maybe as large as 10 to 30% of the current IS flowing through the memory cell MC.
In FIG. 3, the current IS flowing out of the source S of the memory cell MC is to be measured. This is referred to as source-side sensing. It is also possible to measure the current ID flowing out of the drain D of the memory cell MC. This is known as drain-side sensing and the current flowing into the second global bitline GB2 is measured. If a current IF flows through the further memory cell FC leakage will also occur in drain-side sensing, adulterating the current measured.
As a consequence of the leakage due to the neighbor effect, the current IM measured in the sense amplifier SA is less than the current IS or ID flowing through the memory cell MC. If the leakage current is great enough, then the current IM measured may be decreased to such an extent that a programmed memory cell MC is mistakenly read as an erased cell. This will lead to reading failure of the memory as data cannot be correctly retrieved. There is, therefore, a need to reduce the leakage due to the neighbor effect as much as possible.
In prior art, the neighbor effect problem has been partially solved by charging or discharging the local bitlines LB and the global bitline GB before each read operation.
In source-side sensing, all bitlines, global and local, are pre-discharged to the same value as the potential VS applied to the first global bitline GB1 for reading, which typically is 0 V. As a result, the voltage across the source and drain of neighboring cells is approximately zero so that no current flows through the neighboring cells. For drain-side sensing, all the bitlines, global and local, are pre-charged to the same value as the potential VD applied to the second global bitline GB2 for reading, which typically is the supply potential. The switching elements S1 connecting the local bitlines LB of memory cells, which are not to be read, are opened after the pre-charging or pre-discharging.
However, when reading the memory cell MC, voltage drops of 100 mV to 300 mV occur, depending on the state stored in the memory cell MC, so that the neighboring cells also display a potential difference of the same magnitude across source and drain. As a result, a small leakage current will still flow. With reductions in structure sizes the resistance in the path for the current IS will increase and larger voltage drops will occur, leading to more leakage. The pre-charge/pre-discharge solution of the prior art, therefore, fails to completely solve the problems of the neighbor effect.
Besides failing to totally solve the leakage problem, the charge/discharge operations increase the power consumption of the semiconductor memory as all the global and local bitlines must be charged or discharged. A further disadvantage is that the time required for reading the memory cells is increased as the charge/discharge operation must be performed before each read operation and due to the RC time constants involved this takes a certain time.
Prior art also suggests connecting further global bitlines GB at different potentials to the neighboring cells in order to reduce the neighbor effect. However, providing biased potentials is difficult and these solutions usually require complicated interleaved bitline architectures with large increases in the chip area in order to be able to control the potentials of the local bitlines LB independently from each other. Additionally, the global bitlines GB must still be charged and discharged before each read operation, thus increasing the power consumption of the memory.