1. Field of the Invention
The present invention pertains to liquid crystal on silicon (LCOS) displays, and more particularly to improved pixel cell design for liquid crystal on silicon displays with enhanced voltage control and simplified circuit to achieve prior to display frame data loading.
2. Description of the Prior Art
Liquid crystal on silicon (LCOS) microdisplay technology is still challenged by the need to DC balance the liquid crystal material accurately while generating images that are free of flicker and while limiting the RMS voltages to the useful range of the electro-optic efficiency curve of the liquid crystal device. Most liquid crystal devices disclosed in the art fail to meet one or more of these challenges. The current LCOS devices may be thought of as being divided into three classes, based on the method of creating grayscale. Each is prone to a particular class of problems. The three classes of devices are analog drive, digital drive based on simple SRAM, and complex digital drive. All are prone to some degree to the related problems of DC offset and image flicker. The degree to which these problems manifest themselves can influence product acceptability and product longevity and therefore solutions that mitigate or eliminate these problems are worthy subjects of invention.
There are additional considerations beyond the basic problems cited above. For example, in order to achieve savings on power consumption and prolong the life of a display system, it is desirable to have a way of inverting the voltage applied to the liquid crystal pixel without having to change the state of the memory cell and without having to rely on the state of the logic memory cell in order to directly supply a voltage onto the pixel electrode. However, the conventional multiplexing devices that attempt to narrow the range of voltages that are applied to the pixel electrode on an instantaneous basis and that receive input signals directly from a memory cell fail to provide the needed flexibility because they are not capable of independently controlling the memory state that gets driven through the multiplexer to the pixel mirror. Limited by these technical difficulties, the conventional technologies of LCOS display are provide displays of higher quality only with difficulty. Specifically, the displays are often hindered by problems of image sticking and flicker due to the low DC balancing rates as will be further explained below.
Liquid crystal display (LCD) technology has progressed rapidly in recent years, and has become an increasingly common option for display systems. LCD's make up the largest portion of the flat panel display market. This market dominance is expected to continue into the future. The superior characteristics of liquid crystal displays with regard to weight, power, and geometry in image visualization, have enabled them to compete in fields historically dominated by Cathode Ray Tube (CRT) technology, such as high definition television systems, desktop computers, projection equipment, and large information boards. As the cost of LCD systems continues to fall, i.e., is predicted that they will eventually take over the market for traditional CRT applications.
The biggest disadvantages of current CRT systems are their bulky size, geometry, and weight, as well as their high power consumption. These disadvantages are clearly evident when comparing the features of CRT and LCD projection displays with similar characteristics. In general, projection display systems offer several additional advantages over CRT systems. First, projection display systems offer the possibility of using large screens for group viewing with the ability to easily change the image size and position. Second, projection display systems offer high performance, and the ability to accept image data input from a variety of devices such as computers, television broadcasts, and satellite systems. Virtually any type of video input can be projected through such a system. The application of LCDs to projection systems has further attractive features such as high brightness, high resolution, and easy maintenance. LCD front projection displays provide higher resolution and brightness than comparable CRT-based systems. In comparison with CRT's, installation of LCD projection systems is easy and their viewing angles are generally much wider. Most front projection LCD display systems are compatible with personal computers and can operate with video signals from television systems. LCD front projectors are easily adapted for applications such as home theaters.
Typically, LCD projection systems include small LCD panels, usually ranging from 0.5 to 5 inches in diagonal, a series of dichroic mirrors or filters, and a series of projection lenses to cast the images onto a screen. Commonly, three panel systems are used, where one or more dichroic mirrors divide white light coming from a light source, into the three primary colors of red, green, and blue (RGB). The dichroic minors direct each of the RGB components toward a separate LCD panel. The corresponding LCD panel modulates each of the RGB components of the light according to the input image data corresponding to that color. Output dichroic minors synthesize the modulated RGB light components and project the image onto a viewing screen.
To enhance the luminance and fill factor of the liquid crystal projection panels, reflective LCD pixels are often used. These systems, referred to as Liquid Crystal on Silicon micro-displays (LCOS), utilize a large array of image pixels to achieve a high-resolution output of the input image. Each pixel of the display includes a liquid crystal layer sandwiched between a transparent electrode and a reflective pixel electrode. Typically, the transparent electrode is common to the entire display while the reflective pixel electrode is operative to an individual image pixel. A storage element, or other memory cell, is mounted beneath the pixels and can selectively direct a voltage on the pixel electrode. By controlling the voltage difference between the common transparent electrode and each of the reflective pixel electrodes, the optical characteristics of the liquid crystal can be controlled according to the image data being supplied. The storage element can be either an analog or a digital storage element. More and more often, digital storage elements, in the form of static memory are being used for this purpose.
The liquid crystal layer rotates the polarization of light that passes through it, the extent of the polarization rotation depending on the root-mean-square (RMS) voltage that is applied across the liquid crystal layer. (The incident light on a reflective liquid crystal display thus is of one polarization and the reflected light associated with “on state” is normally of the orthogonal polarization.) The reason that the degree of polarization change depends on the RMS voltage is well known to those skilled in the art—it is the foundation of all liquid crystal displays.
Therefore, by applying varying voltages to the liquid crystal, the ability of the liquid crystal device to transmit light can be controlled. Since in a digital control application, the pixel drive voltage is either turned to dark state (off) or to light state (on), certain modulation schemes must be incorporated into the voltage control in order to achieve a desired gray scale that is between the totally on and totally off positions. It is well known that the liquid crystal will respond to the RMS voltage of the drive waveform in those instances where the liquid crystal response time is slower than the modulation waveform time. The use of pulse-width modulation (PWM) is a common way to drive these types of digital circuits. In one type of PWM, varying gray scale levels are represented by multi-bit words (i.e. a binary number) that are converted into a series of pulses. The time averaged RMS voltage corresponds to a specific voltage necessary to maintain a desired gray scale.
Various methods of pulse width modulation are known in the art. One such example is binary-weighted pulse-width-modulation, where the pulses are grouped to correspond to the bits of a binary gray scale value. The resolution of the gray scale can be improved by adding additional bits to the binary gray scale value. For example, if a four-bit word is used, the time in which a gray scale value is written to each pixel (frame time) is divided into fifteen intervals resulting in sixteen possible gray scale values (24 possible values). An 8-bit binary gray scale value would result in 255 intervals and 256 possible gray scale values (28 possible values).
Since most nematic liquid crystal materials only respond to the magnitude of an applied voltage, and not to the polarity of a voltage, a positive or negative voltage, of the same magnitude, applied across the liquid crystal material will normally result in the same optical properties (polarization) of the liquid crystal. However, the inherent physical characteristics of liquid crystal materials cause deterioration in the performance of the liquid crystal material due to an ionic migration or “drift” when a DC voltage is applied to them. A DC current will cause the contaminants always present in liquid crystal materials to drift toward one alignment surface or the other, if the same voltage polarity is continuously applied. This will result in the contaminants plating out onto the alignment layer with the result in that the liquid crystal material will begin to “stick” at an orientation and not respond fully to the drive voltages. This effect is manifested by the appearance of a ghost image of the previous image that is objectionable to viewers. Even highly purified liquid crystal materials have a certain level of ionic impurities within their composition (e.g. a negatively charged sodium ion). In order to maintain the accuracy and operability of the liquid crystal display, this phenomenon must be controlled. In order to prevent this type of “drift”, the RMS voltage applied to the liquid crystal must be modified so that alternating voltage polarities are applied to the liquid crystal. In this situation, the frame time of the PWM is divided in half. During the first half of the frame the modulation data is applied on the pixel electrode according to the predetermined voltage control scheme. During the second half of the frame time, the complement of the modulation data is applied to the pixel electrode. When the common transparent electrode is maintained at its initial voltage state, typically high, this results in a net DC voltage component of zero volts. This technique generally referred to as “DC Balancing” technique is applied to avoid the deterioration of the liquid crystal without changing the RMS voltage being applied across the liquid crystal pixel and without changing the image that is displayed through the LCD panel.
Modulation schemes that are employed to drive the liquid crystal pixel elements must therefore be able to accurately control the amount of time the pixel on and “off”, in order to achieve a desired gray scale from the pixel. The degree of rotation of light that occurs follows the RMS voltage across the liquid crystal pixel. The degree of rotation in turn affects directly the intensity of the light that is visible to the observer. In this manner modulating voltages influences the intensity perceived by an observer. In this manner gray scale differences are created. The combination of all of the pixels in a display array results in an image being displayed through the LC device. In addition to controlling the root-mean square (RMS) voltage that applied to the pixel, the polarity of the voltage must be continuously “flipped-flopped” so that deterioration of the liquid crystal is avoided. Known modulation schemes are not able to prevent liquid crystal deterioration while still being able to accurately control the RMS voltage as that applied to the liquid crystal in many projection applications where the display device is subjected to high heat loading and high light intensity. This results from a combination of electron-hole-pair generation and increased electron mobility due to the aforementioned conditions.
Other liquid crystal display system, more particularly those in flat panel TFT displays, drive the liquid crystal at slower frequencies on the order of 60 Hz. These systems create gray scale by controlling the charge placed on a storage capacitor that is connected to a transparent pixel electrode that forms part of the pixel element. Increasing or decreasing the charge on the storage capacitor is then applied to realize a gray scale effect. These devices typically refresh the storage capacitor at a rate on the order of 60 Hz to 90 Hz. In this case the liquid crystal may not be responding to the RMS voltage of the display but rather directly to the DC charge placed on the device. This is because the time constants of the liquid crystal are often actually faster than the refresh rate on the device. In this case the display is extremely sensitive to ionic contamination because the charge on the pixel electrode will bleed off quickly and the display will flicker if such ionic contamination is present. The common figure of merit that is used to describe ionic contamination for such displays is the voltage holding ratio or charge holding ratio, a high percent holding ratio indicating low contamination.
The electro-optical properties of many liquid crystal materials cause them to produce a maximum brightness at a certain RMS voltage (VSAT), and a minimum brightness at another RMS voltage (VTT). Applying an RMS voltage of VSAT results in a bright cell, or full light reflection, while applying an RMS voltage of VTT results in a dark cell, or minimal light output. Increasing the RMS voltage to a value above that of VSAT, may reduce the brightness of the cell rather than maintaining it at the full light reflection level. Likewise decreasing the RMS voltage to a value below that of VTT, will normally increase the brightness of the cell rather than maintaining it at the zero light reflection level. At RMS voltages between VSAT and VTT the percent brightness increases (or decreases, depending on the electro-optic mode) as the RMS voltage increases. The voltage range between VTT and VSAT therefore defines the useful range of the electro-optical curve for a particular liquid crystal material. It follows that RMS voltages outside of this range are not useful and will cause gray scale distortions if applied to the crystal pixels. It is therefore desirable to confine the RMS voltages applied to the pixels to this useful range between VSAT and VTT. Many known display systems drive the logic circuitry with voltages that are outside of the useful range of the liquid crystal, and applying these voltages directly onto the pixel electrode results in wasted power. For example, logic circuitry may operate at 0 and 5 volts or 0 and 3.3 volts. If the useful range of the liquid crystal material is inside of this range, more time and power must be expended to achieve RMS voltages that are within the useful range. In a system that has a useful VTT to VSAT range of 1.0 to 2.5 volts and that has logic circuitry that operates at 0 to 5 volts, in order to achieve an RMS voltage of 2.5 volts, the pixel must see an equal amount of the 0 volt state and the 5 volt state over a time frame in order to achieve an RMS voltage of 2.5 volts. It would be much more efficient if the logic circuitry operated at the VSAT and VTT levels, rather than at levels outside of the VSAT to VTT range. This would make the time averaging simpler and faster and less power would be required to drive the same systems.
For these reasons, it is desirable to confine the RMS voltages to the useful range of the electro-optical response curve of the liquid crystal material. Furthermore, since the technique of rewriting data to achieve DC balance is used in most of the conventional analog driven TFT panels and micro-displays, it is also desirable to implement a D-C balancing technique for alternating the voltage applied on the liquid crystal, without having to continuously write new data onto the storage element. One of the techniques of accomplishing this it by inverting the voltage applied to the liquid crystal pixel without having to change the state of the memory cell and without having to rely on the state of the logic memory cell in order to direct a voltage onto the pixel electrode.
Conventional multiplexing devices are employed in attempt to narrow the range of voltages that are applied to the pixel electrode on an instantaneous basis and that receive input signals directly from a memory cell. But since the entire panel is written with voltage scales that alternate between a higher voltage range and a lower voltage range, conventional multiplexing devices fail to provide the needed flexibility because they are not capable of independently controlling the memory state that gets driven through the multiplexer to the pixel mirror. For example, in “Miniature FLC/CMOS Color Sequential Display Systems”, SID Digest, 1997, Section 21.3, Handschy et al describe a backplane based on an SRAM device with full static control logic and row and column drivers. In the particular instance the pixel mirror voltage is determined solely by the logic state of the SRAM circuit underlying it. Thus the pixel may receive 0 volts or 5 volts, depending on its logic state. The common electrode value is set at 2.5 volts. No provision is described for decoupling DC balance from the writing of data and the device appears to be a simple SRAM device modified by the addition of pixel mirrors and post processing to make the device part of a liquid crystal cell. A further description, of this is found in PCT Publication WO 01/16928. Xue, et al, “Reduction of Effects Caused by Imbalanced Driving of Liquid Crystal Cells.” While simple, the device does not enable the enhanced performance that comprises part of the present invention.
Another example of display system is disclosed in U.S. Pat. No. 6,005,558. A display system includes a memory element coupled to a multiplexer. Depending on the state of the memory element, the multiplexer directs one of two predetermined voltages onto a pixel electrode. The multiplexer is situated externally to the memory cell and is controlled by external circuitry to operate in conjunction with DC balance and data load operations. In the disclosed invention, operation of the multiplexer external to the cell requires that the voltages delivered via the rails to the cell be modulated to provide DC balance. This adds substantially to the complexity of the device because the modulated voltage must be correct in all respects as these same voltages are used to drive the pixel mirrors and thus achieve DC balance. Design of a line that cam propagate a number of different voltages across long lines that must accurate in all cases is a significant design constraint. Furthermore, the disclosed invention requires that all elements be globally addressed to function. All these technical difficulties limit the effectiveness of the above inventions in providing practical solutions to the above-mentioned limitations.
Furthermore, since the conventional systems utilize the state of the memory cell as a control signal to direct a voltage onto the pixel mirror, there is no independent means for selecting and directing a narrower range of voltages to be consistent with the electro-optical response curve, onto the pixel electrode. It often leads to further difficulties and limitations. Since the gray scale is symmetrical within those two voltage ranges on either side of the voltage of the common plain, there is a transition phase during data load where both upper and lower voltage ranges are present on the display at the same time. The duration of this period is perhaps 200 to 300 microseconds. Such approach places several limitations on the device: First, the common plane (VCOM) must be a fixed value because during the transition time data is present on the display in both upper and lower voltage ranges. This in turn means that the display must have a voltage authority range sufficient to permit the writing of analog data in both the upper and lower ranges. While occasionally this may be done within normal voltages, it is more often the case that the developer of the design must use special silicon processing techniques such as those associated with flash memories or with EEPROM technology. In the cases when the EEPROM is used, the resulting parts may have a 10–15 volt operating range so that Vcom can be set at the 4.5 to 6.5 volt range. This in turn provides a reasonable range of authority for symmetrical driving of the liquid crystal. In the former case, a normal silicon processes may be applied, the best CMOS processes can reach ˜6 volts, which dictates a VCOM of approximately 2.9 volts. However, with this voltage range, there are very few liquid crystal materials available to satisfy the requirement of the panel. The best design, manufacturing and yield economics are associated with standard CMOS designs rather than the high voltage processes. For these reasons, manufacturing LCOS display panels and other LCD devices often results in a lower yields than average yield rate. Thus, the production costs are increased when non-standard CMOS processes have to be carried out for manufacturing the LCOS device in order to satisfy these operational conditions when suitable liquid crystal materials are used.
Furthermore the technique of applying a DC balance switching rate of once per data load in the conventional micro-displays further creates a situation where the ion migrating within the liquid crystal material begin to plate out toward the end of the data frame at a lower DC balancing rate. Eventually such displays begin to show more “image sticking.” where a ghost image reflecting older data remains in a display after new (and different) data is written to the display. It is objectionable and in fact is a specification item for TFT displays that the old data must dissipate within a specified short period. With a low DC balancing rate, a LCOS display often generates a second objectionable flicker artifact due to slow data rates caused by the existence of DC offset mechanisms. The manifestation is that VCOM can no longer be set to a point half way between the two voltage drive ranges but rather must be raise or lowered from that point to achieve a flicker-free image. This second problem creates a dilemma between solving flicker and eliminating image sticking. Further details are disclosed in a patented disclosure of U.S. Pat. No. 6,424,330 to Johnson, entitled “Electro-optic Display Device with DC Offset Correction” and the disclosures in that Patent is hereby incorporated by reference in this Application.
A co-pending patent application Ser. No. 10/329,645 filed by an inventor of this Application discloses a pixel display configuration by providing a voltage controller in each pixel control circuit for controlling the voltage inputted to the pixel electrodes. The controller includes a function of multiplexing the voltage input to the pixel electrodes and also a bit buffering and decoupling function to decouple and flexible change the input voltage level to the pixel electrodes. The rate of DC balancing can be increased to one KHz and higher to mitigate the possibility of DC offset effects and the image sticking problems caused by slow DC balancing rates. The co-pending Application further discloses an enabling technology for switching from one DC balance state to another without rewriting the data onto the panels. Therefore, the difficulties of applying a high voltage CMOS designs are resolved. Standard CMOS technologies can be applied to manufacture the storage and control panel for the LCOS displays with lower production cost and higher yields. The DC-balancing controller in the co-pending Application is implemented with a ten-transistor (10-T) configuration consisted of two P-MOS transistors. While the controller can be more conveniently implemented, it does have a technical limitation due to a constraint that the P-MOS transistors are not effective in pulling down the voltage of the pixel mirror. The lower voltage limit V0 of the controller is set to 1.0 to 1.3 volts above the semiconductor ground voltage VSS depending on the design details of the circuits. The limitation occurs due to the fact that a P-MOS transistor is strong in pulling the voltage up to Vdd while weak in pulling down the voltage to VSS. The technical limitation of not able to operate the pixel control voltage closer to VSS thus reduces the flexibility of material selections of the liquid crystal materials for the LCOS image displays. In many cases, this more limited operation voltage range further reduces the response time of the liquid crystal. The image contrast is also adversely affected due to the reduced range of voltages for dark stage selection.
In addition to the above limitations, for a microdisplay system, in order to achieve a global or time-synchronously update of the image, it is required to write a frame of data to the buffer before the beginning of the display of that frame of data. The timing and sequences of loading the display data into the buffer would allow the image timing management to work as a set of frames rather than with a time skew between rows. Usually, it is optimal to allow the loading of the entire frame of data plus some small margin before the display of that frame to take into account of the minor timing discrepancies. For the purpose of achieving these goals, several conventional circuit designs employ a second stage device that can be implemented as capacitor subject to bleed off of charge during the display time or some sorts of secondary storage device that includes many transistors, e.g. 6T storage device. The secondary stage circuits add to the complexity and density of the display system and increase the probability of failure in the CMOS manufacturing processes. The added circuits further increases the size and volume of the display systems thus requiring a larger minimum circuit size and also increase the power consumptions and further increase the burdens of heat dissipation. Conventional technologies do not provide a effective solution to this limitation.
For these reasons, there is still need in the art of LCOS display to provide improved system with simplified circuit configuration without requiring the second stage circuit to achieve the loading to the data into the buffer before the display of the data. It is further desirable that the circuit can be driven either in a global update mode in a regular load mode that that the circuit designs can be implemented in more than one types of microdisplay systems.