An integrated circuit comprises a substrate on the surface of which and/or inside of which are produced electronic components to form one or more electronic chips.
These integrated circuits are produced by using collective fabrication methods often called “microelectronics” methods. For example, these methods implement a machining of the substrate or layer by photolithography and etching (for example DRIE (Deep Reactive Ion Etching)) and/or a structuring by epitaxial growth and deposition of conductive material. By virtue of these microelectronics methods, the fabricated electronic components are small. In many cases, these components have dimensions of a micrometric or nanometric order. The dimension of micrometric or nanometric order is generally less than 10 μm and, typically, less than 1 μm.
The substrate can be homogeneous, such as a block. Or, the substrate can be heterogeneous, such as a plurality of stacked thin layers. In this case, the electronic components are produced on the surface and/or inside this substrate and the electronic chip or chips are arranged at least partly on the surface of this substrate.
The substrate can also be a “multilayer” substrate. Such a substrate is made of up of a stack of substrates assembled one on top of the other. The stacked substrates can themselves be homogeneous or heterogeneous. Here, to distinguish this substrate from the stacked substrates of which it is composed, the stacked substrates are called “layers.” In the case of a multilayer substrate, the stacked layers are not thin layers. In particular, each stacked layer exhibits a sufficient rigidity in itself to be handled without being bonded onto another substrate. To this end, typically, the stacked layers have a thickness at least 10 or 100 times greater than the thickness of the thin layers. For example, the thin layers have a thickness of less than 1 μm or 0.1 μm, whereas the stacked layers have a thickness greater than 5 or 10 or 100 μm. Several of these layers can include electronic components on the level of the assembly interface between two successive layers of the substrate. These electronic components produced on the surface of the stacked layers constitute one or more electronic chips. The integrated circuit then comprises a stack of electronic chips, stacked one on top of the other. These integrated circuits in which a plurality of electronic chips are stacked one on top of the other are often called “3D integrated circuits.”
One of the main limitations on performance of integrated circuits is the quantity of heat that they produce and which has to be removed. This problem is even greater in 3D integrated circuits.
In order to evaluate, as correctly as possible, the heat from an integrated circuit, it is useful to know the places inside this integrated circuit where the heat is concentrated and reaches a maximum. These places are called “hot spots.” It is also important to know the diffusion from these hot spots inside the circuit.
One of the difficulties commonly encountered is that of knowing both the positions of these hot spots and the diffusion from these hot spots. This difficulty is exacerbated when the hots spots are inside the substrate, especially if they are more than 5 μm away from an outer face of the substrate.
It is known to measure temperature on the surface of the substrate, but now how to directly measure temperature inside the substrate. Thus, currently, to estimate the temperature of a hot spot situated inside the substrate, simulation software is used. Such software is based on mathematical models that make it possible to predict the flow of the heat fluxes inside the substrate. To improve the estimation of this software, the latter can also use, as input data, the temperatures measured on the surface of the substrate. However, these models can prove imprecise, notably in estimating the dynamic aspects of certain thermal phenomena.
The prior art is also known from: FR2878077A1, DE102010029526A1 and US2010/219525A1.