In memory circuits utilizing variable threshold devices, such as MNOS transitors, the threshold value at which the transistor conducts may be controlled to have a low threshold level for supplying a logic or binary "one"; and to have a high threshold level fro supplying a logic or binary "zero", for example. In such circuits, it is desirable to have a short write cycle time to enable fast writing of data into the memory cell as well as reading such data out. In a prior art MNOS memory circuit, data may be written into the memory cell over and over. In other words, the memory cell may be written as a binary one for a number of times in a row before a binary zero is written. This causes the variable threshold transistor to shift its threshold between high and low to the maximum extent during the write cycle which saturates the device to a condition. which may be referred to as the saturated threshold state. Thus, when it is desired to write a binary level of the opposite state into the memory cell, the write pulse must have adequate polarizing voltage and time to shift the threshold voltage of the transistor from the previous saturated state. To speed up the time of writing a binary level or shifting the voltage in a variable threshold transistor, such as an MNOS transistor, the voltage or electric field across the gate insulator of the device is increased by increasing the polarization voltage. Unfortunately, these high electric fields across the gate insulator of the MNOS device during the write cycle serve to accelerate the undesirable endurance phenomena creating a smaller threshold voltage and decreased retention time of the memory state.
In an attempt to prevent saturation of the transistor, one typical prior art circuit operated such that the transistor was cleared prior to each writing of the transistor to a high threshold state. Such clearing consisted of applying a voltage to obtain a low threshold state prior to each writing of the data, regardless of the data already in the memory cell. This was followed by applying the voltage for the high threshold state to selected memory cells. Such a system, which required the application of a write voltage first for logical zeroes, and then for logical ones, required more than twice the minimum write time.
In order to overcome the disadvantages of operation created by the saturated threshold state without increasing the polarization voltage or without requiring that each cell be operated to its low threshold state prior to selectively operating the memory cells to the high threshold state during each write cycle, a system and method described in U.S. Pat. No. 4,090,258, dated May 16, 1978 and issued to J. R. Cricchi, one of the inventors of the present application, is proposed. This system describes a variable threshold MNOS non-volatile memory system and method that utilizes a pair of MNOS transistors for each memory cell. For a binary one, one transistor is operated to its high threshold state, while the other transistor is simultaneously operated to its low threshold state. For a binary zero, the one transistor is operated to its low threshold state while the other transistor is operated to its high threshold state. Prior to each write cycle of the circuit, a read-compare operation is performed, which compares the data to be written with the data actually stored in the memory cell. In the event that the data stored in the memory cell is the same as the data to be written into that memory cell, the write portion of the cycle is inhibited. This inhibiting of the rewriting of the same data into the memory cell prevents the transistor from being operated to its saturation threshold state without the necessity of clearing the transistor prior to the writing in of each new data. Further, in such system the fact that one of the transistors of the cell is operated to its low threshold state and the other to its high threshold state increases the "window" to minimize the errors when reading out the data stored in the memory cell.
However, MNOS memories that have fast write characteristics tend to have short retention periods. Although the proposed system provides for a large window, it is possible that certain memory cell remain in their binary one or binary zero state during extended operations that the detection window would decrease; that is, the high threshold state of one of the transistors of the memory cell would decrease and the low threshold state of the other transistor of the memory cell would increase. Although such a system provided accuracy of operation down to a one-half volt difference between the two transistors of a memory cell, it is desirable that the transistors be refreshed periodically without driving the transistors to their saturated threshold state. Also, it is desirable that the refreshing of the memory cells be controlled internal to the memory array rather than by external programming.