Periodic signals are used in a variety of electronic devices. One type of periodic signal are clock signals that can be used to establish the timing of a signal or the timing at which an operation is performed on a signal. For example, data signals are typically coupled to and from memory, such as synchronous dynamic random access memory (“SDRAM”), in synchronism with a clock or data strobe signal. More specifically, read data signals are typically coupled from a memory in synchronism with a read data strobe signal. The read data strobe signal typically has the same phase as the read data signals, and it is normally generated by the same memory device that is outputting the read data signals. Write data signals are typically latched into a memory device in synchronism with a write data strobe signal. The write data strobe signal typically has a phase relative to the write data signals so that a write data strobe signal transitions during a “data eye” occurring at the center of the period in which the write data signals are valid.
Internal clock signals generated in electronic devices, for example, memory devices or memory controllers, are often synchronized or have some other controlled phase relationships relative to external or internal clock signals. For example, with reference to a memory, a clock signal used for both latching write data and outputting read data may be generated in the memory to which the data are being written. The clock signal is typically generated in the memory device from an internal clock signal that is also derived from the system clock signal.
Various techniques can be used to generate a clock signals or read/write data strobe signal. FIG. 1 illustrates a conventional clock circuit 100 providing an output clock signal ICLK to a clock tree circuit 140. When enabled by an active CkEn signal, the clock tree circuit 140 distributes the ICLK signal as a DCLK signal to various circuitry that operate according to the DCLK signal. In FIG. 1, the DCLK signal is provided to data output circuitry 150. In particular, the DCLK signal clocks a data register 154 which provides data to an output buffer 158 to generate a data output signal DQ. The clock circuit 100 generates an ICLK signal that when delayed through the clock tree circuit 140 results in a DCLK signal that is synchronized with a reference clock signal RCLK (and its complement RCLK/). The clock generator includes a delay-locked loop (DLL) 102 and a duty cycle correction (DCC) circuit and output buffer 116. The DLL includes an input buffer 104 that provides a buffered reference clock CLKS to a DLL delay line 108. The delayed buffered reference clock signal is output to the DCC and output buffer 116 for correction of the duty cycle and buffering before being output as the ICLK signal. The ICLK signal is also provided to a model delay 120. The model delay 120 models propagation delay through the output buffer and the clock tree circuit 140. A feedback clock signal FBCLK is output from the model delay 120 and provided through model delay 124 to a phase detector circuit 128 as the DLLFB signal. The model delay 124 models the propagation delay of the input buffer 104. The phase detector circuit 128 detects a phase difference between the CLKS and DLLFB signals. A phase difference signal indicative of the phase difference between the CLKS and DLLFB signals is provided to shift logic 132 that generates a control signal based on the phase difference signal to adjust the delay of the DLL delay line 108. The delay is increased or decreased in order to synchronize the CLKS and DLLFB signals. When synchronized, the clock circuit 100 is said to be “locked.”
Although the timing of the ICLK signal relative to the RCLK (and RCLK/signal) is set by the clock circuit 100 so that the DQ signal output by the clock tree circuit 140 is synchronized with the RCLK signal, there may be a “jitter” in the DQ signal. The clock jitter may be caused by the resolution of adjustment in the DLL delay line 108, and also the resolution of the phase detection by the phase detector circuit 128. Clock jitter may also be caused by varying operating conditions, such as varying power, voltage, and temperature. For example, the ICLK signal may need to be driven over a relatively long signal line to be input in the clock tree circuit 140. Although the propagation delay to the clock tree circuit 140 and through the clock tree circuit 140 is modeled by the feedback model delay 120, the actual propagation delay due to the signal line may vary under changing operating conditions, thus, resulting in clock jitter.