1. Field
This application relates to an interface between a processor memory controller and a non-volatile memory controller and more particular relates to a direct interface between a memory controller and a non-volatile memory controller using a command protocol.
2. Description of the Related Art
In typical computing devices, main memory includes volatile memory such as dynamic random access memory (“DRAM”) and static random access memory (“SRAM”). A processor typically communicates with the main memory over a wire interface using a low-level wire protocol such as the Joint Electron Devices Engineering Council (“JEDEC”) protocol, the industry standard for processor—DRAM interfaces. The JEDEC standard assumes that physically addressable media is synchronous, heavily parallel, reliable and implements a design structure that is known to a processor memory controller. Consequently, JEDEC uses a series of distinct commands that cause the DRAM devices to execute known operations in hardware.
Recent significant development of flash-based devices enable use of non-volatile memory as a main memory replacement. However, typical non-volatile main memory solutions continue to provide communication between the processor and the non-volatile main memory using a low-level wire protocol such as JEDEC.