Micro-feature devices have a large number of very small features that are typically formed in and/or on wafers or other types of workpieces by selectively removing material from the wafer and/or depositing material onto the wafer. For example, features are often formed by (a) constructing a pattern in a layer of resist to form a mask on the wafer, (b) etching holes and/or trenches in the wafer through openings in the mask, and (c) filling the resulting features with dielectric, semiconductive, and/or conductive materials. Photolithographic processes are generally used to transfer the intricate patterns of the features onto discrete areas of the layer of resist.
A typical photolithographic process includes depositing a layer of radiation-sensitive photoresist material on the wafer, positioning a reticle having a mask pattern over a selected area of the photoresist, and then passing an imaging radiation through the reticle to expose the photoresist in the configuration of the mask pattern. A developer, such as an aqueous base or a solvent, is used to remove either the irradiated areas or the masked areas of the photoresist. For example, when the radiation changes the photoresist from being generally soluble in the developer to generally insoluble, then the developer removes the masked portions of the resist layer. Alternatively, when the radiation changes a photoresist from being generally insoluble in the developer to be generally soluble, then the developer removes the exposed portions of the photoresist.
Existing lithography processes are capable of creating very complex patterns of extremely small features across the surface of a wafer to form the trenches, vias, holes, implant regions, conductive lines, gates, and other features on a wafer. In a typical application, a lithographic tool transfers the pattern in the reticle to the workpiece by scanning or stepping the pattern across precise areas of the workpiece. As microelectronic devices become more complex, there is a drive to continually decrease the size of the individual features and increase the density of the features across the wafer. This significantly increases the complexity of lithographic processing because it is increasingly difficult to accurately focus the pattern onto the face of the wafer. In many applications, the depth of field for focusing the pattern on the wafer is so small that slight variations in the wafer surface and/or the reticle can adversely affect the quality of the pattern transferred to the wafer.
One conventional process to compensate for non-uniformities in reticles is to measure the flatness of the reticles in the photolithography tool before processing the wafers. The topography of the reticles is conventionally measured by detecting light that passes through alignment marks in a perimeter region outside of the pattern area of the reticle. Based on the topographical data of the alignment marks in the perimeter region around the pattern area of the reticle, the topography of the pattern area is estimated. Conventional lithographic tools are then adjusted by tilting the wafer stage and/or adjusting the optics to compensate for variances in the estimated pattern area of the reticle (e.g., the estimated curvature of the reticle).
One problem with such conventional processes is that the topography in the pattern area of the reticle is estimated based on the alignment marks in the perimeter region of the reticle. As the feature sizes decrease, this may not provide sufficiently accurate data to compensate for non-uniformities in the pattern area. Moreover, lithographic tools are extremely expensive and it is very costly to use lithographic tools for measuring the non-uniformities in the reticle. Such use of lithographic tools is expected to reduce the throughput of processing wafers because the time period for qualifying the reticles is effectively downtime for processing wafers. Therefore, there exists a need to improve conventional photolithographic processes.