1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a MOS transistor based on high breakdown voltage specs and a manufacturing method thereof.
2. Description of the Related Art
A conventional high voltage MOS transistor has a structure wherein low-density diffused layers overlap with a gate electrode underneath the gate electrode to relax an electric field under the gate electrode to thereby suppress the occurrence of hot carriers. A method of manufacturing the conventional high voltage MOS transistor will be explained below with an N type MOS transistor as an example with reference to a process sectional views of FIGS. 3(a)–3(c).
An insulating film 302 such as an oxide film is formed on a P type semiconductor substrate 301 by known oxidation or a known CVD technique. Next, a resist pattern 303 is formed thereon by a known photolithography technique. Thereafter, an N type impurity such as phosphorus ions are implanted at a dose of 6.0 E+12 cm−2 by a known ion implantation technique. Next, the N type impurity is activated by a known diffusion technique to form N type low-density diffused layers 304 which serve as layers for relaxing source and drain electric fields in the MOS transistor (see FIG. 3(a)).
Next, the resist pattern 303 is removed and a polysilicon film is deposited on the insulating film 302 by the known CVD technique. Afterwards, the polysilicon film is patterned by using a known photolithography and etching technique to form a gate electrode 305 (see FIG. 3(b)). Incidentally, at this time, the gate electrode 305 is formed in a structure in which the low-density diffused layers overlap with the gate electrode under the gate electrode, in such a manner that the gate electrode 305 covers parts of the N type low-density diffused layers 304 through the insulating film 302 by about 1.5 μm.
Next, a resist pattern is formed by the known photolithography technique. Thereafter, an N type impurity such as As is implanted at a dose of 1.0 E+15 cm−2 by the known ion implantation technique to form N type high-density diffused layers 306 for drawing source and drain electrodes of the MOS transistor (see FIG. 3(c)). Incidentally, at this time, the N type high-density diffused layers 306 are formed away from the gate electrode 305.
Subsequently, a high voltage MOS transistor having a structure in which low-density diffused layers overlap with a gate electrode underneath the gate electrode, is formed via contact formation and wiring formation. Incidentally, both the contact formation and wiring formation are done using a known technique and are not shown in the figure.
In order to improve breakdown voltage characteristics of the MOS transistor, Japanese Unexamined Patent Publication No. Hei 9(1997)-205205 cited as a patent document describes a method of forming high density layers for drawing or withdrawing source and drain electrodes at arbitrary and uniform positions, whereas Japanese Unexamined Patent Publication No. 2002-289845 cited as a patent document describes a method of forming low and high density layers in desired regions on a self-alignment basis.
However, the above-described patent documents make no mention of the fact that the gate electrode is caused to overlap with the low density layers in a desired length. The method of manufacturing the high voltage MOS transistor having such a structure that the low-density diffused layers for field relaxation and the gate electrode both formed as described in the prior art have overlapped, was accompanied by the problem that there was a need to form the gate electrode after the formation of the low-density diffused layers, and when the photolithography technique was used, there was a need to determine the dimensions of the portions where the low-density diffused layers and the gate electrode overlapped in consideration of allowances for alignment between pattering for forming the low-density diffused layers and patterning for forming the gate electrode, thereby causing interference with device's miniaturization.