1. Field of the Invention
This invention relates generally to memory design. Particularly, this invention relates to a new cell for implementation in the Static Random-Access Memory (SRAM) thus taking advantage of the base current reversal phenomenon in a Complementary Metal Oxide Semiconductor (CMOS) for the construction of compatible high gain gated lateral Bipolar Junction Transistor (BJT).
2. Description of the Prior Art
The conventional CMOS SRAM cell essentially consists of a pair of cross-coupled inverters as the storage flip-flop or latch, and a pair of pass transistors as the access devices for data transfer into and out of the cell. (A large number of different cell configurations are cited in the literature, e.g.,B. Prince, Semiconductor Memories--A Handbook of Design, Manufacture, and Application, 2nd ed., New York: John Wiley & Sons, Inc., 1991). Thus, a total of six Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or four MOSFETs plus two very high resistance load devices are required for implementing a conventional CMOS SRAM cell. However, to achieve high packing density, it is the usual practice to reduce the number of the devices needed for realizing a CMOS SRAM cell or the number of the devices for performing the Write/Read operation. Especially for the case of very high resistance load devices, increased process complexity, extra masks, and high fabrication cost are required for forming the undoped polysilicon layers or the Thin Film Transistor (TFT) on the oxide and thus saving the chip area; however, the corresponding product yield is not high. Therefore, more efforts are needed to further reduce the areas occupied by the chip while improving the production yield.
The structures of the conventional SRAM are shown in FIGS. 1 and 2. FIG. 1 shows a circuit schematic of a conventional SRAM cell configuration. The cell comprises a pair of cross-coupled inverters, p-MOSFET 11 and n-MOSFET 13, and p-MOSFET 16 and n-MOSFET 14, as the storage flip-flop or latch. In each inverter the gates of p-MOSFET and n-MOSFET are tied together and connected to the output of another inverter. The output of each inverter are the drains of p-MOSFET and n-MOSFET which are tied together. The conventional cell employs a pair of pass transistors, n-MOSFETs 12 and 15, as the access devices for data transfer into and out of the cell. Two column lines DATA and DATA and two row select lines W and W are depicted. This conventional cell requires 6 MOSFETs.
FIG. 2 shows a circuit schematic of a conventional CMOS cell using undoped polysilicon layer or thin-film transistor for providing very high resistance loads 20. FIG. 2 is very similar to FIG. 1 except for the type of the load. This cell requires complex processes and the resulting yield is low. This conventional cell requires four MOSFETs formed on the silicon plus two undoped polysilicon layers or TFTs formed on the oxide.
A Bipolar-CMOS (BICMOS) process has recently been introduced to achieve the above-mentioned object (refer to the paper: K. Sakui, et al. "A new static memory cell based on reverse base current (RBC) effect of bipolar transistor," IEEE IEDM Tech. Dig., pp. 44-47, December 1988). In this BICMOS process, only two devices are needed for a SRAM cell: one vertical bipolar transistor and one MOSFET as a pass device. However, extra processing steps and increased masks are required along with special deep isolation techniques, resulting in high fabrication cost and process complexity. Also, the yield of the SRAM products utilizing such complex BICMOS process is usually low compared with the existing standard CMOS process. Therefore, the SRAM products fabricated in a complex BICMOS process cannot provide sufficient competition to the conventional CMOS SRAM products.
Very recently, a new phenomenon of base current reversal has been observed in a CMOS compatible high gain gated lateral bipolar transistor (refer to the paper: Tzuen-Hsi Huang and Ming-Jer Chen, "Base current reversal phenomenon in a CMOS compatible high gain n-p-n gated lateral bipolar transistor," IEEE Trans. Electron Devices, Vol. 42, No. 2, pp.321-327, February 1995). This new phenomenon has been extensively investigated and has been found to have many applications. This invention employs this new phenomenon in the existing standard CMOS process for realizing a new SRAM cell constructed by only two MOSFETs. This new SRAM also features only one-sided peripheral circuitry for Read/Write action. Therefore, this invention can efficiently save the chip area with high yield since it is fully compatible with the existing low-cost standard CMOS process.