(1) Field of the Invention
The present invention relates to a method for making a plasma-enhanced chemical vapor deposited (PECVD) silicon oxide/silicon nitride multilayer (stacked layer) as a passivation layer on semiconductor integrated circuits, and more particularly relates to a method for making an insulating/passivating layer over interconnecting metal lines on multilevel interconnections for integrated circuits.
(2) Description of the Prior Art
Multilevels of metal interconnections are used on Ultra Large Scale Integration (ULSI) integrated circuits to wire-up the discrete semiconductor devices on the semi-conductor chips. The different levels of interconnections are separated by layers of insulating material, such as PECVD silicon oxide (SiO.sub.2) and silicon nitride (Si.sub.3 N.sub.4) layers. The silicon nitride also serves as a barrier layer or passivation layer to prevent contamination from moisture and other corrosive chemicals, and to prevent ionic contamination from light alkaline metal ions, such as sodium (Na) and potassium (K) which can degrade the electrical characteristics of the underlying semiconductor devices built in and on the substrate. Via holes etched in the interposed insulating/passivation layers are used to connect one level of metal to the next. Typically the insulation and passivation layers require low-temperature deposition processing (&lt;400.degree. C.) because the metal lines which are usually formed from Al/Cu alloys have a low melting temperature (about 660.degree. C.).
Unfortunately, as the metal lines that form the interconnections are made closer together to satisfy the higher packing density for ULSI integrated circuits, the aspect ratio (the width of the spacings between metal lines to the metal thickness) increases. This can result in the formation of voids (keyholes) in the nonconformal insulating or passivation layer between the metal lines when the passivation is deposited next. Also because the silicon nitride has a higher stress than the silicon oxide, cracking of the silicon nitride layer is prevalent at the bottom corners in the recesses between the metal lines. The voids are particularly prevalent when the passivation layer, usually a silicon nitride, is deposited at low temperatures, such as by PECVD or high-density plasma CVD (HDP-CVD) that results in the nonconformal layer.
The void and cracking problems are best understood by referring to the prior art in FIG. 1, which is a schematic cross-sectional view of a portion of a partially completed semiconductor substrate 18, such as a silicon substrate with an insulating layer 19 on the surface. The underlying semiconductor devices, such as field effect transistors (FETs) and electrical interconnections are not depicted to simplify the drawing and discussion. Two closely spaced interconnecting metal lines 20 are shown on which is deposited first a thin PECVD silicon oxide layer 22 that acts as a stress-release layer for the Si.sub.3 N.sub.4 layer 24 which is deposited next. As is depicted in FIG. 1, the deposition flux of the deposited Si.sub.3 N.sub.4 layer is higher at the top corners of the closely spaced metal lines than in the recess between them. This results in the formation of voids 30 having a keyhole shape. If the Si.sub.3 N.sub.4 is deposited to a thickness 24', as depicted by the broken line 24', then the voids can be partially closed. During the next photo-resist masking step to form the via holes in the passivation layer to the metal lines elsewhere on the substrate 18 (not shown), residual photoresist can be trapped in the voids 30 in the Si.sub.3 N.sub.4 layer 24. The incomplete removal of the residual photoresist then results in contamination and corrosion of the subsequent metal layer when the trapped photoresist outgases during the subsequent metal or alloy deposition step. Concurrently, stress-induced cracks 32 are formed in the silicon nitride layer 24 at the bottom edges of the metal lines 20, as is also depicted in FIG. 1. This is a particularly serious problem for 0.38 micrometer DRAM devices (0.38 um FET channel lengths) when the minimum spacings between the metal lines at the second metal level (M2) of interconnections are less than 0.575 um. The passivation layer typically fails the pinhole test when the total thickness of the silicon oxide layer 22 and the silicon nitride layer 24 is less than 8000 Angstroms, but thicker passivation layers can present a keyhole problem.
One method for depositing a passivation layer is described by Lindenfelser in U.S. Pat. No. 4,692,786, in which a three-layer sandwich passivation coating is deposited directly on the silicon substrate to prevent ion contamination during the fabrication of bipolar transistors, but he does not address the above keyhole or Si.sub.3 N.sub.4 cracking problems. Ang et al., U.S. Pat. No. 4,707,721, describe a method for making a passivated dual-gate system using a titanium nitride which is a good electrical conductor, but do not address the keyhole or cracking problem in a silicon nitride passivation layer.
There is still a strong need in the semiconductor industry to provide a silicon nitride passivation layer over closely spaced metal lines that eliminates the above keyholes and cracking problems on future ULSI and VLSI circuits.