1. Field of the Invention
The present invention relates to an addressing unit, and more particularly to an addressing unit suitable for a storage device which reads and writes information by using an X address (row address) and a Y address (column address).
2. Description of the Related Art
Various storage devices for storing information have been proposed. Among them, a storage device which reads and writes information by using the X address and the Y address has been known. FIG. 4 shows a prior art example of an addressing unit which used the X address and the Y address.
FIG. 4 shows an addressing unit used in a storage device represented by a DRAM. Namely, it shows a so-called address multiplex type addressing unit in which an address signal comprising multiplexed X address and Y address is inputted from an address input terminal common to the row and the column in a plurality of times in a time division fashion in order to reduce the number of address input terminals to improve a packaging density on a printed circuit board.
In FIG. 4, numeral 41 denotes a buffer which translates an address signal ad0 inputted from an address input terminal 8 to an internal X address signal ad1 to be supplied to an X decoder 6 and an internal Y address signal ad2 to be supplied to a Y decoder 7. By translation process, the address signal ad0 inputted from the address input terminal 8 is delayed by a certain period of time.
Numeral 2 denotes an internal control signal generation circuit which generates a control signal (X latch signal) .phi.X0 for taking the X address and a control signal (Y latch signal) .phi.Y0 for taking the Y address.
When the X address is to be taken, the internal control signal generation circuit 2 supplies the X latch signal .phi.X0 to an X address latch 43. Thus, the internal X address signal ad1 outputted from the buffer 41 is latched in the X address latch 43. When the Y address is to be taken, the Y latch signal .phi.Y0 is supplied to a Y address latch 44. Thus, the internal Y address signal ad2 outputted from the buffer 41 is latched in the Y address latch 44.
Numeral 45 denotes an X pre-decoder which temporarily decodes the internal X address signal ad1 latched in the X address latch 43, two bits at a time, before it is input to the X decoder. Namely, it decodes the input n-bit address signal to a signal which identifies 2.sup.n address lines. For example, when the internal X address signal ad1 latched in the X address latch 43 is a 3-bit signal, the X pre-decoder 45 outputs an X pre-decoded signal ad3 for identifying eight addresses.
Numeral 46 denotes a Y pre-decoder which temporarily decodes the internal address signal ad2 latched in the Y address latch 44, two bits at a time, before it is input to the Y decoder 7. For example, when the internal T address signal ad2 latched in the Y address latch 44 is a 3-bit signal, a Y pre-decoded signal ad4 which identifies eight addresses is outputted from the Y pre-decoder 46.
The X decoder 6 generates and outputs an X select signal adX for selecting a word line of a memory cell (not shown) based on the X pre-decoded signal ad3 supplied from the X pre-decoder 45. The Y decoder 7 generates and outputs a Y select signal adY for selecting a bit line of the memory cell (not shown) based on the Y pre-decoded signal ad4 supplied from the Y pre-decoder 46.
In the case where the pre-decoders 45 and 46 are provided in front of the decoders 6 and 7, the number of transistors of the decoders 6 and 7 can be reduced and the process may be conducted faster in comparison with the case where the internal address signals ad1 and ad2 generated by the buffer 41 are directly inputted to the decoders 6 and 7.
FIG. 5 shows another prior art example of the addressing unit which uses the X address and the Y address. FIG. 5 shows a synchronous addressing unit. The blocks, which are identical to those of the addressing unit as shown in FIG. 4 are designated by the identical numerals. Namely, in the addressing unit in FIG. 5, a burst counter 51 is used instead of the Y address latch 44 in FIG. 4. The burst counter 51 comprises a binary counter.
In the example of FIG. 4, a plurality of address data ad2 included in the internal Y address signal is sequentially supplied from the buffer 41 to the Y address latch 44 and latched therein, while in the example of FIG. 5, the first address data ad2' included in the internal Y address signal is latched in the burst counter 51 and then the burst counter 51 is counted up based on the address data so that all address data included in the internal Y address signal are sequentially generated.
As shown in FIG. 5, when the addressing unit is constructed synchronously by using the burst counter 51, the speed of the process is further increased than the addressing unit as shown in FIG. 4.
FIG. 6 is a time chart showing an operation to latch the internal X address signal ad1 in the X address latch 43. In FIG. 6, the address signal ad0 (Valid-Data) is kept to be a high level or a low level in a set-up period tS0 and a hold period tH0 in synchronism with a falling edge of the control signal .phi.0 (FIGS. 6 (a) and (b)).
The address signal ad0 is translated to the internal X address signal ad1 by the buffer 41 and latched in the X address latch 43. The latching is conducted synchronous with the falling edge of the X latch signal .phi.X0 supplied from the internal control signal generation circuit 2 to the X address latch 43 (FIGS. 6 (c) and (d)). The X latch signal .phi.X0 is a signal generated through the processing of the control signal .phi.0 by the internal control signal generation circuit 2, and a certain delay time dt0 is caused for a time period from the input of the control signal .phi.0 to the acquirement of the X latch signal .phi.X0.
Under such a condition, in order to latch the internal X address signal ad1 in the X address latch 43 in synchronism with the falling edge of the X latch signal .phi.X0, namely, in order to keep the value of the internal X address signal ad1 (Valid-data) in the set-up time tS1 and the hold time tH1 to be a high level or a low level in synchronism with the falling edge of the X latch signal .phi.X0, it is necessary to match the delay time dt1 when the internal X address signal ad1 is generated in the buffer 41 from the address signal ad0, to the delay time dt0 in the internal control signal generation circuit 2.
However, the delay time caused in the generation of the internal X address signal ad1 in the buffer 41 is generally shorter than the delay time dt0 caused in the generation of the X latch signal .phi.X0 in the internal control signal generation circuit 2. Accordingly, in the prior art, it is necessary to set the delay time in the buffer 41 wastefully long in order to latch the internal X address signal ad1 in the X address latch 43 in synchronism with the falling edge of the X latch signal .phi.X0.
Namely, in spite of the fact that the process to translate the address signal ad0 to the internal X address signal ad1 in the buffer 41 is completed and it is ready to latch it in the X address latch 43, the X latch signal .phi.X0 is not yet generated at that time and the delay of the buffer 41 is wastefully long. This renders the implementation of high speed processing difficult. This problem is serious in the addressing unit of FIG. 4 as well as the addressing unit of FIG. 5 which aims the further speed-up of the process.