The present disclosure relates to a semiconductor structure, and particularly to a semiconductor structure including locally thinned semiconductor fins and a method for manufacturing the same.
Fin field effect transistors are widely employed in advanced semiconductor circuits for their superior performance over planar field effect transistors. Fin field effect transistors provide a high on-current per area and full depletion of a channel during operation. Typically, the width of the semiconductor fins employed for the field effect transistors is the minimum lithographically printable dimension, which is referred to as the critical dimension. Lithographic bias and etch bias that are introduced during lithographic patterning and pattern transfer can cause variations in the fin widths between semiconductor fins in a nested environment and semiconductor fins in an isolated environment. Thus, a method of selectively adjusting the widths of a group of semiconductor fins without affecting other semiconductor fins is desired.
Further, typical semiconductor processing flows provide semiconductor fins of identical height. This feature tends to quantize the on-current of fin field effect transistors. While the on-current of fin field effect transistors can be increased in multiples of the on-current of a fin field effect transistor employing a single fin, providing a fin field effect transistor having an on-current at a fractional multiple of the on-current of a fin field effect transistor employing a single fin is a challenge for conventional semiconductor processing sequences. Thus, a method is desired for providing field effect transistors having an on-current that is a non-integer multiple of the on-current of a fin field effect transistor employing a single fin.