1. Field of the Invention
This invention relates to analog to digital converters and more particularly to converters which will operate at high speeds and over wide ranges of temperatures and other conditions to produce highly accurate and reliable results, without requiring self-calibration procedures. Converters of the invention have a relatively simple architecture and economically manufacturable.
2. Description of the Prior Art
High speed A/D converters have heretofore been provided which have included "flash" converter integrated circuits. Such circuits have included a plurality of voltage comparators which compare the level of an analog input voltage with a series of reference voltage levels which are supplied in steps of uniform magnitude, typically by a string of resistors which are connected to a reference voltage source. The magnitude of the input analog signal is indicated by the number of comparator output signals produced, i.e., by the number of reference voltage levels which are exceeded by the input voltage. A "thermometer" code output is thus produced which is converted to binary by a decode circuit.
A problem with such flash converter circuits is that the number of required comparators and voltage levels doubles with each additional bit of the required resolution, so that an excessively large number of comparators and associated voltage levels would be required to obtain high resolution. In view of this problem, subranging A/D architectures have been used. A main range A/D converter is used which is of the flash type and which has a limited number of comparators, e.g., 32 or 64. The main A/D converter produces, in effect, a first approximation of the magnitude of an input analog signal. The first approximation so produced is then converted to an analog signal with a high speed precision D/A. The analog signal developed at the output of the D/A is then subtracted from the analog input signal, the result of the subtraction being applied to a second or "subrange" A/D converter to produce a binary coded output which is logically combined with a binary coded output from the main range A/D converter to produce the final binary coded digital output.
In an attempt to obtain high speed operation with prior subranging architectures, the analog input signal has been delayed before subtraction of the output signal of the high speed precision D/A therefrom, for the purpose of matching the delays of the main range A/D. A sample and a hold circuit is typically used as an input stage to apply a signal to the main range A/D and to obtain the required delay, a second sample and hold circuit may be used or, in the alternative, a delay line may be used. There is also a problem with digital skew going into the D/A and a register is oftentimes placed at the output of the main A/D to extend the time that the digital data is valid.
Prior subranging architectures have had problems with respect to accuracy and reliability, especially with respect to the use of a delay line which adds an error source since termination of a delay line is never exact and multiple reflections may be produced to degrade the conversion accuracy when sampling high frequency signals. In addition, the input and output terminations on the delay line may attenuate the signal by a factor of two so that the gain of the sub-range amplifier must be increased by a factor of two. Offsets by buffers in the analog delay line path coupled with the extra sub-range gain required makes the architecture sensitive to temperature variations. In addition, operation at frequencies other than the frequency for which the converter circuitry was designed can cause large conversion errors.
A specially constructed A/D/A (Analog/Digital/Analog) integrated circuit component has been tried in conventional architectures in an attempt to avoid problems, but with only limited success. The A/D/A Component includes comparators which drive decoding logic to develop a binary coded digital output and which also directly drive current sources to develop an analog output, thereby forming an A/D/A component in which the speed of development of the analog output is increased. It is found that although this component has important advantages, the use of this component with the conventional subrange architecture is still limited in providing a high speed and high resolution converter.