1. Field of the Invention
The present invention relates to an operational amplifier, and more particularly, to an operational amplifier capable of driving large capacitive loads with low power consumption.
2. Description of the Prior Art
Operational amplifiers have been applied extensively in the field of electrical devices and electronics, such as inverter amplifiers, integrators, and filter circuits, to name just a few instances. With the rapid scaling in CMOS processes, supply voltages in VLSL have been dramatically reduced in recent years. Acting as a fundamental block in most analog systems, operational amplifiers are required to achieve high gain and large bandwidth simultaneously in low-voltage applications. Since conventional cascade amplifiers, which increase the gain by stacking up transistors, are not suitable in low-voltage design due to small voltage swings, more circuit designers are aware of the importance of multi-stage amplifiers, which boost the gain by increasing the number of gain stages horizontally. However, all multi-stage amplifiers suffer close-loop stability problems due to their multiple-pole nature in the small-signal transfer functions. Therefore, many frequency compensation topologies have been proposed to ensure the stability of the multi-stage amplifiers. Generally, the operational amplifier applied in the conventional driver chip is normally a two-stage amplifier having a first stage amplifying circuit for gain enhancement and a second stage output circuit for driving the capacitive or resistive load. However, three-stage operational amplifiers are also gaining popularity.
The most relevant characteristics of an amplifier circuit are usually gain and bandwidth. There is an inverse relationship between the gain and the bandwidth of amplifiers. In general, higher gain values are associated with lower bandwidths, and lower gain values are associated with higher bandwidth. The performance of an operational amplifier is characterized by its transfer function which can be obtained by applying small-signal analysis. Reference is made to FIG. 1 for a transfer function of an exemplary two-stage amplifier. There is a relatively constant gain from DC to a frequency of the first dominant pole ωP1. When the frequency rises above ωP1, the gain begins to fall sharply. The maximum available bandwidth is related to the second non-dominant pole ωP2. It may be desirable to adjust the frequency of poles ωP1 and ωP2 for different applications. Various compensation techniques, such as Miller compensation or Ahuja compensation, are known for adjusting the frequency of the poles of the amplifier. Miller compensation employs a feedback capacitor connected across an input and output of the second amplifier stage. In Ahuja compensation, a current gain device is added in a feedback loop of the second amplifier stage.
Reference is made to FIG. 2 for a block diagram of a prior art two-stage Miller Compensation (MC) amplifier 10. The two-stage MC amplifier 10 includes a first-stage amplifier 11, a second-stage amplifier 12, and a compensation capacitor Cm. The transconductance, output resistance, and lumped output parasitic resistance of the first gain stage are notated by gm1, ro1, and Cp1, and those of the second gain stage are notated by gm2, ro2, and CL. The compensation capacitor Cm is coupled between the input and the output ends of the second-stage amplifier 12. By introducing the compensation capacitor Cm, the capacitance of the second-stage amplifier 12 appears much larger from its input, thereby shifting the first dominant pole ωP1 to a lower frequency and the second non-dominant pole ωP2 to a higher frequency.
However, the capacitor Cm functions as a short-circuited path at high frequencies, and the combination of the capacitor Cm and the second-stage amplifier 12 creates a diode-connected transistor. In this case, any noise from a reference potential is transferred to the second-stage amplifier 12. In addition, the MC amplifier 100 has a poor power supply rejection ratio (PSRR) during high frequency operations. Therefore, if a good PSRR is required, the two-stage MC amplifier 10 is insufficient for desirable operation.
Reference is made to FIG. 3 for a block diagram of a prior art three-stage Nested Miller Compensation (NMC) amplifier 20. The three-stage NMC amplifier 20 includes a first-stage amplifier 21, a second-stage amplifier 22, a third-stage amplifier 23, and compensation capacitors Cm1 and Cm2. The transconductance, output resistance, and lumped output parasitic resistance of the first gain stage are notated by gm1, ro1 and Cp1, those of the second gain stage are notated by gm2, ro2, and Cp2, and those of the third gain stage are notated by gm3, ro3, and CL. The compensation capacitor Cm1 is coupled between the input end of the second-stage amplifier 22 and the output end of the third-stage amplifier 23. The compensation capacitor Cm2 is coupled between the input end and the output end of the third-stage amplifier 23. Under the assumptions: (1) Cm1, Cm2 and CL>>CP1 and CP2 and (2) gm3>>gm1 and gm2, the three-stage NMC amplifier 20 is characterized by the small-signal transfer function ANMC(s) represented by:
                                          A            NMC                    ⁡                      (            s            )                          =                              A                          D              ⁢                                                          ⁢              C                                ⁢                                    A                              D                ⁢                                                                  ⁢                C                                                                    [                                                      s                                          ω                                              p                        ⁢                                                                                                  ⁢                        1                                                                              +                  1                                ]                            ⁡                              [                                                                            s                      2                                        ⁢                                                                                            C                                                      m                            ⁢                                                                                                                  ⁢                            2                                                                          ⁢                                                  C                          L                                                                                                                      g                                                      m                            ⁢                                                                                                                  ⁢                            2                                                                          ⁢                                                  g                                                      m                            ⁢                                                                                                                  ⁢                            3                                                                                                                                +                                      s                    ⁢                                                                  C                                                  m                          ⁢                                                                                                          ⁢                          2                                                                                            g                                                  m                          ⁢                                                                                                          ⁢                          2                                                                                                      +                  1                                ]                                                                        (        1        )            
where ADC is the DC gain equal to gm1gm2gm3ro1ro2ro3 
and ωP1 is the dominant pole equal to (Cm1gm2gm3ro1ro2ro3)−1 
To stabilize the NMC amplifier 20, following dimension condition shall be obeyed:
                              C                      m            ⁢                                                  ⁢            1                          =                  4          ⁢                      (                                          g                                  m                  ⁢                                                                          ⁢                  1                                                            g                                  m                  ⁢                                                                          ⁢                  3                                                      )                    ⁢                      C            L                                              (        2        )                                          C                      m            ⁢                                                  ⁢            2                          =                  2          ⁢                      (                                          g                                  m                  ⁢                                                                          ⁢                  2                                                            g                                  m                  ⁢                                                                          ⁢                  3                                                      )                    ⁢                      C            L                                              (        3        )            
Pole-splitting can also be achieved in the NMC amplifier 20 by introducing the compensation capacitors Cm1 and Cm2. However, the non-dominant pole depends on Cm2 and thus depends on the loading capacitance CL, as depicted in (1) and (3). When driving a large capacitive load, a large Cm2 is required, thereby shifting the non-dominant pole to a rather low frequency. Therefore, the bandwidth of the NMC amplifier 20 is poor. Moreover, the NMC amplifier 20 is not suitable for low-power design since the previously stated assumption gm3>>gm1 and gm2 may not be valid.
Ahuja frequency compensation scheme is another well-known frequency compensation for operational amplifiers. Reference is made to FIG. 4 for a block diagram of a prior art two-stage Ahuja compensation amplifier 30. The two-stage Ahuja compensation amplifier 30 includes a first-stage amplifier 31, a second-stage amplifier 32, a compensation capacitor Cm, and a current gain device Ig. The transconductance, output resistance, and lumped output parasitic resistance of the first gain stage are notated by gm1, ro1, and Cp1, and those of the second gain stage are notated by gm2, ro2, and CL. The two-stage Ahuja compensation amplifier 30 is characterized by the small-signal transfer function Aahuja(S) represented by
            A      ahuja        ⁡          (      s      )        =            A              D        ⁢                                  ⁢        C              ⁢                  [                              s                          ω              z                                +          1                ]                              [                                    s                              ω                                  p                  ⁢                                                                          ⁢                  1                                                      +            1                    ]                [                                            s              2                                      ω              n              2                                +                      s                          [                                                ω                  n                                                  2                  ⁢                                                                          ⁢                  ξ                                            ]                                +          1                ]            
where
ADC is the DC gain equal to gm1gm2ro1ro2 
ωP1 is the dominant pole equal to (Cmgm2ro1ro2)−1 
ωz is the non-dominant zero equal to
      g          m      ⁢                          ⁢      c            C    m  
ζ is the damping factor equal to
                              1          2                ⁢                                                                              C                  1                                ⁢                                  g                                      m                    ⁢                                                                                  ⁢                    c                                                                                                C                  L                                ⁢                                  g                                      m                    ⁢                                                                                  ⁢                    2                                                                                ⁡                      [                          1              +                                                C                  L                                                  C                  m                                                      ]                                              (        4        )            
ωn is the natural frequency equal to
                                                        g                              m                ⁢                                                                  ⁢                c                                      ⁢                          g                              m                ⁢                                                                  ⁢                2                                                                        C              1                        ⁢                          C              L                                                          (        5        )            
In the two-stage Ahuja compensation amplifier 30, the compensation capacitor Cm and the current gain device Ig are coupled in series between the input and the output ends of the second-stage amplifier 32. By introducing the current gain device Ig, the second-stage amplifier 32 no longer becomes a diode-connected transistor while it is operating at high frequencies. This two-stage Ahuja compensation amplifier 30 can thus achieve a good PSRR at high frequencies. However, the two-stage Ahuja compensation amplifier 30 fails to achieve good compensation in certain cases.