1. Field of the Invention
The invention relates to a signal delay device, and more particularly to a digital delaying device.
2. Description of the Related Art
There are various formats in the data write control specifications for an optical disc such as CD-R, CD-RW, DVD, and the like. The formats, which allow writers to write multilevel data to the optical disc, are sequentially proposed. Therefore, it is more important to precisely control the laser waveform for writing data to the optical disc.
FIG. 1 shows a schematic illustration of a laser write waveform of a CD-R. As shown in FIG. 1, the laser write waveform is a write power from time t0. The write power is held until time t1 and is dropped to an erase power, which is held until time t2. Next, the laser write waveform is again dropped to a read power. The length from time t1 to time t2 is determined by the mark length to be written. The length from time t0 to time t1 is program-controlled and does not vary with the change of the mark length. The basic unit of the mark length is T, and the mark length ranges form 3T to 11T in the CD-R specification. In addition, the leading edge of the laser write waveform at time t0 has about a delay length Δt, which is substantially equal to 0.25T. The delay length Δt is only needed when the previous write mark is 3T. Consequently, it is quite important to precisely control the switch timing of the laser write waveform.
U.S. Pat. No. 6,269,060, entitled “Programmable write signal generator” has disclosed a technology for generating a write signal. FIG. 2 shows a block diagram of the delay signal generating unit of this patent. Referring to FIG. 2, the delay signal generating unit 506 includes an upper course delay unit and a lower fine delay unit. The output signal of the course delay unit is supplied to the fine delay unit, which may precisely control the delay timing. As shown in the drawing, the delay timing of the course delay unit is 2.5 ns while the delay timing of the fine delay unit is 0.25 ns. Each delay unit includes a plurality of cascaded delay cells D1(D2), a multiplexer 612(632), and a selection signal generator 610(630). The plurality of cascaded delay cells D1(D2) receives the input signal, and then a plurality of signals with different delay timings are generated. Next, the multiplexer 612(632) selects one of the signals for output according to a selection signal, which is supplied from the selection signal generator 610(630). Because the patent utilizes voltage control delay cells in the delay lock loop (DLL), it discloses an analog control method, and the charge pumps in the DLL are also of an analog design. In general, the analog design is more complicated and tends to be influenced by the environment.