In the manufacture of semiconductor devices, a semiconductor wafer is divided by scribe lines into a plurality of dies. The dies comprise integrated circuits of identical type and, after appropriate testing to verify operability and reparability of the individual dies, they are sawed from the wafer and are thereafter referred to as chips. Each chip is appropriately packaged to result in the completed semiconductor device.
Each die has a plurality of contact areas, which are typically referred to as pads. In the completed semiconductor device, such pads are connected to leads which are accessible via the device packaging. During electrical testing of the wafer, individual contact areas are contacted by respective testing probes of a probe card. Such probes are typically needle-like elements mounted on a probe card structure, which are aligned with the contact areas before actual contact is made. The needle-like devices penetrate slightly into the contact areas to make electrical contact. There are probe types other than needle-like devices which may be used with various types of pad structures, but the present invention is not dependent on the particular type of contact area or probe which is utilized.
For functional testing, dedicated automated test equipment (henceforth referred to as “IC test system”) is connected to the probe card and voltages are applied through the probes to various contact areas of the wafer. Basic chip operation usually requires a minimum of three types of pads: (1) pads through which a global supply voltage VS is applied, (2) pads that are used to control the command logic of the integrated circuit, and (3) pads that are used to supply data bits to and receive data bits from the chip. Those return signals from the wafer also pass through designated probes and are fed back to the electrical tester. The location of test failures is stored in a fail memory so that repairs can be kept track of, and the testing sequence is controlled automatically.
A probe card may be designed so that its probes cover multiple dies in order to maximize the number of dies can be tested at the same time. The degree to which multiple dies can be tested simultaneously is referred to as parallelism. Each probe is ultimately connected to the electrical tester, and corresponds to a channel of the testing system. Since the factors limiting parallelism are the capacity of the fail memory and the number of available testing channels per device under test, it is desirable to maximize the number of channels which are available for testing.
Typically, less than all of the contact areas on the dies are utilized for testing, and it may be a requirement of the test that one or more of the contact areas which is not tested be held at a predetermined voltage value during the test. In accordance with a prior mode of accomplishing this, the predetermined voltage value was obtained through the probe card, and since any probe(s) used for obtaining such value could not be used for testing, a limitation on the number of testing channels resulted.