International Publication No. WO2010/146738 discloses a shift register for scanning gate bus lines. This shift register is composed of a plurality of cascade-connected stages the number of which corresponds to the number of the gate bus lines. Each stage has terminals to which a high-level power source voltage and a low-level power source voltage are input, respectively, and terminals to which an output signal sent from the previous stage and an output signal sent from the next stage are input, respectively. Further, each stage has a terminal to which a clock signal is input, and a terminal through which an output signal of the current stage itself is output as a gate pulse. Each stage is composed of a plurality of transistors including a transistor (M5) and a transistor (M6), and a capacitor that are connected to one another. The transistor (M5) is connected to the terminal to which the high-level power source voltage is input. Further, the transistor (M6) is connected to a terminal into which the low-level power source voltage is input.
An internal node in a shift register in each stage has a potential that changes with a clock signal. According to a change of the potential of the internal node, the transistor (M5) is turned on, and a power source voltage VDD is output as a gate pulse via the transistor (M5). This shifts a gate bus line into a selected state. Further, the transistor (M6) is turned ON in response to the clock signal, and the transistor (M6) causes the potential of the internal node to have a power source voltage VSS, thereby decreasing the gate pulse. This shifts the gate bus into a non-selected state.