Frequency spectrum is a scarce resource in modern communications systems, and therefore e.g. the Third-Generation Partnership Project (3GPP) specification group is continuously adding new frequency bands.
Most modern transceiver solution use direct conversion receiver and transmitter architectures to reduce complexity and minimize power consumption. Such transceivers use local oscillators for frequency generation in the receiver part as well as the transmitter part. The receiver and the transmitter need quadrature local oscillator signals. These are normally generated by dividing the local oscillator signal by two. Thus the local oscillator signal should preferably be operating at twice (or a higher even multiple) the desired receive/transmit frequency.
The output from the local oscillators has to be a clean low noise signal to get good quality reception/transmission. This is normally done by locking a voltage controlled LC-oscillator to a crystal oscillator using a phase locked loop. The LC-oscillator needs to cover all desired receive and transmit radio frequencies, i.e. a wide range of frequencies has to be supported.
A typical LC-oscillator consists of an inductor, a variable capacitor, a resistor representing all losses and a sustaining amplifier. The inductor can be implemented as a large on chip metal structure and the capacitor is made variable to be able to generate various output frequencies. The capacitor can consist of switchable capacitors, variable capacitors or a combination thereof.
It has proven to be difficult to generate high capacitor variations. When the available range is in-sufficient one has to use multiple VCO:s centered differently and select the correct one via a multiplexer. This generates bulky solutions, and one might need to add a new VCO for each new frequency band to be supported.
By adding a frequency divider at the VCO output to divide the VCO output by two the need for frequency variations of the VCO can be reduced. In principle, it would then be sufficient that the VCO covers a frequency range corresponding to one octave, i.e. with a factor two between the upper and lower endpoints of the VCO frequency range.
However, in practice the VCO center frequency will vary across Process, supply Voltage and Temperature (PVT). Thus if the center frequency has drifted downwards or upwards from its nominal value the complete desired frequency range can not necessarily be covered with a relative VCO range of two. Therefore, the variations of the center frequency impose a need for extra margins at each end of the tuning range. Also to avoid respins of an ASIC, some margin should be added for centering error in the design. Altogether this forces the designer to have ˜12% margins at each end of the tuning range, and the required tuning range for continuous tuning range becomes 2.5 instead of the factor 2 mentioned above. This value is still difficult to achieve with one VCO, and therefore multiple VCOs will still have to be used. Typically, it will take three VCOs to cover a tuning range of 2.5.
It might be possible to reduce the number of VCOs by doing a more clever VCO design. For instance, the inductor could also be made switchable. However it will always be difficult to reach a relative tuning range of 2.5.
Among the main problems with existing solutions are cost and efficiency. Multiple VCOs occupy a lot of space and the multiplexing will consume current. By designing wide tuning range VCOs the number of VCOs required could be reduced. However, when designing wide tuning range VCOs more switching is required, which introduces resonator loss. This means worse noise performance and higher current consumption. Thus there clearly is a need to reduce the tuning range requirements of the VCO.