In general, a cache is used to duplicate a certain part of a lower level memory, so that the duplicated part in the cache can be accessed by a higher level memory or a processor core in a short amount of time and thus to ensure continued pipeline processing of the processor core.
Currently, cache addressing is based on the following ways. First, an index part of an address is used to read out a tag from a tag memory. At the same time, the index and an offset part of the address are used to perform an addressing operation to read out contents from the cache. Further, the tag from the tag memory is compared with a tag part of the address. If the tag from the tag memory is the same as the tag part of the address, called a cache hit, the contents read out from the cache are valid. Otherwise, if the tag from the tag memory is not the same as the tag part of the address, called a cache miss, the contents read out from the cache are invalid. For a multi-way set associative cache, the above operations are performed in parallel on each set to detect which way has a cache hit. Contents read out from the set with the cache hit are valid. If all sets experience cache misses, contents read out from any set are invalid. After a cache miss, cache control logic fills the cache with contents from the lower level storage medium.