As Internet-connected devices become ever more ubiquitous, such devices are becoming physically smaller and otherwise resource-constrained. One term that has been used to describe this trend is the emerging “Internet of Things” (IoT) which utilizes resource-constrained devices to enable various types of internetworked functionality with respect to the objects or things in our everyday environment. In particular, such devices include sensors of various types including imaging sensors. For resource-constrained and particularly energy-constrained devices, compression of sensor data is desirable as a way to efficiently use resources such as wireless transmission resources. However, data compression is itself a computationally intensive task which can cause a significant and possibly excessive draw on device resources.
In addition to the challenges of resource-constrained devices, there are drawbacks associated with conventional computing architectures. In some computers, improvements in memory speed could not match the speed up gain by processor frequency due to increased focus on logic gate density, which resulted in a communication bottleneck. Hence, researchers introduced cache memories closer to the processor to help alleviate the bottleneck and improve the overall system speed. As further enhancement in frequency for a single core could not be achieved due to IO bandwidth limit, the focus moved to multi-core systems combined with memory hierarchy. Although such architecture supports parallel computing, the speed-up gain of the system heavily depends on the ability to parallelize the software code on that architecture. Also, putting accelerators closer to the main memory and sending the result of the executed task instead of the whole data has helped to mitigate the memory access bottleneck. However, the “von Neumann bottleneck” is still there since data needs to be sent back and forth between the memory and core blocks. Increase memory size and hierarchy improves system performance but has negative impact on energy and area. It also adds complexity especially for multi-core where memory coherency need to be dealt with. It is estimated that data migration from off-chip memory to the last level cache (LLC) and through the cache hierarchy, buses, and register file can account for up to 66% of the total energy in data-intensive applications such as those involving data compression.
Conventional attempts to solve the problems of implementing data compression for resource-constrained devices have shortcomings. For example, some conventional attempts are costly, inefficient (e.g., with respect to power consumption, resource utilization, and/or physical space utilization) and/or ineffective (e.g., with respect to particular performance criteria for particular applications). Embodiments of the invention address these and other problems as will be apparent from the description below.