The present invention relates to a write control device, and more specifically, to a technology for rapidly performing a write operation of a nonvolatile memory device configured to sense data based on resistance change.
Generally, memory devices may be classified as volatile memory devices or nonvolatile memory devices. A nonvolatile memory device includes a nonvolatile memory cell capable of preserving stored data even when a power source is off. A nonvolatile memory device may be implemented, for example, as a flash random access memory (RAM) device, a phase change RAM (PCRAM) device, or the like.
PCRAM devices include memory cells that are implemented using a phase change material, for example, germanium antimony tellurium (GST), and are configured to store data in the memory cells by applying heat to the GST so that the GST changes into a crystalline phase or an amorphous phase.
A nonvolatile memory device, such as a magnetic memory device, a phase change memory (PCM) device, or the like, has a data processing speed similar to that of a volatile RAM device. However, unlike a volatile RAM device, a nonvolatile memory device preserves data even when a power source is off.
FIGS. 1a and 1b illustrates a conventional phase change resistance device 4.
Referring to FIGS. 1a and 1b, a conventional phase change resistance device 4 includes an upper electrode 1, a lower electrode 3, and a phase change material 2 interposed between the upper electrode 1 and the lower electrode 3. When a voltage is applied to the upper electrode 1 and the lower electrode 3, a current flows into the phase change material 2, thus inducing a high temperature in the phase change material 2. As a result, the electrical conductive state of the phase change material 2 changes depending on resistance variation due to the high temperature.
FIGS. 2a and 2b illustrate a phase change principle of the conventional phase change resistance device 4.
Referring to FIG. 2a, if a low current smaller than a critical value flows into the phase change resistance device 4, the phase change material 2 is crystallized. When the phase change material 2 changes into a crystalline phase, it becomes a low resistance material. As a result, a current can flow between the upper electrode 1 and the lower electrode 3.
On the other hand, referring to FIG. 2b, if a high current greater than the critical value flows into the phase change resistance device 4, the phase change material 2 has a temperature higher than a quenching point. When the phase change material 2 changes into an amorphous phase, i.e., a non-crystalline phase, it becomes a high resistance material. As a result, a current cannot easily flow between the upper electrode 1 and the lower electrode 3.
The phase change resistance device 4 can store data corresponding to two resistance phases. That is, in one case, if a low resistance phase in the phase change resistance device corresponds to a data “1,” and a high resistance phase corresponds to a data “0,” then the phase change resistance device 4 may store two logic states of data.
This data can be stored in the phase change resistance device 4 as nonvolatile data because the status of the phase change material 2 does not change even when a power source is off.
FIG. 3 illustrates a write operation of a conventional phase change resistance cell.
Referring to FIG. 3, heat is generated if a current flows between the upper electrode 1 and the lower electrode 3 of the phase change resistance device 4 for a given time.
If a low current, smaller than the critical value, flows for a given time, the phase change material 2 changes into a crystalline phase. As a result, the phase change resistance device 4 becomes a low resistance element having a set phase.
On the other hand, if a high current, greater than the critical value, flows for a given time, the phase change material 2 changes into an amorphous phase. As a result, the phase change resistance device 4 becomes a high resistance element having a reset phase.
Accordingly, a low voltage is applied to the phase change resistance device 4 for a long period of time in order to write the set phase in the write operation.
On the other hand, a high voltage is applied to the phase change resistance device 4 for a short period of time in order to write the reset phase in the write operation.
To change the phase change resistance cell into the set phase, it is important to control a quenching slope of a set write current, which is required for crystallizing the phase change resistance cell, by gradually reducing an amount of the set write current. This way of gradually reducing the set write current is called “quenching.”
However, for example, if a reference current, which is used to generate the set write current and is received from the outside or generated inside the chip, changes by some factors or if a clock having a wrong value is generated by mismatched circuits, the set write current may be generated with an undesired quenching slope.
Moreover, without accurately checking the quenching slope, it is impossible to precisely control the phase change resistance cell in program and verify (PNV) operations and a multi-level cell MLC where multi-leveled resistance distribution of a phase change material, e.g., germanium antimony tellurium (GST), is formed.
Meanwhile, a conventional nonvolatile memory device controls a driving voltage supplied to a memory cell array in a program operation using a write driving unit.
The write driving unit is configured to stably supply a write current even though the write current has a small current value. However, it takes a much longer time to supply cells with the write current when using a small current value than when using a large current value.
That is, when the write driving unit supplies a small write current to the cells, it takes much longer to supply the current because of parasitic components on a write path.
FIG. 4 illustrates a write time that is delayed by a large parasitic component and a small write current. Here, IT represents a driving current flowing in a driving transistor of the write driving unit, and IM represents a cell current flowing in a memory cell.
Referring to FIG. 4, the driving current IT flowing in the driving transistor reaches a stabilized current level after a settling time tsettling passes. In addition, there is a time delay due to parasitic components on a write path. A time delay tDELAY occurs in a period of time where the driving current IT of the driving transistor is transmitted to the memory cell.
A small write current is generally determined by characteristics of cells and the size of a cell array. As the size of the cell array becomes larger, the delay time occurring due to the parasitic components on the write path also become greater.
In this way, the write time becomes longer by the small write current and the large size of the cell array. A conventional write driving unit has not introduced improvements to such a write time delay phenomenon.