In a conventional large-scale computer system that includes multiple chips, an error that occurs in the hardware that is contained in the computer system is detected and information on the detected error and information on the time at which the error occurred are stored in a register that is a storage device. A system managing apparatus, managing the computer system, accesses a register in which information on the error is stored and analyzes the error.
A configuration of the above-described computer system will be described below with reference to FIG. 9. FIG. 9 is a diagram of a configuration example of the system according to the conventional technology. The system illustrated in FIG. 9 includes system boards on each of which central processing units (CPUs) are mounted, a crossbar board on which crossbar chips each including a timer are mounted, I/O boards on each of which a large scale integrated (LSI) circuit that controls the I/O device is mounted, and a system management board (MMB) that is a service processors (SVP) and on which firmware that manages the system is mounted. The system management board accesses the register of each chip via an inter-integrated circuit (I2C) bus.
For example, once a slave address and a channel of an I2C multiplexer that is an upper-level device with respect to a chip that is to be accessed are specified, the system management board is connected to the board on which the chip to be accessed is mounted. The system management board then specifies the slave address of the chip to be accessed and starts communications. The system management board then refers to the error information and the timer value (time information) that are stored in the register of the accessed chip and analyzes, for example, how the error occurred.
However, as illustrated in FIG. 9, in a system in which broadcast communications cannot be performed, it is difficult to analyze an error that has occurred in the hardware. Specifically, in a system configuration in which broadcast communications cannot be performed, because the timers of the chips are not synchronized, it is not possible to analyze how an error occurred according to the timer value that is stored in the register and is referred to on the occurrence of the error.
To synchronize the timers (time information) in the above-described large-scale system, various technologies are disclosed in, for example, Japanese Laid-open Patent Publication No. 10-28119 and Japanese Laid-open Patent Publication No. 04-182806.
The above-described conventional technologies, however, have a problem in which it takes time to complete a process for synchronizing the timers (time information).