Consumers continually pressure integrated circuit manufacturers to provide devices that are smaller and faster, so that more operations can be performed in a given amount of time, using fewer devices that occupy a reduced amount of space and generate less heat. For many years, the integrated circuit fabrication industry has been able to provide smaller and faster devices, which tend to double in capacity every eighteen months or so.
However, as integrated circuits become smaller, the challenges of fabricating the devices tend to become greater. Fabrication processes and device configurations that didn't present any problems at a larger device size tend to resolve into new problems to be overcome as the device size is reduced. For example, in the past there was very little incentive to planarize the various layers from which integrated circuits are fabricated, and which are formed one on top of another. Because the devices themselves were relatively wide, the relatively thin layers that were formed did not present many challenges to overcome in regard to surface topography.
However, as the devices have been reduced in size they have become relatively narrower. Although layer thickness has also generally decreased, the surface topography of an underlying layer tends to create greater problems for the proper formation of the overlying layer to be formed, unless the underlying layer is planarized in some way prior to the formation of the overlying layer.
There are several different methods used for planarizing a layer on an integrated circuit. For example, chemical mechanical polishing can be used to physically and chemically erode the surface of the layer against a polishing pad in a slurry that contains both physically and chemically abrasive materials. Further, electropolishing can be used to thin an electrically conductive layer. Unfortunately, neither process tends to produce surface topographies that are as flat as desired.
For example, although each of these two planarization processes tends to preferentially remove higher portions of a layer, they also attack to at least some degree the lower portions of the layer. Thus, even the though the higher portions of the layer are removed at a rate that is somewhat greater than that of the lower portions, and hence some planarization does occur, there also tends to be some amount of dishing in the lower portions of the layer, where a greater amount of material is removed than is desired.
What is needed, therefore, is a method whereby the dishing of planarized layers is reduced.