The present invention relates to a buffer storage system in a data processing apparatus and, more particularly, it relates to a buffer storage system including therein both a buffer storage for accessing operands and a buffer storage for fetching instructions, separately.
Recent increases, in the capability of a data processing apparatus, have led to attempted use of a variety of data-processing methods for coping with this increased capability. In one of these methods, namely the pipeline method, each sequence for executing an instruction is divided into a plurality of phases and each of the phases is executed at each station. This enables operations at respective stations to be achieved independently, and a plurality of instructions to be executed simultaneously.
In the prior art buffer storage system, both the pipeline set up in the operand access buffer storage, and the pipeline set up in the instruction fetch buffer storage, must be synchronized with each other. To strictly maintain such synchronization, often several operand access cycles must be left idle until several instruction fetch cycles with high priority are completed. This will be clarified in detail hereinafter. However, this leads to the problem in that the effective operating speed of the data processing apparatus cannot be made sufficiently high, due to the insertion of the above-mentioned idle operand access cycles, and therefore, the capability of the data processing apparatus cannot be increased to any large degree, even though independent buffer storages for accessing operands and fetching instructions are introduced.