1. Field of the Invention
The present invention relates to an address translation control system, more particularly to an address translation control system which, in addition to an address translation buffer performing a high speed translation from a logical address to a physical address, comprises a memory array copied from a portion of the contents of the address translation buffer, and in which a partial purge in the address translation buffer is performed by searching the memory array.
2. Description of the Related Art
In a data processing system using a virtual storage method, the translation from a logical address to a physical address at a high speed is performed by an address translation control system wherein address translated pairs of logical addresses and physical addresses are registered in a TLB (Translation Lookaside Buffer), i.e., an address translation buffer, and a high speed address translation is performed by accessing the address translation buffer.
The address translation buffer comprises a primary block and an alternate block, wherein each block has a plurality of entries. Each entry comprises a valid flag showing the validity of the entry, a multiple virtual storage identification field identifying a multiple virtual storage space, a logical address field, a physical address field, and a storage protection key field.
In a conventional address translation control system having such an address translation buffer, for an ordinary command fetch or operand access, the above-mentioned address translation buffer is accessed by applying a portion of the logical address to be translated, i.e., access address from an effective address register. By this accessing, the entire contents of the accessed entry stored in the primary block and the alternate block in the address translation buffer are read. A multiple virtual storage identification and the partial logical address which are read from the address translation buffer are compared with a multiple virtual storage identification from a multiple virtual storage identification register and another portion of the logical address from the effective address register, respectively. If the identifications of the comparing contents are obtained, the physical address in the entry is sent to a real address register as a physical address corresponding to a logical address in the effective address register.
In a virtual storage system, since the logical address covers a wider range than the utilizable physical address, a physical address, in turn, is allocated to another logical address when the physical address becomes non-utilizable. At that time, if a translation table in a main storage unit is renewed, since pairs of logical addresses and physical addresses translated before the renewal may remain in the address translation buffer, the pairs must be searched for and then purged. For this reason, in a conventional address translation control system, a partial purge method wherein each entry in the address translation buffer is searched for a physical address, is frequently used. According to this method, when a physical address to be purged is applied to a purge register, the access address in the effective address register is sequentially increased, an entry in the address translation buffer is sequentially read, the physical address in the purge register is compared with the physical address in the address translation buffer, and if the addresses are identical, a valid flag of the entry is made invalid.
In such a conventional address translation control system, when the partial purge is carried out, since all the contents of the address translation buffer must be read out, there is a defect in that the address translation buffer cannot be used at an ordinary command fetch or operand access.
The above defect in the conventional address translation control system causes a decrease in the operating efficiency of the address translation buffer, and in particular a considerable reduction in the performance when using the pipeline method.