1. Field of the Invention
The present invention relates to a constant current circuit and a reference voltage circuit using the same, and more particularly, to stabilizing operation of a constant current circuit.
2. Description of the Related Art
A conventional constant current circuit is described. FIG. 9 is a circuit diagram illustrating a conventional constant current circuit using the difference in K-value (drivability). The K-value is determined by K=W/L·(μCox/2), where W is the gate width, L is the gate length, μ is the mobility of carriers, and Cox is the gate oxide capacitance per unit area.
The conventional constant current circuit includes enhancement mode NMOS transistors 91 and 92 having different K-values, enhancement mode PMOS transistors 93 and 94, and a resistor 95.
The enhancement mode NMOS transistor 91 has a source terminal connected to a ground terminal 100 having a minimum potential, and a drain terminal and a gate terminal which are both connected to a gate terminal of the enhancement mode NMOS transistor 92 and a drain terminal of the enhancement mode PMOS transistor 93. The enhancement mode NMOS transistor 92 has a source terminal connected to the ground terminal 100 via the resistor 95, and a drain terminal connected to a gate terminal and a drain terminal of the enhancement mode PMOS transistor 94 and a gate terminal of the enhancement mode PMOS transistor 93. The enhancement mode PMOS transistors 93 and 94 each have a source terminal connected to a power supply terminal 101 having a maximum potential.
Next, an operation of the conventional constant current circuit is described. The K-value of the enhancement mode NMOS transistor 91 is smaller than the K-value of the enhancement mode NMOS transistor 92. A voltage difference between a gate-source voltage of the enhancement mode NMOS transistor 91 and a gate-source voltage of the enhancement mode NMOS transistor 92 is generated across the resistor 95. A current flowing through the resistor 95 is mirrored by the enhancement mode PMOS transistors 93 and 94, thereby generating a bias current (see, for example, Japanese Patent Application Laid-open No. Hei 03-238513).
However, the conventional constant current circuit has two operating points. One is a normal operating point at which the bias current flows. The other is an operating point at which the bias current becomes 0. When a potential at a connection point 291 becomes the maximum potential of the power supply terminal 101 and a potential at a connection point 290 becomes the minimum potential of the ground terminal 100, the constant current circuit is fixed at the operating point at which the bias current becomes 0, and thus fails to operate. The conventional constant current circuit has therefore a problem of needing a separate start-up circuit for start-up.
In addition, when the potential of the power supply terminal 101 increases and then the potential at the connection point 291 increases, the characteristics of the enhancement mode NMOS transistors 91 and 92 are changed by the channel length modulation effect of the enhancement mode NMOS transistor 92, with the result that the bias current fluctuates. In other words, the conventional constant current circuit has a problem of poor line regulation.