The present invention relates generally to a memory array address decoder and more particularly to a memory array address decoder used by a dynamic random access memory device.
A typical DRAM memory device is comprised of a plurality of memory cells, each comprised of a transistor and a capacitor. Each memory cell stores one bit of data in the form of a voltage. A high voltage level (e.g., 3V) represents a logic “1”, whereas a low voltage level (e.g., 0V) represents a logic “0”. The DRAM may also include peripheral devices, such as drivers, sense amps, input/output devices, and power supplies, etc., that are used to identify memory cells, access the memory cells, and store information within and read information from the memory cells, among others.
The memory cells may be arranged in an array with each memory cell being connected to a wordline and a digitline. Each memory cell has a unique address. Typically, the DRAM's control logic receives commands (e.g., read, write, etc.) and address information from a memory system controller. The address information is decoded by row and column decoders and the specific memory cell for which the command is directed is identified and the command executed.
Most DRAMs have built-in redundancy. Thus, should a memory cell become inoperable, a redundant memory cell can be assigned to logically take its place. For DRAMs incorporating redundancy, address information is sent to a comparator circuit. If the address information corresponds to an inoperable memory cell, a match signal is generated which substitutes the memory address of a redundant cell for that of the inoperable memory cell. The generation of the match signal, however, limits the speed of the DRAM because the other circuitry within the device must wait for the match signal to be generated.
The address information supplied to the row and column decoders can be either “true and complement” or pre-decoded as is known in the art. Pre-decoded address lines, for example, may be formed by logically combining (i.e., using one or more AND logic gates) true and complement addresses. Pre-decoded addressing requires less power than true and complement addressing because fewer signals need to make transitions during address changes. Additionally, pre-decoded addressing has a higher efficiency than true and complement addressing because fewer transitions are required to decode the same number of addresses.
Typical prior art decoders are classified as static or dynamic. FIG. 8 is a schematic of a static column decoder 80 according to the prior art. The static column decoder 80 includes NOR gate 81, NAND gates 82 and 84, and inverters 83 and 85. Pre-decoded address signals CA345i<0> and CA67Ei<0> are input into NOR gate 81 (where the “i” indicates that the signal is active low). The output of NOR gate 81 is fed to an input of NAND gate 82 and to an input of NAND gate 84. The pre-decoded address signal CA012<1> is provided to another input of NAND gate 82, whereas the pre-decoded address signal CA012<0> is provided to another input of NAND gate 84. The output of NAND gate 82 is fed to the input of inverter 83, which outputs the column select signal CSEL<1>. The output of NAND gate 84 is fed to the input of inverter 85, which outputs the column select signal CSEL<0>.
The static column decoder 80, although simple to implement, has several deficiencies. First, different gate delays are created for each column select line because the static column decoder 80 uses CMOS gates. Although originally tolerable, the differing gate delays create problems for today's DRAMs which operate at increased speeds. Second, the static column decoder 80 requires that the turn-on period and turn-off period of a match signal, for example generated when the originally addressed cell is found to be inoperable, be equal (i.e., the rise and fall times of the match signal must be the same). Thus, the cycle time for a static column decoder 80 is adversely affected.
FIG. 9 is a schematic of a dynamic column decoder 90 according to the prior art. The dynamic column decoder 90 includes several p-mos transistors (M2, M4, M6), several n-mos transistors (M1, M3, M5, M7), and several inverters (91–96). Typically, the dynamic column decoder is operated by first applying a precharge signal to the gates of transistors M3 and M7, thus pulling nodes 98 and 99, respectively, to ground. The precharge signal is then removed from the gates of transistors M3 and M7. Inverter 91 is used to latch node 98 at ground (thus, preventing node 98 from floating when the precharge signal is removed from the gate of transistor M3). Likewise, inverter 94 is used to latch node 99 at ground (thus, preventing node 99 from floating when the precharge signal is removed from the gate of transistor M7).
After the precharge signal is removed, the pre-decoded address signals CA012i<1>, CA012i<0>, CA345i<0>, and CA67E<0> are applied to the dynamic column decoder 90. The state of each of the output signals CSEL<1> and CSEL<0> is dependent upon these pre-decoded signals as should be apparent to one skilled in the art.
One advantage of the dynamic column decoder 90 over the static column decoder 80 is that the dynamic column decoder has consistent gate delays. Thus, the column select output lines (i.e., signals CSEL<1> and CSEL<0>) have consistent on/off times. The dynamic column decoder 90, however, has several deficiencies. For example, the feedback inverters 91, 94 must be sized large enough to keep the nodes 98 and 99, respectively, from floating (i.e., must keep the nodes 98 and 99 at ground potential, set when the precharge signal goes active), but sized small enough to be easily overridden when the pre-decoded address signals CA012i, CA345i, and CA67E go active. Additionally, the pre-decoded address signals CA012i, CA345i, and CA67E cannot go active until the precharge signal goes inactive, else the pre-decoded address signals overlap and fight the precharge signal. If the precharge and pre-decoded address signals CA012i, CA345i, and CA67E overlap, the turn on timing of the dynamic column decoder is adversely affected. Thus, the precharge signal consumes a relatively large amount of the cycle time which is available for providing the column select signals.
Thus, there exists a need for an improved memory array decoder that has a consistent turn-on time, that can utilize a precharge signal without adversely affecting the cycle time, and which overcomes the other limitations inherent in prior art.