Virtual memory allows programmers to use a larger range of memory for programs and data than is provided by the actual physical memory available to a processor. In addition virtual memory allows programs to be loaded in parallel to one another with a memory map that is impassive to the presence of other programs and the location to which it is loaded. A computing system maps a program's virtual addresses (also known as a Linear Address in the IA32 architecture—in this description ‘linear address’ or LA is used synonymously with ‘virtual address’) to real hardware storage addresses (e.g., physical memory addresses) using address translation hardware. The hardware uses a tree of tables in memory as the input data for the address translation. The root of the tree is pointed to by a register that holds the physical address of the first table in the page table tree. An example of such a register is CR3 in the IA32 architecture. Page table entries (PTEs) are addressed using a base and an index. The base is taken from a register or a previous table memory pointer. The index is using a portion of the linear address. The PTE includes either the page, if the rest of the sub tree is not present in memory, or a memory pointer and other information to be discussed below. The memory pointer is for a page in memory that may either include data (that belongs to the application or the operating system) or another level of the page-table. If it is the later case, another portion of the linear address is used to index into the table in a scheme similar to what is described. If the address is for an application page, the physical address is constructed by adding the remaining bits of the address (that were not used for indexing) to the page base address that was retrieved from the page table entry. Also, some embodiments may instantiate several translation schemes (e.g., different table tree indexing structures) as described in a register, for the sake of simplifying this description we will consider such information part of the CR3 register, even though it may be kept in one or more other registers.
Beyond the address translation information, these tables include information such as access rights read, write or execute, presence of the data in memory, caching policy indications, page modified state, etc. In some cases, a page table may include pages of different sizes, where larger pages are pointed to in a lower level of the page table tree (instead of pointing to another page of pointers) The size of the page pointed to is stored as an attribute in the page table tree (typically in the level that points to the data page).
To retrieve the physical address, the page-table entries are read in a recursive manner starting from the root (CR3 in IA32) and properties of the page are retrieved and merged. The IA32 Programmers' Reference Manual (e.g., Volume 3A) provides an example of a conventional approach to retrieving physical addresses. This process requires several memory access operations and is implemented by Page-Table Handling hardware or uCode sequences.
Occasionally, software is required to retrieve the physical memory address. In such cases either an emulated full table walk or a shortened heuristic that is based on the limitations of the setup of the table that the operating system imposes are used.
A translation look aside buffer (TLB) is a cache that holds the result of previous translations such that successive accesses to an address (or a range of addresses) may avoid walking the data structure and can use the results of a previous translation. In many cases the address translation also checks for the operation to meet the conditions set for the memory location. Conventional address translation instructions typically return a physical memory address for a linear address provided as an operand without providing any additional information.