In manufacturing integrated circuit elements, there has been progress in miniaturization of processing size in lithography processes with a view to obtaining integrated circuits with a high degree of integration. In these lithography processes, a resist pattern is formed by coating a photoresist composition on a workpiece layer, followed by exposure and development, and the resist pattern thus formed is transferred to a workpiece film such as a wiring layer, a dielectric layer or the like. Conventionally, an exposed region of the workpiece film, being the region exposed in the resist pattern, was removed by dry etching. However, film thickness of the resist layer (i.e., the resist pattern) was decreased by shortening the wavelength of the light source for exposure or the like, accompanied by miniaturization of the processing size. Therefore, sufficient dry etching resistance cannot be acquired, thereby making the processing of the workpiece film with high accuracy difficult to achieve. Also, due to a problem of reflection of the exposed light on the workpiece film, it is difficult to form a resist pattern in a favorable shape.
Hence, for transferring a resist pattern to a workpiece film with good accuracy, insertion of an antireflective film (hard mask) between the workpiece film and the photo resist layer has been studied. As a characteristic of this antireflective film the etching rate is required to have a large difference from that of the resist pattern (see, for example, Patent Documents 1 to 3).
Patent Document 1: Japanese Unexamined Patent Application Publication No. 2004-310019
Patent Document 2: Japanese Unexamined Patent Application Publication No. 2005-015779
Patent Document 3: Japanese Unexamined Patent Application Publication No. 2005-018054