Generally, a high voltage semiconductor device may be utilized when high voltage or high current output is required to drive a motor or when a high voltage is input from an external source. Typically, the high voltage semiconductor device includes a high voltage driving region and a low voltage driving region in a system-on-chip structure. In the high voltage device, when a low voltage is applied to a gate electrode and a high voltage is applied only to a drain electrode, the low voltage driving region and the high voltage driving region are formed at the same time. A through gate-oxide implantation (TGI) process is performed during a manufacturing process of a high voltage semiconductor device to form the low voltage driving region and the high voltage driving region on and/or over the chip while maintaining the existing characteristics. In the TGI process, an ion implantation process is performed to form a well region on and/or over a semiconductor substrate on and/or over which a high voltage gate oxide film is deposited.
As illustrated in example FIG. 1, a high voltage semiconductor device includes semiconductor substrate 1 having a high voltage device region and a low voltage device region, well region 2, device isolation film 3, gate oxide film 4, gate electrode 5, liner film 6 and interlayer insulating film 7. Device isolation film 3 is formed to define a device isolation region on and/or over semiconductor substrate 1 having the high voltage device region and the low voltage device region. Gate oxide film 4 is formed on and/or over semiconductor substrate 1 in the high voltage device region. After high voltage gate oxide film 4 is formed, a photoresist pattern is formed at a portion of the entire surface of substrate 1. Then, an ion implantation process is performed on semiconductor substrate 1 using the photoresist pattern as a mask to form well region 2 therein. In the ion implantation process for forming well region 2, ions are also implanted into the exposed high voltage gate oxide film 4. Accordingly, a trap site may be formed in gate oxide film 4 into which the ions are implanted. The photoresist pattern is then removed.
Gate electrode 5 is formed on and/or over semiconductor substrate 1 having well region 2. Gate electrode 5 is formed in an active region of substrate 1. Liner film 6 is formed on and/or over the entire surface of semiconductor substrate 1 including gate electrode 5 by forming a tetra ethyl ortho silicate (TEOS) film using preferential metal deposition (PMD). Interlayer insulating film 7 is formed on and/or over the entire surface of the resultant structure including liner film 6. Materials such as hydrogen and boron included in interlayer insulating film 7 may move to the trap site in gate oxide film 4. Consequently, leakage current increases in a threshold voltage region of the high voltage semiconductor device, thereby causing problems of increasing power consumption and reducing the device characteristics. Further, when the TEOS film is used as liner film 6, leakage current of the semiconductor device may increase significantly according to the state and atmosphere of a chamber in which liner film 6 is deposited. Particularly, C3F8 gas is used in cleaning the chamber in which the TEOS film of liner film 6 is deposited. If fluorine included in the C3F8 gas has a high density, a low level of leakage current of the NMOS transistor is measured. On the other hand, if fluorine included in the C3F8 gas has a low density, a high level of leakage current of the NMOS transistor is measured. Meaning, there is a problem that the leakage current of the semiconductor device largely increases according to the fluorine atmosphere in the chamber in which the TEOS film is deposited.