In traditional metal insulator semiconductor (MIS) dynamic random access memory (DRAM) devices, high temperature nitridation before the high dielectric constant (k) deposition is needed to prevent bottom electrode oxidation during the high-k deposition. It is noted that a high dielectric constant (k) is above about 3.9.
The major concern is to eliminate native oxide and to increase capacitance. However, a high temperature anneal is not acceptable for embedded DRAM because logic performance will be degraded.
U.S. Pat. No. 6,580,115 B2 to Agarwal describes a capacitor electrode for integrating high-k materials (wherein high-k materials have a dielectric of greater than about 20).
U.S. Pat. No. 5,663,098 to Creighton et al. describes a method for deposition of a conductor in integrated circuits.
U.S. Pat. No. 4,751,101 to Joshi describes low stress tungsten films by silicon reduction of WF6.