1. Field of the Invention
The present invention relates to a data processing apparatus, data processing system, and access area control method and is particularly suitable to a data processing apparatus in which devices having different numbers of address signal lines are connected via an address bus.
2. Description of the Related Art
Conventionally, an information processing system in which a plurality of devices such as central processing units can access (can read out data from and write data in a memory) a memory area (memory space) composed of one or a plurality of memories exists. In one information processing system of this type, a plurality of devices are not connected to a memory bus for accessing a memory, but, as shown in FIG. 6, only a device 61 is connected to a memory bus 67. In this conventional information processing system shown in FIG. 6, another external device (not connected to the memory bus 67) 63 accesses a memory 62 via the device 61 connected to the memory bus 67.
As shown in FIG. 6, this information processing system comprises a central processing unit (CPU) 61, SDRAM (Synchronous Dynamic Random Access Memory) 62, external bus master 63, ROM 64, RAM 65, and input/output buffer (I/O) 66.
The CPU 61 has a CPU core 70 for performing arithmetic processing, an SDRAM controller 71 for performing data write and read to the SDRAM 62, and an external bus controller 72 for exchanging data with the external bus master 63 and the like. The CPU core 70, SDRAM controller 71, and external bus controller 72 are connected to an internal bus 73.
Also, the SDRAM 62 and the SDRAM controller 71 are connected via an SDRAM bus 67, and the external bus master 63 and the external bus controller 72 are connected via a general-purpose bus 68. This general-purpose bus 68 is connected to the ROM 64, RAM 65, and input/output buffer 66.
Referring to FIG. 6, examples of signals exchanged between the CPU 61 (external bus controller 72) and external bus master 63 through the general-purpose bus 68 are indicated by the dotted lines. These signals includes, e.g., a bus request signal BREQ#, a bus grant signal BGRNT#, an address signal A<31:0>, a data signal D<63:0>, a SDRAM select signal SDSEL#, and a read/write signal RW#.
“(Signal name)#” indicates that the signal is activated at low level, and “(signal name)<X:Y>” indicates that the signal is transmitted through a plurality of signal lines in parallel. For example, the address signal A<31:0> indicates that this address signal is transmitted through 32 address signal lines in parallel with a width of 32 bits. The same rules apply to “(signal name)#” and “(signal name)<X:Y>” hereinafter.
In the information processing system shown in FIG. 6, operations when the CPU 61 (CPU core 70) and external bus master 63 access the SDRAM 62 will be explained below. In the following explanation, each address bus width of the general-purpose bus 68 and internal bus 73 is 32 bits.
<When CPU 61 (CPU Core 70) Accesses SDRAM 62>
The CPU core 70 outputs the address signal (address value) and read/write signal to the internal bus 73. The SDRAM controller 71 detects that the address signal supplied via the internal bus 73 indicates a memory space in the SDRAM 62. On the basis of the supplied address signal and read/write signal, the SDRAM controller 71 controls the SDRAM bus 67 to access the SDRAM 62. This allows the CPU core 70 to access the SDRAM 62.
<When External Bus Master 63 Accesses SDRAM 62>
First, the external bus master 63 activates the bus request signal BREQ# and requests the CPU 61 (external bus controller 72) to issue the bus use right (to be simply referred to as the “bus right” hereinafter) of the general-purpose bus 68. In response to this request, the external bus controller 72 activates the bus grant signal BGRNT# and gives the external bus master 63 the bus right.
When acquiring the bus right of the general-purpose bus 68, the external bus master 63 activates the SDRAM select signal SDSEL# which indicates access to the SDRAM 62. In addition, the external bus master 63 outputs the address signal A<31:0> and read/write signal RW# to the general-purpose bus 68.
On the basis of the SDRAM select signal SDSEL#, the external bus controller 72 detects the access request from the external bus master 63 to the SDRAM 62. The external bus controller 72 outputs, to the internal bus 73, an address signal and read/write signal corresponding to the supplied address signal A<31:0> and read/write signal RW#, respectively. In addition, on the basis of these address signal and read/write signal supplied via the internal bus 73, the SDRAM controller 71 controls the SDRAM bus 67 to access the SDRAM 62.
As described above, access from the external bus master 63 to the SDRAM 62 is realized via the CPU 61. That is, access from the external bus master 63 to the SDRAM 62 is executed by a “transparent mode access function” by which the CPU 61 accesses the SDRAM 62 via the SDRAM bus 67 in response to a request from the external bus master 63.
In this “transparent mode access function”, in response to a request from an external bus master (the external bus master 63) connected to an external bus (the general-purpose bus 68), a first bus master (the CPU 61) accesses a resource (in the above explanation, the SDRAM 62) which the external bus master cannot directly access and which is mapped in the memory space of the first bus master, thereby executing access from the external bus master to the resource. The access from the external bus master to the resource mapped in the memory space of the first bus master, which is realized by the transparent mode access function described above, is called “transparent mode access”.
In the above conventional information processing system shown in FIG. 6, however, if the address bus width of the external bus master 63 with respect to the general-purpose bus 68 is smaller than the address bus width of the CPU 61, transmission mode access can be performed only to a partial area fixed in accordance with the address width of the external bus master 63 and cannot be performed for an arbitrary area. For example, when the address bus width of the external bus master 63 is 8 bits, the external bus master 63 can perform transmission mode access only to an area from “0000 0000 h” to “0000 00FF h” in the memory space of the CPU 61 (“h” indicates the hexadecimal notation, and the same shall apply hereinafter). Therefore, to allow the external bus master 63 to perform transparent mode access to an arbitrary area in the memory space, a new external circuit (device) must be formed. This increases the external circuit scale and complicates the wiring between the devices.
Also, if the address bus width of the external bus master 63 with respect to the general-purpose bus 68 is equal to the address bus width of the CPU 61, the whole memory space of the CPU 61 can be subjected to transparent mode access. Accordingly, if an access inhibited area which inhibits access from the outside is necessary in the memory space, an external circuit (device) for limiting input address signals must be formed. This increases the external circuit scale and complicates the wiring between the devices.