The present invention relates to a memory circuit, and more particularly to a dynamic memory circuit having a plurality of memory cell arrays.
The storage capacity of semiconductor memory devices has been becoming greater and greater, and efforts are being made to increase the integration density of integrated circuit chip.
However, if such increase in the storage capacity is achieved by simply increasing the number of memory cells coupled to each word line, the storage capacitance of each word line would become large, resulting in low speed operation.
Furthermore, in the case where the memories are of dynamic type, the written information disappears when a predetermined time has elapsed. Therefore, it is necessary to execute a rewriting cycle called "refresh" within the above time. The refresh is done on the respective word lines one by one and hence, the number of the word lines in the memory corresponds to the cycle times of refresh within the predetermined period of time.
Under the above circumstance, it has been practiced that the memory cells are divided into two or more memory cell arrays each having word lines to which reduced number of memory cells are coupled. In such construction, refresh operations are executed in the respective memory cell arrays in parallel, reducing the time required for refresh for the whole memory cells.
For example, memory cells of a 64 K-bit dynamic RAM are arrayed in two memory cell arrays each having 128 word lines and 256 bit lines, and the whole memory cells are refreshed through 128 refresh cycles. In this kind of memories, one word line in each memory cell array is driven and two word lines are simultaneously driven as a whole in the memory in response to the same driving pulse. Accordingly, the drive circuit for generating the driving pulse is required to have a large driving capacity in order to attain high speed operation. Moreover, since two word lines are driven at the same time to be charged to a power voltage, a large value of peak current necessarily flows to the two word lines through the drive circuit. This peak current causes noise and affects the memory operation, resulting in malfunction.