1. Field of the Invention
The present invention relates to a semiconductor process, and more particularly to a method of fabricating a semiconductor device and a method of adjusting a lattice distance in the device channel region.
2. Description of the Related Art
In the early days, a metal-oxide-semiconductor (MOS) device is composed of a metal gate electrode, a gate dielectric layer, and a semiconductor substrate. Because the adhesion of most metals to silicon is unsatisfactory, currently, the material of the gate electrode is polysilicon. The application of a polysilicon gate electrode, however, incurs other issues. For example, the device performance decays due to the high resistance of the polysilicon. Accordingly, with the present technology, after forming the device, a salicide process is performed to form metal silicide on the gate electrode and the source/drain regions to reduce the resistance of the device.
In another aspect, a chip usually comprises a device area and a peripheral circuit area, wherein, devices in the device area include, for example, memory devices, and electro-static discharge (ESD) protection circuits. Devices in the peripheral circuit area comprise, for example, logic devices. The devices in the device area require high resistances than those in the peripheral circuit area. During the salicide process above, a block layer is used to cover the area on which the metal silicide is not going to be formed. Because the area covered by the block layer does not require additional film layer to prevent the formation of metal silicide, the block layer is also called a self-aligned salicide block layer (SAB) layer.
FIGS. 1A-1E are schematic cross sectional views showing the progression of a prior art method of fabricating a semiconductor device. Referring to FIG. 1A, a substrate 100 is provided. The substrate 100 includes a device area 102, and a peripheral circuit area 104. Gate structures 106 and 108 are formed over the substrate 100 of the device area 102 and the peripheral circuit area 104, respectively. Lightly-doped regions 110 and 112 are formed in the substrate 100 and adjacent to the sidewalls of the gate structures 106 and 108.
Referring to FIG. 1B, after forming spacers 114 on the sidewalls of the gate structures 106 and 108, the source regions 116a and 118a, and the drain regions 116b and 118b are formed in the substrate 100 and adjacent to the spacers 114. An anneal process 120 is performed to the source regions 116a and 118a, and the drain regions 116b and 118b. 
Referring to FIG. 1C, an SAB layer 122 is formed over the substrate 100, covering the gate structures 106 and 108, and the exposed surface of the substrate 100.
Referring to FIG. 1D, the SAB layer 122 in the peripheral circuit area 104 is removed, and the SAB layer 122a in the device area 102 is reserved. A metal layer 124 is then formed over the substrate 100, covering the SAB layer 122a, the gate electrode 108, and the exposed surface of the substrate 100.
Referring to FIG. 1E, a thermal process is performed so that a portion of the metal layer 124 reacts with silicon under the metal layer 124 to form a metal silicide layer 126. The unreacted metal layer 124 is then removed.
In the process described above, the formation of the metal silicide layer can solve the problem of high resistance of the device. However, when the size of the device shrinks, the lattice distance in the channel region 128 seriously affects the electron mobility. The lattice distance becomes an essential factor in determining the device performance.