1. Field of the Invention
The present invention relates to semiconductor products reliability testing and, more particularly, to semiconductor reliability test chips for testing standard and ASIC semiconductor packages.
2. Background and Related Art
During the course of qualifying packages and modules, it is customary to run standard stresses to predict reliability of the packaged semiconductor products under field conditions. Typically, the reliability of the semiconductor packages is tested by subjecting them to a variety of life accelerating environments over a period of time until product failure or minimum requirements are met. The packages are then inspected and tested in an attempt to determine the cause of failure. Since there can be many reasons for failure, the analyses of the failure can be lengthy and difficult. Attempts have also been made to design semiconductor test chips to assess specific types of failure of the product.
For example, an article by J. S. Sweet, entitled “The Use of Special Purpose Assembly Test Chips for Evaluating Reliability In Packaged Devices”, published by Sandie National Laboratory, pages 15–19, describes some of these types of chips. The article describes a series of individual special purpose assembly test chips to aid in assessing the reliability of packaged integrated circuits. The special purpose assembly test chips contain special purpose circuits or sensors which enhance the detection of failures or detect moisture, detect mobile ions, or other contaminants which can lead to failure of the semiconductor component.
Other special purpose test chips have been designed to aid in assessing the reliability of a variety of specific types of failures of semiconductor packages. For example the U.S. Pat. No. 6,538,264 to Corbett, et al. describes a test chip with a plurality of test functions, such as, bond pad pitch and size effects on chip design, wire bond placement accuracy, bond pad damage below the bond pad during bonding (cratering), street width effects, thermal impedance effects, ion mobility evaluation and chip on board in flip chip application test capabilities.
Test chips for flip-chip packages, such as described by Corbett, et al., using C4 solder ball technology have thus taken a variety of forms. The need to verify C4 integrity as part of the chip/package/interconnect qualification is an important product requirement. This requirement has become more important with the advent of organic C4 chip packages. In this regard, it has been found that certain product design features will result in early reliability stressing failures. Thus, to provide the most effective testing process, it is necessary to design the chip/package/interconnect qualification packages as closely to product as possible to avoid having to address, either failures in features that do not appear in the product, or failure to stress features that do exist in the product that may ultimately fail. One of the major stresses that cause failures in organic flip chip packages is the thermal mismatch in CTE between the flip chips and organic substrate. Such thermal mismatch causes stress and, potentially, fatigue at the C4 interconnect initiating fracture and cracking of the C4 bonding, for example, resulting in connection failure. In this regard, it is known that this stress is proportional to the distance from neutral point (DNP) of a particular C4 solder ball connection.
One approach to stressing packages to test for fatigue leading to fracture and cracking of C4 connections due to thermal mismatch is to cyclically heat the packaged chip using electrically resistive heaters in the chip to simulate product thermal cycling. This can be accomplished by designing a test chip with a large resistive heater in the chip M1 metal layer. Such a heater is typically wired through a small number of C4 connections. With a small number of connections and with the need for increased heat and power, there is concern with the resistive heating of the relatively narrow package signal traces such as to potentially introduce excessive temperature induced failures that would not exist in the product. Alternatively, designing the package wires as heavy power supplies connected to signal C4 positions represents a nonstandard feature in the package that does not represent product.
A conventional approach to testing for the reliability and integrity of C4 interconnections between chip and substrate is to employ a continuity-type testing procedure. An example of such an approach is that employed by Corbett, et al. supra wherein metal wire stitch lines are employed to connect selected C4 pads on the chip together and substrate or board level wiring is used to connect all wiring in a daisy chain approach. Thus, the resulting structure has a concatenation of board wire, package wire, chip wire, board wire, etc. While this approach has the advantage of allowing a large number of connections to be tested with one circuit, it has the disadvantage that should there be fatigue or fracture in one of the interconnections being monitored causing a change in resistance, for example, such change can easily be lost in the larger overall resistance of the single circuit interconnecting all of the interconnects.
In this regard, it is known that small changes in resistance are indicative of C4 fatigue and crack initiation. Accordingly, it is advantageous to test for fatigue and crack initiation using a low resistance circuit approach such as to allow easy and ready identification of the connection exhibiting fatigue and crack initiation.
A further limitation of prior art approaches is that the array of pads on the test chip used for testing covers a small area of the chip, and the array of pads is typically near the center of the chip thus discounting the contribution to stress that would be expected for high DNP C4's.
Accordingly, the test chip should be made to replicate the product that it is representing as closely as possible. To this end, it is undesirable to wire out all of the C4 pads to the chip substrate or PCB. In this regard, most product chips require power connections that are handled via the power planes of the package. Thus, to maintain the mechanical properties of the package, it is advantageous to design the test package such that signal and power structures look like the product design. It should be noted that, the highest DNP C4's are typically power and ground connections, particularly in application specific footprints.