The present invention relates to methods and apparatus for data transmission. More particularly, the invention relates to architectures and techniques for implementing a common transceiver design that enables data transmission in any of the three standards: 100BaseT2, 100BaseTX, and 100BaseT4.
In modern data networks, e.g., computer networks, there exist multiple standards for data transmission. There are, for example, currently three standards for transmission of 100 Megabits per second (Mbps) over copper twisted pairs up to a length of 100 meters in an Ethernet Carrier Sense Multiple Access with Collision Detection (CSMA/CD) local area network. These standards are 100BaseT2, 100BaseT4, and 100BaseTX. Each of these standards has its advantages and disadvantages. For example, the 100BaseTX standard permits the use of lower cost circuitry over more expensive wiring while the 100BaseT2 standard requires more complex and thus expensive circuitry over cheaper wiring. The 100BaseT4 standard is generally thought of as being somewhere in the middle. The physical level interface for each standard is thus different, and therefore a physical device (PHY) that supports one of the standards is not inter-operable with a device that supports another standard.
At the start of a channel link, a common protocol, termed "auto-negotiation," is initiated in order to identify the nature of the standard that is supported by the device at the other end of the transmission channel. By way of example, auto-negotiation may be performed between a network "hub" and the network interface card (NIC) of a terminal, which is attempting to communicate with the hub, to ascertain the standard with which the network interface circuitry communicates. If the devices at opposite ends of the channel are not compatible, a link is either not possible, or more practically, the link may be "negotiated" down to a 10BaseT interface, which is a 10 Mbps link.
FIGS. 1 and 2 are prior art illustrations showing respectively the transmission architecture associated with the 100BaseT2 standard and a typical transceiver architecture therefor. Referring to FIG. 1, the 100BaseT2 standard typically employs only two pairs of copper wires, 102 and 104. Over each pair, data transmission takes place at full-duplex, with a bit rate of about 50 Mbps, a baud rate of about 25 Mega bauds per second (MBps). The analog-to-digital (A/D) sampling rate (e.g., on A/D 106 or 108) is about 75 Mega samples per second (Msamples/sec), as is the digital-to-analog (DAC) sampling rate (e.g., on DAC 110 or 112). The sampling rate, as is known, may represent any integer multiple of the baud rate.
FIG. 2 shows the 100BaseT2 transceiver architecture from one end of the channel link. The 100BaseT2 standard employs digital processing techniques, implemented by DSP block 114 in FIG. 2, to compensate for, among others, cable distortion and to perform cross-talk suppression. For each of the full-duplex twisted pair links, the physical device (PHY) dedicates one Digital to Analog Converter (DAC), one transmit filter (Tx filter), one Analog to Digital Converter (A/D), and one receive filter (Rx filter). The transmit and receive filter pairs (Tx/Rx filter pairs) for channels 102 and 104 are shown in FIG. 2 as Tx 116/Rx 118 pair and Tx 120/Rx 122 pair, respectively. As mentioned earlier, the A/Ds and DCs typically sample at 75 MHz, and the signals in the analog filters contain components up to around 25 MHz. In the DSP block the device may also contain two Echo/Near End Cross-Talk Cancellers and Two Equalizers (conventional and not shown in FIG. 2). This digital circuitry also operates typically at 75 MHz. Transformers 124 and 126 are employed to conform the data to the requirements of the standard, which is a conventional technique. Note that a 100BaseT2 transceiver has two of each analog circuit elements required to perform receive and transmit.
FIGS. 3 and 4 are prior art illustrations showing respectively the transmission architecture of the 100BaseTX standard and a typical transceiver architecture therefor. Referring to FIG. 3, the 100BaseTX standard also employs only two pairs of copper wires, 132 and 134. Over each pair, data transmission takes place at only half-duplex, with one pair carry data from master to slave and the other from slave to master. The bit rate is about 100 Mbps, and the baud rate is typically about 125 Mega bauds per second (MBps), which includes coding required for DC control and other signaling functions. The A/D sampling rate (e.g., on A/D 136) is typically at the baud rate, i.e., about 125 Msamples/sec, as is the DAC sampling rate (e.g., on DAC 140).
FIG. 4 shows the 100BaseTX transceiver architecture from one end of the channel link. The 100BaseTX standard also employs digital processing techniques, illustrated in FIG. 4 as DSP block 144, to also compensate for, among others, cable distortion. Since the environment in which the 100BaseTX standard is employed is typically less harsh than that associated with the 100BaseT2 environment, e.g., there is typically lower cross talk and little, if any, echo, the set of DSP functions in DSP block 144 is typically less complex than those implemented in DSP block 114 of the 100BaseT2 architecture. However, the higher sampling rate (i.e., 125 Msamples/sec versus 75 Msamples/sec) requires higher performance A/Ds and DACs in the conventional 100BaseTX implementation.
FIGS. 5 and 6 are prior art illustrations showing respectively the transmission architecture of the 100BaseT4 standard and a typical transceiver architecture therefor. Referring to FIG. 5, the 100BaseT4 standard employs four pairs of copper wires, 160, 162, 164, and 166. On pairs 164 and 166, the transmission is full duplex, and is half duplex on pairs 160 and 162. The bit rate is about 33.33 Mbps, and the baud rate is typically about 25 Mega bauds per second (MBps). The A/D sampling rate (e.g., on A/D 170, 172, or 174) is typically at 50 Mega samples/sec, as is the DAC sampling rate (e.g., on DAC 176, 178, or 180).
FIG. 6 shows the 100BaseT4 transceiver architecture from one end of the channel link. The 100BaseT4 standard also employs digital processing techniques, implemented in FIG. 6 by DSP block 182, to also compensate for, among others, cable distortion and to perform cross-talk suppression. The 100BaseT4 standard employs more pairs of wires at a lower baud rate than the 100BaseT2 standard, and the impairments are less severe than those seen in the 100BaseT2 implementation. Consequently, the set of DSP functions in DSP block 182 is typically less complex than those implemented in DSP block 114 of the 100BaseT2 architecture.
In the prior art, a transceiver is typically custom designed to transmit and receive in only one of the three standards. In other words, a given transceiver, such as that illustrated in one of FIGS. 2, 4, and 6, is not inter-operable with devices, hubs, or network interface cards (NIC) that adhere to a different standard or multiple standards. Consequently, it is typically necessary to design, manufacture, stock, and support different transceivers for different standards. Additionally, when transceivers are implemented as integrated circuits, the prior art custom approach involves a substantial chip die size overhead. By way of example, to implement 100BaseT2 and 100BaseTX, the prior art custom approach would require 50% more die size, and in order to implement 100BaseT4 with 100BaseT2 and/or 100Base TX, the prior art would require 80% to 100% more die size. As can be appreciated, this approach involves a substantial amount of design and manufacturing effort and expense.
In view of the foregoing, there is desired a common denominator transceiver architecture and methods therefor that support all three 100 Mbps standards: 100BaseT2, 100BaseTX, and 100BaseT4. To reduce manufacturing and implementation costs, the common denominator transceiver architecture and methods therefor preferably allow, with minor modifications, circuits of the common denominator transceiver architecture to be reused when implemented to support different standards.