A switching network includes a core module in a router and other data switching devices, and performs switching on a data packet or cell between multiple ports, that is, switches a data packet or cell, where the data packet or cell arrives at an input port, to a corresponding output port. A basic requirement on the switching network is that switched data packets and cells are required to keep an original order. As shown in FIG. 1, in a K-plane multi-level switching network in the prior art, normally a cell may arrive at a destination port through multiple paths, but it is very difficult for a time delay of each of the paths to be completely the same, which incurs an out-of-order phenomenon when cells that belong to a stream (from a same input port to a same output port) arrive at the destination port. The input port may be a source line card, and a component on the source line card, where the component on the source line card is directly related to the present invention, is an FIC (Fabric Interface Chip, switching network interface chip). The FIC performs processing on a data packet together with a switching network chip. An upstream FIC generally receives a slice of a variable-length data packet from a network side, and manages a virtual output queue (VOQ). The FIC may also include TM (Traffic Management, a traffic management function). An output port of the upstream FIC is a network card, and the network card includes mutually-independent switching chips or switching units. By taking a Clos interconnected multi-level switching network as an example, a switching chip may be formed by three levels, that is, switching units of three levels S1, S2, and S3. As shown in FIG. 2, a cell C1 departs from an FIC1, passes through an S1/3(2) and an S2(2), returns to an S1/3(2), and arrives at an FIC2; a cell C2 departs from the FIC1, passes through an S1/3(1), an S2(1), the S2(2), and the S1/3(2), and arrives at the FIC2; and a cell C3 departs from the FIC2, passes through the S1/3(1), the S2(2), the S2(1), and the S1/3(1), and arrives at the FIC1. If the cell C2 is sent first, and then the cell C1 and the cell C3 are sent at the same time, the cells C1 and C3 which are sent later may arrive at the S2(2) earlier than the cell C2 which is sent earlier, or the cells C1 and C3 which are sent later and the cell C2 which is sent earlier may arrive at the S2(2) at the same time, so that in this case an out-of-order problem occurs at the S2(2).