1. Field of the Invention
This invention pertains to the field of bit-mapped alphanumeric and graphic processors, or bit-mapped raster scan video controllers, and in particular to the logic and circuit necessary to implement a variety of strategies for sharing access to display memory among a number of processes under the programmable control of the raster scan video controller. The invention is useful for high and low performance CRT systems, black/white or color, especially those capable of accessing display memory as needed to create and update an image on a video display.
2. Description of the Prior Art
Most presently available video display systems typically include a processor, a video controller, a display memory containing a single current screen image, other system memory, and a raster scan video display. In normal (steady-state) operation, the video controller continually reads out the contents of the display memory and transforms the information read out to the signalling necessary to control the raster scan beam while it is in its active display time. The video controller also provides the horizontal and vertical retrace signalling at appropriate intervals, and blanking of the raster scan beam during retrace.
The processor also has access to the display memory, so that it can change the current screen image. This access may be "through" the video controller or "around" it. The subject invention applies to the former type of system. In either case, use of the display memory is typically carefully controlled between updating and display accesses, to prevent breakup of the video image while it is being changed.
In bit mapped display systems, display memory must be accessed by or shared among (1) the display process that keeps the image on the CRT and one or both of: (2) a dedicated hardware engine that updates or changes the image; and/or (3) a microprocessor that updates or changes the image. Existent CRT controllers typically adopt a fixed strategy for the sharing--either alternating accesses between (1) and (2) and/or (3), and/or allowing 2 and/or 3 access during retrace or blanking times. In most prior art systems, the allocation of display memory accesses between the display process and updating is external to the video controller. The two types of accesses are kept physically separate by logical circuits such that the allocation is fixed and not subject to change.
Depending on the timing of the various parts of the system, the display memory may be available for updating a) only during vertical retrace periods, or b) during horizontal and vertical retrace periods, or c) during retrace periods plus alternating memory cycles during the active display time of scan lines. In any of these cases, however, updating of display memory typically proceeds at a rate slower than could be achieved without interference from the video controller's display accesses.
The invention is a mechanism by which a raster scan video controller can be programmed for any of a variety of sharing strategies, in accordance with application requirements.
Another object of the present invention is to improve performance of a raster scan display system because the update and video operations can occur simultaneously in many cases.