The present invention relates to an improved method and apparatus for interconnecting large scale integrated (LSI) circuits and, more particularly, associative techniques for interconnecting LSI elements on a wafer to enable wafer scale integration.
Present methods of semiconductor fabrication typically require that a plurality of identical semiconductor elements or circuits be fabricated on a single wafer substrate by a series of process steps. At the conclusion of this fabrication process, the elements or circuits are tested and the defective elements identified. The wafer is then scored and diced into individual parts, each containing a complete circuit. Finally, the operable parts are packaged to provide external electrical connections and appropriate environmental protection.
It has long been realized that circuit costs as well as space and power requirements could be reduced if the operable parts or elements on the wafer could be interconnected on the wafer itself. This would reduce the necessity for circuit boards and interconnection wiring between elements, which would, in turn, result in a decrease in space and cost.
A variety of methods for interconnecting elements on a wafer have been suggested. One method is to add another metalization step after the circuits or elements of the wafer are tested to interconnect the operable element on the wafer. The difficulty with this method is that a different mask is required for each individual wafer, greatly increasing the cost of the finished product.
Another method is the inverse of the discretionary wiring concept attempted in the 1960's to achieve LSI circuits with small scale integrated and medium scale integrated circuits. Usually, the arrays to be connected are storage arrays. Each array consists of a storage portion, an address mechanism for accessing the data and a permanent disconnection mechanism. The permanent disconnection mechanism is accomplished by blowing a fuse, or charging up a floating gate MOS (FAMOS) device, or laser burnout, etc. The disconnection isolates a defective array from the wafer bus so that the defective arrays do not interact adversely with the operative arrays. Although this method is suitable for wafer scale integration, it is limited in application. It requires a hardwired decoder and does not permit reconnection of the spring of arrays for increased reliability.
Another wafer integration scheme, as described in U.S. Pat. No. 3,940,740, provides for spare rows and columns on the wafer matrix for appropriate sparing in case of defective elements. One disadvantage of this configuration is that an entire row of elements must be provided, in the worst case, to spare a single defective matrix element. A preferred method would be one where spare elements can be inserted into the matrix on a random basis to allow all spare elements to be used.
In addition, all of these methods require extensive decoding circuits and uniquely dedicated decoding bus lines for element enable, which reduce the usable area of the wafer and add possible failure sites. Because of these reasons, wafer scale integration is seldom achieved.
What is required is a wafer scale integration configuration wherein a relatively small number of spare elements and a relatively simple decoding circuit are employed to obtain high reliability and high functional circuit density at the wafer level.
It is also an object of this invention to allow the replacing circuit element to assume the address of the replaced element so that the system need not be reprogrammed after the replacement.