1. Field of the Invention
This invention relates to technology of manufacturing a semiconductor device. More especially, this invention relates to a set of masks, a method of generating mask data and a method for forming a pattern.
2. Description of the Related Art
In recent years, with the trend toward higher integration of large scale integrated circuits (LSIs), there has been a demand for finer circuit patterns of LSIs. As examples, for a transistor in a microprocessing unit (MPU), an application specific integrated circuit (ASIC), a system LSI, or the like, there is a demanded for a pattern to be delineated with fine line widths of 100 nm or less.
As a method for forming a pattern with fine line widths, there is a known method in which a resist pattern with fine line widths is formed using a positive alternating phase shift mask (Levenson-type phase shift mask) where phase contrasts of adjacent openings are shifted from each other by 180 degrees, and any unnecessary part of the resist pattern is removed using a trim mask. Moreover, as another method for forming a pattern with fine line widths, a method has been studied in which isotropic etching is performed after the formation of a resist pattern, thereby slimming the line widths of the resist pattern.
Here, for example, as to a pattern of a memory cell of a SRAM or the like which coexists with a logic circuit, demand for the pattern have fine space widths in addition to fine line widths in order to reduce the circuit space. In the case of using a positive alternating phase shift mask (Levenson-type phase shift mask), it is required to form fine space widths when a trim mask is used. However, the resolution of a trim mask is low, and it is therefore difficult to form fine space widths in a resist pattern. Moreover, in the case of performing isotropic etching after the formation of a resist pattern, the space widths between the lines of the resist pattern are increased when the line widths of the resist pattern are slimmed. Therefore, it is difficult to delineate a circuit pattern which has fine line widths and fine space widths at the same time.