1. Field of the Invention
This invention relates to reduced dimension MOS field effect transistors and to the formation of field effect transistors having narrow gate electrodes and reduced dimension source/drain structures.
2. Description of the Related Art
Field effect transistors, generally referred to as FETs or MOSFETs, are the most common devices in modern integrated circuit devices. One conventional configuration of a FET is illustrated in FIG. 1. Field isolation regions 12 are formed by the local oxidation of silicon (LOCOS) method at the surface of a substrate 10, defining the active device regions and providing lateral isolation between adjacent devices formed in and on the surface of the substrate 10. A gate oxide layer for the FET covers the active device regions of the substrate 10 and a gate electrode 16 of doped polysilicon is formed on the gate oxide layer 14. Oxide spacer structures 18 are generally provided on either side of the gate electrode 16. The inner edges of source/drain regions 20 define a channel region at the surface of the substrate, with a source/drain region extending from either side of the gate electrode 16 to the field isolation regions 12. Frequently, the source/drain regions 20 have a lightly doped drain (LDD) structure in which an inner, more lightly doped portion of the source/drain region is aligned with the edge of the gate electrode 16, and a more heavily doped portion of the source/drain region 20 is aligned with the oxide spacer structure 18. A P-pocket or halo implant 22 extends slightly below and toward the FET channel from each of the LDD source/drain regions. The P-pocket or halo implant reduces the short channel effects in the FIG. 1 FET.
Generally, the FET structure shown in FIG. 1 is prepared by first forming a field isolation mask on the surface of the substrate 10, with openings in the mask exposing the substrate over regions where the field isolation structures will be formed. The field isolation structures are then formed either using a local oxidation of silicon (LOCOS) process, as illustrated, or a shallow trench isolation method. The field isolation mask is then stripped and various implantations may be made into the active regions of substrate 10 to adjust the doping profile of the substrate within the active regions. A gate oxide layer 14 is then grown on the cleaned surfaces of the active regions of the substrate 10. Polysilicon is blanket deposited by a low pressure chemical vapor deposition (LPCVD) technique over the gate oxide layer and the field isolation regions. The polysilicon layer is doped, typically by ion implantation, and photolithography is used to define gate electrodes 16 over the active regions. The source/drain regions 20 are formed in a two-stage implantation process. A first ion implantation is made using the gate electrode and the field isolation regions to mask the substrate, forming the more lightly doped portions of the LDD source/drain regions 20. A layer of CVD oxide is then deposited over the gate electrodes and over the surface of the device. An etch back process forms spacer structures 18 from the CVD oxide layer on either side of the gate electrode 16. A second ion implantation is performed to form a more heavily doped region aligned to the oxide spacer structures 18 and completing the source/drain regions 20. In the illustrated NMOS device, the source/drain regions 20 may be doped with any N-type dopant or combinations of different N-type dopants might be used to achieve different diffusion profiles. Finally, the P-pocket region 22 is formed by angular ion implantation of boron ions with the implantation made so that the ion flux is at an angle of approximately 30.degree. from normal (perpendicular) to the substrate.
Improvements in device density and reductions in the cost of manufacturing integrated circuits are closely linked to reducing the size of devices within the integrated circuits. The width of gate electrode 16, as well as the sizes of other device structures, are determined by conventional lithography processes. Shrinking the size of the FET shown in FIG. 1 generally cannot proceed beyond the resolution and alignment limitations of the particular process technology used in forming the FIG. 1 device. Thus, the width of the gate electrode 16 is typically designed to be a width d equal to the design rule for the particular process used in making the gate electrode. Further reductions in the size of the gate electrode are desirable to decrease device size and to improve the density of the integrated circuit. Adoption of higher resolution lithography techniques, which could facilitate forming smaller gate electrodes, is very expensive, and may only be economically justified for very high volume manufacturing. Smaller volume manufacturing operations and specialty or low-profit margin circuits might not cost effectively implement such high cost processes. Thus, even with the introduction of higher resolution lithography techniques, it may be difficult to further reduce the size of the FIG. 1 FET.
Another disadvantage of the device illustrated in FIG. 1 and of the method of making the device is that the source/drain electrodes require a significant implantation to ensure that their resistance is sufficiently low to provide good device performance. The required high level of ion implantation causes a variety of problems. For example, the heavy ion implantation dosage renders the substrate amorphous where the source/drain regions are to be formed. Recrystallization of the substrate in the source/drain regions is then performed in an annealing process which can produce defects in the recrystallized material, or which can lead to excessive levels of diffusion from the source/drain regions. Excessive diffusion from the source/drain regions can make the channel region beneath the gate electrode 16 narrower than is desired, compromising device performance. A further disadvantage with the FIG. 1 structure is that the P-type halo implant 22 overlaps with a considerable portion of the source/drain region 20. This extended overlap is undesirable for a variety of reasons, including the size of the P/N junction formed between the halo implant 22 and the source/drain region 20, which impairs the FET's performance by reducing switching speeds.