Modern microprocessors may support branch predictors in their architectures. In a pipelined architecture, the branch predictors may permit the fetch and execution of instructions subsequent to a branch point before the actual resolution of the conditional branch by execution of the branch instruction. This permits enhanced throughput when the branch predictor issues a correct prediction. There are many methods and hardware implementations for these branch predictors, but none of them are proof from errors. The enhanced throughput when the branch predictor issues a correct prediction must be weighed against the branch misprediction penalty that accrues when the branch predictor issues an incorrect prediction. The branch misprediction penalty may include such costs as stalling the pipeline during the branch misprediction recovery time and the execution of instructions along the mispredicted path that are potentially wasted.
Often in programs the two paths (correct and incorrect) of a branch reconnect at a future point, which may be called a convergence point. It would appear that, if the branch was executed along a mispredicted path to a convergence point and beyond, the recovery could consist of re-executing only a portion of the instructions along correct path that were executed on the mispredicted path, and re-use the results of the rest of the instructions on the correct path that were executed on the mispredicted path subsequent to the convergence point. However, this could not generally be accomplished as the renamed physical registers could be contaminated with data from execution of the mispredicted path instructions between the mispredicted path and the convergence point.