Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (“PLDs”), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
Voltage-controlled oscillators (“VCOs”) are building blocks in many high performance analog circuits and systems. For example, VCOs are used in frequency synthesizers, clock multiplication units (“CMUs”), clock and data recovery (“CDR”) circuits, and phase-locked-loops (“PLLs”), among other circuits. VCOs have been implemented with CMOS. The benefits of leveraging high-volume CMOS fabrication for analog and RF devices would be useful. For example, it would be useful if such integration of VCOs was complete, namely forming a VCO entirely in a single-chip, such as in an SOC implementation for example. Some design considerations for VCOs are tuning range and jitter performance. In PLDs, these design considerations may be more stringent because a single PLD may be used to support multiple protocols and applications with different clock frequency performance parameters and with stringent jitter performance parameters.
Accordingly, it would be desirable and useful to provide a high gain varactor circuit capable of meeting stringent jitter performance parameters over a relatively large tuning range to provide a VCO suitable for an application where a single PLD supports multiple protocols and applications.
A VCO “tank” circuit is a well-known circuit for generating oscillations. VCO circuits, like the tank circuit, are known as LC VCOs, where the L and C respectively indicate inductor and capacitor. A tank capacitance “C” in an LC VCO is a combination of a fixed capacitance and a tunable capacitance. The tunable capacitance conventionally includes a varactor. However, a conventional varactor has a relatively limited capacitive range. Furthermore, as is known, CMOS processes may vary from time to time and thus a capacitance-voltage (“C-V”) curve may shift. Heretofore, such a process shift may reduce the useable range of the varactor capacitance.
Accordingly, it would be both useful and desirable to provide a varactor circuit that is programmable for a wide range of capacitances. Moreover, it would be useful and desirable to enhance a varactor's C-V curve gain beyond a device intrinsic C-V curve property. It would additionally be useful and desirable if such varactor circuit could be adjusted to offset process variation.