The present invention relates to an erasing method of a floating gate type nonvolatile semiconductor storage device.
In recent years, there has been a demand for reducing the power consumption in accordance with increase of integration level in a flash memory of a nonvolatile semiconductor storage device. In response to the above demand, a reduction in consumption of power is enabled by using the Fowler-Nordheim tunneling phenomenon for write (program) and erase operations. The flash memory that executes the write and erase operations utilizing the Fowler-Nordheim (referred to as FN hereinafter) tunneling phenomenon is called the FN--FN type flash memory.
On the other hand, flash memories are classified by the memory cell array structure, and four principal types will be enumerated hereinbelow.
[1] The Institute of Electronics, Information and Communication Engineers Technical Report, ICD93-128, p37, 1993
An AND type flash memory reported as ""AND" cell structure for a 3V-only 64Mbit Flash Memory"
[2] The Institute of Electronics, Information and Communication Engineers Technical Report, ICD93-26, p15, 1993
A DINOR type flash memory reported as "A Novel Cell Structure Suitable for a 3 Volt Operation, Sector Erase Flash Memory"
[3] IEDM Technical Digest, p263-266, 1995
A DuSNOR type flash memory reported as "A Novel Dual String NOR (DuSNOR) Memory Cell Technology Scalable to the 256 Mbit and 1 Gbit Flash Memories"
[4] IEDM Technical Digest, p267-270, 1995
An ACT type flash memory published in "A New Cell Structure for Sub-quarter Micron High Density Flash Memory" and "A sensing Scheme for a ACT flash memory" of The Institute of Electronics, Information and Communication Engineers Technical Report, ICD97-21, p37, 1997
The above types are published by several companies.
According to the flash memories of the above types [1] through [4], it is acceptable to execute electrical writing (program) and erasing on a memory cell. However, a voltage is applied to the drain, source or control gate of the selected memory cell in the write operation and the erase operation, while a voltage is also applied to the drain, source or control gate of the unselected memory cell. The threshold voltage of the unselected memory cell is changed by the influence of this voltage application, possibly causing erroneous reading
In recent years, there is an increasing trend toward using a method for applying a negative voltage to the semiconductor substrate (well) in order to reduce the absolute value of a voltage to be used inside the flash memory in the erase operation. This negative voltage applied to the semiconductor substrate brings the unselected memory cell whose drain, source or control gate receives the voltage into a lightly erased state, exerting bad influence (referred to as a substrate disturbance hereinafter) on the threshold voltage of the unselected memory cell. The substrate disturbance tends to become more severe as the flash memory comes to have a larger capacity.
The aforementioned substrate disturbance will be described by taking the ACT (Asymmetrical Contactless Transistor) type flash memory as an example.
FIG. 6 shows a sectional view of one memory cell of the above ACT type flash memory, and the principle of operation of the ACT type flash memory will be described with reference to FIG. 6.
In the above ACT type flash memory of FIG. 6, a tunnel oxide film 14, a floating gate 15, an interlayer insulating film 16 and a control gate 17 are lamellarly formed on a substrate (p-type well) 11 so as to form a bridge between a drain 13 and a source 12 formed on the substrate 11. Then, the drain 13 and the source 12 have different donor concentrations.
In the case of a program operation in the ACT type flash memory having the aforementioned construction, that is, in the case where electrons are extracted from the floating gate 15 to provide a written state (data "0"), a negative voltage Vnw (-8 V) is applied to the control gate 17 and a positive voltage Vpp (+5 V) is applied to the drain 13, thereby extracting electrons from the floating gate 15 by the Fowler-Nordheim (referred to as FN hereinafter) tunneling phenomenon with the source 12 brought into the floating state. By this a program operation, the threshold voltage of the memory cell is lowered to a voltage of about 1.5 V.
In the case of an erase operation, that is, in the case where electrons are injected into the floating gate 15 to provide an erased state (data "1"), a positive voltage Vpe (+10 V) is applied to the control gate 17, a negative voltage Vns (-8 V) is applied to the source 12, and the drain 13 is brought into the floating state. Electrons are injected into the floating gate 15 by the FN tunneling phenomenon. Therefore, the threshold voltage of the memory cell is increased to a voltage of about 4 V or more.
In the case of a read operation, a voltage of +3 V is applied to the control gate 17, a voltage of +1 V is applied to the drain 13, and a voltage of 0 V is applied to the source 12. The data is read by the sensing circuit (not shown) for sensing the current flowing through the memory cell.
The voltages applied to the memory cell in the program, aforementioned operations are shown in Table 1.
TABLE 1 Control Substrate Gate Drain Source P-Type Well Program -8 V 5 V Open 0 V Operation Erase 10 V Open -8 V -8 V Operation Read 3 V 1 V 0 V 0 V Operation
In order to explain the substrate disturbance in the erase operation, the application voltage in the erase operation will be described with reference to the array structure of the ACT type flash memory shown in FIG. 7. As schematically shown in FIG. 7, the array structure of the ACT type flash memory has a virtual-ground-type array structure in which two memory cells jointly own an identical bit line.
In the above ACT type flash memory are shown main bit lines BL0 through BL4096, sub-bit lines SBL00 through SBL04096 and SBL10 through SBL14096 formed from a diffusion layer (the sub-bit lines being in a layer different from that of the main bit lines), word lines WL0 through WL63, selection gate signal lines SG0 and SG1 of selection transistors ST00 through ST04096 for selecting each block and a contact section CN (the portions each being indicated by the mark .box-solid. in FIG. 7) of the main bit lines BL0 through BL4096 and the sub-bit lines SBL00 through SBL04096 and SBL10 through SBL14096. Then, in regard to the memory cells M00, M01, ... , M10, M11, ..., the number of contacts is reduced by making the memory cells of adjoining lines jointly own the sub-bit lines SBL01 through SBL04095 and SBL11 through SBL14095 and using the diffusion layer for the sub-bit lines SBL00 through SBL04096 and SBL10 through SBL14096, by which the array area is sharply reduced, allowing high-density integration to be achieved.
FIG. 8 schematically shows the sub-bit lines SBL00 through SBL04096 and SBL10 through SBL14096 (shown in FIG. 7) formed from the aforementioned diffusion layer in the form of a cross-section of the essential part of the ACT type flash memory.
As shown in FIG. 8, an interlayer insulating film 22, a floating gate 23 (FG) and a control gate 24 (WL) are lamellarly arranged on a semiconductor substrate 20 on which a sub-bit line 21 (diffusion layer) is formed. Then, the common sub-bit line 21 provided below the end portion of adjoining floating gates 23 (FG) has donor concentrations that differ between a drain 21a and a source 21b.
In the case of the aforementioned ACT type flash memory, the erasing operation is executed on a block basis. In the erase operation, for example, a positive voltage (+10 V) is applied to the word lines WL0 through WL31 connected to the control gates of the memory cells M00, M01, . . . of a selected block BLOCK0 shown in FIG. 7 in order to increase the threshold voltage of the memory cells. Further, a negative voltage (-8 V) is applied to a semiconductor substrate (well) and the main bit lines BL0 through BL4096. In this stage, the selection gate signal line SG0 has a voltage of 0 V to turn or the selection transistors ST00 through ST04096, and a negative voltage (-8 V) is applied to the sub-bit lines SBL01 through SBL04095. By this operation, a high electric field is generated between the floating gates and the channels of the memory cells M00, M01, . . . , by which electrons are injected into the floating gate by the FN tunneling phenomenon, increasing the threshold voltage of the n memory cells M00, M01, . . . to a voltage of 4 V.
On the other hand, in an unselected block BLCK1 in FIG. 7, a reference voltage Vss (0 V) is applied to the word lines WL32 through WL63. When a negative voltage (-8 V) is applied to the selection gate signal line SG1, then the selection transistors ST10 through ST14096 are turned off, as a consequence of which the sub-bit lines SBL10 through SBL14096 connected to the selection transistors ST10 through ST14096 are brought into the floating state. In this stage, the semiconductor substrate is common to all the memory cells. Therefore, the negative voltage (-8 V) is applied to the substrate, and an electric field is generated between the floating gate and the semiconductor substrate although the above electric field is less than that of the foregoing selected block. This electric field causes injection of electrons into the floating gate. The injection of electrons into the floating gate in the unselected block more frequently occurs in the memory cell in the low threshold voltage state, i.e., in the memory cell in the programmed state, i.e., in the memory cell of data "0".
Here is now considered the substrate disturbance in a 64-M flash memory in which 512 blocks each having a block size of 16 KB exist. If each block has been subjected to one million times of rewriting, assuming that each erasing time is 2 ms, then a disturbance time obtained by summing up the times applied to the unselected block in the above case is expressed by: EQU 511.times.1,000,000.times.2 msec .apprxeq.10.sup.6 sec (1)
FIG. 9 shows an example of the substrate disturbance in the erase operation. In FIG. 9, the horizontal axis represents the disturbance time, while the vertical axis represents the threshold voltage Vt (conditions:control gate voltage Vg of 0 V; drain Vd and source voltage Vs of floating; and substrate voltage Vsub of -8 V). As is apparent from FIG. 9, the threshold voltage of the memory cell becomes 3 V or more after a lapse of 10.sup.6 seconds of the disturbance time and becomes higher than the Ref voltage of 3 V of the sensing circuit in the reading stage, as a consequence of which data "0" is erroneously detected as data "1", resulting in erroneous reading.
A method for alleviating she substrate disturbance as described above is disclosed in the prior art reference of Japanese Patent Laid-Open Publication No. HEI 10-92958 concerning the AND type flash memory. In this specification, a description of the AND type flash memory will be given on condition that memory cell characteristics of this erasing method are similar to the characteristics of the aforementioned ACT type flash memory in order to clarify the problem of the erasing method of the non-volatile semiconductor storage device. That is, the application voltage conditions in the program operation and the erase operation are assumed to be similar to those of Table 1.
As shown in FIG. 10, an AND type flash memory has an array structure in which memory cells M00, M01, . . . , M10, M11, . . . are arranged in a matrix form, each of the memory cells being constructed of a floating gate type field-effect transistor capable of electrically writing and erasing information. Word lines WL0 through WL31 and WL32 through WL63 are connected to control gates of the memory cells M00, M01, . . . , M10, M11, arranged in an identical row. The memory cells M00, M01, . . . whose control gates are connected to the word lines WL0 through WL31 belong to a BLOCK0. The memory cells M10, M11, . . . whose control gates are connected to the word lines WL32 through WL63 belong to a BLOCK1. In the memory cells M00, M01, . . . of the BLOCK0, sub-bit lines SBL00 through SBL04094 are jointly connected to drains of the memory cells arranged in an identical column, while source lines SL00 through SL04094 are jointly connected to sources of the memory cells arranged in an identical column. Main bit lines BL0 through BL4094 are connected to the sub-bit lines SBL00 through SBL04094 via selection transistors ST00A through ST04094A, while a selection gate signal line DSG0 is connected to the gates of the selection transistors ST00A through ST04094A. A common source line SL is connected to the source lines SL00 through SL04094 via selection transistors ST00B through ST04094B, while a selection gate signal line SSG0 is connected to the gates of the selection transistors ST00B through ST04094B. In the memory cells M10, M11, . . . of the BLOCK1, sub-bit lines SBL10 through SBL14094 are connected to the drains of the memory cells of an identical column, while source lines SL10 through SL14094 are connected to the sources of the memory cells of an identical column. The main bit lines BL0 through BL4094 are connected to the sub-bit lines SBL10 through SBL14094 via selection transistors ST10A through ST14094A, while a selection gate signal line DSG1 is connected to the gates of the selection transistors ST10A through ST14094A. The common source line SL is connected to the source lines SL10 through SL14094 via selection transistors ST10B through ST14094B, while a selection gate signal line SSG1 is connected to the gates of the selection transistors ST10B through ST14094B.
In the AND type flash memory having the aforementioned construction, the case is herein considered where information of memory shells M00, M01, . . . , in the selected block BLOCK0 is subjected to erasing.
A high positive voltage Vpp (+10 V, for example) is applied to the word lines WL0 through WL31 of the selected block BLOCK0, and a voltage Vnv (-8 V, for example) is applied to all the main bit lines BL0 through BL4094 and a semiconductor substrate (well). A reference voltage Vss (0 V, for example) is applied to the source lines SL00 through SL4094 via the common source line SL. In this stage, the reference voltage Vss (0 V, for example) is applied to the selection gate signal line DSG0 and the voltage Vnv (-8 V, for example) is applied to the selection gate signal line SSG0. Then, the selection transistors ST00A through ST04094A whose gates are connected to the selection gate signal line DSG0 are turned on, so that the voltage Vnv (-8 V, for example) is outputted to the sub-bit lines SBL00 through SBL04094. The selection transistors ST00B through ST04094B whose gates are connected to the selection gate signal line SSG0 are turned off, so that the diffusion source lines SL00 through SL04094 are brought into the floating state. By this operation, the channels of the memory cells M00, M01, . . . of the selected block BLOCK0 are turned on, by which the channel layer comes to have a voltage of -8 V to inject electrons into the floating gate. Consequently, the threshold voltage of the memory cells M00, M01, . . . of the selected block BLOCK0 increases to end the erasing.
On the other hand, in the unselected block BLOCK1, the reference voltage Vss (0 V) is applied to the word lines WL32 through WL63 connected to the control gates of the memory cells M10, M11, . . . The voltage Vnv (-8 V) is applied to the selection signal gate line DSG1, so that the selection transistors ST10A through ST14094A whose gates are connected to the selection gate signal line DSG1 are turned off, and consequently the sub-bit lines SBL10 through SBL14094 are brought into the floating state. By applying the voltage Vcc (+3 V) to the selection gate signal line SSG1 and turning on the selection transistors ST10B through ST14096B whose gates are connected to the selection gate signal line SSG1, by which the reference voltage Vss (0 V) is outputted to the source lines SL10 through SL14094 formed from the diffusion layer via the common source line SL. By this operation, a depleted layer is formed instead of a channel layer in the semiconductor substrate (well) just below the tunnel oxide film of the memory cells M10, M11, . . . of the unselected block BLOCK1. For the above reasons, the electric field between the floating gate and the semiconductor substrate (well) is alleviated, by which the substrate disturbance is alleviated.
However, in the aforementioned AND type flash memory, some of the sub-bit lines SBL10 through SBL14094 in the floating state come to immediately have the voltage of -8 V when the voltage of -8 V is applied to the semiconductor substrate (well) due to the diffusion leak (including minute defects) and so on.
For example, the case is considered where a leak current of 0.1 .mu.A exists in the sub-bit line formed from the diffusion layer. This is because the threshold voltage of a memory cell is generally defined as the voltage of the word line when the current flowing through the memory cell is 1 .mu.A in the case of the flash memory, and there are practically many sub-bit lines through which the leak current of about 0.1 .mu.A flows. In the case of the flash memory, it is practical that the leak current of the diffusion layer is not so much reduced by comparison with the DRAM.
In this case, the voltage of -8 V is applied to the semiconductor substrate (well), and a time Ts during which the sub-bit line that should be in the floating state comes to have the voltage of -8 V is expressed by: ##EQU1##
where C: sub-bit line capacitance (0.02 pF)
V: sub-bit line voltage (-8 V) PA1 Ir: leak current (0.1 .mu.A) PA1 main bit lines each connected to an associated sub-bit line so as to form a layered structure together with the associated sub-bit line, wherein: in an erase operation of a selected block of the memory cell array, a first negative voltage is applied to the semiconductor substrate, a first positive voltage is applied to the word lines of an unselected block of the memory cell array, and a reference voltage is applied to the sub-bit lines of the unselected block so that memory cells in a low threshold voltage state within the unselected block are turned on, and that a channel layer formed in each of the memory cells which have been turned on comes to have the reference voltage.
Normally, the erase pulse time is about 1 ms, and therefore, the sub-bit line comes to sufficiently have the voltage of -8 V. In this case, the channel layer is formed in the vicinity of the sub-bit line, as a consequence of which a high electric field is generated between the floating gate and the channel layer (-8 V) in the portion, and electrons are injected into the floating gate, increasing the threshold voltage. In practice, when the memory cell channel layer is sufficiently turned on (i.e., when the channel layer is formed between the source and the drain), the source side of the sub-bit line, which is connected to the common source line SL, comes to have a voltage of 0 V, and therefore, the sub-bit line comes to have a voltage (-6 V, For example) higher than the voltage of -8 V, instead of the voltage of -8 V. However, if the sub-bit line comes to have a voltage higher than -6 V , then the channel layer is cut off by a back gate effect. Therefore, the sub-bit line does not come to have a voltage higher than -6 V (the absolute value is not reduced). The voltage of this sub-bit line differs depending on the threshold voltage and so on of the memory cell.
Therefore, the nonvolatile semiconductor storage device erasing method described above has an disadvantage that the substrate disturbance cannot be stably alleviated.