1. Field
This disclosure relates generally to semiconductor devices, and more specifically, to a 3-D semiconductor die structure with containing feature and method.
2. Related Art
When forming metal to metal die to die interconnections, corresponding pads of each die are sized large enough to overlay one another, taking account of placement misalignment. For large pads that are equally sized, bonding metal like tin (Sn) can run on the surface of the die, thus undesirably shorting adjacent interconnects not meant to be shorted.
There exists a problem of die movement after pick and place of die onto a wafer and during simultaneous bonding of die at the wafer level. The die movement can cause connect to connect shorting or misaligned opens during thermal compression die to wafer bonding.
Accordingly, there is a need for an improved method and apparatus for overcoming the problems in the art as discussed above.