In the manufacture of transistors in a semiconductor substrate, such as a silicon wafer, several steps are required to form the gates of the transistors. A first layer of a gate oxide, e.g., silicon oxide, is deposited over the silicon substrate to protect it. Next a conductive, doped polysilicon layer is deposited, optionally followed by a layer of a conductive material such as a refractory metal silicide. A cap layer of silicon oxide or silicon nitride, preferably a silicon oxide produced by the chemical vapor deposition from tetraethoxysilane (TEOS), is also deposited.
A typical gate stack is shown in FIG. 1A wherein a silicon wafer 12 has a layer of gate oxide 13 thereon, followed by a first gate layer of conductive, highly doped polysilicon 14. A second gate layer 15 of a refractory metal silicide, such as titanium silicide or tungsten silicide, and a cap layer 16 of silicon oxide are also deposited.
The gate stack must now be etched to form a gate between the areas in the substrate in which the source and drain will be formed. The silicon oxide hard mask layer 16 is coated with photoresist, the photoresist is patterned, and the silicon oxide layer etched in conventional manner to form a "hard mask". Suitably the etchant for the hard mask is a fluorine-containing gas such as CHF.sub.3, C.sub.2 F.sub.6, CF.sub.4 and the like.
FIG. 1B illustrates the gate stack after it has been etched, the same numerals used as in FIG. 1A for the same layers. The silicon oxide hard mask and the gate oxide layer remain, and the two conductive layers are etched.
As devices become smaller and are placed closer together, the gates become correspondingly thinner and narrower. Thus wet etch techniques have been largely replaced by dry etching, particularly plasma etching, because plasma etching is more anisotropic and thus does not undercut the gate, particularly at its intersection with the substrate. Also, plasma etchants can be used that are highly selective; that is, they etch certain materials faster than others. In the case of a gate stack, the etchant must etch the silicide layer and the polysilicon layer, but not silicon oxide; thus the cap layers and the initial gate oxide layers remain intact, as shown in FIG. 1B. Plasma processing is also favored because processing can be carried out at comparatively low temperatures that will not damage the substrate or previously formed devices.
Various vacuum chambers have been designed to carry out plasma etching. One particular design has been disclosed by Ogle in U.S. Pat. No. 4,948,458. The etch apparatus forms a magnetically coupled planar plasma for treatment of a substrate such as a silicon wafer. This apparatus comprises a chamber having a dielectric window. A planar coil is mounted proximate to the window, and an RF power source is coupled to the coil, generally through an impedance matching circuit to maximize power transfer, and a timing circuit to provide resonance at the operating frequency, typically 13.56 MHz. Process gas is supplied to the chamber through an inlet port. When the RF power is turned on, a planar magnetic field is induced which extends into the interior of the chamber through the dielectric window. Thus a circulating flow of electrons is induced in the chamber in a plane parallel to the planar coil, limiting the transfer of kinetic energy in non-planar directions.
A surface support in the chamber supports the substrate to be processed parallel to the plane of the coil, and thus to the plasma. Since the plasma species have little velocity in non-planar directions, the kinetic impact of ionic species on the substrate is small and the predominant reaction is a chemical reaction between the plasma species and the layers on the substrate. This reaction takes place at low temperatures and low pressures.
A detailed description of the above apparatus is shown in FIGS. 2-4. Referring to FIGS. 2, 3 and 4, a plasma treatment system 100 suitable for etching individual semiconductor wafers 110, includes a chamber 112 having an access port 114 formed in an upper wall 116. A dielectric window 118 is disposed below the upper wall 116 and extends across the access port 114. The dielectric window 118 is sealed to the wall 116 to define a vacuum sealed interior 119 of the chamber 112. A planar coil 120 is mounted adjacent to the dielectric window 118. The coil 120 is formed as a spiral having a center tap 122 and an outer tap 124. The plane of the coil 120 is oriented parallel both to the dielectric window 118 and to the support surface 113 upon which the wafer 110 is mounted during etching. The coil 120 is able to produce a planar plasma within the interior 119 of the chamber 112 which is parallel to the wafer 110. A suitable distance between the coil 120 and the support surface 113 can be about 5-10 cm.
A radiofrequency (RF) generator 130 leads to a coaxial cable 132 to a matching circuit 134. The matching circuit 134 includes a primary coil 136 and a secondary loop 138 that may be positioned to adjust the effective coupling of the circuit and allow loading of the circuit at the frequency of operation. The primary coil 136 may be mounted on a disk 140 that can be rotated about a vertical axis 142 to adjust the coupling. A variable capacitor 144 is in series with the secondary loop 138 to adjust the circuit resonant frequency with the frequency output of the RF generator 130. Impedance matching maximizes the efficiency of the power transfer to the planar coil 120. An additional capacitor 146 is provided in the primary circuit to cancel part of the inductive reactance of the primary coil 136 in the circuit.
A second RF potential from a source 172 is applied to the wafer support 113. This RF generator 172 can be operated at a low frequency (below about 550 kHz) or a high frequency (13.56 MHz) but generally a low frequency is employed. The frequency of the RF generator 172 and that of the first RF generator 130 is generally different, and provides a resonant current flow in the coil 120. Thus if the primary RF generator 130 operates at 13.56 MHz, the second RF generator 172 operates suitably at 400 kHz for example. This two RF power source configuration allows control of the amount of energy introduced to the system 100 through the primary RF generator 130 and control of the power output of the RF generator 172 permits control of the velocity imparted to the reactive species in the plasma.
In order to maximize the density of the plasma, and therefore to reduce the time required to perform an etch step, comparatively high power is applied to the planar coil 120, on the order of 300-600 watts. A lower power is applied to the substrate support 113 of about 75-300 watts.
Thus high power provides fast etch rates at a low pressure in the chamber, i.e., 1 Torr or less. Further, since the kinetic energy of ions in such a plasma is low, there is less damage to the wafer.
However, we have found that charging of the wafers processed in the above planar coil apparatus is a problem. A net charge on the substrate support 113 is transferred to the wafer 110 being processed. It is believed this net charge is caused by non-uniformities in the plasma. Further, the selectivity of halogen-containing etchants, such as chlorine, is reduced by a high ion density in the plasma. The high density plasma can also result in undercutting of the wafer stack to be etched. For example, a high density plasma contains, of necessity, a high density of radical species that etch laterally as well as horizontally, causing undercutting of the gates, as shown in FIG. 5, discussed further hereinbelow. In order to reduce this undercutting, it has become common to provide sidewall protection of the gate during further plasma processing. During the course of the etching, to prevent lateral etching and undercutting of the etched gate stack, particularly at the base of the gate stack, it is also known to generate a plasma that, in addition to etching the gate stack, also deposits a protective film on the freshly etched sidewall surfaces. The formation of such layers, which can be polymeric, for example, improves the anisotropy of the etch and prevents undercutting. However, the thickness of this sidewall deposit is difficult to control; if it is too thin, it does not protect the etched sidewalls; and if it is too thick, it takes up more space on the substrate, and impairs the critical dimensions of the gates and their devices. This is unacceptable for submicron design rules.
To perform an etch step in the apparatus of FIGS. 2-4, a process gas is introduced into the chamber 112 through a port 150 formed in the side of the chamber 110. A vacuum exhaust system 152 maintains the pressure in the system and evacuates volatile by-product and unreacted gases.
Thus an improved method of etching gate stacks having good etch rates and good selectivity but improved anisotropy, would be highly desirable.