As is generally known in the field of semiconductor memory devices and other semiconductor integrated circuits, it is often required to generate internally voltages that are greater than an external voltages, also known as off-chip power supply voltages. For example, it is known in flash electrically erasable, programmable read-only memories (EEPROMs) that a first high voltage of about +5V is needed to be produced for the read mode of operation of memory cells. Also, a second high voltage of about +10V is needed to be produced for the program mode of operation of the flash memory cells. To meet this requirement, the semiconductor memories also generally include one or more internal voltage boosting circuits for generating output signals boosted to be higher than an external supply voltage.
In FIG. 1, there is shown a simplified block diagram of a conventional voltage boosting circuit 10 for generating a word line voltage VPP, which is passed to appropriate word lines WL0 through WLn in a memory cell array via respective row decoder circuits 20. The voltage boosting circuit 10 includes a high voltage charge pump circuit 14 which is used during the program mode of operation of the semiconductor memory devices. The charge pump circuit 14 serves to charge up the word line voltage VPP at the internal word line supply node N1 to approximately 10V when the enable signal ENVPP is high. The boosting circuit 10 also includes a precharge logic circuit 12 which functions to precharge the word line voltage VPP to the external power supply voltage VCC, before the node N1 is boosted or pumped to a high voltage. The precharge logic circuit 12 will also maintain the supply voltage VPP equal to the external power supply voltage VCC in other modes of operation via the PMOS transistor P1. The capacitor C.sub.L represents the capacitive loading of the row decoder circuits 20, plus all of the parasitic capacitance associated with the line 2 connected to the word line supply node N1.
With reference to FIGS. 2(a) through 2(e), the operation of the voltage boosting circuit 10 depicted in FIG. 1 will now be explained. Initially, it is assumed that prior to time t1 the enable signal ENVPP and the precharge bar signal PRECHARGEB are both low (VSS), and that kick bar signal KICKB is high (VCC). Thus, the output of the NAND gate 18 on the line 3, defining the kick voltage VKICK, will be low (VSS). Further, the word line voltage VPP at the supply node N1 will be at the power supply voltage VCC, since the PMOS transistor P1 will be turned on.
When the kick bar signal KICKB makes a high-to-low transition at the time t1 as shown in FIG. 2(a), the precharge bar signal PRECHARGEB in FIG. 2 will be pulled to the power supply voltage VCC at time t2. At time t3, the kick voltage VKICK will begin making a low-to-high transition, as depicted in FIG. 2(b). This will, in turn, cause the word line voltage VPP at the supply node N1 to be raised or boosted by the kick signal VKICK via the booster capacitor C.sub.BOOST, from an initial value of VPPinit=VCC, to a boosted level VPP.sub.BOOST, starting at the time t3 in FIG. 2(d). As a result, the precharge bar signal PRECHARGEB will be further raised to the boosted level at time t4 as shown in FIG. 2(c).
This boosted level of the word line voltage VPP.sub.BOOST can be calculated from the following equation: ##EQU1## Where: EQU VKICK=Power supply potential VCC (2) EQU VPP.sub.init =Power supply potential VCC (3)
and C.sub.BOOST, C.sub.L are respectively the capacitances of capacitors C.sub.BOOST, C.sub.L. By substituting the equations (2) and (3) into the equation (1) and simplifying, there is given: ##EQU2##
From above equation (4), it can be seen that if the required maximum for the word line voltage VPP is less than the level that can be generated by the voltage boosting circuit 10 of FIG. 1, then the conventional boosting circuit 10 will be able to operate adequately. Unfortunately, as previously pointed out, the word line voltage VPP is typically required to be pumped up to approximately +10V for the program mode of operation of the flash memory cells. Therefore, under these circumstances, an additional means is required for producing this higher voltage, such as a second higher voltage charge pump.
However, the use of the conventional voltage boosting circuit 10 for this purpose is impractical, since the total capacitance that is seen by the high voltage charge pump 14 is very high, which is because the boost capacitor 15 is constantly connected to the kick signal VKICK, which is at a value of either VCC or VSS. As a result, this conventional voltage boosting circuit 10 suffers from the disadvantage that either the charge pump 14 would require a much longer time in order to raise the voltage VPP to the necessary programming level, or the size of the charge pump 14 must be increased, so as to raise the voltage VPP to the necessary programming level in the same amount of time. The first way would increase the programming time, and the second way would increase the cost and complexity of the overall memory device. Thus, neither of these choices offers a satisfactory solution.
More specifically, this problem of the conventional circuit 10 having a high total capacitance can be illustrated by referring back to equation (2) above. If we let VPPmin be equal to the minimum VPP supply voltage required for the read mode of operation for a flash memory cell, and let VCCmin be equal to the minimum VCC power supply voltage of the flash memory cell, then we have through substitution: ##EQU3##
Further, by assuming VPP.sub.min to be equal to +4.2V and VCC.sub.min to be equal to +2.5V, there is given: ##EQU4##
By solving for the booster capacitor C.sub.BOOST, there is given: C.sub.BOOST =2.125C.sub.L. Therefore, the total capacitance C.sub.TOTAL has been shown to have increased due to the booster capacitor: C.sub.TOTAL =C.sub.BOOST +C.sub.L or =3.125C.sub.L.
Accordingly, it would be desirable to provide an improved voltage booster circuit which overcomes the disadvantages of the conventional case, so as to be capable of operating efficiently and effectively in a low supply voltage environment. It would be expedient that the voltage booster circuit be operated effectively so as to produce a significant reduction in power dissipation.