The present invention relates to memory sells for integrated circuits, and, more particularly to memory cells whose retention elements integrate vertically stacked bipolar transistor transistors (“BJT”) with CMOS transistors.
The scale down tendency of the integrated circuit industry is causing an increasing technological barrier. One of the solutions is three-dimensional integrated circuits. These integrated circuits increase the manufacturing complexity significantly.
FIG. 1A shows an ordinary prior art six-transistor memory cell. As can be seen, it has two complementary bit lines, a bit line and a negative bit line. These two complementary bit lines are also tied to differential sense amplifier that has the ability to speed up the loaded bit lines.
Memory blocks hold 50-60% of dies area. Consequently, compacting the area of memory is equivalent to scaling down the size of the chip. The most serious effort to reduce the SRAM area (Static Random Access Memory) has been focused on the effort to reduce the number of transistors per memory cell. Such proposed solutions include the one-transistor SRAM (U.S. Pat. No. 6,765,830) and the Thyristor based SRAM (U.S. Pat. No. 6,944,051). All such proposed solutions, however, are not really SRAM, but rather are DRAM (Dynamic RAM) with SRAM interface. These memory cells require ongoing refresh cycles and significant amount of area for control and emulation of the SRAM interface. Consequently, these memory cells do not have the same applicability as an SRAM. Although these memory cells may achieve approximately 80% of area saving per cell, only less then 40% area saving will hold for full block of such memory with all the peripheral overhead.
It is noted that some of the SRAM cells designed in the past have demonstrated bipolar transistor cells or integration of such BJT (Bipolar Junction Transistors) with MOS transistors or other passive devices (U.S. Pat. No. 4,926,378 and U.S. Pat. No. 4,845,674).
There is a compelling need to have an apparatus that will significantly improve the compactness of integrated circuits, especially for SRAM. There is a further compelling need to have an apparatus that will also reduce the power requirements for such integrated circuits.