Electronic systems generally include at least one printed circuit board (PCB) containing one or more integrated circuit (IC) chips or ICs. ICs typically include input/output (I/O) pins which may be coupled to various interconnects of the PCB. Testing performance of electronic systems which include PCBs and ICs typically requires testing at multiple levels including at the chip level, at the board level, and at the system level. Testing at the board level includes testing interconnects of the PCB. Testing at the system level requires analysis of interconnections between and among the ICs, the PCBs, and other devices both on and off the PCB.
To enhance testability at the board level as well as at the system level, a common design practice at the chip level is to incorporate boundary scan test logic into an IC in accordance with IEEE Standard 1149.1. 1149.1 specifies the function of boundary scan logic known as JTAG, which is named for the Joint Test Action Group, for control of boundary scan testing. Two basic elements of an IC are a core logic and the I/O pins. In accordance with 1149.1, boundary scan cells (BSCs) are inserted between the core logic and the I/O pins of the IC. BSCs are typically inserted for all I/O pins of the plurality of ICs on the PCB and may be used to test the integrity of the interconnections between the plurality of ICs.
Each IC may be controlled by boundary scan logic, in accordance with 1149.1, to operate either in a system mode or in a JTAG test mode. In the system mode, system data signals relating to core functions of the IC are passed through the I/O pins to and from devices external to the IC. In the JTAG test mode, test data are provided by the boundary scan chain for the purpose of testing interconnections between the IC and devices external to the IC. The boundary scan test access port (TAP) controller also provides test control signals which include mode signals, shift signals, clock signals, and update signals, among others, each of which is well known. The mandated public instructions include a bypass instruction, a sample instruction, a preload instruction, and a extest instruction. The extest instruction controls BSCs to perform a boundary scan test among the various ICs.
The IC further includes a test data input (TDI) demultiplexer, a test data output (TDO) multiplexer, a test access port (TAP) controller, and a plurality of test registers such as a bypass register, an instruction register, and an identification register. The TDI demultiplexer includes an input coupled to receive a test data signal from the boundary scan logic which is typically driven externally to the IC. The TDI demultiplexer includes a first output coupled to a TDI input of a first BSC of the plurality of BSCs in the IC. Each of the BSCs includes a TDI input and a TDO output. Each of BSCs is connected serially from a TDO output to a TDI input to propagate test data signals from one BSC to the next BSC in the chain. The TDI demultiplexer further includes a second output coupled to an input of the core logic, a third output coupled to an input of the bypass register; a fourth output coupled to an input of the instruction register; and a fifth output coupled to an input of the identification register.
The TDO multiplexer includes an output which is coupled to provide a test data signal to another IC or to the boundary scan logic. The TDO multiplexer further includes: a first input coupled to a TDO output of a last BSC of the plurality of BSCs in the IC, a second input coupled to an output of the bypass register; a third input coupled to an output of the instruction register, and a fourth input coupled to an output of the identification register. The identification register includes inputs coupled to outputs of the TAP controller. The TAP controller includes inputs coupled to receive a TMS signal, a TCK signal, and a TRST signal from the boundary scan logic.
In general, there are three possible I/O structures for an IC including a two-state I/O structure, a three-state I/O structure, and a bi-directional I/O structure. Each of the three I/O structures provides coupling between the core logic and at least one I/O pin. Any or all of the I/O structures may be used in an IC depending on the particular circumstances. The two-state I/O structure includes a two-state output buffer having an input and an output. The input of the two-state output buffer is coupled to a system data output of the core logic. The output of the two-state output buffer is coupled to an I/O pin. The three-state I/O structure includes a three-state output buffer having an input, an output, and a control input. The input of the three-state output buffer is coupled to a system data output of the core logic. The output of the three-state output buffer is coupled to an I/O pin. The control input of the three-state output buffer is coupled to a three-state system control signal output line of the core logic. The bi-directional I/O structure includes a bi-directional buffer. The bi-directional buffer includes an output buffer element having an input, an output, and a control input and an input buffer element having an input and an output. The control input of the output buffer element is coupled to a bi-directional control signal output line of the core logic. The input of the output buffer element is coupled to a system data output of the core logic. The output of the input buffer element is coupled to a system data received input of the core logic. The output of the output buffer element and the input of the input buffer element are coupled together with an I/O pin.
According to conventional methods and apparatus for boundary scan testing, the BSCs are inserted into the I/O structures between the buffers and the core logic. For a two-state output structure, a BSC is inserted between the core logic and the input of the two-state output buffer. For a three-state output structure, a BSC is inserted between the system data output of the core logic and the input of the three-state output buffer. Also, a BSC is inserted between the three-state control signal output line of the core logic and the control input of the three-state output buffer. For a bi-directional output structure, a BSC is inserted between the system control signal output line of the core logic and the bi-directional output buffer. Also, a bi-directional BSC is inserted between the core logic and the bidirectional output buffer.
IEEE Standard 1149.1 was first adopted in 1990. It has been widely used and has proved to be very successful. 1149.1 has been amended twice to improve it. However, 1149.1 does not address all situations and design practices. One such practice is the inclusion of capacitive coupling in the interconnections between ICs. A capacitor is added either to the connection between the ICs or to one, the other, or both of the I/O pins of the ICs or the PCBs with connectors. The capacitor is designed to reduce noise and block unwanted common mode voltage differences in the interconnection. For discussion, this will be referred to alternatively as either being AC coupled or DC de-coupled.
Turning first to FIG. 1, a block diagram of ten possible combinations of DC and AC coupled interconnections between two devices is shown. The choice of which of the combinations shown that are actually used depends on the circumstances. Because of the capacitor, the value of a signal at the receiving end of the interconnection is no longer the same as the value at the driving end. This assumes that the steady state condition has been reached where all transient values of driven data have subsided. The square wave input signal is transformed at the receiving end into a series of decaying signal spikes corresponding to the transitions of the square wave. The rate of the spike decay depends on the value of the capacitor and the inherent resistance, that is, the RC constant. The result is that conventional 1149.1 testing becomes impractical on AC coupled interconnections. One will note that there are seven possible AC coupled combinations where 1149.1 will not work as compared to only three DC coupled combinations where 1149.1 will work. As the quest for higher signal speeds continues in the future, the use of AC coupling will increase. This becomes especially true with the development of optical communication signals. The consequence will be less and less reliance on conventional 1149.1 testing.
Beyond the direct connected AC coupled testing are the areas of AC coupled cluster testing and AC coupled functional block testing. Under certain circumstances, one might want to test a cluster or functional block of components. As these components might not be directly connected to one another, further testing difficulties might arise. For example, the components might have multiple AC coupled connections in series or they might have non-electrical connections. If so, the test signal propagation may require continuous streams of alternating patterns in order to maintain minimum cutoff frequency requirements of the signal path or to maintain prolonged test signal application to compensate for long signal delays. Delay is one of the difficulties that might be encountered and is a measure of the time that a signal takes to propagate from the transmitter to the receiver. Another way to express the delay of the signal is in terms of the latency of the communication path. Generally the delay is constant but initially unknown. Another potential difficulty is pin skew which is a measure of the variation of two or more signals that are designed to be simultaneous in theory but are not quite in practice. Generally the skew is constant but initially unknown. Yet another potential difficulty is jitter which is a measure of the variation of a signal over time, that is, a signal that is supposed to have uniform timing in theory is not quite in practice. Jitter can be especially problematic when it arises in one or more of the clock signals as a consistent clock signal can be important for accurate timing. Generally the jitter is within bounds that are not initially known. It is not strictly necessary that each of these three difficulties be precisely measured in order to compensate for them, but they should be accounted for to produce accurate testing results. A flexible approach is proposed.