1. Field of the Invention
This invention relates to a decoder circuit, for example for use in memory addressing.
2. Background Art
FIG. 1 shows an example of the structure of a static random access memory (SRAM) and its addressing circuitry. The memory 1 comprises a grid of memory cells 2 arranged in rows and columns. In this example there are four rows and four columns but typical SRAMs have many more rows and columns. All the cells in a row are connected to a single wordline 3. All the cells in a column are connected to a single bitline 4. Each cell has two stable states, representing high and low output values. When one of the wordlines is activated each bitline takes on the state of the cell to which that bitline is connected and which is also connected to the activated wordline. The bitlines are connected to a multiplexer 5 which allows a single one of the bitlines to be selected to provide the final output from the memory at 6.
Each cell in the memory is allotted a number. To access a cell in the memory the cell's number is applied in binary format to input lines 7. A decoder 8 takes some of the lines 7 (indicated at 9) as input and thereby determines which one of the wordlines should be activated to access the cell. The remainder of the lines 7 (indicated at 9) pass to the multiplexer 5, which thereby determines which of the bitlines should be selected so that the final output at 6 takes on the state of the desired cell.
FIG. 2 shows one example of a structure for decoder 8. The lines 9 each branch through an inverter 10 so that address signals representing inverted (indicated at 11) and non-inverted (indicated at 12) versions of each of the lines 9 are available. The appropriate inverted or non-inverted version of each of the lines 9 is applied to a NAND gate 13 corresponding to each wordline. The output of each NAND gate passes to an inverter 14 which drives the respective wordline.
By means of the correct set of connections to each of the NAND gates a wordline is activated only when the appropriate set of inputs is applied at 9. This circuit is simple, but has a number of disadvantages if the number of address line inputs is increased.
1. In many important applications—for example in the caches of high-speed processors—speed of access to the desired memory cell is crucial. However, the large NAND gates are relatively slow.
2. In almost all applications—and especially in battery-powered applications power consumption is very important. However, in the system of FIG. 2 as the input lines 9 change values potentially many, or all, of the distributed address signals will change, giving rise to a high current consumption. The current consumption is further increased by the need to generate an inverted version of each input line to the decoder.
In an alternative structure for decoder 8 a pre-decode level is-added so that fewer distributed signals can change as the input lines 9 change values. In the predecode level the input lines 9 are split into groups that are processed by a first level of NAND gates. The outputs from those NAND gates pass to a second level of NAND gates whose outputs are inverted to drive the wordlines. Since only one of the lines that connect the two levels of NAND gates changes for each change in input values the maximum power consumption is less than for the structure of FIG. 2. Two levels of processing in the alternative structure make it relatively slow for small numbers of addresses, but for wider decoders (e.g. five or more addresses) it can be faster.
An alternative solution is to use a precharge decode structure. FIG. 3 illustrates precharge decode circuitry that represents an alternative structure for decoder 8. As before, inverted 11 and non-inverted 12 versions of each of the input lines 9 to the decoder are generated. A decode line 20 is provided for each wordline. Each wordline is driven by an inverter 14 which receives the output from a two-input NAND gate 18. One of the inputs to the NAND gate 18 is a common timing enable signal at 19. The other of the inputs is from the respective decode line 20.
Each decode line can be taken high by a respective PMOS precharge transistor 21. The precharge transistors are connected with their sources to a high voltage (Voc), their drains to the respective decode line and their gates to a common precharge signal at 22. Each decode line can be taken low by any of a number of NMOS addressing transistors. The addressing transistors 23 are connected with their drains to the respective decode line, their sources to a low voltage (ground) and their gates to a selected one of the inverted and non-inverted input lines 11, 12. The inputs to the gates of the addressing transistors are arranged so that one addressing transistor of each decode line receives a selected inverted or non-inverted version of each of the input lines 9.
In use, to decode a set of signals applied to lines 9, a pulse is applied to the precharge line 22 so that the decode lines float at VDD). Then the signals from the input lines 9 are applied to the addressing transistors 23. At all the decode lines corresponding to all the undesired wordlines at least one of the addressing transistors is turned on, so that those decode lines can all discharge to ground. At the decode line corresponding to the desired wordline none of the addressing transistors is turned on, so that decode line continues to float at VDD. After a delay that is sufficiently long for the voltages on all the undesired decode lines to have fallen, a signal is applied to the timing enable line 19, This causes the NAND gate 18 corresponding to the decode line that remains high to produce a low output, whereas all the other NAND gates produce high outputs. By virtue of the inverters 14 this causes the desired one of the wordlines to be selected.
The delay before application of the timing enable signal is crucial to the operation of the precharge circuit. The timing enable signal cannot be applied before all the undesired decode lines have discharged to below the input threshold voltage of the NAND gates 18, otherwise more than one wordline will be selected. Therefore, the delay is dependant on the speed with which the decode lines discharge. A decode line with all of its addressing transistors turned on will discharge quickly but a decode line with only one of its addressing transistors turned on will discharge relatively slowly. The timing enable signal is usually derived from the arrangement shown at 24. Another instance of the decode structure is provided, this time with all but one of its addressing inputs connected to ground. The decode line 25 of the arrangement 24 therefore falls towards ground as slowly as any of the undesired decode lines can. The enable input to the NAND gate 26 of the arrangement 24 is held high. As soon as the decode line has fallen sufficiently the output 27 of the NAND gate goes high. The output 27 provides the timing enable signal at 19.
The precharge structure of FIG. 3 can be faster than the structures of FIG. 2. However, the discharge of all the undesired decode lines gives rise to high power consumption, and the necessary delay before the timing enable signal is generated reduces the speed of operation of the circuit. The choice between a static decoder (e.g. as shown in FIG. 2) and a precharge decoder is not clear-cut and very often both options have to be investigated when undertaking a design.
It would be desirable to have a decoder circuit that allowed for faster decoding, preferably at reduced power consumption. In addition to providing a technically superior solution such a circuit could save a considerable amount of investigatory design work.