1. Field of the Invention
The present invention relates to a clock processing part and more particularly to an internal clock generating circuit and a method for the same.
2. Description of the Related Art
Typically, a central processing unit (CPU) and a semiconductor memory device are interconnected through a signal bus. In such a case, the CPU and the semiconductor memory device function as master and slave, respectively. The CPU master transmits data including address, command, writing data, and a clock required for sampling data to the memory device slave.
An external clock transmitted through the signal bus may be a clock aligned or centered to the data as shown in FIGS. 1 and 2. The slave memory receives the external clock and generates an internal clock needed for sampling data. In order to correctly sample data, the internal clock should be a data-centered clock as shown in FIG. 1b. If an external clock is a data-aligned clock, it is relatively difficult to generate a data centered internal clock. However, a gradual increase in the data rate/pin decreases the number of valid data windows. If the data and clock have slightly different paths in the system, there may be a bigger skew between the clock and pin that will be applied to the slave. The problem gets worse in a double data rate (DDR) product, which receives two pieces of data at one clock cycle as shown in FIG. 2b, compared to a single data rate (SDR) product as shown in FIG. 2a. 
When an external clock is centered or aligned to data, a system designer desires to adopt to the slave a function of intentionally pushing or pulling the timing of a clock on a time axis as shown in FIG. 3 in order to use an internal clock adjusted to a valid window of data. At this time, the slave memory performs a setup/hold centering function of a data sampling clock by pushing or pulling the timing of a clock on the time axis in response to a setting signal.
Typically, a delay line or delay chain is constructed with an inverter chain having a plurality of inverters as internal delay elements. The inverter chain is constructed with inverters connected in at least more than two levels having a relatively large amount of a unit delay. Therefore, it is not adequate to a case that requires a more precise delay.
What is needed is a delay line or delay chain providing improved resolution degree by decreasing the amount of unit time delay and providing more precise control of the delay while minimizing skew in the clock signal.
Therefore, the present invention is disclosed to solve the aforementioned problems and it is an object of the invention to provide an internal clock generating circuit to generate an internal clock precisely controlled as much as the necessary amount of delay in an improved resolution degree and a method for the same.
It is another object of the present invention to provide an internal clock generating method and the related circuit that can precisely sample data even when there is a skew between clock and data to be applied to a semiconductor memory.
It is a still another object of the present invention to provide an internal clock generating method and the related circuit that can control the delay time in response to an external signal.
It is a further another object of the present invention to provide an internal clock generating method and the related circuit that can minimize skew of an output clock, but in an improved resolution degree.
In order to accomplish the aforementioned objects in accordance with an aspect of the present invention, disclosed is an internal clock generating circuit of a semiconductor device comprising a delay chain having a plurality of delay units for generating multi-phase clocks by adjusting an input clock, a thermometer converter for outputting a thermometer code value in response to an input selection data, and a multiplexer for selectively outputting one of a plurality of clocks input from the delay chain in response to the thermometer code value.
In another aspect of the invention the multiplexer selectively outputs one of the plurality of clocks applied from the delay chain by dividedly multiplexing the thermometer code value into two stages of upper and lower bits.
In another aspect of the invention the delay chain additionally includes regenerators to restore a pulse form of a clock.
In another aspect of the invention the delay unit of the delay chain is constructed with RC delays.
In another aspect of the invention the regenerator is a short type pulse generator.
In another aspect of the invention a pulse regenerator is additionally included to restore a pulse form of a clock output from the multiplexer.
In another aspect of the invention the pulse regenerator is a short type pulse regenerator.
In another aspect of the invention the regenerators are respectively positioned in symmetry at positions where +/xe2x88x92 delay of the delay units against the thermometer code value changes non-linearly.
In another aspect of the invention the selection data is a binary code data applied from outside.
In another aspect of the invention the delay unit of the delay chain is constructed with path gates.
Disclosed is a method of generating clock signals in a semiconductor device comprising the steps of generating multi-phase clock signals by adjusting an input clock signal through a delay chain having a plurality of delay units, decoding a thermometer code value in accordance with selection data, outputting one of the plurality of clock signals in response to the thermometer code value, and restoring a pulse shape of the output clock signal into its original state and outputting it as a delay-controlled internal clock signal.
Disclosed is a semiconductor clock signal circuit, comprising means for generating multi-phase clock signals by adjusting an input clock signal through a delay chain having a plurality of delay units, means for decoding a thermometer code value in accordance with selection data, means for outputting one of the plurality of clock signals in response to the thermometer code value, and means for restoring a pulse shape of the output clock signal into its original state and outputting it as a delay-controlled internal clock signal.