Phase locked loops (PLUs) are circuits well known in the communication arts for synchronizing a variable local oscillator with the phase and/or frequency of a component of a transmitted signal. Typically such circuitry includes a phase detector which is responsive to the transmitted signal and the output of a local oscillator for generating a phase error signal proportional to a difference between a component of the transmitted signal and the oscillator output. The phase error signal is subjected to smoothing and coupled to control the oscillation rate of the variable oscillator thus forming a self-regulating closed loop system. In order to enhance the operation of the PLL, some systems include a second loop which generates an error signal proportional to the difference between the frequency of the variable oscillator and the frequency of the component of the transmitted signal. The frequency error signal is added to the phase error signal for controlling the rate of the oscillator. Nominally, the variable oscillator will achieve the desired frequency before phase lock is achieved, at which time the frequency error signal is substantially zero and the PLL is controlled by only the phase error signal.
An example of a frequency/phase responsive PLL is described by Canfield et al., in U.S. Pat. No. 5,159,292 entitled ADAPTIVE PHASE LOCKED LOOP. In the Canfield system an unlock detector is used to a switch in the frequency error signal path which actively disconnects the frequency error term when the system approaches phase lock. The active disconnection of the frequency term precludes noise in the frequency error signal from causing jitter in the phase of the signal provided by the variable oscillator. In order to detect the frequency unlock condition of the loop, the Canfield system includes a quadrature phase detector that accumulates samples of in-phase and quadrature components of the input signal and the unlock condition is determined by counting the number of times the accumulated in-phase samples change polarity during an interval (e.g., a field) and comparing this count value to a threshold value. In order to prevent the combined frequency and phase error signal from excessively altering the oscillator frequency when unlocked, the combined error signal is applied to a limiter before being low pass filtered and applied to the oscillator.