The processes associated with integrated circuit design generally involve several design transformations from high levels of abstraction to intermediate and lower levels of abstraction. At each level, equivalence verification is performed to prove that any transformation has not functionally or logically altered the design.
Conventional equivalence verification methods generally require a mapping of state elements between the implementations to be verified as equivalent. These mapping methods fall into one of several categories. A naming method, which is fairly common, maps corresponding points in each design that are named similarly. However, the names of state elements may be altered or lost during a design transformation performed by some design tools using the naming method. In addition, the naming method can be fairly unusable for a reverse engineering type application. Another approach is a functional method that makes use of a canonical representation of a state element's fan-in logic cone (e.g., binary decision diagrams or BDDs). However, the functional method can often require that all of the inputs of a cone be mapped when that information might not be available, thereby creating a circular problem.
Another approach is a simulation method that simulates both design levels and then matches or narrows the selection of simulation components to state elements with similar value vectors. The simulation method can however be difficult to use in the presence of intentional or unintentional modifications. In another approach referred to as a structural method, a net-list to net-list type comparison is performed that examines combinational cone structure. In some instances, a combination of these approaches is used. However, many or all of the conventional approaches to equivalence verification have some shortfalls. Accordingly, an improved method for performing equivalence verification is needed.