In the manufacture of integrated circuits (ICs), devices are formed on a wafer and connected together by multiple conductive interconnection layers. These conductive interconnection layers are formed by first forming gaps, like trenches and vias in a dielectric layer and then filling gaps with a conductive material.
The conductive material is usually formed within the gaps by an electrochemical plating process (ECP process). A barrier layer is firstly formed within the gaps in the dielectric layer. A seed layer is then formed over the barrier layer. The remaining space of the gaps is filled in succession with the conductive material. Then a planarization is performed to remove excess conductive material.