1. Field of the Invention
The present invention relates to semiconductor memory devices. More particularly, the present invention relates to a repair circuit and a method of repairing defects in a semiconductor memory device.
This application claims priority under 35 USC § 119 to Korean Patent Application No. 2005-117258, filed on Dec. 3, 2005, the subject matter of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
A semiconductor memory device generally includes a main memory array having a plurality of memory cells, and a redundant memory array having redundant memory cells adapted for use in the repair of defective memory cells in the main array. It is preferable that all memory cells of the main memory array operate normally. However, defective memory cells are often formed within the main memory array due to variations in the manufacturing processes used to fabricate the memory cells as well as variations in electrical performance characteristics across a large number of memory cells. When a defective memory cell is identified in the main memory array, it may be replaced (or substituted) with one of the redundant memory cells. This capability ensures uniformly acceptable memory cell performance across the entire main memory array.
In general, at various stages during the lengthy sequence of fabrication processes used to manufacture a semiconductor memory device, tests are performed to determine whether or not the memory cells are operating normally. After each test, a memory cell identified as defective may be replaced with a redundant memory cell. This test, identification, and replacement procedure is typically performed while the semiconductor memory device is still in its “wafer state”, i.e., before individual dies are cut from the fabrication wafer and packaged into individual device form.
There are many different types of memory cell defects, including row related defects and/or column related defects. That is, while some memory cell defects are identified in relation to a particular memory cell, memory cell defects are more commonly identified as a defective row or column. As a result, semiconductor memory devices require both a row repair circuit and a column repair circuit in order to remedy row defects and column defects, respectively.
Conventional repair techniques may be divided into before-package repair (BPR) techniques—adapted to repair identified defects in wafer state devices, and post-package repair (PPR) techniques—adapted to repair defects in a packaged devices. PPR techniques are commonly used to repair defective memory cells which remained unidentified in the wafer state, but which were subsequently identified during package level testing. Both PPR and BPR techniques require row repair and column repair circuits.
Some PPR techniques use electrical fuse circuits (e-fuses) instead of laser fuse circuits to repair defective memory cells and improve package yield for the semiconductor memory devices. E-fuse circuits offer several performance advantages, but tend to be more complicated in their layout relative to laser fuse circuits. Thus, conventional PPR techniques incorporating both the row and column repair circuits using e-fuse circuits occupy an unacceptably large layout area within the overall semiconductor memory device. This quality is at odds with continuing pressure to increase the fabrication density of memory devices.