1. Field of the Invention
The invention relates to the protection of integrated circuits from electrostatic discharge (ESD), and more particularly to the protection of NMOS transistors by an embedded parasitic silicon controlled rectifier (SCR) which triggers at a very low voltage.
2. Description of the Related Art
The protection of integrated circuits from electrostatic discharge (ESD) is a subject which has received a lot of attention from circuit designers because of the serious damage that ESD can wreak as device dimensions are reduced. Workers in the field and inventors have proposed many solutions, many trying to solve the problem of protecting sub-micron (1 micron=10xe2x88x926 meter) devices while still allowing them to function unencumbered and without undue, or zero, increase of silicon real estate. The main thrust of ESD protection for MOS devices is focused on the use of parasitic npn and pnp bipolar transistors, which together form a silicon controlled rectifier (SCR). Unwanted as this SCR normally is, it can safely discharge dangerous ESD voltages as long as its trigger voltage is low enough to prevent gate oxide breakdown of the MOS devices of which it is a part.
Among ESD protection devices SCR protection shows good clamping capability (a very low holding voltage) compared to Gated-NMOS, however, a larger trigger voltage and latch-up concerns are always the drawbacks. See below a discussion of the graph of FIG. 1. In the sub-micron technologies, the Gated-NMOS is mostly used for a robust ESD design. A problem exists for the 0.15 micron process because the Gated-NMOS snapback voltage (larger than 5 volt) is higher than the gate oxide breakdown of 10 Million volt/cm. For 0.6 and 0.5 micron high voltage technology, the Gated-NMOS will generally show its weakness on high voltage (12 volt, 40 volt) ESD due to higher drain junction breakdown and higher snapback voltage.
The following publications describe low voltage lateral SCR structures to protect the input and output circuitry of an integrated circuit during an ESD event:
xe2x80x9cA Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads,xe2x80x9d A. Chatterjee and T. Polgreen, IEEE Electron Device Letters, Vol. 12, No. 1, Jan., 1991.
xe2x80x9cLateral SCR Devices with Low-Voltage High-Current Triggering Characteristics for Output ESD Protection in Submicron CMOS Technology,xe2x80x9d Ker, IEEE Transactions On Electron Devices, Vol.45, No.4, April 1998, pp.849-860.
FIG. 1 is a graph of the I-V characteristics of a 0.15 micron process SCR/Gated-NMOS device. Curve 1 (dotted line) shows the characteristics for the SCR and Curve 2 (solid line) shows the characteristics for the Gated-NMOS. It is obvious that the SCR has the lower holding voltage while the Gated-NMOS has the lower trigger voltage. Another drawback of the SCR""s is the latch-up concern.
We now describe in FIG. 2 a prior art low-trigger SCR for on chip ESD (IEEE, Electron Device Letters, Vol. 12, No. 1, January, 1991, see reference above). In a substrate 21 is embedded an n-well 32. Also implanted in substrate 21 is gated NMOS T1, comprising n+ drain 22, gate 23, and n+ source 24. Implanted next to n+ source 24 is p+ diffusion 25. Implants 23, 24 and 25 are tied to a voltage reference 39 (typically ground). N+ drain 22 is connected to chip pad 38. Implanted in the n-well are n+ diffusion 26 and p+ diffusion 27 which also are connected to chip pad 38. Halfway straddling the n-well is n+ diffusion 28 which is the drain of gated NMOS T2. T2 further comprises gate 29 and n+ diffusion (source) 30. A p+ diffusion 31 is implanted next to n+ diffusion 30. 29, 30, and 31 are connected to 39. Therefore, both T1 and T2 are grounded gate NMOS transistors. 26, 27, 28, 30, 31, and 32 make up the external SCR (external because the SCR is largely external to the gated NMOS transistors T1, T3, and T4). The latter two transistors are not further described since they follow the pattern of T1. The SCR itself comprises a parasitic bipolar pnp transistor Q1 and a parasitic bipolar npn transistor Q2. Drawbacks of this layout are a) the external SCR and b) low current capacity resulting in poor protection efficiency.
FIG. 3 is a schematic diagram of the layout of FIG. 2 where the same numbers indicates the same items.
Another prior art lateral low-voltage, high-current SCR (IEEE Transactions On Electron Devices, Vol.45, No.4, April 1998, see reference above) is shown in FIG. 4 which is described in the cited IEEE document on page 851. Drawbacks of this design are:
a) poor I/O and VDD/GND connections causing latch-up concerns,
b) the SCR is still outside of the main protection area leading to poor efficiency. Latchup occurred, see Arrow A, at a voltage difference of larger than 0.7 volt caused by diode Dp2 because of P-N diode forward cut-in.
Other related art is described in the following U.S. Patents:
U.S. Pat. No. 5,872,379 (Lee) describes a low voltage turn-on SCR to provide protection to the input and output circuitry of an integrated circuit during an ESD event.
U.S. Pat. No. 5,907,462 (Chatterjee et. al) teaches a gate coupled SCR, where the stress voltage is coupled from a pad to a gate electrode causing a NMOS transistor to conduct, thus triggering the SCR.
U.S. Pat. No. 5,939,756 (Lee) discloses an added P-well implantation for uniform current distribution during an ESD event to provide improved protection to the input and output circuitry of an integrated circuit.
It should be noted that none of the above-cited examples of the related art show part of the drain and the p+ diffusion in the n-well, nor having the drain connection tightly tied together at the p+ diffusion and the n+ drain as in the presently disclosed invention.
It is an object of the present invention to provide circuits and methods for an embedded SCR implemented in either 5 volt or 12 volt I/O devices.
Another object of the present invention is to provide for an embedded SCR which operates at less than or equal to 2 volts to prevent gate oxide damage, particularly in 0.15 micron 5 volt technology.
A further object of the present invention is to provide for an embedded SCR where the ESD pass voltage of 8,000 volt is achieved for the 12 volt process.
Yet another object of the present invention is to provide a latch-up free SCR.
These objects have been achieved by inserting the p+ diffusion and the n-well in the drain side and a part of the drain to form a low-trigger, high efficiency SCR. Further, the layout is such that the drain connection is tightly tied together at the p+ diffusion and the n+ drain making that connection very short and thereby preventing latch-up. The parasitic SCR is made more efficient because it is entirely within the n+ diffusions (the source of the grounded gate NMOS transistor) at either side of the structure and, thus, called an embedded SCR. For the 12 volt I/O device the design is modified by placing each of two n+ drains in its own n-type doped drain (ndd) area and straddling halfway the n-well. The structure is repeated as required and a p+ diffusion is implanted at both perimeters and connected to the nearest n+ source and a reference voltage.