1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and method of testing the same.
2. Description of Related Art
In recent years, as an LSI (Large Scale Integration) has gotten larger in scale, the number of PLLs (Phase-Locked Loops) embedded in an LSI has been increasing. Consequently, the testing time of PLLs embedded in a LSI has been problematically getting longer.
A conventional method of testing PLLs embedded in a LSI is explained hereinafter with reference to FIG. 8. In FIG. 8 shows an exemplary case where a LSI 1000 has two PLLs, i.e., first PLL 1001 and second PLL 1002. A test device 2000 for testing a PLL includes a signal generator 2001 and a signal measuring device 2002. The test device 2000 also includes switches 2003 and 2004. The switch 2003 changes the connection from the signal generator 2001 between the first PLL 1001 and second PLL 1002. Likewise, the switch 2004 changes the connection to the signal measuring device 2002 between the first PLL 1001 and second PLL 1002.
Then, to test the PLLs embedded in the LSI 1000, firstly, the first PLL 1001 is connected to the signal generator 2001 and signal measuring device 2002 by the first and second switches 2003 and 2004. In this state, a clock having a frequency ft outputted from the signal generator 2001 is inputted to the first PLL 1001, and the frequency is frequency-multiplied by N at the first PLL 1001. Then, the clock having a frequency N×ft outputted from the first PLL 1001 is measured in the signal measuring device 2002, and the test of the first PLL 1001 has been completed. Next, by changing the switches 2003 and 2004, the second PLL 1002 is connected to the signal generator 2001 and signal measuring device 2002. In this state, a clock having a frequency ft outputted from the signal generator 2001 is inputted to the second PLL 1002, and the frequency is frequency-multiplied by M at the second PLL 1002. Then, the clock having a frequency M×ft outputted from the second PLL 1002 is measured in the signal measuring device 2002, and the test of the second PLL 1002 has been completed.
FIG. 9 shows a more concrete example of the circuit shown in FIG. 8. As shown in FIG. 9, selectors 1004 and 1005 are connected to the first and second PLLs 1001 and 1002 respectively. In a normal operation mode, the selectors 1004 and 1005 select a clock generated by an OSC (oscillator) 1003, and this clock is inputted to the first and second PLLs 1001 and 1002. On the other hand, in a test mode, the selectors 1004 and 1005 select a clock generated by the signal generator 2001, and this clock is inputted to the first and second PLLs 1001 and 1002. Furthermore, first and second logic circuits 1006 and 1007 are connected to the first and second PLLs 1001 and 1002. The first and second logic circuits 1006 and 1007 become active with the clock outputted from the first and second PLLs 1001 and 1002 in the normal mode, Furthermore, the test device 2000 outputs a control signal for controlling the switching of the selector 1004 and 1005.
Then, to test the PLLs embedded in the LSI 1000, firstly, the first PLL 1001 is connected to the signal generator 2001 by a switch 2005, and the first PLL 1001 is also connected to the signal measuring device 2002 by a switch 2006. At the same time, the test device 2000 inputs the control signal to the selector 1004 such that a clock generated by the signal generator 2001 is inputted to the first PLL 1001. In this state, a clock having a frequency ft outputted from the signal generator 2001 is inputted to the first PLL 1001, and the frequency is frequency-multiplied by N at the first PLL 1001. Then, the clock having a frequency N×ft outputted from the first PLL 1001 is measured in the signal measuring device 2002, and the test of the first PLL 1001 has been completed. Next, the second PLL 1002 is connected to the signal generator 2001 by changing the switch 2005, and the second PLL 1002 is also connected to the signal measuring device 2002 by changing the switch 2006. At the same time, the test device 2000 inputs the control signal to the selector 1005 such that a clock generated by the signal generator 2001 is inputted to the second PLL 1002. In this state, a clock having a frequency ft outputted from the signal generator 2001 is inputted to the second PLL 1002, and the frequency is frequency-multiplied by M at the second PLL 1002. Then, the clock having a frequency M×ft outputted from the second PLL 1002 is measured in the signal measuring device 2002, and the test of the second PLL 1002 has been completed.
However, in the method shown in FIGS. 8 and 9, in the case where a plurality of PLLs are embedded in a LSI, a test has to be performed the same number of times as the number of the PLLs embedded in the LSI to complete the PLL test. Therefore, the testing time of the PLLs gets problematically longer. Furthermore, since both a signal generator and a signal measuring device are expensive, it will be unrealistic to use several test devices simultaneously. In addition, the number of signal generators and signal measuring devices embedded in a single test device is two channels or three at the maximum, and even so it cannot test more than two PLLs simultaneously.
Meanwhile, it is known to test two PLLs simultaneously for a LSI having two PLLs by inputting a clock delayed by a delay circuit to one of the PLLs, comparing the outputted clocks from the two PLLs by a comparator, and detecting the failure of the PLLs from the phase difference between the outputted clocks from the two PLLs. (For example, Japanese Unexamined Patent Application Publication No. 2005-277472 (Ogawa))
However, the technique described in Ogawa can only compare the phase difference between two input clocks, and cannot cope with a LSI having more than two PLLs.