At present, large-sized and high-resolution display panel has become a development trend of liquid crystal display device (LCD). However, with increasing of LCD panel size, RC delay of gate wiring and data wiring also increases (as shown in FIG. 1). Excessive RC delay may cause insufficient charging or wrong charging of pixel area, which seriously affects display quality of LCD panel, such as poor display of LCD panel and abnormal image.
In order to solve the aforesaid problem, it is proposed in the prior art that a thickness of a metal layer can be increased. Under the condition that a capacitance is not increased, a resistance is decreased and a signal line load is reduced. However, if the metal layer is too thick, topography of array film will be affected. As a result, a film coated on the metal layer has difficulty in climbing and may break (as shown in FIG. 2), which leads to problems such as corrosion of wiring and short connection. A qualified rate of a product will be seriously reduced. At the same time, there is no planarization technology in traditional array manufacturing procedure, which limits continuous decrease of a signal line resistance.