Die stacking integrates semiconductor devices vertically in a single package in order to directly influence the amount of silicon that can be included in a given package footprint. Die stacking simplifies the surface-mount pc-board assembly and conserves pc-board real estate because fewer components are placed on the board. Die stacking has included different memory combinations that place flash memory with SRAM and RAM. Die stacking has evolved to multiple die stacks and side-by-side combinations of stacked and unstacked dies within a package.
The dies are mounted on a substrate which may then be bumped to create either a Chip Scale Package (CSP) or a Ball Grid Array (BGA) as the final package. Present die stacking techniques include mounting smaller dies onto larger ones to enable wire bonding of both, as well as techniques for stacking same-size die. To further increase the memory density and memory bandwidth available in a given size footprint, Package-on-Package (PoP) may be utilized to vertically connect multiple packages such as a logic package with a memory package, where each package may contain one or more die. Still, improvements in packaging are needed as the number of stacked-die in a package is expanded.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements.