The present invention relates to integrated circuit (IC) design, and more specifically, to a method and system for clock tree construction, an IC and a fabrication method thereof.
A typical IC may comprise a large amount of logic elements and other circuits for implementing IC logic functionality. Further, an IC chip may comprise a clock tree (i.e., a clock signal distribution network) for distributing a clock signal received at an input to all clock sinks that are “clocked” by the clock signal. A clock tree may comprise wires, buffers etc, to distribute the “clock signal” that controls the timing and operation of logical elements and other circuits of the IC. Clock sinks (or sinks) refer to logic elements or other circuits such as registers (flip-flops), RAM and latches, controlled by a clock signal, such that they add capacitance to the clock tree. Those sinks can change their states in response to clock signal pulses, and the IC synchronizes state changes in various sinks in a clock domain by clocking them with the same clock signal.
Clock skew is a significant aspect in assessing clock tree performance and quality. Clock skew generally refers to the difference (delay) between arrival times at any two clock sinks of a clock signal from an external clock source. Due to different path lengths of various branches to the respective clock sinks in a clock tree, there may be some clock skews between those various clock sinks. Further, in order to deliver the clock signal to every region of an IC, clock cells (buffers, for example) are generally inserted in the clock tree to amplify and/or retransmit the clock signal. However, because each clock cell has an intrinsic delay, it may cause a certain clock skew also. Thus, controlling or restricting the level number of buffers in a clock tree is one way for improving clock tree performance and IC design quality. Theoretically, smaller clock skews can be obtained, if there are less but the same levels of buffers contained in each branch leading to various clock sinks in a clock tree. However, the above assumption cannot be satisfied in practical IC design in many situations. With the technical evolution of digital IC design, a common path method is becoming more important for improving clock tree's skew and timing. A common path generally refers to a path consisted of buffers that are shared by multiple sinks in a clock tree. The longer the common path is, the smaller the clock skew of a clock signal arriving at sinks is. Traditional techniques employ a method to maximize the common path, that is, to allow sinks in a clock tree to share buffers at various levels as much as possible. In principle, the more buffers shared in a clock tree, the longer the common path will be. As a result, the performance of the clock tree may be optimized, and the quality of the IC designed may be improved. Other means for clock tree optimization include, for example, utilizing high performance clock cells (elements) capable of reducing clock skew, and the like.