The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs, and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, mask overlay has become increasingly important as device size shrinks. ICs are typically assembled by layering features on a semiconductor wafer using a set of photolithographic masks. Each mask in the set has a pattern formed by transmissive or reflective regions. During a photolithographic exposure, radiation such as ultraviolet light passes through or reflects off the mask before striking a photoresist coating on the wafer. The mask transfers the pattern onto the photoresist, which is then selectively removed to reveal the pattern. The wafer then undergoes processing steps that take advantage of the shape of the remaining photoresist to create circuit features on the wafer. When the processing steps are complete, photoresist is reapplied and wafer is exposed using the next mask. In this way, the features are layered to produce the final circuit.
Regardless of whether a mask is error-free, if all or part of the mask is not aligned properly, the resulting features may not align correctly with those on adjoining layers. This misalignment can result in reduced device performance or complete device failure. Conventional overlay metrology tools are used to check mask alignment but have not been satisfactory in all regards. The tools are expensive, slow, and are limited in their ability to detect variations within the die area.