The present invention relates to semiconductor storage devices, and in particular, to a semiconductor storage device having a nonvolatile memory for executing a collective erase verify operation.
Nonvolatile semiconductor storage devices have been remarkably developed in recent years, and in particular, the rewriting times of flash memories have been substantially shortened. However, about a half of the rewriting time is consumed by the verify operation of checking whether or not the data in a memory cell has been rewritten in conformity to an expected value, and therefore, it is indispensable to provide a device for reducing this verify operation time.
In view of the above, there has been an attempt at reducing the verify operation time by providing sense amplifiers corresponding in number to memory cells to be subjected to a simultaneous write operation and simultaneously verifying the memory cells subjected to the simultaneous write operation in the verify operation.
According to the above verify method, in regard to the write operation of the above rewrite operation, the number of memory cells to be subjected to the simultaneous write operation correspond to about 1 bit to 4 kbits. Since the data to be written into individual memory cells differ from one another, it can be considered efficient to simultaneously verify the memory cells of about 1 bit to 4 kbits subjected to the simultaneous write operation.
However, in regard to the erase operation of the rewrite operation, memory cells of not less than 2 kbits to 512 kbits are collectively erased and all the memory cells are rewritten into identical data ("0" or "1"). Therefore, the conventional verify operation, in which memory cells of about 1 bit to 4 kbits are simultaneously verified by sense amplifiers similar to the write operation, is hard to be considered efficient.
In view of the above, a variety of erase verify methods as follows have been proposed. It is to be noted that the term "verify" mentioned hereinafter means the erase verify.
The discrimination between 0 and 1 of information held in the memory cells of the nonvolatile semiconductor storage device is normally executed by detecting whether a threshold voltage of the memory cell transistor is high or low. However, the verify methods described below are the verify methods of a memory cell array in which the low threshold voltage state is defined as an erased state. The verify operation in this case is required to collectively check the event that the threshold voltages of all the memory cell transistors have been reduced (i.e., the event that a current flows through all the memory cell transistors when a voltage intermediate between the high and low threshold voltages is applied to the gates of all the memory cell transistors).
(1) The erase operation is completed at the point of time when the event that a current has flowed through the memory cell transistor exhibiting the minimum threshold voltage among all the memory cell transistors is detected (Japanese Patent Laid-Open Publication No. HEI 4-3395.)
(2) The n(n: integer) memory cells connected to one word line are simultaneously verified by the same number of decision circuits (Japanese Patent Laid-Open Publication No. HEI 8-227590). This verify method has the same concept as that of the line test proposed in connection with the prior art DRAM (Dynamic Random Access Memory) and the like.
(3) In a virtual ground type memory cell array, when a current flows by applying a voltage in series across the sources and the drains of a number of memory cell transistors connected to one word line, it is decided that all the memory cells connected to the word line have been erased (Japanese Patent Laid-Open Publication No. HEI 7-111901).
However, the aforementioned prior art nonvolatile semiconductor storage device verify methods have the problems as follows.
That is, as stated before, the above verify methods are executed by collectively checking whether or not a current flows through all the memory cell transistors when the voltage intermediate between the high and low threshold voltages is applied to the gates of all the memory cell transistors.
However, the operation of collectively verifying the event that a current flows through all the memory cells is required to detect one memory cell through which no current flows among a number of memory cells through which currents are flowing, and this is very hard to be achieved physically.
For example, according to the verify method listed in the item (1), the erase operation is executed by reducing the threshold voltages of the memory cell transistors from a programmed state D1 to an erased state D2 as indicated by the memory cell transistor threshold voltage distribution shown in FIG. 13. Then, the completion of the verify operation is determined by detecting the event that the threshold voltage A of the memory cell which is most likely to be erased has lowered from a word line selection voltage C in the verify operation. Accordingly, there still remains the possibility that the threshold voltage B of the memory cell which is least likely to be erased is greater than the selection voltage C and is kept intact in the programmed state, and this poses the problem that the erasing of all the memory cells has been verified.
According to the verify method listed in the item (2), the n memory cells connected to one word line are simultaneously verified by the same number of decision circuits, and therefore, the problem of the verify method (1) can be solved. However, the method has the problem of an increase in area for the requirement of n decision circuits identical in number to the n memory cells to be verified collectively and the problem of an increase in time of the verify operation for the requirement of the verify operation times in a cycle identical to the number m(m: integer) of the word lines.
According to the verify method listed in the item (3), the problem of the verify method (1) can be solved. However, if the ON-state resistance of the memory cell transistor and the substrate effect are taken into consideration, the method has the problem that the current is too infinitesimal and the problem that not so much memory cell transistors can be connected and simultaneously verified due to an increase in threshold value.