1. Field of the Invention
The present invention relates to a sample-and-hold circuit.
2. Description of the Related Art
A sample-and-hold circuit as shown in FIG. 3, which constitutes a part of an active matrix type liquid crystal driver circuit is known. Analog signals are input to the sample-and-hold circuit through signal lines V1 to Vn. The sample-and-hold circuit is provided with capacitors C1 to Cn and capacitors D1 to Dn for sampling and holding input voltages from the signal lines (the capacities of those capacitors include wire capacitances and stray capacitances). Ends on one side of the capacitors C1 to Cn are connected to the signal lines V1 to Vn through the analog switches S1 to Sn which are turned on and off by control signals SS1 to SSn, respectively, and the other ends of the capacitors C1 to Cn are all connected to ground. Ends on one side of the capacitors D1 to Dn are connected to the ends on one side of the capacitors C1 to Cn through analog switches H1 to Hn which are turned on and off by a control signal HS. The other ends of the capacitors D1 to Dn are connected to ground. Noninverting input terminals of operational amplifier circuits P1 to Pn are connected to the ends on one side of the capacitors D1 to Dn, respectively, while the inverting input terminals are connected to output terminals thereof, respectively. The output terminals of the operational amplifier circuits P1 to Pn are tied to a common line. Output control signals CN1 to CNn are input respectively to the operational amplifiers.
When high-level control signals SS1 to SSn are input respectively to the analog switches S1 to Sn, the analog switches turn on, for this input period, so that the capacitors C1 to Cn are connected to the signal lines V1 to Vn and charged. When the control signals SS1 to SSn go to the low level to turn off the switches S1 to Sn, the signal voltages just before that are held in the capacitors C1 to Cn, respectively. Then, when a high-level control signal HS is input, the switches H1 to Hn turn on for the input period, so that the capacitors D1 to Dn are respectively connected in parallel with the capacitors C1 to Cn and charged. After the control signal HS goes to the low level to turn off the switches H1 to Hn, the capacitors D1 to Dn hold voltages corresponding to the voltages heretofore held by the capacitors C1 to Cn, respectively.
When specified, output control signals CN1 to CNn are applied to the operational amplifier circuits P1 to Pn, respectively, their outputs are made active, and the voltages supplied to the noninverting input terminals are output, respectively. Therefore, by using control signals CN1 to CNn, it is possible to determine which of the voltages held by the capacitors D1 to Dn are output. For example, in case that a control signal CN1 is applied to the operational amplifier circuit P1, the output of the operational amplifier circuit P1 is made active, and the voltage held in the capacitor D1 is output as the output Vo. By changing over the control signals CN1 to CNn respectively, the voltages held in the capacitors D1 to Dn are output sequentially as the output Vo from the operational amplifier circuits P1 to Pn.
However, in such a sample-and-hold circuit, operational amplifier circuits are provided as buffer circuits on a one-to-one correspondence with the capacitors D1 to Dn. As a result, the number of devices constituting the sample-and-hold circuit is large. Accordingly a large chip area is required when this circuit is formed as an integrated circuit.