The present invention relates to the field of electronic design automation and, in particular, to improved techniques for performing optical proximity correction.
The manufacture of integrated circuits strives to place ever smaller features onto a given area of the integrated circuit chip. One challenge encountered in this effort to fabricate smaller features is the diffraction of the light used in photolithography. That is, the quality and fidelity of the microlithography stage of very large scale integrated (VLSI) circuit chip production depends on the wavelength of the light source and the size of the features to be printed.
Recent sub-wavelength lithography approaches aim to use wavelengths that are larger than the minimum feature size to generate the images, (e.g., light with a wavelength of 193 nanometers is being used to generate features with dimensions of 90, 65, or 45 nanometers). This approach, however, requires methods for the correction of degradations and distortions in the final pattern caused by light diffraction. That is, the photolithography mask used to generate the desired circuit pattern includes structures that anticipate and, at least partially correct for, the imperfections arising from striving to fabricate small features.
A computational simulation of the exposure and lithographic is run and the degradations or distortions are computed with various additions, inclusions and adjustments to the mask design. A mask design is selected that improves the final structure. These methods, commonly known as optical proximity correction (OPC), are mainly dependent on the optical system and mask features and may be computationally intensive. While regions having densely packed features tend to be more prone to distortions (the “proximity” effect), OPC calculations are not limited to such regions and can be advantageously applied to less-dense regions of the circuit.
OPC typically numerous features in a pattern layout to be computationally processed one or more times. Recent advances in semiconductor manufacturing allow billions of transistors (i.e., multibillion features) to be placed on a single chip. The well-known “Moore's law” postulates that the number of transistors that can be placed on a single chip doubles about every 12-24 months. Unfortunately, despite the advances in the central processing unit (CPU) clock speed and computing power, the gap between the computational power required for OPC calculations and the available CPU processing power keeps increasing. That is, the computing power required to efficiently execute the OPC calculations in a timely manner is growing at a faster rate than the available CPU power in a reasonably priced engineering workstation.
To further complicate the issue, the number of masks or layers to which OPC should be applied increases at each new semiconductor device manufacturing node. Since the features are getting smaller with every manufacturing node while the illumination wavelengths remain the same or decrease at a slower rate, the number of neighboring features effecting the fidelity of each feature increases. Therefore, the computational processing power required to perform OPC operations on new chip designs has been increasing at a rate of approximately factors of three or four or more for each successive manufacturing node.
Presently, the generation of optically corrected masks takes from many hours to several days per mask and the complexity of this process continues to grow. Because the features printed after the OPC process may still be different from the desired features, the impact of each feature on the functionality and performance of the chip needs to be readdressed in an iterative manner. A typical VLSI design process consists of several iterations of mask generation, OPC process, and interpretation of the results. These iterations may contribute several months of delay in the chip qualification and manufacturing process.
The persistent time-to-market pressures on new chip designs mandate improved methods to estimate and shorten the impact of the OPC process in the early stages of the design. Since it is computationally prohibitive to perform many iterations of OPC on a full-chip scale, partial or simple model-based OPC approaches are being applied in limited fashion, still necessitating full-chip OPC once the design is completed.
Therefore, a need exists in the art for improved systems and methods that shorten the time required to perform OPC, improve the accuracy of OPC methods, and are scalable to address larger chip designs.