In the field of electronic devices, such as systems on a chip, a phase lock loop is often used to generate a master clock signal. That master clock signal is then divided downward into a variety of different clock signals for use by different components within the system on chip.
This division is performed by coupling multiple divider circuits to the output of the phase locked loop. For example, a divide by 2, a divide by 4, and a divide by 8 divider circuit are each coupled to the phase locked loop. However, this approach has drawbacks. For example, power consumption may be undesirably high.
It is therefore desirable for new divider circuits to be developed.