The present invention relates to interconnect structures for high-speed microprocessors, application specific integrated circuits (ASICs), and other high-speed integrated circuits (ICs). More particularly, the present invention provides an interconnect structure of the dual damascene-type which includes a low dielectric constant (i.e., low-k) dielectric having Cu regions formed therein. The Cu interconnect structures of the present invention have enhanced circuit speed and reduced fabrication cost. Moreover, the inventive interconnect structures contain an inventive diffusion barrier layer that is used as a post-CMP (chemical-mechanical polishing) cap.
Many low-k dielectrics having a dielectric constant, k, of about 3.5 or less, plus Cu interconnect structures are known in the art; See, for example, R. D. Goldblatt, et al., xe2x80x9cA High Performance 0.13 xcexcm Copper BEOL Technology with Low-K Dielectricxe2x80x9d, Proceedings of the International Interconnect Technology Conference, IEEE Electron Devices Society, Jun. 5-7, 2000 pgs. 261-263. Such prior art interconnect structures include inorganic, organic or mixed dielectric materials as the interlevel or intralevel dielectric. It is widely accepted that dual-damascene structures are lower cost than single damascene or subtractive metal structures.
Typically, there are two essential problems associated with prior art Cu interconnect structures which include: Cu migration out of the conductive regions into the surrounding dielectric which causes a reliability problem with the structure; and increasing cost of fabricating the interconnect structure due to increasing number of processing steps and expensive tools. A discussion concerning the problem of Cu migration in Cu interconnect structures is found, for example, in A. Loke, et al., xe2x80x9cEvaluation of Cu Penetration in Low-k Polymer Dielectrics by Bias-Temperature Stressxe2x80x9d, Mat. Res. Soc. Symp. Proc., Vol. 565 (1999) p. 173.
Common solutions to the above problems add additional processing steps, thus further increasing the cost to fabricate the desired low-k plus Cu interconnect structure. Furthermore, the post-CMP cap layers in prior art dual damascene structures are made using vacuum-based plasma-enhanced chemical vapor deposition (PECVD) tools that are costly to purchase and maintain.
Co-assigned U.S. application Ser. No. 09/371,340 filed Aug. 10, 1999 provides an interlayer dielectric that is capable of reducing or eliminating Cu ion migration. Specifically, the interlayer dielectric of the ""340 disclosure comprises a dielectric material having a dielectric constant of 3 or less and an additive. The additive employed therein is capable of binding Cu ions, is soluble in the dielectric material and is substantially, uniformly distributed throughout the dielectric. This disclosed interlayer dielectric is not used as a spin-on dielectric in the ""340 disclosure.
In view of the above-mentioned problems in prior art processes of fabricating dual damascene-type structures, there is a continued need for providing a new and improved method for forming such interconnect structures which substantially minimizes Cu migration into the surrounding dielectric layers, without adding extra processing steps and cost in fabricating the interconnect structure.
One object of the present invention is to provide an interconnect structure which includes a new diffusion barrier layer (i.e., post-CMP cap) that substantially minimizes the migration of Cu into the surrounding low-k dielectrics.
A further object of the present invention is to provide a Cu interconnect structure of the dual damascene-type that is made without any vacuum-based PECVD tools.
A still further object of the present invention is to provide a Cu interconnect structure that has an effective low dielectric constant (on the order of about 3.5 or less), which is easy to manufacture and does not include extra processing steps that would increase the cost of fabricating the same.
These and other objects and advantages are achieved in the present invention by providing a diffusion barrier layer (i.e., post-CMP cap) that is based on a spin coated dielectric layer. Specifically, the diffusion barrier layer of the present invention (hereinafter referred to as spin-on cap) comprises a low-k dielectric (on the order of about 3.5 or less) that includes at least one additive. The at least one additive employed in the present invention is capable of binding Cu ions, and is soluble in the spun-on low-k dielectric. The spin-on cap of the present invention may further include a spun-on low-k (on the order of 3.5 or less) reactive-ion etch (RIE) stop layer. Spin-on caps containing a bilayer of low-dielectric plus at least one additive and low-k RIE stop layer are preferred. It is noted that the inventive spin-on cap does not significantly increase the effective dielectric constant of the interconnect structure and does not add additional cost to the fabrication of the interconnect structure since a single deposition tool, i.e., spin coating tool, is employed.
One aspect of the present invention relates to a Cu interconnect structure which includes the inventive spin-on cap as a post-CMP cap. Specifically, the inventive Cu interconnect structure comprises:
a substrate having a patterned low-k interlevel dielectric formed thereon, said patterned low-k interlevel dielectric having an effective dielectric constant of about 3.5 or less;
Cu conductive regions formed within said patterned low-k interlevel dielectric;
a polish stop layer on surfaces of said patterned low-k interlevel dielectric not containing said Cu conductive regions; and
a spin-on cap present on said Cu conductive regions and said polish stop layer, wherein said spin-on cap comprises a low-k dielectric having a dielectric constant of about 3.5 or less and at least one additive, wherein said at least one additive is capable of binding Cu ions, and is soluble in the spun-on low-k dielectric.
In one embodiment of the present invention, the polish stop layer is not present on the patterned low-k interlevel dielectric. Instead, in this embodiment, the spin-on cap is formed on the patterned low-k interlevel dielectric.
Another aspect of the present invention relates to a method of fabricating the above mentioned Cu interconnect structure. Specifically, the method of the present invention comprises the steps of:
(a) forming a low-k interlevel dielectric on a surface of a substrate, said low-k interlevel dielectric having an effective dielectric constant of about 3.5 or less;
(b) forming a hard mask on said low-k interlevel dielectric, said hard mask including at least a polish stop layer;
(c) forming an opening in said hard mask so as to expose a portion of said low-k interlevel dielectric;
(d) forming a trench in said low-k interlevel dielectric using said hard mask as an etch mask;
(e) filling said trench with at least Cu;
(f) planarizing said Cu stopping on said polish stop layer; and
(g) forming a spin-on cap on said Cu and said polish stop layer, wherein said spin-on cap comprises a low-k dielectric having a dielectric constant of about 3.5 or less and at least one additive, wherein said at least one additive is capable of binding Cu ions, and is soluble in the spun-on low-k dielectric.
The term xe2x80x9ctrenchxe2x80x9d as used herein denotes a line, via or a combination of a line and via. In one embodiment of the present invention, step (b) above is omitted.