1. Field of the Invention
The present invention relates to a chemical mechanical polish (CMP) process, and more particularly, to a CMP process and a method for improving accuracy of determining a polish endpoint thereof.
2. Description of the Related Art
With advance of semiconductor technology, number of transistors which can be fabricated in a chip per unit area is increased. The higher the device integrity is, the more the unplanar surface of a chip is undesirable. As a result, enhancing surface planarization of a chip becomes essentially important. A chemical mechanical polish (CMP) process is a method to provide a uniform surface planarization, and has become a vital thin film planarization technique for deep sub-micron technology.
Use the commonly applied tungsten plug CMP process as an example. FIG. 1A is a cross sectional view of a prior art metal interconnect structure. The silicon oxide layer 111 is formed on the substrate 101 of the chip 100. The silicon oxide layer 111 comprises the opening 130. The adhesion layer 140 covers the silicon oxide layer 111. The material of the adhesion layer 140 can be, for example, titanium nitride/titanium (TiN/Ti). The conductive layer 150 is formed over the adhesion layer 140. The material of the conductive layer 150 can be, for example, tungsten. The opening 130 serves as a contact hole. The adhesion layer 140 and the conductive layer 150 filled in the opening 130 serve as a conductive plug. Since conductive lines are formed on the surface of the silicon oxide layer 111 to connect with the conductive plugs, the adhesion layer 140 and the conductive layer 150 over the surface of the silicon oxide layer 111 should be removed by a CMP process.
In order to avoid residues, dishing, or erosion resulting from under-polish or over-polish by the CMP process, how to accurately detect polish endpoints of the CMP process becomes an important topic in this field. For the presently used method of determining the polish endpoint, an IR light irradiates the conductive layer 150 while the to-be-polished layer, e.g., the conductive layer 150 and the adhesion layer 140 of FIG. 1A, is polished by the CMP process. The reflection of the IR light from the to-be-polished layer is continuously detected. Most of the material of the to-be-polished layer contains metal, and the silicon oxide layer 111 is non-metal. Accordingly, the reflection of the IR light from the to-be-polished layer is much stronger than that from the silicon oxide layer 111. When the reflection is weakened, it can be determined that the to-be-polished layer is removed and the surface of the silicon oxide layer 111 is exposed. At this moment, it also indicates the polish endpoint of the CMP process.
In another aspect, since the device integrity is increased due to advance of semiconductor technology, the high device integrity reduces line width and increases difficulty for photolithographic process. As a result, the misalignment issue is easy to happen. The issue becomes serious when a reflective layer, such as a metal layer or a polysilicon layer, is included in the structure. The reflective layer results in reflection of incident light on the film surface and diffraction. Thus, the photolithographic pattern may be incorrectly transferred. To prevent the issue described above, an anti-reflection coating (ARC) layer or a dielectric anti-reflection coating layer (DARC) layer is formed on the film layer to reduce the errors caused by the reflection during the photoresist exposure step, and to enhance device yield.
Though the ARC layer or the DARC layer is necessary for the photolithographic process, a new issue arises. During the CMP planarization process, the layer that should be polished is the material layer 120 of FIG. 1B, rather than the original single silicon oxide layer 111. The material layer 120 comprises, for example, the silicon oxide layer 111, the first DARC layer 113, the second DARC layer 115 and the cap oxide layer 117, which are sequentially formed on the substrate 101. These film layers enhance reflection of the IR light, which becomes irregular from the original reflection. With reducing the thickness of the to-be-polished layer, the reflection of IR light is enhanced and reflection variation becomes severe. This phenomenon may make the polish endpoint detection failed. If the film layers are under-polished, the residue of the material layer 120 may be generated on the conductive layer 150, causing bridge. In contrast, if the film layers are over-polished, the material layer 120 may be eroded. The material layer 120 may become thinner, and the conductive layer 150 is also subject to the over-polish. In a high-density device, the dielectric material among the metal interconnect structure is not sufficient to serve electrical isolation so as to affect device operation.