The present invention disclosed herein relates generally to memory systems, and more particularly, to memory systems and memory cards in which a bad block is used in a single level cell (SLC) mode.
Recently, the number of devices using nonvolatile memories has increased. For example, an MP3 player, a digital camera, a mobile phone, a camcorder, a flash card, and a solid state disk (SSD) are examples of devices that use nonvolatile memories as storage devices.
As more devices use nonvolatile memories as storage devices, the capacity of the nonvolatile memory is drastically increasing. One method for increasing memory capacity is a so-called multi level cell (MLC) method in which a plurality of bits is stored in one memory cell.
FIG. 1 is a block diagram illustrating a conventional memory system. Referring to FIG. 1, a conventional memory system 100 includes a host 110, a memory controller 120, and a flash memory 130.
The memory controller 120 includes a buffer memory 121. The flash memory 130 includes a cell array 131 and a page buffer 132. Although not shown in FIG. 1, the flash memory 130 includes a decoder, a data buffer, and a control unit.
The memory controller 120 receives data and a write command from the host 110, and controls the flash memory 130 to program data into the cell array 131. Also, the memory controller 120 controls the flash memory 130 to read data stored in the cell array 131 according to a read command input from the host 110.
The buffer memory 121 temporarily stores therein data to be programmed into the flash memory 130, and data read from the flash memory 130. The buffer memory 121 transfers the temporarily stored data to the host 110 or the flash memory 130 under control of the memory controller 120.
The cell array 131 of the flash memory 130 includes a plurality of cells. The memory cells are nonvolatile and can retain stored data even when no power is applied. A page buffer 132 is a buffer that stores data to be programmed into a selected page of the cell array, or data read from a selected page.
A memory cell of the flash memory 130 is categorized into a single level cell (SLC) and a multi level cell (MLC) according to the number of data bits that can be stored therein. The SLC can store single-bit data, and the MLC can store multi-bit data.
The SLC, a memory cell storing single-bit data, will now be described. The SLC has two states depending on distribution of a threshold voltage. After being programmed, the memory cell stores data 1 or data 0. A memory cell storing data 1 is considered to be in an erase state, and storing data 0 is considered to be in a program state. The cell in the erase state may be called an “on-cell,” and the cell in the program state may be called an “off-cell.”
The flash memory 130 performs a program operation by page. The memory controller 120 transfers data to the flash memory 130 by page, using the internal buffer memory 121 during a program operation.
The page buffer 132 temporarily stores data loaded from the buffer memory 121, and simultaneously programs the loaded data to a selected page. After the program operation is completed, a program verification operation for verifying whether data is correctly programmed or not is performed.
If the program verification result is a “program fail,” a program operation and a program verification operation are performed again with an increased program voltage. After the program operation for one-page of data is completed in the above described manner, the next data are received for a program operation.
An MLC, a memory cell storing multi-bit data, will now be described. FIGS. 2 and 3 illustrate a process of programming a least significant bit (LSB) and a most significant bit (MSB), that is, 2-bit data, into one memory cell.
Referring to FIG. 2, a memory cell is programmed to have any one of four states 11, 01, 10 and 00 according to distribution of a threshold voltage. First, a process of programming the LSB is the same as that of programming of the SLC. A memory cell having a state 11 is programmed to have a state A indicated by a dotted line according to the LSB.
To program the MSB, the memory controller transfers one-page data in the buffer memory 121 to the flash memory 130. Referring to FIG. 2, the memory cell in state A indicated by a dotted line is programmed to be in state 00 (program 1) or be in state 10 (program 2) according to the MSB. A memory cell in state 11 maintains state 11 or is programmed to be in state 01 (program 3) according to the MSB.
Referring to FIG. 3, a memory cell is programmed to have any one of four states 11, 10, 00 and 01 according to distribution of a threshold voltage. First, a memory cell in state 11 maintains the state 11 or is programmed to be in state 10 (program 1) according to the LSB. Thereafter, the MSB is programmed. A memory cell in state 10 maintains the state 10 or is programmed to be in state 00 (program 2) according to the MSB. A memory cell in state 11 maintains the state 11 or is programmed to be in state 01 (program 3) according to the MSB.
Referring again to FIG. 1, the memory system 100 uses the above-described method to program multi-bit data into the cell array 131 of the flash memory 130. That is, the LSB is programmed first in a memory cell, and then the MSB is programmed in the same memory cell.
While the MSB is programmed after the programming of the LSB, a program fail may occur. In general, a possibility of a program fail is relatively low in the case of an SLC, while being relatively high in the case of an MLC because of a small threshold voltage margin of the cell. As the number of bits programmed in one MLC increases, the possibility of the program fail gradually increases.
In conventional MLC technology, a program fail occurs when the MSB is programmed after the LSB is normally programmed. In this case, a memory block including a fail cell is processed as a bad block. The fail cell cannot be restored even by an error correction circuit (ECC). Thus, in conventional MLC technology, because the memory block including a fail cell is processed as a bad block, even normal cells in the bad block become unavailable for an LSB programming operation.