The present inventive concept relates to a delay locked loop (DLL), and more particularly, to a DLL for generating a clock signal having a frequency obtained by multiplying the frequency of a reference clock signal, and having an accurate phase delay and a constant duty cycle by compensating for an error occurring due to process variation.
A DLL may be used to generate an internal clock signal in electronic devices. The DLL usually delays an external clock signal by a predetermined period of time using a delay line and generates an internal clock signal synchronized with the external clock signal. The DLL may be used to generate a timing signal for the operation of a semiconductor memory device, e.g., dynamic random access memory (DRAM), that is, a signal used to read data from the semiconductor memory device or write data thereto.
To increase the data transmission speed between electronic devices, it is necessary to increase the frequency of an internal clock signal of the electronic devices. To decrease errors occurring in high-speed data transmission, a data valid window needs to be accurately positioned. For instance, when an internal clock signal having a frequency obtained by multiplying the frequency of an external clock signal is used in a semiconductor memory device, the data transmission speed of the semiconductor memory device can be increased. In addition, errors in high-speed data transmission can be reduced when clock signals having an accurate phase delay and an accurate duty cycle are used.
When the frequency of the internal clock signal increases, however, harmonic locking may occur during the locking operation of the DLL. Also, the influence of process variation is increasing with the microminiaturization of manufacturing technology. Accordingly, it is increasingly difficult to generate a clock signal having an accurate phase delay and a constant duty cycle due to phase delay mismatch between delay lines of the DLL.