Silicon integrated circuits continue to grow ever denser, requiring that the gate oxides in FETs (field effect transistors) be thinner and, in particular, that the gate electrodes in the FETs become narrower. Said gate electrodes are most usually made of polysilicon and, until relatively recently, were patterned by conventional use of photoresist masking.
However, as gates have grown narrower, use of a photoresist mask has become increasingly problematical. There are a number of reasons for this--undercutting of the photoresist during etching, which can be tolerated in wider lines, introduces a degree of uncertainty into the process which can no longer be tolerated in very narrow lines; because of the high level of resolution required, the photoresist layer must be thinner than that used for etching wider lines; sensitivity of photoresist-based processes to process parameters such as exposure wavelength, brand of resist used, etc. becomes more of a problem; and line width control, and reduction of line edge roughness, through use of photoresist trimming, becomes more difficult if the photoresist is also used as the primary etch mask.
Another factor that needs to be considered when forming structures through etching is the need to use an ARC (anti-reflection coating). This is laid down just below the photoresist layer to prevent formation of standing wave patterns within the resist. ARCs may be either organic or inorganic, the former being relatively thick while the latter are relatively thin. For reasons that will become apparent, an inorganic ARC is part of the present invention.
A routine search of the prior art was performed but no references that describe the exact process taught by the present invention were discovered. Several references of interest were, however, encountered. For example, Bell (U.S. Pat. No. 5,767,018) determined that a process being used by him to etch a silicon oxynitride ARC caused pitting of the polysilicon gate structure. Polymer formation during etching was considered to be a large contributor to this problem so an etchant that did not form a polymer was selected. This allowed a passivating coating to form on the sidewalls as the polysilicon was etched (using HBr/Cl.sub.2 /He--O.sub.2). The final step was an anisotropic etch that cleaned the top surface of the gate without removing the protective layer from the sidewalls.
Kumar et al. (U.S. Pat. No. 5,851,926) teach use of a tungsten silicide hard mask together with an NF.sub.3 and Cl.sub.2 etch to achieve vertical edges for a polysilicon gate. Keller (U.S. Pat. No. 5,346,586) etches a polysilicon layer that has been coated with a silicide layer by first forming an oxide hard mask and then successively etching the suicide and polysilicon layers.
Muller (U.S. Pat. No. 5,674,409) shows a photoresist trim process for forming lines while Shin et al. (U.S. pat. No. 5,914,276) describe a process for etching a polycide/polysilicon gate.