1. Field of the Invention
This invention relates to integrated circuit manufacturing generally and, more particularly, to a method of planarizing a semiconductor wafer prior to the formation of circuits thereon.
2. Description of the Prior Art
In dielectric isolated (DI) wafer fabrication, bonded wafers are becoming less expensive than wafers made by existing grow-handle-and-grind methods of DI wafer fabrication. However, bonded wafers in general may not be sufficiently fiat for advanced integrated circuit manufacturing, e.g., submicron CMOS technology. There exists a need for an inexpensive process for planarizing bonded wafers, preferably using existing grinding/polishing equipment found in many chip manufacturing plants.