1. Field of the Invention
The present invention relates to a semiconductor memory capable of executing a read test for stored contents comparatively easily, and more particularly to a nonvolatile semiconductor memory such as an electrically writable/erasable flash memory.
2. Description of the Background Art
In general, the production cost of a memory implies the total of the cost required for a wafer process, an assembly and a test. The cost of the test depends on how many chips can be tested per unit time by means of one tester. In order to reduce the test cost to produce a more inexpensive memory, accordingly, it is required that the prolongation of a test time caused by an increase in a storage capacity of the memory should be minimized even if the storage capacity of the memory is increased twofold to fourfold with an increase in the capacity.
In order to shorten a test time of the memory, the following should be implemented:
(1) a reduction in an operation time required for write, read or the like;
(2) development of a test pattern having a higher defect detecting capability; and
(3) development of a test mode capable of carrying out write/read at a higher speed.
Referring to (1), an increase in a speed of production has been required. Therefore, the test time tends to be shortened comparatively easily without a special contrivance through an enhancement in transistor performance by microfabrication and a reduction in a load capacity.
Referring to (2), there are various test patterns having high defect detecting capabilities. Typically, a checker board pattern can be taken as an example.
FIG. 95 is a diagram illustrating an example of the checker board pattern. FIG. 95 shows a checker board pattern having one bit/cell (binary-value).
As shown in FIG. 95, a checker board pattern CHK2 is a test pattern having a repetitive cycle of 2 bits in which adjacent bits always have a relationship of xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d. The checker board pattern CHK2 can detect open (disconnection) and a short circuit of a word line, open and a short circuit of a bit line, and a defective short circuit of floating gates in a nonvolatile semiconductor memory represented by a flash memory.
FIG. 96 is a diagram illustrating a checker board pattern CHK4 having 2 bits/cell (quaternary-value). As shown in FIG. 96, 2-bit patterns CHK4-A to CHK4-D are repeated every 4-bit repetitive cycle in order to correspond to the quaternary-value (2 bits/cell) to be multiple-valued storage through application of the checker board pattern CHK2 shown in FIG. 95.
FIG. 97 is a diagram illustrating a checker board pattern CHK8 having 3 bits/cell (octal-value). As shown in FIG. 97, a 3-bit pattern is repeated every 8-bit repetitive cycle in order to correspond to the octal-value (3 bits/cell) to be multiple-valued storage.
In the checker board pattern CHK4 and the checker board pattern CHK8, it is possible to detect a defective mode of the checker board pattern CHK2, and furthermore, to detect that all multiple-valued data can be written and read or not in the same word line and the same bit line.
Referring to (3), there have been various methods. In general, if a test mode is incorporated into a chip, a chip area tends to be increased due to an incorporated circuit. Consequently, a cost required for a wafer process is increased. Accordingly, in the case in which the test mode is to be incorporated into the chip, it is necessary to note that the total production cost should be minimized.
Next, the trend of a product of a flash memory and that of development will be described.
As an alternative to an EPROM (electrically writable nonvolatile semiconductor memory), a flash memory has spread for code storage. In recent years, a flash memory for mass data storage has spread more increasingly than the flash memory for code storage. In the case in which the flash memory for data storage carries out writing and reading randomly, it operates at a lower speed than that of the flash memory for code storage. However, in the case in which the flash memory for data storage carries out writing and reading sequentially, it can operate at a higher speed than that of the flash memory for code storage. The flash memory for data storage has had a larger capacity to exceed a DRAM through microfabrication of a processing pattern and a multiple-valued technique for storing multibit data in one memory cell.
Next, a test time for the flash memory will be described.
The flash memory for code storage has such a structure that a reading operation can be carried out at a much higher speed than a writing operation. Therefore, a time required for a read test can be almost ignored with respect to the whole test time. However, the flash memory for data storage carries out the writing operation at a higher speed and has a larger capacity than the flash memory for code storage. Therefore, the time required for the read test cannot be disregarded with respect to the whole test time.
For example, a 256 Mbit flash memory has a 16 Ksector structure in which a 2 Kbyte write/read unit (hereinafter referred to as a xe2x80x9csectorxe2x80x9d) is present for 16K. Approximately 50 xcexcs is required for a reading head every sector (hereinafter referred to as a xe2x80x9c1st accessxe2x80x9d) and 50 ns is required for subsequent data transfer every byte.
Accordingly, approximately 2.5 s ((50 xcexcs+50 nsxc3x972 Kbyte)xc2x716 Ksector) is required for carrying out a read test in the whole area of the 256 Mbit flash memory.
In a probing check stage of a wafer state, furthermore, it is hard to carry out a read test with a 2nd access 50 ns of a product specification due to a resistance and a capacitance of a probe needle and a resistance and a capacitance of a probe card, and a test time is further increased.
In general, the flash memory has an automatic writing/erasing function. The automatic writing function implies a function of repeating a write pulse applying operation and an operation (hereinafter referred to as a xe2x80x9cverify operationxe2x80x9d) for deciding whether desirable data are written (or erased) to (or from) an object memory cell for writing in accordance with a logic circuit (hereinafter referred to as a xe2x80x9ccontrol circuitxe2x80x9d) provided in an EEPROM, ending the repetition of the write pulse applying operation and the verify operation when it is decided that all the object memory cells store the desirable data and outputting a signal for giving, to the outside of the EEPROM, a notice that the writing operation (or the erasing operation) has been completed.
In order to decide whether xe2x80x9cthe contents stored in all the object memory cells are the desirable dataxe2x80x9d, an all latch deciding circuit (hereinafter referred to as an xe2x80x9cALL deciding circuitxe2x80x9d) is provided. The ALL deciding circuit serves to decide that all sense latches in a sense latch group provided for storing the result of read of the memory cell are xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
FIG. 98 is a block diagram schematically showing a conventional ALL deciding circuit and a periphery thereof. In this specification, it is assumed that the case in which xe2x80x9c1xe2x80x9d is written to the memory cell is set to xe2x80x9cwritexe2x80x9d and the case in which xe2x80x9c0xe2x80x9d is written to the memory cell is set to xe2x80x9cerasexe2x80x9d. Referring to FIG. 98, description will be given in which a left memory cell group 31 is referred to as an L mat 31 and a right memory cell group 32 is referred to as an R mat 32.
As shown in FIG. 98, a sense latch group 33 is provided between the L mat 31 and the R mat 32. The sense latch group 33 transmits and receives data in a sector unit to and from the L mat 31 or the R mat 32. The latch data of the sense latch group 33 are output to an ALL deciding circuit 34.
The ALL deciding circuit 34 receives control signals LorR, 0or1 and ENABLE from an external control CPU 35 and outputs a decision result ALL34 to the control CPU 35. xe2x80x9c0xe2x80x9d/xe2x80x9c1xe2x80x9d of the LorR designates reading from the L mat 31/R mat 32, xe2x80x9c0xe2x80x9d/xe2x80x9c1xe2x80x9d of the 0or1 designates write verify/erase verify, and xe2x80x9c0xe2x80x9d/xe2x80x9c1xe2x80x9d of the ENABLE designates inactivity/activity of the ALL deciding circuit 34.
FIGS. 99 to 102 are diagrams illustrating an operation principle of a conventional ALL deciding circuit, in which the ALL deciding circuit has a function of deciding that all sense latches are xe2x80x9c0xe2x80x9d.
As shown in FIGS. 99 to 102, the sense latch group 33 is provided between the L mat 31 and the R mat 32, and nodes N11 and N12 of each latch L33 of the sense latch group 33 are connected to the L mat 31 and the R mat 32 in one memory cell unit, respectively. The node N11 and the node N12 in the latch L33 are constituted to have a logical inverting relationship. A data latch group 36 is provided on the opposite side of the sense latch group 33 with the L mat 31 interposed therebetween, and a data latch group 37 is provided on the opposite side of the sense latch group 33 with the R mat 32 interposed therebetween.
First of all, the ENABLE is set to xe2x80x9c1xe2x80x9d for initialization and the ALL deciding circuit 34 is thus brought into an active state.
As shown in FIG. 99, when the write verify for the L mat 31 is to be carried out, LorR=xe2x80x9c0xe2x80x9d (L) and 0or1=xe2x80x9c1xe2x80x9d are set so that data read from the L mat 31 are latched onto each latch L33 of the sense latch group 33. If xe2x80x9c1xe2x80x9d is normally written to the L mat 31, the nodes N11 of all the latches L33 of the sense latch group 33 are set to xe2x80x9c1xe2x80x9d and the nodes N12 are set to xe2x80x9c0xe2x80x9d.
Accordingly, it is possible to execute the L mat write verify by deciding the state of the nodes N12 of all the latches L33 in the sense latch group 33 (whether all of them are xe2x80x9c0xe2x80x9d) through the ALL deciding circuit (R side sense latch decision).
As shown in FIG. 100, similarly, when the erase verify for the L mat 31 is to be carried out, LorR=xe2x80x9c0xe2x80x9d and 0or1=xe2x80x9c0xe2x80x9d are set. If xe2x80x9c0xe2x80x9d is normally written to the L mat 31, the nodes N11 of all the latches L33 in the sense latch group 33 are set to xe2x80x9c0xe2x80x9d and the nodes N12 are set to xe2x80x9c1xe2x80x9d.
Accordingly, it is possible to execute the L mat erase verify by deciding the state of the nodes N11 of all the latches L33 in the sense latch group 33 through the ALL deciding circuit (L side sense latch decision).
As shown in FIG. 101, when the write verify for the R mat 32 is to be carried out, LorR=xe2x80x9c1xe2x80x9d (R) and 0or1=xe2x80x9c1xe2x80x9d are set so that data read from the R mat 32 are latched onto each latch L33 of the sense latch group 33. If xe2x80x9c1xe2x80x9d is normally written to the R mat 32, the nodes N12 of all the latches L33 of the sense latch group 33 are set to xe2x80x9c1xe2x80x9d and the nodes N11 are set to xe2x80x9c0xe2x80x9d.
Accordingly, it is possible to execute the R mat write verify by deciding the state of the nodes N11 of all the latches L33 in the sense latch group 33 through the ALL deciding circuit (L side sense latch decision).
As shown in FIG. 102, similarly, when the erase verify for the R mat 32 is to be carried out, LorR=xe2x80x9c1xe2x80x9d and 0or1=xe2x80x9c0xe2x80x9d are set. If xe2x80x9c0xe2x80x9d is normally written to the R mat 32, the nodes N12 of all the latches 33 in the sense latch group 33 are set to xe2x80x9c0xe2x80x9d and the nodes N11 are set to xe2x80x9c1xe2x80x9d.
Accordingly, it is possible to execute the R mat erase verify by deciding the state of the nodes N12 of all the latches L33 in the sense latch group 33 through the ALL deciding circuit (R side sense latch decision).
The ALL deciding circuit carries out the R or L side sense latch decision based on a logical expression of {(LorR) X OR (0or1)}. It is sufficient that the R side sense latch decision is carried out with xe2x80x9c1xe2x80x9d and the L side sense latch decision is carried out with xe2x80x9c0xe2x80x9d.
Based on the result of the decision of the ALL deciding circuit for deciding whether all the memory cells in the sector are xe2x80x9c0xe2x80x9d, thus, it is possible to execute the write verify and erase verify operations without outputting read data for each bit from data input/output pins.
In this case, a time of approximately 150 xcexcs (50 xcexcs+50 nsxc2x72 Kbyte) required for normal reading per sector can be shortened to 50 xcexcs+xcex1 (xcex1 less than 1 xcexcs). Therefore, the read test time can be shortened to approximately one-third.
In this case, however, it is premised that all the write data in the sectors are identical. For this reason, there has been a problem in that the write data cannot be used for test reading through the checker board pattern CHK2, CHK4, CHK8 or the like which has a high defect detecting capability.
A first aspect of the present invention is directed to a semiconductor memory comprising a plurality of memory cells, each of which can store N-valued (Nxe2x89xa72) information, a data reading device for reading a predetermined number of read data from a predetermined number of memory cells out of said plurality of memory cells during a reading operation for a test, and a deciding device for classifying the predetermined number of read data into K (Kxe2x89xa72) groups and outputting a decision result based on whether all the read data in the respective K groups are identical during the reading operation for a test.
A second aspect of the present invention is directed to the semiconductor memory according to the first aspect of the present invention, wherein the K includes N, the memory cells include memory cells arranged in a matrix defined by first and second directions, the predetermined number of memory cells include memory cells provided in the same position in the second direction and provided in series in the first direction, and the deciding device classifies the predetermined number of read data such that the predetermined number of memory cells are classified into the same groups at N intervals in the second direction.
A third aspect of the present invention is directed to the semiconductor memory according to the second aspect of the present invention, wherein the N-value includes a 2m-value (mxe2x89xa71).
A fourth aspect of the present invention is directed to the semiconductor memory according to any of the first to third aspects of the present invention, the deciding device includes a sense storing device for sensing and storing the predetermined number of read data, and a decision result output device for deciding whether all the read data in the respective K groups are identical based on stored contents of the sense storing device and for outputting a result of the decision.
A fifth aspect of the present invention is directed to the semiconductor memory according to any of the first to fourth aspects of the present invention, wherein the N-value includes a multiple-value to be ternary or more, the reading operation for a test includes first to Lth (Lxe2x89xa72) partial reading operations for a test which have different reading conditions and the read data include first to Lth 1-bit read data, the data reading device reads the predetermined number of first to Lth 1-bit read data during execution of the first to Lth partial reading operations for a test, the result of decision includes first to Lth partial decision results, and the deciding device outputs an ith (i=1 to L) partial decision result based on whether all ith 1-bit read data in the respective K groups are identical during an ith partial reading operation for a test.
A sixth aspect of the present invention is directed to a semiconductor memory comprising a plurality of memory cells, each of which can store N-valued (Nxe2x89xa72) information, a data reading device for reading a predetermined number of read data from a predetermined number of memory cells out of said plurality of memory cells during a reading operation for a test, an expectation storing device for storing a predetermined number of expectation data, and a deciding device for outputting a result of decision based on a result of comparison of the predetermined number of read data with the predetermined number of expectation data during the reading operation for a test.
A seventh aspect of the present invention is directed to the semiconductor memory according to the sixth aspect of the present invention, the deciding device includes a sense storing device for sensing and storing the predetermined number of read data, and a decision result output device for outputting the result of decision based on a result of comparison of stored contents of the sense storing device with stored contents of the expectation storing device.
An eighth aspect of the present invention is directed to the semiconductor memory according to the seventh aspect of the present invention, wherein the N-value includes a multiple-value to be ternary or more, the reading operation for a test includes first to Lth (Lxe2x89xa72) partial reading operations for a test which have different reading conditions, the read data include first to Lth 1-bit read data and the expectation data include first to Lth 1-bit expectation data, the data reading device reads the predetermined number of first to Lth 1-bit read data every execution of the first to Lth partial reading operations for a test respectively, the result of decision includes first to Lth partial decision results, the deciding device outputs an ith (i=1 to L) partial decision result based on a result of comparison of the predetermined number of ith 1-bit read data with the predetermined number of ith 1-bit expectation data during the ith partial reading operation for a test, and the predetermined number of second to Lth 1-bit expectation data are obtained by changing the predetermined number of first to (Lxe2x88x921)th 1-bit expectation data based on the stored contents of the expectation storing device and the sense storing device, respectively.
A ninth aspect of the present invention is directed to the semiconductor memory according to any of the sixth to eighth aspects of the present invention, wherein the expectation storing device includes a data storing device for temporarily storing data when transmitting and receiving data between the memory cells and an outside.
As described above, according to the first aspect of the present invention, a comparatively complicated test pattern having the same value set to the K groups is written to the memory cells and the reading operation for a test is then executed to obtain the result of decision. Consequently, the read test for the memory cells can be carried out at a high speed.
Moreover, it is sufficient that the deciding device has the function of deciding whether all the read data in the respective K groups are identical. Therefore, the circuit area of the semiconductor memory is rarely increased due to the provision of the deciding device therein.
According to the second aspect of the present invention, a predetermined number of memory cells are classified into the same group at the N intervals in the second direction. Therefore, it is possible to carry out the read test in which the checker board pattern having the N-value is set to be a test pattern.
According to the third aspect of the present invention, it is possible to carry out a read test in which a checker board pattern having a repetitive cycle of m bits is set to be the test pattern.
According to the fourth aspect of the present invention, a predetermined number of read data are sensed and stored in the sense storing device. Consequently, it is possible to obtain a result of decision with high precision.
According to the fifth aspect of the present invention, the result of decision comprising the first to Lth partial decision results is obtained. Consequently, it is possible to carry out the read test in a multiple-valued storage state for the memory cell without hindrance.
According to the sixth aspect of the present invention, a predetermined number of expectation data are stored from the outside into the expectation storing device. Consequently, it is possible to carry out a read test based on an optional test pattern. Moreover, in the case in which the predetermined number of expectation data are utilized in common between the predetermined number of data read plural times, it is preferable that the predetermined number of expectation data should be stored in the expectation storing device at a first time. Therefore, a time required for storing the predetermined number of expectation data in the expectation storing device can be omitted during the reading operation of the predetermined number of read data at and after a second time. Correspondingly, the read test can be carried out at a high speed.
Moreover, it is preferable that the deciding device should have the function of outputting the result of decision based on the result of comparison of the predetermined number of read data with the predetermined number of expectation data. Therefore, the circuit area of the semiconductor memory is rarely increased due to the deciding device constituted therein.
According to the seventh aspect of the present invention, the predetermined number of read data are sensed and stored in the sense storing device. Consequently, it is possible to obtain a result of decision with high precision.
According to the eighth aspect of the present invention, the result of decision comprising the first to Lth partial decision results is obtained. Consequently, it is possible to carry out the read test in a multiple-valued storage state for the memory cell without hindrance. In this case, the predetermined number of second to Lth 1-bit expectation data are obtained by changing the predetermined number of first to (Lxe2x88x921)th 1-bit expectation data based on the contents stored in the expectation storing device and the sense storing device, respectively. Therefore, it is sufficient that only the predetermined number of first 1-bit expectation data should be stored in the expectation storing device.
According to the ninth aspect of the present invention, the expectation storing device does not need to be added specially for expectation data storage.
An object of the present invention is to provide a semiconductor memory capable of executing a read test at a high speed based on a comparatively complicated test pattern without increasing a circuit area. These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.