1. Field of the Invention
This invention relates to integrated circuit functional testing and, more particularly, to system level functional testing of microprocessors.
2. Description of the Related Art
Semiconductor integrated circuit (IC) devices are manufactured using many complex processing steps. In many cases, more complex ICs may require more processing steps. During any of which one or more defects may be introduced into the IC. For example, microscopic airborne particulates that find their way onto the device during manufacture may cause either latent or hard defects. Many ICs are typically manufactured on one wafer (i.e., semiconductor substrate). To reduce manufacturing defects and improve product quality and yield many manufacturers have implemented ongoing quality control in the wafer fabrication and device assembly facilities.
However, there are still a fair number of IC s that are either defective from the start or may have latent defects. Thus, device manufacturers typically test the ICs using various test strategies during the various manufacturing phases. For example, to screen out bad ICs prior to assembling the ICs into device packages, ICs may be tested while still part of the wafer. This type of testing is sometimes referred to as wafer-level test or wafer probe. In addition, since defects may be introduced during the assembly process, each IC may be tested again, after assembly, during what is sometimes referred to as production or final testing.
Production testing may take many forms depending on the various factors including customer requirements. The goal is to screen out all devices that have defects. In some cases, the ICs may be operated under various operational and environmental stresses to allow latent defects to manifest.
The type of testing performed during wafer-level and production final test typically includes the use of testing machines designed to provide necessary voltages and stimuli to the inputs of an IC. During a type of testing referred to as Functional testing, the voltages and stimuli attempts to place the device in as many operational modes as possible thereby simulating device operation. While the device is operating, the IC outputs are monitored and compared against a theoretically known good output signature that is typically stored in a test file in the tester memory. Functional testing uses a large number of test files (also referred to as test patterns) that define the stimulus and response patterns. Functional testing may generally be expected to screen a large number of defects in many fault classes.
An alternative and sometimes complementary test method used to screen defects is referred to as scan testing. Scan testing also uses test patterns. However, unlike functional testing, scan testing doesn't attempt to operate the device in all of its operational modes. Instead scan testing relies on test logic and testability features that have been designed into the IC that enable scan chains consisting of many clocked circuit elements such as flip-flops and some latches, for example, to be loaded with special test patterns. The scan chains may loaded in one mode (e.g., scan) and clocked in another mode (e.g., run). The test patterns are propagated through the IC logic. The scan patterns are clocked out of the device and compared to response patterns stored within tester memory. For certain fault classes such as stuck at faults, for example, scan testing has been known to obtain fault coverages as high as 99% and in some cases 100%.
However, regardless of the test methods used, as IC operating speeds have increased, it has been increasingly difficult to develop testing machines that can adequately operate at the required speeds. This is especially true for microprocessor testing. Testing machines that can operate at the required frequencies are very expensive. Furthermore, neither functional testing nor scan testing may screen all defects in any fault class without using enormous test patterns requiring long test durations. To obtain very high fault coverage for all fault classes, combinations of test methods may be used. For example, due to the parallel nature of superscalar microprocessor core logic, certain types of failures, such as certain speed paths, may not necessarily manifest when an IC is run through a conventional production test flow.