This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-294966, filed on Sep. 27, 2000; the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a structure of a MIS type integrated circuit on an SOI substrate and a manufacturing method thereof.
It has become an important target over the recent years to decrease a consumption of the electric power of an LSI, and a MIS type transistor using an SOI (Silicon On Insulator) substrate has been increasingly developed as one of effective solving methods.
FIGS. 11A through 11G are sectional views showing manufacturing steps of a method of manufacturing the conventional MIS type transistor provided on the SOI substrate.
To start with, as shown in FIG. 11A, an SOI substrate is composed of a silicon substrate 1, an embedded oxide layer 2 and a mono-crystalline layer. On this SOI substrate, a device isolation is carried out by a STI (Shallow Trench Isolation) device isolation method based on a normally used shallow trench, and the isolation is done with a isolation region 5 embedded with an oxide layer, thereby providing a device region 3 of which the surface is covered with a thermal oxide layer 4.
Next, as shown in FIG. 11B, an NMOS channel region 6 is provided by implanting ions of a p-type impurities into the device region 3, and a PMOS channel region 7 is provided by implanting ions of an n-type impurities into the device region 3 by making use of resist patterning based on photolithography.
Subsequently, as shown in FIG. 11C, after removing the oxide layer 4 on the device regions 6, 7, a gate insulation layer 8 is provided by performing again the thermal oxidation. Thereafter, undoped polysilicon is deposited over the entire surface by use of an LPCVD method, and gate electrodes 9, 10 are provided on an NMOS channel region 6 and a PMOS channel region 7 by using the resist patterning and reactive ion etching (RIE).
Next, as shown in FIG. 11D, a low concentration diffused layer 11 is provided in the NMOS region by implanting the ions of n-type impurities, and a low concentration diffused layer 12 is provided in the PMOS region by implanting the ions of p-type impurities by using the resist patterning(not shown) and the gate electrodes 9, 10 as ion implantation masks.
Next, as shown in FIG. 11E, a nitride layer is deposited by using the LPCVD method, and thereafter a side wall 13 is provided on side surfaces of the gate electrodes 9, 10 by effecting the RIE. Further, a high concentration diffused layer 14 is provided in the NMOS region by implanting the ions of the n-type impurities, and a high concentration diffused layer 15 is provided in the PMOS region by implanting the ions of the p-type impurities by making the use of the resist patterning (not shwon). The ion implantation for providing these high concentration diffused layers 14, 15 also functions to add the impurities to the gate electrodes 9, 10 at the same time. That is, the gate electrode 9 becomes an n-type gate electrode, and the gate electrode 10 becomes a p-type gate electrode. Thereafter, a refractory metal such as Co, Ti, Ni is deposited on an entire wafer surface, and the thermal process is executed thereon, thereby providing a metal silicide 16 selectively on only the region where the silicon of the MIS type transistor is exposed.
Subsequently, as shown in FIG. 11F, after an oxide layer 17 serving as an inter-layer insulating layer has been deposited, a contact hole 18 to the NMOS, a contact hole 19 to PMOS and a contact hole 20 to the a silicon substrate 1 are respectively formed by the resist patterning based on the photolithography and by the RIE. The contact hole is formed deeper by thickness of the embedded oxide layer 2 and thickness of the isolation region 5 than the contact holes 18, 19.
Further, a high concentration impurity layer 21 having the same conductivity as that of the silicon substrate 1 is provided at the bottom of the contact hole 20 by effecting the resist patterning and the ion implantation, and thereafter the thermal process executed thereon, thereby activating the impurity layer 21. Note that this contact hole 20 is used for stabilizing an electric potential of the silicon substrate 1, and the high concentration impurity layer 21 is provided to ensure an ohmic contact between a interconnection metal formed subsequently and the silicon substrate 1.
Thereafter, a metal 22 of Ti/TiN etc is deposited thin within the contact holes 18, 19, 20, and a metal 23 such as tungsten (W) etc is grown with the metal 22 used as a base, and polishing is executed, whereby the metals 22, 23 are left only within the contact holes. Further, after the metal interconnections of Al etc has been deposited on the entire wafer surface, a predetermined metal interconnection 24 is formed by effecting the resist patterning and the RIE.
Thus, according to the conventional semiconductor device, the MIS type transistor is provided and the inter-layer insulation layer is deposited. Thereafter, when forming the contact hole with respect to each of the electrodes to the transistor, the contact holes are so opened as to penetrate the inter-layer insulation layer, the device isolation oxide layer and the embedded oxide layer at the same time, and the metal interconnection is provided as in the case of other contacts, thereby making an electric connection to the silicon substrate. Accordingly, in the semiconductor device manufactured by using the present method, the circuit using the MIS type transistor can be provided on the SOI substrate, which largely contributes to decrease the consumption of the electric power of the LSI.
There arise, however, the following problems inherent in the conventional semiconductor device and the manufacturing method thereof described above.
First, it is desirable that the metal interconnection for stabilizing the electric potential of the silicon substrate be, when forming this metal interconnection, taken from the underside of the substrate, however, there is no alternative but to often take it out from the surface of the substrate as the case may be. In this case, as shown in FIG. 11F, the contact hole 20 to the silicon substrate is formed deeper by the thickness of the device isolation oxide layer plus the embedded oxide layer than other contact holes 18, 19, and hence an aspect ratio increases, with the result that it is difficult to form a minute hole corresponding to a design rule.
Second, even when forming the contact hole, it is quite difficult to grow a base metal thin layer for growing tungsten uniformly up to side and bottom portions of the hole having a high aspect ratio as in the case of the contact hole 20.
Third, it is required for ensuring the ohmic contact with respect to the silicon substrate that the high concentration impurity layer 21 be provided at the bottom of the contact hole 20. If the impurity layer formed by executing the ion implantation is activated at a temperature as high as, e.g., 950xc2x0 CRTA after the contact hole 20 has been formed, however, the metal silicide already provided on the MIS type transistor is weak to the heat and decline in its characteristic. This results in a problem that a junction leak is brought about, and a resistance rate rises.
As described above, in the semiconductor device manufactured by using the conventional technology, it is difficult to stably form the contact hole to the silicon substrate constituting the SOI substrate.
A semiconductor device according to an embodiment of the present invention comprises an SOI substrate formed with a mono-crystalline semiconductor layer through an embedded insulating layer on a first conductivity type semiconductor substrate; a MIS type field-effect transistor provided within a device region defined by isolating said mono-crystalline semiconductor layer with a device isolation region and having a gate electrode; an opening formed penetrating said device isolation region and said embedded insulating layer and reaching said semiconductor substrate; and a substrate electrode provided covering said opening and taken out up to the surface flush with said gate electrode.
A semiconductor device according to another embodiment of the present invention comprises: an SOI substrate configured by providing a mono-crystalline semiconductor layer through an embedded insulation layer on a first conductivity type semiconductor substrate of which the surface is provided with a first impurity diffused layer of the first conductivity type and a second impurity diffused layer of the second conductivity type; a MIS field-effect transistor provided within a device region defined by isolating said mono-crystalline semiconductor layer with a device isolation region, and having a gate electrode;
first and second openings penetrating said device isolation region and said embedded insulation layer and reaching said first impurity diffused layer of said semiconductor substrate; third and fourth openings penetrating said device isolation region and said embedded insulation layer and reaching said second impurity diffused layer of said semiconductor substrate; first and fourth polysilicon substrate electrodes of the first conductivity type, taking such a configuration as to fill and cover said first and fourth openings, and taken out up to the surface flush with said gate electrode; and second and third polysilicon substrate electrodes of the second conductivity type, taking such a configuration as to fill and cover said second and third openings, and taken out up to the surface flush with said gate electrode, wherein first and second diodes for an electrostatic protection are composed respectively of a group of said first polysilicon electrode, said first impurity diffused layer and said second polysilicon electrode, and a group of said third polysilicon electrode, said second impurity diffused layer and said fourth polysilicon electrode.
A method for manufacturing semiconductor device according to an embodiment of the present invention comprises: providing a device isolation region for defining a device region on a mono-crystalline semiconductor layer of an SOI substrate formed with a mono-crystalline semiconductor layer through an embedded insulation payer on a semiconductor substrate of a first conductivity type; forming an opening penetrating said device isolation region and said embedded insulation layer and reaching said semiconductor substrate; depositing polysilicon on said SOI substrate and within said opening and providing a gate electrode and a substrate electrode of said MIS type field-effect transistor by executing the patterning thereon; and implanting impurities into said gate electrode and said substrate electrode.
A method for manufacturing semiconductor device according to another embodiment of the present invention comprises: providing a device isolation region for defining a device region on a mono-crystalline semiconductor layer of an SOI substrate formed with a mono-crystalline semiconductor layer through an embedded insulation payer on a semiconductor substrate of a first conductivity type; providing a first polysilicon layer on the entire surface; forming an opening penetrating said first polysilicon layer, said device isolation region and said embedded insulation layer and reaching said semiconductor substrate;
providing a second polysilicon layer on the entire surface to cover said opening; providing a substrate electrode by patterning said first and second polysilicon layers; and
implanting an impurity into said substrate electrode.