Determining the electrical integrity of complex and high density conductive patterns formed on both the exterior and inner layers of ceramic substrates, printed circuit boards and other like items before populating the substrates and boards with components, has become of increased concern to the electronics industry due to rapidly changing technology and economic considerations. Foremost, PC boards in ever shrinking dimensions, are being designed with increasingly dense patterns to accept surface mounting techniques (SMT) of components. These are in the form of extremely reliable, but expensive, chips, DIP's and EPROM's which reduce the need for after assembly "in-circuit" and "functional circuit" testing, provided the unpopulated boards and substrates are free of defects and leakage paths.
Printed circuit board and substrate designs are changed frequently and the lot size of production runs of these items have decreased, but the variety and varying shapes have increased. In board manufacture, the trend is away from the use of expensive metals which have superior bonding characteristics, such as gold and silver, to the use of less reliable metals such as copper, which has a propensity to cause cracks or "open" conditions. Lastly, the decision "not to test" unpopulated printed circuit boards and substrates can lead to costly scrappage losses after almost error-free component loading under conditions where board continuity failures occur or already existed prior to the mounting of the components.
In the past, test equipment to verify circuit integrity and resistivity of PCBs and substrates used either fixtures of multiple probe (bed-of-nails), spring loaded probe cards, or two programmable probes (flying probes). Another known technique is the use of a single probe or capacitance measurement which requires a second connection to the ground plane. All of these known methods have shortcomings. Multiple probe fixtures and cards are fragile, expensive to build, and cause delays since they have to be specially designed for each PCB or substrate design. Dual probe and capacitance testers exhibit relatively slow test cycles in testing dense patterns on substrates and PC boards. Further, probes can make dents or marks on the metallic conductor pads or points to which they are applied, which can cause component bonding failures and may preclude use of surface mounting techniques. Pressure may cause micro cracks to close. Also, high density printed circuit boards of less than 20 mil pad sizes and spacing often preclude the use of "bed-of-nails" and probe devices due to high cost factors and physical size constraints. Even a more critical limitation to the use of these known test methods is the possibility of failure to detect micro or hair line cracks in both inner and exposed upper of lower layers. An isolation or "open" condition (which occurs where hair line cracks exist) may go undetected by these known systems since they apply an electric potential through the conductors under test. A hair line crack of the order of 1 micron (0.0001 inch) can be bridged by a test voltage as low as 6-10 volts.
To overcome many of these problems, an electro-luminescent gas glow discharge continuity testing system was introduced in the early 1980's by Testamatic Corporation for testing the electrical integrity of unpopulated multi-layer ceramic substrates and printed circuit boards. This electro-luminescent gas discharge continuity testing system is described more fully in U.S. Pat. No. 4,507,605 issued March 26, 1985 for a "Method and Apparatus for Electrical and Optical Inspection and Testing of Unpopulated Printed Circuit Boards and Other Like Items", assigned to Testamatic, Inc. (the assignee of the present invention), the disclosure of which hereby is incorporated in it's entirety into the disclosure of this application.