1. Field of the Invention
The present invention relates to dynamic random access memory (DRAM) semiconductor devices and systems, and more particularly to methods and apparatus for transitioning to a self-refresh mode in a device that performs per-bank auto-refresh operations.
2. Description of the Related Art
DRAM devices are well known and commonly found in digital systems having a need for read/write digital memory. DRAM devices are so-named because the data in each memory cell must be refreshed periodically by reading the data, or else the stored data will be corrupted. Modern synchronous DRAM devices (SDRAMs) typically employ an “auto-refresh” mode, which refreshes one row of the DRAM memory cell array each time an auto-refresh operation is initiated by an external memory controller. An internal refresh row counter increments through the rows for successive auto-refresh operations, and wraps back to the top of the array upon reaching the bottom. The DRAM memory controller thus has some flexibility as to when it issues the auto-refresh commands to a DRAM device, as long as all rows are refreshed within the maximum time specified for the array to maintain stable data.
Many SDRAM devices contain multiple banks of memory, with the high-order row address bits supplied to the SDRAM along with an operation determining which bank is to receive the operation. Some of these devices allow a bank address to be supplied with an auto-refresh command, and then an auto-refresh operation is performed in the bank specified by the bank address with regard to the current refresh row while a data access operation may be performed in the unselected banks at the same time. Such devices will be referred to herein as Per-Bank Refresh (PBR) SDRAM devices. The inventor of the present application has filed a copending application, U.S. Pat. application Ser. No. 11/105,169, disclosing novel PBR SDRAM architectures and methods of operation, the disclosure of which is incorporated herein by reference.
Many SDRAM devices also incorporate a “self-refresh” mode. In self-refresh mode, the SDRAM device generally enters a lower-power state during which it does not respond to bus commands until awakened. In self-refresh mode, the SDRAM device is expected to perform its own refresh operations, based on internal timing, sufficient to retain data saved in the memory device.