1. Field of the Invention
The present invention relates to a matrix type display apparatus such as a liquid crystal display (hereinafter referred to as an LCD), and particularly to a technique for the enlarged display of a screen.
2. Description of the Related Art
FIG. 2 is a structural diagram of a conventional LCD.
This LCD displays image signals supplied from a personal computer or the like (referred to below as a PC) on a color screen having a size of 1024 pixels horizontally by 768 pixels vertically. This LCD comprises a control circuit 10, a display signal circuit 20, a scan signal circuit 30, and a liquid crystal panel 40.
Red, green, and blue color image signals formed from R, G, and B signals, clock signals CLK showing timings of a sampling of these R, G, and B signals, horizontal synchronizing signals HSYN, and vertical synchronizing signals VSYN are fed to the input side of the control circuit 10 from an unillustrated PC. On the basis of these signals, the control circuit 10 then generates start signals EI, clock signals CK, R, G, B data, and strobe signals STB and outputs these to the display signal circuit 20. The control circuit 10 also has the function of generating start signals ST and clock signals CP and outputting these to the scan signal circuit 30.
The display signal circuit 20 is provided with a 1024 stage shift register 21 which corresponds to the 1024 pixels in the horizontal direction, data latches 22 and 23, and a display drive section 24. The shift register 21 sequentially shifts and holds the start signals EI based on the clock signals CK and the held contents of each stage are fed to each stage of the data latch 22 as latch signals L1, L2, etc up to L1024. The data latch 22 holds the R, G, B data fed from the control circuit 10 based on the latch signals L1 to L1024.
The data latch 23 stores the R, G, B data of the 1024 horizontal pixels held by the data latch 22 at the strobe signal STB timing. The display drive section 24 generates display voltages S1, S2 etc up to S3072 which correspond to R, G, B data of the 1024 pixels stored in the data latch 23 and outputs these display voltages.
The scan signal circuit 30 is provided with a 768 stage shift register 31 and scan drive section 32 for sequentially scanning and displaying the 768 pixels in the vertical direction in horizontal line units. The shift register 31 holds the start signals ST in the initial stage register as scan signals and then sequentially shifts these scan signals in accordance with the timing of the clock signals CP. The contents at each stage of the shift register 31 are fed to the scan drive section 32 and are output as scan voltages G1, G2, etc up to G768.
The liquid crystal panel 40 is provided with 768 X electrodes X1, X2, etc up to X768 arranged at equal spacing in a line direction, and 1024 groups (note that each group is made up of 3 electrodes corresponding to R, G, and B) of Y electrodes Y1, Y2, etc up to Y3072 arranged at equal spacing in a column direction. Color pixel display is performed in line units in accordance with display voltages S1 to S3072 applied respectively to the Y electrodes Y1 to Y3072 at locations where an X electrode Xj to which a scan voltage Gj (wherein j is a number from 1 to 768) is applied intersects with a Y electrode Y1 to Y3072.
In this type of LCD, when R, G, B signals, clock signals CLK, horizontal synchronizing signals HSYN, and vertical synchronizing signals VSYN are supplied from a PC, horizontal cycle start signals EI and, thereafter, in synchronization with the clock signals CLK, R, G, B data is sequentially transmitted in single pixel units from the control circuit 10 to the display signal circuit 20. In the shift register 21, latch signals L1 to L1024 are generated in accordance with the clock signals CK. R, G, B data is further sequentially held in the data latch 22 in synchronization with the latch signals L1 to L1024.
When the R, G, B data of the 1024 pixels of a single line is held in the data latch 22, a strobe signal STB is output from the control circuit 10. Accordingly, the R, G, B data of the single line in the data latch 22 is also stored in the data latch 23. In the display drive section 24, display voltages S1 to S3072 are generated based on the R, G, B data of the 1024 pixels stored in the data latch 23 and are output.
Moreover, start signals ST for each vertical cycle and clock signals CP for shifting the start signals ST and generating scan signals are output from the control circuit 10 to the scan signal circuit 30. When the start signals ST are supplied, the output signal of the initial stage of the shift register 31 of the scan signal circuit 30 is set to a level xe2x80x9cHxe2x80x9d for designating display and output signals of subsequent stages are set to a level xe2x80x9cLxe2x80x9d for designating non-display. Output signals of each stage of the shift register 31 are then sequentially shifted one stage at a time towards the rear in synchronization with the clock signals CP which correspond to the horizontal cycle. The output signals of each stage of the shift register 31 are fed to the scan drive section 32 and scan voltages G1 to G768 are generated for each line in accordance with the display/non-display and output.
The display voltages S1 to S3072 which correspond to the R, G, B data of a single line output from the display drive section 24 are fed to the Y electrodes Y1 to Y3072 of the liquid crystal panel 40. Moreover, the scan voltages G1 to G768 output from the scan drive section 32 are fed to the X electrodes X1 to X768 of the liquid crystal panel 40. The timing of the strobe signals STB fed from the control circuit 10 to the display signal circuit 20 is substantially identical to the timing of the clock signals CP fed to the scan signal circuit 30. Therefore, a single line which corresponds to the X electrode Xj driven by the scan voltage Gj output from the scan drive section 32 is displayed through the display voltages S1 to S3072 based on the R, G, B data for the single line stored in the data latch 23. In addition, all other X electrodes other than the X electrode Xj are placed in a non-display state.
A screen is displayed by the X electrodes X1 to X768 being sequentially driven from top to bottom by the scan voltages G1 to G768 sequentially output from the scan drive section 32.
However, this type of conventional LCD has the following problems.
For example, when an image signal supplied from a PC is for displaying on a 640 horizontal pixel by 480 vertical pixel screen, no pixel data exists for displaying at the right hand side and bottom of a liquid crystal panel 40 having 1024 horizontal pixels by 768 vertical pixels. Therefore, the problem has existed that the displayed screen is small and the display position is offset to the top left.
In order to solve this problem, attempts have been made to provide a processing device and frame memory corresponding to the resolution of the liquid crystal panel 40 in the LCD. Image signals fed from the PC are interpolated by this processing device and converted into image data for a 1024 horizontal pixel by 768 vertical pixel screen and displayed.
However, in this type of method, because a large amount of frame memory and a high speed processing device are necessary, the problem arises that costs are increased and the amount of power needed to run the processing device at high speed also increases.
The present invention solves the above problems in the conventional technology and provides a matrix type display apparatus such as an LCD which has a simple circuit structure and which is capable of enlarging the display of a screen.
In order to solve the above problems, the first aspect of the present invention is a matrix type display apparatus comprising: display means having M number of X electrodes (wherein M is a number greater than one) arranged in parallel, N number of Y electrodes (wherein N is a number greater than one) arranged so as to intersect the X electrodes, and display elements provided at each point of intersection of the X electrodes and Y electrodes, the display means performing a matrix type display at the points of intersection of the N number of Y electrodes and the X electrodes which are driven by scan voltage in accordance with a display voltage applied to each Y electrode; scan drive means for generating the scan voltage in order to sequentially drive the X electrodes; and display drive means for holding image data which corresponds to the X electrodes driven by the scan drive means, and for generating the display voltage based on the held image data and driving each of the Y electrodes, wherein the scan drive means and the display drive means have the following structure.
Namely, the scan drive means is provided with M number of flip-flop circuits (referred to below as xe2x80x9cFF circuitsxe2x80x9d) and switches for altering the connections of the M number of FF circuits and, in normal display mode, the scan drive means forms shift registers having M number of stages by connecting the M number of FF circuits in series and also generates the scan voltages based on each output signal of the M number of FF circuits and, in enlarged display mode, the scan drive means forms shift registers having m number of stages (wherein m is a number less than M) by connecting a portion of the M number of FF circuits in parallel at a constant ratio and also generates the scan voltages based on each output signal of the M number of FF circuits.
Moreover, the display drive means is provided with N number of FF circuits and switches for altering the connections of the N number of FF circuits and, in the normal display mode, the display drive means forms shift registers having N number of stages by connecting the N number of FF circuits in series and also holds the image data based on each output signal of the N number of FF circuits and generates the display voltages in accordance with the image data and, in the enlarged display mode, the display drive means forms shift registers having n number of stages (wherein n is a number less than N) by connecting a portion of the N number of FF circuits in parallel at the constant ratio and also holds the image data based on each output signal of the N number of FF circuits and generates the display voltages in accordance with the image data.
The second aspect of the present invention is the matrix type display apparatus according to the first aspect, wherein switches in the scan drive means and the display drive means are formed from analog switches (referred to below as xe2x80x9cSWxe2x80x9d) controlled by mode signals which designate the normal display mode or the enlarged display mode.
According to the first and second aspects of the present invention, because the above described structure is employed, the following operation can be performed.
In normal display mode, the M number of FF circuits in the scan drive means are connected in series by switches such as SW or the like. Scan voltages are sequentially generated from each FF circuits and fed to the X electrodes of the display means. The N number of FF circuits in the display drive means are also connected in series by switches. Image data based on output signals sequentially output from each FF circuit is held, and display voltages are generated in accordance with the image data and fed to the Y electrodes of the display means.
In contrast, in enlarged display mode, the M number of FF circuits in the scan drive means are connected in parallel and in series at a constant ratio by switches. Scan voltages are generated based on output signals from each FF circuit and fed to the X electrodes of the display means. The N number of FF circuits in the display drive means are also connected in parallel and in series at a constant ratio by switches. Image data based on output signals from each FF circuit is held, and display voltages are generated in accordance with the image data and fed to the Y electrodes of the display means.
The third aspect of the present invention is the matrix type display apparatus according to the first and second aspects, wherein the scan drive means is provided with a plurality of integrated circuits used for shifting which are connected in a cascade connection and, in the enlarged display mode, the scan drive means simultaneously drives outputs of scan voltages for front or rear non-display regions based on selection signals which correspond to the integrated circuit connection position.
The fourth aspect of the present invention is the matrix type display apparatus according to the third aspect, wherein selection signals for a plurality of integrated circuits in the scan drive means are directly fed from ground voltage or power supply voltage supplying the integrated circuits.
According to the third and fourth aspects of the present invention, the following operation is performed in the scan drive means in the matrix type display apparatus according to the first and second aspects of the present invention.
Selection signals corresponding to the connection positions at which a plurality of integrated circuits used for shifting are connected in a cascade connection in the scan drive means are directly fed, for example, from a power supply and ground voltage identical to the integrated circuits. In enlarged display mode, the output of scan voltages for front and rear non-display regions is stopped based on the selection signals.