Multi-layered heteostructures are employed to implement devices for a number of applications. These applications include, but are not limited to, optoelectronic components (e.g. PIN junction or multi-quantum well). The functionality of these multi-layered heteostructures are typically built from layer to layer in a vertical direction, using different semiconductor materials. Further, the multi-layered heteostructures are vertically etched leading to the exposure of their sidewalls, and polymer is spun to seal the sidewalls. To facilitate provision of a contact to one of these devices, the polymer may be etched back to expose the top semiconductor layer, to allow a metal contact to be deposited thereon. Alternatively, a vertical via may be etched to open the polymer to facilitate contact between the top semiconductor layer and the metal contact.
However, both practices have disadvantages. In particular, the former practice may not be able to clear the top semiconductor layer without exposing the sidewalls of some of the device layers underneath the top layer. Whereas, the latter practice is difficult and complicated, especially in the smaller than micro scale, e.g. at nanometer scale. As at the nanometer scale, not only alignment of the via mask becomes very difficult, making of the via mask in and of itself becomes almost impossible, due to current sub-micro lithography is unable to accurately resolve nanometer via printing. Also, at nanometer scale, the via approach will not allow the full use of the available area of the top semiconductor layer because a typical via approach requires some margin so the via must be smaller than the device. Even if the first practice is able to open the whole area of the top device layer, at micrometer or nanometer scale, the top semiconductor area may not be sufficiently large to provide a desired low contact resist interconnect (as resist is inversely proportional to the contact area).