1. Technical Field
The present invention relates generally to processor performance measurement systems, and more particularly, to a performance counting system with low latency and error.
2. Description of the Related Art
Performance measurement in processing units is typically performed by a set of counters that accumulate information about the usage of units within the processor. By obtaining such usage information, sophisticated power management algorithms can adjust operating conditions such as processor frequency and voltage, idle time or other energy usage control mechanism to reduce power consumption or dissipation, while ideally providing a minimal impact on processing performance.
Accurate performance evaluating systems have been proposed based on a complex polynomial metric, but require measurement of a large number concurrent events. If the events contributing to the performance measurement are the individual usage of a set of processing units as mentioned above, then a counter is provided for each unit for which usage is being measured. In such implementations, a large number of counters is required to measure performance in present-day processors, which may have multiple pipelines having dozens of processing units, cache units, and other units that contribute to overall processor performance. However, existing performance counting implementations typically require a separate counter for each metric being measured and typically do not process a large number of events concurrently. Therefore, such performance counting implementations cannot provide an accurate estimate of performance change when power management control changes operating parameters of a processor.
One alternative to the above-described scheme of providing a usage counter for each metric, is to time-multiplex a smaller set of counters (or a single counter) to perform the individual measurements. However, the overall latency of such a scheme is too high for energy management systems requiring a fine granularity of control. Further, the inter-metric measurement delays introduce error into the measurements. Even when individual counters are employed, they are not typically accessed simultaneously, which also introduces both inter-metric delay error and latency.
It is therefore desirable to provide a performance counting method and system that provides usage information having low error and latency. It would be further desirable to provide such a system and method that does not require a counter for each metric contributing to the overall performance measurement.