1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method of the semiconductor memory device.
2. Related Art
Data reading from a NAND flash memory is performed in a page unit. One page includes 4 k-bit to 64 k-bit data, for example. Therefore, in read operation, data of 4,000 to 64,000 memory cells are read simultaneously. Because cell current flows simultaneously to the 4,000 to 64,000 memory cells at this time, potentials of cell source lines sometimes increase (or is lifted). When the potentials of the cell source lines increase, cell current decreases. Consequently, a threshold voltage of the memory cells increases, and a distribution of the threshold voltage of the memory cells is spread. To suppress the spreading of the threshold voltage distribution, the cell source lines connecting between source drivers and sources of the memory cells preferably have as low resistance as possible. For this purpose, a top-layer wiring layer of low resistance in a multilayer wiring structure on a memory cell array can be used as cell source lines and cell well lines (see Japanese Patent Application Laid-open No. 2005-142493 and Japanese Patent Application Laid-open No. 2006-245547).
In recent years, to improve performance of memories, the ABL (All Bit Line) sense scheme has come to be used frequently. In the ABL sense scheme, sense amplifiers are provided corresponding to all bit lines and all bit lines are simultaneously read. Therefore, a large amount of current is consumed in the sense amplifiers. To supply power to the sense amplifiers, wide power source lines need to be arranged from a pad to the sense amplifiers. This increases chip size.
To further downscale the chip size, there is considered a layout of forming on the top-layer wiring layer of the memory cell array a VSS (ground potential) power source lines to be connected to the sense amplifiers, as well as the cell source lines and the cell well lines (see Kanda et al. “A 120 mm2 16 Gb 4-MLC NAND Flash Memory with 43 nm CMOS Technology” ISSCC 2008/SESSION 23/NON-VOLATILE MEMORY/23.6 p.p. 430, 431 and 625). To decrease resistance of the wiring formed on the top-layer wiring layer in this way, an installation area of each wiring is preferably increased. To increase each wiring area of the cell source lines, the cell well lines, and power source lines as far as possible, each wiring formed on the top-layer wiring layer can cover a whole upper part of the memory cell array. However, when the wiring covers the whole upper part of the memory cell array, hydrogen is not thoroughly supplied to the memory cells in a forming gas/anneal process performed at a final stage of a memory-chip manufacturing process. This becomes a cause of degradation of a data holding characteristic of the memory cells.