Integrated circuits (ICs) may be designed to include or not include IEEE 1149.1 boundary scan circuitry and interface. The benefits of including 1149.1 in an IC include but are not limited to; (1) boundary scan testing of interconnects between ICs on a substrate, (2) testing of the IC, (3) debugging circuits within the IC and (4) programming circuits within the IC. The drawbacks of including 1149.1 in an IC include; (1) the requirement of a dedicated 4 pin test interface which increases the IC package size and a timing penalty on the ICs inputs and outputs due to the boundary scan cell multiplexers. Most large digital ICs, such as CPUs, DSPs and ASICs, include 1149.1 for boundary scan testing and even more importantly to enable debug, trace and emulation of embedded core circuits within the ICs. However, 1149.1 is not widely used in memory, analog and mixed signal ICs due to the above mentioned increase in package size and decrease in input and output performance. Memories in particular are resistant to using 1149.1 due to JDEC's memory pin out standardization.
FIG. 1 illustrates an example integrated circuit die 102 that includes a functional circuit 104 that has external functional inputs (FIN) 106 and external functional outputs (FOUT) 108. Circuit 104 may have bidirectional signals as well, but for simplicity only inputs and outputs are discussed in this disclosure. The circuit 104 may be a digital, analog or mixed signal circuit that performs the functional operation of the die. Circuit 104 may also be a memory circuit, such as but not limited to a double data rate random access memory. As can be seen the die of FIG. 1 does not include 1149.1 boundary scan circuitry.
FIG. 2 illustrates an example integrated circuit die that includes a functional circuit 104 and 1149.1 circuitry consisting of a test access port (TAP) 204 and associated boundary register (BREG) 206. The TAP has an external interface of TDI, TCK, TMS inputs 212 and a TDO output 214 signals. The TAP responds to the TCK and TMS signals to input data from TDI and output data to TDO. If the boundary register is selected for access it will shift data from TDI to TDO. During normal operation of the die, the boundary register couples the FIN signals 106 to the internal inputs 208 of the circuit and the internal outputs 210 of the circuit to the FOUT signals 108. During boundary scan test mode using the well known 1149.1 Extest instruction, the boundary register isolates the FIN signals 106 from the internal inputs 208 and the internal outputs 210 from the FOUT signals 108. In the boundary scan test mode the boundary register can be operated to capture test data from the FIN signals 106 and update test data to the FOUT signals 108. The boundary scan test mode enables the testing of the FIN and FOUT connections between multiple die/ICs on a substrate.
FIG. 3 illustrates the TAP 204 of die 202 in more detail. The FIN signals 106 and the 1149.1 input signals 212 define the inputs 318 to the die. The FOUT signals 108 and the 1149.1 output signal 214 define the outputs 320 of the die. The 1149.1 TAP includes, at minimum, a TAP state machine (TSM) 304, an instruction register 306, a Bypass Register 308, the Boundary Register 206 and TDO output multiplexers 310 and 312. While not shown, the TAP may also include other data register between TDI and TDO, including an optional Identification Register which contains a 32 bit code identifying the die. During functional operation, the FIN signals 106 and FOUT outputs signals 108 are coupled to the circuit 104 via the boundary register 206 and buses 208 and 210. The TSM 304 operates according to the well known 16 state transition diagram of FIG. 3A in response to the TCK and TMS input signals to; (1) place the TAP is a Test Logic Reset state, (2) place the TAP in a Run Test/Idle state, (3) perform a scan operation to the instruction register from TDI to TDO, (4) to perform a data scan operation to the Bypass Register 308 from TDI to TDO or (4) perform a data scan operation to the Boundary Register 206 from TDI to TDO. The 1149.1 input interface 212 may include an optional TRST input, shown in dotted line, to reset the TSM and other TAP circuits. If the TRST input is not included, a Power Up Reset (POR) circuit 316 may be used to reset the TSM and other TAP circuits.
During instruction scan operations, the TSM outputs control (CTL) signals to the instruction register 306 and multiplexer 312. In response to the CTL signals the instruction register performs capture, shift and update operations. During the shift operation the instruction register shifts data from TDI to TDO via multiplexer 312.
During data scan operations, the TSM outputs CTL signals to the selected data register 308 or 206 and multiplexer 312. The instruction register output (IRO) bus enables the selected data register and controls multiplexer 310 to couple the TDO output of the selected data register to the TDO output of the die via multiplexer 312. In response to the CTL signals the selected data register performs capture, shift and update operations, except for the Bypass Register 308 which does not have update circuitry. During the shift operation the selected data register shifts data from TDI to TDO via multiplexers 310 and 312.
During manufacturing test of die 202, the inputs 318 and outputs 320 are connected to a tester. The tester operates the inputs 318 and outputs 320 to test the circuit 104 within the die 202. The test may include operating only the FIN 106 and FOUT 108 signals, operating the FIN 106, FOUT 108 and 1149.1 input 212 output 214 signals, or operating only the 1149.1 input 212 and output 214 signals. After testing and found to be good, the die is ready for use within in a system.
FIG. 4 illustrates three die 402-406 connected to a system substrate 408 via their inputs 318 and outputs 320. The system of this and following examples could be any type of electronic system such as a computer system or a cell phone system. Each die contains a functional circuit 104 and a TAP 204 as shown in FIGS. 2 and 3. The functional circuits 104 of each die provide a different functional operation on the substrate.
FIG. 5 illustrates the circuits 104 of die 402-406 connected on the system substrate 408. The substrate provides a functional bussing path 502 that connects the FIN 106 and FOUT 108 signals of the die together to enable the die to communicate. The substrate has FIN signals 504 to allow it to input signals from an external device, such as a keyboard, and FOUT signals 506 to allow it to output signals to an external device, such as a display.
FIG. 6 illustrates the TAPs 204 of die 402-406 connected on the system substrate 408. The substrate provides a serial bussing path 602 that connects the TAPs 204 to externally accessible 1149.1 input 212 and 1149.1 output 214 signals. When an 1149.1 controller is connected to the external 1149.1 input and output signals, the TAPs can be serially accessed to perform test or other operations. One of the most important test operations the TAPs perform is the verification that the FIN 106 and FOUT 108 of each die are properly connected together via the substrate bussing path 502. This test operation is performed by loading Extest instructions into each TAP's instruction register then operating the boundary registers of each TAP to test the connectivity between each die's FIN 106 and FOUT 108 signals.
FIG. 7 illustrates a device 700 comprising three stacked die 702-706 mounted on a silicon interposer 708. Each die includes a circuit 104 and a TAP 204 as described in FIGS. 2 and 3. Again, each die circuit 104 will typically provide a different functional operation. Die 702 and 704 in this example are designed using through silicon vias (TSV) 710. TSVs are connectivity paths formed between the top and bottom surfaces of the die. TSVs allow input 318 and output 320 signals to flow vertically up and down the die stack. In addition to TSV input and output signal connections from the interposer, the die 702-704 are also connected together locally using input 712 and output 714 signal connections. Interposers 708 are used to provide electrical connections between one surface and another surface. The primary purpose of an interposer is to spread connections from fine pitch contact points on one surface to wider pitch contact points on another surface. In this example, the fine pitch contact points on the bottom surface of die 702 are spread to match the wider pitch contacts points of a system substrate device 700 will be mounted on. Once the device 700 is mounted on a substrate, it receives input signals 318 from the substrate and sources output signals 320 to the substrate.
Before device 700 is assembled, each die 702-704 and the interposer 708 are tested to insure the device is assembled with known good die and interposer. As mentioned in regard to FIG. 3 the test may performed by a tester operating some are all of the FIN 106 and FOUT 108 signals of buses 318 and 320, operating some are all of the FIN 106, FOUT 108, and the 1149.1 input 212 output 214 signals of buses 318 and 320, or operating only the 1149.1 input 212 and output 214 signals of buses 318 and 320.
FIG. 8 illustrate a first example arrangement of how the TAPs 204 of die 702-706 in device 700 may be accessed by a tester. In this example, interposer signal bussing path 802 provides the TDI and TCK inputs to all TAPs, interposer signal path 804 provides a TMS1 input to the TAP of die 702, interposer signal path 806 provides a TMS2 input to the TAP of die 704, interposer signal path 808 provides a TMS3 input to the TAP of die 706 and interposer signal path 810 provides the TDO outputs from all the TAPs. Having unique TMS1-3 inputs for each TAP allows enabling one TAP while the other TAPs are disabled. When disabled a TAP's TDO output is tri-stated to avoid contention on signal path 1206 with an enabled TAP's TDO output. This is commonly referred to as the 1149.1 Star mode of accessing TAPs. To access the TAP of die 702 for a test or other operation, the tester inputs TMS1, TDI and TCK signals to the TAP via busses 804 and 802, and receives TDO signals from the TAP via bus 810. To access the TAP of die 704 for a test or other operation, the tester inputs TMS2, TDI and TCK signals to the TAP via busses 806 and 802, and receives TDO signals from the TAP via bus 810. To access the TAP of die 706 for a test or other operation, the tester inputs TMS3, TDI and TCK signals to the TAP via busses 808 and 802, and receives TDO signals from the TAP via bus 810.
FIG. 9 illustrates three devices 902-906 connected to a system substrate 908 via their inputs 318 and outputs 320. Each device contains a stack of die 910 with TAPs and an interposer 708 as shown in FIGS. 7 and 8.
FIG. 10 illustrates the substrate providing a functional bussing path 1002 that connects the FIN 106 and FOUT 108 signals of the devices 902-906 together to enable them to communicate. The substrate has FIN signals 1004 to allow it to input signals from an external device, such as a keyboard, and FOUT signals 1006 to allow it to output signals to an external device, such as a display.
FIG. 11 illustrates the substrate providing an externally accessible 1149.1 signal bussing path 1102 to the TAPs of the devices 902-906. Assuming the devices are assembled as shown in FIG. 8, the 1149.1 bussing path 1102 would include 9 unique TMS signals. In this example, TMS signals 1-3 would be used to individually access one of the three TAPs of device 902, TMS signals 4-6 would be used to individually access one of the three TAPs of device 904 and TMS signals 7-9 would be used to individually access one of the three TAPs of device 906.
When an 1149.1 controller is connected to the externally accessible 1149.1 bussing path 1102, a selected TAP in device 902 is enabled by one of the TMS1-3 inputs, a selected TAP in device 904 is enabled by one of the TMS4-6 inputs and a selected TAP in device 906 is enabled by one of the TMS7-9 inputs so that they can be serially accessed from the external 1149.1 input bus 212 and 1149.1 output bus. After accessing this first group of serially connected device TAPs, the 1149.1 controller can select a second group of serially connected device TAPs for access using a different set of TMS signals, and so on. Accessing separate groups of device TAPs can be used for performing an 1149.1 Extest operation to verify that the FIN 106 and FOUT 108 signals of each device are properly connected together via the substrate bussing path 1002.
A first problem with the 1149.1 access approach of FIG. 11 is that the 1149.1 bus 1102 requires a large number of TMS signals that must be routed through the substrate and connected to the multiple TAPs of devices 902-906.
A second problem with the 1149.1 access approach of FIG. 11 is that standard 1149.1 controllers typically only provide a single TMS signal to support 1149.1 access approaches as shown in FIG. 6. 1149.1 access approaches like that shown in FIG. 11 would require modifying standard 1149.1 controllers to include and operate multiple TMS signals.
A third problem with the 1149.1 access approach of FIG. 11 is that Extest operations are encumbered by having to individually select different groups of device TAPs to access their boundary register to test the FIN 106 and FOUT 108 connections to the functional bus 1002 of the substrate 908.
A fourth problem is that Extest operations are lengthened due to having to shift test data through boundary register cells of the local inputs 712 and outputs 714 of each die in the device. For example, when the boundary register of the TAP of die 704 of FIG. 8 is being accessed during an Extest operation to test the die's FIN 106 and FOUT 108 connections to a substrate, the boundary register cells on the die's local inputs 712 and outputs 714 also have to be shifted which adds to the test time. Since the local inputs 712 and outputs 714 of each die were tested after the device was assembled, as mentioned in regard to FIG. 7, they do not need to be tested again when the device is mounted on the substrate. Only the device's FIN 106 and FOUT 108 connections to the substrate need to be tested.
FIG. 12 illustrate a second example arrangement of how the TAPs 204 of die 702-706 in device 700 may be accessed by a tester. In this example, interposer signal bussing path 1202 provides the TCK and TMS inputs to all TAPs, interposer signal path 1204 provides a TDI input to the TAP of die 702, a local signal path 1208 provides the TDO output of the TAP of die 702 to the TDI input of the TAP of die 704, a local signal path 1210 provides the TDO output of the TAP of die 704 to the TDI input of the TAP of die 706 and interposer signal path 1206 provides a TDO output from the TAP of die 706. In this arrangement all the die TAPs of a device are connected in a daisy-chain and can be serially accessed together by the tester.
FIG. 13 illustrates three devices 1302-1306 connected to a system substrate 1308 via their inputs 318 and outputs 320. Each device contains a stack of die 1310 with TAPs and an interposer 708 as shown in FIG. 12.
FIG. 14 illustrates the substrate providing a functional bussing path 1402 that connects the FIN 106 and FOUT 108 signals of the devices 1302-1306 together to enable them to communicate. The substrate has FIN signals 1404 to allow it to input signals from an external device, such as a keyboard, and FOUT signals 1406 to allow it to output signals to an external device, such as a display.
FIG. 15 illustrates the substrate providing an externally accessible 1149.1 signal bussing path 1502 to the TAPs of the devices 1302-1306. Assuming the devices are assembled as shown in FIG. 12, the 1149.1 bussing path 1102 would provide a serial path through all the device TAPs using a single TMS signal. Signal path 1504 in each device is provided to indicate the daisy-chaining of the device TAPs.
When an 1149.1 controller is connected to the externally accessible 1149.1 bussing path 1502, all TAPs in devices 1302-1306 can be serially accessed from the external 1149.1 input 212 to the external 1149.1 output 214.
A first problem with the 1149.1 access approach of FIG. 15 is that the IEEE 1149.1 standard has rules that support only one TAP in a device to be implemented in a system. For example a device should only have one TAP instruction register 306, one TAP bypass register 308, one optional TAP identification register and one TAP boundary register 206. As seen in FIG. 15, the system devices 1302-1306 each have multiple TAP instruction registers 306, multiple TAP bypass registers 308, multiple TAP boundary registers 206 and multiple optional TAP identification registers. Therefore the system devices 1302-1306 of FIG. 15 are considered to be non-compliant with the IEEE 1149.1 standard.
A second problem is that Extest operations are lengthened due to having to shift test data through boundary register cells of the local inputs 712 and outputs 714 of the die within each device. For example, when the boundary registers of the TAPs of the device of FIG. 12 are being accessed during an Extest operation to test the device's FIN 106 and FOUT 108 connections to the substrate of FIG. 15, the boundary register cells on the die's local inputs 712 and outputs 714 also have to be shifted which adds to the test time. Since the local inputs 712 and outputs 714 of each die were tested after the device was assembled, as mentioned in regard to FIG. 7, they do not need to be tested again when the device is mounted on the substrate. Only the device's FIN 106 and FOUT 108 connections to the substrate need to be tested.
The following disclosure provides a solution to the above mentioned problems of FIGS. 11 and 15. The solution is based on the concept of improving conventional interposers to include IEEE 1149.1 TAP circuitry.