1. Field of the Invention
The present invention generally relates to the production techniques of integrated circuits and, more particularly, to a dynamically switched voltage screening method for quality assurance testing of integrated circuit dies on a wafer.
2. Description of Related Art
Integrated circuit (IC) chips or dies fabricated on the same wafer have a wide range of performance in critical parameter characteristics due, in a large part, to process variations. As a result, out-going quality and reliability is compromised by the inconsistent performance of IC chips from the same wafer lot. Typically, stress testing is performed on the wafer during this fabrication process to eliminate the weaker chips from entering the next phase of the production cycle. For example, one of the tests regarded as one of the most severe, is that of subjecting the devices to particularly high temperatures; typically between 85xc2x0 C. and 150xc2x0 C., for accelerating the infant mortality of chips in a wafer. This test, commonly referred to as xe2x80x9cburn-inxe2x80x9d, has the objective of stimulating the failure of those devices which have developed some defects during the fabrication process and/or during handling. However, this test does not segregate parts based solely on performance characteristics. Rather, the stress is uniformly applied to all chips of a semiconductor wafer. Additionally, this test is time consuming, equipment intensive, and costly to perform.
Alternatively, the industry has administered a voltage stress test for implementing a screen with less degrading effects. A voltage screen is basically a higher than normal voltage applied during wafer test: that effectively causes defects to manifest as failures in IC chips during subsequent verification or operational testing. The problem associated with applying a higher than normal voltage level across a semiconductor die is that some dies processed with short channel lengths have a higher tendency to fail when exposed to higher voltages. These short channel length devices would not otherwise be failures except for their vulnerability to high voltage exposure. The failures are not related to defects, rather, to the over stressing of the short channel lengths in the die. Thus, as applied, the voltage screen can be responsible for false failures, an undesirable quality assurance test result. Nevertheless, the industry standard has been to continuously apply a voltage stress at one voltage level to all die on a semiconductor wafer.
As discussed by Lee and Sonoda, in xe2x80x9cTEST SYSTEM FOR NARROWING THE RANGE OF PERFORMANCE CHARACTERISTICS OF MONOLITHIC INTEGRATED CIRCUITSxe2x80x9d, IBM Technical Disclosure Bulletin, Vol. 15, No. 4, September 1972, some circuits, such as those employed with FET technology, have performance characteristics that can differ by as much as 100% due to tolerances in the threshold voltage. Because of these wide differences, there are at one end of the distribution curve chips exhibiting fast response time and high power dissipation, and at the other end of the distribution curve chips having slower circuit response time and lower power dissipation. Thus, sorting the wafer at the IC chip level during quality assurance or reliability testing would be advantageous to identifying the more vulnerable short channel length devices and exposing them to less stress, thus, eliminating false failures during voltage screening.
In the prior art, parts have been screened during wafer testing to classify individual IC chips at various speeds. In U.S. Pat. No. 5,196,787 issued to Ovens et al. on Mar. 23, 1993, entitled, xe2x80x9cTEST CIRCUIT FOR SCREENING PARTSxe2x80x9d, a test circuit was developed on the die to measure the DC characteristics of a device, which in turn, enabled one to estimate the AC characteristics. The AC characteristic estimations were then used to screen parts into various speed classes. However, no suggestion is made to dynamically switch or adjust the stress test levels based on the operational parameters measured.
Another method for determining the operational speed of an IC chip is disclosed in U.S. Pat. No. 5,099,196 issued to Longwell et al. on Mar. 24, 1992, entitled, xe2x80x9cON-CHIP INTEGRATED CIRCUIT SPEED SELECTION.xe2x80x9d By forming an oscillator in an IC semiconductor chip to generate pulses representative of the speed of other components formed in the chip, the operational speed of the oscillator (typically, a ring oscillator), and therefore, that of the other components formed in the semiconductor chip, can be determined. Again, the stress test levels are not altered in response to the operation speed measurements taken.
IC chip segregation tests also include bit-pattern recognition on each device under test. This method is particularly useful in memory device testing. In U.S. Pat. No. 4,335,457 issued to Early on June 15, 1982, entitled, xe2x80x9cMETHOD FOR SEMICONDUCTOR MEMORY TESTINGxe2x80x9d, semiconductor memory devices are tested using a special purpose computer which employs simple test patterns to determine the weakest bits of the device, and then tests only these relatively few xe2x80x9cweak bitsxe2x80x9d along with structurally and operationally adjacent bits using highly complex test patterns to determine if the device is functioning properly. Bit pattern recognition, however, is not a stress test screen. Thus, no adjustment of stress test levels, predicated on the bit pattern results, is either taught or suggested by this prior art.
Still, other methods may be employed to distinguish the IC chips based on variations in the operational parameters. However, independent of the method chosen, some functionally operating IC chips continue to remain vulnerable to excessive stress test screening levels due to chip-to-chip process variations.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an apparatus and method that determines the speed of IC chips on a semiconductor wafer and adjusts the stress test levels based on the speed measured for each device.
It is another object of the present invention to provide an apparatus and method for effectively protecting the short channel IC chip population with a lower voltage during voltage stress testing of a semiconductor wafer.
A further object of the invention is to increase the outgoing quality and reliability of a semiconductor die using a voltage screen without falsely rejecting the short channel die during voltage stress testing of a semiconductor wafer.
It is yet another object of the present invention to provide an apparatus and method for segregating IC chips capable of a higher voltage withstand level without compromising the resultant yield from the wafer lot.
Another object of the present invention is to increase the measure of reliability of the devices on a semiconductor wafer by assigning supply current limits as a function of device speed.
Still other objects of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method for testing integrated circuit semiconductor devices comprising the steps of: providing a wafer containing a plurality of integrated semiconductor devices; measuring a desired parameter of the devices; and, applying a stress test to the devices wherein test conditions of the stress test are adjusted based on the desired parameter measurements of the devices. Measuring a desired parameter first comprises verifying functionality of at least some of the integrated semiconductor devices at a set of operating conditions. The method further comprises the steps of: verifying device functionality at nominal operating conditions after the stress test; and, classifying the devices as failed if the devices do not function properly after the stress test.
The measuring of a desired parameter comprises measuring the operational speed of the devices prior to applying the stress test.
Additionally, applying a stress test comprises applying a first voltage at a value higher than the device normal operating voltage to the devices with a first measured operational speed, and a second voltage at a value lower than the first voltage to the devices with a second measured operational speed, the first operational speed being less than the second operational speed.
The method also comprises assigning supply current specification limits and measuring the limits of the devices such that a first supply current specification limit is assigned to devices with a faster of the operational speeds and a second supply current specification limit is assigned to devices with a slower of the operational speeds, the first supply current limit being greater than the second supply current limit.
The current invention is directed to, in a second aspect, a method for testing integrated circuit semiconductor devices comprising the steps of: providing a wafer containing a plurality of integrated semiconductor devices; determining functionality of the integrated semiconductor devices at nominal operating conditions; segregating the integrated semiconductor devices on the wafer by measuring a parameter of the devices; applying a stress test to the devices wherein test conditions of the stress test are adjusted based on the segregation parameter measurements of the devices; determining functionality of the devices at nominal operating conditions after the stress test; and, classifying the devices as failed if the devices do not function properly after the stress test.
The wafer includes devices having short and long gate channel widths, and the step of segregating the integrated semiconductor devices comprises determining which of the devices on the wafer have short gate channel widths. Applying a stress test pursuant to this method comprises applying a voltage higher than the device normal operating voltage to the devices. The step of determining which of the devices have short gate channel widths further comprises measuring the operational speed of the devices prior to applying the stress test.
Applying a stress test comprises applying a first voltage at a value higher than the device normal operating voltage to the devices with a first measured operational speed, and a second voltage at a value lower than the first voltage to the devices with a second measured operational speed, the first operational speed being less than the second operational speed.
Measuring the operational speed of the devices may comprise using flush delay time measurements or a performance sort ring oscillator to determine the operational speed of the devices.
The wafer is fabricated to include n-type and p-type field effect transistors, and wherein the step of measuring the operational speed of the devices comprises the steps of:
i) measuring drain-to-source current for the n-type and p-type field effect transistors;
ii) determining a drain-to-source current sum by summing the value of the n-type drain-to-source current with the absolute value of the p-type drain-to-source current;
iii) determining a device ISUM value by dividing the drain-to-source current sum by the gate channel width of the device; and,
iv) segregating the devices based on the ISUM value wherein the devices with lower ISUM values correspond to slower operational speeds and devices with higher ISUM values correspond to faster operational speeds.
Step (iv), segregating the devices based on the ISUM value, further comprises assigning devices with ISUM values less than or equal to 700 xcexca/xcexcm as slower operational speed devices.
The current invention provides, in a third aspect, an apparatus for testing a wafer containing a plurality of integrated semiconductor devices including n-type and p-type field effect transistors with short and long gate channel widths, and electrical parameters comprising:
a computer containing therein a set of instructions adapted to perform the following functions:
a) measure the short and long gate channel widths of the semiconductor devices;
b) segregate the semiconductor devices by the short and long gate channel width measurements;
c) apply a voltage stress to the devices wherein the voltage stress is a function of the short and long gate channel width measurements; and,
d) perform a functionality test to the devices after the voltage stress such that devices not passing the functionality test are labeled failed devices.
In a fourth aspect, the current invention provides a program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for voltage screening semiconductor devices on a wafer, the method steps comprising:
a) determining functionality of the integrated semiconductor devices at nominal operating conditions;
b) segregating the integrated semiconductor devices on the wafer by measuring a parameter of the devices;
c) applying a stress test to the devices such that test conditions of the stress test are adjusted based on the segregation parameter measurements of the devices;
d) determining functionality of the devices at nominal operating conditions after the stress test; and,
e) classifying the devices as failed if the devices do not function properly after the stress test screen.
Lastly, in a fifth aspect, the current invention provides a method for testing integrated circuit semiconductor devices comprising the steps of:
a) providing a wafer containing a plurality of integrated semiconductor devices including n-type and p-type field effect transistors with short and long gate channel widths, and operational speed parameters;
b) determining functionality of the integrated semiconductor devices at nominal operating conditions;
c) segregating the integrated semiconductor devices on the wafer by measuring the operational speed parameters;
d) applying a stress test to the devices wherein test conditions of the stress test are adjusted based on the operational speed measurements of the devices, such that a first voltage at a value higher than the device normal operating voltage is applied to the devices with a first measured operational speed, and a second voltage at a value lower than the first voltage is applied to the devices with a second measured operational speed, the first operational speed being less than the second operational speed;
e) determining functionality of the devices at nominal operating conditions after the stress test; and,
f) classifying the devices as failed if the devices do not function properly after the stress test.