1. Field of the Invention
The present invention relates generally to integrated circuit semiconductor memory devices and associated methods. In particular, the present invention relates to a column select line (CSL) control for which the same signal controls the enable timing and the disable timing signals for synchronous random access memory devices.
2. Description of Related Art
Speed improvements in semiconductor memory devices, such as Dynamic RAMs and Static RAMs, have historically come from process and photolithography advances. More recent memory speed improvements, however, have resulted mainly from making changes to the base architecture. An example of fast RAM architecture is the synchronous architecture. One key advancement of the synchronous memories is their ability to synchronously burst data at a high-speed data rate. Additionally, in a system with a synchronous RAM, since data, addresses and control signals are latched into the memory in synchronism with the system's clock signal, the system's processor is able to perform other tasks freely until data is available after a known number of clock cycles. This architecture provides substantial advantages in memory operating performance.
In a typical semiconductor memory device, in order to write/read data into/from a specific memory cell in a memory device, the specific memory cell should be designated by a row address and a column address. When the specific memory cell is designated in a read/write operation, a charge distribution operation is performed with respect to data read out from the designated memory cell to a bit line, and the readout data is amplified by a sense amplifier. The amplified data is transmitted to an input/output line through an I/O gate circuit, and then is output from the memory chip via associated output circuits. The read operation of one-bit data stored in the specific memory cell is completed by the above-described process. The column decoder turns on the selected I/O gate by receiving and decoding the column address.
To simplify the complexity of the decoding operation in highly integrated memories, a column pre-decoder is typically provided to pre-decode the column address prior to the main decoding operation therefor. This column decoding scheme has been adopted in most high density memory devices.
FIG. 1 is a block diagram illustrating a conventional exemplary synchronous memory device. Referring to FIG. 1, an array 100 of memory cells is provided to store data. Word lines WL0-WLm and bit lines BL0-BLn coupled with the cells run along the rows and columns of the memory cell array 100, respectively. In the vicinity of the cell array 100, a row decoder 120 is provided for selectively driving the word lines WL0-WLm, and an input/output (I/O) gate circuit 140 for supporting the selective transmission of data from the bit lines BL0-BLn to a data I/O buffer 280, and vice versa. The I/O gate circuit 140 is controlled by column select lines CSL0-CSLn. Externally applied address signals A0-Ax including both column and row address signals are fed to an address buffer 160. The column address signals CA0-CAi among the address inputs are applied to a column pre-decoder 180.
A clock buffer 230 is suppled with an external clock signal XCLK and provides an internal PCLK synchronized with the external clock signal XCLK. A CSL enable control circuit 240 generates a CSL enable control clock signal PCSLE by the logical combination of the internal clock signal PCLK and a column address setting signal PYE from a timing control logic (not seen). The column pre-decoder 180 pre-decodes the column address signals CA0-CAi and generates pre-decoded address signals DCA0-DCAj.
The column pre-decoder 180 outputs the DCA0-DCAj signals under the control of the PCSLE signal from the CSL enable control circuit 240. Main decoding operation of the column address signals are then carried out by a column main-decoder 200. This decoder 200 generates decoded signals DCAB0-DCABk by decoding the DCA0-DCAj. The DCAB0-DCABk signals are provided to a column driver 220 which drives the column select lines CSL0-CSLn selectively in response to the DCAB0-DCABk signals. A CSL disable control circuit 260 generates a CSL disable control clock signal PCSLD by the logical combination of the internal clock signal PCLK and a normally logic-high signal PVCCH. The column driver 220 is disabled by the PCSLD signal from the CSL disable control circuit 260, and hence stops driving the column select lines CSL0-CSLn.
FIGS. 2A and 2B illustrate the constructions of the CSL enable and disable control circuits 240 and 260, respectively, in detail. Referring first to FIG. 2A, the CSL enable control circuit 240 includes a delay circuit formed by inverters IV1-IV4 ("first" delay circuit), a NAND gate G1, and an inverter IV5. The internal clock signal PCLK is provided to the delay circuit. The NAND gate G1 has one input applied with the delayed signal of the clock signal PCLK and the other input applied with the column address setting signal PYE. The output signal of the NAND gate G1 is output through the inverter IV5 as the CSL enable control clock signal PCSLE.
Referring to FIG. 2B, the CSL disable control circuit 260 includes a delay circuit formed by inverters IV6-IV8 ("second" delay circuit) and a NAND gate G2. The second delay circuit is also fed with the clock signal PCLK. This delay circuit has a smaller delay time than the first delay circuit. The output of the second delay circuit is supplied to one input of the NAND gate G2. The normally logic-high signals PVCCH is provide to the other input of the NAND gate G2. This gate G2 outputs the CSL disable control clock signal PCSLD.
FIG. 3 shows the detailed configuration of a unit circuit of the column pre-decoder 180. As shown in FIG. 3, the unit pre-decoder circuit 180' includes inverters IV31-IV49 and NAND gates G34-G49. The unit column pre-decoder circuit 180' is provided with three column address signals CA0-CA2 from the address buffer 160, and generates eight pre-decoded column address signals DCA0-DCA7. The CSL enable control clock signal PCSLE is commonly applied to the first inputs of the NAND gates G42-G49. The second inputs of the NAND gates G42-G49 are provided with the substantial pre-decoded column address signals, i.e., the output signals of the inverters IV34-IV41, respectively. When the PCSLE signal becomes high, the output signals of the inverter IV34-IV41 can be propagated to the inverters IV42-IV49 via the NAND gates G42-G49, respectively, and they are output as the pre-decoded column address signals DCA0-DCA7. The PCSLE signal should go high only after the completion of the pre-decoding operation with the inverters IV31-IV41 and the NAND gates G34-G41 in order to prevent pre-decoding errors.
FIG. 4 illustrates the detailed construction of unit circuits of the column main-decoder 200 and column driver 220, respectively. Referring to FIG. 4, the unit column main-decoder circuit 200' includes NAND gates G50-G57, and inverters IV50-IV57 corresponding to the NAND gates G50-G57, respectively. Each of the NAND gates G50-G57 has one input provided with a corresponding pre-decoded column address signal DCAy (where, y=0, 1, . . . , or 7) and the other input with a gate control signal GCS from a timing control logic (not shown). Each output signal of the NAND gates G50-G57 is provided as a finally decoded signal DCABy (where, y=0, 1, . . . , or 7) through the corresponding inverter IV50, IV51, . . . , or IV57.
The unit column driver circuit 220' includes inverters IV60-IV67, cascode inverters (sometimes called "dual gate inverters") 40-47, and inverting latches 60-67. Each of the cascode inverters 40-47 consists of two PMOS transistors (e.g., MP40a and MP40b) and one NMOS transistor (e.g., MN40), and each inverting latch (e.g., 60) is formed of two cross-coupled inverters (IV60a and IV60b). For each cascode inverter (e.g., 40), three transistors (MP40a, MP40b and MN40) have their source-drain paths coupled in series between a boosted supply voltage terminal VEXT and a ground voltage terminal GND. Each decoded column address signal (e.g., DCAB0) is applied to the gates of the corresponding pull-up and pull-down transistors (MP40a and MN40). The PCSLD signal from the CSL disable control circuit 260 is commonly fed to the gates of the switching transistors MP40b-MP47b of the respective cascode inverters 40-47 via the inverters IV60-IV67. Each inverting latch (e.g., 60) is coupled to the drain junction of the corresponding switching and pull-down transistors (MP60a and MN60).
The pre-decoding operation begins with the CSL disable control clock signal PCSLD of a high level. A pre-decoded column address signal of a high level (e.g., DCA0) can be transferred to the gate of the PMOS transistor MP40a as a decoded column address signal DCABO only when the gate control signal GCS remains at a high level. Namely, the GCS signal determines whether to propagate the DCA0-DCA7 signals through the unit column main-decoder circuit 200' or not. The decoded signal DCAB0 goes high when both DCA0 and GCS signals are high, so PMOS pull-up transistor MP40a turns off and NMOS pull-down transistor MN40 on. The high-level DCAB signal is latched by the inverting latch 60, so that a corresponding column select line CSL0 is driven high. After the PCSLD signal has gone low, the GCS signal also goes low. Accordingly, the pull-up transistor MP40a turns on and the pull-down transistor MN40 off, but the column select line CSL0 still remains high owing to the inverting latch 60. In this situation, when the PCSLD signal goes high again, the switching transistor MP40b turns on, so the CSL0 line is driven low.
As described above, the column select lines CSL0-CSLn are selectively activated by the column pre-decoder 180, but deactivated by separately controlling the column driver 220.
FIG. 5 is a timing diagram illustrating read/write operations of the conventional synchronous memory device of FIG. 1. With reference to FIG. 5, after a column address strobe signal CAS is activated low, in clock cycle T0, the CSL disable control clock signal PCSLD goes high in synchronism with the external clock signal XCLK (or the internal clock signal PCLK). After a predetermined time (i.e., Tm1) has elapsed, during which the first column address signals CA#0 (i.e., CA0-CAi) have reached the column pre-decoder 180, the CSL enable control clock signal PCSLE goes high in response to the activation of the column address setting signal PYE (see FIG. 2A). Of course, the PCSLE signal is also synchronized with the clock signal XCLK (or PCLK). A unit column pre-decoder circuit 180' pre-decodes the column address signals CA#0 (CA0-CA2) and generates the pre-decoded column address signals DCA#0 (DCA0-DCA7) of which only one is active and the others inactive. Here, assuming DCA0 signal is activated high, then a corresponding column select line CSL0 will be driven high by a unit column driver circuit 220'.
In the next clock cycle T1, the PCSLD signal becomes high before the low-to-high transition of the PCSLE signal, so that the line CSL0 is deactivated. Next, after the second column address signals CA#1 (CA0-CA2) had reached the unit column pre-decoder circuit 180' and the time Tm1 has elapsed, when the CSL enable control clock signal PCSLE goes high again in response to the activation of the column address setting signal PYE. The unit column pre-decoder circuit 180' generates the second decoded column address signals DCA#1 (DCA0-DCA7). Here, assuming DCA1 signal is activated high, then a corresponding line CSL1 will be driven high by a unit column driver circuit 220'.
The other column select lines (such as CSL2 and CSL3) also will become activated and deactivated during next clock cycles (T2 and T3) in response to the other column address signals (such as CA#2 and CA#3) in the same manner as the above-mentioned.
In the above conventional memory device, the CSL enable control clock PCSLE should not go active until valid column address signals arrive at the pre-decoder 180 during each clock cycle Tc (where, c=0, 1, 2, . . . ). However, in the event the PCSLE signal goes high during a clock cycle (e.g., T1) before the valid column address signals CA#1 arrive at the column pre-decoder 180, owing to an insufficient delay time of Tm1, then the invalid column address signal CA#0 for the previous clock cycle T0 may be pre-decoded again by the corresponding column pre-decoder circuit 180' (refer to FIG. 3). Hence, the invalid decoded signal DCAB0 will be latched by the corresponding inverting latch 60 via the cascode inverter 40 (refer to FIG. 4). This leads to the activation of the column select line CSL0. Thereafter, when the valid decoded signal DCAB1 is activated by decoding the valid column address signals CA#1 and latched by a corresponding inverting latch 41 in cycle T1, the column select line CSL1 corresponding to the valid column address signals CA#1 also becomes active along with the invalid CSL0 line, causing an erroneous read/write operation. For the above reason, it is essential to ensure sufficient delay time Tm1 in the conventional memory device. This limits the memory access speed improvements.
In addition, according to the conventional memory device structure, a significant area penalty may result from the large reiterative layout area of the unit column driver circuit 220'.
Furthermore, since the pull-up and switching transistors MP40a-MP47a and MP40b-MP47b within the respective cascode inverters 40-47 provide current leakage paths together with the inverters IV60b-IV67b of the inverting latches 60-67 during power-up, the conventional device has large power-up current dissipation.