1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device that includes a DLL (Delay Locked Loop) circuit having a coarse adjusting unit and a fine adjusting unit.
2. Description of Related Art
Some of high-speed semiconductor memory devices such as a DRAM (Dynamic Random Access Memory) use a DLL circuit to accurately match an output timing of read data with a clock signal. The DLL circuit generates an internal clock signal accurately phase-controlled and, in some cases, employs a coarse adjusting unit that controls a phase of the internal clock signal at a relatively large adjustment pitch and a fine adjusting unit that controls the phase of the internal clock signal at a relatively small adjustment pitch (see Japanese Patent Application Laid-open Nos. 2009-284266 and 2009-21706).
However, when an adjustment code supplied to the fine adjusting unit is changed, jitters may be caused in the internal clock signal. It is therefore desired that the semiconductor device can decrease jitters caused by changes in the adjustment codes.