Testing VLSI circuit wafers has become over the years a significant part of the cost associated with the manufacturing of semiconductor products. Such testing generally entails inputting data into a logic circuit on the wafer at one or more primary inputs or testing test access point, and then reading the output results at one or more primary output terminals or output test access points.
Advances in VLSI designs has introduced radical changes in the field of testing and the diagnose of faults principally because the requirement of shipping defect free products to the customer has necessitated adding additional testing features to the design that have become part and parcel of the overall final product.
Techniques known as Design for Testability have been specifically introduced to this end. An example of such a technique is a scan design known as Level Sensitive Scan Design (LSSD) described in U.S. Pat. No. 3,761,695 to Eichelberger, which is today widely used throughout the VLSI design community.
The introduction of scan design has facilitated testing VLSI chips and integrated circuit (IC) packages by introducing linking latches and the like in scan chains memory devices scan chains, and alternating combinatorial portions of combinatorial logic between pairs of the scan chains.
The LSSD architecture incorporates several basic test concepts, such as the scan design. In such a design most of the device's storage elements, e.g., latches or registers, are concatenated in one or more scan chains and can be externally accessible via one or more serial inputs and outputs. Storage elements that are not in this category are usually memory or other special macros that are isolated and tested independently. Furthermore, this design methodology ensures that all logic feedback paths are gated by one or more of these storage elements, thereby simplifying a sequential design into subsets of combinational logic sections.
While scan chains are useful in determining whether the logic circuitry is functioning properly, the scan chains themselves may also be defective. While such defects may be from defective latches in the scan chain, if the latches are robust (designed to ensure their integrity), then defects are primarily in the wiring connecting the latches. Such defects may be open circuits (a clean break in the wiring), short circuits (a wire contacting another wire inadvertently), or stuck-at faults (the wiring touching either ground or voltage). The most problematic wiring defect is a stuck-at fault, since the latch otherwise appears to function properly, albeit with a constant input value.
Basic design concepts in conjunction with the associated system and scan clocking sequences greatly simply the test generation, testing, and diagnosability of complex logic structures. Every latch can be used as a pseudo Primary Input (PI) and as a pseudo-Primary Output (PO) in addition to the standard PIs and POs to enhance the stimulation and observability of the device being tested or diagnosed. LSSD latches are typically implemented in a L1/L2 configuration where the L1 or master latch has two data ports and may be updated be either a scan clock or a functional clock. The L2 or slave latch has only one clock input and that clock is out-of-phase with both L1 clocks. Scanning is performed using separate A and B clocks.
Of particular importance to the field of testing is a technique known as Self-Test, whereby a set of reproducible random binary test vectors are generated, thereby allowing creating testing means applicable to any chip, multi-chip modules, up to a system level, without requiring heavy expenditures of CPU time. Two basic components of a LBIST (Logic Built-in Self-Test) structure are a Liner Feedback Shift Register (LFSR) and a Multiple Input Signature Register (MISR). The LFSR serves as a pseudo random pattern generator that provides the stimuli for the logic to be tested, while the MISR is utilized to generate a unique signature representing the responses from the logic. Ideally the signature for each failing device is different from the signature of a good device after a predefined number of test cycles.
The configuration of the scan chain in the LBIST test mode is partitioned into several sub-chains of approximately the same length as described in U.S. Pat. No. 5,150,366 to Bardell et al. These chains are loaded and unloaded serially for each LBIST test. Once in LBIST mode, the scan chain is reconfigured into a number of parallel sub-chains. The pseudo random data loaded in parallel into each sub-chain is supplied by the LFSR and used as test stimuli. Similarly, the state of all the latches in the sub-chains is unloaded serially into the MISR forming a signature representing the compressed data.
Each LBIST test cycle, in addition to the loading and unloading of the sub-chains, requires timed application of system clocks to launch the test vector from these latches through the combinational logic and capture the resulting response in the receiving latches. Since a typical system design may consist of several system clocks and various path delays, the clock test sequence and timing set-up may be applied multiple times with different clock combinations and timings. Typically, this is accomplished by an on-product clock generation (OPCG) function and LBIST control.
An LBIST test interval in turn consists of a relatively large number of these load/unload sequences followed by the system clock cycle. At the end of the interval, the MISR contents or signature is unloaded and compared to an expected signature. Several signature intervals may be applied to achieve the desire test coverage.
This LBIST methodology is an effective Design for Test (DFT) that can support structural test from the chip level, various package levels, up to the system level. Some of the benefits associated with this approach include relatively low test data volumes, minimal VLSI test system requirements, at-speed test rates, and extendibility to system test.
The GPTR chain has been getting longer with each server design version. Currently, some of the chains have 1000+ SRLs. GPTR scan chains are expected to become significantly longer as multiple cores and additional arrays on the chip are added. The scan-only GPTR latches perform multiple functions, such as dynamic configurability, redundancy and repair, timing and performance optimization, test and debug “chicken switches”, and many other future design options.
Although the current GPTR chains represent a relatively small percentage of the total latches on the chip, their impact do diagnosability is more severe. In a stuck-at GPTR chain, the configurability of the chip is questionable and, in most cases, diagnosing most other problems on the chip becomes difficult and time consuming. In cases where the GPTR chain causes a very low or zero yield for the product, the diagnosability becomes a severe problem.
For illustrative purposes, and with reference to FIG. 1, there is depicted a prior art GPTR scan chain 100 including a chain of shift Register Latches (SRL), SRL1-SRLN, each including a master latch L1 (102) and a slave latch L2 (104). The master latch L1 (102) has a pair of data ports SCAN and DATA that may be captured by the latch responsive to a scan clock A-CLK. The slave latch L2 (104) captures the value stored in the master latch L1 (102) responsive to a second scan clock B-CLK.
Generally, the major drawback of the scan based design test methodology is encountered when a scan chain does not function properly which reduces the access to the internal logic of the device, severely complicating the diagnostic process and inhibiting rapid determination of the problem's root cause. In low or zero yield situations, the most common failure is often caused by the scan chain. Since the design requires a scan based design, it is found that the scan chains occupy a significant portion of the real estate area. Having a solution that speeds the ‘stuck-at’ scan chain diagnostics on failing chips results in timely yield improvements and, consequently, ensuring a successful production of the design.
The broken or stuck-at scan chain problem is even more severe when it occurs in scan chains that are used to control the test modes and configuration of the remaining latches on the device. In these situations, the diagnosis of the problem is necessary to identify and rapidly resolve catastrophic zero yield or design problems.
Additionally, these type of problems are usually encountered early in the technology's life cycle and diagnosing them is critical in improving the process so it quickly achieves manufacturing yield levels. The inability to improve the technology and yield of the device can greatly impact a program or at least severely minimize the revenue that could be realized. Rapid diagnosis to a location for Physical Failure Analysis (PFA) is needed to understand and correct the process anomalies.
A common approach to diagnose “broken” or stuck-at scan chains is to use the system port to switch the latches down stream from the “break” and than unload the scan chain and determine the last latch position that switches to the complement state of the stuck-at state. Of course, one needs to provide the proper logic state to the system port input of the latch. Furthermore, to get an accurate diagnostic call for the stuck latch, one needs to provide the proper logic input to the next latch downstream to the stuck-at latch, otherwise only an approximate latch diagnostic location can be determined.
Thus, there is a need for a GPTR and a system capable of diagnosing broken scan chain defects of long non-scannable register chains (GPTR), primarily those exceeding 10K latches).