1. Field of the Invention
The present invention relates generally to semiconductor devices, and, more particularly, to semiconductor devices that combine high-speed performance and low power consumption.
2. Description of the Related Art
An example of reducing power consumption by substrate bias control is described in 1996 IEEE International Solid-State Circuit, Digest of Technical Papers, (1996), pp. 166-167.
With the recent popularity of low-power CMOS LSIs (Complementary Metal Oxide Semiconductor Large Scale Integrated circuits), a trend has developed to maintain high-speed operation by decreasing the threshold voltage VT of the MOSFETs as the operating or supply voltage is dropped. When the supply voltage drops to 2 V or lower and when the threshold voltage VT is decreased to 0.5 V or lower correspondingly, however, the subthreshold leakage current increases, whereby the transistor cannot be cut off completely. Consequently, the standby current of the LSI chip increases, which represents a bottleneck in the design of a system that includes a battery-powered CMOS LSI chip. Furthermore, the current during normal operation also increases as the threshold voltage VT increases.
In order to break the bottleneck, a well-known system achieves a high-speed operation by decreasing the threshold voltage of each of the MOSFETs in the chip during normal operation, and decreases the standby current by increasing the threshold voltage at the time of standby. Nevertheless, the following three problems exist in this system:
(1) An overcurrent flows because of latching-up when the power supply is turned on, and the wiring in the CMOS LSI chip may fuse, or the normal supply voltage may become inapplicable as the load exceeds the current capacitance of the power supply. This problem is caused because the layout and connections of the circuit are designed so that the substrate (well) and source of the MOSFET are not at equipotential.
For example, when a p-channel MOSFET (PMOSFET) is used for applying a positive supply voltage (e.g., 1.8 V) to the source (p-layer), the pn junction between the source and well is excessively biased in the forward direction because the well (n-well) remains at a floating 0 V just until the application of the supply voltage, thus causing latch-up of the CMOS. In the case of conventional CMOS LSI products at 2 V or higher, the pn junction is never biased in the forward direction as in the normal operation thereafter, even during the application of the supply voltage, since the well and source of the MOSFET are connected so that both are at equipotential as much as possible. Since the threshold voltage VT is constant at all times at a value of substantially 0.5 or higher, moreover, there is no problem of subthreshold current.
In the case of an n-channel MOSFET (NMOSFET), the problem is not so serious. When the supply voltage is applied to the drain, the substrate (p-well) of the NMOSFET is at a floating 0 V and the source is fixed to an earth potential of 0 V, because the pn junction, formed between the drain and the well, is not biased in the forward direction. However, there is a subthreshold current flowing between the drain and source when the threshold voltage is 0.5 V or lower. By separately controlling the well and source, the threshold voltage in the CMOS LSI is lowered.
(2) The time required to switch the normal mode to the standby mode and the time required to switch the standby mode to the normal mode are extremely long, on the order of xcexcs. Assuming that the substrate voltage is generated on-chip, by a charge pumping circuit for pumping the capacitor in the chip, the output current is limited to a low level. On the other hand, the transistor in the chip is used to connect the power supply terminals of the substrate in common, and consequently the total substrate capacitance has an extremely large value (100 pF or greater). Therefore, a large load (substrate) capacitance is driven by a substrate-voltage generating circuit whose current driving capability is low when the mode is switched, so that the response time tends to become longer.
(3) The subthreshold current flows everywhere, even in the CMOS circuit, thus increasing the operating current of the whole chip. This problem exists because, in the inactive state, the threshold voltage of the transistor in the CMOS circuit or circuit block is low during normal operation.
The present invention controls the substrate or well voltage of a transistor in a manner that solves the foregoing three problems.
An object of the invention is to hinder the latching-up that occurs when the supply voltage is applied to a CMOS circuit that includes MOSFETs having a low threshold voltage, or when the supply voltage is cut off to the CMOS circuit.
Another object of the invention is to decrease the subthreshold current during normal operation.
A further object of the invention is to realize low power consumption while maintaining high operating speed, for a CMOS circuit that operates at a voltage of 2 V or below, a CMOS LSI, and a semiconductor device using the CMOS circuit.
In general, the invention achieves these and other objects by controlling the well voltage of a CMOS circuit when the power supply is turned on and when cut off, and during operation.
In one embodiment of the invention, in which the CMOS circuit includes MOSFETs that cannot be cut off substantially satisfactorily during normal operation, after the well voltage is applied to the well of the CMOS circuit so that the MOSFETs can be cut off, the supply voltage is applied to the CMOS circuit.
In another emboidment, after a third supply voltage (generated from a first supply voltage by a voltage conversion circuit) is applied as a well voltage to the well of the CMOS circuit, a second supply voltage is applied to the CMOS circuit.
In yet another embodiment, the invention provides a circuit for fixing the well potential of the CMOS circuit, and a circuit for varying the well potential of the MOSFETs by capacitive coupling according to the variation of the input signal of the CMOS circuit.
In still another embodiment, the invention provides a semiconductor device that includes a dynamic memory cell comprising a MOSFET, a capacitor, and a CMOS circuit, wherein the well potential of the MOSFETs constituting the CMOS circuit is subjected to a pulse variation, and wherein the substrate voltage of the dynamic memory cell is substantially a DC supply voltage.
In another embodiment, the invention provides a semiconductor device including a static memory cell that is operated at a high voltage and is constituted by MOSFETs of high threshold voltage, and a CMOS circuit operated at a low voltage and constituted by MOSFETs having a low threshold voltage. The well potential of the MOSFETs constituting the CMOS circuit is subjected to a pulse variation.
In yet another embodiment, the invention provides a semiconductor device including at least one CMOS circuit, a standby control circuit, and a voltage conversion circuit, wherein the voltage generated by the voltage conversion circuit is supplied to the standby control circuit, and the standby control circuit varies the well potential of the CMOS circuit using the output of the voltage conversion circuit, depending on operating conditions. A capacitor having a capacitance that is greater than the capacitance of the well is connected to the output of the voltage conversion circuit.