1. Field of the Invention
The present invention generally relates to high voltage on-chip circuitry for electrically erasable programmable read-only memory EEPROMs or flash memory. More particularly a low power, high-voltage ramp-up rate control circuit is described which utilizes a current reference, a current controlled oscillator, a charge pump, a feedback transistor, a reference transistor, and a ramp-up transistor.
2. Description of the Prior Art
FIG. 1 contains a circuit schematic which shows the prior art implementation of a ramp-up rate control circuit. A functional block labeled charge pump+oscillator+current reference 110 is shown. The output of this block 110 is a charge pump current, Icp 170. In addition, the voltage on the output node 195 of this block 110 is HV. (High Voltage). A reference current, Iref, 120 is developed in a current source. This current flows into the drain of an N-channel metal oxide semiconductor field effect transistor, NMOS FET, M1130. The gate 175 of FET M1130 is connected to its drain. The source of FET M1 is connected to ground 185.
The ramp current Ir 190 flows into the drain 165 of NMOS FET M2140. The gate of FET M2140 is connected in common to the gate of FET M1175. The source of FET M2 is connected to ground 185. The drain 165 of FET M2 is connected to the gate of NMOS FET M3150. The drain 180 of FET M3150 receives the leaking current Ileak. The source of FET M3 is tied to ground 185.
In this prior art circuit in FIG. 1, the leak transistor M3150 will tend to discharge the charge pump output node HV 195. The leakage current Ileak 180 depends on the gate voltage V1165 of FET M3150. The ramp-up rate (dV/dt) is equal to Ir/C where C is the capacitance of the capacitor 160 and V is the voltage across capacitor C. In FIG. 1, the leakage path will consume the extra current Ileak. If this extra leakage path 180 can be eliminated, then the power consumption can also be reduced.
U.S. Pat. No. 4,488,060 (Simko) “High Voltage Ramp Rate Control Systems” describes high voltage ramp rate control systems. These systems are useful for on-chip EEPROM high voltage power supplies.
U.S. Pat. No. 5,872,733 (Buti et al.) “Ramp-Up Rate Control Circuit for Flash Memory Charge Pump” describes a ramp-up rate control circuit. This circuit controls the ramp-up rate of a charge pump having an output which provides an output voltage and an output current.
U.S. Pat. No. 5,408,133 (Honnigford et al.) “Ramp Control Circuit” discloses an apparatus for providing an EEPROM programming signal.
U.S. Pat. No. 5,365,121 (Morton et al.) “Charge Pump with Controlled Ramp Rate” discloses a charge pump with a controlled ramp rate. It is made up of a charge pump, a differentiator circuit and a trigger circuit.