1. Field of the Invention
The present invention relates generally to redundancy repair of integrated circuit memory devices, and more particularly to a memory device having row redundancy repair.
2. Brief Description of the Related Art
Electronic memory, including read only memory (ROM), flash memory, and random access memory (RAM) devices, such as DRAMs and SRAMs, typically utilize memory arrays having rows and columns of memory cells for storing data. Manufactured memory arrays are tested for integrity, and defects are repaired. Typical tests involve writing data to the array using an external pattern, and reading the pattern back to confirm that the data is stored accurately.
When testing reveals a defective primary row or column, a non-defective redundant row or column is used to replace the defective primary row or column. This is achieved with fuses or anti-fuses that set hardwired latches associated with the defective row or column and map the address of the defective primary row or column to a fully-operable redundant row or column. With this re-mapping, all attempts to access the defective row or column will be redirected to the redundant row or column known to be properly working. The remapping process and logical substitution of the redundant region is transparent to the end user. U.S. Pat. No. 6,314,030 to Keeth, the entire disclosure of which is incorporated herein by reference, further describes memory circuit device testing and repair using redundant memory.
Testing memory devices by writing data to the array is a relatively slow process, especially for flash memory. During such memory testing, one bit pattern which is used employs a repetitive bit pattern, for example, of alternating ones and zeroes arranged in a xe2x80x9ccheckerboardxe2x80x9d or inverse xe2x80x9ccheckerboardxe2x80x9d pattern throughout the memory array. The pattern is written in blocks to the flash memory array.
The checkerboard testing pattern is obtained by loading each row of the flash memory array with an alternating series of 1""s and 0""s. The checkerboard pattern alternates from row to row, thus, even rows (rows 0, 2, 4, etc.) are loaded with a repeating pattern of 0""s and 1""s (0-1-0-1 . . . ), while odd rows (1, 3, 5, etc.) are loaded with a repeating pattern of 1""s and 0""s (1-0-1-0 . . . ).
A short between adjacent cells in two adjacent memory rows is a typical fault in a flash memory array, which requires replacement of the shorted pair of rows with a corresponding pair of redundant rows. Each pair of bad rows will be either an even and odd row (e.g., rows 2 and 3, for example), or an odd and even row (e.g., rows 3 and 4).
A flash memory device typically is divided into several memory banks, each of which is further divided into a plurality of memory blocks. Each memory block is provided with a number of primary rows and a lesser number of redundant rows, the latter bit available for repairing faulty primary rows in the associated block. Pattern writing during testing includes writing the pattern to the primary rows of the memory block, as well as to the redundant rows of the block, as these too must be tested for integrity. If a defective primary row is replaced by a redundant row during testing, the testing pattern must be rewritten to the block with the redundant row receiving the same bit pattern as the replaced defective row, for further testing. This is a time consuming process.
The present invention provides an easier way to test primary rows and redundant rows in memory blocks, and to substitute redundant rows for defective primary rows while permitting continued testing without requiring a rewrite of the testing pattern. In the invention, pairs of defective rows of memory are replaced with redundant rows having an odd-even row pairing which matches the odd-even row pairing of the defective row pair. Consequently, a loaded test pattern of a redundant row used for repair matches that of the defective row which requires repair. This avoids having to rewrite the test pattern when making a repair using redundant rows and saves time in testing the memory.
A memory device according to the present invention includes memory blocks, each block having rows of primary memory cells having either an even or an odd address. Each memory block also includes at least two rows of redundant memory cells. Like each primary memory row, each row of redundant memory has an even or an odd row address. In each adjacent row pair, whether a primary or redundant row, one row has an even address, and the other row has an odd address.
During testing, the memory block is pre-loaded with an external test pattern, such as a checkerboard pattern, the arrangement of which alternates a xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d pattern at each column and with each row, as shown in the example in the Table below:
Upon detection of a failed odd-even or even-odd pair of primary memory rows, circuitry in the memory device remaps using programmed coding the addresses of the defective pair of adjacent rows, to a corresponding odd-even or even-odd pair of redundant rows as replacements. Advantageously, the replacement redundant rows have addresses that correspond correctly (odd or even) with the odd or even addresses of the replaced primary rows. By using the correct odd-even or even-odd pairing of redundant rows as replacements, the pre-loaded test pattern (checkerboard) will not change and need not be rewritten during further testing, so the pattern that is read out from the replacement redundant rows does not change from that of the replaced primary rows of the block during the further testing. The test pattern used need not be a checkerboard. Any pattern can be utilized that distinguishes even and odd rows, and preferably allows detection of failed row pairs.
Although preferred embodiments of the present invention are described with respect to repairing rows of memory arrays, the invention is not so limited. Repairs of shorted columns, for example, also could take place in odd/even pairs utilizing the teachings of the present invention.