1. Field of the Invention
The present invention relates generally to a deep trench capacitor, and more specifically to the process of fabricating and the device of a trench capacitor, providing increased capacitance.
2. Description of the Prior Art
An important design goal in the design and fabrication of deep trench capacitors is reduced size. Another design goal in designing and fabricating deep trench capacitors is increased capacitance.
In accordance with some conventional processes for fabricating deep trench capacitors, capacitors are formed above the substrate. This type of structure utilizes some of the limited space above the substrate. Therefore, the available space for fabricating other devices is reduced. In order to provide space for fabricating other devices, and in order to increase the density of devices, the size of the trench capacitor must be reduced or the capacitor may be built within the substrate. A trench type capacitor is a capacitor that is fabricated within the substrate.
FIG. 1 shows a transverse cross-sectional view of a typical prior art trench type capacitor at 10. A trench 12 having sidewalls and a bottom is formed within a semiconductor substrate 14. The trench 12 is typically formed in the substrate 14 by a process of patterning and etching the substrate 14. Subsequently, a first conductor 18 is formed in a portion of the substrate 14 that envelopes a portion of the trench 12 by doping the inside walls and bottom surface of the trench 12 with arsenic ion (or phosphoric ion). The first conductor 18 is used as a bottom conductor, or xe2x80x9cbottom electrode platexe2x80x9d, of the conventional trench type trench capacitor 10. After forming the first conductor 18 by doping the semiconductor substrate 14 as described above, a dielectric layer 22 is formed typically by depositing a silicon nitridexe2x80x94silicon oxide layer (commonly referred to as an NO layer). After forming the dielectric layer 22, a second conductor 26 is formed by depositing amorphous silicon into the trench 12 and over the dielectric layer 22. The second conductor 26 provides a top conductor, or xe2x80x9ctop electrode platexe2x80x9d, of the conventional trench type capacitor 10.
One problem associated with the depicted prior art deep trench capacitor 10 is that it provides only a limited amount of capacitance. The capacitance of the deep trench capacitor 10 is proportional to the surface areas of the first and second plates 18 and 26. It is possible to increase the capacitance of the deep trench capacitor 10 by increasing the size of the plates. However, increasing the size of the plates also increases the total size of the trench type capacitor which defeats the design goal of minimizing the size of the trench capacitor.
It is an object of the present invention to provide a deep trench capacitor having increased capacitance, and requiring a decreased amount of space. What is needed is a design and method of fabricating a deep trench capacitor having increased capacitance, and decreased size.
It is an object of the present invention to provide a deep trench capacitor having increased capacitance, and decreased size.
It is another object of the present invention to provide a process of fabricating a deep trench capacitor having increased capacitance, and requiring a decreased amount of space.
Briefly, a presently preferred embodiment of the present invention provides a process of fabricating a trench capacitor. The process includes the steps of: depositing a nitride masking layer over a top surface of a semiconductor substrate; patterning and etching to remove a portion of the nitride masking layer and a portion of the substrate to form an exposed deep trench in the substrate, and to expose an edge of the nitride masking layer, the trench having sidewalls and a bottom surface; forming an oxide fill plug to fill a bottom portion of the trench, the oxide fill plug extending from the bottom surface of the trench to a predetermined depth level below the top surface of the substrate; etching a portion of the sidewalls to form an etched back portion of the sidewalls located between the oxide fill plug and the top surface of the substrate; forming a collar insulating layer within the etched back portion of the sidewalls; forming a protection layer over the exposed edge of the nitride masking layer and over the collar insulating layer; and removing the oxide fill plug from the trench.
The process also includes the steps of: doping a region of the substrate enveloping the bottom portion of the trench; depositing a spacer insulating layer over the protection layer, the sidewalls, and the bottom surface of the trench; removing a portion of the spacer insulating layer to expose a substantially central portion of the bottom surface of the trench; depositing a conducting layer over the nitride masking layer, the spacer insulating layer, and the exposed central portion of the bottom surface, the conducting layer and the doped region of the substrate being in electrical contact and forming a first plate of the capacitor; depositing a photo resist fill plug into the trench and over the conducting layer, the photo resist fill plug providing protection of a bottom portion of the conducting layer, and leaving an unprotected portion of the conducting layer; removing the unprotected portion of the conducting layer to expose a top surface of the conducting layer; and removing the photo resist fill plug to expose inner walls of the conducting layer.
The process further includes the steps of: removing the spacer insulating layer to expose outer walls of the conducting layer, and leaving empty space between the outer walls and the sidewalls; removing the protection layer; forming a dielectric layer over the sidewalls of the trench and over the top surface, the inner walls, and the outer walls of the conducting layer; and depositing a conducting plug over the dielectric layer and filling the trench, the conducting plug forming at least a portion of a second plate of the capacitor.
An important advantage of a deep trench capacitor formed in accordance with the present invention is that it provides increased capacitance, and requires a decreased amount of space thereby optimizing the use of silicon real estate.