1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to a filtering circuit, and more particularly to a filtering circuit which can suppress a jammer in a wireless communication system.
2. Description of the Related Art
In a multi-channel wireless communication environment, we have not only the signal in a desired channel, but also jammers in other channels. All of the jammers should be suppressed so strongly that the signal to noise ration (SNR) of the desired signal can be improved to a level necessary for successful wireless communication.
A channel selection filter with the frequency characteristic to pass only the signal in the desired channel is needed to suppress jammers. The bandwidth of the filter corresponds to that of the channel bandwidth.
A short-range communication system has a narrow channel bandwidth of less than 1 MHz, while some other communication systems have much wider channel bandwidths, for example, 20 MHz for Wi-Fi and more than 4 GHz for ultra-wideband (UWB).
Generally, in an integrated circuit (IC), the die area of an analog filter is inversely proportional to the frequency bandwidth. This means that the analog channel selection filter in a short-range communication system would typically occupy more than half of the entire wireless IC. A digital filter is used for channel selection in most of the commercial wireless IC's for a short-range communication system since a digital filter can be implemented with much smaller area than an analog filter.
In the case of using a digital filter for channel selection, analog signals including the desired signal and jammer signals must be converted to digital signals before suppressing jammers. Given that a wireless IC should provide successful communication under jammers 40 dB larger than the desired signal, an analog-to-digital converter (ADC) should have a 40 dB wider dynamic range than it should have without the presence of jammers. Therefore, the ADC is required to have higher resolution, leading to larger power consumption.
The block diagram shown in FIG. 1 is a proposed architecture to suppress jammers without any analog filters as an example of background art.
This architecture has two signal paths between a mixer circuit and an ADC.
In the first path, the jammers are extracted from the input signal by suppressing a desired signal. The input signal to the first path is converted to a digital signal using an ADC with a low resolution. Subsequently, only the desired signal is suppressed using a digital band stop filter. Finally, the digital signal that contains only the jammers is converted back to an analog signal.
In the second path, the input signal is delayed such that that jammers in the output of the second path are synchronous with jammers in the output signal of the first path.
The output signal from the first path consists of only jammers while the output signal from the second path consists of the desired signal and jammers. The jammers can be suppressed by subtracting the output signal in the first path from the output signal from the second path.
Since this architecture shown in FIG. 1 does not contain analog filters, it can be realized with a smaller integrated circuit die area than previous architectures having analog filters. In addition, the required ADC resolution can be reduced since the jammers are suppressed before reaching the second ADC.
However, the architecture shown in FIG. 1 has the severe problem of introducing noise to the system.
The delay circuit in the second path consists of sample and hold circuits connected in series as shown in FIG. 2.
The number of sample and hold circuits, Nc, is equal to the total delay time required for the delay circuit, Td, divided by the sampling time of the sample and hold circuit, Ts, as in the following equation 1:Nc=Td/Ts  Equation 1
Td is set to a value equal to the delay time seen by the jammers going through the first path. This delay is nearly equal to the reciprocal of the bandstopwidth of the digital band stop filter in the first path, which corresponds with the bandwidth of the desired channel.
Ts is typically set to one-quarter of the reciprocal of the entire bandwidth of all the signals including the desired signal and jammers.
This architecture usually needs more than 100 sample and hold circuits in a narrow band communication system.
Since a delay circuit introduces noise, such as thermal noise and switching noise, this architecture makes the SNR significantly worse.