Integrated circuits (“ICs”) such as, for example, programmable integrated circuits can be programmed to perform specific functions. One example of programmable integrated circuits is programmable logic devices (“PLDs”) which can be programmed by a user to perform specified logic functions. One type of programmable logic device, called a field programmable gate array (“FPGA”), is popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
In a typical architecture, the FPGA includes a processor, an array of configurable logic blocks (“CLBs”), and programmable input/output blocks (“IOBs”) which provide external access to the CLBs. The processor, CLBs, and IOBs are interconnected by programmable fabric routing. The fabric routing comprises many interconnect wires and associated programmable interconnect points (PIPs) which can be programmed to selectively route signals among the various CLBs and IOBs.
The processor typically implements numerous debug features such as a trace feature. When the trace feature is enabled, the instruction stream executed by the processor is monitored and certain debug events are used to cause trigger events. When a trigger event occurs, the processor asserts an output-trigger-event signal to indicate that the trigger event occurred. The output-trigger-event signal is typically modified outside the processor and fed back to the processor using the fabric routing.
For proper operation of the trace feature, there is typically a constraint that the output-trigger-event signal be fed back to the processor within less than a fraction of one clock period. However, placement of pins on the processor is based on optimizing processor performance rather than optimizing debug features, and thus the debug pins associated with the input and output trigger-event signals are typically placed far apart from each other. Thus, the delays associated with using the fabric routing (e.g., the delay associated with driving the output-trigger-event signal to two or more CLBs) are too great to satisfy this constraint when the processor is running at or near maximum speed. As a result, features such as trace collection cannot be done reliably unless the processor is configured to run at a slower speed. However, processor performance and efficiency are significantly decreased if the processor is configured to run at a slower speed. In addition, a problem may not appear if the processor is configured to run at a slower speed because the problem may only occur when the processor is running at the faster speed. For example, deadlock may occur between the processor and a hard disk drive only when the processor is running at full speed. However, deadlock may not occur when the processor is running at a slower speed.
Therefore, it is desirable to feed back a signal such that stringent timing requirements are satisfied while still maximizing processor performance.