Universal Serial Bus (USB) technology allows numerous peripheral devices to be connected to computing devices in a plug-and-play fashion. Such devices include, for example, keyboards, speakers, cameras, joysticks, mice, hard drives, flash drives, DVD drives, and various transceivers. Current peripheral devices are designed and implemented as defined by the Universal Serial Bus 2.0 Specifications, Revision 2.0, which is herein incorporated by reference in its entirety. Users now expect a high level of performance from USB devices. These peripheral devices require ever-increasing bus bandwidth. Therefore, USB technology is evolving from USB 2.0 “High-Speed” to USB 3.0 “SuperSpeed”.
The Universal Serial Bus 3.0 Specifications, Revision 1.0, which is also herein incorporated by reference in its entirety, define a number of criteria to be met in order to comply with the USB 3.0 Specifications. USB 3.0 improves on USB 2.0 by improving power management while leveraging existing USB infrastructure. USB 3.0 is a physical SuperSpeed bus combined in parallel with a physical USB 2.0 bus. It has similar architectural components as USB 2.0, including USB 3.0 interconnect, USB 3.0 devices, and USB 3.0 host. The USB interconnect is the manner in which USB 3.0 and USB 2.0 devices connect to and communicate with the USB 3.0 host. The USB 3.0 interconnect inherits core architectural elements from USB 2.0, although several are modified to accommodate the dual bus architecture. Modifications in USB 3.0 include eight primary conductors: three twisted signal pairs for USB data paths and a power pair. One of the twisted signal pairs accommodates for USB 2.0 data path, while two of the twisted signal pairs are used to provide USB 3.0 data paths, one for the transmit path and one for the receive path. In all, USB 3.0 inherits the Vbus, D+, D−, and GND wires from USB 2.0, and incorporates VDD33 conductors to accommodate for SuperSpeed interfaces. USB 3.0 accommodates forwards and backwards-compatibility with existing USB 2.0 peripherals at a lower speed using a Type-A connector.
While USB technology evolves towards the USB 3.0 standard, many current computing devices and peripherals only support USB 2.0. One such peripheral includes a transceiver. 40-nm FPGA's and ASCI's with transceivers have higher integration than prior nodes, including the 65-nm and 45-nm nodes. Another performance benefit of the 40-nm process includes shorter minimum transistor gate lengths than the 45-nm process. Further, power consumption is reduced in the 40-nm node, as smaller process geometries reduce parasitic capacitances. Therefore a need exists for integrating a USB 2.0 transceiver on the same SOC as a USB 3.0 PHY without incurring excess area or system costs.