This invention relates to the field of hermetic ceramic substrates for microelectronic applications. More particularly, this invention relates to protective surface layers for providing hermeticity and corrosion protection.
In the microelectronics environment, there is a need for high density, high strength packaging to provide interconnection between semiconductor devices and connection from the devices to the electrical power supply. The electrical properties which are desirable include a highly conductive medium in a highly insulative carrier medium having a low dielectric constant. Thermally, the package must withstand not only the operating environment but also the thermal excursions encountered during the processing and fabrication of the part.
Mechanically, it is preferable to have a substrate package which can withstand chip and pin joining stresses and stresses related to interconnecting with the next level of packaging.
The packaging should also be hermetic to prevent degradation of any of the desired properties due to adverse environmental effects. In particular, corrosion of any of the metallurgies used in the package is a real concern if not adequately protected from ambient moisture and deleterious ionic contaminants.
Boss et al. U.S. Pat. No. 4,880,684, the disclosure of which is incorporated by reference herein, discloses the present day state of the art for the bottom surface of a ceramic substrate. Thus, there is a capture pad, a polymeric sealing and stress relief layer followed by an I/O (conventional nomenclature meaning "input/output") bonding pad. Thereafter, the I/O pin is brazed to the I/O bonding pad.
It has recently been discovered by the present inventors, however, that there is a concern with the structure disclosed by Boss et al. The I/O bonding pad is typically made from a plurality of layers of metallic material. The present inventors have found the presence of corrosion at this I/O bonding pad during reliability testing which has led to premature failure of the I/O pad structure. While not wishing to be held to a particular theory, it is believed by the present inventors that the corrosion of the I/O bonding pad occurs by a galvanic corrosion mechanism wherein the less noble metals become anodic to the more noble metals in the presence of a suitable electrolyte such as water. At the edges of the I/O bonding pad, the different metals of the pad are exposed together to the environment which thus allow these deleterious corrosion cells to form.
It has thus been proposed by the present inventors to apply a protective coating to the bottom surface of the ceramic substrate after the pins have been attached to protect the edges of the I/O bonding pads.
Various solutions have been proposed to protect electronic substrates from the effects of corrosion.
Bakos et al. U.S. Pat. No. 4,048,356, the disclosure of which is incorporated by reference herein, discloses in general the application of a hermetic topsealant for the active areas of an integrated circuit device.
Darrow et al. U.S. Pat. No. 4,233,620, the disclosure of which is incorporated by reference herein, discloses the application of an epoxy material to the surface of a substrate having electrically conductive pins protruding therefrom and to the sides of the substrate so as to hermetically seal the backside of the substrate containing a chip in a cap. Such arrangements wherein epoxy is applied are typically not reworkable, a disadvantage for many ceramic substrates such as those contemplated by the present inventors wherein reworkability is a necessity. Additionally, epoxies are not suitable for the substrates contemplated by the present inventors because epoxies are brittle which could lead to their cracking. Manifestly, such cracking destroys any advantage epoxies may have as a barrier material. The poor thermal stability of epoxies is yet another disadvantage.
Dalencon U.S. Pat. No. 4,360,559, the disclosure of which is incorporated by reference herein, discloses the application of a protective varnish to a printed circuit card, including the weld area of the pins.
Harris U.S. Pat. No. 4,427,715, the disclosure of which is incorporated by reference herein, discloses an inorganic passivation layer such as polysilicon glass or vapox overlapping the edge of the bonding pad that is applied prior to the bonding operation. The patent is directed to a structure for TAB bonding pads on semiconductor chips that is aimed at preventing the cracking of the chip during the thermo-mechanical bonding process.
Clark et al. U.S. Pat. No. 4,592,944, the disclosure of which is incorporated by reference herein, discloses a polymeric coating over the top surface of substrates for corrosion protection, insulation, etc. The corrosion protection is directed at the top surface thin film circuitry and solder connections.
Notwithstanding the numerous solutions and disclosures proposed by those familiar with electronic substrates, there still remains a very real need to solve the problem discovered by the present inventors, namely, the corrosion of the I/O bonding pad due to corrosive effects.
Accordingly, it is an object of the present invention to solve the problem of I/O bonding pad corrosion by providing a protective layer over the I/O bonding pads to insulate them from the deleterious effects of corrosion.
This and other objects of the invention will become apparent to those skilled in the art after referring to the following description considered in conjunction with the accompanying drawings.