1. Field of the Invention
The present invention relates generally to semiconductor fabrication techniques and, more particularly, to a fabrication technique for improving conductivity at an interface between a polysilicon layer and a conductive layer in an integrated circuit device.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Semiconductor memory devices, such as dynamic random access memory (DRAM) devices, are widely used for storing data in systems such as computer systems. A DRAM memory cell typically includes an access device such as a field effect transistor (FET) coupled to a storage device such as a capacitor. The access device allows the transfer of charged electrons to and from the storage capacitor thereby facilitating read and write operations in the memory device. The memory cells are typically arranged in a number of rows and columns to provide a memory array. Each memory cell in the array is connected to at least one row or “wordline” and at least one column or “bitline.” Generally speaking, the gate terminal of the access device may be coupled to the wordline while at least one of the remaining terminals (e.g. drain/source) is coupled to the bitline. The other terminal may be coupled to the capacitor. When a voltage is applied to the wordline, the gate of the access device opens and charged particles flow from the bitline to the storage device or vice versa, depending on the mode of operation of the memory cell (e.g. read or write).
As can be appreciated, a variety of technologies are used to fabricate the memory cells. Generally speaking, layers of conductive, non-conductive, and semiconductive materials are generally disposed on a substrate to form the access and storage structures described above. Numerous fabrication techniques may be used to facilitate the deposition, masking, and etching steps used to construct the memory cells, as can be ascertained by those skilled in the art. In one technique, a conductive material, such as doped polysilicon, is used to form the wordlines which are used to control the gate of the access devices in the memory cell. Each wordline may include several layers disposed on the conductively doped polysilicon layer, thereby forming a wordline stack.
During formation of the wordline stack, a nitride layer, such as silicon nitride (Si3N4), may be formed on the polysilicon layer to provide an even etch surface. While the nitride layer may be advantageous for part of the fabrication process, it may be the cause of problems in later processing steps. For example, during formation of the wordline stack, a conductive metal material, such as tungsten (W), may be disposed on the polysilicon layer to provide conductive contact to metal layers disposed above the integrated circuit. However, because the thin nitride layer may be used to provide an even etch surface on top of the polysilicon layer, the nitride layer may form a barrier between the conductive metal material and the polysilicon layer. Thus, the nitride layer may ultimately reduce the conductivity between the metal layers and the polysilicon, thereby reducing the effectiveness of the integrated circuits.