1. Field of the Invention
The present invention relates to a Bi-CMOS logic circuit, and particularly to an integral Bi-CMOS logic circuit in which the drains of an N-type MOS transistor and a P-type MOS transistor are formed as a dual layer diffusing structure to serve as the bases of PNP and NPN bipolar transistors, thereby integrally constructing the functional section and the driving section.
2. Description of the Art
Attempts to form different semiconductor devices such as bipolar transistors and CMOS transistors on the same semiconductor substrate have been made for a long time, and a Bi-CMOS semiconductor device has advantages due to a complementing effect such as the high speed and high power driving ability of the bipolar transistor, and the high density and the low power consumption of the CMOS transistor.
FIG. 1 is a circuit diagram of a Bi-CMOS transistor. In this drawing, the Bi-CMOS logic circuit is an inverter circuit for inverting signals supplied through its input terminal before outputting through its output terminal.
The Bi-CMOS logic circuit of FIG. 1 includes: a pair of first transistors, i.e. a P-type MOS transistor MP11 and an N type MOS transistor MN11, with their sources connected respectively to a power voltage Vcc and ground GND, with their gates receiving input signals IN, and with their common drain outputting first output signals OUT11;
a pair of second transistors, i.e. N-type MOS transistors MN13, MN12, with their gate terminals and the base of a bipolar transistor BN11 respectively receiving the input signals IN and first output signals OUT11 of the pair of the first transistors MP11, MN11 respectively, with the drain of one terminal and the source terminal connected respectively to an output terminal OUT and ground, and with the common source terminal and the drain terminal outputting second output signals OUT12; and
a pair of third transistors, i.e. NPN-type bipolar transistors BN11, BN12, with their bases receiving the first output signals OUT11 and the second output signals OUT12 of the second transistors including the N-type MOS transistors MN11, MN12, with their collectors connected respectively to the power voltage Vcc and ground, and with their common emitter outputting the final output signals OUT.
In the Bi-CMOS inverter circuit described above, if a high signal is supplied to input terminal IN, the N-type MOS transistor of the pair of the first transistors turns on, and the first output signal OUT11 shifts to a low state. At the same time, the N-type MOS transistor MN13 of the pair of the second transistors turns off, and the MOS transistor MN12 turns on, so that the output terminal OUT is pulled low.
If a low signal is supplied to the input terminal IN, the P-type MOS transistor MP11 of the pair of the first transistors turns on, and the first output signal OUT becomes high. When the N-type MOS transistor MN13 of the second transistors turns on, the second output signal OUT12 becomes low. Therefore, the NPN type bipolar transistor BN11 turns on, so that the final output signal OUT is high.
Bi-CMOS logic circuits have been applied to digital logic devices having a high power driving ability, and also applied to the static RAM (SRAM) and to gate array devices.
The Bi-CMOS logic circuit described above consists of four MOS transistors and two NPN-type bipolar transistors, with the MOS transistors serving as a functional section, while the bipolar transistors serve as a driving section. Thus, the Bi-CMOS logic circuit above described performs a two-step operation, i.e. inverting the input signals IN and transferring them to the output terminal OUT.
FIG. 2 is a vertical sectional view of the integrated circuit in which the Bi-CMOS logic circuit of FIG. 1 is formed on an epitaxial layer. That is, an NPN-type bipolar transistor is provided with a buried layer in such a form that: an n- epitaxial layer 22 which functions as a collector region is formed on buried layer 21, and a P base region 24 and an n+ emitter region 23 are formed on the n- epitaxial layer 22.
An N-type MOS transistor is formed with n+ source and drain regions 26, 27 on a P- epitaxial layer 25. A P-type MOS transistor is formed with an n- epitaxial layer 29 on an n+ buried layer 28, and P+ source and drain regions 30, 31 are formed on an n- epitaxial layer 29. Here, the n+ regions 32, 34 and the P+ region 33 are the regions for separating the devices.
Referring to the vertical sectional view of FIG. 2, an exemplary Bi-CMOS logic circuit comprises a functional section consisting of MOS transistors and a driving section consisting of bipolar transistors as described above. Further, they are formed by simply connecting N type and P type MOS transistors and NPN type bipolar transistors which are independent of one another.
Therefore, there are disadvantages in the above-described structure. First, in terms of the chip, an area as great as the area of the driving section including the bipolar transistors is required, and therefore the entire area of the chip may be increased. Further, since there is a two-stage signal path, the processing speed is slower than that of the inverter circuit which includes the pair of the first MOS transistors MP11, MN11.
Further, mutually independent N-type and P-type MOS transistors and NPN-type bipolar transistors are formed on an epitaxial layer of a semiconductor substrate through a large number of process steps and therefore, the process is complicated, and the number of the masks required becomes large, with the result that productivity is reduced.
In addition, in the case where the above Bi-CMOS logic circuit is used for obtaining signal products, the formation of vertical PNP transistors becomes impossible, and its application to the actual products is limited.