As a kind of integrated circuit (IC) memory devices, flash memories have the function of storing information in an electrically erasable and rewritable manner. For this reason, flash memories are widely used in electronic products including portable computers, cell phones and digital music players. A flash memory has many memory cells that are required to be so arranged as to be adapted to its operations. Each of the memory cells stores a single bit of data.
FIG. 1 schematically illustrates a memory cell of a conventional flash memory device, and FIG. 2 shows an array of memory cells of the conventional device. The flash memory device includes a plurality of the arrayed memory cells, as well as a plurality of bit lines (BL0, BL1, BL2, BL3, . . . , and BLm), a plurality of word lines (WL) and a plurality of control gates (e.g., CG0, CG1 and so forth), configured to select and provide drive signals to the individual memory cells. As shown in FIG. 1, each of the memory cells includes two memory bits, i.e., bits A and B, and a word line common to the two bits. Each of the memory bits includes a bit line and a control gate. While only two control gates are depicted in FIG. 2, i.e., CG0 and CG1, in practical, the memory may have more control gates (i.e., CG0, CG1, CG2, CG3, . . . , and CGn), as generally and commonly known in this art, and a detailed description thereof is therefore omitted herein.
Conventionally, in order to check whether a memory bit has been properly programmed, programming verification is generally carried out by reading the memory bit. This process is explained below with the programming of the memory bit A as an example. Typically, the memory bit A is programmed, concurrently with voltages of the control gate CG0, the word line WL and the control gate CG1 at 8.6 V, 1.5 V and 5V, respectively. In addition, after completion of the programming, the memory bit A is typically verified with the voltages of the control gate COO, the word line WL and the control gate CG1 at 0 V, 4.5 V and 5 V, respectively.
Referring to FIG. 3, in which the abscissa axis represents time t. The memory bit A is programmed at an instant t0, with the voltage of the control gate CG0 at 8.6 V and the voltage of the word line WL at 1.5 V. After the programming is completed at an instant t1, in order to enable the programming verification, it is needed to decrease the voltage on the control gate CG0 to 0 V and increase the voltage on the word line WL to 4.5V. However, due to latch-up and other effects, the decrease of the voltage at the control gate CG0 to 0 V takes a period of time tf and ends at an instant t2, which lead to elongation of the programming verification time. In addition, after the programming verification has ended at an instant t3, the voltage on the control gate CG0 is required to increase again to 8.6 V, with the voltage on the word line WL required to drop to 1.5 V, in order to allow the next programming cycle to start. Again, due to latch-up and other effects, the increase of the voltage on the control gate CG0 takes a period of time tr and ends at an instant t4. This makes an additional contribution to the elongation of the needed programming time.