1. Field of the Invention
The present invention relates to a data error detecting apparatus and a data error detecting method. The present invention particularly relates to a data error detecting apparatus and a data error detecting method in a single-chip microcomputer.
2. Description of the Related Art
Semiconductor devices called as microcomputers are installed in many commercially available apparatuses. The microcomputer has a microprocessor (CPU) for performing arithmetic and logic processing and a memory, which are generally formed as an integrated circuit (IC) on a single LSI chip.
For apparatuses with microcomputers installed, there are apparatuses that reliability is especially important. For example, electric components provided for vehicles require high reliability at all times. For this reason, the microcomputer provided to such an apparatus is designed based on a design concept called fail-safe, in order to measure unexpected trouble occurrence. Such a microcomputer is designed under the presumption that problems such as a failure, an operational mistake, and a design defect occur. In occurrence of the problem, the microcomputer has a function for keeping damage minimum. For example, when a CPU in a system reads out extremely important data, the fail-safe function instantaneously detects data abnormality resulting from device failure by always monitoring the data to prevent occurrence of false operations.
One fail-safe function is realized as a data error detecting apparatus in a microcomputer. A parity bit is added to important data, and a parity check is carried out when a CPU reads the data. If any abnormality is found, parity error interrupt is issued to inform data abnormality as soon as possible.
FIG. 1 is a block diagram showing a configuration of a conventional microcomputer 101 having a data error detecting apparatus. With reference to FIG. 1, the conventional microcomputer 101 includes a peripheral function 102, a data error detecting apparatus 103, and a CPU 104. Additionally, as shown in FIG. 1, the data error detecting apparatus 103 includes a parity bit adding circuit 105, a register 106, and a parity check circuit 107, which are connected through a bus 109.
In the conventional microcomputer 101, the parity bit adding circuit 105 adds a parity bit to a data in storage of the data, and writes the data with the added parity bit into the register 106. The parity check circuit 107 carries out parity check when the CPU 104 reads out the data from the register 106. The parity check circuit 107 determines whether there is any breaking of a data line and failure in a circuit for controlling the data, based on the result of the parity check. When it is determined that there is breaking of the data line or a failure in a circuit for controlling the data, the parity check circuit 107 issues a parity error interrupt, thereby detecting data abnormality.
As stated above, the conventional data error detecting apparatus 103 detects a failure in the microcomputer 101 by carrying out parity check to detect a data error corresponding to the data line (data line and the circuit for controlling the data). In general, the data error detecting apparatus 103 does not monitor any failure in the control circuit for writing the data into the register, breaking of a clock line, and so on. Therefore, the data error detecting apparatus 103 cannot know whether or not the data is originally right. In other words, the data error detecting apparatus 103 regards a currently retained data as a correct data and continues a reading operation even when data update is no longer possible.
FIG. 2 shows an operation of the data error detecting apparatus 103 in the conventional microcomputer 101 when there is occurrence of a failure in a control circuit writing data into a register or breaking of a clock line. With reference to FIG. 2, the following data are outputted from the peripheral function 102:
First time: 0111;
Second time: 0101;
Third time: 1110; and
Fourth time: 1010.
Also, it is shown that data update is not carried out due to the breaking of a line when the data should be updated from second data to third data. As shown in FIG. 2, the parity check circuit 107 reads non-update data when data update is not possible due to the breaking of the line. At this time, an error is not detected in the parity check since a consistency between a register value and a parity bit is kept. For this reason, the CPU reads an old data as a correct data, leading a delay to detection of trouble occurrence. Therefore, the conventional data error detecting apparatus 103 continues data readout without determination of a failure even if a read value is the same value for ten consecutive times.