1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to the formation of a dielectric interlayer between and over circuit elements including closely spaced lines, such as gate electrodes, polysilicon interconnect lines and the like.
2. Description of the Related Art
During the fabrication of integrated circuits, a large number of circuit elements are formed on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as micro-processors, storage chips and the like, MOS technology based on silicon is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost effectiveness. During the fabrication of complex integrated circuits using MOS technology, millions of transistors, i.e., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer, such as a silicon-based layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with a lightly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode that comprises a line-like portion and is formed above the channel region and separated therefrom by a thin insulating layer.
Typically, the circuit elements, such as the MOS transistors, capacitors, resistors and the like, are formed in a common layer, which will be referred to hereinafter as a device layer, whereas the “wiring,” i.e., the electrical connection of circuit elements according to the circuit design, may be accomplished only to a certain degree by means of polysilicon lines and the like within the device layer so that one or more additional “wiring” layers formed over the device layer may be required. These wiring layers include metal lines embedded into an appropriate dielectric material, such as silicon dioxide, silicon nitride and the like, or, in advanced devices, low-k materials having a permittivity of 3.0 or less are used. The metal lines and the surrounding dielectric material will be referred to hereinafter as a metallization layer. Between two stacked adjacent metallization layers and also between the device layer and the first metallization layer, respective dielectric interlayers are formed through which metal-filled openings are formed to establish the electrical connection between metal lines or between circuit elements and metal lines. In typical applications, the dielectric interlayer separating the device layer from the first metallization layer is essentially formed from silicon dioxide that is deposited above a dielectric etch stop layer by well-established plasma enhanced chemical vapor deposition (PECVD) techniques, which enable the formation of a smooth and dense silicon dioxide film with sufficient conformality at moderately high deposition rates. Due to the continuous device scaling resulting in gate lengths of MOS transistors on the order of 50 nm or less, the distances between neighboring circuit elements, such as polysilicon lines, gate electrodes and the like, are also reduced and have now reached in modern CPUs approximately 200 nm and less, which translates into approximately 100 nm or less for the space width between the densely packed polysilicon lines. It turns out, however, that the gap-fill capabilities of well-established high rate PECVD techniques for the deposition of silicon nitride, which is frequently used as material for the etch stop layer, and silicon dioxide, which is often used as interlayer dielectric, may no longer suffice to reliably form a dielectric interlayer, thereby requiring a fill technique providing enhanced fill capabilities as will be described in more detail with reference to FIGS. 1a-1b. 
In FIG. 1a, a semiconductor device 100 comprises a substrate 101 that may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate having formed thereon a device layer 102 including, for instance, a silicon-based layer 110, in and on which is formed a structure 103 that may comprise closely spaced polysilicon lines 104. The device layer 102 may represent a substantially crystalline silicon region in which and on which circuit elements, such as field effect transistors, capacitors and the like, are formed. The structure 103 may represent an area having a plurality of dense polysilicon lines, or the lines 104 may represent portions of gate electrodes of transistor elements. The lines 104 may have formed on sidewalls thereof corresponding spacer structures 105, as are typically used for forming gate electrode structures. The spacer structures 105 may include a plurality of spacers, such as an offset spacer 105A and one ore more “outer” spacers 105C, and a liner 105B that may act as an etch stop layer during an etch process for forming the respective spacers 105C. The structure 103 further comprises an etch stop layer 109, typically comprised of silicon nitride, that is formed over the device layer 102 to cover the layer 110 and the line structure 103. A silicon dioxide layer 107 is formed above the etch stop layer 109 so as to completely enclose the line structure 103.
A typical conventional process flow for forming the device 100 as shown in FIG. 1a may include the following processes. After fabrication processes to form circuit elements, such as transistors, capacitors and the line structure 103, which include well-established lithography, deposition, etch, implantation and other techniques, the etch stop layer 109 is formed, typically by PECVD, since PECVD of silicon nitride may be accomplished at moderately low temperatures of less than approximately 600° C., which is compatible with preceding manufacturing processes and materials, such as metal silicides and the like. In many conventional techniques, the etch stop layer 109 may be provided with a high intrinsic stress level so as to act as a strain-inducing source for creating a strain in an area 108 located below the lines 104. When the lines 104 represent gate electrodes, the area 108 may be considered as a channel region of a transistor, in which the induced strain may result in a modified charge carrier mobility. For example, for a standard crystallographic orientation of the semiconductor layer 110, that is, when the layer 110 represents a silicon-based material having a surface orientation (100) with the channel length oriented along a <110> direction, a compressive strain in the area 108 may result in an improvement of the hole mobility while a tensile strain may result in an improvement of the electron mobility. The enhanced charge carrier mobility thus directly translates into enhanced transistor performance with respect to current drive capability and operating speed. In order to selectively enhance the transistor performance, the etch stop layer 109 may be deposited on the basis of appropriately selected process parameters so as to obtain the desired degree and type of intrinsic stress. For example, silicon nitride may be deposited by PECVD with high tensile or compressive stress, depending on the deposition parameters. Moreover, well-established process sequences may be used to selectively form portions of the etch stop layer 109 with a different type of intrinsic stress above different transistors in order to enhance the performance of both N-type transistors and P-type transistors.
As previously discussed, the ongoing shrinkage of feature sizes also means that a distance between neighboring circuit elements, such as a distance 111 between the closely spaced lines 104, is reduced and may be as low as approximately 100 nm, or the distance 111 may even be as small as 30 nm and even less for CPUs of the 90 nm technology node. Hence, any deposition techniques for forming a dielectric layer for embedding the line structure 103 with open spaces therebetween have to meet the requirements of an appropriate fill capability so as to reliably and completely fill the empty spaces between the densely spaced lines 104. By means of PECVD process recipes for silicon nitride, the layer 109 may be deposited in a more or less conformal fashion with a thickness in the range of approximately 10-100 nm, wherein possibly different types of intrinsic stress may be provided above respective portions of the structure, thereby requiring sophisticated deposition and patterning strategies, in particular when the creation of voids 106a is to be suppressed.
Thereafter, the silicon dioxide layer 107 is deposited, which in less critical applications is typically done by PECVD on the basis of precursors TEOS (tetra-ethyl-ortho-silicate) and oxygen, since PECVD, contrary to thermal TEOS chemical vapor deposition (CVD), allows the deposition of silicon dioxide in a moderately conformal manner—yet with significantly less gap filling qualities compared to thermal CVD—with relatively high mechanical stability at temperatures below 600° C. at high deposition rates, which provides a high production yield.
However, with the distance 111 approaching approximately 30 nm and even less, it turns out that the fill capabilities of well-established PECVD techniques for depositing silicon dioxide having superior material characteristics on the basis of TEOS and oxygen may not be adequate to completely fill the empty spaces between the lines 104, thereby possibly creating voids 106b, which may lead to severe reliability concerns during the further processing of the semiconductor device 100, i.e., during the fabrication of contacts providing an electrical connection between individual elements of the structure 103 to a metallization level to be formed. Moreover, it should be noted that the silicon dioxide layer 107 has a certain topography caused by the underlying structure of the device layer 102, for instance, by the line structure 103, which may jeopardize subsequent manufacturing processes, such as a photolithography step for forming contact openings to underlying portions of circuit elements located in the layer 110 or on the lines 104. Consequently, a standard process flow requires that the silicon dioxide layer 107 be planarized, typically by chemical mechanical polishing (CMP), wherein excess material of the silicon dioxide layer 107 is removed by chemical and mechanical interaction with a slurry and a polishing pad so as to finally obtain a substantially planarized surface of the silicon dioxide layer 107. The CMP process itself is a highly complex process and requires sophisticated process recipes, which significantly depend on the characteristics of the silicon dioxide layer 107, such as density, mechanical stress, water contents and the like. Hence, a great deal of effort is required to develop corresponding process recipes for reliable and reproducible CMP processes for PECVD TEOS silicon dioxide, as this material is frequently used for a dielectric interlayer in silicon-based semiconductor devices and even in devices formed from other semiconductors.
For this reason, the dielectric layer 107 formed on the silicon nitride layer 109 may be deposited by a different deposition technique having a significantly enhanced gap filling capability to avoid the creation of the voids 106b. Hence, the silicon dioxide layer 107 may be formed by a thermal CVD process on the basis of TEOS and ozone, which generates a silicon dioxide film exhibiting excellent gap filling capabilities, that is, this deposition technique provides even a “flow”-like behavior, thereby reliably filling the empty spaces between the lines 104. In view of the film and deposition characteristics, the thermal CVD process is typically performed at significantly higher pressures compared to the plasma enhanced deposition technique, for example, in the range of 200-760 Torr, and is therefore denoted as sub-atmospheric chemical vapor deposition (SACVD). However, the material and process characteristics of the SACVD oxide may differ significantly from the PECVD oxide, as, for instance, the layer 107 formed by SACVD may tend to incorporate moisture more readily and also exhibit an increased rate of out-gassing compared to PECVD oxide. Furthermore, the deposition rate is lower, resulting in a reduced throughput. For these reasons, the layer 107 is provided as an intermediate material used as a gap fill material and thereafter a further silicon dioxide layer 107A may be deposited by PECVD to provide the desired deposition rate and enhanced material characteristics for at least the upper portion of the interlayer dielectric material. Thus, during the further processing, for instance the planarization of the interlayer dielectric material 107A, well-established process techniques may be used, while, however, the inferior material characteristics of the SACVD oxide may have an inverse effect on the overall reliability of the final interlayer dielectric material and thus on the structure 103.
FIG. 1b schematically illustrates the semiconductor device 100 according to another illustrative example in which the deposition process having the desired high gap filling capability may result in a high degree of non-uniformity during the further processing of the device 100. As shown, the device 100 may comprise the etch stop layer in the form of a first portion 109A having a high intrinsic stress level, for instance, a high compressive stress, while a second portion 109B may have a high intrinsic stress level of opposite behavior, such as a tensile stress. As previously explained, the lines 104 of the structure 103 may represent gate electrode structures of transistors, in which an appropriately selected type of strain in the respective channel regions 108 may provide enhanced transistor performance, as previously explained. When forming the portions 109A, 109B, respective deposition parameters may be adjusted, such as the deposition pressure, temperature, precursor flow rate, ion bombardment and the like, in order to obtain the desired high intrinsic stress levels. For example, according to well-established process recipes, a stressed dielectric material may be deposited in a highly conformal manner and a portion thereof may then be removed to obtain, for instance, the portion 109A. Thereafter, the dielectric material may be deposited with the opposite intrinsic stress level to that of the portion 109B while an unwanted part thereof may be removed from above the portion 109A, thereby obtaining the configuration as shown in FIG. 1b. 
During these manufacturing processes, the respective deposition parameters may also be selected so as to obtain a highly conformal deposition behavior in order to substantially avoid the creation of any voids between the densely spaced lines 104. Thereafter, the interlayer dielectric material 107 or a portion thereof may be deposited on the basis of the sub-atmospheric deposition process, as previously described, in order to ensure a reliable filling of the spaces between the lines 104. It turns out, however, that the growth rate during this deposition process may be different for a material having a high compressive stress and a tensile-stressed dielectric material, thereby resulting in a different layer thickness of the interlayer dielectric material 107 above the portions 109A, 109B. Consequently, during the further processing, for instance, when providing a further interlayer dielectric material, such as the material 107A, planarizing the resulting surface topography and the like, an increased degree of process non-uniformity may be encountered, which may also result in respective device non-uniformities, for instance, in view of a reduced planarity and the like.
Thus, although the enhanced gap filling capabilities of the sub-atmospheric deposition technique for silicon dioxide may be highly advantageous with respect to avoiding structure irregularities, in particular in densely packed line structures and gate electrodes, the inferior material characteristics, possibly in combination with deposition specific non-uniformities, may result in a reduced reliability and increased device irregularities, in particular for highly scaled semiconductor devices.
The present disclosure is directed to various techniques and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.