The present invention relates to an aparatus for restoring the cell storage regions of an ATM (Asynchronous Transfer Mode) switch having a common buffer structure, and a method therefor.
Generally, data is communicated as cells in an ATM network, and each of the cells consists of 53 bytes including a header of 5 bytes and a payload of 48 bytes. The header stores information of an address, a sender, etc., while the payload stores content data in order to distribute such data cells according to addresses, there may be employed an ATM switch having a common memory structure. The earlier ATM switch comprises a first multiplexer for multiplexing the cells with the header and content data separated, a common memory for storing the content data generated from the first multiplexer, a plurality of FIFO (first-in first-out) registers having the same number as the output ports to store the addresses for the content data by the headers, an idle addresses for the content data stored in the common memory, a second multiplexer for multiplexing the outputs of the FIFO registers, an address checker for checking the state of the addresses generated from the second multiplexer to store them into the idle address pool, and a demultiplexer for distributing the data output from the common memory among the output ports.
In operation, an ATM cell applied from a subscriber""s board or another system to the ATM switch is separated by the multiplexer into the header and payload. The header determines the output port for the content data stored in the payload of the ATM cell. The content data is stored into the common memory at an address designated by the idle address pool storing the idle addresses of the common memory. The header is stored into the corresponding FIFO register together with the address where the content data is stored into the common memory. Each register generates the address where the header and content data of the ATM cell are stored towards the multiplexer according to a read signal generated from a read time generator. Then the multiplexer generates towards the address checker the address of the common memory where the content data of the ATM cell, and towards the common memory a read signal to read the data of the address transferred to the address checker. The data read from the common memory is demultiplexed by the demultiplexer generated through respective output port. Meanwhile, the address checker checks if there is an error in the received addresses. The address checker cancels the erroneous address, or transfers the correct address to the idle address pool (IAP). The IAP goes on storing the addresses where the content data may be stored into the common memory.
In this case, whenever the address checker cancels erroneous address, there is reduced the number of the addresses where the content data may be stored into the common memory. Namely, although there has occurred to errors in the common memory, the addresses where the content data may be stored into the common memory are converted into the error state, thus making it impossible to use the storage regions of the erroneous addresses. If stored in the IAP, the erroneous address stored into the IAP may cause a loss of the data of the ATM cell. However, if allowed to continue, the number of erroneous addresses stored into the address checker from the registers through the multiplexer, the number of the addressses stored in the IAP becomes reduced accordingly. In order to restore the storage regions of the common memory, the operator must detach the board mounted with the switch from or reset the system to restore the IAP.
Takechi et al U.S. Pat. No. 5,513,191 discloses an Asynchronous Transfer Mode (ATM) Cell Error Processing System. In addition to an error detector, Takechi et al discloses an error editing unit. This error editing unit has the function of determining for each of the ATM cells, whether based on the respective and corresponding decision signals, a respective ATM cell should be discarded. Takechi et al does not indicate that the error editing unit restores error cells because of an erroneous address. What is needed is a method and apparatus for ATM networks for restoring cells having erroneous addresses.
It is an object of the present invention to provide an apparatus for restoring the idle addresses of the common memory in an ATM switch system without detaching or resetting the system.
It is yet another object of the present invention to provide a method and apparatus for an ATM network for restoring cells that have erroneous addresses.
According to one aspect of the present invention, an apparatus for restoring the cell data storage regions of the common memory in an asynchronous transfer mode (ATM) switch system, comprises a first multiplexer for multiplexing the cell data with the header and content data separated, a second multiplexer for multiplexing the addresses generated from a plurality of FIFO registers, an address checker for checking the addresses from the second multiplexer to generate a first and second address signals if the addresses are checked normal, an address memory storing all addresses of the common memory in error state to selectively convert the addresses into normal state according to the second address signal from the address checker, a controller for checking the address memory at predetermined intervals to restore an address stored in error state to a normal state, and an address multiplexer for generating an idle address to an IAP according to the first address signal and address restored signal.
According to another aspect of the present invention, an ATM switch system, which includes a common memory, an address checker, address multiplexer and controller for checking the address memory to restore the addresses of the common memory, is provided with a method for restoring the cell data storage regions of the common memory, which comprises the steps of causing the address checker to check during operation of the timer of the controller whether multiplexed read addresses are correct, writing corresponding storage regions of the address memory with correct addresses or canceling erroneous addresses according as the multiplexed read addresses are correct or not, sequentially checking the addresses of the address memory upon termination of the timer, and restoring the erroneous addresses checked in the previous step into correct state,