The reduction in memory cell size required for high density dynamic random access memories (DRAMs) results in a corresponding decrease in the area available for the storage node of the memory cell capacitor. Yet, design and operational parameters determine the minimum charge required for reliable operation of the memory cell despite decreasing cell area. Several techniques have been developed to increase the total charge capacity of the cell capacitor without significantly affecting the chip area. These include structures utilizing trench and stacked capacitors, as well as the utilization of new capacitor dielectric materials having higher dielectric constants.
One common material utilized for capacitor plates is conductively doped polysilicon. Such is utilized because of its compatibility with subsequent high temperature processing, good thermal expansion properties with SiO.sub.2, and its ability to be conformally deposited over widely varying topography.
As background, silicon occurs in crystalline and amorphous forms. Further, there are two basic types of crystalline silicon known as monocrystalline silicon and polycrystalline silicon. Polycrystalline silicon, polysilicon for short, is typically in situ or subsequently conductively doped to render the material conductive. Monocrystalline silicon is typically epitaxially grown from a silicon substrate. Silicon films deposited on dielectrics (such as SiO.sub.2 and Si.sub.3 N.sub.4) result in either an amorphous or polycrystalline phase. Specifically, it is generally known within the prior art that silicon deposited at wafer temperatures of less than approximately 580.degree. C. will result in an amorphous silicon layer, whereas silicon deposited at temperatures higher than about 580.degree. C. will result in a polycrystalline layer. The specific transition temperature depends on the source chemicals/precursors and the reactor used for the deposition.
The continued increase in circuit density continues to drive the thickness of the capacitor and gate layers in DRAM cells to smaller dimensions. Yet, the application of doped polysilicon films in DRAM memory cells demands high quality thin films. Historically, very thin polysilicon films (i.e., less than or equal to about 100 Angstroms) are fundamentally difficult to achieve, and the necessity of conductively doping such thin films is even more problematic. Generally, there are two basic approaches to doping thin film polysilicon, namely a) ion implantation, and b) in-situ doping during silicon film deposition. It has usually been easier to control the doping concentration through ion implantation than by in situ doping. However, ion implantation of dopants is typically limited to lower dopant concentrations, such as less than or equal to about 1.times.10.sup.16 atoms/cm.sup.3. In many applications, desired dopant concentrations to render polysilicon films suitably conductive exceeds 10.sup.20 atoms/cm.sup.3. Therefore, in situ doping (which is capable of much higher level doping without damage as compared to ion implantation) continues to be a desired form of processing for thin polysilicon films.
In-situ doping is commonly achieved by feeding a dopant gas to a chemical vapor deposition reactor simultaneously with feeding of a suitable silicon source gas. Example silicon source gases include silane (SiH.sub.4), disilane (Si.sub.2 H.sub.6), trisilane, and organosilane, while example conductivity enhancing dopant gases include phosphine (PH.sub.3), diborane (B.sub.2 H.sub.6), arsine (AsH.sub.3) and certain organometallic precursors. However, the resultant silicon film from the high level doping can suffer serious drawbacks. Such include the degradation of the interface of such film to the substrate, which in the presence of the dopant atoms can initiate local undesired strains in the resultant silicon film. Such local strains can further propagate to induce gathering of dopant atoms which can be particularly problematic the thinner the desired resultant polysilicon film. The situation is magnified where a polysilicon film is being provided over a SiO.sub.2 layer, which is typically the case. The result of the above mentioned situations can be a non-uniformity of the film thickness and in the sheet resistance from position to position and in wafer to wafer.
Accordingly, needs remain for producing improved polysilicon layers which are effectively in situ conductively doped during provision of the silicon on the substrate. Although the invention principally arose out of concerns specific to the art area of provision of thin doped polysilicon films, the artisan will appreciate applicability of the invention to thicker polysilicon films as well. The invention is limited only by the accompanying claims appropriately interpreted in accordance with the Doctrine Of Equivalents.