1. Field of the Invention
The present invention relates to a semiconductor device of a chip-on-chip structure that has a semiconductor chip bonded with other semiconductor chips thereon, and to a method for manufacturing same.
2. Description of Related Art
There are semiconductor devices increased in integration degree, including system-on-chips (SOCs) and multi-chip modules (MCMs). In the system-on-chip, the functions conventionally realized on a plurality of ICs are integrated on one semiconductor chip. Meanwhile, the multi-chip module is structured by a plurality of semiconductor chips arranged with density on a wiring board of glass-epoxy or the like. Each of them has multiple functions as one semiconductor device and can be size-reduced as compared to a combination of a plurality of semiconductor devices realizing the equivalent functions. Meanwhile, this reduces the wiring length in the overall, enabling high-speed transmission of signals.
However, the system-on-chip is complicated in manufacture process, requiring a huge amount of capital investment and hence high manufacture cost. Meanwhile, the multi-chip-module has a plurality of semiconductor chips mutually arranged side by side on a wiring board. Because these semiconductor chips are connected by wirings, the size is greater as compared to the system-on-chip and hence integration degree lowers.
On the other hand, there is a chip-on-chip structure as one form of an integration increased semiconductor device. The chip-on-chip-structured semiconductor device has a structure having a plurality of semiconductor chips that are oppositely placed for mutual connection. Such a semiconductor device is not configured with an integration of the functions conventionally realized on a plurality of ICs (semiconductor chips) as in the system-on-chip. Consequently, the manufacture process is not so complicated as that of the system-on-chip. Therefore, there is a merit to reduce the manufacturing cost.
The chip-on-chip-structured semiconductor devices include those having a plurality of small semiconductor chips (child chips) arranged side by side on one large semiconductor chip (parent chip). Such a semiconductor device, at a glance, is similar in structure to the multi-chip module having a plurality of semiconductor chips arranged side by side on a wiring board.
In the chip-on-chip-structured semiconductor device, however, the parent chip not only serves as a wiring board to connect between the child chips but also acts itself as a semiconductor chip having functional elements. This results in higher integration degree. On the other hand, the wiring formed on the parent chip, made by a semiconductor process, is by far finer than the wiring of a wiring board of a multi-chip-module. This allows the functional elements of the semiconductor chips (parent and child chips) to be connected at a short length of wiring, whereby signal transmission speed can be increased higher as compared to that of the multi-chip module.
The chip-on-chip-structured semiconductor devices include those that a child chip has, further, one or a plurality of child chips vertically superposed thereon. Namely, such a semiconductor device has a structure connected, on a parent chip, with one or a plurality of chip blocks each having one or a plurality of superposed semiconductor chips. This structure realizes a highly integrated semiconductor device.
In such a semiconductor device, however, the wiring between arbitrary two of the semiconductor chips is provided necessarily through a wiring plane (usually, active surface) of the parent chip, thereby increasing the mean wiring length. Namely, in the case the semiconductor chip is in a position close to the top end of the chip block (position distant from the parent chip), there is an increased length of wiring between that semiconductor chip and the parent chip. Consequently, signals could not be transmitted at sufficient high speed. Meanwhile, even if the wiring length is tried to decrease throughout the entire semiconductor device, there is encountered a low freedom in design, e.g. restriction in semiconductor chip arrangement.