Complementary Metal Oxide Semiconductor (CMOS) devices are dominated by n-channel (NMOS) and p-channel (PMOS) transistor structures. Various physical characteristics of each type of transistor determine the threshold voltage (Vt) that must be overcome to invert the channel region and cause a given transistor to conduct majority carriers (either by electrons movement in an NMOS device or by hole movement in a PMOS device).
One of the controlling physical characteristics is the work function of the material used to form the gate electrode of the transistor device. In semiconductor devices, such as a Dynamic Random Access Memory (DRAM) device, the transistor gates are predominantly made of polysilicon and an overlying layer of metal silicide, such as tungsten silicide and the gate dielectric is typically a high quality silicon oxide. The industry has moved to a transistor gate dielectric possessing a high dielectric constant of seven or greater (high-k dielectrics) for better leakage at given Effective Oxide Thickness (EOT). However, choosing a material with the appropriate work function as a gate electrode is still a challenge.
Studies have been conducted in one area of using high-k dielectric concerning Fermi-level pinning at the polysilicon/metal oxide interface of the transistor gate structure. Taking HfO2, for example, the hafnium and the polysilicon form Hafnium-Silicon bonds whose energy level in the band gap causes the Fermi-Level of the polysilicon to be pinned near the conduction band. With this scenario, using the HfO2 as the transistor gate dielectric in an NMOS device, a small shift in the transistor Vt, relative to N+ polysilicon on SiO2 will occur due to Hafnium-Silicon interface. However, applying this case in a PMOS device, a large shift in the transistor Vt will occur due to the Hafnium-Silicon bonds still pinning the Fermi-Level of the polysilicon near the conduction band.
Taking Al2O3, for example, the aluminum and the polysilicon form Aluminum-Silicon bonds that cause the Fermi-Level of the polysilicon to be pinned near the valence band due to the creation of the interface states that reside close to the valence band. With this scenario, using the Al2O3 as the transistor gate dielectric in a PMOS device, a small shift in the transistor Vt will occur due to P+ Aluminum-Silicon interface. However, applying this case in an NMOS device a large shift in the transistor Vt will occur due to the Aluminum-Silicon interface still having the Fermi-Level of the polysilicon being pinned near the conduction band and the transistor will not function in the desired range.
CMOS transistor devices that use the traditional polysilicon gate electrodes in combination with a metal oxide dielectric (high-k dielectric) must be fabricated such that the NMOS and PMOS devices will each possess a suitable transistor threshold voltage (Vt).
There is a need for the construction of CMOS devices using high-k dielectric materials for the transistor gate dielectric which will successfully be used to form both n-channel (NMOS) and p-channel (PMOS) transistors in semiconductor devices.