As a result of progress in current CMOS (complementary metal oxide semiconductor) technology, such as advances in 65-nm and 45-nm processes, in a programmable logic device (PLD), such as a field programmable gate arrays (FPGAs), have increased logic elements and I/O buffer (or pin) densities. Because simultaneous switching noise (SSN) is associated with the number of toggling I/O buffers, signal voltage level, and the switching rate of I/O buffers, it is important for FPGA users to be able to evaluate SSN performance in a “chip-package-board” environment. The SSN caused by FPGA output buffers is widely known as simultaneous switching output (SSO) noise and can be differentiated from the SSN caused by input buffers.
SSN in an FPGA system may be attributed to two primary factors: the mutual inductive coupling among switching I/O buffers and the impedance profile of a power distribution network (PDN) including die, package, and printed circuit board (PCB). In essence, reducing SSN is a design-cost issue. While designers can minimize the mutual inductive coupling by increasing the ratio of FPGA ground pins (or return-current pins) to I/O buffers, this approach sacrifices I/O buffer densities. Engineers can improve PDN performance by increasing on-die capacitance and adding on-package decoupling capacitors, but this approach increases costs.
Because FPGAs are programmable, they fit into a wide variety of user applications, so it is useful for designers to have a tool to determine their own SSN budget without additional costs. Ideally, this kind of tool requires instantaneous and accurate result predictions for various FPGA I/O buffer assignments and ideally would provide an optimum buffer assignment under certain design constraints. In the past, designers have constructed system-level, “SPICE-like” models to anticipate SSN in FPGA systems. These models are based on an understanding of SSN cause mechanisms and correlate well with bench measurements, helping IC and packaging designers improve designs.
However, these models are so complicated that they require signal/power integrity expertise to perform time-consuming, system-level simulations. It is cumbersome for all FPGA designers to perform the same level SSN analysis without considering their different design margins. Therefore, there is a need for a tool to help FPGA users execute a comprehensive FPGA SSN analysis in a short design cycle, though the invention claimed below has applicability to other applications beyond this particular application, as will become apparent from the following description and the drawings which accompany it.