1. Field of the Invention
The present invention relates to an energy recovery circuit and energy recovering method using the same, and more particularly, to an energy recovery circuit and energy recovering method using the same that is capable of reducing the number of components.
2. Description of the Related Art
Recently, there have been developed various flat panel display devices reduced in weight and bulk that is capable of eliminating disadvantages of a cathode ray tube (CRT). Such flat panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) and an electro-luminescence (EL) display, etc.
The PDP among them is a display device using gas discharge and has an advantage that it can be easily produced in a large sized panel. As shown in FIG. 1, a three electrode AC surface discharge PDP is typical as the PDP, wherein it has three electrodes and is driven by AC voltage.
Referring to FIG. 1, a discharge cell of a three-electrode, AC surface-discharge PDP includes a scan electrode 12Y and a sustain electrode 12Z provided on an upper substrate 10, and an address electrode 20X provided on a lower substrate 18.
On the upper substrate 10 provided, in parallel, with the scan electrode 12Y and the sustain electrode 12Z, an upper dielectric layer 14 and a protective film 16 are disposed. Wall charges generated upon plasma discharge are accumulated onto the upper dielectric layer 14. The protective film 16 prevents a damage of the upper dielectric layer 14 caused by a sputtering during the plasma discharge and improves the emission efficiency of secondary electrons. This protective film 16 is usually made of magnesium oxide (MgO).
A lower dielectric layer 22 and barrier ribs 24 are formed on the lower substrate 18 provided with the address electrode 20X. The surfaces of the lower dielectric layer 22 and the barrier ribs 24 are coated with a phosphorous material 26. The address electrode 20X is formed in a direction crossing the scan electrode 12Y and the sustain electrode 12Z. The barrier rib 24 is formed in parallel to the address electrode 20X to thereby prevent an ultraviolet ray and a visible light generated by a discharge from being leaked to the adjacent discharge cells.
The phosphorous material 26 is excited by an ultraviolet ray generated during the plasma discharge to generate any one of red, green and blue visible light rays. An inactive mixture gas for a gas discharge is injected into a discharge space defined between the upper and lower substrates 10 and 18 and the barrier rib 24.
The three electrode AC surface discharge PDP is divided into a plurality of subfields to be driven, wherein the light emission of numbers proportional to the weight of a video data is in progress in each subfield period, thereby performing the gray level display. The subfield is re-divided into an initialization period, an address period, a sustain period and an erasure period to be driven.
Herein, the initialization period is a period when uniform wall charges are formed in a discharge cell, the address period is a period when a selective address discharge is generated in accordance with the logical value of the video data, the sustain period is a period when a discharge is kept in the discharge cell where the address discharge is generated, and the erasure period is a period when the sustain discharge generated during the sustain period is eliminated.
In AC surface discharge PDP driven like this way, a high voltage of not less than several hundreds of volts is required in the address discharge and the sustain discharge thereof. Accordingly, an energy recovery circuit is used for minimizing a drive power required in the address discharge and the sustain discharge. The energy recovery circuit recovers the voltage between the scan electrode 12Y and the sustain electrode 12Z, and utilizes the recovered voltage as a drive voltage for the next discharge.
FIG. 2 is a diagram illustrating an energy recovery circuit installed for recovering a voltage of the sustain discharge.
Referring to FIG. 2, energy recovery circuits 30, 32 of the related art PDP are symmetrically installed with a panel capacitor Cp, therebetween. Herein, the panel capacitor Cp equivalently represents the capacitance which is formed between the scan electrode Y and the sustain electrode Z. In the energy recovery circuits, a first energy recovery circuit 30 supplies a sustain voltage to the scan electrode Y and a second energy recovery circuit 32 supplies the sustain voltage to the sustain electrode Z while it alternately operates with the first energy recovery circuit 30.
The composition of the energy recovery circuits 30, 32 of the related art PDP is described in reference with the first energy recovery circuit 30. The first energy recovery circuit 30 includes an inductor L connected between a panel capacitor Cp and a source capacitor Cs; first and third switches S1, S3 connected in parallel between the source capacitor Cs and the inductor L; and second and fourth switches S2, S4 connected in parallel between the panel capacitor Cp and the inductor L.
The second switch S2 is connected to a sustain voltage source Vs, and the fourth switch S4 is connected to a ground voltage source GND. The source capacitor Cs recovers the voltage charged into the panel capacitor upon the sustain discharge to be charged and re-supplies the charged voltage to the panel capacitor Cp. The voltage of Vs/2 corresponding to the half value of the sustain voltage source Vs is charged in the source capacitor Cs. The inductor L forms a resonance circuit together with the panel capacitor Cp. For this, the first to fourth switches S1 to S4 control the flow of electric current.
On the other hand, fifth and sixth diodes D5, D6 each installed between the first and third switches S1, S3 and the inductor L prevent the current from flowing in a reverse direction.
FIG. 3 is a timing diagram and waveform diagram representing an output waveform of a panel capacitor and an on/off timing of switches of the first energy recovery circuit.
Before a T1 period, assuming that a voltage of 0 volt is charged in the panel capacitor Cp and a voltage of Vs/2 is charged in the source capacitor Cs, the operation process is described in detail.
In the T1 period, a first switch S1 is turned on to form a current path from the source capacitor Cs to the panel capacitor Cp through the first switch S1 and the inductor L. Accordingly, the voltage of Vs/2 charged in the source capacitor Cs is supplied to the panel capacitor Cp. At this moment, the inductor L and the panel capacitor Cp forms a series resonance circuit, thus the sustain voltage Vs which is double of the voltage of the source capacitor Cs is charged in the panel capacitor Cp.
In a T2 period, the second switch S2 is turned on. When the second switch S2 is turned on, the voltage from the sustain voltage source Vs is supplied to the scan electrode Y. The voltage of the sustain voltage source Vs supplied to the scan electrode Y prevents the voltage of the panel capacitor Cp from dropping below the sustain voltage source Vs to cause the sustain discharge to be generated in a normal manner. On the other hand, the voltage of the panel capacitor Cp rises to the sustain voltage Vs in the t1 period, thus the drive power supplied from the outside to generated the sustain discharge is minimized.
In a T3 period, the first switch S1 is turned off. At this moment, the scan electrode Y maintains the voltage of the sustain voltage source Vs for the T3 period. In a T4 period, the second switch S2 is turned off and the third switch is turned on. When the third switch S3 is turned on, there is formed a current path from the panel capacitor Cp to the source capacitor Cs through the inductor L and the third switch S3 to recover the voltage charged in the panel capacitor Cp to the source capacitor Cs. At this moment, the source capacitor Cs is charged with the voltage of Vs/2.
In a T5 period, the third switch S3 is turned off and the fourth switch S4 is turned on. When the fourth switch S4 is turned on, a current path is formed between the panel capacitor Cp and the ground voltage source GND, thus the voltage of the panel capacitor Cp drops to 0V. In a T6 period, it maintains at the T5 state for a designated period. In fact, an AC drive pulse supplied to the scan electrode Y and the sustain electrode Z is obtained while the T1 to T6 periods are repeated periodically.
On the other hand, as shown in FIG. 4, the second energy recovery circuit 32 supplies the drive voltage to the panel capacitor Cp while alternately operating with the first energy recovery circuit 30. Accordingly, the panel capacitor Cp receives the sustain pulse voltage Vs that has a different polarity as shown in FIG. 4. In this way, the sustain pulse voltage Vs having the different polarities is supplied to the panel capacitor Cp, thus the sustain discharge is generated at the discharge cells.
However, since the first energy recovery circuit 30, installed at a side of the scan electrode Y, and the second energy recovery circuit 32, installed at a side of the sustain electrode Z, are respectively operated, lots of circuit components such as switching device are required. Accordingly, there is a problem that a manufacturing cost thereof becomes increased. In addition, if lots of circuit components are installed to the energy recovery circuits 30, 32, then a large amount of power consumption becomes wasted.