The subject matter of the present application relates to microelectronic assemblies and fabrication methods therefor, and more particularly to the structure of and fabrication method for a multilayer interconnect element.
There is a current need for microelectronic interconnect elements to provide greater wiring density. Microelectronic interconnect elements include, for example, package substrates used for direct interconnection to microelectronic elements such as semiconductor chips. Other types of interconnect elements include circuit panels which can be directly connected to microelectronic elements or indirectly, such as through a package substrate of a packaged chip. The need is felt especially to improve the density of metal wiring lines, e.g., conductive traces on a dielectric element, as measured by the pitch of the metal lines and minimum spacing between adjacent metal lines.
Some package substrates and circuit panels have multiple dielectric layers and metal wiring lines provided on some or all of the dielectric layers. A multi-layer wiring substrate 12 according to the prior art, referred to as “High Density Interconnect” is illustrated in FIGS. 1-2. The substrate 12 has a plurality of dielectric layers, two such dielectric layers 14, and 14′ being shown in FIG. 1. As shown therein, each of a plurality of metal lines 10, 10′ and 10″ has approximately the same width w and thickness t.
One limitation of the substrate shown in FIG. 1 is a vertical distance factor d by which each of the metal lines 10, 10′ and 10″ is spaced from closest adjacent metal lines (of lines 10, 10′ and 10″) in a vertical direction 30, i.e., the direction of the thickness of each metal line. Each of the metal lines 10 and 10′ is supported by a respective dielectric layer 14 or 14′. As illustrated in FIG. 1, the metal lines 10′ and 10″ are separated in a vertical direction 30 of the substrate 12 by a distance d through a portion of the thickness td of the dielectric layer 14′. A minimum vertical spacing constrains the metal wiring density within the volume occupied by metal lines and dielectric layers 14 of the substrate 12. As further shown in FIG. 2, each of a plurality of traces 10″ adjacent to each other in a horizontal direction 40 has width w and is spaced from the adjacent trace 10″ by a spacing s. Thus, a minimum pitch of the traces 10″, measured between the centers of adjacent traces, is the value of w+s. A minimum spacing s is required for manufacturability of the traces. For example, the traces 10″ of FIG. 2 may be formed subtractively by etching a metal layer. In such case, a constraint in the form of a minimum spacing s is imposed by the resolution of the photolithographic exposure process used to define an etch mask, e.g., a photoresist mask, and the need for the etching process to reliably produce separated traces from a metal layer having a given thickness t. In another example, when the traces 10″ of FIG. 2 are formed in an additive manner by electroplating, a minimum spacing s is imposed by the resolution of the photolithographic exposure process used to define a plating mask, e.g., a photoresist mask, the electroplating process used to form the lines, and the requirements of processes employed after the plating process, e.g., photoresist mask removal. Accordingly, in a HDI implementation, the resulting multi-layer substrate 12 has adjacent traces 10″ spaced apart in a horizontal direction 40 of the substrate by a minimum spacing s. Also, a minimum distance d separates traces of adjacent dielectric layers in a vertical direction 30 of the substrate.