The present invention relates generally to improved circuits and methods for generating clock signals by multiplying a fundamental clock frequency, and more particularly to substantially increasing the accuracy of the multiplied clock frequency above the accuracy achievable in the prior art.
“Prior Art” FIG. 1 shows a clock generation circuit 1 which includes a typical relaxation oscillator 2 that is believed to be representative of the closest prior art. Relatively “tight” frequency specifications are required for some integrated circuits including internal clock generators based on internal relaxation oscillators. For example, relatively tight frequency specifications are required for internal clock signals in integrated circuits which are designed to communicate over an RS232 interface. In the manufacture of such an integrated circuit, it may be desirable to perform a laser trimming operation on certain resistors in the integrated circuit at room temperature to produce a desired relaxation oscillator frequency. However, after the laser trimming operation the relaxation oscillator frequency nevertheless may vary significantly over a specified temperature range (e.g., minus 50 degrees Centigrade to plus 125 degrees Centigrade). There may be a need to ensure that the laser trimming operation at room temperature results in the relaxation oscillator frequency being within the specified range over the entire allowable temperature range. This has been difficult to achieve for internal clock generation circuits based on prior art relaxation oscillator circuits.
Referring to FIG. 1, clock generator circuit 1 includes a relaxation oscillator 2 including a current source 11 which supplies a current I1 to the sources of P-channel transistors M1 and M2, the gates of which are controlled by a logic circuit 10. The drain of transistor M1 is connected by conductor 3 to capacitor C1, switch S2, and a comparator 13. The drain of transistor M2 is connected to capacitor C2, switch S1, and comparator 12. Comparators 12 and 13 receive a reference voltage Vref that is produced by a current source Iref flowing through a resistor having a resistance R1.
The outputs of comparators 12 and 13 are connected to inputs of an OR gate 14, the output of which clocks a flip-flop 15. The output 16 of flip-flop 15 is connected to the inputs of a inverter 18 and a non-inverting buffer 20 and to an input of logic circuit 10. Logic circuit 10 produces clock signals φ1, φ2, φ1, and φ2 in response to the signal produced by flip-flop 15, where φ2 can be equal to φ1 and φ1 can be equal to φ2.
If transistor M1 is on, transistor M2 is off, switch S1 is closed, and switch S2 is open, causing the current I1 to flow through transistor M1 and gradually charge up capacitor C1, producing the ramp section “A1” of V3 as shown during which the clock signal CLK in the timing diagram of FIG. 2 is at the level P1. When V3 exceeds reference voltage Vref, the output 36 of comparator 12 switches from a “0” level to a “1” level after a propagation delay Tprop, causing a “1” level to be produced at the output of OR gate 14. This causes flip-flop 15 to change state, causing buffer 20 to produce the low level N1 of clock signal CLK in FIG. 2 and causing logic circuit 10 to switch φ1 to a high level and to switch φ2 to a low level
That turns transistor M1 off, turns transistor M2 on, closes switch S2, and opens switch S1. The closing of switch S2 discharges capacitor C1, producing transition B1 of voltage signal V3. The current I1 flows through transistor M2 and gradually charges up capacitor C2, producing the ramp section “A2” of signal V4. The operation continues similarly to that described above, and when V4 exceeds reference voltage Vref, the output 37 of comparator 13 switches from a “0” level to a “1” level, and a “1” level then produced at the output of OR gate 14 causes flip-flop 15 to change state, reversing the levels of φ1 and φ2. This discharges capacitor C2 to ground, causing transition “B2” of voltage signal V4 and also causing the transition of clock signal CLK to the level P2. As the foregoing operation is repeated, the level of CLK changes and the levels of φ1 and φ2 change each time the ramp portions of V3 and V4 exceed Vref.
The period of oscillation TOSC of relaxation oscillator 2 is given by the expressionTOSC=(2*C*Vref)/I1+Tprop.   Eq. (1)
The value of Tprop has a great influence on the ability of relaxation oscillator 2 to operate at very high clock frequencies (e.g., several hundred megahertz) over a typical expected temperature range (e.g., −50 degrees Centigrade to +125 degrees Centigrade) because Tprop can vary significantly over that range.
For clock signal periods requiring an accuracy of less than, for example 2%, over a predetermined typical temperature range and power supply range, the variance of the propagation delay Tprop can limit the maximum clock frequency obtainable. For example, a deviation of 1 nanosecond in Tprop can produce a corresponding 1% deviation in a 10 MHz nominal frequency of relaxation oscillator 2 and hence in the frequency of CLK. However, since the propagation delay Tprop is not totally dependent on the frequency of relaxation oscillator 2, if in this example relaxation oscillator 2 oscillates at a frequency higher than 10 MHz, any deviation of the propagation delay Tprop over the expected temperature range results in a correspondingly greater percentage deviation than 1% in the corresponding period of relaxation oscillator 2.
Thus, there is an unmet need for a clock generator circuit based on a relaxation oscillator that provides increased accuracy of the generated clock signal.
There also is an unmet need for a circuit and technique for multiplying the frequency of a signal produced by a relaxation oscillator without having to increase the current supplied by a current source in the relaxation oscillator or varying the value of capacitors such as capacitors C1 and C2 in FIG. 1.
There also is an unmet need for a circuit and technique for multiplying the frequency of a signal based on a clock signal derived from a relaxation oscillator without having to increase the frequency of the relaxation oscillator.
There also is an unmet need for an analog technique and circuit for multiplying an output signal produced by a relaxation oscillator to obtain a signal having a frequency which is a multiple of the frequency of the output signal produced by the relaxation oscillator without reducing overall circuit performance of the relaxation oscillator and the analog multiplying circuit over an expected temperature range.
There also is an unmet need for an analog technique and circuit for multiplying an output signal produced by a relaxation oscillator to obtain a signal having a frequency which is a multiple of the frequency of the output signal produced by the relaxation oscillator without unacceptably limiting the maximum achievable frequency of the multiplied output signal.
There also is an unmet need for an analog technique for obtaining signals within certain phase specifications or time delay specifications of a fundamental relaxation oscillator output.