The semiconductor industry is rapidly decreasing the dimensions and increasing the density of electronic circuitry and electronic components in microelectronic devices, silicon chips, liquid crystal displays, MEMS (Micro Electro Mechanical Systems), printed wiring boards, and the like. The integrated circuits within them are being layered or stacked with constantly decreasing thicknesses of the insulating layer between each circuitry layer and smaller and smaller feature sizes. As the feature sizes have shrunk, patterns have become smaller, and device performance parameters tighter and more robust. As a result, various issues which heretofore could be tolerated, can no longer be tolerated or have become more of an issue due to the smaller feature size.
In the production of advanced integrated circuits, to minimize problems associated with the higher density and to optimize performance, both high k and low k insulators, and assorted barrier layer materials have been employed.
Titanium nitride (TiN) is utilized for semiconductor devices, liquid crystal displays, MEMS (Micro Electro Mechanical Systems), printed wiring boards and the like, and as ground layers and cap layers for precious metal, aluminum (Al) and copper (Cu) wiring. In semiconductor devices, it may be used as a barrier metal, a hard mask, or a gate metal.
In the construction of devices for these applications, TiN frequently needs to be etched. In the various types of uses and device environments of TiN, other layers are in contact with or otherwise exposed at the same time as the TiN is etched. Highly selective etching of the TiN in the presence of these other materials (e.g. metal conductors, dielectric, and hard marks) is mandatory for device yield and long life. The etching process for the TiN may be a plasma etching process. However, using a plasma etching process on the TiN layer may cause damage to either or both the gate insulating layer and the semiconductor substrate. In addition, the etching process may remove a portion of the semiconductor substrate by etching the gate insulating layer exposed by the gate electrode. The electrical characteristics of the transistor may be negatively impacted. To avoid such etching damage, additional protective device manufacturing steps may be employed, but at significant cost.
Wet etching methods for TiN are known. Such methods may include use of etchants containing hydrofluoric acid in combination with other reagents. However, the selectivity with silicon based dielectrics and metals (e.g., Al) is not sufficient and other exposed metals in the device may also undergo corrosion or etching.
Hydrogen peroxide/ammonia/EDTA (ethylenediaminetetraacetic acid) mixtures and hydrogen peroxide/phosphate mixtures have been disclosed as means of overcoming the acidic HF based etchants. However, the etch rates obtained are insufficient.
Thus, there is a need for TiN etching solutions that have high etch rates, but have low etch and corrosion rates for other semiconductor materials which are exposed or in contact with the TiN during the etching process.