1. Field of the Invention
The present invention relates to non-volatile memory cells. More particularly, the present invention relates to push-pull non-volatile memory cells and to arrays of such memory cells.
2. The Prior Art
Push-pull non-volatile memory cells are known in the art. FIG. 1 is a schematic diagram shows an illustrative prior-art push-pull non-volatile memory cell. The memory cell includes a p-channel non-volatile memory transistor connected in series with an n-channel non-volatile transistor. The p-channel non-volatile memory transistor and the n-channel non-volatile transistor may be fabricated as floating-gate flash transistors or may be fabricated using other known non-volatile transistor technologies.
The memory cell shown in FIG. 1 may be used to drive a switch transistor such as the n-channel transistor shown with its gate coupled to the common drain connections of the p-channel non-volatile memory transistor and the n-channel non-volatile transistor. Such a memory cell arrangement may be used to form programmable circuit connections in a programmable integrated circuit such as a field programmable gate array (FPGA) integrated circuit.
The memory cell shown in FIG. 1 may be programmed into one of two states. In the first state, the n-channel non-volatile transistor is turned on and the p-channel non-volatile transistor is turned off. In this state, the gate of the n-channel switch transistor is grounded, turning it off. In the second state, the p-channel non-volatile transistor is turned on and the n-channel non-volatile transistor is turned off. In this state, the gate of the n-channel switch transistor is at approximately VDD, turning it on.
In the case of flash non-volatile memory transistors, the p-channel non-volatile transistor is programmed by placing a negative voltage, such as −4v, on the source of the p-channel non-volatile transistor, placing a positive voltage such as 8.5v on its gate, while its bulk is biased at a voltage such as 1.2v. The gate and source of the p-channel non-volatile transistor are biased at 0v during this procedure.
The n-channel flash non-volatile transistor is programmed by placing a voltage such as 8.5v, on its gate, and placing a voltage such as 4.5v on its source. The gate of the p-channel non-volatile transistor is biased at a voltage such as −3.3v and its source is biased at a voltage such as 0v during this procedure.