The present embodiments relate to the operation of a hardware accelerator. More specifically, the embodiments relate to hardware accelerator memory address translation fault resolution.
Hardware accelerators are often included in processor-based systems such as computer systems to perform specific operations efficiently in hardware rather than in software. Traditionally, a hardware accelerator performs complex parallel transformations on input data, which can enhance performance of a computer based system. Additionally, in some cases, the hardware acceleration can be more power-efficient than performing the same tasks in software. Power efficiency can be even greater if the hardware accelerators are incorporated on the same semiconductor substrate (“on-chip”) as the processors. Particularly, integrating hardware accelerators onto multi-core chips such as chip multiprocessors and/or chip multithreaded processors can be efficient, because the accelerator can be shared among the cores/threads.
Typically, a privileged layer of software in the computer system manages access to the hardware accelerator. The access management enables the hardware to be shared in a distributed manner so that various threads/cores have the opportunity to take advantage of the hardware accelerator. Additionally, the access management enables the hardware accelerator to be shared in a secure manner (e.g. preventing one thread/core from disrupting, and/or corrupting, the operation issued by another thread/core to the hardware accelerator).