A flash memory is typically configured by an array of multiplicity of memory cells aligned in the word line direction and the bit line direction. A memory cell is configured by a stacked gate structure in which a floating gate electrode, interelectrode insulating film, and control gate electrode are stacked in the listed sequence. As flash memory increases its storage capacity through densification, features within the memory cell are packed in tighter dimensions. Dimensions typically affected by the densification are widths of floating gate electrodes and element isolation trenches. For instance, narrowing of the element isolation trenches makes formation of control gate electrode difficult since polysilicon film, typically employed as a control gate electrode material, needs to be filled in the narrowed gaps between the neighboring floating gate electrodes which are further narrowed by the presence of the interelectrode insulating film. One solution to this problem may be thinning the interelectrode insulating film. However, as the memory cells become smaller, relatively higher electric field is applied to the floating gate electrode through the interelectrode insulating film during programming. This is because downscaling of a memory cell often results in a floating gate electrode with a sharp tip. Because electric field tends to concentrate at the tips, edges, and corners, the downscaled floating gate having relatively larger percentage of such high electric field regions are subjected to larger amount of high electric field leakage current which prevents the memory cell from being programmed to the desired threshold.
The interelectrode insulating film is often configured by an ONO structure in which a silicon nitride film is interposed between the top silicon oxide film and the bottom silicon oxide film. The problem encountered in such ONO structure is electron traps within the silicon nitride film, which typically occurs in the aforementioned high-field regions located at the top portion of the floating gate electrode where electric field concentration occurs. The trapped electrons, when detrapped, degrades the charge retainability of the interelectrode insulating film.
It is further known that thinner interelectrode insulating film results in shorter endurance, in other words, reduced voltage tolerance. The interelectrode insulating film is not only used in the gate structures in the memory cell region but also in the elements for driving device operation provided in the peripheral circuit region such as capacitors for generating voltage. In applications where the device is expected to run extensively, enhanced endurance, i.e. voltage tolerance of the interelectrode insulating film is an important factor in achieving a long running device. However, a thinner interelectrode insulating film, which is advantageous in terms of gap fill capability, degrades the endurance/voltage tolerance of the interelectrode insulating film, and thus, will subject the elements in the peripheral circuit region and consequently the entire device to greater risk of malfunctioning. It is thus, required to further improve the insulativity of the interelectrode insulating film.