1. Field of the Invention
The invention relates to a polished semiconductor wafer for the fabrication of electronic components, having a front surface and a back surface and an edge which forms the periphery of the semiconductor wafer and is part of a profiled boundary of the semiconductor wafer. The semiconductor wafer has a polished front surface, into which the components are formed. Strict demands are imposed on the flatness of the front surface, and these demands are extraordinarily high if it is intended to accommodate electronic structures with line widths of 0.1 μm or below (≦0.1 μm technology). To enable the maximum number of circuits of this type to be integrated, it is necessary to ensure the required flatness to as close as possible to the edge of the front surface.
2. The Prior Art
Most efforts to increase the flatness of the side faces of the semiconductor wafer in general and the front surface in particular have consistently been concentrated on substeps involved in the production of a semiconductor wafer which influence the flatness. These substeps include in particular steps such as the lapping and/or grinding and polishing of one or both side faces. At least one polishing step, carried out as a single-side or double-side polishing step, is virtually always carried out. As is made clear by European Patent No. EP 1119031 A2, however, it is also possible for substeps such as the etching of the side faces to have an effect on the flatness, in particular on the flatness in the edge region of the side faces. A semiconductor wafer is usually etched prior to a first polishing step, in order to remove damage from the surface left behind by a previous shaping operation, for example by grinding and/or lapping of the semiconductor wafer. The abovementioned patent application states that a raised portion in the edge region of the polished front surface of the semiconductor wafer is likely if the semiconductor wafer is exposed to a flow of a liquid etchant which is guided onto the boundary of the semiconductor wafer during etching. To avoid this effect, a shield can be positioned in front of the boundary of the semiconductor wafer preventing the etchant from being able to strike the boundary of the semiconductor wafer directly. The document does not give any indications with regard to any potential for targeted influencing of the flatness of a semiconductor wafer in its edge region, in particular with a view to making the semiconductor wafer suitable for the ≦0.1 μm technology.