1) Field of the Invention
The present invention relates to a timing analysis apparatus, a timing analysis method, a timing analysis program, and a recording medium for static timing analysis of circuits arranged and wired on a large-scale integration (LSI) chip.
2) Description of the Related Art
In the conventional technology, in static timing analysis (STA) of a LSI, on chip variation (OCV) of delay time (or delay) in a LSI chip arising from temperature, voltage, and manufacturing process is used.
In concrete, a variation on this LSI chip is quantified, and is used as a variation value. For example, by multiplying delay time of a path to input to a sync flip-flop (FF), a path to input to a source FF, and a path between both the FFs by a variation value, timing analysis is carried out. It is necessary to make this variation value a value in which all the variations of supposed delay time are taken into consideration. Among them, with regard to manufacturing process variations, a distance between circuit elements that cause a variation value is set with a supposed maximum range as a reference. Meanwhile, with regard to voltage variations, a potential difference owing to a power source decline is set as a variation value. Furthermore, with regard to temperature variations, a temperature difference between circuits is set as a variation value.
A timing analysis method according to the conventional technology is explained. FIG. 1 is a flowchart showing a timing analysis method according to the conventional technology. Macro cells and logic circuits are arranged and wired on a LSI chip (step S1101). From layout data obtained from this arrangement and wiring, wire resistance values and inter-wire capacity values are extracted (step S1102). Then, by use of the layout data, wire resistance values, and inter-wire capacity values, a delay time is calculated (step S1103). By use of this calculated delay time and the variation values mentioned above, timing analysis is carried out (step S1104). Finally, an error obtained by the result of timing analysis is corrected (step S1105).
In fully custom LSI designs, a delay characteristic analysis method is disclosed where prompt and precise delay characteristic analysis is enabled, when conditions concerning circuit designs and signal transmissions are changed partially, by making the most of analysis results on circuits before the change (see, for example, Patent Application Laid-Open Publication No. 2002-215710). Furthermore, a method to attain both a shortened development period and a low electricity consumption that are in relations of a trade-off is disclosed (see, for example, Patent Application Laid-Open Publication No. 2002-312410).
However, in the methods according to the conventional technology, variation values used in timing analysis are values in which all the variations of supposed delay time, i.e., variations of voltage, temperature, and manufacturing process, should be taken into consideration, therefore, the values are used as constant ones to any of circuits.
Accordingly, when the range of a circuit that causes variation values is narrow (for example, the distance between a sync FF and a source FF is short), variations of manufacturing process and voltage become excessive, and as a result a useless margin occurs. The useless margin makes it difficult to converge the timing, and also increase the size of LSI chips, which has been a problem with the conventional technology.