It is a recognized fact that electronic devices, and especially BJT transistors, should be operated within safe limits for proper operation and without the risk of becoming damaged.
In many applications, such devices are operated far from the limiting conditions; however, for some of them, such as power devices, it is extremely important to bring component performances to the limit, but without overtaking the limiting conditions which would result in the device being damaged.
Shown on a graph in FIG. 1 are the working points in safe limit conditions of a power transistor (FBSOA (Forward Base Safe Operating Area) curve). In particular, on the graph, a set of collector current curves are plotted against the collector-emitter voltage for a same power device as the duration of the base current varies.
As follows from this FIG. 1, if the base current is of the pulsed type, as the duration of the individual pulses decreases (100 msec, 1 msec, 100 .mu.sec, 10 m sec, 1 .mu.sec), the area included by the FBSOA curve (curves I, II, III, IV, V) increases.
In order to limit the maximum dissipatable power during operation, protection circuits are often associated with such devices. FIG. 1 also shows a curve (VI) of possible operation of a linear protection circuit according to the prior art.
A first embodiment of that protection circuit is shown in FIG. 2, which depicts an electronic regulator circuit for driving a power device Q0. That regulator circuit comprises a first driving portion 1 and a second protection portion 2.
That first driving portion 1 is realized by a first amplifier OP1 with a first input terminal I1 connected to a voltage reference Vref, a second input terminal I2 connected to a voltage divider Vd, and an output terminal O1 connected to a control terminal 6 of the device Q0.
The second protection portion 2 comprises a second amplifier OP2 having a feedback resistor Rs connected between its input terminals I3 and I4.
In particular, the amplifier OP2 is an operational stage with an inherent offset voltage Voffset.
The input I3 is connected to a terminal 4 of the power device Q0 through a series connection of a Zener diode Dz and a resistor R. An output terminal O2 of the second amplifier OP2 is connected to the terminal 6 of the device Q0.
One end of the resistor Rs is also connected to a terminal 5 of the device Q0, the other end being connected to the divider Vd.
In the circuit architecture of FIG. 2, the current flowing in the output load goes through the resistor Rs and is picked up at the input terminals of the amplifier OP2.
So long as the voltage picked up across the resistor Rs is lower than the voltage Voffset of the amplifier OP2, the output voltage of the power device Q0 will be regulated through the driving portion 1.
Upon the load current exceeding the maximum current for which the transistor Q0 has been designed, the increased voltage Voffset will set the protection circuit to operate.
A more detailed description of the operation of a regulator circuit of that type is found in U.S. Pat. No. 5,714,905, which is incorporated herein by reference.
While being in many ways advantageous, this solution has several drawbacks.
As the fabrication process varies, the operation curve of the protection circuit SOA can vary to the point of overtaking the FBSOA curve. To prevent the power device from operating outside the safe operation range, the power device is provided oversize such that the SOA curve is contained within the FBSOA curve with ample margin.
A first disadvantage of this solution is that the capacity for integration of the power device is altered for the worse, because its being oversize involves the use of a larger amount of silicon for its formation. This obviously results in an undesired cost increase.
A second disadvantage of this construction is the appearance of the so-called latch-down phenomenon in the regulator circuit. With high values of the power device working voltage, the protection circuit heavily limits the current delivered from Q0, which may create difficulties in initially charging the capacitive loads provided downstream of the circuit.