1. Field of the Invention
The present invention relates to a semiconductor package and a fabrication method thereof, and more particularly to semiconductor packages each with an extra plurality of electrical connecting points and a fabrication method thereof.
2. Description of the Prior Art
Owing to the trend toward multi-function, high-performance, and high-speed electronic products, semiconductor manufacturers nowadays are devoted to research and development of semiconductor devices integrated with multiple chips or packages with a view to meeting the requirement for today's electronic products.
Referring to FIG. 1, U.S. Pat. No. 5,222,014 discloses a stack structure of a semiconductor package, and a method for fabricating the stack structure of a semiconductor package involves providing a first ball grid array (BGA) substrate 11 having bonding pads 110 disposed thereon, mounting a semiconductor chip 10 on the first BGA substrate 11, forming an encapsulant 13 on the first BGA substrate 11 such that the encapsulant 13 encapsulates the semiconductor chip 10, mounting and electrically connecting a second BGA substrate 12 (which has been packaged like the first BGA substrate 11) to the bonding pads 110 via solder balls 14.
However, in the stack structure of the semiconductor package described above, the number of the bonding pads 110 electrically connecting the second BGA substrate 12 with the first BGA substrate 11 is restricted by the size of the encapsulant 13, thus limiting the type of semiconductor packages to be stacked and the number of I/O connections that can be formed, such that the type of semiconductor packages to be stacked and I/O connection layout on the second BGA substrate 12 would be restricted by the bonding pad 110 arrangement on the first BGA substrate 11. Moreover, due to the height limitation of the solder balls 14, the height of the encapsulant 13 disposed on the first BGA substrate 11 must be minimized (typically below 0.3 mm), which increases the difficulty of fabrication. Other stack structures of semiconductor packages such as that disclosed in U.S. Pat. Nos. 6,025,648 and 6,828,665 also experienced the same problem.
Besides, in accordance with the foregoing known stack structures of semiconductor packages, electrical connecting points for forming electrical connections with external devices rely totally on the circuits on the substrate surface, while the encapsulant which occupies the majority of space in a package, however, is incapable of providing extra electrical connecting points, such that not only the overall electrical performance of the semiconductor product cannot be improved, the usage of the package would also be limited.
Thus, there is an urgent need to develop a semiconductor package and a method for fabricating the same, for providing an extra plurality of electrical connecting points, thereby solving the problem of package usage limitation, improving the electrical performance of electronic products and overcoming the stacking limitation in terms of size and type of semiconductor packages and the number of I/O connections.