1. Field of the Invention
The present invention generally relates to a Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) made on semiconductor on insulator (SOI) substrates. In particular, the invention relates to MOSFETs with a recessed channel film in an SOI layer. The recessed channel film forms an abrupt junction.
2. Description of Related Art
U.S. Pat. No. 7,041,538 B2, issued on May 9, 2006 to Ieong et al., describes a high performance CMOS device on an SOI substrate with a gate recessed into an SOI layer and ion implanted source/drain regions with halo and extension implants.
U.S. Pat. No. 6,939,751 B2 issued on Sep. 6, 2005 to Zhu et al. describes a raised source drain field effect devices with a channel recessed into a silicon germanium film located above a SOI layer.
U.S. Pat. No. 7,652,332 B2 issued on Jan. 26, 2010 to Cartier et al. describes extremely thin silicon on insulator transistor with raised source/drain, high dielectric constant (high-k) oxide and metal gate.
U.S. Pat. No. 7,429,769 B2 issued on Sep. 30, 2008 to Diaz et al. describes a recessed channel field effect transistor (FET).
In a paper entitled “Extremely Thin SOI (ETSOI) CMOS with Record Low Variability for Low Power System-on-Chip Applications,” by K. Cheng et al. published in 2009 IEEE International Electron Device Meeting, Dec. 7-9, 2009 a method of making CMOS transistors on ETSOI substrates is disclosed.
In a paper entitled “Ultra-thin SOI replacement gate CMOS with ALD TaN/high-k gate stack,” by B. Doris et al. in IEEE VLSI-TSA International Symposium on VLSI Technology, Apr. 25-27, 2005 a device built on an ETSOI substrate using a replacement gate substrate is disclosed.
In a presentation by B. Doris et al., entitled “FD SOI for Low Power CMOS,” 2009, available at http://www.soiconsortium.org/pdf/fullydepletedsoi/FD%20SOI%20for%20Low%20Power%20CMOS.pdf, a summary of device performance challenges and possible solutions are reviewed. Some possible solutions include various devices made using ETSOI substrates.
In a paper entitled “CMOS Transitions to 22 and 15 nm,” by D. Lammers published Jan. 1, 2010, in Semiconductor International describes device structures and possible methods of manufacture for FETs at ground rules less than or equal to 22 nm. Possible devices include planar MOSFETs on ETSOI substrates.
In a paper entitled “Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering,” by J. Kavalieros et al. available at http://download.intel.com/technology/silicon/tri-gate_paper_VLSI—0606.pdf, the authors describe a non-planar MOSFET on SOI with recessed source and drains.