A system on a chip (SOC) generally includes at least one processing core, which generally is operatively coupled to a level 2 (L2) memory cache. A cache in a SOC typically needs to fetch, from a memory, current instructions and current data (as and when required by the processing core, in case such current instructions and current data are, for example, not already cached in the cache and/or is dirty), as well as pre-fetch instructions and pre-fetch data corresponding to instructions and data that are likely to be needed, by the processing core, in a forthcoming operation. In conventional SOC architectures each of the current instructions, current data, pre-fetch instructions and pre-fetch data are communicated between the processor and the cache, such as an L2 cache, via dedicated ports.
The description in this section is related art, and does not necessarily include information disclosed under 37 C.F.R. 1.97 and 37 C.F.R. 1.98. Unless specifically denoted as prior art, it is not admitted that any description of related art is prior art.