1. Field of the Invention
The present invention relates to a numerical simulation in a real time system and particularly to a high speed processing apparatus which is suitable for computing a system having sparse and irregular characteristics such as an electronic circuit, a logic circuit, a structure analysis, a tidal current computation or the like.
2. Description of the Prior Art
As a computer for rapidly performing a numerical computation, there exists super computers and array processors, however they have the following problems.
(1) In case of accomplishing a computation in a sparse or irregular system as described above, the efficiency is remarkably reduced because of shortened vector length. PA1 (2) It is difficult to increase the degree of parallel processing so as to speed up the computation. PA1 (i) The kinds of nodes are limited to the four rules of arithmetic. PA1 (ii) There exist no loops from a view of a graph. PA1 (iii) There is no case of converting a value of the input terminal (a.sub.11, a.sub.31, . . . in FIG. 1(a)). PA1 (i) The input data are assembled, that is, the operation-executed nodes are discriminated. PA1 (ii) The operations of these first nodes (only the four rules of arithmetic) are executed. PA1 (iii) The nodes to which the outputs of the first nodes are searched and the processing results of the first node are set as the input data of the nodes to which the results of the first nodes are output.
Though there are some realized devices in a data flow machine (Mizoguchi, et al.: Image processing processor TIP-1, Shingakugiho: EC81-59), there is a limit to the speedup because the data reading section is series-connected.