1. Field of the Invention
The present invention relates to the field of displaying technology, and in particular to a method for manufacturing a TFT (Thin-Film Transistor) backplane and a structure of a TFT backplane.
2. The Related Arts
Flat panel displays have a variety of advantages, such as thin device body, low power consumption, and being free of radiation, and are thus widely used. Currently available flat panel displays generally include liquid crystal displays (LCDs) and organic light emitting displays (OLEDs)
Organic light emitting displays (OLEDs) have a variety of superior properties, such as being self-luminous, requiring no backlighting, high contrast, reduced thickness, wide view angle, fast response, applicability to flexible panels, wide range of operation temperature, and having simple structure and manufacturing process, and are regarded as emerging technology of the next generation flat panel displays.
The TFTs are a vital constituent part of the flat panel displays. Since the TFTs can be formed on a glass substrate or a plastic substrate, they are commonly used as switch devices and driver devices for devices, such as LCDs, OLEDs, and electro-phoretic displays (EPDs).
Oxide semiconductor TFT technology is the most attention-attracting technology currently. The oxide semiconductors have a relatively high electron mobility and, compared to low-temperature poly-silicon, the oxide semiconductors have a simple manufacturing process and high compatibility to amorphous silicon manufacturing processes, being applicable to the fields of LCDs, OLEDs, and flexible displays, and are also compatible to high generation manufacturing lines, being applicable to large-, medium-, and small-sized displays, making them possess excellent prosperous future of development.
A conventional structure of an oxide semiconductor TFT backplane that is considered relatively mature is one that includes an etch stop layer. As shown in FIGS. 1-10, a method for manufacturing a conventional oxide semiconductor TFT backplane comprises the following steps:
Step 1: providing a substrate 100, forming a first metal layer on the substrate 100, and applying a photolithographic operation to patternize the first metal layer so as to form a gate terminal 200 on one side portion of the substrate 100 and a first metal electrode M1 on an opposite side portion of the substrate 100;
Step 2: forming a gate insulation layer 300 on the gate terminal 200, the first metal electrode M1, and the substrate 100 and applying a photolithographic operation to patternize the gate insulation layer 300 to form a gate insulation layer via 310 for exposing a portion of the gate terminal 200;
Step 3: forming a film on the gate insulation layer 300 and applying a photolithographic operation to patternize the film to form an island-like oxide semiconductor layer 400;
Step 4: forming an etch stop layer 500 on the oxide semiconductor layer 400 and the gate insulation layer 300 and applying a photolithographic operation to patternize the etch stop layer 500 to a plurality of etch stop layer vias 510 for exposing portions of the oxide semiconductor layer 400;
Step 5: forming a second metal layer on the etch stop layer 500 and applying a photolithographic operation to patternize the second metal layer to form source/drain terminals 600 on one side portion of the substrate 100 and a second metal electrode M2 on an opposite portion of the substrate 100, wherein the source/drain terminals 600 fill up the plurality of etch stop layer vias 510 to connect to the oxide semiconductor layer 400 and the source/drain terminals 600 fill up the gate insulation layer via 310 to connect to the gate terminal 200;
wherein the first metal electrode M1, the second metal electrode M2, and a portion of the gate insulation layer 300 and a portion of the etch stop layer 500 that are sandwiched between the first and second metal electrodes M1, M2 form a storage capacitor C;
Step 6: forming a passivation protection layer 700 on the source/drain terminals 600 and the second metal electrode M2, followed by patternizing by applying a photolithographic operation;
Step 7: forming a planarization layer 800 on the passivation protection layer 700, followed by patternizing by applying a photolithographic operation;
Step 8: forming a pixel electrode layer 900 on the planarization layer 800, followed by patternizing by applying a photolithographic operation;
Step 9: forming a pixel definition layer 1000 on the pixel electrode layer 900 and the planarization layer 800, followed by patternizing by applying a photolithographic operation; and
Step 10: forming a spacer pillar 1100 on the pixel definition layer 1000.
The conventional oxide semiconductor TFT backplane manufacturing method suffers certain problems, which are generally presented in three aspects: The first one is that the manufacture of the oxide semiconductor TFT backplane requires ten processes of photolithographic operation, wherein the manufacture of the etch stop layer 500 requires a complete process of photolithographic operation (including the steps of film forming, yellow light, etching, and stripping). This leads to an extended operation process, a reduced manufacturing efficiency, and an increase of manufacturing cost, and the more the manufacturing steps, the more the yield problems there will be. The second one is that the gate insulation layer 300, the oxide semiconductor layer 400, and the etch stop layer 500 are not formed consecutively so that the interfaces of the oxide semiconductor layer 400 and with respect to the other two layers may be readily contaminated by etching solutions and stripping solutions, leading to a potential risk of deterioration of the performance of the TFT. The third one is that the storage capacitor C is formed of the first metal electrode M1, the second metal electrode M2, and a portion of the gate insulation layer 300 and a portion of the etch stop layer 500 sandwiched between the first and second metal electrodes M1, M2 and due to an additional thickness resulting from the presence of the etch stop layer 500, the storage capacitor C requires an enlarged area, which causes reduction of aperture ratio.
Thus, it is desired to improve the conventional method to eliminate the problems existing therein.