The background is presented herein only by way of example to multichip modules (MCMs), which are multimaterial, multilayered devices that are becoming one of the electronics packaging industry's most preferred components for a variety of aerospace, computer, military, and telecommunications applications. MCMs are replacing or reducing the complexity of printed circuit boards, thus enhancing product efficiency and reliability.
MCMs and other multimaterial, multilayered electronic devices for packaging single chips such as ball grid arrays (BGA), pin grid arrays (PGA), etc; circuit boards; and hybrid and semiconductor microcircuits typically include separate component layers of metal and an organic dielectric and/or reinforcement materials. The standard metal component layer(s) may contain aluminum, copper, gold, molybdenum, nickel, palladium, platinum, silver, titanium, or tungsten, or combinations thereof. These layers typically have a depth or thickness of about 9 to 36 .mu.m (where 7.8.times.10.sup.-3 kg of metal equals a thickness of about 9 .mu.m), but may be thinner or as large as 72 .mu.m. A standard organic dielectric layer may include bismaleimide triazine (BT), cardboard, cyanate esters, epoxies, phenolics, polyimides, or polytetrafluorethylene (PTFE). These layers typically have a depth of about 50 to 400 .mu.m. A standard reinforcement component "layer" may include fiber matts or dispersed particles of aramid fibers, ceramics, glass, or Kevlar.TM. woven or dispersed into the organic dielectric layer to reinforce it. These reinforcements typically have a diameter or thickness of about 1 to 10 .mu.m. Stacks having several layers of metal, dielectric, and reinforcement material may be larger than 2 mm.
MCMs present, however, new manufacturing obstacles because they require finer lines and smaller high aspect ratio interconnections or vias and use a variety of new materials. The term "vias" is used herein generally to refer to complete through-holes or incomplete holes called "blind vias." A high aspect ratio implies a depth-to-width comparison that is typically from about one to five. After the vias are formed, they are typically plated with a metal to form interconnections between metal circuits in the multilayered electronic devices. The ability to increase the packaging density of MCM-L, MCM-L/D, PCMCIA, and laminate BGA devices to fulfill present and future technology requirements is now limited by existing processes for forming interconnections between layers. More detail concerning the industry trend and its obstacles may be found in "The Interconnect Challenge: Filling Small, High Aspect Ratio Contact Holes," Semiconductor International, Vol. 17, No. 9, Aug. 1994, at 57-64.
The laminate circuit board industry has explored a variety of multistep processes for forming interconnections. The most common interconnection formation process includes via formation, precleaning, surface activation, preplating, plating, and homogenization or planarization. Via formation is generally achieved by mechanical drilling or punching, but has also been accomplished to a limited extent by excimer and CO.sub.2 laser ablation. The precleaning or desmearing process typically entails a chemical process employing an acid or permanganate solution.
The surface activation process generally entails seeding the internal wall surfaces with palladium to form a preliminary conductive layer or a metal adhesive layer. The palladium can be directly deposited as ions from an alkaline solution or in the form of an organometallic coating, the organics of which are subsequently chemically removed. These processes seem to work in the range of about 150 to 250 .mu.m. Other techniques, such as carbonizing the internal wall surfaces of the via to make them sufficiently conductive for certain preplating processes, are sometimes employed.
Electroless chemical plating is the most common method for preplating the internal wall surfaces of vias. Electroless chemical plating employs a liquid solution of electroless copper to chemically react with and deposit on the internal wall surface of the via a few nanometers thickness of metal. This type of copper plating reduces the resistance across the outer layers of the multilayered electronic device to about 10 ohms (for thousands of vias). The chemical reaction generates a gas byproduct (hydrogen and oxygen) having a volume that is approximately six times the volume of a via. The electronic device is typically agitated in solution to exchange gas and reactant inside the via. At via diameters smaller than about 250 .mu.m, the gas and reactant exchange becomes economically impractical and generally infeasible, resulting in poor coverage of the via internal wall surface.
A typical electroless copper process line includes approximately 30 tanks, each containing over 100 gallons of chemical solutions, that are sequentially connected together by a conveyor handling system. The process includes precleaning, surface activation, and electroless copper deposition steps. The entire process line is typically 60-100 feet long, and the equipment costs approximately $250,000. The various chemical solutions may cost up to about $300/gallon.
Electrochemical plating is the industry-preferred method for plating vias. The electrochemical plating process places a charge across the outer layers of the via while the electronic device is submersed in a plating bath of a copper solution. The copper ions are galvanically attracted to and cling to the via internal wall surfaces. This process is limited by its speed and the access that the electrolyte solution has to the internal wall surfaces. Thus, the vias are not totally filled. A variety of other methods for creating electrical interconnects adopted from the hybrid circuit and semiconductor industries, some of which are described below, have also been used for preplating and then followed by electrochemical plating.
Plating has also been accomplished by application of a variety of organometallic solid- or liquid-phase compositions. The compositions, such as conductive pastes, are either squeezed into the vias or the vias are submersed in the baths of the compositions. The organics are then chemically or thermally removed or displaced with more or other metals. This process generally creates porous interconnections.
Physical vapor deposition (PVD), a process primarily used for creating thin layers on horizontal surfaces, has also been adapted for plating vias. A PVD process converts the plating material into the vapor phase, transports the vapor across a region of reduced pressure, and condenses the material onto the horizontal surface to form a thin film. The two common types of PVD, evaporative PVD and sputtering, employ the addition of heat or the physical dislodgement of surface atoms by momentum transfer, respectively, to convert the material to the vapor phase. The processes necessitate a protective mask to safeguard the top surface of the device prior to via plating or an etching step to remove undesirable metal after via plating. These processes also cause the formation of "keyhole voids." These voids occur because vias typically have aspect ratios greater than one, so the top via rim accumulates metal and becomes sealed before the entire via volume is filled. In some cases, especially whenever the aspect ratio is high, the vias may inadvertently be sealed prior to the sufficient coating of the entire internal wall surfaces.
The chemical vapor deposition (CVD) process, on the other hand, reacts chemical vapors of desired concentrations with the heated surface of the device to form a thin film. Like the other vapor deposition processes, CVD necessitates device surface protection when the process is utilized as a via plating technique.
Postplating homogenation or planarization are typically employed to diffuse metals into porously filled vias or to reduce the voids or diminish the lips formed at via rims. These processes are generally thermal.
Some researchers, particularly in the semiconductor industry, have investigated using laser technology to assist in some of the steps for forming a conductive interconnect. For example, lasers have been used to modify the surface in preparation for a metallization step, a process similar to that employed in copy machine technology. The surface is charred with, for example, a CO.sub.2 laser and then exposed to some standard thin film technique that preferentially responds to the laser- activated sites. Lasers have also been used to enhance chemical vapor deposition where the laser acts to heat the via site and prepare the area for the chemical diffusion of the metals in the vapor (pyrolytic decomposition). This method is described in U.S. Pat. No. 5,060,595 of Ziv et al., but this method works only with certain Si and Si oxide combinations that exhibit high absorption at 532 nm (frequency-doubled YAG).
A variety of laser metal deposition techniques has also been explored for use in direct imaging of circuits as described by Liu in "Laser Metal Deposition for High-Density Interconnect," Optics & Photonics News, June 1992, at 10-14. Such laser-activated chemical deposition processes are generally characterized as either photolytic or pyrolitic. These processes are typically followed by chemical electroplating techniques.
Laser photolytic processes employ laser light to directly cause chemical changes in organo-metallic solutions such that the metals dissociate from the organics and cling to the internal wall surfaces of the vias. These photolytic processes generally result, however, in plating speeds that are too slow for commercial use.
Laser pyrolytic processes employ heat from a laser source to break apart organo-metallic molecules applied as thin films to electronic devices. The heat releases the organic molecules and leaves the metals. A variety of metals have been deposited in this manner.
Another method uses an XeCl excimer laser at 308 nm to planarize a top aluminum layer causing melted aluminum to flow into vias creating interconnections as described by Bachmann in "Physical Concepts of Materials for Novel Optoelectronic Device Applications," SPIE, Vol. 1361, 1990, at 500-11.
Excimer lasers have also been employed to enhance PVD sputtering processes at very low power and repetition rates to produce thin films of several materials. Further details concerning this technique can be found in "Pulsed Laser Deposition of Thin Metallic Alloys," Appl. Phys. Lett., Vol. 62, No. 19, May 10, 1993, by Krebs and Bremert.
Skilled persons will appreciate that the cleaning, preplating, and planarizing techniques described above are all relatively slow batch processes, requiring expensive baths, masks, or postprocessing. In addition to being expensive and largely inefficient, most of the plating techniques require both a cleansing as well as a preplating process. The industry needs, therefore, faster and more efficient via plating and/or preplating processes that minimize the tooling as well as the steps for plating vias comprising a wide variety of sizes and internal wall materials.