1. Field of the Invention
The present invention relates generally to the design of integrated circuits and more particularly to sense amplifiers.
2. Description of the Background Art
Many systems on an integrated circuit are designed to respond differently depending upon whether their input voltages are considered HIGH or LOW. Sometimes, an input voltage must be modified to conform to the HIGH or LOW state (e.g., during the period when the input voltage transitions between states). Sense amplifiers are circuits that detect a small voltage differential and increase or decrease the voltage to a level required by the system. An example of a system that utilizes sense amplifiers is a computer memory circuit. Information stored in the memory cells of a memory chip using sense amplifiers can be retrieved much faster than from a memory chip without sense amplifiers.
As shown in FIG. 1, a common static random access memory (SRAM) configuration generally designated 100 includes an array 105 of memory cells 110. Each memory cell 110 is connected to a word line 115, a bit line B 120, and a complement of the bit line, B 145. The memory cells 110 connected to each of the word lines 115 define a memory cell array row 125, and the memory cells connected to each of the bit line B 120 and a corresponding complement of the bit line B 145 define a memory cell array column 130. Each memory cell 110 stores information in the form of a voltage charge representing a logic value of LOW or HIGH. A voltage level equal to V.sub.DD represents the logic value of HIGH and V.sub.SS represents the logic value of LOW.
Bit lines B 120 and B 145 are connected to an equalization and precharge circuit 150. The precharge component of the equalization and precharge circuit 150 initially charges bit lines B 120 and B 145 to the voltage level of V.sub.DD. The equalization component of the equalization and precharge circuit 150 ensures that the voltages on bit lines B 120, .nu..sub.B, and B 145, .nu..sub.B, are initially at the same level.
The word lines 115 are connected to a row decoder 155. When a memory cell 110' is accessed, the row decoder 155 selects and changes the voltage of a word line 115' corresponding to memory cell 110'. A changed voltage signal (e.g., LOW to HIGH) from the word line 115' allows memory cell 110' to communicate with bits lines B 120' and B 145'. If memory cell 110' stores a logic value of HIGH, then .nu..sub.B will remain at HIGH and .nu..sub.B will decrease to LOW. If memory cell 110' stores a logic value of LOW, then .nu..sub.B will decrease to LOW and .nu..sub.B will remain at HIGH.
Bit lines B 120 and B 145 are connected to a sense amplifier 160 which detects and amplifies the difference in voltage between .nu..sub.B and .nu..sub.B. Depending on the difference between .nu..sub.B and .nu..sub.B, the sense amplifier 160 will output either V.sub.DD or V.sub.SS.
Connected to the sense amplifier 160 is a column decoder 165. The column decoder 165, like the row decoder 155, includes a combination of logic circuits that select a logic signal from either one or a set of the memory cell array columns 130 for final output from SRAM 100.
The prior art described above suffers from a number of limitations. To store more information on a single memory chip, smaller memory cells are used. Smaller memory cells, however, use smaller transistors, which have less driving capability, resulting in a longer time for .nu..sub.B and .nu..sub.B to reach distinct HIGH or LOW voltage levels. To reduce the time required to read a memory cell, sense amplifiers are used to quickly detect the small voltage difference between .nu..sub.B and .nu..sub.B without having to wait for .nu..sub.B and .nu..sub.B to reach definite HIGH or LOW voltage levels. However, when .nu..sub.B and .nu..sub.B reach definite HIGH or LOW voltage levels before the operation of the sense amplifier, the operation of the sense amplifier is not required and consumes unnecessary power.
What is needed is a sense amplifier design that overcomes the shortfalls of the sense amplifier designs known in the art.