1. Field of the Invention
The present invention relates generally to the field of information storage devices, and, more particularly, the present invention relates to an improved system and method for allocating memory.
2. Description of the Related Art
In processor-controlled devices, a memory, whether dynamic or static RAMs (Random Access Memory) is provided for the storage of programming instructions and data. In order to write data to memory areas of the memory or read data from the individual memory areas, the processor generates a memory area address and passes it to a memory controller known as an SRAM or DRAM controller to those of ordinary skill in the art. The memory controller forwards this memory area address via address lines to address inputs of the memory. The memory area addresses generally represent a binary number, the smallest addressable memory area usually comprising one or more bytes.
The memory is formed by a plurality of insertion regions, into which in each case at least one memory module, usually an integrated memory chip, can be inserted. The insertion regions, which are typically plug-in devices, are frequently configured such that memory modules or memory chips having different storage capacities can be inserted. For example, memory modules with one or four Kbytes or Mbytes are typically used. Consequently, because of the various insertion regions, optimum matching of the storage capacity of the memory to the respective application is possible. This means that the memory modules must be inserted into the address-conforming insertion regions as a function of their storage capacity in order to ensure error-free memory addressing. Incorrect information regarding the storage capacity and the insertion regions leads to significant disturbances in the processor system and possibly to its failure.