1. Field of the Invention
The present invention relates to flash EPROM memory technology, and more particularly to unique cell structure having extended floating gates to improve the coupling ratio between the control gate, floating gate, and source or drain of the transistor cell.
2. Description of Related Art
Flash EPROMs are a growing class of non-volatile storage integrated circuits. These flash EPROMs have the capability of electrically erasing, programming, and reading a memory cell in the chip. The memory cell in a flash EPROM is formed using so-called floating gate transistors, in which the data is stored in a cell by charging or discharging the floating gate. The floating gate is a conductive material, typically made of polysilicon, which is insulated from the channel of the transistor by a thin layer of oxide, or other insulating material, and insulated from the control gate or word line of the transistor by a second layer of insulating material.
Data is stored in the memory cell by charging or discharging the floating gate. The floating gate is charged through a Fowler-Nordheim tunneling mechanism by establishing a large, positive voltage between the control gate and source or drain. Alternatively, an avalanche mechanism may be used by applying potentials to induce high energy electrons in the channel of the cell which are injected across the insulator to the floating gate. The voltage on the control gate is divided by the so-called coupling ratio of the cell, resulting in a first voltage between the control gate and floating gate, and a second voltage between the floating gate and the source or drain. With a 50% coupling ratio, half of the voltage applied to the control gate appears across the oxide between the floating gate and the source or drain. This voltage between the floating gate and the source or drain causes electrons to tunnel or be injected into the floating gate through the thin insulator. When the floating gate is charged, the threshold voltage for causing the memory cell to conduct is increased above the voltage applied to the word line during a read operation. Thus, when a charged cell is addressed during a read operation, the cell does not conduct. The non-conducting state of the cell can be interpreted as a binary 1 or a zero, depending on the polarity of the sensing circuit.
The floating gate is discharged to establish the opposite memory state. This function is typically carried out by F-N tunneling between the floating gate and the source or drain of the transistor, or between the floating gate and the substrate. For instance, the floating gate may be discharged through the source by establishing a large, positive voltage from the source to the gate, while the drain is left at a floating potential.
The high voltages used to charge and discharge a floating gate place significant design restrictions on flash memory devices, particularly as the cell dimensions and process specifications are reduced in size. Thus, the coupling ratio for the memory cells becomes a critical design parameter.
One way of increasing the coupling ratio, is to increase the surface area of the floating gate between the control gate and the floating gate. This can be accomplished by extending the floating gate over the source or drain regions, such as described in Bergemont, et al., U.S. Pat. No. 5,012,446.
One approach to extending the floating gate is described in Kume, et al., "A 1.28 .mu.m.sup.2 Contactless Memory Cell Technology for a 3 V-only 64 Mbit EEPROM", IEDM 92, pp. 991-993; Hisamune, et al., "A High Capacitive-Coupling Ratio (HiCR) Cell for 3 V-only 64 Mbit and Future Flash Memories", IEDM 93, pp. 19-22.
All of these prior art designs for extending the floating are relatively complicated process technologies.
Accordingly, an improved process for extending the floating gate to increase the coupling ratio of flash EPROM, and a circuit for utilizing such structure, is desirable.