1. Field of the Invention
The present invention relates to a structure of a complementary metal insulator semiconductor device (CMIS) using a metal gate electrode, and a manufacturing method thereof.
2. Description of the Related Art
In order to meet the requirements for an effective reduction in the thickness of a gate insulating film associated with increasing performance and increasing integration of semiconductor devices, it will be necessary in the future to introduce the technique for a metal gate electrode and a high dielectric (high-k) gate insulating film. To obtain proper performance in a CMIS transistor (cMISFET) using the metal/high-k gate insulating film, an effective work function φeff of a metal gate material needs to be about 3.9 to 4.3 eV for an n-channel MIS transistor (nMISFET), and about 4.8 to 5.2 eV for a p-channel MIS transistor (pMISFET).
However, a metal having a low work function suitable for the n-channel MIS transistor is generally not stable in a heat treatment step necessary for a transistor formation process, and cannot have a φeff of about 3.9 to 4.3 eV suitable for the n-channel MIS transistor especially on the high-k gate insulating film after the formation of the transistor. Therefore, insertion of a layer containing groups IIA and IIIA metallic elements into a gate stack structure is necessary, which is effective as a technique of reducing Vth in the n-channel MISFET.
On the other hand, the layer containing the groups IIA and IIIA metallic elements increases Vth in the p-channel MIS transistor, so that there is a need for a step of detaching the layer containing the groups IIA and IIIA metallic elements in the p-channel MISFET region.
However, the layer containing the groups IIA and IIIA metallic elements is generally low in resistance to an etching solution (e.g., refer to H. Y. Yu et al., Tech. VLSI, P18(2007)). Accordingly, there has been concern that the layer containing the groups IIA and IIIA metallic elements in the n-channel MISFET region may also be detached in the step of detaching the layer containing the groups IIA and IIIA metallic elements in the p-channel MISFET region or in an associated mask detaching step, and proper Vth modulation may not be obtained in the n-channel MISFET region.
Thus, there has been desired the realization of a CMIS structure which inhibits the effects of the Vth modulation by the layer containing the groups IIA and IIIA metallic elements in the p-channel MISFET region without performing the step of detaching the layer containing the groups IIA and IIIA metallic elements formed in the p-channel MISFET region.