The present invention relates to a charge-pump circuit outputting voltage fluctuation within a step or power source voltage Vdd and a control method thereof, particularly a control method of a charge-pump circuit capable of normal charging pump operation removing influence of a parasitic diode following to a charge transfer device.
The charge-pump circuit developed by Dicson generates higher voltage than power source voltage Vdd of an LSI chip by voltage fluctuation of each pumping packet connecting plural stages of the pumping packet in series. For example, it is used for generating voltage for program/erase of flash memories.
However, the conventional charge-pump circuit carries out voltage fluctuation with a step of the power source voltage Vdd, and a circuit capable of carrying out voltage fluctuation with lower voltage step than the Vdd was not yet proposed. So, the inventor has already proposed a charge-pump circuit capable of carrying out voltage fluctuation with lower voltage step than the Vdd and improving efficiency xcex7 of the circuit (U.S. patent application No. 09/732,944 filed on Dec. 8, 2000).
The outline thereof will be described below. FIG. 10 to FIG. 12 are circuit diagrams showing a structure of an operation of xe2x88x920.5 Vdd voltage fluctuation charge-pump circuit. The charge-pump circuit generates voltage of voltage fluctuation of xe2x88x920.5 Vdd to earth voltage (0 V).
In FIG. 10, diodes D1 and D2 are connected in series as charge transfer devices. To a cathode of the diode D1, earth voltage (0 V) is supplied. The diodes D1 and D2 generally consist of MOS transistors for charge transfer in order to integrate into an LSI.
Switches S1, S2 and S3 connect two capacitors 1 and 2 to a connecting point between the diodes D1 and D2 switching in parallel or in series. These switches S1, S2 and S3 can consist of MOS transistors. Thus, on and off of the switches S1, S2 and S3 corresponds to on and off of the MOS transistors. A clock driver 3 supplies clock CLK to the capacitor 2. Output voltage output from the diode 2 is applied to a load 4.
An outline of control method of the charge-pump circuit will be described below. Power source voltage of the clock driver is assumed 5 V. Although forming the diodes D1 and D2 and the switches S1, S2 and S3 actually occurs voltage drop, the voltage drop is assumed 0 V omitting the voltage drop here.
When input clock of the clock driver 3 is high level (CLK=High), assuming that S1 is off, S2 is on and S3 is off, two capacitors 1 and 2 are connected in series and each node voltage is: VL1≈0V, VA=VB=2.5V, VC=5V. VL1 is voltage of a connecting node between the diode D1 and the capacitor 1 (a pumping node), VA is voltage of a connecting node between the capacitor C1 and the switch S2, VB is voltage of a connecting node between the switch S2 and the capacitor 2, and VC is voltage of a connecting node between output of the clock driver 3 and the capacitor 2.
That is, if capacitance values which capacitors 1 and 2 have are equal, capacitors 1 and 2 are respectively charged to voltage of Vdd/2 by distributing equally electric charge to the capacitors 1 and 2 (see FIG. 10).
Next, when S2 is off and S1 and S3 are on in the state of CLK=High, two capacitors 1 and 2 are switched to parallel connection. Thus, each node voltage becomes: VL1≈2.5V, VA=5V, VB=2.5V, VC=5V (See FIG. 11).
Next, when the input clock CLK is transferred to low level (CLK=Low) in the state of the parallel connection, each node voltage becomes: VL1≈2.5V, VA=0V, VB=xe2x88x922.5V, VC=5V by effect of the capacitor coupling because the capacitors 1 and 2 are connected to the pumping node (See FIG. 12).
Thus, by repeating switching the capacitors 1 and 2 alternately to series and parallel according to the input clock CLK, output voltage of xe2x88x922.5 V (=(xe2x88x92xc2xd)xc2x7Vdd) is supplied to the load 4 from the diode D2.
When the diodes D1 and D2 consist of MOS transistors for charge transfer where a source and a gate are connected, there are a problem that needless current flows transitionally by that the diode D1 is biased to forward direction when voltage of the pumping node VL1 becomes 2.5V. Then, in order to avoid the problem, gate voltage of the MOS transistor for charge transfer may be controlled separating from source voltage.
At timing connecting the capacitors 1 and 2 in series, gate voltage of the transistor for charge transfer suitable for the diode D1 is made on by setting low level (see FIG. 10), at timing connecting the capacitors 1 and 2 in parallel, gate voltage of the transistor for charge transfer suitable for the diode D1 is made off by setting high level (see FIG. 11).
However, in the above-mentioned control method of the charge-pump circuit, voltage of the pumping node VL1 repeats change such as 0Vxe2x86x922.5Vxe2x86x92xe2x88x922.5V. Because of that, even if the MOS transistors for charge transfer are any of P-channel and N-channel, a problem occurs that a parasitic diode formed incidentally to the MOS transistors is biased to forward direction and voltage fluctuation is not carried out normally.
FIGS. 13A and 13B are views showing a problem in the case that the diode D1 is made by P-channel MOS transistor as a charge transfer device. In this case, a source S and a substrate B are earthed to improve efficiency of the charge-pump circuit depressing back gate bias effect of the MOS transistor.
As shown in FIG. 13A, there is not any problem in case that voltage of the pumping node VL1 is xe2x88x922.5V. However, as shown in FIG. 13B, when a parasitic diode formed between a drain and the substrate in the case that voltage VL1 is 2.5V of the pumping node is biased to forward, forward direction current of the diode flows between the drain and the substrate, power efficiency becomes bad, and charge-pump operation is not carried out normally.
FIGS. 14A and 14B are views showing a problem in the case that the diode D1 is made by N-channel MOS transistor as a charge transfer device. In this case, a drain D (pumping node) and a substrate B are connected to depress back gate bias effect of the MOS transistor.
As shown in FIG. 14A, there is not any problem in case that voltage of the pumping node VL1 is xe2x88x922.5V. However, as shown in FIG. 14B, a parasitic diode formed between the substrate and a source is biased to forward in the case that voltage VL1 is 2.5V. Then, forward direction current of the diode flows between the drain and the substrate, power efficiency becomes bad, and charge-pump operation is not carried out normally.
An object of the invention is to prevent that the parasitic diode is biased to forward direction and needless current flows, and to make normal operation of the charge-pump circuit possible.
A charge-pump circuit of the invention comprises, at least first and second MOS transistors for charge transfer connected in series, first and second capacitors, clock supplying means supplying clock to one end of the second capacitors, first switching means for connecting said first and second capacitors to a connecting point of the first and second MOS transistors for charge transfer in series, and second switching means for connecting said first and second capacitors to the connecting point of the first and second MOS transistors for charge transfer in parallel, wherein said clock supplying means changes the state of said clock when said first and second switching means turn off.
By such the structure, a timing that the clock is supplied to the capacitor changes to high level from low level (or to low level from high level) is adjusted in the state that both of the first and second switch means are off. In this state, the first and second capacitors are separated from the connecting point (pumping node) of the first and second MOS transistors for charge transfer.
Thus, it is prevented that the parasitic diodes following the first and second MOS transistors for charge transfer are biased to forward direction because change of potential of the pumping node is depressed.