As is well known in the field of integrated circuit design, layout and fabrication, the manufacturing cost of a given integrated circuit is largely dependent upon the chip area required to implement desired functions. The chip area, in turn, is defined by the geometries and sizes of the active components such as gate electrodes in metal-oxide-semiconductor (MOS) technology, and diffused regions such as MOS source and drain regions and bipolar emitters and base regions. These geometries and sizes are often dependent upon the photolithographic resolution available for the particular manufacturing facility. The goal of photolithography in establishing the horizontal dimensions of the various devices and circuits is to create a pattern which meets design requirements as well as to correctly align the circuit pattern on the surface of the wafer. As line widths shrink smaller and smaller in submicron photolithography, the process to print lines and contact holes in photoresist becomes increasingly more difficult.
With circuit advancement to the ultra-large-scale integration (ULSI) levels, more and more layers are added to the surface of the wafer. These additional layers in turn create more steps on the wafer surface. The resolution of small image sizes in photolithography thus becomes more difficult over the additional steps due to the increased problem of depth of focus. Planarization techniques become increasingly more important to offset the effects of a varied topography.
Planarization techniques may be applied to both dielectric layers and conductors or semiconductors. Planarizing regions of a wafer may be done in degrees from smoothing a particular layer to reduce the severity of steep slopes to global planarization across the entire wafer regardless of the underlying topography. Of course, global planarization is ideal but is also more difficult to achieve particularly between widely isolated features. The variations in the thickness of the material to be etched, differences in adjacent materials being etched and the underlying topography all add to the degree of difficulty of achieving global planarization.
Interconnect technology, creating connections between conducting regions, relies heavily on planarization techniques. In modern integrated circuits, the material of choice for upper-level conductive interconnection systems has been aluminum, including doped aluminum and aluminum alloys. Aluminum is an attractive material for integrated circuit metallization due to its high conductivity and low cost. The processing required to form aluminum metallization is also relatively easy, as it can readily be evaporated or sputtered onto the wafer. Aluminum is also able to form good ohmic contact to both p-type and n-type doped semiconductor material, such as silicon. In addition, aluminum is quite compatible with conventional semiconductor processes, such as that used to form bipolar and metal-oxide-semiconductor (MOS) devices, unlike other metals such as copper or gold which can diffuse into active regions and degrade device performance.
Certain drawbacks do exist for aluminum-based metallization systems, however, particularly as geometries enter the submicron regime. A well-known limitation of aluminum is its poor step coverage, particularly for vertical or retrograde sidewalls of contact openings through insulating layers such as silicon dioxide, and especially for sputtered aluminum, due to the shadowing effect of steep contact walls. In addition, mechanical stress in the aluminum film can cause voids therein. Stress-induced voids and step coverage faults of sufficient size can each cause an open in a metal line or contact. Furthermore, since aluminum metallization is subject to electromigration, and since the rate of electromigration increases with current density through the film, necking or narrowing of an aluminum line due to such voids or poor steps locally increases the current density. As a result, the electromigration rate increases at narrowed locations of the film, greatly increasing the electromigration failure rate.
A prior technique for addressing these limitations of aluminum metallization systems includes the use of refractory metal plugs, such as tungsten plugs, to fill contact openings in insulating layers. According to one example of this technique (for which many specific methods are well known in the art), after the opening of contacts through the insulating layer, a layer of tungsten is deposited by CVD over the wafer in such a manner as to conformally fill the contact opening, and is subsequently etched back to expose the surface of the insulating layer with the tungsten remaining in the contact opening. Alternatively, selective tungsten deposition has been used (the tungsten deposition on silicon but not on silicon dioxide) to fill contact openings. In either case, a subsequently deposited aluminum layer can readily make contact to the tungsten plug.
While the tungsten plug technique has many advantages, including good step coverage in all contacts, compatibility with planarized processing, and tolerance of misalignment in the etch of overlying aluminum lines (since the aluminum can be etched selectively relative to the tungsten), the tungsten plug process adds complexity to the manufacturing flow. In addition, deposited tungsten is vulnerable to poor adhesion and high contact resistance, requiring the use of additional sputtered barrier films prior to the deposited tungsten, and the associated added process complexity therewith.
As circuit density and device performance requirements increase, more complex wiring or routing of interconnects between conductors is required. Vertical as well as horizontal interconnects are required as the number of metallization layers increase to meet the requirements of more complex circuits. Current generation devices may require up to 5 to 6 layers of metallization to meet the wiring needs of state-of-the-art devices such as logic devices and SRAMs. To make such devices manufacturable within the limitations of existing equipment, planarization at each stage of processing becomes even more critical.
Accordingly, it is an object of the present invention to provide a method of forming planarized multilevel metallization regions to allow for complex routing of metal interconnections to achieve greater device density.
It is a further object of the present invention to form planarized regions containing metal interconnections and vertical metal pillars or vias between metal interconnections to support the multilevel metallization process.
It is yet a further object of the present invention to form planarized aluminum interconnections and vias in submicron geometries with adequate step coverage absent of stress-induced voids and electromigration problems.
It is a further object of the present invention to provide such a method which utilizes standard processing techniques.
It is yet a further object of the present invention to provide such a method which allows for closer spacing of interconnect lines enabling more devices to be formed in a smaller chip area.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.