This invention relates to a semiconductor integrated circuit device. More particularly, the present invention relates to a technique which will be effective when applied to a semiconductor integrated circuit device having self-alignment type bipolar transistors inside a region defined by an element isolation region for isolating semiconductor elements from each other.
The bipolar transistor which is now being developed by the inventor of the present invention employs an SICOS (Side Wall Base Contact Structure) structure disclosed in Japanese Patent Laid-Open No. 95662/1988. A so-called "self-alignment type" bipolar transistor employing this SICOS structure has a low parasitic capacitance formed in each of the emitter, base and collector regions and can therefore obtain high frequency characteristics at a low current.
The self-alignment type bipolar transistor is formed in a protruding (convex) island region which is in turn formed in an active region of a semiconductor substrate. The operation regions of the emitter, base and collector regions are formed vertically in the protruding island region from its main plane in the direction of depth of the semiconductor substrate. A graft base region is disposed on the side wall (shoulder portion) of the protruding island region and a base lead-out electrode is connected to this graft base region in self-alignment therewith. An emitter lead-out electrode is connected to the emitter region. Each of the emitter region and emitter lead-out electrode is formed in self-alignment with the base lead-out electrode.
The island region in which the self-alignment type bipolar transistor is to be formed is encompassed by the element isolation region and is electrically isolated from other island regions disposed on the semiconductor substrate. The element isolation region consists primarily of thin trenches, an insulating film disposed inside and along each thin trench and a buried material buried into the thin trench through the insulating film. The thin trench is formed at a position spaced-apart by a predetermined distance from the protruding island region. This thin trench is formed by etching anisotropically the semiconductor substrate by RIE or the like. The insulating film formed along the surface of the thin trench is a silicon dioxide film formed by thermally oxidizing the semiconductor substrate on the surface of the thin trench. The buried material is formed selectively only inside the thin trench by depositing a polycrystalline silicon film on the entire surface of the semiconductor substrate by CVD (Chemical Vapor Deposition) and etching back the polycrystalline silicon film thus deposited. The device isolation region of this kind has a small occupying area because the thin trench is formed by anisotropic etching having a small side etching quantity, and can therefore improve the integration density of the semiconductor device.