There are many various types of data acquisition systems available for use on personal computers, including an architecture for plug-in printed circuit boards built to the “PCI” standard for IBM-compatible personal computers. Certain PCI cards can be used as digital sampling systems; however, the fastest available such PCI digital sampling systems are not consistent with regard to their sampling rates. For example, when a PCI data acquisition card transfers data to the personal computer, there is a time interval where incoming samples can be lost. If the time interval to transfer data between the PCI data acquisition card and the personal computer is greater than the sampling rate period, then data that needs to be sampled may be lost during this transfer. The result is that the incoming data would not be correctly sampled at the desired rate.
Another limitation of the PCI technology is that the data transfer time is limited to the PCI interface parameters, and since the PCI interface is based upon the architecture of the personal computer itself, this transfer time can vary depending upon the chip set of the PC. The end result in using PCI data acquisition cards is that the “raw” data sampling frequency has an upper limit, and furthermore the sampling rate itself is inconsistent.
In addition to PCI digital sampling systems, certain other types of digital data receivers have been disclosed in the patent literature, including U.S. Pat. No. 5,539,782, which discloses a digital data receiver that restores the symbol timing of an analog signal received over a digital communications link. The analog signal is transmitted in a form of a complex signal, and the receiver first demodulates and samples the received analog signal, and then samples the demodulated signal by a frequency that is eight times the frequency of a symbol frequency of the transmitted symbols (digital data). This sampled data is presented to a low pass filter, then sampled again to a four to one ratio by the first sampling section, which outputs a frequency that is twice that of the symbol frequency. The low pass filter output is sampled using a first clock that is applied from a symbol timing restoring circuit. The output data of the “first sampling section” is presented to a matched filter, then to an equalizer circuit, and then is sampled again to a two to one ratio at a second sampling section, which outputs symbol data at the symbol frequency. The second sampling section samples the output data of the equalizer in accordance with a second clock applied from the symbol timing restoring circuit. The output data of the matched filter is presented to a timing data generating section. The average value of the positional information of the first sampled signal is determined, and this information is compared to a positive threshold value. The present sampling position can be adjusted to be faster by a certain magnitude if the average value is greater than or equal to the positive threshold value. A second comparison occurs that compares the average value and a negative threshold value, when the average value was less than the positive threshold value, determined earlier. The sampling position can be adjusted by a certain magnitude when the average value is less than or equal to the negative threshold value. If the average value was greater than the negative threshold value and less than the positive threshold value, then the present sampling position is maintained. The first and second sampling means use clocks generated by the symbol timing restoring circuit, and these clocks are used to create the adjusted sampling position.
U.S. Pat. No. 4,965,884 discloses a method for data alignment that receives parallel digital data signals and an aligned frame pulse. The frame pulse occurs at a regular interval that is a multiple of the data clock period. A set of six clock signals are provided that are each phase-shifted from one another. The multiple clock signals are used to begin sampling the incoming data signals while awaiting a frame pulse. The incoming data is stored in a register or a memory circuit, and once the frame pulse arrives and is discovered, a decision logic circuit analyzes the position of the frame pulse within the shift register storing the data.
This decision logic circuit chooses the three clock samples that are most centered on the frame pulse. The data is then sampled using the three selected clocks, and a “majority value” of the multiple samples is used. The sampled data is then aligned with a locally generated frame pulse. The data that has been selected as having the majority value is then output.
U.S. Pat. No. 5,572,556 discloses a method for controlling the reproduction of a sampling clock signal. Since transmission frequency clock signals and sampling clock signals are almost never of the same frequency and phase, in the prior art these clock signals typically are aligned by running one of the digitized signals through a buffer memory. Alignment is established between the asynchronous clock signals, using a voltage controlled oscillator (VCO) to make the signal frequencies coincide. However, quantization error is contained in the reproduced sampling clock signal, which can cause jitter problems. The method not only determines the difference in frequency between the incoming transmission path clock signal and the sampling clock signal, but can use the frequency difference and phase difference information to detect a “start timing” of a reproduced sampling clock signal. In this manner, not only is the frequency controlled, but also the phase angle. Once the transmission path clock signal is extracted from the incoming data transmission signal, digital data is first stored in a buffer memory, and the “start timing” is detected for reproducing a sampling clock signal, which is then used for generating a phase control signal. A “reception frequency difference data signal” is created that is related to the difference in frequency between the extracted transmission path clock signal and the reproduced “sampling clock signal,” which is then used to generate a frequency control signal. The sampling clock signal is then reproduced in response to both the phase control signal and the frequency control signal. The result is that digital data can be read out from the buffer memory with both controlled frequency and phase.
U.S. Pat. No. 5,502,750 discloses a jitter attenuator that generates multiple phase clocks to generate a transmit clock having less jitter than the receive clock. The generated transmit clock has the same average frequency as the receive clock. The receive clock is first divided into a series of write clocks for writing data into an elastic buffer, and the transmit clock is divided into a series of read clocks for reading data from the elastic buffer. A phase selector, using a counter, selects one of the multi-phase clocks to be the transmit clock. The phase of the transmit clock that is closest to one of the multiple read clocks is adjusted by the phase comparison of the read and write clocks used with the elastic buffer. An external oscillator that has a constant frequency is used to generate the plurality of multi-phase clocks that are used for the transmit clock output. The phase, rather than the frequency, is adjusted thereby eliminating feedback to an external voltage controlled oscillator, which allows the jitter attenuator of this invention to be integrated on a single silicon substrate.
U.S. Pat. No. 5,708,686 discloses a method for receiving digital signals having a constant bit rate using cell-structured asynchronous transmission with pauses of different length between individual cells. The digital signals are written into a FIFO memory until the FIFO is half filled, at which time the digital signals begin to be read out, using a readout clock whose frequency is less than the frequency of the receive clock. During this readout, a signal controls the frequency of the readout clock, and this signal is derived from the loading state of the FIFO memory. The control variable generated based on the loading of the FIFO is fed to multiple voltage controlled oscillators, thereby making it possible to cover a large frequency range used for the output data rate. The time interval for querying the loading state of the FIFO memory can be at rather large time intervals, or a cell clock can be obtained from the received digital signals that is used to stipulate the point in time of such queries. This invention can be used with encoded audio and video signals, including MPEG-encoded signals in which the MPEG signals use a constant data rate. While the coder and decoder circuits can be set to different bit rates, during operation the bit rate remains constant.
U.S. Pat. No. 5,493,589 discloses a sampling circuit that synchronizes a data stream at a high sampling rate. The samples are received at a high sampling rate and are converted into data samples at a low sampling rate which is related to the high sampling rate, in which the low rate samples are synchronized with the high rate samples. The data is stored in memory, and the read address signals are derived by combining the write address signals with a difference address signal that is generated by a circuit that includes a modulo counter. A sample-and-hold circuit stores the count of the modulo counter and supplies it to an allocating circuit that generates the difference address signal. A decoder controlled by the modulo counter supplies a clock signal at the low sampling rate to a second sample-and-hold circuit that is provided with data from the memory. The second sample-and-hold circuit outputs synchronized data at the low sampling rate.
U.S. Pat. No. 5,828,698 discloses a processing system which allows Cellular Digital Packet Data (CDPD) to be transmitted over existing cellular telephone networks. One objective of this invention is to convert from serial in-phase (I) and quadrature-phase symbols at the IS-54 standard symbol rate to time-aligned IQ pairs at the CDPD standard symbol rate. This is accomplished by using two different sampling rates: one rate being an integer multiple of 24.3 kHz (the transmission rate of digital voice), and the second rate being an integer multiple of 19.2 kHz (the transmission rate of CDPD). Once the data has been converted, the invention also provides a method for ensuring that the digital signal processor reads the correct number of samples from the FIFO buffers. This achieves virtual real time processing independent of burst arrival time.
U.S. Pat. No. 5,796,795 discloses a data transferring circuit which aligns a clock with data. The invention relates to high speed processing of synchronous data, typically in a switch for a broadband network. Alignment is achieved by delaying, by approximately the same amount, a reference clock and the data itself through the data processing section of the circuit, and by regenerating a master clock from the delayed reference clock.
U.S. Pat. No. 4,841,551 discloses a high speed data-clock synchronization processor. A local crystal clock undergoes a series of parallel output delays through a clock-delayed phase generator. The phased clock signals are then sent to the clock-delayed phase processor. After processing, the optimum clock phase is selected at the optimum phase selector. An optimum clock phase is selected with each received data message. As a result, the utilizable bandwidth may be increased and data distortion is minimized so that the number of stations connected to a data bus provided with the data clock from the synchronization processor may be substantially increased.
U.S. Pat. No. 4,941,156 discloses a linear jitter attenuation circuit. The jitter attenuator utilizes a FIFO data register for receiving and temporarily storing data in a plurality of storage locations. The FIFO register stores data using a Write pointer driven by a Write clock and Read pointer driven by a Read clock to read the stored data. A phase locked loop is used to synchronize the Read and Write pointers, so to maintain the FIFO in a half empty/half full state. The phase locked loop determines the phase difference between the Read and Write clocks. The phase locked loop is driven by a separate oscillator.
The prior patents listed above do not solve the problem of an actual data acquisition device that purports to operate at a constant, fast data sampling rate, but in reality does not do so without missing or losing samples. These documents do not provide a solution that offers a front end device for sampling data at a consistent, fast sampling rate, while allowing the actual data acquisition device to sample at a slower, varying rates.