1. Field of the Invention
The present invention relates to a color linear image sensor apparatus, and more specifically to a color linear image sensor apparatus comprising three arrays of photosensor cells.
2. Description of Related Art
Referring to FIG. 1, there is shown one conventional color linear image sensor apparatus comprising three arrays of photosensor cells. This conventional color linear image sensor apparatus includes three arrays 1R, 1G and 1B of photoelectric conversion cells, namely, photocells, and a CCD register 2R-1, 2R-2, . . . located at each side of each of these photocell arrays 1R, 1G and 1B. In this example, these photocell arrays 1R, 1G and 1B have a peak sensitivity in red, in green and in blue, respectively, so that the apparatus functions as a color linear image sensor. With this arrangement, since the three linear image sensors are located in parallel, a distance "L" between each pair of adjacent photocell arrays is ordinarily required to be on the order of 100 .mu.m to 200 .mu.m.
Because of this distance "L" between each pair of adjacent photocell arrays, each of the photocell arrays senses a different position on the same subject copy, as will be apparent from FIG. 3 illustrating an optical path diagram in the case of using the color linear image sensor apparatus. Color signal processing needs a color signal for red, a color signal for green and a color signal for blue on the same position. Because of the difference between the positions sensed by the photocell arrays, it was necessary to externally store the color signals of the amount in proportion to the distances "L" between the photocell arrays. For example, assuming that the distance "L" between each pair of adjacent photocell arrays is 140 .mu.m, a size "d" of each photocell is 14 .mu.m, and a signal for each one pixel has information of 10 bits, a memory capacity "M.sub.1 " required for each one pixel is expressed as follows: EQU M.sub.1 =10(L+2L)/d=300 (bits)
Furthermore, assuming that one line is composed of, for example 5,000 pixels, a memory capacity "M.sub.T " required for processing the color signals for one line is expressed as follows: EQU M.sub.T =M.sub.1 .times.5000=1.5 (megabits)
in general, memory for this purpose is required to have a high speed reading operation; therefore, an expensive memory such as a static random access memory (SRAM) has been used. Accordingly, there is a demand for a color linear image sensor apparatus having a shortened distance "L" between adjacent photocell arrays, so that a required external memory capacity can be made small.
In the above mentioned conventional color linear image sensor apparatus, as will be understood from FIG. 1, there is restriction in shortening the distance between adjacent photocell arrays, because there are wiring conductors for clocks .phi..sub.1 and .phi..sub.2 between the CCD register 2R-2 and the CCD register 2G-1.
For example, referring to FIG. 2, there is shown an enlarged layout pattern diagram of a portion "A" in FIG. 1.
In FIG. 2, the CCD register 2R-2 and the CCD register 2G-1 are located between two photocell arrays 1R and 1G, each of which is formed by arranging a number of photodiodes PD (isolated from each other by a channel stopper 6) in a single line. The CCD register 2R-2 and the CCD register 2G-1 have first transfer gate electrode 11-1 (formed of a first level polysilicon film) and a second transfer gate electrodes 11-2 (formed of a second level polysilicon film), which are common to the CCD register 2R-2 and the CCD register 2G-1. The CCD register 2R-2 and the CCD register 2G-1 are isolated from each other by a channel stopper 6A. Between the photocell array 1R and the CCD register 2R-2, there is formed a transfer gate electrode 12-2 (3R-2) of the second level polysilicon film, and similarly, between the photocell array 1G and the CCD register 2G-1, there is formed a transfer gate electrode 12-1 (3G-1) of the second level polysilicon film. Clock signal wiring conductors 14(.phi..sub.1) and 14(.phi..sub.2), which also function as a light shield, are connected to the first transfer gate electrode 11-1 and the second transfer gate electrode 11-2 through contact holes C1 and C2, respectively.
This arrangement was attributable to an idea of forming the clock signal wiring conductors 14(.phi..sub.1) and 14(.phi..sub.2) above the CCD registers. Nevertheless, the channel stopper 6A was required to have a sufficient width to form the contact holes C1 and C2 which connect the clock signal wiring conductors to the first and second gate electrodes, respectively. For example, in the case of designing the layout pattern under the 2 .mu.m rule, assuming that the size of the contact holes is 2 .mu.m.times.3 .mu.m and the alignment margin is 1 .mu.m, the channel stopper 6A is required to have the width of at least 10 .mu.m, and preferably about 12 .mu.m. In this connection, only for the purpose of electrical isolation of the transfer channels, it is sufficient if this width of the channel stopper is at least 2 .mu.m. Therefore, even if the above mentioned design is adopted, the existence of the clock signal wiring conductors is still hindrance in shortening the distance "L" between the photocell arrays.
Furthermore, as one method for shortening the distance "L" between the photocell arrays, it might be possible, as shown in FIG. 4, to connect the gate electrodes (11-1A, 11-2A, . . . ) of the CCD register 2 on the channel stopper 6 of the photocell array 1, as adopted in an area image sensor. However, this method requires four-phase, tri-level, pulses .phi..sub.1, .phi..sub.2, .phi..sub.3 and .phi..sub.4 for driving the CCD registers, and therefore, the driving condition becomes complicated.