1. Field of the Invention
This invention relates to a display device that has a plurality of pixels disposed in a matrix configuration, a plurality of gate lines extending in a row direction, and a driving circuit sequentially supplying a gate scanning signal to each of the gate lines, especially to a display device with improved image quality.
2. Description of the Related Art
FIG. 10 is a diagram of a conventional liquid crystal display device. A liquid crystal panel 100 has a plurality of pixels formed in a matrix configuration of n-rows and m-columns. Each of the pixels has a pixel selecting thin film transistor 10, a liquid crystal LC, and a storage capacitor Csc. The thin film transistor will be referred to as TFT hereinafter.
A gate line 20 extending in a row direction is connected to the gate of the TFT 10, and a data line 22 extending in a column direction is connected to the drain of the TFT 10. A gate scanning signal is sequentially supplied from a vertical driving circuit (V drive circuit) 130 to the gate line 20 of each row, and the TFT 10 is selected accordingly. Also, a video signal is applied to the liquid crystal LC through the TFT 10 based on a drain scanning signal supplied from a horizontal driving circuit (H drive circuit) 140.
Japanese Patent Application Publication No. Hei 10-115839 discloses a liquid crystal display device with the above configuration.
However, a gate insulating layer of the TFT in the output portion of the gate scanning signal of the vertical driving circuit 130, sometimes suffers from a break down and leakage due to static charge induced during the TFT manufacturing process of the conventional liquid crystal display device. This kind of trouble will be explained by referring to FIG. 11A and FIG. 11B. FIG. 11A and FIG. 11B are enlarged view of part B encircled by the dotted line in FIG. 10. These figures show the pattern of the edge of the gate line 20 as well as the output portion of the vertical driving circuit 130. FIG. 11A is a plan view, and FIG. 11B is a cross-sectional view along with the X—X line in FIG. 11A.
A dry-etching method is employed for processing the gate line 20, a storage capacitor line 21, and a gate wiring in the vertical driving circuit 130. Static charge is induced and stored in the gate line 20, the storage capacitor line 21, and the gate wiring during the dry-etching process. When the ion implantation of an N-type impurity such as arsenic or phosphorus into a P-Si layer, or the ion implantation of a P-type impurity such as boron in case of P-type channel TFT, is performed for forming a source region and a drain region using the gate line 20 as a mask, static charge is also stored in the gate line 20, the storage capacitor line 21, and the gate wiring due to the charge-up phenomena. It is especially easy for the gate line 20 and the storage capacitor line 21 to store static charge because they extend across the liquid crystal panel 100.
The stored charge is discharged from the edge of the gate line 20 to the gate wiring 13 of the TFT 1 located close to the gate line 20. The charges from the discharge will reach a gate electrode of an adjacent TFT 2 through the gate wiring 13, causing a dielectric break down and leakage at part A of the gate insulating layer 12 of the TFT 2-1. In the figure, the reference numeral 40 indicates a transparent insulating substrate, the reference numeral 11 denotes an active layer (poly-silicon layer) disposed on the transparent insulating substrate 40, and the reference numeral 14 indicates an aluminum wiring layer. FIG. 11B is a cross-sectional view of the device before the aluminum wiring layer 14 is disposed.