The present invention relates generally to the manufacture of high speed, high performance MOS semiconductor devices fabricated on strained lattice semiconductor substrates, and MOS devices obtained thereby. Specifically, the present invention relates to an improved method of manufacturing MOS devices including gate insulator layers comprised of high-k dielectric materials on strained lattice semiconductor substrates, which method substantially eliminates, or at least minimizes, stress relaxation of the strained lattice semiconductor layer attendant upon gate insulator layer formation.
Recently, there has been much interest in investigating the feasibility of various approaches having the aim or goal of developing new semiconductor materials which provide increased speeds of electron and hole flow therethrough, thereby permitting fabrication of semiconductor devices, such as integrated circuit (IC) devices, with higher operating speeds, enhanced performance characteristics, and lower power consumption. One such material which shows promise in attaining the goal of higher device operating speeds is termed xe2x80x9cstrained siliconxe2x80x9d.
According to this approach, a very thin, tensilely strained, crystalline silicon (Si) layer is grown on a relaxed, graded composition Sixe2x80x94Ge buffer layer several microns thick, which Sixe2x80x94Ge buffer layer is, in turn, formed on a suitable crystalline substrate, e.g., a Si wafer or a silicon-on-insulator (SOI) wafer. Strained Si technology is based upon the tendency of the Si atoms, when deposited on the Sixe2x80x94Ge buffer layer, to align with the greater lattice constant (spacing) of the Si and Ge atoms therein (relative to pure Si). As a consequence of the Si atoms being deposited on the Sixe2x80x94Ge substrate comprised of atoms which are spaced further apart than in pure Si, they xe2x80x9cstretchxe2x80x9d to align with the underlying lattice of Si and Ge atoms, thereby xe2x80x9cstretchingxe2x80x9d or tensilely straining the deposited Si layer. Electrons and holes in such strained Si layers have greater mobility than in conventional, relaxed Si layers with smaller inter-atom spacings, i.e., there is less resistance to electron and/or hole flow. For example, electron flow in strained Si may be up to about 70% faster compared to electron flow in conventional Si. Transistors and IC devices formed with such strained Si layers can exhibit operating speeds up to about 35% faster than those of equivalent devices formed with conventional Si, without necessity for reduction in transistor size.
Another tactic for improving the performance of semiconductor devices, e.g., MOS devices such as PMOS and NMOS transistors and CMOS devices, involves increasing the capacitance between the gate electrode and the underlying channel region within the semiconductor substrate. Typically, the capacitance is increased by decreasing the thickness of the gate dielectric layer, typically an oxide layer such as a silicon oxide, to below about 100 xc3x85. Currently, silicon oxide, e.g., SiO2, gate dielectric layer thicknesses are approaching about 40 xc3x85 or less. However, the utility of silicon oxide as a gate dielectric is severely limited at such reduced thicknesses, e.g., due to direct tunneling through the gate dielectric layer to the underlying channel region, thereby increasing the gate-to-channel leakage current and an increase in power consumption.
Inasmuch as further reduction in the silicon oxide gate dielectric thickness is impractical in view of the above-mentioned increase in gate-to-channel leakage current, various approaches have been investigated for reducing the gate-to-channel leakage current while maintaining a thin SiO2 xe2x80x9cequivalent thicknessxe2x80x9d, i.e., the thickness of a non-SiO2 dielectric layer determined by multiplying a given SiO2 thickness by the ratio of the dielectric constant of the non-SiO2 dielectric to that of SiO2, i.e., knon-SiO2/kSiO2. Thus, one approach which has been investigated is the use of materials with dielectric constants higher than that of silicon oxide materials as gate dielectric materials, whereby the xe2x80x9chigh-kxe2x80x9d dielectric materials, i.e., materials with dielectric constants of about 5 or above, replace the conventional silicon oxide-based xe2x80x9clow-kxe2x80x9d dielectric materials with dielectric constants of about 4 or below. The increased capacitance k (or permittivity ∈) of the gate dielectric material advantageously results in an increase in the gate-to-channel capacitance, which in turn results in improved device performance. Since the capacitance C is proportional to the permittivity ∈ of the gate dielectric material divided by the thickness t of the gate dielectric layer, it is evident that the use of a high-k (or high-∈) material permits use of thicker gate dielectric layers, i.e.,  greater than 40 xc3x85, whereby both greater capacitance and device speed are obtained with less gate-to-channel leakage current.
Typically, high-k dielectric materials, i.e., with kxe2x89xa75, suitable for use as gate dielectric layers in the manufacture of semiconductor devices, are formed with a physical thickness from about 40 to about 500 xc3x85, typically 40-100 xc3x85 (or a SiO2 equivalent thickness less than about 40 xc3x85), and comprise metal and oxygen-containing material including at least one dielectric material selected from the group consisting of metal oxides, metal silicates, metal aluminates, metal titanates, metal zirconates, ferroelectric materials, binary metal oxides, and ternary metal oxides. Suitable metal oxides include aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, tantalum oxide, tungsten oxide, cerium oxide, and yttrium oxide; suitable metal silicates include zirconium silicate, and hafnium silicate; suitable metal aluminates include hafnium aluminate and lanthanum aluminate; suitable metal titanates include lead titanate, barium titanate, strontium titanate, and barium strontium titanate; suitable metal zirconates include lead zirconate; and suitable ferroelectric and/or ternary metal oxides include PST (PbScxTa1xe2x88x92xO3), PZN (PbZnxNb1xe2x88x92xO3), PZT (PbZrxTi1xe2x88x92xO3), and PMN (PbMgxNb1xe2x88x92xO3). Deposition of the high-k metal oxide layers and/or post-deposition treatment of the high-k metal oxide layers typically involves processing at elevated temperatures, e.g., at about 500-900xc2x0 C. in the case of aluminum oxide (Al2O3) deposition from an AlCl3/O2 ambient.
However, an important concern in the manufacture of practical semiconductor devices utilizing strained semiconductor layers, e.g., strained Si layers, is the requirement for maintaining the tensilely strained condition of the strained semiconductor layer throughout device processing, without incurring significant strain relaxation disadvantageously leading to reduction in electron/hole mobility resulting in degradation in device performance characteristics. For example, many device fabrication steps, including for example, the above-described high-k dielectric deposition and post-treatment, frequently involve high temperature processing at temperatures on the order of about 900-1,100xc2x0 C. for intervals sufficient to result in significant relaxation of the tensile strain of the Si layer, which in turn, results in a lowering of the electron and hole mobilities therein to values comparable to those of conventional Si layers, whereby the potential advantages attributable to enhanced electron/hole mobility in the strained Si layer are partially or wholly lost.
Accordingly, there exists a need for improved methodology for fabrication of semiconductor devices with strained semiconductor layers, notably strained Si layers, which substantially eliminates, or at least minimizes, deleterious stress relaxation during device processing at elevated temperatures, e.g., as in the formation of high-k dielectric gate insulator layers as part of a process sequence for the manufacture of MOS-type transistors and CMOS devices.
The present invention, wherein processing for deposition of high-k dielectric gate insulator layers and buffer layers therefor, e.g., metal oxide-based high-k dielectrics and silicon oxide-based buffer layers, forming part of a sequence of steps for fabricating MOS-type transistors and CMOS devices, is performed at temperatures which effectively eliminate, or at least minimize, disadvantageous strain relaxation of the strained lattice semiconductor arising from the thermal annealing. As a consequence, the inventive methodology facilitates manufacture of high speed, high performance, reduced power consumption semiconductor devices utilizing strained semiconductor technology. Further, the methodology afforded by the present invention enjoys diverse utility in the manufacture of numerous and various semiconductor devices and/or components therefor which require use of strained semiconductor technology for enhancement of device speed and lower power consumption.
An advantage of the present invention is an improved method for manufacturing a semiconductor device comprising a strained lattice semiconductor layer.
Another advantage of the present invention is an improved method for manufacturing a semiconductor device comprising formation of a high-k dielectric gate oxide layer on a strained lattice semiconductor layer without incurring significant stress relaxation.
Still another advantage of the present invention is an improved method for fabricating a MOS-type semiconductor device on a strained lattice semiconductor layer.
Yet another advantage of the present invention are improved MOS-type semiconductor devices fabricated on strained lattice semiconductor substrates.
Additional advantages and other aspects and features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the invention, the foregoing and other advantages are obtained in part by a method of manufacturing a semiconductor device, comprising the sequential steps of:
(a) providing a semiconductor substrate comprising a strained; lattice semiconductor layer at an upper surface thereof, the strained lattice semiconductor layer having a pre-selected amount of lattice strain therein;
(b) forming a thin buffer/interfacial layer of a low-k dielectric material on the upper surface of the semiconductor substrate; and
(c) forming a layer of a high-k dielectric material on the thin buffer/interfacial layer of a low-k dielectric material, wherein:
steps (b) and (c) are each performed at a minimum temperature sufficient to effect formation of the respective dielectric layer without incurring, or at least minimizing, strain relaxation of the strained lattice semiconductor layer.
According to embodiments of the present invention, step (a) comprises providing a semiconductor substrate including a crystalline, graded composition Sixe2x80x94Ge layer, with a lattice-matched crystalline silicon (Si) layer on a first side of the Sixe2x80x94Ge layer and comprising the strained lattice semiconductor layer; and according to particular embodiments of the present invention, step (a) further comprises providing a semiconductor substrate including a crystalline Si layer on a second, opposite side of the Sixe2x80x94Ge layer;
In accordance with embodiments of the present invention, step (b) comprises forming the thin buffer/interfacial layer of a low-k dielectric material having a dielectric constant k less than 5 and at a thickness from about 2 to about 6 xc3x85.
According to particular embodiments of the present invention, step (b) comprises forming the thin buffer/interfacial layer of a low-k dielectric material from at least one material selected from the group consisting of silicon oxides and silicon oxynitrides and at a temperature ranging from about 200 to about 400xc2x0 C., by means of an atomic layer deposition (ALD) method selected from chemical vapor deposition (CVD), molecular beam deposition (MBD), and physical vapor deposition (PVD).
Embodiments of the invention include performing step (c) by forming a layer of a high-k dielectric material having a dielectric constant k greater than 5 and a thickness from about 40 to about 100 xc3x85.
According to particular embodiments of the present invention, step (c) comprises forming the layer of a high-k dielectric material from at least one metal and oxygen-containing material selected from the group consisting of metal oxides, metal silicates, metal aluminates, metal titanates, metal zirconates, ferroelectric materials, binary metal oxides, and ternary metal oxides, i.e., step (c) comprises forming the layer of a high-k dielectric material from at least one material selected from the group consisting of aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, tantalum oxide, tungsten oxide, cerium oxide, yttrium oxide, zirconium silicate, hafnium silicate, hafnium aluminate, lanthanum aluminate, lead titanate, barium titanate, strontium titanate, barium strontium titanate, lead zirconate; ferroelectric oxides, ternary metal oxides, PST (PbScxTa1xe2x88x92xO3), PZN (PbZnxNb1xe2x88x92xO3), PZT (PbZrxTi1xe2x88x92xO3), and PMN (PbMgxNb1xe2x88x92xO3); wherein step (c) comprises forming the layer of a high-k dielectric material at a temperature ranging from about 200 to about 400xc2x0 C., by means of an atomic layer deposition (ALD) method selected from chemical vapor deposition (CVD), molecular beam deposition (MBD), and physical vapor deposition (PVD).
In accordance with embodiments of the present invention, the method further comprises sequential steps of:
(d) forming an electrically conductive layer on the layer of a high-k dielectric material; and
(e) patterning the electrically conductive layer, the layer of a high-k dielectric material, and the thin buffer layer of a low-k dielectric material to form at least one gate insulator layer/gate electrode stack on at least one portion of the upper surface of the semiconductor substrate;
(f) implanting dopant species of one conductivity type into the semiconductor substrate utilizing the at least one gate insulator layer/gate electrode stack as an implantation mask, thereby forming at least one pair of shallow depth source/drain extension regions in the semiconductor substrate vertically aligned with opposite side edges of the at least one gate insulator layer/gate electrode stack;
(g) forming insulative sidewall spacers on the opposite side edges of the at least one gate insulator layer/gate electrode stack;
(h) implanting dopant species of the one conductivity type into the semiconductor substrate utilizing the at least one gate insulator layer/gate electrode stack with the insulative sidewall spacers thereon as an implantation mask, thereby forming at least one pair of deeper source/drain regions in the semiconductor substrate vertically aligned with opposite side edges of the sidewall spacers; and
(i) thermally annealing the thus-formed structure for a minimum interval sufficient to activate the dopant species implanted in the at least one pair of shallow depth source/drain regions and in the at least one pair of deeper source/drain regions without incurring, or at least minimizing, strain relaxation of the strained lattice semiconductor layer.
According to particular embodiments of the present invention, step (i) comprises performing laser thermal annealing (LTA) or rapid thermal annealing (RTA) at a temperature from about 1,200 to about 1,400xc2x0 C. for from about 1 to about 100 nanosec.
Another aspect of the present invention are PMOS or NMOS transistors and CMOS and IC devices manufactured according to the above method.
Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein embodiments of the present invention are shown and described, simply by way of illustration of the best mode contemplated for practicing the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as limitative.