1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory configured by a plurality of nonvolatile memory cells with the transistor structure having a charge storage layer and a manufacturing method thereof.
2. Description of the Related Art
Recently, much attention has been paid to a NAND flash memory configured by a series connection a plurality of nonvolatile memory cells with the transistor structure as one nonvolatile semiconductor memory device configuration. It is required for the memory cells (cell transistors) used in the NAND flash memory to satisfy the following two conditions. One condition is to suppress the short channel effect and maintain the preferable turn-on/off characteristic of the transistor even when the gate length is made smaller. The other condition is to raise the channel potential of a non-selected cell to prevent erroneous programming at the programming time.
In order to suppress the short channel effect, it is necessary to increase the dopant impurity concentration of the silicon substrate and reduce the depletion layer width. On the other hand, a rise in channel potential required for preventing erroneous programming is realized when the impurity concentration of the substrate is low and the depletion layer width is large. Therefore, as the gate length is reduced, the contradiction between the conditions of suppression of the short channel effect and prevention of erroneous programming becomes more significant. That is, it becomes extremely difficult to miniaturize memory cells while maintaining the basic function of the memory cell.
As one solution for the above problem, formation of memory cells on a silicon-on-insulator (SOI) substrate is provided. However, since the procurement cost for the SOI substrate is high, there occurs a problem that the SOI substrate is not suitable for a flash memory in which greater importance is attached to the manufacturing cost.
The structure in which thin insulating films are formed under source/drain regions is proposed in order to suppress the short channel effect of a MOS transistor (JP-A H5-218417 [KOKAI]). However, this is the normal transistor structure and is not the transistor structure that realizes a memory cell. Further, even if the structure is applied to a memory cell, the effect of preventing erroneous programming cannot be attained. This is because the insulating films under the source/drain regions are thin and the effect of extending the depletion layer in a depth direction of the substrate cannot be attained.
Further, in a NAND cell unit, the structure in which a thin insulating film is formed under a channel region is proposed (JP-A 2007-329366 [KOKAI]). However, the structure is made to form a NAND cell unit with a partial SOI structure and the sufficiently large effect of suppression of the short channel effect and prevention of erroneous programming is not attained.