In the fabrication of ultra-large scale-integration (ULSI) circuits it has been very common to utilize vertical stacking, or vertical integration, of metal wiring circuits to form multilevel interconnection. Multilevel fabrication process has become an efficient way to increase circuit performance and increase the functional complexity of the circuits. One drawback of multilevel interconnection is the loss of topological planarity resulting from various photolithographic and etching processes. The various integrated circuit fabrication processes invariably produce nonplanar surface, or nonplanar topography, on the wafer, from which semiconductor devices are fabricated. During the multilevel metallization of VLSI or ULSI devices, the multiplicity of layers of nonplanar surfaces further add together to cause even more serious topography problems. For example, the conductive or insulative properties of the various deposited films can be degraded on the area of the film layers across the step height. Those films in high topography areas can be easily broken during heat, electrical current, or mechanical stress steps, resulting in the pattern areas becoming discontinuous. Such discontinuity can cause failures in the device to perform certain intended functions. Furthermore, a nonplanar surface cannot be precisely focused during the photolithography process, because the depth of focus of the conventional photolithographic stepper will be deviated by different step heights of the wafer. Such an out-of-focus problem is more profound with respect to device features of very small sizes.
To alleviate these problems, the wafer is planarized at various stages in the fabrication process to minimize non-planar topography and thus its adverse effects. Such planarization is typically implemented in the dielectric layers. However, it is also possible to implement the planarization process in the conductor layer. More recently, chemical-mechanical polishing (CMP) processes have become very well received to planarize the wafer surface in preparation for further device fabrication. The CMP process mainly involves the step of holding a semiconductor wafer against a rotating polishing pad surface wetted by a polishing slurry, which typically comprises an acidic or basic etching solution in combination with alumina or silica particles. On the one hand, the liquid portion of the slurry chemically removes, loosens, or modifies the composition of the material on the wafer which is to be removed. On the other hand, the particle portion of the slurry, in combination of the rotating polishing pad, physically removes the chemical modified material from the wafer. Thus, the name "chemical-mechanical polishing" was obtained.
One of the most commonly used sacrificial materials in the chemical-mechanical polishing process is a solution-type silicon dioxide, which is commonly referred to as the spin-on-glass (SOG). The SiO.sub.2 -based SOG is initially formed as a low viscosity solution which can be coated onto the nonplanar surface to quickly fill the recessed areas by a conventional spin coating technique. After the SOG coating, the coated layer is hard-baked to remove the solvent contained therein and turn the SOG layer into a hardened layer. Because of its high electrical resistance, the solidified SOG layer on top of the integrated circuit structure (i.e., the metal layer) must be etched back, typically by a chemical-mechanical polishing procedure using an abrasive slurry containing hydrogen fluoride in the chemical portion of the polishing procedure. If the SOG layer on the top surface of the wafer is not completely removed, it can generate the so-called vias poisoning, causing the vias to have a very high electrical resistance and adversely affect the interlayer conduction.
One of the commonly observed problems in using SOG during the planarization process is the so-called dishing effect. The etching process is not a selective process and it will remove all the affected material on the wafer surface. During the chemical-mechanical polishing of the SOG layer, the portion of the SOG layer inside the trenches can be affected by the etching solution being dished out from the mechanical polisher, resulting another type of un-planarized top surface. Many times, the dishing effect could cause even more serious nonplanar surface on the wafer. One way to ameliorate the dishing effect in the etch back process is to use a etch-back photoresist. However, this would require an extra photolithography process using an extra photo mask to remove the sacrificial material above the patterned structure. This can add substantially to the total manufacturing cost.
Another way to avoid such dishing effect is to use a non-silicon-based polymeric material, such as polyimide, which exhibits excellent chemical and electrical resistance, as the sacrificial material for chemical-mechanical polishing processes. The polymer-based sacrificial material, however, will not be removed by the conventional chemical-mechanical polishing slurry designed for SOG. Thus, the IC manufacturers must stock two different types of chemical-mechanical polishing slurries. And the use of a different chemical-mechanical polishing slurry may cause material compatibility problems and other handling concerns. In a co-pending application, it was demonstrated that excellent result can be obtained by treating the polymeric material so that it becomes removable by hydrofluoric acid. However, in semiconductor devices which contain relatively wide trenches, the polymeric sacrificial layer will be warped into the trench bottom, and the dishing effect can again become significant.
U.S. Pat. No. 4,944,836 disclosed a chemical-mechanical polishing method for producing coplanar metal-insulator films on a substrate. It taught the conventional approach of using silicon dioxide based slurry to provide a planarized surface by chemical-mechanical polishing. However, when the layer thickness of the semiconductor device becomes increasing thin, and the depth of the trench becomes correspondingly shallow, the dishing effect caused by the exposure of the silicon dioxide in the trench area becomes relatively more profound.
U.S. Pat. No. 5,169,491 disclosed a method for planarizing SiO.sub.2 -containing dielectric in semiconductor wafer processing. It involved the steps of (1) providing a layer of undoped SiO.sub.2 atop a wafer; (b) depositing a layer of borophosphosilicate glass (BPSG) atop the layer of undoped SiO.sub.2 ; and (c) chemical mechanical polishing the borophosphosilicate glass selectively relative to the underlying layer of undoped SiO.sub.2 and using the underlying layer of undoped SiO.sub.2 as an etching stop.
U.S. Pat. No. 5,314,843 disclosed a method for planarizing a semiconductor wafer using the chemical-mechanical polishing process. The method included the steps of (1) masking the semiconductor wafer surface layer to define first and second laterally adjacent portions; (2) altering only the first portion of the surface layer of material to polish at a different removal rate in the chemical-mechanical polishing process than the second portion of the surface layer; and (3) polishing the surface in the chemical-mechanical polishing process. As discussed before, the method disclosed in the '843 patent may minimize the dishing effect, but it requires an additional expensive photolithography step.