1. Field of the Invention
The present invention relates an erroneous operation protection circuit for preventing an erroneous operation due to coupling noises in a large scale integrated circuit (LSI) in which data bus wirings are aligned in close vicinity to each other on a semiconductor chip, and a large scale integrated circuit (LSI) into which the erroneous operation protection circuits are incorporated.
2. Description of the Prior Art
In recent years, according to the progress of fine pattern technology and the request for improvement in system performance, the large scale integrated circuit (LSI) is manufactured on a larger scale and is operated at a higher speed. FIG. 1 shows an example of a microprocessor in which a plurality of circuit blocks 101, 191 are aligned on a semiconductor chip (LSI chip) 100. As shown in FIG. 1, a data bus wiring 110 to which the circuit blocks 101, 191 are connected is disposed between a plurality of sender (transmitter) side circuit blocks 101 and a receiver side circuit block (or the next stage circuit block) 191. This kind of the data bus wiring 110 is provided to correspond to a bit width which is processed simultaneously by the LSI chip 100 and provided in parallel at as narrow pitches as possible to reduce a wiring area. A wiring length of the data bus wiring 110 becomes long since the data bus wiring 110 extends over a plurality of circuit blocks 101, 191 on LSI chip.
Conversely, in order to improve the device packing density on a single LSI chip, wiring widths and wiring intervals of the metal wirings in the LSI chip are reduced year after year. However, a certain lower limit value is set to thicknesses of the metal wirings because the wiring resistance must be maintained small. In other words, the thicknesses of the metal wirings cannot be reduced below the lower limit value and therefore only an interval between both metal wirings is reduced while mutually opposing areas are kept at a certain value. Thus, there is a tendency to increase capacitance between mutually neighboring data bus wirings. Therefore, a rate of capacitance (wiring capacitance) between adjacent data bus wirings to a total wiring capacitance of the LSI is increased. In this manner, the capacitance between the two adjacent data bus wirings in the LSI corresponding to adjacent bits is extremely high and therefore influence of the coupling (coupling noises) between data on the concerned adjacent bits becomes large when the potential level of one of the adjacent bits is swinged.
In the prior art, as a system driving the data bus wirings, there has been known "a CMOS system" in which the potential level of respective wirings are swinged between a power supply level ("H" level) and a ground level ("L" level) with the use of circuits made of n-MOSFETs and p-MOSFETs being connected in series between the power supply and the ground. As another system driving the data bus wirings, "a precharge type system" in which respective wirings are set to the power supply level beforehand and then the n-MOSFETs arranged in the circuit block are turned ON only when the signal propagates the data bus at the ground level is also known. The precharge type system has such excellent features rather than the CMOS system that (1) no Miller effect is caused, and (2) direction of data transition is constant and thus optimization for the transition direction can be implemented in circuit design.
FIG. 2 is a circuit diagram showing an example of the precharge type system, or a configuration of precharge type data bus wirings, which are generally used as the data bus wirings in the prior art. In FIG. 2, data bus wirings 110n-1, 110n, 110n+1 to which a plurality of circuit blocks 101 are connected have a function of propagating output data from the circuit blocks 101 to input buffers 111 of the circuit block 191 respectively. In respective circuit blocks 101, n-MOSFETs 102 for driving the data bus wirings 110n-1, 110n, 110n+1 into an "L" level are provided. Precharge circuits 112 for setting respective data bus wirings into an "H" level beforehand and latch circuits 113 for holding the data when the data bus wiring is at the "H" level are connected to the data bus wirings 110n-1, 110n, 110n+1.
In turn, an operation of the circuit shown in FIG. 2 will be explained. The data bus wirings 110n-1, 110n, 110n+1 are set to the "H" level by the precharge circuits 112 in advance. When one of the plurality of circuit blocks 101 transfer the data via the data bus wirings 110n-1, 110n, 110n+1, respective precharge circuits 112 are turned OFF. When the circuit block outputs the "L" level, the circuit block 101 for transferring the data renders the n-MOSFET 102 to turn ON and thus drive the corresponding data bus wiring into the "L" level. On the contrary, when one of the circuit blocks 101 outputs data at the "H" level, the latch circuit 113 continues to hold the "H" level of the corresponding data bus wiring while the corresponding n-MOSFET 102 in the circuit blocks 101 is kept in its OFF state. Thereby, the concerned data bus wiring can propagate the "H" level. As a consequence, the input buffers 111 of the circuit block 191 positioned on the preceding stage can receive desired data OUT.sub.n-1, OUT.sub.n, OUT.sub.n+1.
However, if the integration density of the LSI is improved, as described above, capacitances 114 between the two adjacent wirings are increased in the circuit shown in FIG. 2 and thus capacitances between the two adjacent wirings are increased rather than the capacitance between the data bus wirings 110n-1, 110n, 110n+1 and the ground level. In this case, even if the LSI circuit is designed such that one of the data bus wirings is driven into the "L" level and the adjoining data bus wiring is held at the "H" level by the latch circuit 113, the adjoining data bus wiring to be held at the "H" level is shifted into the "L" level due to influence of the coupling therebetween. As a result, data at the "L" level is transferred to the gate in the circuit block 191 to cause the erroneous operation.
As the countermeasure for such disadvantage, there is a method wherein transition to the "L" level can be prevented by increasing a driving force of the latch circuit 113 rather than the force generated by the influence of the coupling between two adjacent data bus wirings. However, in this case, when the circuit block 101 outputs the "L" level onto the data bus wirings, the latch circuits 113 drive the data bus wirings strongly into the "H" level. As a result, there is such a disadvantage that collision of data happens and the delay of data is caused.
As a method of preventing erroneous operation by avoiding such collision of data, as shown in FIG. 3, a method has been proposed wherein the data bus wirings 110n-1, 10n, 10n+1 are driven by tri-state buffers 103 in respective circuit blocks 101. The tri-state buffers 103 can drive respective data bus wirings 110n-1, 10n, 10n+1 into the "L" level, the "H" level, or its floating state. In the example shown in FIG. 3, when the data bus wirings 110n-1, 10n, 10n+1 are precharged or when the circuit blocks are inactivated, the tri-state buffers 103 are brought into their non-output state not to drive the data bus wirings 110n-1, 10n, 10n+1. Only when the circuit blocks are activated to output the data, the tri-state buffers 103 can drive the data bus wirings into the "L" level or the "H" level according to the data.
As in the above circuit example shown in FIG. 2, respective data bus wirings 110n-1, 10n, 110n+1 are set to the "H" level in advance and data on the data bus wirings are shifted only when the data is at the "L" level, nevertheless the data bus wirings to be held at the "H" level are driven into the "H" level by the tri-state buffers 103 in the circuit blocks 101 which are activated. Hence, even if data transition is caused due to the coupling between the adjacent data bus wirings, the tri-state buffers 103 drive strongly the data bus wiring to the "H" level. Therefore, transition of data to the "L" level can be suppressed and also erroneous operation can be prevented.
However, in the circuit shown in FIG. 3, the tri-state buffers, each having a driving force larger than the force generated by the influence of the coupling, must be provided according to the number of the circuit blocks. This is because such tri-state buffers must be arranged in or near respective circuit blocks since the tri-state buffers need the output signals of respective circuit blocks. In the event that the tri-state buffers are connected to the data bus wirings according to the number of the circuit blocks, the number of transistors constituting the tri-state buffers is of course increased. Therefore, junction capacitances of the transistors are increased as a whole and total parasitic capacitances of the data bus wirings are increased. As a consequence, stray capacitance of the data bus wirings are increased so that wiring delay is increased. In addition, in case the length of the data bus wirings are extremely prolonged to the extent that special variation in the signal level is caused due to the wiring delay on the same data bus wiring, it is difficult to suppress the coupling noises at only one location on the data bus wiring.
Like the above, in the prior art, there has been a problem that a large number of tri-state buffers must be prepared to suppress the coupling noises and thus stray capacitances of the data bus wirings are significantly increased to increase the wiring delay.