Communication systems employ coding to ensure reliable communication across noisy communication channels. These communication channels exhibit a fixed capacity that can be expressed in terms of bits per symbol at certain signal to noise ratio (SNR), defining a theoretical upper limit (known as the Shannon limit). As a result, coding design has aimed to achieve rates approaching this Shannon limit. One such class of codes that approach the Shannon limit is Low Density Parity Check (LDPC) codes.
Traditionally, LDPC codes have not been widely deployed because of a number of drawbacks. One drawback is that the LDPC encoding technique is highly complex. Encoding an LDPC code using its generator matrix would require storing a very large, non-sparse matrix. Additionally, LDPC codes require large blocks to be effective; consequently, even though parity check matrices of LDPC codes are sparse, storing these matrices is problematic.
From an implementation perspective, a number of challenges are confronted. For example, storage is an important reason why LDPC codes have not become widespread in practice. One of the major issues in LDPC decoding is the organization of memory. Recognizing the fact that the larger the memory size, the lower is the cost of per bit, there is motivation to the investigate of code architectures that allow efficient lumped memory structure for the large amount of edge values in a LDPC decoder.
Also, a key challenge in LDPC code implementation has been how to achieve the connection network between several processing engines (nodes) in the decoder. Further, the computational load in the decoding process, specifically the check node operations, poses a problem.
It is recognized that, in general, a code corresponding to set number of parallel engines cannot be reconfigured to accommodate different numbers of parallel engines such that an efficient memory architecture is maintained. Because different applications require different decoding speeds, this inflexibility presents a serious drawback. Also, this constraint hinders the ability to adopt and exploit advancements in semiconductor capabilities. For instance, as processing power increases, the number of parallel engines needed for a given decoding speed should reduce; however, the design of a fixed number of engines does not permit a straightforward reduction in the number of processors utilized.
Therefore, there is a need for a LDPC communication system that employs efficient decoding processes. There is also a need to minimize storage requirements for implementing LDPC coding. There is a further need for a decoding scheme that can readily accommodate future technological advancements.