1. Field of the Invention
This invention relates to memory circuits, and more particularly to a memory cells formed from floating-body transistors and their applications.
2. Description of the Related Art
Integrating memory circuits (e.g., caches) on microprocessor dies is a power efficient way of achieving higher performance. In fabricating these dies, a direct correlation exists between memory cell density and performance; that is, performance generally increases with the number of cells in the memory. The degree of integration that can be achieved is not limitless and most often is constrained by memory type, the limited die space available for accommodating the memory circuits, and manufacturing costs as well as other practical considerations.
One memory type that has been proposed for integration onto a microprocessor die is SRAM memory. When implemented in large caches, each SRAM memory cell uses six transistors to read and write the data therein. This six-transistor configuration consumes considerable die space and thus leads to low memory cell density. This, in turn, places a significant limitation on microprocessor system performance, and for at least these reasons using SRAM cells to fabricate on-die caches is considered to be less than optimal.
Another memory type proposed for integration onto a microprocessor die is DRAM memory. As shown in FIG. 1, a conventional DRAM cell uses one transistor T and one capacitor C to control the storage of data therein. Switching of the transistor is controlled by the voltage state of a word line WL and data is conveyed along a bit line BL via a sense amplifier. Because fewer components are used, an on-die cache formed from this so-called 1T/1C structure has far greater cell density and data storage capacity than SRAM memory. In fact, DRAM cells can be ten times smaller in area compared with SRAM cells. For this reason, DRAM has been favored by chip designers over other types of memory for forming caches on microprocessor dies.
While they are favored, conventional DRAM caches are not without drawbacks. For example, the switching transistor and storage capacitor in each cell are implemented as separate elements. This necessarily reduces the cell density of the memory, which has an adverse affect on system integration and performance. Also, costly processing steps are required to make a capacitor in each cell that can store enough charge to maintain reasonable refresh times (e.g., typically at least 25 ff is needed).
A need therefore exists for a memory cell which has a higher density than other cells which have been proposed and which therefore may be relied on to improve, for example, the on-die integration of caches in microprocessor systems. A need also exists to construct a memory cell of this type at low cost using existing manufacturing technologies.