Types of non-volatile memory such as NAND memory typically suffer from a limited number of program/erase cycle counts before these types of memory perform unacceptably and/or become unreliable. For example, some types of NAND memory store charge on a floating gate that is surrounded by an insulating oxide layer to keep the charges trapped. NAND memory operations depend on the quality of the oxide layer between a memory cell channel and the floating gate. As program/erase cycle counts increase the oxide layer progressively wears down or degrades due to charges (electrons/holes) flowing through the oxide layer at each program/erase cycle. This oxide layer degradation may result in slower erase operations, higher bit-error rates (BER) during programming and charge leakage from the floating gate. All three of these symptoms of oxide layer degradation may limit NAND memory endurance.
NAND memory endurance may also be limited by charge trapped in an oxide above a lightly doped drain (LDD) region of a NAND memory cell. Trapped charges may cause an apparent increase in resistance of a memory string (bitline). In a worst case, no current passes through the memory string and the memory string may appear as an open circuit. Appearing as an open circuit may lead to all bits on that memory string to read as programmed “0” even after erase operations. As a result of always reading as programmed, these memory cells will no longer be used.