In recent years, a higher integration of a semiconductor device requires the narrower wiring and the multilayer wiring, and hence it is necessary to make a surface of a semiconductor substrate highly planarized. Specifically, finer interconnections in highly integrated semiconductor devices have led to the use of light with shorter wavelengths in photolithography, so that a tolerable difference of elevation at the focal point on the substrate becomes smaller in the light with shorter wavelengths. Therefore, a difference of elevation at the focal point should be as small as possible, i.e., the surface of the semiconductor substrate is required to be highly planarized. One customary way of planarizing the surface of the semiconductor substrate is to remove irregularities (concaves and convexes) on the surface of the semiconductor substrate by a chemical mechanical polishing (CMP) process.
In the chemical mechanical polishing process, after a surface of a semiconductor substrate has been polished for a certain period of time, the polishing process should be finished at a desired position or timing. For example, some integrated circuit designs require an insulating film (layer) of SiO2 or the like to be left on a metallic interconnection of copper, aluminum, or the like. Since a metallic layer or other layers are further deposited on the insulating layer in the subsequent process, such an insulating layer referred to as an interlayer. In this case, if the semiconductor substrate is excessively polished, the lower metallic layer is exposed on the polished surface. Therefore, the polishing process needs to be finished in such a state that a predetermined thickness of the interlayer remains unpolished.
According to another polishing process, interconnection grooves having a certain pattern are formed in a surface of a semiconductor substrate, and after a Cu layer is deposited on the semiconductor substrate, the interconnection grooves are filled with copper or copper alloy, and then unnecessary portions of the Cu layer are removed by a chemical mechanical polishing (CMP) process. Specifically, the Cu layer on the semiconductor substrate is selectively removed by the chemical mechanical polishing process, leaving only the Cu layer in the interconnection grooves. More Specifically, the Cu layer is required to be removed until an insulating layer of SiO2 or the like is exposed in surfaces other than the interconnection grooves.
Further, in some cases, interconnection grooves for a predetermined wiring pattern are formed in a semiconductor substrate, conductive materials such as copper (Cu) or copper alloy are filled in such grooves of the semiconductor substrate, and then unnecessary portions of the conductive materials on the surface of the semiconductor substrate are removed by a chemical mechanical polishing (CMP) process. When the copper layer is polished by the CMP process, it is necessary that the copper layer on the semiconductor substrate be selectively removed therefrom in such a state that the copper layer is left in the grooves for a wiring circuit, i.e. the interconnection grooves. More specifically, the copper layer on those surfaces of the semiconductor substrate other than the interconnection grooves needs to be removed until an insulating layer of SiO2 or the like is exposed on the polished surface.
In such cases, if the semiconductor substrate is excessively polished until the Cu layer in the interconnection grooves is removed together with the insulating layer, then the resistance of the circuits on the semiconductor substrate would be so increased that the semiconductor substrate might possibly need to be discarded, resulting in a large loss of resources. Conversely, if the semiconductor substrate is insufficiently polished to leave the copper layer on the insulating layer, then interconnections on the semiconductor substrate would not be separated from each other as desired, but a short circuit would be caused between those interconnections. As a result, the semiconductor substrate would be required to be polished again, and hence its manufacturing cost would be increased. The above problems also occur when another metallic film of aluminum or the like is formed on a semiconductor substrate and polished by the CMP process.
Therefore, it has been proposed to detect an end point of the CMP process with use of an optical sensor. Specifically, an optical sensor comprising a light-emitting element and a light-detecting element is provided in a polishing apparatus. The light-emitting element of the optical sensor applies light to the polished surface of a semiconductor substrate, and the light-detecting element detects a change in reflectance of the light reflected from the polished surface for thereby measuring the thickness of an insulating layer or a metallic layer on the polished surface. Thus, the end point of the CMP process is detected from the measured film thickness.
In a polishing apparatus for performing the CMP process, a polishing pad mounted on the upper surface of a polishing table usually has a low light transparent. Therefore, in the case where light from the optical sensor is to be applied from below the polishing pad to the polished surface of a semiconductor substrate placed on the polishing table, a light-transmittable window having a high light transmittance for allowing light to pass therethrough is provided in the polishing pad, and light from the optical sensor is applied through the light-transmittable window to the polished surface of the semiconductor substrate.
FIG. 1 is an enlarged fragmentary cross-sectional view showing a conventional double-layer polishing pad including a light-transmittable window. As shown in FIG. 1, a polishing pad 310 comprises an upper-layer pad 311 and a lower-layer pad 312. The upper-layer pad 311 has a hole 311a defined therein, and a light-transmittable window 341 is disposed in the hole 311a of the upper-layer pad 311. The lower-layer pad 312 has a light passage hole 312a defined therein. The light passage hole 312a has a diameter smaller than the hole 311a. The holes 311a, 312a having different diameters provide a step 313 therebetween.
The conventional polishing pad 310 is manufactured as follows: An adhesive agent is applied to the lower surface of the upper-layer pad 311 and the upper surface of the lower-layer pad 312, and the upper-layer pad 311 and the lower-layer pad 312 are vertically pressed against each other. Thus, the upper-layer pad 311 and the lower-layer pad 312 are bonded to each other. Then, the light-transmittable window 341 is fitted into the hole 311a. The light-transmittable window 341 is bonded to the lower-layer pad 312 by the adhesive agent applied to the upper surface of the step 313.
However, since the light-transmittable window 341 is bonded to the lower-layer pad 312 only at the upper surface of the step 313, its bonded area and hence bonding strength is small. Therefore, the light-transmittable window 341 may possibly be peeled off the polishing pad 310. Depending on the forces applied to the polishing pad 310, the light-transmittable window 341 may not be peeled off in its entirety, but may partly be peeled off and a gap is produced between the light-transmittable window 341 and the lower-layer pad 312 or the step 313. The gap thus formed permits a polishing liquid used on the upper surface of the polishing pad 310 to leak onto the lower surface of the light-transmittable window 341. When the polishing liquid is attached to the lower surface of the light-transmittable window 341, the reflectance of the light-transmittable window 341 is greatly reduced, thereby making it difficult to detect a change in reflectance of the polished surface of the semiconductor substrate with the optical sensor. In this case, the film thickness of the semiconductor substrate cannot be measured with high accuracy.
If the polishing liquid is introduced into the gap between the light-transmittable window 341 and the step 313, then a region where the elasticity is not uniform is produced in the polishing pad 310 due to the swelling thereof. This region may adversely affect the polishing process of the semiconductor substrate. Furthermore, if the polishing liquid having a low transparent is irregularly introduced into between the light-transmittable window 341 and the optical sensor, then signals detected by the optical sensor become unstable, making the detected result less reliable.
As described above, the light-transmittable window 341 is fitted in the hole 311a defined in the upper-layer pad 311. The hole 311a has dimensions slightly greater than the light-transmittable window 341 to allow the light-transmittable window 341 to easily be fitted in the hole 311a. Therefore, after the light-transmittable window 341 has been placed in the hole 311a, there is a small gap 314 between the light-transmittable window 341 and the hole 311a. Accordingly, the polishing liquid tends to be introduced into the small gap 314 and become solidified in the small gap 314. The solidified polishing liquid may cause scratches on the semiconductor substrate which is polished on the upper surface of the polishing pad 310.