1. Field of the Invention
The present invention relates to a semiconductor chip package, and relates more particularly to a stacked multichip package.
2. Description of the Related Art
Integration of multiple stacked chips into a single package can increase electronic component package density and reduce the signal distances between electronic components. In other words, the integration technique can not only decrease the total volume required to prepare for individual chips, but can also improve the integral performance of the chips. Among the techniques for packaging multiple stacked chips, the package technique for multiple stacked chips of the same size is one of the most common package techniques.
In the package technique for multiple stacked chips of the same size, a plurality of chips of the same size are stacked one upon another on a substrate and the active surfaces of the chips usually face upward for convenient to wire bond. To prevent bonding wires of a lower chip from being damaged or shorted by an upper chip, interposers are provided between the chips. The height of each interpose should be greater than the loop heights of the corresponding bonding wires. Conventionally, the interposer can be a polyimide tape, a dummy chip, a metal piece, etc.
However, using interposers requires additional processes such as, for example, a chip attach adhesive coating process, a chip mounting process, and a curing process. Such additional processes increase manufacturing cost and risk lowering manufacturing yield.
Specifically, manufacturing yield is an important consideration in the production of multiple chip packages. When multiple chips are packaged into an encapsulation body, the result of composite manufacturing yields greatly influences manufacturing cost. In particular, when the encapsulation body includes a high-priced chip, the risk of low manufacturing yield is more important. If a low price chip in the encapsulation body malfunctions or if a chip is damaged during the chip stacking process, the high-priced chip will have to be discarded with the nonfunctional chip, and such discard causes serious impact to the manufacturing cost.
Thus, in light of the trend of multiple chip package development and the high cost risk of multiple chip packages, a low cost and high manufacturing yield multichip package structure is required by the packaging industry.