1. Field of the Invention
The invention relates to a locking detection circuit used in a PLL (phase locked loop) frequency synthesizer for detecting whether the PLL is locked.
2. Description of the Related Art
Referring to FIG. 1, a conventional PLL frequency synthesizer 10 comprises a reference frequency demultiplier counter 11, a comparison frequency demultiplier counter 12, a phase comparator 13, a charge pump 14, a low pass filter (hereafter abbreviated as LPF) 15, a voltage controlled oscillator (hereafter abbreviated as VCO) 16 and a lock detection circuit 17.
The reference frequency demultiplier counter 11 produces a reference signal fr from a signal of generated by a crystal oscillator 18 through frequency demultiplication. The comparison frequency demultiplier counter 12 produces a compared signal fp obtained from an output signal fv from the VCO 16 through frequency demultiplication. The phase comparator 13 produces a first and a second phase difference signals xcfx86R, xcfx86P in accordance with a phase difference between the reference signal fr and the compared signal fp. On the basis of both phase difference signals xcfx86R, xcfx86P through the operations of the charge pump 14 and the LPF 15, the magnitude of voltage of a control signal VT which is input to the VCO 16 is changed. The PLL circuit 10 also operates to lock the frequency of the output signal fv from the VCO 16 to a desired frequency.
The lock detection circuit 17 receives the first and second phase difference signals xcfx86R, xcfx86P from the phase comparator 13, and also receives a reference clock signal CK from the reference frequency demultiplier counter 11 which is obtained by the frequency demultiplication of the signal of from the crystal oscillator 18 at a given ratio. The lock detection circuit 17, which operates in synchronism with the reference clock signal CK, detects whether the output signal fv is locked on the basis of the first and second phase difference signals xcfx86R, xcfx86P, and generates a locking detection signal LD having a level which depends on the result of such detection.
Referring to FIG. 2, there is shown a specific circuit arrangement of the lock detection circuit 17. As shown, the lock detection circuit 17 includes a NAND circuit 21 that receives the first and the second phase difference signals xcfx86R, xcfx86P from the phase comparator 13 and provides an output signal S1 corresponding to the phase difference which is represented by each pulse width of the signals xcfx86R, xcfx86P. A data flip-flop circuit (hereafter referred to as FF circuit) 22 has a data terminal D for receiving the output signal S1 and a clock terminal CK for receiving the reference clock signal CK, and delivers an output signal S2 corresponding to the output signal S1 at its output terminal Q in synchronism with the rising edge of the reference clock signal CK.
A NAND circuit 23 receives the signals S1, S2, and delivers its to an inverter circuit 24. An inverted signal S3 is supplied to a data terminal D of an FF circuit 25 from the inverter circuit 24.
The FF circuit 25 has a clock terminal for receiving the reference clock signal CK, and provides an output signal S4 at its output terminal Q which depends on the inverted signal S3 in synchronism with the rising edge of the reference clock signal CK.
An inverter circuit 30 receives the output signal S4 and generates an inverted signal S4a. A synchronous counter is formed by a plurality of FF circuits 27, 28, 29. The first stage FF circuit 27 has a data terminal D, to which the inverted signal S4a is applied. Each of the FF circuits 27 to 29 has a clock terminal, to which an inverted signal S1a, formed by an inverter circuit 26 with the signal S1, is applied. The FF circuit 27 delivers an output signal S5 at its output terminal Q in synchronism with the rising edge of the inverted signal S1a (or the falling edge of the signal S1). The FF circuit 28 has a data terminal D, to which the output signal S5 is applied, and delivers an output signal S6 at its output terminal Q in synchronism with the falling edge of the output signal S1. The FF circuit 29 has a data terminal D, to which the output signal S6 is applied, and delivers an output signal S7 at its output terminal Q in synchronism with the falling edge of the output signal S1. The output signals S5, S6, and S7 are input to a NAND circuit 31, which then delivers the locking detection signal LD.
In the lock detection circuit 17, when one or both of the phase difference signals xcfx86R, xcfx86P has an L level, the NAND circuit 21 delivers the signal S1 which has an H level. The phase difference signals xcfx86R, xcfx86P each have a pulse width which is related to a phase difference between the reference signal fr and the compared signal fp, as will be further described later. Accordingly, the NAND circuit 21 delivers the signal S1 of the H level for a time interval corresponding to the phase difference between the signals fr, fp. The greater the phase difference between the signals fr, fp, the longer the pulse width of the signal S1 or vice versa.
The lock detection circuit 17 detects whether the PLL circuit 10 is locked on the basis of the number of rising edges of the reference clock signal CK which are input during a time interval corresponding to the pulse width of the output signal S1 or a time interval during which the NAND circuit 21 delivers the output signal S1 having the H level, and delivers the locking detection signal LD having a level which depends on the result of such detection. Thus it will be seen that the lock detection circuit 17 requires the reference clock signal CK of a higher frequency than the frequencies of the reference signal fr and the compared signal fp. Hence, the reference frequency demultiplier counter 11 produces the reference clock signal CK by the frequency demultiplication at a ratio which is less than the ratio of frequency demultiplication applied to the reference signal fr. Alternatively, the reference frequency demultiplier counter 11 may deliver the input crystal oscillator signal of directly as the reference clock signal CK.
The synchronous counter delivers the locking detection signal LD having an H level only when a phase coincidence is reached between the reference signal fr and the compared fp a number of times which is equal to the number of counter stages or more. This prevents the locking detection signal LD having the H level from being delivered from the lock detection circuit 17 for an accidental phase coincidence between the both signals fr, fp.
Digital mobile equipment generally requires the output signal fv of a higher frequency than analog mobile equipment, and consequently, the PLL circuit 10 produces the reference signal fr and the compared signal fp of higher frequencies, which then approach the frequency of the reference clock signal CK. This may result in a malfunctioning of the lock detection circuit 17.
For example, if the PLL circuit is locked between two consecutive rising edges of the reference clock signal CK, the lock detection circuit 17 may be unable to detect the locked condition, thus undesirably delivering the locking detection signal LD having the L level. Because the locking detection signal LD is used in controlling the charge pump 14, the LPF 15 or other external circuit, there are adverse influences upon the operation of the entire PLL circuit or external circuit, causing instability in the operation of the mobile equipment.
An object of the present invention is to provide a lock detection circuit and a PLL frequency synthesizer capable of reliably detecting a locked condition.
To achieve the above objective, the present invention provides a lock detection circuit for detecting whether a phase of a compared signal is locked with that of a reference signal based on first and second phase difference signals that represents a phase difference between the reference signal having a reference frequency and the compared signal having a preset frequency, the lock detection circuit comprising: a clock generating unit for receiving the first and the second phase difference signals and generating a detecting clock signal in synchronism with one of the first and the second phase difference signals, based on the first and the second phase difference signals; and a lock detecting unit for receiving the first and the second phase difference signals and the detecting clock signal, and detecting whether the phase of the compared signal is locked with the pulse of the reference signal based on the relationship between the detecting clock signal and the phase difference between the first and the second phase difference signals, and generating a lock detecting signal.
The present invention further provides a PLL synthesizer comprising: a voltage control oscillator for generating a frequency signal corresponding to a value of a control voltage signal; a comparison frequency demultiplier for generating a compared signal by frequency-demultiplying the frequency signal from the voltage control oscillator; a reference frequency demultiplier for generating a reference signal by frequency-demultiplying an oscillation signal; a phase comparator for receiving the reference signal and the compared signal to compare the phases thereof, and generating first and second phase difference signals, representing a relationship between the reference signal and the compared signal, based on a result of the phase comparison; a charge pump for converting the first and the second phase difference signals from the phase comparator to voltage signal; a low pass filter for receiving the voltage signal from the charge pump and generating the control voltage signal provided to the voltage control oscillator; and a lock detection circuit for detecting whether a phase of the compared signal is locked with a phase of the reference signal based on the first and second phase difference signals and generating a lock detecting signal, the lock detection circuit comprising: a clock generating unit for receiving the first and the second phase difference signals and generating a detecting clock signal in synchronism with one of the first and the second phase difference signals, based on the first and the second phase difference signals; and a lock detecting unit for receiving the first and the second phase difference signals and the detecting clock signal, and detecting whether the phase of the compared signal is locked with the phase of the reference signal based on the relationship between the detecting clock signal and the phase difference between the first and the second phase difference signals, and generating a lock detecting signal.
The present invention provides a lock detection circuit for use with a PLL frequency synthesizer for detecting a locked condition of the synthesizer, the synthesizer including a phase comparator which receives a reference signal and a compared signal and generates first and second phase difference signals therefrom, the lock detection circuit comprising: a phase difference detector which receives the first and second phase difference signals and generates a third phase difference signal which depends on a pulse width of each of the first and second phase difference signals; a clock generator circuit which receives the first and second phase difference signals and produces a detection clock signal synchronized with the third phase difference signal; a plurality of delay circuits connected in parallel with each other and in series with the phase difference detector, each of the delay circuits receiving the third phase difference signal and delaying the third phase difference signal by a different delay time; a plurality of switches connected in series with the plurality of delay circuits; a flip-flop circuit having a data input connected to the delay circuits for receiving the third phase difference signal delayed by a predetermined time period, a clock input connected to the clock generator circuit for receiving the detection clock signal, and a data output for providing a status signal, wherein one of the plurality of switches is selectively turned on to delay the third phase difference signal by a selected predetermined time period; and a locking counter connected to a data output of the flip-flop circuit for receiving the status signal and connected to the clock generator circuit for receiving the detection clock signal, the locking counter counting a number of pulses of the detection clock signal while the status signal is at a predetermined level and generating a locking detection signal therefrom, the locking detection signal indicating locked condition of the synthesizer.