The present disclosures relate generally to semiconductor memories, and more particularly, to semiconductor memories with recessed devices.
As bitcell size for static random access memories (SRAMs) continues to scale to smaller sizes, the bitcell current (Icell) performance degrades. In addition, static noise margin (SNM) variation of the bitcell increases. Together, the degradation of Icell performance and the increase in SNM variation limits the low supply voltage (Vdd) operation of the bitcell.
Some SRAM devices have been known to achieve a higher bitcell current, however, the SRAM's beta ratio (i.e., the ratio of strength of the pull-down device to the pass device) suffers negatively. As a result, the adverse impact on the SRAM beta ratio degrades the SNM and makes the bitcell unstable at low Vdd operation. Still further, the bitcell may be unstable even at nominal Vdd operation. Furthermore, with scaling to smaller and smaller sizes, transistor threshold voltage (Vt) variation increases due to dopant fluctuations and variations in gate length.
Accordingly, it would be desirable to provide an improved memory for overcoming the problems in the art, as discussed above.