1. Field of the Invention
The present invention relates to a high speed charge balancing comparator and, more particularly, to an improved charge balancing comparator having a substantially reduced response time whereby the speed of operation of the comparator is greatly improved.
2. Description of the Prior Art
Charge balancing comparators have been known and used for several years. The charge balancing comparator operates on the principle that the net charge onto its input nodes from two or more sources will cause either a positive or a negative voltage swing at the input charge balancing node. The state of the output of the comparator will depend on the polarity of the change of the voltage at this node. The comparator does not respond to the absolute value of the voltage at this node. At a suitable time, the output node is interrogated to see if it has swung in either a positive or a negative direction and this information is stored elsewhere.
This type of comparator is becoming increasingly popular in successive approximation analog-to-digital (A/D) converters using MOS or CMOS semiconductor integrated circuit technologies (although its use is not limited to these applications). One of the principle goals of any A/D converter is usually to minimize its time for making a conversion and most converters are ultimately limited in their high speed operation by the speed of their comparators.
Previous designs of comparators have been limited in speed of response due to the settling time of the input charge balancing node. The initial incorrect voltage on the input charge balancing node causes the output of the comparator, together with its internal nodes, to be disturbed significantly such that when the input charge balancing node does finally settle to its correct value, the comparator must first correct the internal node voltages, resulting in a long total response time at its output.
A better understanding of this problem can be derived with reference to FIG. 1, which shows a schematic diagram of a typical charge balancing comparator, generally designated 10, and to FIG. 2, which shows a series of waveforms as a function of time which are useful in understanding the operation of comparator 10. For purposes of discussion, comparator 10 utilizes an operational amplifier 11 as the gain element. However, in practice, because of speed limitations, other configurations will almost always be used. Switches S.sub.1, . . . S.sub.N apply voltages V.sub.1, . . . V.sub.N, respectively, via capacitors C.sub.1, . . . C.sub.N, respectively, to input node A of operational amplifier 11. Similarly, switches S.sub.11, . . . S.sub.NN apply voltages V.sub.11, . . . V.sub.NN, respectively, via capacitors C.sub.1, . . . C.sub.N, respectively, to input node A. An autozero switch S.sub.AZ connects the inverting input of amplifier 11 to its output. Switches S.sub.1, . . . S.sub.N and S.sub.AZ are controlled by a timing signal shown as waveform 12 in FIG. 2 and switches S.sub.11, . . . S.sub.NN are controlled by a timing signal shown as waveform 13 in FIG. 2. Waveform 14 shown in FIG. 2 is the theoretical output V.sub.OUT of operational amplifier 11.
During the autozero phase, switches S.sub.1, . . . S.sub.N and S.sub.AZ will be closed and switches S.sub.11, . . . S.sub.NN will be open. During this phase, switch S.sub.AZ connects the inverting input of amplifier 11 to its output, thereby putting amplifier 11 into a unity gain configuration. If amplifier 11 is perfect, the voltage V.sub.OUT will be at ground. In practice, because of finite errors such as input offset voltages, V.sub.OUT will be offset from ground potential up to a few millivolts. For the sake of simplicity, it will be assumed that amplifier 11 has no errors and that there are only two input pairs of voltages to be compared, V.sub.1 and V.sub.11 plus V.sub.2 and V.sub.22 (N=2 and NN=22). During the autozero phase, capacitors C.sub.1 and C.sub.2 will be charged to voltages V.sub.1 and V.sub.2, respectively.
During the compare phase, switches S.sub.AZ, S.sub.1 and S.sub.2 are opened and switches S.sub.11 and S.sub.22 are closed. The voltage V.sub.A at the input node A to amplifier 11 will eventually assume a voltage V.sub.A : ##EQU1## It can be seen that V.sub.A can have any real positive or negative value depending on the magnitude of C.sub.1 and C.sub.2 and the magnitudes and polarities of (V.sub.11 -V.sub.1) and (V.sub.22 -V.sub.2).
The output voltage V.sub.OUT will respond after a finite time to the new value of V.sub.A. For example, if voltage V.sub.A has acquired a negative shift of value compared to that during the autozero phase, V.sub.OUT will swing by a positive amount as shown as waveform 14 in FIG. 2. At the end of this phase, V.sub.OUT is detected and stored elsewhere (on a capacitor or latch) and the cycle repeated. Each complete cycle is defined as the analog-to-digital conversion time and it is usually desired that this time be as short as possible.
Problems arise in the use of comparator 10 when the mechanical switches shown in FIG. 1 are replaced by MOS switches or the like having finite values of series resistance and when the values in the numerator of equation (1) are different by a very small value to those in the denominator, i.e.: ##EQU2## The problem manifests itself in an initially inaccurate high value of voltage V.sub.A at node A at the beginning of the compare cycle. Although the voltage V.sub.A will finally settle to its correct value, this initial voltage can make the gain element (operational amplifier 11 in FIG. 1) swing its output and internal node voltages to incorrect values such that when the input voltage V.sub.A has settled down to near its correct value and final polarity, the gain element requires significantly more time to correct its output voltage V.sub.OUT and its internal node voltages compared to the case where this initial transient of input voltage had not occurred.
To demonstrate this initial transient, reference should be had to FIG. 3, wherein the input of comparator 10 is modified by eliminating switches S.sub.11 and S.sub.22 and substituting therefore single switches S.sub.1 and S.sub.2 with their respective series resistors R.sub.1 and R.sub.2. Additionally, for the sake of simplicity, switch S.sub.AZ is shown connecting node A to ground during the autozero phase. Switches S.sub.1 and S.sub.2 also connect capacitors C.sub.1 and C.sub.2, respectively, to voltages V.sub.1 and V.sub.2, respectively, during the autozero phase.
The voltage at node A from the beginning of the compare phase is defined by the equation: EQU V.sub.A =V.sub.A(FINAL) +[V.sub.A(INITIAL) -V.sub.A(FINAL) ]e.sup.-A/t, (2)
where t=time, ##EQU3##
It should be noted that the initial value of V.sub.A is solely dependent upon the input differential voltages (V.sub.11 -V.sub.1) and (V.sub.22 -V.sub.2) and the equivalent resistance of R.sub.1 and R.sub.2, that the final value of V.sub.A is solely dependent on the same differential voltages and capacitors C.sub.1 and C.sub.2, and that the time constant for the voltage V.sub.A to change from V.sub.A(INITIAL) towards V.sub.A(FINAL) is dependent on the equivalent RC product of the two resistors R.sub.1 and R.sub.2 in series and the two capacitors C.sub.1 and C.sub.2 in series.
To demonstrate this situation, consider a practical case for an 8-bit A/D converter. The reference voltage (V.sub.11 -V.sub.1) is -2.500 volts and the full scale input voltage (V.sub.22 -V.sub.2) less one least significant bit is (5.000-5.000/256) volts or approximately 4.980 volts. In this example, capacitor C.sub.1 has a value of 10 picofarads, capacitor C.sub.2 has a value of 5 picofarads and the equivalent series resistances R.sub.1 and R.sub.2 of the MOS switches are 2000 ohms each. Inserting these values in equations (5) and (1): ##EQU4## The time constant TC for V.sub.A is defined by: ##EQU5## Between four and five time constants (approximately 14 nanoseconds) are required before voltage V.sub.A assumes approximately its correct value.
This example is shown in FIG. 4 where voltage V.sub.A is plotted as a function of time (curve 15). The ratio of the initial magnitude of voltage V.sub.A is almost 200 times that of its final value. More importantly, its initial polarity is reversed from its final condition. As the example shows, the initial input transient can be of such a high magnitude and sign that it can cause the gain element of the comparator to slam its output into an incorrect state and, often just as undesirable, cause its internal nodes to assume grossly incorrect voltage values such that when the input voltage V.sub.A assumes its correct polarity, at time t.sub.1 in FIG. 4, and then its small terminal magnitude, the internal node and output voltages have to be initially corrected to their autozero values and then to their final values. This produces a delay at the output of the comparator which is usually twice to many times that which would occur if no input transient had been allowed and the input voltage V.sub.A had been connected to the input of the comparator only after the time t.sub.1. Since the speed or response time of the comparator is the limiting factor for A/D converters and other systems using comparators, it is highly desirable to eliminate or reduce the effect of input voltage transients for this family of charge balancing comparators.