1. Field of the Invention
The present invention relates to integrated circuit test apparatus, more particularly, to test systems for so-called system LSIs in which a circuit for implementing one function is formed into a macro in a single integrated circuit together with another circuit.
2. Description of the Related Art
Conventionally, circuits of, e.g., a CPU, a DSP, a DRAM, etc., are respectively mounted as independent devices on different boards. In recent years, as such circuits continue to shrink in feature size and increase in density, so-called system LSIs are increasing in which those circuits are formed as macros and integrated as verified function macros in a single integrated circuit together with other circuits. As an increasing trend, one integrated circuit includes two or more function macros.
In many cases, the layout of a function macro which assembles an independent device into a macro is fixed. It is, therefore, difficult to add a test support circuit such as a so-called logic scan circuit into a function macro later. An operation test for a system LSI including a function macro is often done by a function test of externally supplying an instruction or necessary signal, actually running the function macro, and extracting the processing result outside.
FIG. 1 is a circuit diagram showing a conventional fundamental construction for running a function test on a function macro. FIG. 1 shows only the input side of the function macro as a representative. As shown in FIG. 1, a function macro 100 comprises input terminals IN0, IN1, . . . , INn−1, and INn. Selectors S0, S1, . . . , Sn−1, and Sn are so provided as to correspond to the respective input terminals IN0, IN1, . . . , INn−1, and INn.
Each of the selectors S0 to Sn receives two inputs: a signal (instruction or necessary signal for a function test) input from the external input terminal of an integrated circuit including the function macro 100, in function test operation, and a signal input from a circuit of the integrated circuit other than the function macro 100 in normal operation of the integrated circuit. Each selector selects either of the signals, and supplies the selected one to the corresponding one of the input terminals IN0 to INn of the function macro 100. At this time, the selectors S0 to Sn switch the selection states of two inputs in accordance with control signals input to their control terminals.
More specifically, when the control signal represents that a test mode is set, each of the selectors S0 to Sn selects a signal input from the external input terminal of the integrated circuit in function test operation, and supplies the selected signal to the corresponding one of the input terminals IN0 to INn of the function macro 100. When the test mode is not set, i.e., a normal operation mode is set, each of the selectors S0 to Sn selects a signal input from a circuit of the integrated circuit other than the function macro 100, and supplies the selected signal to the corresponding one of the input terminals IN0 to INn of the function macro 100.
In the construction shown in FIG. 1, the terminal definition is changed by the selectors S0 to Sn to connect all the input terminals IN0 to INn of the function macro 100 to the external input terminals of the integrated circuit in test operation so as similarly to run an existing function test for an independent device on the verified function macro 100 integrated in the integrated circuit.
FIG. 2 is a circuit diagram showing a conventional construction when one integrated circuit includes two different function macros. In the construction shown in FIG. 2, one integrated circuit includes two function macros A and B (101 and 102) and another user logic 103, to which necessary signals are supplied from external input terminals 107 of the integrated circuit to run function tests sequentially. The processing results in the function macros 101 and 102 are output from external output terminals 108 of the integrated circuit to obtain the results of the function tests.
For example, function tests are sequentially run on the function macros 101 and 102, and then a function test is run on the user logic 103. In running a function test on the function macro 101, a select signal is supplied from a function macro A select terminal 104 to the function macro 101. In running a function test on the function macro 102, a select signal is supplied from a function macro B select terminal 105 to the function macro 102. In running a function test on the user logic 103, a signal representing a test mode is supplied from a control signal input terminal 106 to the user logic 103.
In running a function test on the function macro 101, signals input from the external input terminals 107 of the integrated circuit are supplied to the function macro 101. At this time, signals input from some of the external input terminals 107 are supplied to the function macro 101 via selectors 109 each for selectively outputting either of the input signal and a signal processed by the user logic 103. The processing results in the function macro 101 are output outside from the external output terminals 108 of the integrated circuit via selectors 111 each for selectively outputting any of a signal processed by the function macro 101, a signal processed by the function macro 102, and an output signal in normal operation.
In running a function test on the function macro 102, signals input from the external input terminals 107 of the integrated circuit are supplied to the function macro 102. At this time, signals input from some of the external input terminals 107 are supplied to the function macro 102 via selectors 110 each for selectively outputting either of the input signal and a signal processed by the user logic 103. The processing results in the function macro 102 are output outside from the external output terminals 108 of the integrated circuit via the selectors 111. Note that the external output terminals 108 include a dedicated terminal for outputting only a signal processed by, e.g., the function macro 102.
In running a function test on the user logic 103, signals input from the external input terminals 107 of the integrated circuit are supplied to the user logic 103. Signals processed by the user logic 103 are supplied to the function macros 101 and 102 via the selectors 109 and 11 zero the processing results in the function macros 101 and 102 are output outside from the external output terminals 108 of the integrated circuit with or without the mediacy of the selectors 111.
In this construction, external terminals of the integrated circuit connected to only the function macros 101 and 102 are test terminals.
As shown in FIG. 1, an integrated circuit such as a conventional system LSI must be equipped with test terminals (external input terminals) for externally supplying various test signals to the input terminals of a function macro in order to run an existing function test even on a function macro integrated in the integrated circuit. This also applies to output terminals for outputting processing results in a function macro. For this purpose, a large number of external test terminals not used in normal operation must be provided on an integrated circuit, resulting in a highly costly integrated circuit.
As shown in FIG. 2, in an integrated circuit including function macros, the input/output terminals of function macros to be tested are selectively connected to the external test terminals of the integrated circuit to run function tests on the function macros sequentially. This prolongs the time required to test all the function macros.
As a means for preventing an increase in test time, as shown in FIG. 3, function tests are simultaneously run on two function macros 101 and 102 by simultaneously supplying a select signal for selecting function macros from a macro select terminal 112 to the function macros 101 and 102.
In this construction, however, all the input/output terminals of the function macros 101 and 102 must be connected to the external test terminals of the integrated circuit in test operation, to say the least. Thus the number of external test terminals of the integrated circuit must be increased. Such an increase in the number of test terminals greatly increases the cost.