1. Field of the Invention
The present invention relates to integrated circuit fabrication, and more particularly to methods for fabricating high-density integrated circuit devices.
2. Description of Related Art
Photolithographic processes can be used to form a variety of integrated circuit structures on a semiconductor wafer. In photolithography, features of these structures are typically created by exposing a mask pattern (or reticle) to project an image onto a wafer that is coated with light sensitive material such as photo resist. After exposure, the pattern formed in the photo resist may then be transferred to an underlying layer (e.g. metal, polysilicon, etc.) through etching, thereby creating the desired features.
One problem associated with manufacturing devices having very small features arises because of variations introduced by the photolithographic processes. Specifically, resist material properties, process conditions, optical distortions and other factors can cause systematic and random deviations in the etched shapes of the features from their desired shapes. Examples of deviations include corner-rounding, line-shortening and line edge roughness.
In a typical lithographic patterning process, a line of resist is used as an etch mask to create a corresponding line of material in the underlying layer. In such a case, the deviations in the patterned line of resist will be transferred to the critical dimensions of the etched line in the underlying layer. As process technologies continue to shrink, these deviations become a greater percentage of the critical dimension of the etched lines, which can reduce yield and result in significant performance variability in devices such as transistors implemented utilizing these etched lines.
Accordingly, it is desirable to provide high-density structures such as integrated circuit devices which overcome or alleviate issues caused by deviations introduced by photolithographic processes, thereby improving performance and manufacturing yield of such devices.