This invention relates to a reference clock architecture for an integrated circuit device, and particularly for types of integrated circuit devices, such as programmable devices, where a user may specify a clock rate.
Certain types of integrated circuit devices allow users to specify various settings, such as clock rates. In particular, programmable devices, including, for example, programmable logic devices such as field-programmable gate arrays (FPGAs), may allow a user to specify a complete logic configuration, various portions of which may require different clock rates, none of which are known with any certainty at the time of device manufacture. Such devices have been manufactured with circuitry to allow various clock rates to be selected by the user, which may have resulted in overly complex clock networks, including many components that may never be used by a particular user.
For example, such devices may incorporate high-speed serial interfaces to accommodate high-speed (i.e., greater than 1 Gbps) serial I/O standards. Because there are multiple different standards, which may operate at multiple different rates, and because a user may elect to use more than one standard and/or rate, the ability to provide multiple reference clocks may be desirable. Heretofore, this has required the provision of multiple reference clock sources such as phase-locked loops (PLLs) or delay-locked loops (DLLs), with a clock network capable of routing a reference clock signal from any one of those sources to any one of a number of interface circuits.