Semiconductor manufacturers have developed components, such as packages and BGA devices, which contain multiple semiconductor dice. For example, systems in a package (SIP) include multiple dice having different configurations, such as a memory, a processing, or an application specific configuration. The multiple dice provide increased integration, security and performance in a component.
One aspect of these multi-dice components is that they typically have a relatively large peripheral outline and thickness. For example, conventional systems in a package have two or more dice spread out on a common substrate. These components are typically larger than conventional plastic semiconductor packages. It would be desirable to be able to fabricate semiconductor components, such as packages and BGA devices, with multiple dice, but also with a chip scale outline and thickness.
At the same time, components need a reliable and efficient internal signal transmission system, and a high input/output capability. One aspect of conventional chip scale components, such as chip scale packages (CSP), is that they are difficult to manufacture with the reliability required in the industry. For example, some chip scale components include relatively complicated signal transmission systems, such as beam leads and wire conductors. These signal transmission systems are difficult to manufacture, and are prone to failure, particularly at the high pin counts required for demanding electronics applications. It would be desirable for a multi-dice component to have a reliable signal transmission system capable of volume manufacture.
The present invention is directed to a multi-dice component having a chip scale outline, an integrated internal signal transmission system, and a high input-output capability. In addition, the present invention is directed to wafer level methods for fabricating multi-dice, chip scale components.