The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down has also significantly decreased the space separating contact openings (or windows) from adjacent devices of ICs. Contact openings provide contact between various devices and features of the integrated circuit. Due to the scaled down devices and decreased space separation between devices, it has been observed that conventional processing provides a smaller than desirable contact process window, which leads to restrictive processing and design issues. For example, the smaller contact process window results in design rules requiring a minimum spacing between the contact openings and device features (e.g., gate structures), which provides a smaller than desirable margin of contact/gate structure overlay. Further, if the minimum spacing between the contact openings and such device features varies, poor device performance results, such as contact/gate structure short and contact open issues.
Accordingly, what is needed is a method for making a semiconductor device that addresses the above stated issues.