The present invention relates to packages for power semiconductor chips, and, more particularly, to hermetic power chip packages.
Power semiconductor chips (hereinafter, simply "power chips") generate waste heat during operation typically in excess of about one watt. This heat must be removed in order to prevent destruction of the power chip. Power chips are accordingly assembled in a package or arrangement designed to facilitate the removal of heat from the power chip. Hermetic, or airtight, packages are particularly desirable for packaging power chips, since hermetic packages shield the power chips from contaminants and moisture that are known to degrade the operating performance of power chips.
A typical hermetic power chip package that is presently available includes a relatively massive metallic baseplate on which the power chip is thermally mounted, and, which, in turn, is adapted to be thermally mounted upon a metallic heat sink. Two glass-to-metal hermetic seals are typically incorporated in the power chip package to permit electrical access to the power chip via current leads. These glass-to-metal seals are expensive to make, and the use of the metallic baseplate is also expensive. The power chip package additionally includes a housing that hermetically encloses the power chip and one or more of the foregoing glass-to-metal seals resulting in further expense of the package.
The foregoing describes a hermetic power chip package in an essentially completed form, that is, in a form ready for use in circuit applications. Initial electrical testing of power chips has heretofore been carried out by assembling the power chips in completed hermetic power chip packages to provide for removal of waste heat. Such testing is necessary to ascertain important device characteristics, such as, in a power Darlington transistor, the common emitter current gain, H.sub.FE, and the collector-to-emitter voltage at device saturation, V.sub.CE(SAT). If the power chip in a power chip package does not meet the required standards, the entire power chip package is discarded. As a consequence, the testing of power chips in presently available hermetic packages is costly. In order to make testing of power chips more economical, it would be desirable to provide a hermetic power chip package in a partially-completed or building block form, so as to reduce the expense of discarded packages.