1. Field of the Invention
The present invention relates to a demodulation circuit and a demodulating method for demodulating a digital-modulated signal.
2. Description of the Related Art
FIG. 1 is a block diagram of a common QPSK demodulation circuit. A QPSK-modulated signal is received by a tuner not shown in the attached drawings, and converted into an intermediate frequency signal IFin. The intermediate frequency signal IFin is converted by an A/D converter 12 into digital data at the timing synchronous with the sampling clock with a predetermined frequency, and further converted by an IQ separator 13 into a baseband signal formed by an I signal and a Q signal.
The IQ separator 13 includes multipliers 13a and 13b for multiplying the output of the A/D converter 12 by a sine wave and a cosine wave having the frequencies equal to the center frequency of the intermediate frequency signal IFin. Low pass filters (LPF) 14a and 14b remove the upper frequency components of the output of the multipliers 13a and 13b, and the output is transmitted to interpolaters 15a and 15b. 
Each of the interpolaters 15a and 15b is constituted by an FIR (finite impulse response) filter, a thinning circuit, etc., and the data of the original sampling point (symbol timing) is obtained by interpolation from the received data sampled by the A/D converter 12.
Each of the Root Nyquist filters 16a and 16b is constituted by a low pass filter, and restricts the band of the output signal of the interpolaters 15a and 15b. 
A rotor 17 is constituted by a butterfly circuit, etc., advances or delays the phase of a regenerated carrier wave according to the phase difference signal output from a carrier recovery circuit 18, and thereby allows the regenerated carrier wave to be synchronous with the carrier wave of a received signal.
The carrier recovery circuit 18 calculates the phase difference between the signal point on the I and Q phase plane obtained from the I signal and the Q signal and the normal signal point, and outputs the signal in the phase difference decreasing direction to the rotor 17.
A timing recovery circuit 19 calculates the amount of shift of the sampling timing, and output an interpolating tap coefficient to the interpolaters 15a and 15b. 
FIG. 2 shows the configuration of a timing recovery loop. The timing recovery loop is constituted by the interpolaters 15a and 15b and the timing recovery circuit 19.
The timing recovery circuit 19 includes a phase comparator 21, a loop filter 22, a numerical controlled oscillator 23, a thinning control unit 24, and a tap coefficient arithmetic unit 25. The interpolaters 15a and 15b includes Fir filters 26a and 26b, and thinning circuits, 27a and 27b. 
The phase comparator 21 determines whether the value of a received signal at each sampling timing indicates a monotonous increase, a monotonous decrease, or none of them, and outputs a signal depending on a discrimination result.
The loop filter 22 is a completely secondary loop filter, and includes a multiplier 28 constituting a low pass filter, a multiplier 29 constituting a high pass filter, an adder 30 for adding the output of the multiplier 28 to the output of the integrator 31, a limiter 32, an integrator 31, and an adder 33 for adding the output of the integrator 31 to the output of the multiplier 29. The integrator 31 is constituted by a flip-flop, etc. The coefficient α provided for the multiplier 28 is a gain adjustment coefficient for a low pass filter, and the coefficient β provided for the multiplier 29 is a gain adjustment coefficient for a high pass filter.
The numerical controlled oscillator (NCO) 23 includes a flip-flop 34 and an adder 35 for adding the output of the flip-flop 34 to the output of the loop filter 22. The numerical controlled oscillator 23 outputs digital oscillation frequency data according to a signal indicating the shift of the sampling timing output from the loop filter 22.
The tap coefficient arithmetic unit 25 provides a tap coefficient for advance or delay of a phase for the Fir filters 26a and 26b depending on the oscillation frequency data output from the numerical controlled oscillator 23, and outputs the I signal and the Q signal at the original sampling point from the Fir filters 26a and 26b. 
The thinning control unit 24 controls the thinning circuits 27a and 27b, and thins data at an unnecessary sampling point in the data at each sampling point output from the Fir filters 26a and 26b. 
Next, the operation of the phase comparator 21 of the above-mentioned timing recovery loop is explained by referring to the operation explanation shown in FIG. 3.
FIG. 3 shows the analog waveform of the input of the phase comparator 21. FIG. 3A shows the case in which the value of the input signal of the phase comparator 21 at each of the sampling time t−1, t and t+1 indicates a monotonous increase, and FIG. 3B shows the case of a monotonous decrease.
It is determined whether the values of the input signal indicate either a monotonous increase, based on the values of the input signal of the phase comparator 21 at each of the sampling time t−1, t and t+1, which are d(t−1), d(t), and d (t+1), a monotonous decrease, or any other cases, a predetermined arithmetic operation is performed on the value of an input signal at each sampling time based on the determination result, and outputs the arithmetic result as a phase determination result.
The phase comparator 21 outputs a value obtained by the following equation when the values of the adjacent input signal at the sampling time t−1, t, t+1 indicate a monotonous increase.−2×(d(t)+{d(t+1)−d(t−1)}/2)
The phase comparator 21 outputs a value obtained by the following equation when the values of the input signal at the sampling time t−1, t, t+1 indicate a monotonous decrease.2×(d(t)+{d(t+1)−d(t−1)}/2)
Furthermore, the phase comparator 21 outputs “0” when the values of the input signal at the sampling time t−1, t, t+1 do not indicate a monotonous increase nor a monotonous decrease.
FIG. 4A shows the output of the loop filter 22 when the frequency error between the original sampling point (hereinafter referred to as a symbol timing) and the sampling clock is small. FIG. 4B shows the output of the loop filter 22 when the frequency error against the symbol timing is large.
When the frequency error is small, and the values of the input signal indicate a monotonous increase or a monotonous decrease, the phase comparator 21 outputs a value indicated in the above-mentioned equations, and the integrator 31 of the loop filter 22 integrates the values. As a result, for example, as shown in FIG. 4A, the output of the loop filter 22 increases until it reaches the convergence point of the timing recovery loop, and the capturing operation is completed at the convergence point.
On the other hand, when the frequency error is large, the signal points are distributed at random on the I and Q phase plane. Therefore, the average value of the output of the phase comparator 21 is approximately 0. As a result, the output of the loop filter 22 is fixed to a specific value, for example, as shown in FIG. 4B, close to “0”, or is fixed to a specific value.
FIG. 5 shows the value of the limiter 32. When the average value of the output of the phase comparator 21 is approximately 0, the value of the limiter 32 to which an integration result is input is also a constant value.
The characteristic shown by the dotted line in FIG. 4B indicates the desired output characteristic of the loop filter 22 for reaching the convergence point, but the above-mentioned timing recovery circuit 19 cannot realize the capture characteristic as such.
That is, when the timing error is large, the output of the loop filter 22 is fixed to a specific value, and it is hard for the timing recovery circuit 19 to maintain the synchronization of clock timing.
FIG. 6 shows the configuration of the carrier recovery loop for synchronization of the regenerated carrier wave with the carrier wave of a modulated signal.
The carrier recovery loop includes the rotor 17 and the carrier recovery circuit 18. The carrier recovery circuit 18 includes a phase comparator 41, a loop filter 42, a numerical controlled oscillator 43, and a Sin/Cos table 44.
The phase comparator 41 determines the advance or delay of the phase of the signal point on the I and Q phase plane obtained from the I signal and the Q signal to the phase of the normal signal point, and outputs a phase error signal for amendment of the advance or delay of the phase.
The loop filter 42 is a completely secondary loop filter, and includes a multiplier 45 constituting a low pass filter, a multiplier 46 constituting a high pass filter, an adder 47 for adding the output of the multiplier 45 to the output of an integrator 48, a limiter 49, the integrator 48, and an adder 50 for adding the output of the integrator 48 to the output of the multiplier 46. The integrator 48 is constituted by a flip-flop, etc. The coefficient α provided for the multiplier 45 is a gain adjustment coefficient for a low pass filter, and the coefficient β is a gain adjustment coefficient for the high pass filter.
The numerical controlled oscillator 43 includes a flip-flop 51 and an adder 52 for adding the output of the flip-flop 51 to the output of the loop filter 42. The numerical controlled oscillator 43 outputs oscillation frequency data for amendment of the frequency error (phase error) of a carrier.
The Sin/Cos table 44 is a table for generation of a sine wave and a cosine wave corresponding to the oscillation frequency data output from the numerical controlled oscillator 43.
The rotor 17 includes multipliers 53 and 54 for multiplying an I signal by the sine wave and the cosine wave output from the Sin/Cos table 44, multipliers 55 and 56 for multiplying a Q signal by the sine wave and the cosine wave, an adder 57 for adding the output of the multiplier 53 to the output of the multiplier 56, and an adder 58 for adding the output of the multiplier 54 to the output of the multiplier 55. (The output of the multiplier 54 is multiplied by “−1” and input to the adder 58.)
The rotor 17 multiplies the I signal and the Q signal by the sine wave and the cosine wave output from the Sin/Cos table 44 to rotate the signal point by the primary transform, and outputs the I signal and the Q signal at a desired sampling point.
FIG. 7 shows a signal point of the I and Q phase plane (constellation point). The point indicated by the black dot shown in FIG. 7 is a normal signal point, the point indicated by a white dot is a signal point indicating a minus phase difference, and the point indicated by a dot with diagonal lines is a signal point having a plus phase difference. The counterclockwise rotation is a positive rotation and the clockwise rotation is a negative rotation.
The phase comparator 41 outputs a minus error signal when the position of the signal point on the I and Q phase plane determined according to the I signal and the Q signal output from the rotor 17 is detected in a predetermined range of the plus side relative to the position of the normal signal point, and outputs a plus error signal when it is detected in a predetermined range on the plus side on the I and Q phase plane. The phase comparator 41 outputs “0” when the position of the signal point depending on the I signal and the Q signal is detected in the position of the normal signal point.
In the carrier recovery loop, when the frequency error of a carrier is large, a signal point is distributed at random on the I and Q phase plane. Therefore, the average value of the output of the phase comparator 41 is approximately 0. Therefore, there has been the problem that, like the above-mentioned timing recovery loop, the output of the loop filter 42 is fixed to a specific value, and no carrier can be captured.
The patent document 1 describes providing a limiter for outputting an initialization value at the minimum level when the input value becomes larger than the limiter value in the feedback route to prevent pseudo synchronization.
The patent document 2 describes integrating a phase error signal, detecting synchronization by comparing an integrated value with a threshold, and stopping frequency sweep when synchronization is detected.
[Patent Document 1] Japanese Patent No. 2885058
[Patent Document 2] Japanese Patent Publication No. H5-30098