1. Field of the Invention
The present invention generally relates to methods and systems for inspection of an entire wafer surface using multiple channels. Certain embodiments relate to detecting light scattered from different portions of the entire wafer surface using different detection channels.
2. Description of the Related Art
Fabricating semiconductor devices such as logic and memory devices typically includes processing a specimen such as a semiconductor wafer using a number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that typically involves transferring a pattern to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a semiconductor wafer and then separated into individual semiconductor devices.
Wafers may contain defects both in central portions of the wafers as well as in edge portions of the wafers, which includes a relatively narrow region around the periphery of the wafers, and on the outer edge of the wafers. Examples of defects that may be found in the edge portion and on the outer edge of wafers include, but are not limited to, chips, cracks, scratches, marks, particles, and residual chemicals (e.g., resist and slurry). As wafer sizes continue to increase, both wafer and integrated circuit (IC) manufacturers are becoming more concerned about defectivity at or near the wafer edge. The main concerns are that edge defects could fall onto the central part of the wafer thereby causing untraceable yield loss, cross contamination during processing, and/or catastrophic wafer breakage. These yield loss mechanisms are experienced by most wafer and IC manufacturers at one time or another.
Traditionally, wafer inspection tools are designed to inspect a central portion of the wafers (i.e., a surface area of the wafer on which electrical elements will be formed or a surface area of the wafer opposite that on which electrical elements will be formed). Since these areas of the wafer reflect or scatter relatively small amounts of light, such wafer inspection tools are designed to detect relatively small amounts of light. However, near the outer edge of the wafer, relatively large amounts of light may be reflected or scattered from the wafer due to edge features such as a bevel formed at or near the outer edge. As a result, these large amounts of light will saturate the detectors of traditional wafer inspection systems. Consequently, any output signals generated near or at the edge of wafers by such wafer inspection tools are generally unusable. In some instances, the wafer inspection systems may be designed to block the light from reaching the detectors when inspecting near the edge of the wafer to protect the detectors from damage that may be caused by the relatively high intensity light.
Some edge inspection systems are being developed to detect defects at or near the outer edge of wafers. Examples of apparatuses for detecting defects along the edge of electronic media such as semiconductor wafers are illustrated in U.S. Patent Application Publication Nos. 2003/0030050 by Choi and 2003/0030795 by Swan et al., which are incorporated by reference as if fully set forth herein. Due to the substantially different reflecting and scattering characteristics of the outer edge of wafers in comparison to the inner portion of the wafer, such edge inspection systems have substantially different configurations than the traditional wafer inspection tools. Therefore, the edge inspection systems are not optimized to, or even able to, detect defects in the central portion of the wafers. Consequently, if wafer or IC manufacturers want to detect defects in both the central and outer portions of wafer (as is usually the case since defects in either portion may result in expensive yield losses and other problems), they will need to purchase two separate tools. Using two different wafer inspection tools instead of just one inspection tool will obviously increase costs in many ways such as increases in clean room real estate and operating costs, increases in tool maintenance costs, and increases due to reduced throughput. However, since a tool that is capable of inspecting both the inner and outer portions of wafers is not currently available, and due to the increasing costs associated with defect-based yield losses, wafer and IC manufacturers may not be able to avoid the costs associated with multiple, different inspection tools.
Accordingly, it may be advantageous to develop a wafer inspection system that is capable of inspecting substantially an entire surface of wafers including both center and edge portions of the wafers.