A well-known embodiment of a stack arrangement provides for stacking two memory chips within an FBGA package. Here, the lower memory chip, with its active surface area face-down, is integrated into the circuit by means of the conventional Board-on-Chip (BoC) technology and the upper memory chip, with its active surface area face-up, is attached to the lower memory chip and integrated by means of wire bond connections.
Since the electrical connections of the upper memory chip on the carrier substrate must be on the same side as those of the lower memory chip, this stack arrangement for memory chips with bond pads in a double-row arrangement, because of the simultaneous face-up and face-down arrangement in one stack, requires that the individual wire bond connections for the upper memory chip be crossed. In addition to prolonging the signal transit times, this design leads to technical problems because of the potential mechanical, electrical or thermal interactions between the wire bond connections at the crossover points. Another serious disadvantage of this stack arrangement is that bum-in and testing are possible only once the stack arrangement has been completely assembled, which leads to a relatively high loss rate which amounts to approximately the square of the loss rate of one discrete component.
Thus, one problem that can be solved by some embodiments of the present invention is to make available a stack arrangement for a memory module that meets the requirements of small dimensions and low electrical parasitism, approximately identical to that of discrete components, makes it possible to achieve especially low signal transit times, reduces the loss rate of the assembled arrangements, and can be integrated into the existing manufacturing and testing technology.