The present invention relates generally to electronic packaging. More particularly, the present invention relates to a marked structure such as a wafer or an array of packages.
As is well known to those of skill in the art, integrated circuits, i.e., electronic components, are fabricated in an array on a wafer. The wafer is then cut, sometimes called diced, to singulate the integrated circuits from one another.
FIG. 1 is a cross-sectional view of a section of a wafer 10 being cut from a front-side surface 10F of wafer 10 in accordance with the prior art. Formed in wafer 10 were integrated circuits 12. Integrated circuits 12 were delineated by scribe lines 14, which included a first scribe line 14A and a second scribe line 14B, on front side surface 10F of wafer 10. For example, scribe lines 14 were formed by selective etching of a silicon oxide layer 18 on front-side surface 10F.
To illustrate, first scribe line 14A delineated a first integrated circuit 12A from a second integrated circuit 12B. Each scribe line 14 had a width WF.
A back-side surface 10B of wafer 10 was attached to a tape 20. Wafer 10 was then sawed with a saw blade 22. Saw blade 22 was aligned with scribe lines 14 using an optical alignment system in a well-known manner. Saw blade 22 cut through wafer 10 along scribe lines 14. In this manner, integrated circuits 12 were singulated. Tape 20 supported wafer 10 during sawing and supported the singulated integrated circuits 12 after sawing was complete.
Generally, width WF of scribe lines 14 was sufficient to accommodate the width of the saw cut plus tolerance in the positioning of saw blade 22. Stated another way, width WF of scribe lines 14 was sufficiently large such that the saw cut made by saw blade 22 was always within a scribe line 14. For example, saw blade 22 is within scribe line 14B in FIG. 1.
Since the optical alignment system used scribe lines 14 directly to align saw blade 22, saw blade 22 was aligned to scribe lines 14 to within tight tolerance. Accordingly, scribe lines 14 were relatively narrow and, more particularly, were only slightly wider than saw blade 22. To illustrate, width WF was within the range of 0.002 inches (0.051 mm) to 0.008 inches (0.203 mm).
In certain instances, it was important to protect the front-side surface of the wafer during sawing, e.g., from shards and particulates generated during sawing. To protect the front-side surface, the wafer was sawed from the back-side surface of the wafer as discussed below in reference to FIG. 2.
FIG. 2 is a cross-sectional view of a section of a wafer 30 being cut from a back-side surface 30B of wafer 30 in accordance with the prior art. To protect a front-side surface 30F of wafer 30, front-side surface 30F was attached to a tape 32. Tape 32 supported wafer 30 during sawing.
Saw blade 22 was aligned with scribe lines 14-1 on front-side surface 30F of wafer 30 using a two-step process. First, tape 32 was aligned with scribe lines 14-1. Front-side surface 30F was attached to tape 32. Tape 32 had area greater than the area of front-side surface 30F such that tape 32 had an exposed region, which extended beyond wafer 30. Tape 32 had alignment marks in the exposed region of tape 32. As an example, see alignment holes 30a and 30b of Roberts, Jr. et al., U.S. Pat. No. 5,362,681, which is herein incorporated by reference in its entirety. In the above manner, scribe lines 14-1 were aligned with the alignment marks of tape 32.
Second, saw blade 22 was aligned with the alignment marks of tape 32. Wafer 30 was then sawed with saw blade 22 from back-side surface 30B. However, since saw blade 22 was aligned indirectly to scribe lines 14-1 using alignment marks of tape 32, a large tolerance was associated with the alignment of saw blade 22 to scribe lines 14-1.
To accommodate this large tolerance, each of scribe lines 14-1 had a relatively large width WB. More particularly, referring now to FIGS. 1 and 2 together, width WB of scribe lines 14-1 of wafer 30, which was designed to be cut from back-side surface 30B, was significantly larger than width WF of scribe lines 14 of wafer 10, which was designed to be cut from front-side surface 10F. To illustrate, width WB was approximately 0.012 inches (0.305 mm) or more.
Disadvantageously, forming scribe lines 14-1 with a relatively large width WB resulted in less integrated circuits 12 for any given size wafer 30 than the corresponding number of integrated circuits 12 formed in the same size wafer 10, i.e., there was a loss of yield of integrated circuits 12 from wafer 30. As a result, the cost of each integrated circuit 12 from wafer 30 was greater than the cost of each integrated circuit 12 from wafer 10. However, it is desirable to minimize the cost of each integrated circuit 12.
In accordance with the present invention, a method includes identifying and determining a position of a scribe grid on a front-side surface of a wafer with a camera. Based on this information, a computer aims a laser at a first location on a back-side surface of the wafer. The laser is fired to form a first alignment mark on the back-side surface of the wafer. Advantageously, the alignment mark is positioned with respect to the scribe grid to within tight tolerance, e.g., to within 0.001 inches (0.025 millimeters) or less.
The front-side surface of the wafer is attached to a tape to protect the front-side surface of the wafer during sawing. A saw blade is aligned with a scribe line of the scribe grid using the alignment mark on the backside surface of the wafer. The wafer is cut from the back-side surface along the scribe line with the saw blade.
Advantageously, the wafer is cut from the back-side surface thus protecting the front-side surface of the wafer and, more particularly, the integrated circuits. Of further importance, the saw blade is precisely aligned to the scribe line using the alignment mark such that the scribe line is not fabricated with the extra large width of scribe lines of conventional wafers designed to be cut from the back-side surface.
Recall that in the prior art, in certain instances, it was important to cut the wafer from the back-side surface. However, to accommodate the large tolerance associated with back-side wafer cutting, the wafer designed to be cut from the back-side surface was formed with relatively wide scribe lines. Disadvantageously, forming the scribe lines with a relatively large width resulted in less integrated circuits for any given size wafer, i.e., a loss of yield. This resulted in a substantial increase in the cost of the integrated circuits.
In stark contrast, the wafer is cut from the back-side surface in accordance with the present invention without the associated loss of yield of the prior art. As a result, the integrated circuits of the wafer are protected during singulation yet are fabricated without the associated substantial increase in cost of the prior art.
In accordance with another embodiment of the present invention, an array of packages is marked. In accordance with this embodiment, a back-side surface of the array is scanned by a camera to identify and determine the position of fiducials on the back-side surface. Based on this information, a computer aims a laser at a first location on a front-side surface of the array. The laser is fired to form an alignment mark on the front-side surface of the array. Advantageously, the alignment mark is positioned with respect to the fiducials to within tight tolerance, e.g., to within 0.001 inches (0.025 millimeters) or less.
The back-side surface of the array is attached to a tape. A saw blade is aligned with the array using the alignment mark as a reference. The array is cut with the saw blade thus singulating the packages.
A pick and place machine removes the packages from the tape. Advantageously, the packages are directly removed from the tape by a standard and relatively simple pick and place machine. Accordingly, removal of the packages from the tape is relatively simple and thus low cost. As a result, the packages are fabricated at a low cost.
In the prior art, an array of packages was singulated from the back-side surface. More particularly, the array was placed upside down on the tape such that a layer of encapsulant of the array was adhered to the tape and the fiducials extended upwards and were exposed. The array was singulated by cutting from the back-side surface using the fiducials as a reference.
However, after singulation, the singulated packages had to be removed from the tape and inverted, e.g., using a pick and place machine with flip capability. The singulated packages had to be removed from the tape and inverted so that the singulated packages could be loaded into the grid carrier with the contacts (or other interconnection structure) facing downwards into the grid carrier. Back-end processing, e.g., automated attachment to the printed circuit mother board or automated testing, required that the singulated packages be loaded into the grid carrier in this manner. Disadvantageously, removing the singulated packages from the tape and inverting the packages required complex machinery, was labor intensive and, accordingly, increased the cost of the packages. In contrast, removal of the packages from the tape in accordance with the present invention is relatively simple and thus low cost.
In accordance with one particular embodiment, a structure includes a substrate, e.g., a wafer, having a first surface and a second surface. The structure further includes a reference feature, e.g., a scribe grid, on the first surface and at least one alignment mark on the second surface. The alignment mark has a positional relationship to the reference feature.
In accordance with another embodiment of the present invention, an array of packages includes a substrate having a first section, an electronic component such as an integrated circuit attached to the first section, metallizations on a first surface of the first section, and contacts on the metallizations. Bond pads of the integrated circuit are electrically connected to the contacts by bond wires. A layer of encapsulant covers the integrated circuit, the bond pads, the bond wires, the contacts, and the metallizations. A fiducial is on a first surface of the array and an alignment mark is on a second surface of the array. More particularly, the alignment mark is in the layer of encapsulant.
In one embodiment, a method includes identifying a reference feature on a first surface of a substrate such as a wafer or an array of packages. The method further includes marking a first location on a second surface of the substrate with a first alignment mark. The first alignment mark is used to determine a position of the reference feature.
These and other features and advantages of the present invention will be more readily apparent from the detailed description set forth below taken in conjunction with the accompanying drawings.