1. Field of the Invention
This invention generally relates to an apparatus for recording digital information on a recording medium such as a magnetic disk or tape and reproducing the recorded information and more particularly to a code-error correcting device for correcting code-errors in digital signals used in the apparatus for recording digital information on the recording medium and reproducing the recorded information.
2. Description of the Related Art
Referring first to FIG. 8, there is shown the structure of a code of digital signals used in a typical apparatus for recording audio signals on a magnetic tape by means of a rotary head and reproducing the recorded information (that is, what is called an R-DAT (Digital Audio Tape recorder)) therefrom. As shown in this figure, the code includes data (DATA) composed of 28.times.26 symbols, a transverse or horizontal parity code (C.sub.2 PARITY) composed of 28.times.6 symbols and a longitudinal or vertical parity code (C.sub.1 PARITY) composed of 4.times.32 symbols. In the case of Reed Solomon Code (R.S.C), sets of data concerning the parity codes C.sub.1 and C.sub.2 are (32, 28, 5) and (32, 26, 7), respectively. In each of the parentheses, a first, second and third numeral indicates values of the total length of a code, the length of data and a minimum distance between code words, respectively.
Further, referring now to FIG. 9, there is shown the format of signals employed when recording the signals having such structure of codes. In this figure, reference characters SYNC indicates a synchronizing signal; ID an identification signal; ADR an address signal; P a block parity signal; DATA data of 28 symbols; and C.sub.1 a C.sub.1 parity code of 4 symbols. That is, signals SYNC, ID, ADR and P are added to data signals. Incidentally, in this case, the block parity signal is given by EQU P=ID.sym.ADR.
Namely, the signals, of which the format is as shown in FIG. 9, are recorded on the magnetic tape and reproduced therefrom.
The above described conventional apparatus can detect address errors to some extent by transmitting the block parity signal indicating ID.sym.ADR together with the signal indicating data DATA. However, the conventional apparatus has a drawback that the capability of detecting the address errors is not sufficient to precisely detect the address error and as a consequence the address errors increase. In this case, data are stored in an erroneous area within a memory in accordance with the erroneous address information because the address information generally determines an area in the memory in which data are to be stored. Conventionally, even when the error cannot be detected by using the longitudinal parity code (C.sub.1), the error can still be corrected if the error is present within the range which can be corrected by using the transverse parity code (C.sub.2). Further, if the error exceeds the capability of detecting the error by using the transverse parity code (C.sub.2), it is necessary to locate the error on the basis of the error information which is generated after the check by using the parity codes C.sub.1 and C.sub.2.
In such case, if only the area in the memory is erroneous and the parity code C.sub.1 is correct, there is the inconvenience that in spite of the fact that a sequence of data is erroneous, the error cannot be detected. Thus, to eliminate such inconvenience, it has been proposed that when the parity code C.sub.1 is generated, the address is included as a generating element for the parity code C.sub.1. Such approach has a defect that the capability of correcting error is degraded because the code is not a product code.
Therefore, it is an object of the present invention to provide a code correcting device of which the capability of correcting error is significantly improved, thereby decreasing the possibility of passing over the error.