1. Field of the Invention
This invention relates to methods and apparatus for systems for manufacture of semiconductor devices and more particularly to yield loss analysis in yield management systems.
2. Description of Related Art
U.S. Pat. No. 5,598,341 of Ling et al. for "Real-Time In-Line Defect Disposition and Yield Forecasting System" shows a real time defect disposition and yield forecasting system which uses KLA and INSPEC inspection tools. A particle in contact with two conductor lines is described as a "killer defect." It is stated that the particle "may kill or prevent the normal operation of the semiconductor device which utilizes conductors . . . " Ling describes a real time, in-line system. An inspection method/tool provide for inspection of at least two layers of a semiconductor wafer, producing "first information" on particle size, particle location, and the number of particles. A design review station inspects those at least two layers and produces "second information" including the layouts of each of those at least two layers. A yield management station is operatively connected to the in-line fabrication inspection tool and to the design review station. The yield management station determines at least one of a number of killer defects for the devices in each of the at least two layers or a defect sensitive area index for each of the at least two layers responsive to layers using the first and second information. Determination of a priority is made for analyzing each of the at least two layers responsive to at least one of the number of killer defects and the defect sensitive area index for each of the at least two layers. See col. 5, line 55 to col. 7, line 8. Ling does not appear to disclose the 6th order polynomial curve fit to identify the killer stage, but Ling does describe a general analysis method/tool/program, Col. 6, line 55 to Col. 7, line 8 .
U.S. Pat. No. 5,475,695 of Caywood et al. for "Automatic Failure System" teaches an automatic failure analysis system which discloses automatic fault extraction (AFE) and a specific analysis technique called inductive fault analysis (IFA).
U.S. Pat. No. 4,801,869 of Sprogis for "Semiconductor Defect Monitor for Diagnosing Processing-Induced Defects" shows a design for a defect monitor pattern/wafer.
U.S. Pat. No. 5,544,256 of Brecher for "Automated Defect Classification System" shows an automated defect classification system for analyzing digital images of defects.
KLA In-line defect inspection tools and the Yield Management System (YMS) are popular tools for studying the visual defect in process but heretofore, there has been no systematic method for determining the correlation between yield loss and visual defects. In the more complicated manufacturing processes, the state of the art methods of yield loss analysis have made it difficult to correlate the major killing stages to the resulting losses in yield. Thus it has been difficult to be efficient in selecting which action to take to improve the yield.