The present invention pertains to a configurable system memory map. More particularly, the present invention pertains to the modification of a memory map so as to improve performance in a computer system or the like.
In a computer system or the like, a memory map may be created which reflects the addressability of devices coupled together in a system including a processor. For example, a computer system or the like may include a processor that accesses a variety of addressable components such as the following: a buffer memory, an internal and/or external Read-Only-Memory (ROM), one or more peripherals, internal or external static random access memory (SRAM), etc. In some cases both memory devices and input/output devices are accessed from the same memory map. In other words each address identifies either a location in an internal or external device, or identifies a different type of device such as a peripheral device (or a storage area in the peripheral device).
The memory map is especially important during reset and interrupt processing. As is known in the art, when a processor is reset, the processor will look for instructional code to execute at a certain memory location. For example, with a 32-bit address space, the processor may first access address 00000000 (hex) for the first instruction code to be executed so as to set up the processor to execute additional code (one skilled in the art may refer to this initial code as a xe2x80x9cboot-upxe2x80x9d or initialization sequence of code). Because a reset condition typically occurs after a power-down/power-up sequence, it is necessary that the first address accessed after reset be in non-volatile memory.
Many processors also receive interrupt inputs which will cause the processor to stop execution of the code sequence currently being executed and to jump to another, preset address. In many processors, the preset address is a relatively low address like the reset address (e.g., the example above, 00000000(hex)). For example, an interrupt address could be 00000100 (hex). Then, the processor can execute code at this address. The processor may continue to execute instruction codes at sequential address locations, or the instruction code stored at the interrupt address may cause the processor to jump to another address for instruction codes to be executed to handle the interrupt. When execution of the code to handle the interrupt is completed, the processor returns to the execution of code that was previously interrupted.
As stated above, the reset address and the interrupt addresses (sometimes individually referred to as vectors) are typically located relatively close together at the lower or upper part of the address space. Since the reset vector must point to valid instruction code, it usually points to a non-volatile memory device. It is expected, then, that the interrupt vectors will also point to the same non-volatile memory device. Furthermore, the non-volatile memory may be an external device because on-chip, rewritable non-volatile memory may not be available in the IC technology used and the code may not be available at the time of fabrication of the chip to use internal ROM. A problem that is seen with this kind of configuration is that code execution on interrupts may occur with external, non-volatile memory that provides a slower access time when compared to other types of memory such as an internal SRAM device. In applications where interrupts must be handled at high speed, or must be dynamically changed during normal system operation, continuous access to the non-volatile memory space (e.g., an external ROM) during interrupt processing may not be acceptable. Though the first instruction(s) from the ROM may cause a jump to a different memory address (e.g., a memory address that points to a faster memory device), these initial accesses can waste processing time and negatively impact performance.
In view of the above, there is a need for an improved method and apparatus for a computer system using a memory map.
According to an embodiment of the present invention, a configurable memory map is provided. During a first condition, such as during a reset, the memory map is in a first configuration so that access to a first portion of the memory space (e.g., for a reset vector) results in an access to a first memory device. During a second condition (e.g., during normal processing), the memory map is in a second configuration (e.g., through the operation of a bus controller) so that accesses to the same portion of the memory space result in accesses to a second memory device (e.g., during interrupt processing). Using such a configurable memory map can result in improved performance for the computer system. For example, accesses by a processor during a reset operation will result in accesses to non-volatile memory (e.g., a ROM) while accesses by the processor during interrupt processing will result in accesses to faster memory devices (e.g., an internal SRAM) even though the reset and interrupt vectors are in the same portion of the memory space. In addition, access to the first memory device and access to the second memory device are available in other fixed portion of the memory devices to facilitate initialization of the volatile memory device (e.g., internal SRAM) after reset.