1. Field of the Invention
The present invention relates to a liquid crystal display device and, more particularly, to a structure of a liquid crystal display device and its fabrication method.
2. Background of the Related Art
Generally, a liquid crystal display device includes a lower substrate on which thin film transistor and pixel electrode are arranged, an upper substrate on which a color filter for displaying colors and a common electrode are formed. A liquid crystal is filled between those two substrates, and a polarizing substrate is installed on both sides of those two glass substrates and for pre-polarizing the visible ray (natural ray).
FIG. 1 is a circuit diagram of the thus-structured liquid crystal display (LCD) device. The device includes a thin film transistor (TFT), namely, a switching circuit, a liquid crystal capacitor and a storage capacitor formed by the liquid crystal between the upper/lower substrate electrodes, a gate signal line and a data signal line.
If a voltage signal is applied to the gate line, the TFT turns on while the data voltage signal containing the picture image data is applied to the data signal line. The data voltage of the data signal line passes through the TFT and charges up the storage capacitor and the liquid crystal capacitor, thereby operating the LCD device.
FIG. 2 is a plan view of the lower substrate of the related art LCD device. FIGS. 3A to 3H are sectional views illustrating the fabrication steps of the LCD device taken along lines I--I of FIG. 2.
As illustrated in FIG. 3A, a polycrystalline silicon is deposited on a transparent substrate 1 such as glass or quartz substrate, and patterned to form a semiconductor layer 2 on a predetermined portion of the substrate 1. The semiconductor layer 2 is used for an active area of TFT and an electrode of the storage capacitor.
As illustrated in FIG. 3B, a photoresist layer 3 is coated on the overall surface of the substrate and patterned to expose the semiconductor layer 2, which will be used as the lower electrode of the storage capacitor. Impurity ions, P or B, are implanted into the semiconductor layer 2 using the photoresist layer 3 as a mask.
As illustrated in FIG. 3C, the photoresist layer 3 is eliminated and a gate insulating layer 4 is formed on the overall surface of the substrate 1, including the semiconductor layer 2. A layer made of a material such as B or P doped polycrystalline silicon or silicide is deposited on the overall surface of the substrate 1, including the gate insulating layer 4, and patterned to form a gate line 5a and a common electrode line 5b. The common electrode line 5b serves as the upper electrode of the storage capacitor.
As illustrated in FIG. 3D, impurity ions, P or B, are implanted into the semiconductor layer 2 by using the gate line 5a as a mask, and the semiconductor layer 2 is heat-treated to activate the implanted ions and to form source and drain regions.
As illustrated in FIG. 3E, the first interlayer insulating layer 6, such as silicon oxide, is deposited on the overall surface of the substrate 1. The gate insulating layer 4 and the first interlayer insulating layer 6 are selectively removed to open a source region in the semiconductor layer 2, thereby forming a first contact hole 7.
As illustrated in FIG. 3F, a metallic layer is deposited on the overall surface of the substrate 1 including a first interlayer insulating layer 6. The metallic layer is patterned to form a data line 8 and is connected to the source region of the semiconductor layer 2 through the first contact hole 7.
As illustrated in FIG. 3G, a second interlayer insulating layer 9 is deposited on the overall surface of the substrate 1 including the data line 8. The gate insulating layer 4 and the first and second interlayer insulating layers 6 and 9 are selectively eliminated to expose a drain of the semiconductor layer 2, thereby forming a second contact hole 10.
As illustrated in FIG. 3H, the transparent conductive layer made of a material such as indium tin oxide (ITO) is deposited on the second interlayer insulating layer 9, and patterned to form the pixel electrode 11 which is connected to the drain region of the semiconductor layer 2. A passivation layer 12 is formed on the overall surface of the substrate 1 including the pixel electrode 11 to complete the formation of the lower substrate of the LCD device.
The related art device and its fabrication method have various disadvantages. For example, the sequential deposition of the semiconductor layer, the gate insulating layer and the common electrode line to form the storage capacitor decreases the aperture ratio of the LCD device. The common electrode line is too opaque and the aperture ratio is decreased by the size of the storage capacitor, namely, by 20-30% of the pixel area.
Further, since the gate line is formed by using a polycrystalline silicon including impurity ions, its resistance is too large for application to a LCD device of high image quality. Moreover, the hydrogen ions cannot enter into a channel area through the gate electrode during a hydrogenation process in which hydrogen radicals are fed into the semiconductor layer to enhance the performance of the device by the polycrystalline silicon TFT. Instead, the hydrogen radicals are laterally diffused through the gate insulating layer when the gate line is formed of a silicide material, such as WSix or MoSix. Such a process is time consuming to perform the hydrogen process the performance of the device.
The above references and/or description are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.