In the design, processing and implementation of embedded capacitors for power decoupling in electronic appliances and systems, different techniques have been proposed for the implementation of the embedded capacitors. In the implementation of embedded capacitors, limitations may arise in relation to the integration of the embedded capacitors with power distribution networks in terms of performance and space utilization. For example, blind/buried vias are typically required in existing techniques, resulting in process limitations and increased manufacturing complexity. Furthermore, in existing techniques, vias for high current and high-frequency decoupling, respectively, must typically be provided, resulting in increased number of interconnection and solder joints.
Often, the different existing techniques for the implementation of embedded capacitors are designed and limited to a specific process technology during manufacturing, which can impose further limitations of existing techniques due to lack of adaptability for different manufacturing process technology.