This application claims the benefit of priority under 35 U.S.C. xc2xa7119 to Japanese Patent Application No. 2001-74236 filed on Mar. 15, 2001, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to a semiconductor memory device which dynamically stores data with using a channel body of a transistor as a storage node.
2. Related Background Art
In a related DRAM, a memory cell is composed of an MOS transistor and a capacitor. The scale-down of the DRAM has been remarkably advanced by the adoption of a trench capacitor structure and a stacked capacitor structure. At present, the cell size of a unit memory cell is scaled down to an area of 2Fxc3x974F=8F2, where F is a minimum feature size. Namely, the minimum feature size F decreases with the advance of generation, and when the cell size is generally taken to be xcex1F2, xcex1 coefficient a also decreases with the advance of generation. Thus, at the present of F=0.18 xcexcm, xcex1=8 is realized.
In order to hereafter secure the trend of cell size or chip size which is the same as before, it is demanded to satisfy xcex1 less than 8 in F less than 0.18 xcexcm and further satisfy xcex1 less than 6 in F less than 0.13 xcexcm, and together with microfabrication, the formation of cell size of the possible small area becomes a large problem. Accordingly, various proposals for decreasing the size of the one memory cell with the one transistor and one capacitor to 6F2 or 4F2 are made. However, practical use is not easy since there are a technical difficulty that the transistor has to be a vertical type, a problem that electric interference between adjacent memory cells increases, and in addition difficulties in terms of manufacturing technology including fabrication, film formation, and the like.
It is therefore an object of the present invention to provide a semiconductor memory device which includes memory cells with simple transistor structure and which can store data dynamically.
According to one aspect of the present invention, a semiconductor memory device including MIS transistors to constitute memory cells, each of the MIS transistors comprising:
a semiconductor layer;
a source region formed in the semiconductor layer;
a drain region formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state;
a first gate which forms a channel in the channel body;
a second gate formed so as to control a potential of the channel body by a capacitive coupling; and
a high concentration region formed in the channel body on the second gate side, impurity concentration of the high concentration region being higher than that of the channel body,
wherein the MIS transistor has a first data state in which the channel body has a first potential and a second data state in which the channel body has a second potential.
According to another aspect of the present invention, a semiconductor memory device including MIS transistors to constitute memory cells, each of the MIS transistors comprising:
a semiconductor layer;
a source region formed in the semiconductor layer;
a drain region formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state; and
a first gate which forms a channel in the channel body,
wherein characteristics of the MIS transistor in the case where a channel current flows from the source region to the drain region is different from characteristics of the MIS transistor in the case where a channel current flows from the drain region to the source region, even when the same potential is applied to the first gate, and
wherein the MIS transistor has a first data state in which the channel body has a first potential and a second data state in which the channel body has a second potential, the first data state being set by the impact ionization generated near a drain junction or by a drain leakage current caused by the first gate, the second data state being set by sending a forward bias current between the drain region and the channel body.
According to a further aspect of the present invention, a semiconductor memory device including MIS transistors to constitute memory cells, each of the MIS transistors comprising:
a semiconductor layer;
a source region formed in the semiconductor layer;
a drain region formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state; and
a gate which forms a channel in the channel body,
wherein the MIS transistor has a first data state in which the channel body has a first potential and a second data state in which the channel body has a second potential, the first data state being set by a drain leakage current caused by the gate to which a negative potential is applied, the second data state being set by sending a forward bias current between the drain region and the channel body.