1. Field of the Invention
This invention relates to computer memory systems and, more particularly, to techniques for avoiding data corruption during sparing of memory chips.
2. Description of the Related Art
Evolving standards of reliability, availability, and serviceability for computer memory systems have led to systems that include one or more redundant memory chips. In such systems, when failures from a particular memory chip exceed a threshold, a spare chip may be employed to take the place of the failed chip. This strategy, referred to as chip sparing, allows a multi-chip system to tolerate more than one failed memory chip by sparing out one known bad chip with a high number of failures and using error-correcting code (ECC) checking and correction to carry on without interruption when failures occur on other chips.
A sparing operation typically includes sequentially reading the contents of a failed chip, applying error correction, and writing the corrected values to the spare chip. A simple approach to preventing data corruption is to stop other memory transactions during a sparing operation. However, stopping other memory transactions during a sparing operation may adversely affect system performance since chip sparing may take a significant amount of time to write-back the corrected contents of an entire chip. For example, to spare a DDR-533 512 Mb DRAM may take approximately 4 seconds. On the other hand, allowing a mixture of chip sparing transactions and other memory transactions could lead to data corruption. For example, when a non-sparing memory write to a given location occurs in between a read and a write of a chip sparing read/write pair to the same location (i.e. after the read but before the write), the data in the given location may be corrupted because the chip sparing write operation may overwrite the data written by the non-sparing write operation. Also, when a non-sparing memory write is issued to a given location that has been spared, data may be written to both the given location and to a corresponding spared location. In addition, a non-sparing memory read operation that takes place during a chip sparing operation to the same location may return different data depending on whether the read takes place before or after the chip sparing write-back. Accordingly, a system and method are needed that avoid data corruption during chip sparing operations while maintaining adequate system performance.