When developing new chip designs, it is common for chip designers to combine pre-designed components to form the new chip. This modular chip fabrication process is beneficial as it takes advantage of preexisting proven technology. For example, a chip designer might combine components from several different previously developed chips.
The computer chip industry is constantly developing and employing process technologies to produce chips having smaller feature sizes. For example, the achievable feature size of about three micrometers (μm) (or 3,000 nanometers (nm)) in 1976 was reduced to about 90 nm in 2003. Smaller feature sizes allow for a greater number of functionalities to be associated with a given chip, and thus generations of chip scaling have followed scaling laws first set forth by R. Dennard et al., “Design of ion-implanted MOSFETs with very small physical dimensions,” IEEE Journal of Solid State Circuits, vol. SC-9, no. 5, pp. 256-268 (October 1974). Further, chips with smaller feature sizes require less power to operate. With an estimated $2.7 billion spent in 2005 to run servers and other associated computer equipment in the United States alone, power consumption is a growing concern.
These rapid advances in chip scale technology, however, can have notable drawbacks with regard to modular chip fabrication. Namely, as chip technology changes, incompatibilities can often arise between the ‘old’ and the ‘new’ technologies. By way of example only, a change in chip feature size typically coincides with a change in power requirements. Different power requirements can render one component incompatible with another component. Thus, the versatility of current chip design technology can be limited unless all of the components are redesigned into the latest node for a new chip and fabricated using the scaled down features associated with the latest node of semiconductor wafers.
Therefore, modular chip fabrication techniques which improve the compatibility of different chip technologies would be desirable.