1. Field of the Invention
The present invention relates to a non-volatile memory device and, more particularly, to methods of erasing a non-volatile memory device having discrete charge trap sites.
2. Description of the Related Art
A non-volatile memory device is configured to retain data previously stored in its memory cells, even when the power supply is turned off, unlike a volatile memory device which loses stored data when power is removed. The non-volatile memory device includes a charge storage layer, which is interposed between a semiconductor substrate and a gate. Non-volatile memory devices may be classified as a floating gate type memory device and an MNOS type memory device, depending on the structure of the charge storage layer.
The floating gate type non-volatile memory device structure includes a tunnel dielectric layer, a floating gate, an inter-gate insulating layer, and a control gate, which are sequentially stacked on a semiconductor substrate. The floating gate, in which the charge is stored, is formed of a conductive layer.
The MNOS type non-volatile memory device structure includes a stacked metal/nitride/oxide/semiconductor (MNOS) or metal/oxide/nitride/oxide/semiconductor (MONOS). In this configuration, a dielectric layer such as nitride, is interposed between a semiconductor substrate and a gate, to serve as a charge storage layer. The MNOS type non-volatile memory device stores data by using trap sites within the dielectric layer, and trap sites in an interface of the dielectric layer, for example, the interface between adjacent dielectric layers, and trap sites in an interface between the dielectric layer and the semiconductor substrate.
Chan, et. al. introduced SONOS (silicon oxide nitride oxide silicon)-type memory devices in “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device, IEEE Electron Device Letters, Vol. 8, No. 3, pp. 93–95, 1987). The conventional SONOS type non-volatile memory device includes a dielectric layer and a gate, which are formed on a silicon substrate, and source/drain formed in the semiconductor substrate adjacent to both sidewalls of the gate. The dielectric layer includes a tunnel dielectric layer, a charge storage dielectric layer, and a blocking dielectric layer. The tunnel dielectric layer, the charge storage dielectric layer and the blocking dielectric layer may be formed of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer respectively. The gate may be formed of a silicon layer. That is, the SONOS structure is formed of the silicon oxide layer, the silicon nitride layer, the silicon oxide layer and silicon layer, which are sequentially stacked on the silicon substrate.
When the SONOS type non-volatile memory device becomes programmed, and electrons are injected into the charge storage dielectric layer, the device threshold voltage is increased. Thus, when a voltage, being lower than the increased threshold voltage, is applied on the gate, electric current does not flow through the channel. When a voltage higher than the threshold voltage is applied, current flows through the channel. Using this property, stored data can be read.
Furthermore, the erase operation of the SONOS type non-volatile memory device is performed by applying a negative voltage to the gate and by applying a positive voltage to the source, while floating the drain and the semiconductor substrate. As such, the electrons stored within the charge storage dielectric layer are removed. In the case where the charge storage layer is a floating gate comprising a conductive layer, the electrons stored within the charge storage layer can be freely moved. On the contrary, in the case where the charge storage layer is formed of a dielectric layer, such as in the case of the SONOS type non-volatile memory device, the electrons stored inside the trap sites cannot be freely moved. Thus, the conventional erasing method described above fails to provide a complete erasure in such a SONOS type non-volatile memory device.
FIG. 1 is a graph showing the change of threshold voltage as a function of the number of program(P)/erase(E) cycles in the typical SONOS type non-volatile memory device. As shown in FIG. 1, while program threshold voltages remain somewhat constant as a function of the number of program/erase operations, the erase threshold voltages are gradually increased. Such an increase of the erase threshold voltages results from the fact that the electrons trapped within the charge storage layer are not completely removed as a result of the erase operation, as described above. If the increase in erase threshold voltage cannot be suppressed, after approximately 100,000 P/E cycles, a threshold voltage window between a programmed non-volatile memory device and a non-programmed non-volatile memory device is not obtained, thereby resulting in deterioration of device reliability.