The unbroken popularity of the World Wide Web and its annual increase in size requires increasingly larger switching fabrics. To meet today's switching requirement of 1 Tb/s throughput and above, switches are growing not only in terms of port speed, but also in number of ports. With 5 Gb/s links, port sizes of 64, and today's link and fabrication technologies, multichip and even multishelf solutions are necessary. As a consequence, the input adapters with virtual output queuing (VOQ) are at a distance from the switching device such that the roundtrip time (RTT) bandwidth product is significantly greater than 1. On the other hand switch packet sizes in terms of bytes remain constant. This means that there are more packets on the link, which requires larger memories in the switch, for it to be able to accept all packets in transit. This is a necessity in order that the switch be work-conserving or loss-less, depending on the link-level flow-control scheme used.
A large amount of the expenses invested in switch design goes into link technology, i.e. links, cables, and connectors. Therefore bandwidth is expensive, but however the bandwidth is not used efficiently at present.
IBM's PRIZMA switch-chip family uses a grant flow-control scheme that returns to each input adapter a vector of stop and go signals per output. This scheme is described in the publication “A Combined Input- and Output-Queued Packet-Switch System Based on PRIZMA Switch-on-a-Chip Technology” by C. Minkenberg and T. Engbersen in IEEE Commun. Mag., vol. 38, no. 12, December 2000, pp. 70-77. For fabric sizes of N=64 for instance, with N the number of switch ports, a vector length and hence a flow control bandwidth of 8 bytes per packet cycle would be required. If there are not potentially complex optimization schemes applied, the grant flow-control scheme will prevent switches to grow to larger sizes.
The Atlas switch as described by G. Kornaros et al. in the publication “Implementation of ATLAS I: a Single-Chip ATM Switch with Backpressure” in Proc. IEEE Hot Interconnects VI Symposium, Stanford, Calif., USA, 13-15, Aug. 1998, pp. 85-96 represents the category of switches that use a flow-control scheme based on credits. The flow-control bandwidth is designed to return two credits per packet cycle. The storage, serialization, and return of credits is performed per input using a so-called credit-out FIFO (first-in first-out memory). The FIFO must be large enough to hold all credits that are allowed in the worst case to circulate per adapter/switch input pair. For reasons of correctness the FIFO size scales with the number of ports and the memory size assigned per switch input/output pair. Therefore, the FIFO size roughly scales with O(MN), where M signifies the assigned memory size per memory point, and N the number of switch ports. More importantly, each FIFO must provide N write accesses per packet cycle, because each switch row can have up to N parallel departures. For N≧16 this presents tough hardware design challenges. For ever larger switches it is nearly an impossible task. Therefore the FIFO concept for storage and serialization is not a scalable solution.
Further problems arise from the limited bandwidth of the in-band flow-control channel. An out-of-band flow-control is prohibitively expensive for terabit and betabit solutions. Flow-control bandwidth becomes a real bottleneck if one scales existing switches to ever larger sizes realized as single or multistage fabrics. Furthermore, for scalable multistage fabrics, there are severe restrictions that enforce a number of flow-control events per packet-cycle in the channel.
From the above follows that there is still a need in the art for a new kind of flow-control mechanism which is performant, efficient, robust, scalable, and has the potential to be used in future switching fabrics. The mechanism should be suitable for various switch environments such as communication systems and multiprocessor interconnects. It is therefore an object of the present invention to provide an improved flow-control mechanism for high and efficient packet throughput.