1. Field of the Invention
This invention in general relates to a method for forming semiconductor devices and more particularly, to a method for forming shallow trench isolations (STI) structure on a semiconductor substrate.
2. Description of the Related Art
Isolation structure on a semiconductor substrate is used to prevent carriers from migrating to the adjacent devices. Typically, the isolation structure is formed in a semiconductor substrate with densely packed devices, such as in DRAM or in field effect transistor (FET) devices, for mitigating leakage current induced along the edges of EFT devices.
One method for forming the isolation structure in the semiconductor substrate is local oxidation. However, there are some inherent problems in local oxidation technology, such as the stress of the isolation structure or bird's beak encroachment incurred thereby. Therefore, in high-density semiconductor devices, the use of shallow trench isolation structure is proposed.
The method for forming shallow trench isolation structures in semiconductor substrate comprises the application of anisotropic etching on a semiconductor substrate to form trenches therein and then filling the trenches with dielectric material. Since the field isolation effect provided by the shallow trench isolation structures is scaleable and the Bird's Beak Encroachment in field oxidation is also resolved, the technology of shallow trench isolation structure has become a trend in the technology of semiconductor.
FIGS. 1A to 1B schematically illustrate in cross-sectional representation of the conventional method for forming a shallow trench isolation structure. Referring to FIG. 1A, a pad oxide layer 102 and a silicon nitride layer 104 are provided on a substrate 100. The silicon nitride layer 104 is patterned as a mask to etch a trench 106 in the substrate 100. Then, a liner oxide layer 108 is formed on the surface of substrate exposed in the trench 106 by dry oxidation. Next, a silicon oxide layer 110 is overlaid on the substrate 110 and fills the trench 106 therein. Now referring to FIG. 1B, the oxide layer 110 is removed by chemical mechanical polishing until the silicon nitride layer 104, which is used as a stop layer, is exposed. Next, the silicon nitride layer 104 is removed and then, the pad oxide layer 102 is removed by hydrofluoric acid. A trench isolation structure 112 is formed to completion in the substrate 100.
In the above-described method, the silicon oxide layer 110 covered on the substrate is formed by chemical deposition, while the pad oxide layer is formed by thermal oxidation. The compactness of the former is less than that of the latter. Therefore, while using hydrofluoric acid as an etchant to remove the pad oxide layer 102, the silicon oxide 110 in the trench 106 is etched at a rate higher than that for pad oxide layer 102. As a result, lateral etching occurs on the top surface of trench 106 to form a groove 116, which results in the less-smooth corner profile at the corner 114. Due to the lateral etching, the gate layer subsequently formed on the substrate will be thinner at the corner area 114 than in other places, so the kink effect will occur on the substrate.
Therefore, a need exists to improve the method for forming shallow trench isolations (STI) structure on a semiconductor substrate to eliminate the above mentioned problems.