With the increasing clock speed of integrated circuits (ICs), the relative timing between two or more signals received at the same component is becoming more and more of a design consideration and constraint. Generally, in ICs, there is a typical propagation rate through a given component of an IC. Therefore, the time of propagation of a signal that arrives over a first signal path is synchronized with a computer clock, and a second signal that arrives over a signal path is also synchronized with the computer clock. These signal path propagation times can be calculated and appropriate design choices made. However, if two signals are received at the separate inputs at substantially the same time or relatively close in time to one another, the propagation speed of the resulting signal through that component can be either substantially shorter or substantially longer than the design considerations typically allow for. This can create two potential error conditions in chip design.
The first error condition is generally known as a “late mode” failure, wherein the signal takes longer to propagate, due to simultaneous reception by a component of two incoming signals, than was accounted for in the ideal “non-simultaneous reception” case. The “late mode” case can typically be compensated for slowing the computer clock cycle speed, thereby allowing the signal time to get to the next clock-synchronized component.
The second error condition is an “early mode” failure. In a race condition, due to the substantially simultaneous receipt of two different signals, the resulting signal propagates out of the component faster than anticipated. This is especially irksome, as typically the simultaneous receipt of two independent signals is itself not a function of a received clock cycle, so slowing down the clock cycle typically will not prevent an early condition. Conventional technologies and methods for calculating acceptable design margins to account for both the early and late conditions tend to be either unwieldy, unacceptably inaccurate, or both.
Therefore, there is a need for a method and/or system for estimating design parameters for both early and late race conditions in IC design that addresses at least some of the problems associated with conventional methods and/or systems for estimating design parameters for both late and early race conditions.