A dynamic random access memory (DRAM) cell typically comprises a charge storage capacitor coupled to an access device such as a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). The MOSFET functions to apply or remove charge on the capacitor, thus affecting a logical state defined by the stored charge. The amount of charge stored on the capacitor is determined by the capacitance C=εεo A/d, where ε is the dielectric constant of the capacitor dielectric, εo is the vacuum permittivity, A is the electrode (or storage node) area, and d is the interelectrode spacing. The conditions of DRAM operation, such as operating voltage, leakage rate and refresh rate, will in general mandate that a certain minimum charge be stored by the capacitor.
In the continuing trend to higher memory capacity, the packing density of storage cells must increase, yet each must maintain required capacitance levels. This is a crucial demand of DRAM fabrication technologies if future generations of expanded memory array devices are to be successfully manufactured. Nevertheless, in the trend to higher memory capacity, the packing density of cell capacitors has increased at the expense of available cell area. Yet, design and operational parameters determine the minimum charge required for reliable operation of the memory cell despite decreasing cell area.
Several techniques have been developed to increase the capacitance of the cell capacitor without significantly affecting the cell area. For example, capacitor electrodes having textured surface morphology have been introduced to increase the interfacial area between the dielectric thin film and the adjacent electrode and, therefore, to increase the capacitance. For example, in conventional dual-sided (or double-sided) container capacitors, hemispherical grain polysilicon (HSG) has been introduced as the material of choice for the double-sided electrode because the increased surface area of the HSG electrode and of its respective interfacial area is directly proportional to the cell capacitance. However, current technologies for the formation of a double-sided HSG electrode involve using HSG on the outside of the capacitor plate. Accordingly, when two neighboring dual-sided HSG capacitors are fabricated on a DRAM memory circuit, for example, a short circuit between the two dual-sided HSG capacitors may occur and thus, may negatively affect the characteristics of the device.
Accordingly, as memory cell density continues to increase, there is a need for an improved method for forming a dual-sided HSG container capacitor having increased capacitance per cell and low leakage, as well as a method of forming a capacitor structure that achieves high storage capacitance without increasing the size of the capacitor and without a short circuit between the capacitor structure and an additional adjacent capacitor.