1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and an image processing apparatus having the same.
2. Description of the Related Art
According to a conventional technology for data transmission, a plurality of devices can be connected to a peripheral component interconnect (PCI) bus. One of the devices obtains a right to use the PCI bus, and such a device is determined as a master. The master device can transmit and receive data to and from any of the other devices.
Because the PCI bus employs a parallel transmission system, when the PCI bus receives a large amount of data, it is likely to cause a bottleneck. In order to overcome such a problem of the PCI bus, a technology called PCI Express (PCIe) has been proposed.
The PCIe allows point-to-point links between devices, and employs a serial transmission system.
The PCIe employs a full-duplex system in which transmission and reception of data are performed separately, and thereby the PCIe supports split transaction. Thus, the transmission and the reception of data can be performed at the same time. In the split transaction, a request and a response to the request are separately performed, and therefore a subsequent request can be issued before the response is obtained. In this manner, the transmission and the reception of data can be performed in an effective manner and at a high speed.
In the PCIe, a latency time of a read request to read data from a memory becomes longer. The latency time is a period starting from issuing the read request and ending at receiving the data from the memory. For this reason, a timing of issuing a read request affects the throughput efficiency of a bus in use for split transaction.
FIG. 10 is a schematic diagram for explaining transmission efficiency of a conventional PCIe. When write requests are continuously received from an arbiter in an application specific integrated circuit (ASIC) or the like, the write requests are first issued, and afterwards a read request is issued. Therefore, a reception line is in an idle state during a period T1, during which write requests and data corresponding to the write requests are sent via a transmission line. As a result, the conventional PCIe obtains low transmission efficiency.
FIG. 11 is a schematic diagram for explaining another example of transmission efficiency of a conventional PCIe. If the data transmission rate in an ASIC 5 is lower than the packet transmission speed of a PCIe 6, a request is sent to the PCIe after all of data corresponding to the request is stored in a data buffer that is arranged in a PCIe interface (I/F) circuit. Thus, it is possible to prevent data underflow. However, because a request cannot be sent to the PCIe before all the data is stored in the data buffer, the transmission line is in an idle state during a period T2. Occurrence of the period T2 causes the period T1 in the reception line to increase, and therefore the transmission efficiency becomes much lower.
The use of the PCIe makes it possible to perform the transmission and the reception of data separately and at the same time, nevertheless read data transmission can still be delayed.
A master (bus master device) often executes some operation on data that is read from a memory, and then writes the resultant data in the memory. Therefore, a delay in time for receiving read data from the memory causes a delay in an issue of a write request by the master. As a result, the throughput of the whole system is lowered.
According to a conventional technology disclosed in Japanese Patent Application Laid-Open No. 2006-154910, a memory controller selects a memory access request that allows continuous access to a memory upon sending a write request and a read request, and such continuous access achieves high-speed access to the memory. Furthermore, a plurality of read accesses is collectively processed as continuous read access, and a plurality of write accesses as continuous write access. A read cycle and a write cycle are alternately processed. Thus, it is possible to reduce the number of times of switching between a read access and a write access, and achieve high-speed access to the memory.
However, such a conventional technology has a problem if employed in the PCIe. Specifically, when write requests are collectively issued via a transmission line, a reception line is in an idle state. On the other hand, when read requests are collectively issued, a transmission line is in an idle state. As a result, utilization efficiencies of the transmission line and the reception line are decreased, and the throughput of the whole system is lowered.