The disclosure relates generally to deadlock avoidance in a multi-processor computer system with extended cache line locking.
As contemporary multi-processor computer designs have scaled to larger symmetric multiprocessing (SMP) systems, performance issues around contentious cache lines have become more noticeable to the system. In SMP systems, a traditional deadlock avoidance mechanism based on a length of time that an operation is valid for is implemented to address functional and performance issues. That is, the traditional deadlock avoidance mechanism is initiated to help an operation make forward progress, if that operation is valid for longer than a set time. Additionally, in SMP systems, a next instruction access intent (NIAI) lock instruction can be utilized by a processor core to purposefully hold onto a cache line for an extended period of time to allow the processor core to complete critical sections of code. In this case, while the NIAI lock instruction is purposefully holding the cache line, the traditional deadlock avoidance mechanism (which is based solely on the duration of an operation) can falsely activate and cause instruction sequences waiting on the hold to interfere with other unrelated instruction sequences.