The presently described advancements relate to a multi-core processor interface function and topology, and, more particularly, to a multi-core processor interface leveraging a generated topology for providing decreased energy utilization and increased operational speed, and associated methodology.
The “background” description provided herein is for the purpose of generally presenting the context of the inventive field. Work of the presently named inventors, to the extent described in this section, as well as aspects of the background description which may not otherwise qualify as prior art at the time of filing, are neither expressly or impliedly admitted as prior art, but instead, provided in the spirit of teaching the overall context of the advancements claimed herein.
As software increases in complexity and resource consumption, a corresponding demand on hardware platforms is created. In answering this demand, single-core processors and the performance imperative of Moore's Law, have limited the ability to keep pace by corresponding increases in processing power (i.e., via increasing clock speeds). To overcome this problem, multi-processor architectures have been developed such that two or more processors are utilized on a same board to achieve performance gains. These multi-processor architectures are known as “multi-core”. Multi-core processors increase processing performance while reducing processor footprints and providing better power consumption and thermal characteristics.
Yet, most legacy application software is written for a single processor. Such application software will not automatically run faster on an embedded multi-core computer; in fact it may not run at all. This may be the case even if the software is multi-threaded, as in a single processor the threads will run sequentially whereas in a multi-core computer they may run concurrently, exposing synchronization problems not discovered in the single processor case. Programming multithreaded code often requires complex coordination of threads and can easily introduce bugs that are difficult to find due to the interleaving of processing on data shared between threads. To further complicate matters, the threads are ideally distributed among the multiple cores in a manner that loads the cores equally, to achieve maximum benefit (performance and power consumption).
Given the increasing emphasis on multi-core chip design, the extent to which software can be multithreaded to take advantage of these new chips is likely to be the single greatest constraint on computer performance in the foreseeable future.
Presently, there is a need for a portable API, devoid of the aforementioned deficiencies, providing an optimized communications topology for multi-core processor applications.