As the feature sizes in complementary metal-oxide-semiconductor (CMOS) technology continue to shrink, it becomes increasingly difficult to fabricate the metal interconnects using conventional processing techniques. For example, using a damascene process to fill trenches with copper often results in undesirable effects including poor liner/seed coverage on the trench walls, pinch off at the trench mouth, and reentrant reactive ion etch (RIE) profiles. In addition, the increasing ratio of the liner to copper, copper grain growth, and copper grain scattering phenomena result in increased copper resistivity, which makes the copper less effective as an interconnect material.