1. Field of Invention
This invention relates generally, to a method for forming a doped region in a semiconductor device, and more particularly, to a method for forming a shallow doped junction using ion implantation.
2. Description of the Prior Art
As the demand for high performance semiconductor devices increases, device manufacturers continually redesign semiconductor devices, such as integrated circuits, to have smaller and smaller dimensions. Of the many different device components used in an integrated circuit, the dimension of the gate electrode in a metal-oxide semiconductor (MOS) device is the benchmark dimension by which all other device components are measured. Typically, state of the art MOS devices have gate dimensions in the range of about 0.1 to 0.25 microns.
As gate dimensions are scaled to smaller and smaller values, a concomitant requirement for a reduction in the junction depth of transistor components such as source and drain regions, exists. In addition to requiring a small junction depth, state of the art MOS transistors also require extremely high surface doping concentrations in the source and drain regions. Typically, many doped regions are formed in a semiconductor substrate in the vicinity of the substrate surface. Dopant atoms of either n-type or p-type are typically incorporated into the silicon substrate using both thermal diffusion and ion implantation.
Ion implantation is a physical process in which dopant atoms are ionized, accelerated to a velocity high enough to penetrate the surface of a silicon substrate, focused into a narrow ion beam, and scanned as a beam across the surface of a semiconductor substrate. Dopant ions impacting the surface of the substrate enter the substrate and come to rest below the substrate surface. The depth of penetration into the semiconductor substrate depends upon the particular species and the ion implantation energy. Ion implantation is used in most doping operations in the fabrication of submicron dimension integrated circuit devices. State of the art ion implantation processes can be carried out to form doped regions of precise doping concentration and implantation depth. Doping by means of thermal diffusion is a chemical process typically used to dope thin film layers that do not require the formation of well-defined doped regions.
Typically, source and drain regions in MOS transistors are formed by ion implantation techniques, and in the case of an n-type transistor, dopants such as phosphorus, arsenic, and antimony are commonly used. Modem ion implantation systems analyze an ion beam that has been extracted from an ion source. The extraction efficiency varies depending upon the particular source material and the particular dopant species to be implanted. For common n-type dopants the maximum beam currents are obtained from singly charged individual ions.
To operate an ion implantation system efficiently, and at low cost, a maximum beam current is necessary to maintain a high throughput. Accordingly, the formation of n-type source and drain regions is most commonly carried out using singly-charged, single n-type ions. Since the ion implantation depth, for a given species, varies directly with the ion implantation energy, a very low implantation energy must be used to form a shallow junction in the substrate. The ion implantation system must be operated at very low voltages to obtain the low implantation energy necessary to form a shallow doped region. However, both ion beam extraction efficiency and dose measurement can be adversely affected at low voltage operation. Additionally, at low voltages, beam stability is reduced and spot size control becomes more difficult. Accordingly, a need existed for a method of forming a shallow, highly-doped region in a semiconductor substrate, while maintaining optimal ion implantation operating conditions.