Level shifters, which receive and convert input signal(s) of smaller signal range to output signal(s) of larger signal range, are important blocks of interface circuits. For example, in gate driver chip for driving display panel, internal control signals inside the chip have a signal range of 0 to 3 Volts, but signals outputted to gates of display panel require a signal range of −8 to 3 Volts. For conversion between two different signal ranges, a level shifter is adopted to convert an input signal range of 0 to 3 Volts to an output signal range of −8 to 3 Volts.
Please refer to FIG. 1 illustrating a conventional shifter 10. The conventional level shifter 10 includes a pair of (p-channel MOS, Metal-Oxide-Silicon) transistors TP1, TP2 and a pair of (n-channel MOS) transistors TN1 and TN2. An input signal IN is inverted to another input signal INB by an inverter INV, wherein the input signals IN and INV have a signal range between voltages VPP and VSS. The level shifter 10 operates between voltages VPP and VGL for respectively providing output signals OUT and OUTB at nodes n2 and n1 according to the input signals IN and INB, with a signal range of the output signals OUT/OUTB expanded between voltages VPP and VGL. Gates of the transistors TP1 and TP2 respectively receive the input signals IN and INB, and gates of the transistor TN1 and TN2 are respectively coupled to the nodes n2 and n1.
In the prior art, the operation of level shifter 10 can be described as follows. For example, when the input signal IN transits from the voltage VPP to the voltage VSS, the transistor TP1 starts to turn on, and then pulls the voltage of the node n1 (i.e., the output signal OUTB) up to the voltage VPP. As the voltage of the node n1 raises, the transistor TN2 starts to turn on, and then pulls the voltage of the node n2 (the output signal OUT) down to the voltage VGL.
However, when the input signal is originally maintained at the voltage VPP, the transistor TN1 is turned on. When the input signal IN transits from the voltage VPP to the voltage VSS, the turned-on transistor TP1 has to compete against the turned-on transistor TN1. The turned-on transistor TN1 tends to keep the node n1 to the lower voltage VGL, so the transistor TP1 has to conduct more current than the transistor TN1 with better conduction for pulling the voltage of the node n1 up to the voltage VPP.
Since the transistor TP1 is a p-channel transistor, it suffers from lower current driving ability (e.g., lower carrier mobility). Therefore, a larger aspect ratio (ratio of channel width to length, W/L) is required to drive enough current against the transistor TN1. This requirement leads to a disadvantage that the layout area of the transistors TP1 and TP2, as well as the total layout area of the level shifter 10, can not be reduced.
In addition, when the transistor TP1 competes against the transistor TN1 owing to transition of the input signal IN, the large current conducted by the transistor TP1 causes a larger short current of longer duration which continues to drain power from the voltage VPP during the competition, and increases power consumption of the conventional level shifter 10.
Furthermore, in the prior art, the level shifter 10 is driven by voltage. That is, the transistors TP1 to TP2 and TN1 to TN2 operate respectively according to cross voltages between their gates and sources. Thus, circuit design must be specifically customized according to voltage ranges of the input and output signals. The circuit design has to be tailored for different applications. For example, if an application requires a level shifting from an input signal range of 0 to 3 Volts to an output signal range of −3 to 3 Volts, and another application needs a level shifting from an input signal range of 0 to 3 Volts to an output signal range of −20 to 3 Volts, the level shifter designed for former application can not be adopted for the latter application in the prior. The level shifter has to be re-designed with different parameters (e.g., larger circuit dimensions) to fit the latter application.