1. Field of the Invention
The present invention relates generally to a server and the method for recovery from a failure in one of its links (hereinafter referred to “link recovery”), and in particular, to link recovery in a server equipped with a PCI Express interface.
2. Description of the Related Art
As the computer system processes more data and the processor becomes faster, the interface for interconnecting various components in the computer system is required to transfer larger amounts of data at higher speeds.
For some time now, the Peripheral Component Interconnect (PCI) has been used widely as an interface for interconnecting various components in the computer system. In more recent years, the serial PCI Express has been catching broader market attention because it realizes high-speed, large-capacity data transfer at low implementation costs. It is now expected to be used widely in a variety of computer systems, from personal computers (PCs) and small-scale servers for front-end use to mission critical servers for back-end use.
Mission critical servers are required to have high system availability. It is important to minimize the possibility of a system down as well as the system's down time. One of the known methods of achieving high availability in a system equipped with a PCI Express interface has been the reduced lane mode of operation, whereby, in the event of a failure in one of the links in the system, an alternative link is configured using those lanes constituting the failing link which are usable, so that the system is kept operating with reduced lanes.
In such an arrangement, link recovery calls for the recognition of whether any receiver is present on the PCI Express interface. Without this information, it is impossible to tell whether the link is failing even though a receiver is present on the interface or it is failing because no receiver is present on the interface; as a result, it is impossible to properly process link recovery. In addressing this problem, PCI Express employs a mechanism called receiver detection during the link training sequence, as defined in the PCI Express Specifications (refer to the Web link below), to determine the presence or absence of a receiver.
“PCI Express Base Specification 1.1a,” PCI-SIG <URL: http://www.pcisig.com/specifications/pciexpress/base/>
Receiver detection is a mechanism for detecting the presence or absence of a receiver on a link, whereby, after power-on of the system, the transmitter on the PCI Express interface applies a certain level of voltage to the lanes that make up the link and measures the difference in transition time to determine whether a receiver is present on the link. It takes advantage of the fact that the presence of a receiver pulls down the receiver-side of the AC coupling capacitor inserted between the transmitter and the receiver on the physical signal lines of PCI Express, thereby increasing the load capacitance as seen by the transmitter and lengthening the signal transition by as much time as needed to charge the excess capacitance. This means that the signal transition time is long if a receiver is present on the PCI Express interface, and is short otherwise. This difference is used to determine the presence or absence of a receiver on the interface.
As stated above, the PCI Express interface is also expected to apply to large-scale servers that are used in mission critical systems. With servers of a large form factor such as those, implementing a high-speed interface as fast as, for example, 2.5 GHz results in extended wiring lengths, which makes it difficult to keep the signal quality because of the resulting transmission losses. Therefore it becomes necessary to insert, along the PCI Express interface, a redriver such as an equalizer for compensating transmission losses. The problem, however, is that with the receiver detection mechanism, the insertion of the redriver makes it appear as if there were always a receiver present on the interface, rendering it impossible to determine whether or not an I/O extension adapter is mounted.
As a result, when a link failure occurs on a PCI Express interface in a server, one cannot determine whether one should carry out link recovery, and thus cannot realize high system availability.