The present invention relates to phase-locked loops (PLLs) and, in particular, to an integrated PLL having a resistor-less loop filter.
PLLs are used in integrated circuits, such as application specific integrated circuits (ASICs), for clock synchronization, recovery of serial data streams and frequency synthesis. A typical PLL includes a phase/frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator (VCO) and a frequency divider. The VCO generates a clock signal with a phase and frequency that is a function of the voltage applied to the oscillator. The phase/frequency detector detects a phase and/or frequency difference between the VCO output and the input signal. The phase/frequency detector generates a control signal as a function of the phase difference and applies the control signal to the charge pump which increases or decreases the voltage across the loop filter. This voltage is applied to the VCO for controlling the oscillation frequency and phase of the clock signal.
A typical first-order loop filter includes a resistor and a capacitor which are coupled together in series between two external pins of the integrated circuit. In a PLL which is fabricated on an integrated circuit, an external loop filter is usually used. An external loop filter is prone to noise pick-up and increases system cost. It is therefore desireable to implement the loop filter on the integrated circuit to form a fully integrated PLL. However, good filter resistors are not readily available in standard digital complementary metal-oxide semiconductor (CMOS) processes. As a result, efforts have been made to eliminate or "replace" the filter resistor in on-chip loop filters of fully integrated PLL's. For example, Ilya I. Novof et al. Fully Integrated CMOS Phase-Locked Loop with 15 to 20 MHz Locking Range and +/-50 ps Jitter, IEEE Journal of Solid State Circuits, Vol. 30, No. 11 (November 1995) discloses a phase-locked loop which uses an auxiliary charge pump for replacing the loop filter.