1. Field of the Invention
The present invention relates to nonvolatile memory. More particularly, the present invention relates to methods and apparatus for injecting electrons and holes onto the floating gate of a floating gate MOS transistor nonvolatile memory cell.
2. The Background
Nonvolatile memories employing floating gate technology have found wide use in a variety of applications, and have become an increasingly important type of semiconductor nonvolatile memory. In a floating gate nonvolatile memory, the floating gate electrode of a MOS transistor is electrically isolated from neighboring electrodes by a high quality dielectric that surrounds the floating gate. The contents of the memory, e.g. whether a xe2x80x980xe2x80x99 or a xe2x80x981xe2x80x99 in a digital memory, is determined by the amount of charge on the floating gate.
In a memory known to those of ordinary skill in the art as flash memory, electrons are commonly added to the floating gate by a process of hot electron injection that is controlled by the bias applied to various elements of the floating gate transistor. To remove electrons from the floating gate, electrons tunnel from the floating gate to surrounding electrodes under the influence of a high electric field. In the most common form of this technology, the electrons are caused to tunnel from the floating gate to an underlying silicon region by applying a bias across a relatively thin layer of silicon dioxide. In order that the charge be retained on the floating gate for an extended period of time, it is important that the tunneling operate in what is referred to by those of ordinary skill in the art as the Fowler-Nordheim mode so that the current under cell storage and read conditions is very low, typically less than 10xe2x88x9215 A/cm2.
It has been demonstrated that to restrict tunneling to the Fowler-Nordheim mode, the oxide through which the electrons tunnel should be thicker than about 5 nanometers. Further, the 5 nm lower bound is not a practical limit because the act of applying the voltage across the oxide to cause tunneling damages the oxide. To reduce the stress induced leakage current that occurs due to the damage to the oxide, the minimum oxide thickness should be increased from the lower bound of about 5 nm to about 8 nm. Naruke, K., et al, xe2x80x9cStress Induced Leakage Current Limiting to Scale Down EEPROM Tunnel Oxide Thicknessxe2x80x9d, IEDM Tech. Digest pp. 424-7 (1988).
As integrated circuit (IC) dimensions have been scaled below 0.25 xcexcm, the operating voltages of CMOS circuits have also been scaled down. Unfortunately, it has been demonstrated that the applied voltages typically employed to inject electrons onto and tunnel off of the floating gate of an electrically erasable programmable read only memory (EEPROM) are not capable of being scaled down to the same degree as the operating voltages of below 0.25 xcexcm processes. Yoshikawa, K. et al, xe2x80x9cFlash EEPROM Cell Scaling Based on Tunnel Oxide Thinning. Limitationsxe2x80x9d, Symp. on VLSI Technol. Dig. Tech. Papers, pp. 79-80 (1991); Yamaguchi, Yoshiko, et al, xe2x80x9cONO Interpoly Dielectric Scaling Limit for Non-volatile Memory Devicesxe2x80x9d, Symp. on VLSI Technol. Dig. Tech. Papers, pp. 85-86 (1993); Caywood, J. M. and Gary Derbenwich xe2x80x9cNonvolatile Memoriesxe2x80x9d, in ULSI Device Technology, ed. S. M. Sze and C. Y. Chang, in press.
Because charge leakage through the tunnel oxide limits the scaling of the tunnel oxide thickness and the physics of the phenomena used for injecting charge onto the floating gate limit the scaling of the voltages, it is well understood in the art that the mismatch between the minimum physical dimensions and minimum operating voltages of the floating gate nonvolatile memories and the surrounding CMOS logic technology is becoming increasingly acute. Accordingly, what is needed are new apparatus and methods for charging and discharging the floating gate so that the physical dimensions and required voltages can be reduced to values more compatible with CMOS logic technology.
A tunneling charge injector that includes a conducting injector electrode, a grid insulator disposed adjacent to the conducting injector electrode, a grid electrode disposed adjacent to the grid insulator, a retention insulator disposed adjacent to the grid electrode, and a floating gate disposed adjacent to the retention insulator, may be employed to inject charge from the conducting injector electrode onto a floating gate.
In one aspect of the present invention, the tunneling charge injector may be employed to inject both electrons and holes onto the floating gate electrode. Electrons are injected onto the floating gate when the conducting injector electrode is sufficiently negatively biased with respect to the grid electrode and the floating gate is biased to collect electrons from the grid. Holes are injected onto the floating gate when the conducting injector electrode is sufficiently positively biased with respect to the grid electrode and the floating gate is biased to collect, holes from the grid.
In another aspect of the present invention, separate tunneling electron and hole injectors may be employed to inject electrons or holes onto the floating gate. Electrons are injected onto the floating gate when the conducting injector electrode is sufficiently negatively biased with respect to the grid electrode and the floating gate is biased to collect electrons from the grid. Holes are injected onto the floating gate when the conducting injector electrode is sufficiently positively biased with respect to the grid electrode and the floating gate is biased to collect holes from grid.
In another aspect of the present invention, the tunneling charge injector may be employed in a nonvolatile memory cell having a nonvolatile memory element with a floating gate such as a floating gate MOS transistor. In the nonvolatile memory cell, the floating gate of the tunneling charge injector is coupled to or forms a part of the floating gate of the nonvolatile memory element. The tunneling charge injector is employed to inject charge onto the floating gate of the nonvolatile memory element.
In another aspect of the present invention, separate tunneling electron and hole injectors may be employed in a nonvolatile memory cell having a nonvolatile memory element with a floating gate such as a floating gate MOS transistor. In the nonvolatile memory cell, the floating gates of the separate tunneling electron and hole injectors are coupled to or form a part of the floating gate of the nonvolatile memory element. The tunneling electron injector is employed to inject electrons onto the floating gate of the nonvolatile memory element, and the tunneling hole injector is employed to inject holes onto the floating gate of the nonvolatile memory element.
In another aspect of the present invention, a memory device includes an array of nonvolatile memory cells wherein each of the memory cells comprises a nonvolatile memory element with a floating gate such as a floating gate MOS transistor and a tunneling charge injector having a floating gate that is either coupled to the floating gate of the nonvolatile memory element or forms a portion of the floating gate of the nonvolatile memory element.
In another aspect of the present invention, a memory device includes an array of nonvolatile memory cells wherein each of the memory cells comprises a nonvolatile memory element with a floating gate such as a floating gate MOS transistor, a tunneling electron injector having a floating gate that is either coupled to the floating gate of the nonvolatile memory element or forms a portion of the floating gate of the nonvolatile memory element, and a tunneling hole injector having a floating gate that is either coupled to the floating gate of the nonvolatile memory element or forms a portion of the floating gate of the nonvolatile memory element.
In another aspect of the present invention the tunneling charge injectors and memory devices described herein are equipped with a retention insulator featuring a first band gap in a first portion of said retention insulator disposed adjacent to said grid electrode and a second, greater band gap in a second portion of said retention insulator disposed between said grid electrode and said floating gate to facilitate charge injection.