1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for determining grid dimensions using scatterometry.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
The technologies underlying semiconductor processing tools have attracted increased attention over the last several years, resulting in substantial refinements. However, despite the advances made in this area, many of the processing tools that are currently commercially available suffer certain deficiencies. In particular, such tools often lack advanced process data monitoring capabilities, such as the ability to provide historical parametric data in a user-friendly format, as well as event logging, real-time graphical display of both current processing parameters and the processing parameters of the entire run, and remote, i.e., local site and worldwide, monitoring. These deficiencies can engender nonoptimal control of critical processing parameters, such as throughput, accuracy, stability and repeatability, processing temperatures, mechanical tool parameters, and the like. This variability manifests itself as within-run disparities, run-to-run disparities and tool-to-tool disparities that can propagate into deviations in product quality and performance, whereas an ideal monitoring and diagnostics system for such tools would provide a means of monitoring this variability, as well as providing means for optimizing control of critical parameters.
Semiconductor devices are manufactured from wafers of a substrate material. Layers of materials are added, removed, and/or treated during fabrication to create the electrical circuits that make up the device. The fabrication essentially comprises four basic operations. Although there are only four basic operations, they can be combined in hundreds of different ways, depending upon the particular fabrication process.
The four operations typically used in the manufacture of semiconductor devices are:                layering, or adding thin layers of various materials to a wafer from which a semiconductor device is produced;        patterning, or removing selected portions of added layers;        doping, or placing specific amounts of dopants in the wafer surface through openings in the added layers; and        heat treatment, or heating and cooling the materials to produce desired effects in the processed wafer.        
Among the important aspects in semiconductor device manufacturing are rapid thermal annealing (RTA) control, chemical-mechanical polishing (CMP) control, etch control, and photolithography control. As technology advances facilitate smaller critical dimensions for semiconductor devices, the need for reduction of errors increases dramatically. Proper formation of sub-sections within a semiconductor device is an important factor in ensuring proper performance of the manufactured semiconductor device. Critical dimensions of the sub-sections generally have to be within a predetermined acceptable margin of error for semiconductor devices to be within acceptable manufacturing quality.
Generally, most features on a semiconductor device are formed by depositing layers of material (e.g., conductive or insulative) and patterning the process layers using photolithography and etch processes. The various process layers used for forming the features have many specialized functions. Certain layers are used to form conductive features, others are used to form insulating features, and still others are intermediate layers used to enhance the functionality of the processing steps used to pattern and form the functional layers.
There are many variables that affect the accuracy and repeatability of the photolithography and etch processes used to form features from the process layers. Typical metrology data collection for measuring the efficacy of the photolithography and etch processes do not provide data that is sufficiently accurate and timely to facilitate run-to-run control of such processes. Certain techniques, such as scanning electron microscope (SEM) analysis, may be used to generate two-dimensional data, such as a critical width dimension, but they cannot be used to characterize the entire feature. For example, to generate a sidewall angle measurement, an important measure of quality, a destructive cross-section SEM analysis is required. Destructive tests are expensive, as they require destruction of the wafer, and thus, it is impractical to perform such tests at a frequency that would allow run-to-run control.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.