The present invention relates to programmable circuits. More particularly, the present invention relates to state machines in programmable logic devices.
Non-volatile memory devices, such as EPROM, EEPROM, and Flash EEPROM, store data even after power is turned off. One common application of EEPROMs is in programmable logic devices (PLDs). PLDs are standard semiconductor components purchased by systems manufacturers in a xe2x80x9cblankxe2x80x9d state that can be custom configured into a virtually unlimited number of specific logic functions. PLDs provide system designers with the ability to quickly create custom logic functions to provide product differentiation without sacrificing rapid time to market. PLDs may be reprogrammable, meaning that the logic configuration can be modified after the initial programming.
One type of PLD is known as a Field-Programmable Gate Array (FPGA). An FPGA is a general purpose device that can be programmed by an end user to perform one or more selected functions. An FPGA typically includes an array of individually programmable logic cells (PLCs), each of which is programmably interconnected to other PLCs and to input/output (I/O) pins via a programmable routing structure to provide the selected function. Examples of such devices are exemplified in U.S. Pat. Nos. 4,642,487; 4,706,216; and 4,758,985.
An FPGA device can be characterized as an integrated circuit that may include four major features:
(1) A user-accessible, configurable memory device, such as SRAM, EPROM, EEPROM, anti-fused, fused, or other, is provided in the FPGA device so as to be at least once-programmable by device users for defining user-provided configuration information. Static Random Access Memory or SRAM is a form of reprogrammable memory that may be differently programmed many times. Electrically Erasable programmable ROM or EEPROM is another example of nonvolatile reprogrammable memory. The configurable memory of an FPGA device may be formed of a mixture of different kinds of memory elements if desired (e.g., SRAM and EEPROM).
(2) Input/Output Blocks (IOBs) are provided for interconnecting other internal circuit components of the FPGA device with external circuitry. The IOBs may have fixed configurations or they may be configurable in accordance with user-provided configuration information.
(3) PLCs are provided for carrying out user-programmed logic functions (e.g., logic gates) as defined by user-provided configuration information. Typically, each of the many PLCs of an FPGA has at least one lookup table (LUT) that is user-configurable to define any desired truth table. A PLC may have other resources such as LUT input signal pre-processing resources and LUT output signal post-processing resources.
(4) An interconnect network is provided for carrying signal traffic within the FPGA device between various PLCs and/or between various IOBs and/or between various IOBs and PLCs. At least part of the interconnect network is typically configurable so as to allow for programmably-defined routing of signals between various PLCs and/or IOBs in accordance with user-defined routing information.
Using these features, traditional FPGA architectures implement state machines by using the LUT-based logic elements in a decoding structure and as register storage elements. The state machine typically includes multiple states that are cycled through based on input signals. Typically, every clock cycle, the state of the input signals dictates whether the state machine maintains its current state or changes to a new state. Although state machines may be easily constructed in an FPGA, as the state machine grows large, performance begins to suffer as logic elements invariably get located at greater distances apart, thereby slowing propagation times. Additionally, such state machines consume a lot of area.
Thus, it is desirable to provide a PLD that can free PLC resources while increasing overall functionality. It is also desirable to implement an efficient state machine within a PLD.
A PLD is disclosed that includes a state machine integrated into a block memory. The state machine includes state machine logic and memory elements from the block memory. The state machine logic and memory elements together may be used as an instruction unit of a processor. In such a case, the instruction unit functions as a counter, instruction store, and possibly a decode that is coupled to a processor execution unit to form a high-performance, embedded processor.
In one aspect, the state machine logic includes a program counter and an adder coupled to memory elements within the block memory.
In another aspect, control logic may be added to the state machine to receive state machine inputs and to determine the next state of the state machine.
In another aspect, the state machine may further include a stack pointer that is used to implement a stack within the block memory.
In yet another aspect, the state machine allows for implementing certain classes of instructions, such as jumps, branches and calls. Additionally, processor interrupts can be handled within the memory block.
These and other aspects will become apparent from the following detailed description, which makes reference to the accompanying drawings.