Data processing systems may use virtual addresses to indicate storage locations while the processing system uses physical addresses that represent actual locations on the silicon to store the data in. Virtual addresses may be used to reduce the number of bits required to identify an address location or to allow several processes to access a restricted memory space.
A complete set of current mappings for the virtual to physical addresses are stored in memory, however in order to decrease access time to these mappings, recently used mappings are stored in caches that can be accessed more quickly by the processor. There may be an L1 cache that is fast to access and acts as a micro TLB and stores a small subset of recently used mappings, and a slower L2 cache that is the macro TLB and stores a set of currently used mappings while a full set of page tables of mappings are stored in memory.
The mapping of virtual to physical address space is done in blocks and these may vary in size, thus, these are for example blocks of 1 Gbyte, 2 Mbyte or 4 Kbyte. The number of bits that need to be mapped for a translation depends on the size of the block that an address is located in. If, for example, an address is in a 2 Mbyte block, then only the higher n to 21 bits need to be found from the translation tables, while if it is in the 4 Kbyte block then the n to 12 bits need to be found.
The mappings and the final page sizes are therefore stored in tables in the memory, with the first n to 31 bits that represent 1 Gbyte blocks, being stored in a first table, the next 30 to 21 bits being stored in a next table and so on. A page table walk in memory that is used to retrieve the mappings is performed in steps or walks and where the address is in a larger block only the first step(s) needs to be performed.
When a mapping has been found following a page table walk it is stored in the L2 macro TLB and in the L1 micro TLB.
As can be appreciated retrieving these mappings from memory is expensive in both time and power.
In order to increase efficiency in some data processing systems, the RAM used as the level 2 cache for the macro TLB is also used as a walk cache and as a prefetch buffer, such that in addition to retrieving the requested mapping, a mapping for the subsequent virtual address is retrieved during the same page table walk. This can then be written into the prefetch buffer, after the originally requested mapping has been written into the macro TLB.
The walk cache will store intermediate translations following some of the page table walks, the stored values being an input to a final page table walk required to finish the translation.
In some systems there may be double virtualisation. This occurs where there are several guest OSs and each references a large amount of memory. The memory of the data processing system is not sufficiently large from them to all to reference different distinct portions of memory. Instead they share some memory area but this is not visible to them and is managed by the hypervisor with each guest OS using intermediate physical addresses IPA, that the hypervisor then maps to real physical addresses. In this way the hypervisor controls the memory use and allows each guest OS to believe it has sight of a large dedicated memory space. In this case each guest OS manages the page tables for the VA to IPA translations and the hypervisor manages tables of translations from IPA to PA. In these cases an IPA2PA cache may be provided in the level 2 RAM storing intermediate steps in the IPA to PA translations.