1. Field of the Invention
The present invention relates to a shift clock generator for generating a shift clock, a timing generator for generating predetermined timing and a test apparatus for testing electronic devices.
2. Related Art
Conventionally, a test apparatus for testing electronic devices such as a semiconductor device is provided with a timing generator for generating predetermined timing. For example, the test apparatus supplies a test pattern to the electronic device with the timing generated by the timing generator. The timing generator generates the predetermined timing by receiving a reference clock and by delaying the reference clock by a predetermined time.
The timing generator has a variable delay circuit section for receiving the reference clock and for delaying the reference clock by the predetermined time and a linearize memory for controlling a value of delay in the variable delay circuit section for example. The variable delay circuit section has a plurality of delay elements in general. The linearize memory stores a delay preset value corresponding to linearization of the predetermined value of delay in the variable delay circuit section. Based on the data stored in the linearize memory, the variable delay circuit section delays the reference clock by passing the reference clock through a route of predetermined delay elements. Although the data stored in the linearize memory is set in advance by design information of the plurality of delay elements, an error occurs between the value of delay in the variable delay circuit section and the delay preset value which is the predetermined value of delay due to dispersion in manufacturing the plurality of delay elements and to ambient temperature in using the delay elements for example.
Conventionally, in order to compensate the error, a shift clock having a phase which is different from that of the the reference clock by a predetermined value is generated and the shift clock is outputted to the outside to measure a compensation value of the value of delay of the shift clock by using a measuring instrument and to linearize the value of delay. The shift clock is compared with the output of the variable delay circuit section to detect the error of the value of delay and to select the data to be stored in the linearize memory based on the error.
Presently, the present applicant is unaware of related patent documents, so that description thereof will be omitted here.
Conventionally, in order to generate the shift clock having the predetermined phase difference from the reference clock, pulses are inputted to the shift clock to phase-shift the shift clock by a method as described later in connection with FIGS. 3 and 4. Conventionally, the shift clock is phase-shifted by counting pulses of the shift clock and by inserting insertion pulses per predetermined count. However, there is a case when the phase shift amount of the shift clock does not change linearly with respect to the number of insertion pulses and this method causes an error in the phase shift amount of the shift clock when the phase shift amount of the shift clock does not change linearly with respect to the number of insertion pulses.
There is also a method of using a memory for storing a number of pulses to be inserted per predetermined phase shift amount in order to eliminate such error. However, in order to accurately measure the value of delay in the variable delay circuit section, resolution of the phase shift amount must be increased and a memory having a wide range of addresses is required. Still more, the number of pulses to be inserted must be stored in each address. Because the number of pulses to be inserted is normally around one to several thousands and such memory must have several tens bits in each address, a memory having a large capacity is required.