1. Field of the Invention
This invention relates to a semiconductor integrated circuit device, for example, to a CMOS (Complementary Metal Oxide Semiconductor).
2. Brief Description of the Prior Art
Conventionally, in well known semiconductor integrated circuit devices, for example, ones having a CMOS structure, latchup, which is characteristic of such CMOS device, occurs easily. That is, in adjacent elements (e.g., P channel and N channel MOS transistors), a PNPN or NPNP structured parasitic thyristor occurs and acts to induce malfunction by trigger action of some external factor.
To prevent such latchup, diffusion layers, referred to in general as guardrings, are provided in predetermined areas.
With regard to FIGS. 7 and 8 there is shown an N type well 2 in a P type silicon substrate 1, with P channel MOS transistors 20a and 20b having a source region (a P+ type diffusion region) 9 and drain regions (P+ type diffusion regions) 10, both provided in this N type well 2, (the two drain regions 10 being provided here with the common source region 9).
On the other hand, N channel MOS transistors 20c and 20d include a source region (an N+ type diffusion region) 4 and drain regions (P+ type diffusion regions) 5, both provided in the P type silicon substrate 1, (the two drain regions 5 being provided with the common source region 4). Furthermore, as seen in FIG. 7, a CMOS device (e.g., an inverter circuit) comprises two gate electrodes 7 commonly provided to the P channel MOS transistors 20a and 20b and to the N channel MOS transistors 20c and 20d respectively.
A guardring region (an N+ type diffusion region) 8 is formed in a predetermined area so as to surround the P channel MOS transistors 20a and 20b. However, as seen in FIG. 7, this guardring region 8 is not provided in the area where the gate electrodes 7 cross over the guardring region 8 (i.e., the guardring region 8 is not continuously formed). Referring to reference numerals shown in FIG. 8, 3 is a field oxide film, 6 is a gate oxide film, 8a is an island shaped N+ type diffusion region (a part of the guardring region), 11 is a contact hole, and 12 is an electrode (or contacts) to maintain the guardring region at a supply voltage V.sub.cc.
According to the above structure, as shown in a chart of FIG. 9, the conventional CMOS type 1M dynamic RAM has a higher resistance to latchup when the voltage is applied to the guardring (comparison 2) than when it is not applied thereto (comparison 1). However, the reliability is still insufficient, and the below noted problems remain.
(1) In the area where the gate electrodes 7 cross over the guardring region 8 (directly below the gate electrodes 7), the guardring region 8 is mutilated and not continuously formed, so there is a possibility that latchup may occur through the area without the guardring.
(2) Because there is the island shaped guardring region 8a as described above (one region in this case), a contact 12a must be defined to separately apply the supply voltage V.sub.cc also to this guardring region 8a (a certain area is required to provide this contact). It is difficult to make the contact in such a place with a minimum area so that taking excess area cannot be avoided.