Reference is made to FIG. 1 which shows a schematic diagram of a standard six transistor (6T) static random access memory (SRAM) cell 10. The cell 10 includes two cross-coupled CMOS inverters 12 and 14, each inverter including a series connected p-channel and n-channel transistor pair. The inputs and outputs of the inverters 12 and 14 are coupled to form a latch circuit having a true node 16 and a complement node 18. The cell 10 further includes two transfer (pass gate) transistors 20 and 22 whose gate terminals are coupled with a wordline node and are controlled by the signal present at the wordline node (WL). Transistor 20 is source-drain connected between the true node 16 and a node associated with a true bitline (BLT). Transistor 22 is source-drain connected between the complement node 18 and a node associated with a complement bitline (BLC). The source terminals of the p-channel transistors in each inverter 12 and 14 are coupled to receive a high supply voltage (for example, VDD) at a high voltage node VH, while the source terminals of the n-channel transistors in each inverter 12 and 14 are coupled to receive a low supply voltage (for example, GND) at a low voltage node VL. The high voltage VDD at the node VH and the low voltage GND at the node VL comprise the power supply set of voltages for the cell 10.
In an integrated circuit including the SRAM cell 10, this power supply set of voltages may be received at pins of the integrated circuit, or may instead be generated on chip by a voltage regulator circuit which receives some other set of voltages received from the pins of the chip. The power supply set of voltages at the nodes VH and VL are conventionally applied to the SRAM cell 10 at all times that the cell/integrated circuit is operational. It will be recognized that separate low voltage values at node VL may be provided for the sources of the n-channel MOS transistors in the inverters 12 and 14 while separate high voltage values at node VH may be provided for the sources of the p-channel MOS transistors in the inverters 12 and 14.
The reference above to a six transistor SRAM cell 10 of FIG. 1 for use as the data storage element is made by way of example only, it being understood to those skilled in the art that the cell 10 could alternatively comprise a different data storage element. The use of the term SRAM cell 10 will accordingly be understood to refer any suitable memory cell or data storage element, with the circuitry, functionality and operations presented herein in the exemplary context of a six transistor SRAM cell.
Reference is now made to FIG. 2 which shows a block diagram of a self-timed memory 30, for example of the static random access memory (SRAM) type using SRAM cells 10, with “w” words and “b” bits organized as a column mux of “m”. Those skilled in the art understand that self-timed memories need to support a high dynamic operating voltage range. In other words, these memories need to be functional over a wide range of supply voltages, starting from a very high operating voltage and down to a very low operating voltage. In most cases, in the low operating voltage range, it is considered acceptable if the memory achieves a lower performance (i.e., it is slower). In nominal operating voltage range, the memory needs to support a higher performance (i.e., it needs to be faster).
The memory 30 includes a first section 32 comprising a plurality of memory (such as SRAM) cells 10 arranged in a matrix format and which function to store data. The first section 32 includes “b” sub-sections 34 corresponding to the “b” bits per word stored by the memory. The first section 32 is arranged to store “w” words and is organized as a column mux of “m”. Thus, each of the “b” sub-sections 34 is organized in “w/m” rows with “m” columns in each row. In the first section 32, all cells 10 in a same row share a common wordline (WL) coupled to an output of a row decoder circuit 60 (well known to those skilled in the art), and all cells 10 in a same column share a common true bitline (BLT) and a common complement bitline (BLC) coupled to column circuitry 62 (which includes bitline precharge and equalization circuitry, column mux circuitry, write driver circuitry, column address decoder circuitry and input/output circuitry, each of which is well known to those skilled in the art).
To read data from the first section 32, the wordline of the row selected according to the row address is driven high by the row decoder circuitry 60, a column is selected in each sub-section 34 by the column address decoder and column mux in the column circuitry 62 based on the column address to connect the selected column's true bitline and complement bitline to the input/output circuitry (which, for example, will typically utilize sense amplifiers), and both the true bitline and complement bitline of the selected column in each sub-section 34 are made floating by the precharge and equalization logic in the column circuitry 62. One of the true bitline and complement bitline discharges in each sub-section 34 depending on whether the internal true node 16 or complement node 18 of the memory cell 10 in the selected row and column in the sub-section 34 stores a logic zero. This discharge is sensed by the sense amplifiers corresponding to respective sub-section 34 in the input/output logic of the column circuitry 62 to transfer the stored data state to the respective memory output pin.
The memory 30 includes a second section 46 including plurality of memory cells 10 arranged in a matrix format, but these cells do not function to store data. Indeed, these cells are only required, if desired, in order to have a regular layout of the memory array. The wordline ports of the memory cells 10 both the rows in this section are connected to the ground reference voltage (GND).
The memory 30 includes a third section 36 including plurality of memory cells 10 arranged in a matrix format, and these cells also do not function to store data. Rather, these cells in the third section 36 are used to emulate the same load on a reference wordline (REFWL), which is coupled to a reference row decoder 64 within the section 36, as is present on the actual wordlines (WL) of the first section 32. In other words, the purpose of section 36 is to emulate a total load of “b*m” columns of memory cells 10 on the reference wordline REFWL. It will be noted that the REFWL signal generated by the reference row decoder circuit 64 passes through the second section 46 to the third section 36 without being connected to cells 10 included in section 46.
The section 36 includes “b” sub-sections 38. Each sub-section 38 includes two rows of “m” memory cells 10. All memory cells 10 within the third section 36 either have their true bitlines and complement bitlines connected to a power supply voltage (for example, at node VH) or have them floating. The wordline ports of the memory cells 10 within one of the two rows of the first half of the total “b” sub-sections 38 (i.e., of the first “b/2” sub-sections 38) are coupled to the reference wordline signal generated by the reference row decoder circuit 64 and arriving in section 36 after having passed through the second section 46. This is done to emulate the same propagation delay corresponding to “b*m/2” columns on REFWL as is present on all the WL signals in propagating from row decoder 60 to the middle of section 32. Further, the REFWL signal which has thus reached at or about the center of the section 36 is twisted back and returned towards reference row decoder circuit 64. This returning REFWL signal is connected to the other of the two rows of the first half of the total “b” sub-sections 38 (i.e., of the first “b/2” sub-sections 38), eventually reaching the second section 46 again after experiencing a propagation delay corresponding to travelling across “b*m” columns—same as that experienced by the signal WL in propagating from row decoder 60 to the column farthest from the row decoder 60 at the end of section 32. The reference wordline of the memory cells 10 in both rows within other “b/2” sub-sections 38 (i.e., later “b/2” sub-sections 38) is coupled to a ground supply voltage (at the node VL) because these sub-sections 38 are present in the memory only for maintaining regularity and rectangular shape of the array of the memory cells 10, and so the memory cells 10 in these sub-sections 38 are deactivated permanently by connecting their wordline ports to a ground supply voltage (for example, at the node VL).
The memory 30 further includes a fourth section 40 including a plurality of read timer cells 42 and load cells 44 arranged in a matrix format: “w/m” rows and one column. The timer cells 42 and load cells 44 each have a configuration similar to a memory cell 10, but with different connections as shown, in an exemplary manner, in FIGS. 3A-3C for timer cells 42 and FIGS. 3D-3E for load cells 44.
The timer cells 42 are essentially pre programmed memory (for example, SRAM) cell like elements that are built from the same devices as used by the memory cells 10 in section 32. These timer cells 42 operate to discharge the reference true bitline (REFBLT) in response to arrival of a reference wordline (REFWL) signal (with their discharge time being indicative of time required to discharge of actual bitline until safe detection level during a read operation). It may also be noted that the timer cell configurations in FIGS. 3A and 3B discharge both reference true bitline (REFBLT) and reference complement bitline (REFBLC), and are helpful in using double the number of discharge cells with double the load on the reference bitline for improved statistical variability without any area impact. However, going further, for the purpose of description of functionality only, a description is provided for the use of discharge of only the reference true bitline (REFBLT) at the next logic stage, without any loss in the description of functionality.
The load cells 44 are elements similar to timer cells 42, with the difference that either their reference wordline (REFWL) ports only or both the reference wordline (REFWL) ports and the gate terminal of the pulldown transistor in series with the passgate transistor coupled with reference true bitline (REFBLT) are grounded, so that they do not discharge REFBLT and REFBLC and only serve to match the load of actual bitlines (BLT/BLC) on REFBLT and REFBLC. The wordlines WL generated in the row decoder circuitry 60 simply pass through this section 40 in order to reach the first section 32.
With respect to the timer cells 42, the reference true bitlines (REFBLT) and reference complement bitlines (REFBLC) are shared with each other, respectively, along a column and the reference wordlines (REFWL) for the timer cells 42 are shared with each other and coupled to the reference wordline (REFWL) node at the point emerging from the second section 46 after having traversed through and returned after half the columns in the memory in third section 36. With respect to the load cells 44, the reference wordline (REFWL) ports are grounded as already described earlier. Furthermore, with respect to the timer cells 42 and load cells 44, the reference true bitlines (REFBLT) and reference complement bitlines (REFBLC) are shared with each other, respectively, along a column and connected to the column circuitry 62.
There are a total of “w/m” timer cells 42 and load cells 44, in order to emulate same load on the reference true and complement bitlines within section 40 as is present on the true and complement bitlines within first section 32. A certain number of these “w/m” cells are timer cells 42, and the remaining are load cells 44. Multiple timer cells 42 are used in order to discharge the reference true bitline (REFBLT) at a much faster rate as compared to the rate at which the selected actual memory cells 10 discharge the actual bitlines (BLT or BLC depending on data stored in the respective memory cells 10) during a read operation. The rate of discharge for reference true bitline (REFBLT) is desired to be much faster than the rate of discharge of the actual bitline (true or complement) so that the node REFBLT is able to discharge to a level detectable by an inverter circuit contained within the column circuitry 62 (for example, almost VDD/2) in the same time in which a statistically worst memory cell 10 is able to discharge the actual bitline (BLT or BLC) to a voltage level beyond the offset of the sense amplifiers (contained in column circuitry 62). Also, the multiple timer cells 42 help in reducing statistical variability of the access and cycle time of read operation. This detection of REFBLT discharge is propagated by subsequent logic to generate an enable signal which activates the sense amplifiers (also contained in the column circuitry 62) during a read operation. Thus, the intention of this operation is to time the activation of the sense amplifier at an optimum time permitting a certain statistically worst memory cell 10 in section 32 to clear the sense amplifier offset for reading from that memory cell 10.
A more detailed description of memory operation is now provided. Before any read cycle begins, all memory bitlines and the reference bitlines are precharged to logic high (VDD), and all memory wordlines (WL) and the reference wordline (REFWL) are driven to logic low (GND). At the start of a valid read operation characterized by the “clock” edge when the “chip select” signal is asserted for enabling the memory and the “write enable” signal is asserted to the level corresponding to the read operation, a clock generator triggers the internal clock signal at the arrival of the “clock” edge (either rising or falling edge depending on the functionality of the memory). The internal clock signal causes the following operations to be performed more or less concurrently: a) driving of one of the “w/m” wordlines (WL), selected depending on row address, to logic high (VDD); b) driving of the reference wordline (REFWL) to logic high (VDD); c) turning off of precharge of the reference bitlines (REFBLT, REFBLC) and of the bitlines (BLT, BLC) of one of the “m” columns of each of “b” bits, selected depending on column address; d) connecting one of the “m” true bitline (BLT) and complement bitline (BLC) pairs in each of the “b” bits to the inputs of the sense amplifier circuitry (contained within the column circuitry 62).
The triggering of above operations in turn starts the following operations (performed more or less concurrently): a) the rising of the selected wordline starts an operation in each selected memory cell 10 (in the first section 32) to discharge either the true bitline (BLT) or complement bitline (BLC) based on the stored data; and b) the rising of reference wordline (REFWL) starts an operation in the timer cells and load cells of third section 40 to discharge the reference true bitline (REFBLT).
It will be noted that in each bit (I/O), there is only a single memory cell 10 which causes a discharge of one of the true and complement bitlines (BLT, BLC), but there are multiple timer cells 42 in a column causing a discharge of the reference true bitline (REFBLT). Thus, over a same time period in which one of the true and complement bitlines (BLT, BLC) in any bit (I/O) discharges by a first voltage amount (e.g., x mV), the reference true bitline (REFBLT) would be expected to discharge by a second voltage (e.g., y mV), where y>x, because the number of timer cells 42 discharging the reference true bitline (REFBLT) is greater than the single actual memory cell 10 discharging the bitlines (BLT or BLC) in any bit (I/O). It can also be observed that the time it takes for bitline discharge (i.e., data to be read from any memory cell 10 of the first section 32) is much more variable than what it takes for true reference bitline (REFBLT) discharge from the timer cells 42 of the fourth section 40 because of the presence of multiple timer cells (the standard deviation of the read current of “n” memory cells is known to be “sigma/squareroot(n)” where “sigma” is the standard deviation of a single memory cell 10).
In the memory of FIG. 2, as per the prior art, both the wordline WL and reference wordline REFWL are driven by similarly sized drivers, to a full logic high (VDD), causing the discharge of one of the bitlines (either BLT or BLC depending on data present in the selected memory cell 10 in any bit (I/O)) as well as the true reference bitline REFBLT. The discharge of reference bitline further generates the sense amplifier enable signal. The generated sense amplifier enable signal activates the sense amplifier for each bit (I/O) so as to allow the sense amplifier circuitry to resolve the discharge of one of the true or complement bitlines (BLT, BLC) of the selected column in that bit (I/O) to a logic low (GND) or logic high (VDD). The data resolved by the sense amplifiers of different bits (I/Os) is transferred to memory output (“Q”) of respective bits, thus completing the read operation.
It is desirable to have the timer cells 42 designed and their number chosen such that, in about the same time that a statistically worst memory cell 10 takes to discharge one of the true and complement bitlines (BLT, BLC) beyond the sense amplifier offset voltage, on a certain worst process (P), voltage (V) and temperature (T) condition, the multiple timer cells 42 are able to discharge the true reference bitline REFBLT to a level detectable by a simple detector circuit such as an inverter within the column circuitry 62. That way, the discharge of true reference bitline REFBLT can be detected by the column circuitry 62 to generate the sense amplifier enable signal at an optimum time for performing the read operation successfully and with a least read access and cycle time.
Reference is now made to FIG. 4 which presents a timing diagram illustrating the read operation. From FIG. 4, it can be observed that in order to design a robust memory (i.e., one capable of successful read/write operations in spite of high statistical variability in electrical characteristics of the memory cell 10), it is important to tune the delay duration “TREFBLT” (measuring the delay from initiation of the discharge of the true or complement bitline (BLT, BLC) of any bit (I/O) to a full voltage swing discharge of the true reference bitline REFBLT) in such a way that a read from a statistically worst memory cell 10 is able to provide sufficient voltage differential (partial voltage swing) between the true and complement bitlines (BLT, BLC) to clear the sense amplifier voltage offset for correct operation of sense amplifier resulting in sensing of the appropriate read data. Thus, if “iread” is the read current of a statistically worst memory cell 10, and “irefread” is the current of the “n” timer cells 42, the ideal scenario is to have the ratio “irefread/iread” substantially constant across the process, voltage and temperature conditions of the memory. The ratio should be such that for any process, voltage and temperature condition, the time it takes for one of the true and complement bitlines (BLT, BLC) to discharge beyond the sense amplifier offset is equal to the time it takes for the true reference bitline REFBLT to discharge almost fully and be detected by a simple detector circuit such as an inverter which is used to generate the sense amplifier enable (SAEN) signal.
The issue with the prior art design described above is that the read current (i.e., iread) for a statistically worst memory cell 10 in section 32 is produced by the pass-gate and pulldown transistor devices (see, FIG. 1 and the n-channel passgates 20 and 22 and the n-channel pulldowns within latches 12 and 14) whose threshold voltages (“vtpg” and “vtpd”, respectively) are much higher than those of any nominal memory cell 10 (i.e., memory cell with average read current) within section 32. However, the current which discharges the true reference bitline REFBLT is produced by multiple timer cells 42. Those multiple timer cells 42 coupled together in parallel in section 40, while reducing the statistical variability and hence resulting in discharge current of the timer cell which more nearly matches that of the passgate and pulldown devices for memory cells 10 in section 32 having nearly nominal threshold voltages with multiplicity of number of number of timer cells, is not representative of the statistically worst memory cell 10 (in terms of voltage characteristics). This condition may lead to non-optimal voltage scaling characteristics of sense amplifier enable time and hence also of memory read access time.
The reason for the difference in voltage characteristics mentioned above is that the current of a mosfet as a function of operating voltage is such that the change in current is much greater with change in voltage when the operating voltage of the memory is nearer to the transistor threshold voltage, as compared to when operating voltage of the memory is much higher than the transistor threshold voltage. Thus, those skilled in the art will recognize that as per the design described above, if “n1” timer cells 42 are required for qualifying the statistically worst memory cell 10 read current at a certain low operating voltage (i.e., to achieve a desired irefread/iread ratio), then at a higher operating voltage, because of the discharge current of timer cells 42 increasing by lesser percentage compared to the discharge current of statistically worst memory cell 10, the same “n1” timer cells would lead to a lower “irefread/iread” ratio (i.e., a successful but slower operation leading to sub-optimal access time of read operation). This means that as per design approach described above (primary design parameter is the electrical characteristics of read timer cell 42 and its number), if a memory read self timing is designed to be functional at a certain low voltage using a certain number of timer cells (say “n1”), that same number “n1” timer cells will lead to a much slower operation and hence higher read access and cycle time what is possible to achieve when the memory is operated at a higher voltage. In other words, the performance (read access time and cycle time) will be sub-optimal at higher operating voltages. The amount of extra margin that is undesirably introduced at those higher operating voltages increases as the designed-to minimum operating voltage is lowered.
To address this issue, one prior art circuit uses two different numbers of timer cells 42 (say “n1” and “n2”), to be selectively chosen based on operating voltage of the memory. For example, “n1” timer cells 42 would be used over one range of operating voltage and “n2” timer cells 42 would be used over another range of operating voltages. To assist the operation for selecting a number of timer cells 42 for use, the memory device would include a low voltage control signal input (for example, LV) for selecting the number of timer cells 42. If the control signal input is in a first logic state, then n1 timer cells 42 are enabled for use in discharging the true reference bitline REFBLT, while if the control signal input is in a second logic state, then n2 timer cells 42 are enabled for use in discharging the true reference bitline REFBLT.
Limitations of this prior art solution include: a more complicated system design resulting from having to generate and process the low voltage control signal input (LV) based on operating voltage; and voltage scaling of memory read access and cycle time that are not seamless across the entire operating voltage range because there will be an abrupt change in read performance when the operating voltage changes across the threshold point for low voltage control signal (LV) and the low voltage control signal transitions in response thereto.
More generally speaking, the prior art solutions consider two options.
In a first option, the designer may decide the number of timer cells 42, capacitance on the reference bitline and logic delay subsequent to reference bitline when the reference wordline REFWL level is full logic high level “VDD”, based on the required “wordline on to sense amplifier enable” time for a statistically worst memory cell 10 to generate a voltage differential greater than sense amplifier offset at the inputs of the sense amplifier, at the minimum required memory functional voltage at the worst case temperature and for the worst case process corner, and operate with the same setting on other voltages.
In a second option, the designer may decide the number of timer cells 42, capacitance on the reference bitline and logic delay subsequent to reference bitline at multiple voltage points (typically two) when the reference wordline REFWL=VDD, after sub-dividing the required memory functional voltage range into smaller voltage ranges (typically two), tune the parameters to obtain required “wordline on to sense amplifier enable” time at the lower voltage limit of each range, and then control the selection of respective setting with control pins required to be asserted/deasserted corresponding to the voltage range of operation at any point of time.
Both of the above solutions have shortcomings as described earlier. A need therefore exists in the art to address the foregoing problems with respect to self-timed memory read operation over a wide range of supply voltage. Such a memory will have optimum read access and cycle time at all voltages in the supported voltage range including the nominal (higher) voltage range. Thus, such a memory will have a very low read access and cycle time value in nominal (higher) voltage range required during high frequency operations while still remaining functional for read in a lower operating voltage, without any control signal requirements from the system.