Magnetoresistive random-access memory (“MRAM”) is a non-volatile memory technology that stores data through magnetic storage elements. These elements are two ferromagnetic plates or electrodes that can hold a magnetic field and are separated by a non-magnetic material, such as a non-magnetic metal or insulator. This structure is known as a magnetic tunnel junction (MTJ).
MRAM devices can store information by changing the orientation of the magnetization of the free layer of the MTJ. In particular, based on whether the free layer is in a parallel or anti-parallel alignment relative to the reference layer, either a one or a zero can be stored in each MRAM cell. Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell change due to the orientation of the magnetic fields of the two layers. The electrical resistance is typically referred to as tunnel magnetoresistance (TMR) which is a magnetoresistive effect that occurs in a MTJ. The cell's resistance will be different for the parallel and anti-parallel states and thus the cell's resistance can be used to distinguish between a one and a zero. One important feature of MRAM devices is that they are non-volatile memory devices, since they maintain the information even when the power is off.
MRAM devices are considered as the next generation structures for a wide range of memory applications. MRAM products based on spin torque transfer switching are already making its way into large data storage devices. Spin transfer torque magnetic random access memory (STT-MRAM), or spin transfer switching, uses spin-aligned (polarized) electrons to change the magnetization orientation of the free layer in the magnetic tunnel junction. In general, electrons possess a spin, a quantized number of angular momentum intrinsic to the electron. An electrical current is generally unpolarized, e.g., it consists of 50% spin up and 50% spin down electrons. Passing a current though a magnetic layer polarizes electrons with the spin orientation corresponding to the magnetization direction of the magnetic layer (e.g., polarizer), thus produces a spin-polarized current. If a spin-polarized current is passed to the magnetic region of a free layer in the MTJ device, the electrons will transfer a portion of their spin-angular momentum to the magnetization layer to produce a torque on the magnetization of the free layer. Thus, this spin transfer torque can switch the magnetization of the free layer, which, in effect, writes either a one or a zero based on whether the free layer is in the parallel or anti-parallel states relative to the reference layer.
FIG. 1 shows a conventional MRAM memory array architecture. Two adjacent memory cells 101 and 110 are shown. As shown in the memory cell 100, the MRAM cell has a bit line 102 and a source line 103 to write zeros and ones to an MTJ 104. As shown in cell 100, when the bit line 102 is high (e.g., Vdd) and a source line 103 is low (e.g., Vss) and a word line 106 is high, activating a gating transistor 105, current flows from the bit line 102 through the MTJ 104 to the source line 103, writing a zero in the MTJ 104. This is illustrated as the current 107. As shown in the memory cell 101, when the bit line 110 is low and the source line 111 is high and the word line 112 is high to activate the gating transistor 113, current flows from the source line 111 through the MTJ 114 (e.g., in the opposite direction) to the bit line 110, writing a one, as shown by the current 115.
FIG. 2 shows a conventional MRAM array 200. The array 200 shows columns of cells arranged between respective source lines 240-243 and bit lines 230-233. As fabrication process sizes get smaller and smaller, more and more cells are able to be fabricated within a given die area, effectively increasing the density of a memory array. Increasing density has the benefit of more memory per unit area and less power consumption. As the cell sizes get smaller, an overriding limitation becomes the pitch width of the parallel traces of the source lines 240-243 and the bit lines 230-233. As the array becomes more and more dense with increasingly smaller fabrication processes, a limitation emerges regarding the pitch width 250-252 (e.g., the amount of distance between parallel traces) of the array. This pitch width can approach a minimum. Below the minimum jeopardizes the proper functioning of the array. This minimum pitch width can effectively halt the increasing density of memory arrays even while using increasingly smaller fabrication processes.
Thus what is needed is a way to increase densities of an MRAM array without reducing pitch width below minimums. What is needed is a way to take advantage of advancing semiconductor fabrication techniques without impinging upon the minimum pitch width limits. What is needed is a way to increase MRAM array density and thereby increase performance and reduce costs while maintaining MRAM array reliability.