The present invention relates to electronic circuits, and more particularly to storage elements used in sequential logic circuits.
Flip-flops are widely used in electronics circuits to store data. FIG. 1 is a block diagram of a flip-flop 10 commonly referred to as master-slave flip-flop. Master-slave flip-flop 10 includes a master D-latch 12, a slave D-latch 14, and an inverter 16. When clock signal CLK is at a high logic level (high), slave latch 14 is enabled, i.e., samples the data, and its output Q is the same as the master latch 12 output Y. When clock signal CLK is high, master latch 12 is disabled, i.e., latches (holds) its data. When signal CLK is at a low logic level (low), master latch 12 is enabled and the data in the external D input is transferred to the master latch 12 output Y. When signal CLK is low, slave latch 14 is disabled, holds its data, and thus any changes in the external D input changes the master latch output Y and cannot change the slave output Y. When signal CLK returns to high, master latch 12 is in the latched mode and is isolated from the D input. At the same time, slave latch 14 is enabled and the value of Y is transferred to the output Q.
A D-latch may be formed using transmission gates and inverters, as shown in FIG. 2. Input CLK controls the two transmission gates 22, 24. When CLK is low, transmission gate 22 has a closed path and transmission gate 24 has an open path, therefore, D-latch 20 is in a sampling mode. This cause output Q to be the inverse of input D and output Q to be the same as input D. When CLK is high, transmission gate 24 has a closed path and transmission gate 22 has an open path, therefore, D-latch 20 is in a holding mode; this causes outputs Q and Q to hold their previous values.
A need continues to exist for a flip-flop that can operate at higher data rates for any given clock frequency.