1. Field of the Invention
The disclosure relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device having an increased trap site density and a method of manufacturing the same.
2. Description of the Related Art
In semiconductor memory devices, especially DRAMs (Dynamic Random Access Memory), a unit memory cell includes one transistor and one capacitor. Therefore, to increase the integration density of semiconductor memory devices, the volume of the transistor or the capacitor must be reduced.
In early semiconductor memory devices when the integration density was not a large concern, photography and etching processes could be performed with sufficient process margins. The integration density of semiconductor memory devices could be increased by reducing the volume of each element of the memory device.
However, as the demand for highly integrated semiconductor memory devices increases, a different method to reduce volume is needed.
The integration density of a semiconductor memory device is closely related to a design rule. Therefore, to increase the integration density, the design rule must be strict. In this case, the process margins of photography and etching processes can be significantly reduced, meaning that these processes must be performed more precisely.
When the process margins of the photography and etching processes are reduced, the yield can also be reduced. Therefore, a method to increase the integration density of semiconductor memory devices without reducing the yield is needed.
According to this requirement, many semiconductor memory devices having different structures than conventional semiconductor memory devices have been introduced by including a data storing medium that can store charge on the upper side of a transistor, with a different data storing function.
The SONOS (Semiconductor-Oxide-Nitride-Oxide-Semiconductor) memory device is another newly introduced semiconductor memory device. FIG. 1 is a cross-sectional view illustrating a conventional memory device.
Referring to FIG. 1, a source region 12 and a drain region 14 to which an n type conductive dopant is implanted on a p type semiconductor substrate 10 (hereinafter, semiconductor substrate) are formed. A channel region 16 is formed between the source region 12 and the drain region 14. Also, a gate stack 18 is formed on the channel region 16 of the semiconductor substrate 10. The gate stack 18 is composed of a tunneling oxide film 18a, a nitride film Si3N4 18b, a blocking oxide film 18c, and a gate electrode 18d. Here, the nitride film 18b has trap sites. Therefore, when a voltage is applied to the gate electrode 18d, electrons pass through the tunneling oxide film 18a and are trapped in the trap site of the nitride film 18b. The blocking oxide film 18c blocks the migration of electrons to the gate electrode 18d while the electrons are trapped.
In this conventional semiconductor memory device, binary scale information can be stored and read using the characteristic that the threshold voltage varies depending on whether electrons are trapped in the trap site of the nitride film 18b. 
When the density of a trap site increases, more electrons can be trapped, and the variation of the threshold voltage can be increased. That is, the density of the trap site can significantly affect the characteristics of the memory device. Conventionally, to increase the density of a trap site, techniques of scattering or depositing nano-scale particles on the surface of a thin film have been developed. However, these methods can only provide limited increases in the density of the trap site per unit area. These methods have various technical problems, especially with respect to uniformity in the flash memory. Also, in the case of conventional memory devices, the only way to increase the integration density is to reduce the volume. However, since this makes the design rule more strict, there is a limit to increasing the integration density of memory devices by reducing their volume.