1. Field of the Invention
The present invention generally relates to digital data processing systems and more particularly relates to large scale digital data processing systems having multiple, asynchronously clocked processing components.
2. Background of the Invention
It is well known to design digital data processing systems using a number of separate processing components. As the required computational capacity increases, it is easier to meet the need with a number of separate components using a parallel processing architecture rather than attempt to provide a single large capacity device. The limit of this approach is determined by the degree to which a processing task may be accomplished by the separate processing components operating in parallel.
Given that a system has been implemented using a number of separate processing entities, the necessity to communicate amongst them arises. A simple form of such communication is via the input/output capability of a processor. Using this approach, each processor appears as a peripheral device to each of the other processors to which it is interconnected. Various early real time systems, such as the Naval Tactical Data System (i.e. NTDS) utilized this technique. Today, many intra-office personal computers are coupled in this fashion in a network.
The major advantage of this input/output approach is the ease and simplicity by which it is implemented. However, this interface technique is inherently slow. Though the bandpass tends to be sufficient for processor to peripheral communication, because of the limited internal speed of most peripheral devices, this method is very slow when compared to internal processor speeds. The technique is further limited by its software control, which makes it unsuitable for a number of maintenance and control tasks requiring a more complete control of the hardware.
An approach having substantial promise involves scan/set communication. In the earliest form, this provided multiprocessor systems with the capability for a processor to read/modify/write to a shared memory location. Most often, individual memory bits were defined as control flags permitting multiple, asynchronous processors to share various tasks and resources. Scanning and controlling flags in this manner substantially speeds the intercommunication amongst processors. However, because this use of the scan/set approach is software oriented, it possesses the same disadvantages with regard to maintenance and control tasks as with other software approaches.
A significant contribution to the use of scan/set intercommunication is found in U.S. Pat. No. 4,996,688, issued to Byers, et al. In this reference, a separate scan.backslash.set interface is established among the microcontrollers which provide the control logic for the various components within a system. Thus, status and control information is readily transferred amongst system components. This communication occurs under firmware control. Therefore, it is inherently faster than similar transfers under software control. Furthermore, because the transfers are at the level of the basic logic control, hardware control and status information can be exchanged, particularly for maintenance purposes.
Though the Byers et al. approach to scan/set communication is rapid, the total bandpass is very limited, because only discrete command and status signals are transferred. There is no provision of the interface for sending and receiving larger data sets.