1. Field of the Invention
The present invention relates generally to memory devices and, more particularly, to characterization of memory devices which implement a delay locked loop to synchronize input signals to the memory devices.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Microprocessor-controlled integrated circuits are used in a wide variety of applications. Such applications include personal computers, vehicle control systems, telephone networks, and a host of consumer products. As is well known, microprocessors are essentially generic devices that perform specific functions under the control of a software program. This program is stored in a memory device which is coupled to the microprocessor. Not only does the microprocessor access memory devices to retrieve the program instructions, but it also stores and retrieves data created during execution of the program in one or more memory devices.
There are a variety of different memory devices available for use in microprocessor-based systems. The type of memory device chosen for a specific function within a microprocessor-based system generally depends upon which features of the memory are best suited to perform the particular function. Memory manufacturers provide an array of innovative fast memory chips for various applications, including Dynamic Random Access Memories (DRAM), which are lower in cost but have slower data rates, and Static Random Access Memories (SRAM), which are more costly but offer higher data rates. Although both DRAMs and SRAMs are making significant gains in speed and bandwidth, even the fastest memory devices cannot match the speed requirements of most microprocessors. Regardless of the type of memory, the solution for providing adequate memory bandwidth depends on system architecture, the application requirements, and the processor, all of which help determine the best memory type for a given application. Limitations on speed include delays in the chip, the package, and the system. Thus, significant research and development has been devoted to finding faster ways to access memory and to reduce or hide latency associated with memory accesses.
Because microprocessor technology enables current microprocessors to operate faster than current memory devices, certain techniques for increasing the speed of memory devices are often implemented. For example, one type of memory device that can contribute to increased processing speeds in the computer system is a Synchronous Dynamic Random Access Memory (SDRAM). An SDRAM differs from a standard DRAM in that the SDRAM includes input and output latches to hold information from and for the processor under the control of (i.e., synchronous with) the system clock. Because input information (i.e., addresses, data, and controls signals) is latched, the processor may perform other tasks while waiting for the SDRAM to finish its task, thereby reducing processor wait states. After a predetermined number of clock cycles during which the SDRAM is processing the processor""s request, the processor may return to the SDRAM and obtain the requested information from the output latches.
A technique for increasing the speed of an SDRAM is to implement a Double Data Rate (DDR) SDRAM. In a DDR memory device, the data transfer rate is twice that of a regular memory device, because the DDR""s input/output data can be strobed twice for every clock cycle. That is, data is sent on both the rising and falling edges of the clock signal rather than just the rising edge of the clock signal as in typical Single Data Rate (SDR) systems.
In high speed memory devices such as DDR SDRAMs, it is often desirable to synchronize the timing of certain signals, such as clock signals and data signals which may be external to the memory devices, with internally generated clock signals or data signals, or with other external signals. One means of synchronizing signals is by implementing a delay locked loop (DLL) circuit. The DLL circuit is used to create an output signal that is matched in terms of frequency and/or phase to the input signal, which may be an external clock signal, for example. In DLL circuits, an input buffer is used to receive an input signal and to transmit the signal to one or more delay lines. The delay line includes a number of delay elements. A phase detector may be used to compare the input clock signal to the output signal by using a feedback loop. The information can then be fed from the phase detector to a shift register to move through the delay elements in the delay line incrementally to search for a match. When the input signal and output signal are equal, as indicated by a phase difference which is essentially equal to zero (typically within +/xe2x88x9211 degrees), the signals are synchronized, and the DLL is considered locked.
It should also be understood that memory devices are typically mass produced by fabricating thousands of identical circuit patterns on a single semiconductor wafer and subsequently dividing them into identical die or chips. To produce the integrated circuit, many commonly known processes are used to modify, remove, and deposit material onto the semiconductor wafer, which is generally made of silicon. Once the active and passive parts are fabricated in and on the wafer surface, one or more layers of conductive material, such as metal, for electrically connecting circuit components are added, and a protective layer is deposited over the silicon wafer. The wafer is visually evaluated and electrically tested to determine which memory devices are good so that they may be packaged for use. After the memory devices are tested in wafer form, they may be separated through a sawing process. The electrically good die are generally packaged, and the packaged device may again be tested using various testing systems.
For memory devices which incorporate a DLL circuit, electrical testing and characterization of the DLL circuit is generally performed while the device is still in wafer form. As previously discussed, the delay lines incorporated in the DLL circuits generally include a number of delay elements. Depending on variables such as the input voltage, clock period, temperature, etc., the DLL may lock at a particular xe2x80x9centry point.xe2x80x9d The entry point refers to the location along the delay line, corresponding to some number of delay elements, at which a signal lock is achieved. The delay loop is locked when the difference between the phase of the input and the output of the delay line in the DLL is essentially zero. Because the devices may be produced to function over various frequency ranges, the entry point may change for a given signal. However, knowing the entry point of various devices over varying input voltages, for instance, for a given design provides designers with information to implement improvements and changes for various applications. For this reason, the DLL is typically tested using a tester and oscilloscope to track the entry point of each device while it is still in wafer form. The current method of entry point characterization requires direct access to the internal DLL signals, and thus dictates that the DLL be tested before it is packaged. Disadvantageously, this process is tedious and labor intensive due to the manual nature of the tests. Further, although testing the DLL while the device is still in wafer form may provide useful information, the characteristics of the DLL may change once the device is packaged.
The present invention may address one or more of the problems set forth above.