The dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits is the metal-oxide-semiconductor field effect transistor (MOSFET) technology. The reduction in the size of MOSFETs has provided continued improvement in speed, performance, circuit density, and cost per unit function over the past decades. As the gate length of the conventional MOSFET is reduced, the source and drain areas increasingly interact with the channel and influence the channel potential. Consequently, transistors with short gate lengths suffer from problems related to the inability of the gate electrode to substantially control the “on” and “off” states of the channel. Phenomena such as reduced gate control associated with transistors with short channel lengths are termed short-channel effects. Increased body doping concentration, reduced gate oxide thickness, and ultra-shallow source-drain junctions are ways to suppress short-channel effects. For device scaling well into the sub-50 nanometer regime, however, the requirements for body-doping concentration, gate oxide thickness and source/drain (S/D) doping profiles has become increasingly difficult to meet with conventional device structures based on bulk silicon substrates. Innovations in front-end process technologies with the introduction of alternative device structures are needed to sustain the historical pace of device scaling.
As technology continues into the sub-30 nanometer regime, the promising approach for controlling short-channel effects is to use an alternative transistor structure with more than one gate, i.e., multiple gate transistors. An exemplary multiple gate transistor is shown in the plan view of FIG. 1 which represents the prior art. The multiple gate transistor of FIG. 1 includes a semiconductor fin 2 formed over insulator 4 which is formed over a substrate. Gate electrode 8 straddles semiconductor fin 2 and a gate dielectric (not shown) is disposed between semiconductor fin 2 and gate electrode 8. The transistor active areas (source, drain and channel) are formed in the semiconductor fin. Examples of multiple-gate transistors include double-gate transistors, triple-gate transistors, omega field-effect transistors, and a surround-gate or wrap-around gate transistor. Multiple-gate transistor structures are expected to extend the scalability of CMOS technology beyond the limitations of conventional bulk MOSFET and realize the ultimate limit of silicon MOSFETs. The introduction of additional gates in the multiple-gate transistors improves capacitive coupling between gates and the channel, increases the control of the channel potential by the gate, helps suppress short-channel effects, and extends the scalability of the MOS transistor.
The simplest example of a multiple-gate transistor is the double-gate transistor such as described in U.S. Pat. No. 6,413,802 B1 issued to Hu et al., the contents of which are hereby incorporated by reference. FIG. 2A is a prior art cross-sectional view of a double-gate transistor and illustrates gate electrode 8 that straddles the channel formed in the semiconductor fin structure 2, thus forming a double-gate structure. Semiconductor fin 2 includes fin height 18 and fin width 6. There are two gates, one on each sidewall 12 of semiconductor fin 2, along which gate dielectric 14 extends. U.S. Pat. No. 6,413,802 B2 provides that the semiconductor fin that forms the transistor channel, is a thin silicon fin defined using an etching mask and formed on an insulating layer such as insulator 4, which is a silicon oxide layer formed over silicon substrate 10. A gate oxidation process is performed prior to the removal of etching mask 16 and the oxidation process is followed by gate material deposition and patterning that forms gate electrode 8 which traverses (i.e. straddles) semiconductor fin 2 to form a double-gate structure overlying the top (etching mask 16) and sidewalls 12 of semiconductor fin 2. Both the source-to-drain direction and the gate-to-gate direction are along the plane of the substrate surface.
Another example of a multiple-gate transistor known in the art is a triple-gate transistor, an exemplary one of which is illustrated FIG. 2B. The plan view of such an exemplary triple-gate transistor is as illustrated in FIG. 1. The triple-gate transistor has a gate electrode that forms three gates: one over top surface 20 of semiconductor fin 2, and the other two along fin sidewalls 12 as in the double-gate structure shown in FIG. 2A. Gate dielectric 14 extends along sidewalls 12 and top surface 20.
FIG. 2C shows an omega field-effect transistor (FET) or simply omega-FET, so called because the gate electrode has an omega type shape in the cross-sectional view. The omega-FET is a variation of the triple-gate transistor shown previously in FIG. 2B as gate dielectric 14 extends along sidewalls 12 and over top 20. Gate electrode 8 encroaches semiconductor fin 2 at encroachment locations 28 due to notch 24 that extends beneath semiconductor fin 2 due to the recession of the upper surface of insulator 4. The omega-FET resembles a gate-all-around (GAA) transistor, provides excellent scalability and is manufactured using a very manufacturable process similar to that of the double or triple-gate transistor. Due to the gate extension or encroachment beneath the semiconductor fin, the omega-FET is an FET with a gate that almost wraps around the fin body. The encroachment 28 of gate electrode 8 under semiconductor fin 2 helps to shield the channel from electric field lines from the drain and improves gate-to-channel controllability, thus alleviating the drain-induced barrier lowering effect and improving short-channel performance.
The described multiple-gate transistor structures, i.e., the double-gate transistor, the triple-gate transistor and the omega-FET, have a common feature in that the sidewall surfaces of the semiconductor fins are used for a significant amount of source-to-drain current conduction. Essentially, the effective gate width of the multiple-gate transistor is a function of the fin height. In a double-gate transistor, the gate width is twice the fin height and in a triple-gate transistor, the gate width is twice the fin height plus the fin width. (Fin height 18 and fin width 6 are shown in FIGS. 2A and 2B.) As such, as fin height increases, the amount of current deliverable by the device similarly increases. To deliver maximum current, then, it is desirable to maximize fin height. A tradeoff exits, however, because as fin height increases, it becomes increasingly difficult to form the gate electrode by patterning the gate material that is formed over the fin. This undesirable aspect is also common to all of the aforementioned gate transistors.
Each of the multiple-gate transistors includes a semiconductor fin that forms the active region and is disposed above the substrate surface. The formation of a gate electrode that straddles the semiconductor fin involves the deposition of a substantially conformal gate electrode material over the semiconductor fin followed by a definition step using techniques such as photolithography and an etching step such as plasma etching, to form the gate electrode. The formation of the gate electrode over the large step height introduced by the semiconductor fin presents a very challenging problem. As deposited, the substantially conformal gate electrode material has a non-planar top surface with a significant step as it traverses the semiconductor fin. This is shown in FIG. 3A. Surface 34 of gate electrode material 8 is clearly non-planar and therefore presents patterning problems.
FIG. 3B shows mask material 38 formed over the structure shown in FIG. 3. Mask material 38 may be a photoresist or other photosensitive material and is commonly formed by spin-coating which produces a planar top surface 40. It can therefore be seen that the thickness of the mask material varies from greater thickness 44 to lesser thickness 42 over step 52 influenced by semiconductor fin 2. This varying thickness makes it difficult to accurately transfer the pattern on the lithographic mask 46 to mask material 38. The pattern may be considered opaque region 48 within transparent region 50 of the exemplary lithographic mask 46. Opaque region 48 has a constant width. The thinner portions 42 of mask material 38 over step 52 are thinner than other portions 44 of mask material 38 and are effectively exposed to a greater extent than other portions of the mask material. After exposure and develop, the patterned mask material 54 may be formed with different widths as shown in FIG. 3C. FIG. 3C shows that narrow portion 56 of patterned mask material 54 over step 52, is substantially narrower than other portions of pattern mask material 54. When unmasked portions 58 of gate electrode material 8 are subsequently etched to expose insulator 4 such as shown in FIG. 3D, the etched gate electrode 62 is formed with a non-uniform gate length, i.e., narrow portion 64 is narrower than other portions of etched gate electrode 62. This is also shown in the plan view of FIG. 3E which shows patterned gate electrode 62 having narrow portion 64 with width 65 representing a gate length and other portion 66 with width 67. It can be seen that width 67 is greater than gate length 65 even though formed from a mask feature (48) having constant width. The gate width of vertical portion 63 shown in FIGS. 3D and 3E, may be anywhere between width 65 and width 67. The non-uniform and uncontrollable critical gate length dimension is undesirable and represents one shortcoming of conventional multiple-gate transistor technology.
Another shortcoming of the conventional technology used to form multiple gate transistors is that the gate electrode is usually doped in the same process operation used to dope the source and drain regions. In conventional transistors, the gate electrode is substantially planar, as are the source and drain regions. In a multiple-gate transistor or semiconductor fin device, however, both the gate electrode and the source and drain regions are essentially three dimensional structures. Because the source/drain, and gate electrode materials have different doping requirements, both spatially and concentration-wise, it would be desirable to introduce dopant impurities in the source/drain region and the gate electrode material in different processing operations.
U.S. Pat. No. 6,413,802 B1 (Hu et al.) and U.S. Pat. No. 6,432,829 to Muller et al., hereby incorporated by reference as if set forth in its entirety, provide processes for manufacturing multiple-gate transistors. Neither of these references teach the planarization of the gate electrode material prior to photolithographic patterning of the gate electrode, however. U.S. Pat. No. 6,492,212 issued to leong et al., hereby incorporated by reference as if set forth in its entirety, provides a method for forming a double-gate transistor using several planarization steps to form the gate electrode of a multiple-gate transistor. The multiple planarization steps required by this reference, however, increase manufacturing costs. Additionally, U.S. Pat. No. 6,492,212 fails to provide methods for optimizing the doping of the gate electrode and the source/drain regions of the multiple-gate transistors.
The present invention is directed to addressing the above-described shortcomings associated with multiple-gate transistor manufacturing technologies.