(1) Field of the Invention
The present invention relates to semiconductor integrated circuits, and more particularly to a method for fabricating an array of dynamic random access memory (DRAM) cells with brush-shaped stacked capacitors to increase the capacitance. The brush-shaped capacitors are formed from a hemispherical grain polysilicon layer that is used as a hard mask to increase the surface area of the capacitor bottom electrodes.
(2) Description of the Prior Art
Dynamic random access memory (DRAM) circuits (devices) are used extensively in the electronics industry, and more particularly in the computer industry for storing data in binary form (1 and 0) as charge on a storage capacitor. These DRAM devices are made on semiconductor substrates (or wafers) and then the substrates are diced to form the individual DRAM circuits (or DRAM chips). Each DRAM circuit (chip) consists in part of an array of individual DRAM storage cells that store binary data (bits) as electrical charge on a storage capacitor. Further, the information is stored and retrieved from the storage capacitor by means of switching a single access transistor (via word lines) on or off in each memory cell using peripheral address circuits, while the charge stored on the capacitor is sensed by means of bit lines and by read/write circuits formed on the periphery of the DRAM chip.
The access transistor for the DRAM device is usually a field effect transistor (FET), and the single capacitor in each cell is either formed in the semiconductor substrate as a trench capacitor, or built over the FET in the cell area as a stacked capacitor. To maintain a reasonable. DRAM chip size and improved circuit performance, it is necessary to further reduce the area occupied by the individual cells on the DRAM chip. Unfortunately, as the cell size decreases, it becomes increasing more difficult to fabricate stacked or trench storage capacitors with sufficient capacitance to store the necessary charge to provide art acceptable signal-to-noise level for the read circuits (sense amplifiers) to detect. The reduced charge also requires more frequent refresh cycles that periodically restore the charge on these volatile storage cells. This increase in refresh cycles further reduces the performance (speed) of the DRAM circuit.
Since the capacitor area is limited to the cell size in order to accommodate the multitude of cells on the DRAM chip, it is necessary to explore alternative methods for increasing the capacitance without increasing the lateral area that the capacitor occupies on the substrate surface. In recent years the method of choice is to build stacked capacitors over the access transistors within each cell area, rather than forming trench capacitors that need to be etched to increasing depths in the substrate to maintain the necessary capacitance. The stacked capacitors also provide increased latitude in capacitor design and processing while reducing cell area. More specifically, the stacked capacitors can be extended in the vertical direction (third dimension) to increase the stacked capacitor area, and therefore to increase the capacitance.
Many methods of making DRAM circuits using stacked capacitors have been reported in the literature. One method is to use polysilicon Hemispherical Shaped Grains (HSG) as a mask to etch deep vertical grooves in a capacitor bottom electrode. This MOdulated STacked (MOST) capacitor is described by Jun et al. in an article entitled "The Fabrication and Electrical Properties of Modulated Stacked Capacitors for Advanced DRAM Applications," IEEE Electron Device Letters, Vol. 13, No. 8, Aug. 1992, pages 430-432. Other methods in which hyperfine patterns are etched in the capacitor electrode using HSG structures are also taught by Jun et al. in U.S. Pat. No. 5,256,587 and by Jun in U.S. Pat. No. 5,342,800. Another method is described by Ahn, in U.S. Pat. No. 5,134,086 in which an HSG structure is replicated in a thin oxide mask over a polysilicon capacitor node electrode. The mask is then used to selectively etch the node electrode to increase the surface area.
There has been considerable work done to increase the capacitance area using hemispherical grain structures as etch masks to increase the area of the capacitor. However, it is still desirable to further improve on these capacitors using the hemispherical grain (HSG) structure as a hard mask, and including portions of the HSG structure in the capacitor to further increase the capacitance.