Among existing non-volatile memory-based ICs, flash memory is the most advanced of its kind. A distinguishing feature of a conventional flash memory is that, in addition to an oxide insulating layer typically formed in a conventional MOSFET, a floating gate is formed in between a gate and a channel in the MOS of the tradition flash memory, such that data are stored by introducing into or removing from the floating gate negative charges. However, as regards conventional flash memory, the gate is made of doped polysilicon. With the conventional floating gate, electric conduction is achieved, using charges stored in doped polysilicon which forms the floating gate. Charges are stored in the doped polysilicon and thus they move freely within the doped polysilicon. Charges will hardly be maintained in the doped polysilicon, if there is a current leakage from any point of a tunnel oxide layer beneath the polysilicon floating gate. Moreover, the tunnel oxide layer will have to be thinned down if the size of the memory is to be reduced. However, whatever thinning-down effort is subject to the physical limit of direct tunneling, and thus a thinning down process does have its own limit.
In view of this, U.S. Pat. No. 5,714,766 proposes a nano-structure memory device. FIG. 1 (PRIOR ART) is a cross-sectional view of a nanocrystal memory 100 known in the prior art. The nanocrystal memory 100, which has a basic structure of a transistor comprising a substrate 101, a source 102, a drain 103, a tunnel oxide layer 104, and a gate 105, coupled with nanocrystals 106 embedded in a nanocrystal layer 107 between the gate layers, allows charges to be stored. The proposed nano-structure memory device not only solves the drawbacks of flash memory, namely high operating voltage and slow reading speed, but also enhances memory retention. Unlike a conventional polysilicon floating gate, the proposed nano-structure memory device has charges stored in spaced-apart nanocrystals, and the spaced-apart nanocrystals do not move in relation to each other. The proposed nano-structure memory device overcomes a drawback of the prior art, that is, it is difficult to store charges (wherein charges are stored in polysilicon which forms a floating gate to achieve electric conduction in accordance with the prior art) in the presence of a current leakage from any point of a tunnel oxide layer underlying the conventional polysilicon floating gate. Moreover, the conventional polysilicon floating gate achieves charge blocking solely by being barrier-dependent, thus causing insurmountable difficulty in a thinning-down process performed on the tunnel oxide layer. However, the nanocrystals provide insulation required for quantum confinement, so as to store charges in quantum wells. In the absence of an applied voltage, charges are confined to the quantum wells and thereby are stored, allowing the tunnel oxide layer to be thinned down further.
Although the insurmountable difficulty in the foregoing design of the polysilicon floating gate is solved (by thinning down the tunnel oxide layer and thereby enabling charges to enter the quantum wells readily and thereby be stored), but charges stored in the silicon nanocrystal floating gate may readily tunnel out and hardly be retained, because disposed between the channel and the nanocrystals is a mere insulating layer, that is, the tunnel oxide layer.
To address the foregoing problems, academics suggest that charge loss should be prevented by an improved floating gate made of self-aligned double layered silicon (R. Ohba, IEDM, December 2000). Referring to FIG. 2B (PRIOR ART), a nanocrystal structure known in the prior art is replaced with a double layered nanocrystal structure 200. Referring to FIG. 2A (PRIOR ART), the fabricating method comprises the steps of: growing a tunnel oxide layer 204 on a silicon substrate 201; depositing a silicon layer 208 on the tunnel oxide layer 204; forming an oxide layer 209 on the silicon layer 208; depositing a silicon dot 210 (Si dot) on the oxide layer 209; and oxidizing the silicon dot 210 before finalizing the self-aligned double layered silicon structure as shown in FIG. 2B (PRIOR ART). Silicon nanocrystals 211 are formed by a portion of the silicon layer 208 covered by the silicon dot 210 and thereby not oxidized. With the double layered quantum well structure, after charges are stored in the nanocrystals, it is difficult for subsequent charges to enter the nanocrystals because of Coulomb blockade. Accordingly, charges are confined to the quantum wells and are unlikely to tunnel out due to Coulomb blockade; therefore, charge retention is enhanced.
However, this method still has practical drawbacks. Although its structural theory is better than the foregoing single layered nanocrystal, but insurmountable difficulty still exists in practice when fabrication parameter is considered. If the previous level of the operating voltage is to be maintained or even lowered, the oxide layer will have to be thinned down, but the thinning down process will cause a memory retention problem. Although memory retention can be enhanced if the thickness of the oxide layer is increased, the operating voltage is compromised.
In addition to the aforesaid problems, a nanocrystal fabrication process has to address an issue, that is, the control of the formation of nanocrystals during the fabrication process. For instance, it will be impossible to store enough charges in a nanocrystal layer disposed with nanocrystals, if the nanocrystals disposed in the nanocrystal layer are too small or over-dispersed; as a result, the charges present in a channel beneath an oxidation layer decrease, causing difficulty in interpretation. In other words, in the event that few charges are stored in the nanocrystal layer, there will be a negligible difference between a threshold voltage associated with the presence of nanocrystals in the nanocrystal layer and a threshold voltage associate with the absence of nanocrystals from the nanocrystal layer, and in consequence it is impossible to determine whether charges are stored in the nanocrystal layer and perform effective interpretation. Accordingly, a nanocrystal fabrication process should be preferably provided with sufficient nanocrystals to store charges so as to create a significant difference between the threshold voltage associated with the presence of charge storage and the threshold voltage associated with the lack of charge storage, thereby enabling the memory to perform effective interpretation.
There are presently two methods for storing more charges, namely enhancing nanocrystal density, and increasing the number of charges stored in each nanocrystal. According to current technology, it is difficult to increase nanocrystal density, and thus considerations are given to attempts to store more charges in each nanocrystal. However, after a charge is stored in a nanocrystal, it is difficult for the next charge to enter the well and be stored in the nanocrystal because of an increase in potential energy. Even if the charge is forcibly stored in the well, the barrier will be insufficient to stop the charge from tunneling out; as a result, the charge tunnels into an oxide layer and fails to be stored in the nanocrystal.
Therefore, metal nanocrystal is used, which has higher charge storage density due to a metal has more states in conduction band compared to the silicon nanocrystal. Moreover, a metal with a higher work function can be chosen to be the nanocyrstal to enhance the potential barrier of a quantum well, so as to enhance charge retention.
The urgent problem to be solved is to maintain the foregoing advantages of silicon nanocrystal when operating voltage and charge retention are considered, and keep the foregoing advantages of metal crystals such as containing more charges.