The present disclosure relates to a method of patterning a structure, and more particularly to a non-lithographic method of patterning a structure employing successive mask erosion, and structures formed by the same.
Semiconductor device scaling has been limited by the limitations of lithographic tools. For example, dimensions of minimum printable features have been limited by the capabilities of available lithographic tools to print such features. The slow progress in the capabilities of lithographic tools in recent years has made it difficult to aggressively scale the pitch of line level patterns near critical dimensions.