SiC has a large band gap and has larger maximum dielectric breakdown electric field and thermal conductivity than those of silicon (Si). Moreover, SiC has a carrier mobility as large as that of silicon, and has large electron saturation drift velocity and large breakdown voltage. Accordingly, it is expected to apply SiC to a semiconductor device required to achieve high efficiency, high voltage, and large capacity. An exemplary method for manufacturing such a SiC semiconductor device is a technique disclosed in Japanese Patent Laying-Open No. 2008-294204 (Patent Literature 1).
Patent Literature 1 discloses that in a method for manufacturing a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) serving as a SiC semiconductor device, thermal oxidation of approximately 1000° C. is performed in each of an ion implantation step performed before forming a gate oxide film; a sacrificial oxidation and sacrificial oxide film removing step of removing surface roughness resulting from activation heating treatment; and a gate oxide film forming step. It is also disclosed that in performing the thermal oxidation in each of the sacrificial oxidation and sacrificial oxide film removing step and the gate oxide film forming step, rate of the thermal oxidation greatly differs between a region having an impurity implanted therein and a region having no impurity implanted therein.
In Patent Literature 1, in view of the problem, the following method for manufacturing a MOSFET is disclosed. FIG. 13 and FIG. 14 are cross sectional views showing steps in manufacturing the MOSFET in Patent Literature 1. As shown in FIG. 13, an n− epitaxial layer 202 is epitaxially grown on a SiC substrate 201. Ions are implanted into this n− epitaxial layer 202 to form p− base regions 203. On n− epitaxial layer 202 thus including p− base regions 203, an n− channel layer 205 is epitaxially grown. Thereafter, ion implantation is performed using an LTO film 221 as a mask to form n+ source regions 204. On this occasion, each of n+ source regions 204 is formed to have a region 204a and a region 204b containing an n type impurity at a concentration lower than that of region 204a. In thermal oxidation for forming a gate oxide film 207 (see FIG. 14) in a subsequent step, region 204b will be oxidized whereas region 204a will not be oxidized and will remain as n+ source region 204. Thereafter, activation heating treatment is performed. Next, as shown in FIG. 14, LTO film 221 is removed, thus forming gate oxide film 207 on the surface of the epitaxial layer. Then, on gate oxide film 207, a gate electrode 208 is formed. Further, an insulating film 209 is formed, and a source electrode 210 and a drain electrode 211 are formed.