Peripheral Component Interconnect (PCI) is a parallel bus architecture that has become the predominant local bus for various computing platforms. The implementation of the PCI technology has come close to its practical limits of performance and is not easily scaled up in frequency or down in voltage. PCI Express is another architecture utilizing point-to-point transmission, having a higher speed, and which is scalable for future improvements.
A PCI Express link is built around dedicated unidirectional couples of serial (1-bit), point-to-point connections known as “lanes.” PCI Express is a layered protocol, consisting of a Transaction Layer, a Data Link Layer, and a Physical Layer. In addition to data packets transferred from one device to another via the PCI Express, various other packets are also transferred, such as configuration packets and flow control packets. Thus, some bandwidth allocated for data packet transfer is expended in transferring management configuration cycles and flow control update packets, which in some instances results in traffic blockages in critical data paths.
Additionally, bandwidth allocated for data transfer for a particular device coupled to the PCI Express link may go unused, further contributing to system inefficiency.