1. Field of the Invention
This invention relates to a solder structure in the form of a column which structure provides enhanced fatigue life properties when reflowed and used to bond substrates and, more particularly, to a solder structure having a metal portion at one end thereof which forms an alloy with solder and which structure is used to make C-4 connections in electronic components such as joining a chip to a substrate.
2. Description of Related Art
The use of solder to join materials such as components of an electronic structure is well known in the art. In the electronics area there are a myriad of electronic components which require connection to other electronic components or to other levels of packaging. Examples include mounting of integrated circuit chips to a metallized substrate, multilayer ceramic substrate, laminate organic substrate, glass ceramic substrate, card (direct-chip-attach, DCA), and any substrate made of composite materials meeting thermal and mechanical properties.
For the sake of clarity and consistency in describing the present invention the specification will be directed to electronic components made using Controlled Collapse Chip Connection (C-4) technology and, in particular, to the use of C-4 solder columns as compared with spherical solder bumps.
C-4 technology is an interconnection technology developed by IBM as an alternative to wire bonding. Broadly stated, in one application, one or more integrated circuit chips are mounted above a single or multilayer substrate and pads on the chip are electrically connected to corresponding pads on the substrate by a plurality of electrical connections known as solder bumps or solder columns. An example of a C-4 configuration is a square grid array which is 11 C-4 pads long by 11 C-4 pads wide on 10 mil centers. A five mil solder bump is located at every intersection in the grid except one which is typically displaced for orientation purposes. A popular chip is a circuit "computer-on-a-chip" which has 762 C-4 solder bumps in a 29.times.29 area array.
The C-4 technology has also extended to other applications and is now used on thin-film resistor and composite chips in hybrid modular applications. Solder pads for this application are very large-about 25 mil in diameter. At the other extreme, C-4s have been used for precision registration and alignment in the joining of a GaAs wave guide. The most dense area array reported has been a 128.times.128 array of 1 mil bumps on about 2 mil centers resulting in 16,000 pads.
The C-4 technology typically utilizes spherical solder bumps deposited on solder wettable metal terminals on the chip and a matching foot print of solder wettable terminals on the substrate to be joined thereto. The upside-down chip (flip chip) is aligned to the substrate, and all joints are made simultaneously by reflowing the solder bumps. The flow on the chip is limited by a ball limiting metallurgy (BLM) pad which is generally a circular pad of evaporated, thin-film metal such as chromium, copper and gold that provides the sealing of the via as well as the solderable, conductive base for the solder bump. A very thick deposit of evaporated solder acts as the primary conduction and joining material between chip and substrate.
Melting point has been a consideration in the choice of solder alloys for C-4s. Lead solders, especially 95 Pb/5 Sn have been widely used with alumina ceramic substrates because of their high melting point of approximately 315.degree. C. Their use for the chip connection allows other lower-melting point solders to be used at the module-to-card or card-to-board packaging level without remelting the chip's C-4s. Intermediate melting point solders such as eutectic 63 Sn/37 Pb (melting point 183.degree. C.) and a 50 Pb/50In melting point of approximately 220.degree. C. have been used. In "Microelectronics Packaging Handbook", edited by R. R. Tummala and Rymaszewski, 1989, van Nostrand Reinhold, pages 361-391, C-4 chip to package interconnections as well as typical solders used in C-4 technology are discussed and this reference is hereby incorporated by reference.
Once the solder bumps or columns are deposited on the BLM, the joining of the BLM of the chips to the substrate using C-4 technology is relatively straight forward. Flux, either water-white rosin for high-lead solders with watersoluble flux for low lead and other low-melting solders, is normally placed on the substrate to be joined as a temporary adhesive to hold the chips in place. Such an assembly is then subjected to a reflow thermal cycle wherein the pads on the chip and the pads on the substrate self-align due to the high-surface-tension forces of the solder to complete the assembly. Once the chip-joining operation is complete, cleaning of flux residues is accomplished with such solvents as chlorinated solvents or xylene. The assembly is then electrically tested.
New technologies are continuously increasing the number of C-4 interconnections per device, and/or the size of the chip, both of which affect the stresses on the solder interconnections. As chips become more and more dense, higher input/output counts will drive area arrays of terminals to as many as 155,000 pads on a 20 mm chip. This will result in the number of pads increasing while the pad sizes and spacings decrease. The new technologies will induce large strains to the solder joint and new solders and solder structures are needed to meet the fatigue requirements of these types interconnections.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a solder and solder structure which provides enhanced fatigue life properties when used to bond substrates particularly electronic substrates such as a chip to a multilayer ceramic substrate.
It is another object of the present invention to provide a method for making C-4 solder interconnections, using the specially defined column solder structure of the invention.
A further object of the invention is to provide C-4 containing electronic structures made using the solder column structure and method of the invention.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.