The present invention relates to stacked multiple die semiconductor assemblies, printed circuit board assemblies, computer systems, and their methods of assembly. More particularly, the present invention relates to an improved scheme for increasing semiconductor die density.
Conventional Chip On Board (COB) techniques used to attach semiconductor dies to a printed circuit board include flip chip attachment, wirebonding, and tape automated bonding (xe2x80x9cTABxe2x80x9d). Flip chip attachment consists of attaching a flip chip to a printed circuit board or other substrate. A flip chip is a semiconductor chip that has a pattern or array of electrical terminations or bond pads spaced around an active surface of the flip chip for face down mounting of the flip chip to a substrate. Generally, the flip chip has an active surface having one of the following electrical connectors: Ball Grid Array (xe2x80x9cBGAxe2x80x9d)xe2x80x94wherein an array of minute solder balls is disposed on the surface of a flip chip that attaches to the substrate (xe2x80x9cthe attachment surfacexe2x80x9d); Slightly Larger than Integrated Circuit Carrier (xe2x80x9cSLICCxe2x80x9d)xe2x80x94which is similar to a BGA, but having a smaller solder ball pitch and diameter than a BGA; or a Pin Grid Array (xe2x80x9cPGAxe2x80x9d)xe2x80x94wherein an array of small pins extends substantially perpendicularly from the attachment surface of a flip chip. The pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto.
With the BGA or SLICC, the solder or other conductive ball arrangement on the flip chip must be a mirror-image of the connecting bond pads on the printed circuit board such that precise connection is made. The flip chip is bonded to the printed circuit board by refluxing the solder balls. The solder balls may also be replaced with a conductive polymer. With the PGA, the pin arrangement of the flip chip must be a mirror-image of the pin recesses on the printed circuit board. After insertion, the flip chip is generally bonded by soldering the pins into place. An under-fill encapsulant is generally disposed between the flip chip and the printed circuit board for environmental protection and to enhance the attachment of the flip chip to the printed circuit board. A variation of the pin-in-recess PGA is a J-lead PGA, wherein the loops of the J""s are soldered to pads on the surface of the circuit board.
Wirebonding and TAB attachment generally begin with attaching a semiconductor chip to the surface of a printed circuit board with an appropriate adhesive, such as an epoxy. In wirebonding, bond wires are attached, one at a time, to each bond pad on the semiconductor chip and extend to a corresponding lead or trace end on the printed circuit board. The bond wires are generally attached through one of three industry-standard wirebonding techniques: ultrasonic bondingxe2x80x94using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bondingxe2x80x94using a combination of pressure and elevated temperature to form a weld; and thermosonic bonding-using a combination of pressure, elevated temperature, and ultrasonic vibration bursts. The semiconductor chip may be oriented either face up or face down (with its active surface and bond pads either up or down with respect to the circuit board) for wire bonding, although face up orientation is more common. With TAB, ends of metal leads carried on an insulating tape such as a polyamide are respectively attached to the bond pads on the semiconductor chip and to the lead or trace ends on the printed circuit board. An encapsulant is generally used to cover the bond wires and metal tape leads to prevent contamination.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As new generations of integrated circuit products are released, the number of devices used to fabricate them tends to decrease due to advances in technology even though the functionality of these products increases. For example, on the average, there is approximately a 10 percent decrease in components for every product generation over the previous generation with equivalent functionality.
In integrated circuit packaging, in addition to component reduction, surface mount technology has demonstrated an increase in semiconductor chip density on a single substrate or board despite the reduction of the number of components. This results in more compact designs and form factors and a significant increase in integrated circuit density. However, greater integrated circuit density is primarily limited by the space or xe2x80x9creal estatexe2x80x9d available for mounting dies on a substrate, such as a printed circuit board.
U.S. Pat. Nos. 5,994,166 and 6,051,878, the disclosures of which are incorporated herein by reference, represent a number of schemes for increasing semiconductor chip density on a single substrate or board. Despite the advantages of the most recent developments in semiconductor fabrication there is a continuing need for improved schemes for increasing semiconductor die density in printed circuit board assemblies.
This need is met by the present invention wherein an improved die stacking scheme is provided. In accordance with one embodiment of the present invention, a multiple die semiconductor assembly is provided comprising a substrate and first and second semiconductor dies. The first semiconductor die includes a pair of major surfaces. One of the pair of major surfaces of the first die defines a first active surface. The other of the major surfaces of the first die defines a first stacking surface. The first active surface includes at least one conductive bond pad. The first stacking surface is secured to the substrate. The second semiconductor die includes a pair of major surfaces. One of the pair of major surfaces of the second die defines a second active surface. The other of the major surfaces of the second die defines a second stacking surface. The second active surface includes at least one conductive bon pad. The first semiconductor die is electrically coupled to the second semiconductor die by at least one topographic contact extending from a conductive bond pad on the second active surface to a conductive bond pad on the first active surface.
In accordance with another embodiment of the present invention, a multiple die semiconductor assembly is provided comprising a substrate and first and second semiconductor dies. The substrate includes a first surface and conductive contacts included on the first surface. The first semiconductor die includes a pair of major surfaces. One of the pair of major surfaces of the first die defines a first active surface. The other of the major surfaces of the first die defines a first stacking surface. The first active surface includes at least one conductive bond pad. The first stacking surface is secured to the first surface of the substrate. The second semiconductor die includes a pair of major surfaces. One of the pair of major surfaces of the second die defines a second active surface. The other of the major surfaces of the second die defines a second stacking surface. The second active surface includes at least one conductive bond pad. The first semiconductor die is electrically coupled to the second semiconductor die by at least one topographic contact extending from a conductive bond pad on the second active surface to a conductive bond pad on the first active surface. At least one conductive line extends from a bond pad on the first active surface to a conductive contact on the first surface of the substrate.
In accordance with yet another embodiment of the present invention, a multiple die semiconductor assembly is provided comprising a substrate and first and second semiconductor dies. The first semiconductor die includes a pair of major surfaces. One of the pair of major surfaces of the first die defines a first active surface. The other of the major surfaces of the first die defines a first stacking surface. The first active surface includes at least one conductive bond pad. The first active surface is electrically coupled to the substrate by at least one topographic contact extending from a conductive bond pad on the first active surface to a conductive contact on the substrate. The second semiconductor die includes a pair of major surfaces. One of the pair of major surfaces of the second die defines a second active surface. The other of the major surfaces of the second die defines a second stacking surface. The second active surface includes at least one conductive bond pad. The first stacking surface is secured to the second stacking surface.
In accordance with yet another embodiment of the present invention, a multiple die semiconductor assembly is provided comprising a substrate and first and second semiconductor dies. The substrate includes a first surface and conductive contacts included on the first surface. The first semiconductor die includes a pair of major surfaces. One of the pair of major surfaces of the first die defines a first active surface. The other of the major surfaces of the first die defines a first stacking surface. The first active surface includes at least one conductive bond pad. The first active surface is electrically coupled to the substrate by at least one topographic contact extending from a conductive bond pad on the first active surface to a conductive contact on the first surface of the substrate. The second semiconductor die includes a pair of major surfaces. One of the pair of major surfaces of the second die defines a second active surface. The other of the major surfaces of the second die defines a second stacking surface. The second active surface includes at least one conductive bond pad. The first stacking surface is secured to the second stacking surface. At least one conductive line extends from a bond pad on the second active surface to a conductive contact on the first surface of the substrate.
In accordance with yet another embodiment of the present invention, a multiple die semiconductor assembly is provided comprising a substrate, first and second semiconductor dies, and at least one decoupling capacitor. The first semiconductor die defines a first active surface. The first active surface includes at least one conductive bond pad. The second semiconductor die defines a second active surface, the second active surface includes at least one conductive bond pad. The first semiconductor die is interposed between the substrate and the second semiconductor die such that a surface of the second semiconductor die defines an uppermost die surface of the multiple die semiconductor assembly and such that a surface of the first semiconductor die defines a lowermost die surface of the multiple die semiconductor assembly. The decoupling capacitor is secured to the uppermost die surface and is conductively coupled to at least one of the first and second semiconductor dies.
In accordance with yet another embodiment of the present invention, a multiple die semiconductor assembly is provided comprising a substrate, first and second semiconductor dies, and at least one decoupling capacitor. The first semiconductor die is positioned adjacent the substrate relative to the cross section. The second semiconductor die is positioned adjacent the first semiconductor die relative to the cross section. The first semiconductor die is interposed between the substrate and the second semiconductor die relative to the cross section. The decoupling capacitor is positioned adjacent the second semiconductor die relative to the cross section and is secured to the second semiconductor die. The second semiconductor die is interposed between the decoupling capacitor and the first semiconductor die relative to the cross section.
In accordance with yet another embodiment of the present invention, a printed circuit board assembly is provided comprising a substrate, first and second semiconductor dies, and a printed circuit board. The first semiconductor die includes a pair of major surfaces. One of the pair of major surfaces of the first die defines a first active surface. The other of the major surfaces of the first die defines a first stacking surface. The first active surface includes at least one conductive bond pad. The first stacking surface is secured to the substrate. The second semiconductor die includes a pair of major surfaces. One of the pair of major surfaces of the second die defines a second active surface. The other of the major surfaces of the second die defines a second stacking surface. The second active surface includes at least one conductive bond pad. The first semiconductor die is electrically coupled to the second semiconductor die by at least one topographic contact extending from a conductive bond pad on the second active surface to a conductive bond pad on the first active surface. The printed circuit board is positioned such that a first surface of the printed circuit board faces the substrate. A plurality of topographic contacts extend from the substrate to the first surface of the printed circuit board.
In accordance with yet another embodiment of the present invention, a printed circuit board assembly is provided comprising a substrate, first and second semiconductor dies, and a printed circuit board. The first semiconductor die includes a pair of major surfaces. One of the pair of major surfaces of the first die defines a first active surface. The other of the major surfaces of the first die defines a first stacking surface. The first active surface includes at least one conductive bond pad. The first active surface is electrically coupled to the substrate by at least one topographic contact extending from a conductive bond pad on the first active surface to a conductive contact on the substrate. The second semiconductor die includes a pair of major surfaces. One of the pair of major surfaces of the second die defines a second active surface. The other of the major surfaces of the second die defines a second stacking surface. The second active surface includes at least one conductive bond pad. The first stacking surface is secured to the second stacking surface. The printed circuit board is positioned such that a first surface of the printed circuit board faces the substrate. A plurality of topographic contacts extend from the substrate to the first surface of the printed circuit board.
In accordance with yet another embodiment of the present invention, a computer system is provided comprising a programmable controller and at least one memory unit. The memory unit comprises a printed circuit board assembly according to the present invention.
In accordance with yet another embodiment of the present invention, a method of stacking a plurality of semiconductor die is provided. The method comprises the steps of: providing a substrate; providing a first semiconductor die including a pair of major surfaces, wherein one of the pair of major surfaces of the first die defines a first active surface, the other of the major surfaces of the first die defines a first stacking surface, and the first active surface includes at least one conductive bond pad; securing the first stacking surface to the substrate; providing a second semiconductor die including a pair of major surfaces, wherein one of the pair of major surfaces of the second die defines a second active surface, the other of the major surfaces of the second die defines a second stacking surface, and the second active surface includes at least one conductive bond pad; electrically coupling the first semiconductor die to the second semiconductor die with at least one topographic contact extending from a conductive bond pad on the second active surface to a conductive bond pad on the first active surface.
In accordance with yet another embodiment of the present invention, a method of stacking a plurality of semiconductor die is provided. The method comprises the steps of: providing a substrate; providing a first semiconductor die including a pair of major surfaces, wherein one of the pair of major surfaces of the first die defines a first active surface, the other of the major surfaces of the first die defines a first stacking surface, and the first active surface includes at least one conductive bond pad; electrically coupling the first active surface to the substrate with at least one topographic contact extending from a conductive bond pad on the first active surface to a conductive contact on the substrate; providing a second semiconductor die including a pair of major surfaces, wherein one of the pair of major surfaces of the second die defines a second active surface, the other of the major surfaces of the second die defines a second stacking surface, and the second active surface includes at least one conductive bond pad; and securing the first stacking surface to the second stacking surface.
In accordance with yet another embodiment of the present invention, a method of stacking a plurality of semiconductor die is provided. The method comprises the steps of: providing a substrate; providing a first semiconductor die defining a first active surface, the first active surface including at least one conductive bond pad; providing a second semiconductor die defining a second active surface, the second active surface including at least one conductive bond pad; interposing the first semiconductor die between the substrate and the second semiconductor die such that a surface of the second semiconductor die defines an uppermost die surface of the multiple die semiconductor assembly and such that a surface of the first semiconductor die defines a lowermost die surface of the multiple die semiconductor assembly; securing at least one decoupling capacitor to the uppermost die surface; and conductively coupling the decoupling capacitor to at least one of the first and second semiconductor dies.
In accordance with yet another embodiment of the present invention, a method of stacking a plurality of semiconductor die along a cross section is provided. The method comprises the steps of: providing a substrate; positioning a first semiconductor die adjacent the substrate relative to the cross section; positioning a second semiconductor die adjacent the first semiconductor die relative to the cross section; interposing the first semiconductor die between the substrate and the second semiconductor die relative to the cross section; positioning at least one decoupling capacitor adjacent the second semiconductor die relative to the cross section; securing the decoupling capacitor to the second semiconductor die; and interposing the second semiconductor die is between the decoupling capacitor and the first semiconductor die relative to the cross section.
In accordance with yet another embodiment of the present invention, a method of assembling a printed circuit board is provided. The method comprises the steps of: providing a substrate including first and second surfaces and conductive contacts included on the first surface; providing a first semiconductor die including a pair of major surfaces, wherein one of the pair of major surfaces of the first die defines a first active surface, the other of the major surfaces of the first die defines a first stacking surface, the first active surface includes a plurality of conductive bond pads, and the first stacking surface is devoid of conductive bond pads; securing the first stacking surface to the first surface of the substrate between the conductive contacts included on the first surface of the substrate; providing a second semiconductor die including a pair of major surfaces, wherein one of the pair of major surfaces of the second die defines a second active surface, the other of the major surfaces of the second die defines a second stacking surface, and the second active surface includes a plurality of conductive bond pads; electrically coupling the first semiconductor die to the second semiconductor die with a plurality of topographic contacts extending from respective conductive bond pads on the second active surface to a corresponding conductive bond pad on the first active surface; securing a single decoupling capacitor to the second stacking surface; providing a pair of conductive lines, each of the conductive lines connecting a terminal of the decoupling capacitor, a bond pad on the first active surface, and a conductive contact on the first surface of the substrate; electrically coupling the bond pad on the first active surface to the second semiconductor die via one of the plurality of topographic contacts extending from respective conductive bond pads on the second active surface to a corresponding conductive bond pad on the first active surface; arranging the pair of conductive lines such that the decoupling capacitor is connected across Vss and Vcc pins of the first and second semiconductor dies; positioning a printed circuit board such that a first surface of the printed circuit board faces the substrate; and providing a plurality of topographic contacts extending from the second surface of the substrate to the first surface of the printed circuit board.
In accordance with yet another embodiment of the present invention, a method of assembling a printed circuit board is provided. The method comprises the steps of: providing a substrate including a first surface and conductive contacts included on the first surface; providing a first semiconductor die including a pair of major surfaces, wherein one of the pair of major surfaces of the first die defines a first active surface, the other of the major surfaces of the first die defines a first stacking surface, and the first active surface includes a plurality of conductive bond pads; electrically coupling the first active surface to the substrate with a plurality of topographic contacts extending from respective conductive bond pads on the first active surface to corresponding conductive contacts on the first surface of the substrate; providing a second semiconductor die including a pair of major surfaces, wherein one of the pair of major surfaces of the second die defines a second active surface, the other of the major surfaces of the second die defines a second stacking surface, the second active surface includes a plurality of conductive bond pads, and the first stacking surface is devoid of conductive bond pads; securing the first stacking surface to the second stacking surface; securing a single decoupling capacitor to the second stacking surface; providing a pair of conductive lines, each of the conductive lines connecting a terminal of the decoupling capacitor, a bond pad on the second active surface, and a conductive contact on the first surface of the substrate; electrically coupling the conductive contact on the first surface of the substrate to the first semiconductor die via one of the plurality of topographic contacts extending from respective conductive bond pads on the first active surface to corresponding conductive contacts on the first surface of the substrate; arranging the pair of conductive lines such that the decoupling capacitor is connected across Vss and Vcc pins of the first and second semiconductor dies; positioning a printed circuit board such that a first surface of the printed circuit board faces the substrate; and providing a plurality of topographic contacts extending from the substrate to the first surface of the printed circuit board.
Accordingly, it is an object of the present invention to provide an improved die stacking scheme. Other objects of the present invention will be apparent in light of the description of the invention embodied herein.