As digital electronic processing systems trend toward higher operating frequencies and smaller device geometries, power management has become increasingly important to prevent thermal overload while maintaining system performance and prolonging battery life in portable systems.
The two principal sources of power dissipation in digital logic circuits are static power dissipation and dynamic power dissipation. Static power dissipation is dependent on temperature, device technology and processing variables, and is composed primarily of leakage currents. Dynamic power dissipation is the predominant loss factor in digital circuitry and is proportional to the operating clock frequency, the square of the operating voltage and the capacitive load. Capacitive load is highly dependent on device technology and processing variables, so most approaches to dynamic power management focus on frequency and voltage control.
One conventional approach to power management halts the processing system to adjust core clock frequencies and voltages, during which time the processor does not execute operating system code or application code, and then restarts the system after the new frequencies and voltages have stabilized. Such an approach is described in U.S. Pat. No. 6,754,837, as illustrated in FIG. 1. FIG. 1 illustrates a processor or processing system 1 contains a programmable voltage ID (VID) register 3, a clock frequency control register 4 and a count register 5. When the processor determines that a change in the voltage and/or frequency is desired, the desired voltage and frequency control information is loaded into the VID register and the clock frequency control register, respectively. Access to those registers triggers a stop request 9 to the CPU core logic 11. In response to the stop request, the CPU completes the current instruction and issues a stop grant signal 13 to indicate to a power controller 7 that processing has stopped. The stop grant state is maintained, for a time determined by a value in the count register, while the voltage and/or frequency are changed and stabilized. In addition to the processing time lost during the stop grant state, this approach may also result in large transient power surges when the processor restarts.
Another conventional approach to power management, described in U.S. Pat. No. 6,788,156, changes the clock frequency of a processor while the processor is operating, but requires the frequency changes to be made in small increments to avoid processing errors that large frequency steps would cause. As a result, this approach may require a significant time period to achieve a desired operating frequency.
Yet another conventional approach to power management, described in U.S. Pat. No. 6,778,418, employs a fixed relationship between voltage and frequency, either through a lookup table or by use of a frequency to voltage converter. In this approach, a frequency increase is always preceded by a voltage increase and a frequency decrease always precedes a voltage decrease. In addition, a frequency increase is delayed while the voltage is ramped up to a corresponding voltage. The new frequency and voltage are not scaled independently, and the new operating point may not be optimum with respect to an application's processing demand.