1. Field of the Invention
The present invention relates to information handling systems and more particularly to methods for testing address line failures in a storage system of an information handling system.
2. Prior Art
U.S. Pat. No. 4,369,511 describes a semi-conductor memory test system which reads a memory under test at an address generated by a pattern generator and compares data read from the address with expected data. A block mask memory is read by a portion of the address and the comparing operation of the comparator is inhibited by block mask data read from the block mask memory.
The method for memory testing according to the patent is significantly different from the present invention in that the patent requires a comparison of data read from a memory with data generated and fed through a test memory 22 and compared in comparator 19.
In the method according to the present invention, data is stored in address locations being one bit different and the data is read from the two locations and compared. There is no second memory used to generate an expected storage pattern as in the prior art.
U.S. Pat. No 4,404,519 provides method and apparatus for testing data stored in a memory array embedded in a large scale integrated circuit. The method and apparatus of the patent do not describe or suggest the method for testing address lines in accordance with the present invention.
U.S. Pat. No. 4,429,389 teaches a test pattern address generator which generates specialized address patterns in which an address generator is complimented and then incremented on a series of increment-compliment actions so that all combinations of row and column drivers in the integrated circuit memory under test are exercised.
The patent does not contemplate the method of testing address lines in accordance with the present invention where each address line bit is separately tested by a two-pass test in which divergent data is stored into the address under test and the address into which data would be stored if there was an address line failure for the address bit under test.
U.S. Pat. No. 4,559,626 teaches a test apparatus for testing memories which includes an internal memory into which data patterns are stored for comparison with data patterns stored in a memory under test. The patterns are then read from the internal memory of the tester and the memory under test and compared.
The patent does not contemplate the method of testing address lines in accordance with the present invention where each address line bit is separately tested by a two-pass test in which divergent data is stored into the address under test and the address into which data would be stored if there was an address line failure for the address bit under test.