1. Field of the Invention
The present invention relates to a Low Drop-Out (LDO) voltage regulator with efficient frequency compensation, and more particularly, to a LDO voltage regulator that adjusts output capacitance to fix frequency of a pole according to current variation of a back-end load.
2. Description of the Prior Art
A linear voltage regulator has ability to provide a stable output voltage. A Low Drop-Out (LDO) linear voltage regulator is further able to generate an output voltage very close to an input voltage, so as to save power consumption of power transistors and increase battery life. Thus, the LDO voltage regulator is widely used in various portable electronic products, such as music players, digital cameras, mobile phones, notebook computers, and so on.
Please refer to FIG. 1, which shows a schematic diagram of a conventional LDO voltage regulator 10. The LDO voltage regulator 10 includes an error amplifier 110, a transmission element 120 and an output capacitor Cout, and mainly operates by utilizing a voltage divider 130 to generate a feedback voltage VFB for the error amplifier 110 to control the transmission element 120 according to difference between the feedback voltage VFB and a reference voltage VREF, so as to generate stable output voltages. Additionally, the output capacitor Cout is utilized for providing current temporarily required by a back-end load to improve transient response of the output voltage when load current Iload of the back-end load is changed suddenly.
Generally, loop stability is an important issue in the design of the LDO voltage regulator. In a traditional circuit structure, the load current and the output capacitor are two major factors affecting the loop stability. By establishing a small signal circuit model of the above LDO voltage regulator, it can be found that the circuit loop mainly has two poles, which relate closely to the design of the loop stability. A dominant pole is generated by a parasitic capacitor formed between the error amplifier and the transmission element and output impedance of the error amplifier, and can be expressed as:
            fp      ⁢                          ⁢      1        ≈          1              2        ⁢        π        ×        Roe        ×        Cpar              ,in which Roe and Cpar represent the output impedance of the error amplifier and the parasitic capacitor between the error amplifier and the transmission element, respectively. A second pole is generated by the output capacitor and output impedance of the LDO voltage regulator, and can be expressed as:
            fp      ⁢                          ⁢      2        ≈          1              2        ⁢        π        ×        Ro        ×        Cout              ≈                  λ        ×                  I          load                            2        ⁢        π        ×        Cout              ,in which Ro and λ represent the output impedance of the transmission element 120 and a channel length modulation coefficient, respectively.
As can be seen in the above, when the load current Iload varies, frequency of the second pole will drift while the other pole remains unchanged. However, since the frequency drift may significantly change frequency response of the LDO voltage regulator, loop instability may occur due to insufficient phase margin in some situations.
In short, the LDO voltage regulator may suffer problems of loop instability when the load current varies.