The invention relates to a process for the selective metallization of 3D structures, in particular for the selected gold-plating of 3D contact structures on wafers, such as contact bumps, which are electrically connected to a bond pad on the wafer via a three-dimensional, mechanically flexible structure in the form of a redistribution layer, for subsequent electrical connection to a carrier element, e.g., a printed circuit board.
The increasing integration of semiconductor components and the constantly rising number of electrical connections which are required between semiconductor chips and carrier elements, and in particular the need to miniaturize the electronic modules which are to be produced has led to the use of direct contact-making with the semiconductor chips on the carrier element (flip-chip bonding). This has considerably simplified assembly technology, since metallic intermediate carriers and the production of wire bridging links for making electrical contact can be dispensed with.
However, in order to allow direct contact to be made with semiconductor chips on carrier elements, such as a PCB (printed circuit board), it is necessary to produce 3D structures, known as solder bumps, on the semiconductor chip, these structures at their highest point in each case having a gold-plated contact surface, which is connected via a metal conductor track to a bonding pad of the semiconductor chip.
These solder bumps may be three-dimensional, mechanically flexible structures, resulting in a certain degree of compensation for mechanical loads on the finished assembly, for example caused by different coefficients of thermal expansion of the individual components or during their handling.
The metal conductor tracks comprise, for example, a Cu conductor track and a layer of Ni above it, which is used to protect the layer of Cu from corrosion. Beneath the metal conductor tracks (redistribution layer) and the solder bumps there is a dielectric, so that it is ensured that there is only an electrical connection between the gold-plated contact surface on the solder bump and the associated bond pad. To achieve solderability, the nickel layer has to be coated with gold at the corresponding locations, i.e., the tips of the 3D structures.
In this context, it must at all costs be ensured that the gold coating takes place only at the tips of the 3D structures or that the redistribution layer which leads down from the 3D structures is absolutely free of gold, in order to ensure a solder stop during soldering of the semiconductor chip on a carrier element. Otherwise, the solder material would flow uncontrolled over the redistribution layer and adversely affect mechanical and electrical properties. In particular, the reliability of the finished electronic module would be adversely affected.
In the methods which are currently in practical use, the need to pattern the layer of gold is realized by a generally known lithographic process. This is effected by the gold being deposited on the entire redistribution layer immediately after the Cu/Ni of the distribution layer has been deposited. Then, the gold layer is covered by a lithography mask, so that selective etching can take place and ultimately a layer of gold remains only directly at the tip of the 3D structure.
According to the prior art, the production of the layer of gold and its patterning, in simplified form, involves the following process steps:                Cu/Ni plating by layer electrodeposition        Au plating of the entire redistribution layer by layer electrodeposition        electrophoretic coating of the structure with photoresist        exposure of the solder stop mask        developing of the solder stop mask        gold strip, i.e., removal of the uncovered gold layer using a cyanide-based solution        Continuation with common process flow        
This process sequence requires considerable outlay and also involves the possibility of defects on account of the large number of process steps.
The invention is based on the object of providing a process for the selective metallization of 3D structures, in particular for the selective gold-plating of 3D contact structures on semiconductor chips, using a simplified process sequence. Furthermore, it is an object to provide an arrangement for carrying out the method which is simple to realize.