Frequency dividers are one of the most essential building blocks in phase-locked loops (PLLs) and frequency synthesizers, which are required in all data and telecommunication communication systems. As illustrated in FIG. 1, to lock the phase or frequency of the PLLs or synthesizers, frequency dividers are needed to divide down the high frequency output from VCO and feed-back the signal to a PFD (phase/frequency detector). This is because the PFD can usually only accept frequencies which are much lower than the frequency output by the VCO in most applications.
On the other hand, quadrature-phase clock signals are widely required in many applications, for example direct-conversion wireless systems for in-phase and quadrature-phase (IQ) mixing. In particular, in frequency synthesizers for UWB transceivers, many quadrature signals are needed to generate desired LO signals by single-sideband (SSB) mixing. In addition, SSB (single-sideband) mixers require accurate quadrature inputs so as to perform output additions or subtractions with high sideband or image rejection.
A common and reliable solution is to use divide-by-2 circuitries to generate desired IQ signals with quadrature phases, as shown in FIG. 2. The divide-by-2 divider takes a simple signal, halves the frequency and converts it into quadrature outputs (two outputs, foutI—the ‘in-phase signal’ and foutQ ‘the quadrature-phase signal’ which is 90 degrees advanced or delayed in phase compared to the ‘in-phase signal’). The frequency of the divider's outputs is half of that of the input signals.
However, the output phase matching of the existing quadrature signal generators (quadrature VCOs, or divide-by-2 dividers) is still limited in practical applications. One of the critical contributions to the output IQ phase mismatch of a quadrature signal generator is the mismatch in its output loading, which typically is dominated by the input capacitance of dividers used to achieve lower frequency. In all the existing dividers, only differential input signals are used to achieve divided-by-2 operation. Therefore, an identical dummy divider is normally implemented to balance the IQ loading of the previous quadrature signal generator, as explained in FIG. 3. Nevertheless, there would still exist significant capacitive loading mismatch if the dummy divider were disabled to save power consumption. Alternatively, the dummy divider could be turned on to improve the IQ loading matching, but that would double the power consumption. In either case, the chip area needs to be doubled due to the dummy divider. Another problem with the configuration shown in FIG. 3 is that there is no deterministic relationship between the IQ phase sequence of the input signals and the IQ phase sequence of the output quadrature signals. The relationship is random and dependent on the device parameters in a non-predictable manner.