The present invention generally relates to semiconductor integrated circuits, and more particularly, to the structure and formation of an interconnect level overlying embedded magnetoresistive random access memory (MRAM) devices. The structure and formation of the interconnect level includes providing pre-patterned etch stops for trenches so as to control trench depth, which can be done in both non-MRAM and embedded MRAM areas.
Embedded magnetic random access memory (MRAM) can be used to replace embedded flash memory or embedded dynamic random access memory (DRAM) for its unique features of writing/reading speed, writing endurance, and low power consumption. In order to make embedded MRAM production-worthy, one must not only overcome the technical challenges of making the magnetic junction array to meet the embedded memory product design requirements including read/write speed, read/write current limits, reading margin, long-term thermal stability, etc., but also integrate the memory array seamlessly with the peripheral logic circuit which normally occupies the majority of the space.