1. Technical Field
The present invention relates to computer systems and, more specifically, to computer systems and methods thereof for improving the performance of a digital signal processing (DSP) data access operation.
2. Discussion of the Related Art
Recent trends in constructing computer systems are directed to designing the computer system-on-a-chip (SOC). In a SOC design, the computer system's components such as processors, cache memories, peripheral devices, and bus interface units are integrated on a single chip. Thus, the SOC may be regarded as a miniature computer system.
In a typical SOC design, the SOC may have two or more built-in processors such as: (1) a microprocessor (e.g., central processing unit (CPU)) to control the overall operations thereof; and (2) a coprocessor (e.g., digital signal processor (DSP)) to manage data processing operations. The DSP is further used to carry out data multiplication and accumulation, read and write operations for one or more memories, and operations for incrementing address pointer registers.
FIG. 1 illustrates several data processing features of a DSP in a SOC system. As shown in FIG. 1, a SOC 110 includes a CPU core 112, a DSP core 114, and a data cache 116. The CPU core 112 is a functional block or unit constructed by a preliminarily designed circuit pattern. The DSP core 114 accesses an external memory 120 by way of the data cache 116. The external memory 120 includes several storage fields (which are available to the DSP core 114), such as an input data field 122, a temporary data field 124, and an output data field 126. The input data field 122 stores data legible to the DSP core 114 and the output data field 126 stores data provided from the DSP core 114. The temporary data field 124 stores data to be read from/written to the DSP core 114. The data cache 116 is located between the DSP core 114 and the external memory 120, operates with a faster access time, and has a smaller memory capacity than the external memory 120. Data in the temporary, input, and output data fields 124, 122 and 126 is temporarily stored in the data cache 116 and then transferred to the DSP core 114 or the external memory 120.
The data stored in the data cache 116 is frequently accessed for the purpose of increasing a “hit ratio” of the data cache 116. However, as data in the input and output data fields 122 and 126 is stored in the data cache 116, the operational performance of the data cache 116 may degrade because it becomes difficult to access data therein more than once. In addition, because the temporary, input, and output data fields 124, 122, and 126 occupy a single restricted data address space accessible by the DSP core 114, the temporary data field 124 may become smaller if the input and output data fields 122 and 126 become extended due to an increase in the volume of data in each field 122 and 126. Thus, resulting in a degradation of DSP function when the DSP core 114 deals with a large amount of data.
Thus, there is a need for a computer system that does not have functional degradation of a DSP core and cooperates with data caches when there are large amounts of data processed by the DSP core.