As IC technology advances, the complexity of chips increases and higher performance is required. As the industry moves towards a system on a chip model (SoC), uncertainties such as interface requirements and integration of analog blocks must be addressed and resolved. In considering an IC design flow, companies face two major issues: cost and risk.
Cost
Chip design and manufacturing costs for 0.13 μm and 90 nm technologies are estimated to be, respectively in the range of 14 million and 30 million dollars. Costs of this magnitude inhibit many startup companies, and even established companies, from developing products in 0.13 μm and below technologies. Cost components associated with chip design and manufacturing include, without limitation, design resources, acquisition and development of intellectual property (IP), EDA tools, fabrication masks, manufacturing, assembly, validation and verification.
Risk
As chip complexity increases, driven by industry SOC migration, the level of risk increases as well. Set forth below are some of the risk factors associated with development of advanced mixed signal ICs.
Time to Market. Development cycles have increased along with the complexity of the ICs, delaying product introduction cycles by 18 months or more.
Market Acceptance. Market acceptance is a fundamental problem, and can be achieved only by successful chip definition, low cost and short introduction time (time to market).
IP Availability. Complex, mixed signal ICs require many analog and digital IP components. In most cases, all required IPs are not available from the same source. Based on diverse levels of required expertise and depending on project requirements, IP design and development may need to be contracted out. IC manufacturers, fabrication houses and foundries develop multiple flavors of process technologies, i.e., low power, high performance, etc., to address customer requirements, which in turn affects IP availability across all processes.
IP Quality. Price erosion, downward pressure on the cost of IP development, lack of validation and lack of understanding of the overall system have led to serious IP quality issues. Complex analog blocks are sensitive to their surrounding environments, and analog IP is often developed without an understanding of the environment in which it will be incorporated. Advanced technologies and high speed signaling result in narrow design margins and, due to validation time and cost, analog IP providers have no means of validating their IP prior to its usage by end users. It is noteworthy that no analog IP vendor has managed to prove a successful business model.
Design Parameters. In 0.13 μm technologies and below, leakage, noise margin, reduced supply voltage and device mismatches have created a new set of design parameters that further complicate design of high performance analog circuits, causing more emphasis to be placed on silicon verified IP and system validitation.
Validation. Verification and validation of high performance ICs introduces another risk factor due to system environment and complexity. Many IP vendors are now required to validate their IPs in silicon. While this is a partial answer to the problem, validation increases cycle time and does not address solidity of design over process corners which, in effect, translates to yield. Moreover, validation of mixed signal IPs by IP vendors is done in a completely different environment and does not eliminate many risk factors. It is noteworthy that validation of complex IP blocks requires infrastructure, a characterization lab, which is costly and most IP providers do not have.
Yield. Before advanced technologies reach a maturation point, process parameters change and, depending on design time, performance and yield problems may manifest themselves. The overall IC yield is a product of the individual integrated IP yields, design marginalities and manufacturing yields. At present, there are no means for analyzing the yield of acquired IP blocks. Should IP be acquired from multiple sources, there is no guarantee that different IPs will provide a consistent yield across different manufacturing corners, resulting in serious yield loss at the chip level.
Development Cost. Development cost directly affects market acceptance and profit margins, which in turn drives cost structure and system quality.
Analog/Digital Integration. Because IP designers cannot consider all parameters associated with chip level integration, i.e., package, transistor count, supply noise, etc., IC designers must have a good understanding of circuit sensitivity in order to integrate the analog and digital blocks of the chip. The risk factors associated with analog/digital integration at the chip level, and the sensitivity of IP blocks and dependencies at the chip and system levels, are the reasons that many successful IC companies develop analog IPs internally.
Redesign. Redesign lengthens the development cycle, thereby delaying time to market and increasing cost, resulting in lower profit margins, reduced market acceptance and the possibility of missing the potential market window. This emphasizes the importance of first time silicon success without redesign.
Due to these many cost and risk factors, migration to advanced technologies and SOCs has become a barrier that many companies cannot overcome and has created a roadblock in the industry. While several “band aid” solutions have been developed, which are discussed below, there is a clear need for a different and revolutionary design platform that allows easy migration to advanced technologies and SOC design.
Attempted Solutions
The engineering community has attempted to address these problems by forming standards bodies to create standard platforms for specification and validation, and to lower the barriers to adoption and improve overall system quality. Standards are developed across different technologies addressing different bottlenecks. Examples include input and output standards, memory controller standards, parallel and serial link standards such as USB, PCI, Infiniband, IEEE 802.11, and so on.
IC manufacturers have adopted large foundry rule sets and device performance to minimize manufacturing variability in advanced technologies. An example is the adoption of TSMC design rules as a standard by many independent device manufacturers (IDMs) and manufacturing houses. By consolidating processes, barriers to technology portability are reduced and overall energy is focused on bringing up fewer technologies through collaboration. Many IC companies are also developing their designs based on merged rule sets to allow for second sourcing and reduction of possible manufacturing issues and cost.
Other design concepts have also been developed to address the aforementioned risk and cost issues. The proposed solutions, discussed below, while addressing some aspects of the problems, fail to provide a platform that addresses all issues.
Field Programmable Gate Array (FPGA) Design Flow
A field programmable gate array (FPGA) is an IC that can be programmed in the field after manufacture to carry out a specific function. FPGAs are readily available in different configurations and sizes. FPGAs are similar in principle to, but have vastly wider potential application than, programmable read-only memory (PROM) chips.
FPGAs provide a cost effective solution for concept validation and address many aspects of time to market and IP availability. Recent FPGAs provide complex IP blocks in advanced technologies, and reduce risks associated with IP integration and quality. The shortfalls of FPGAs, however, are in the areas of potential usage, performance and production costs. Potential usage is limited to the rigid FPGA structure and its pre-defined IP blocks. Due to the nature of FPGA design, performance is limited and in general only lower frequency ranges can be accommodated. Relative to COT and ASIC flow (discussed below) in the same technologies, FPGAs provide only ⅕ to ⅓ of the performance. High production costs prohibit moderate to high volume designs from having competitive ASPs. Increased cost of development has helped FPGA companies in recent years, such as Xilinx, Altera and so on. More FPGA companies are forming to meet the market demand.
Structural Array (SA) Design Flow
Structural arrays were developed to address the production cost associated with FPGAs and to reduce the performance gap between FPGAs and COT flow. SAs typically have a lower cost for larger production volumes than FPGAs. In some instances, structural arrays can provide larger gate counts, better performance and wider IP selection than FPGAs. Depending on the definition of the SA, companies providing these platforms may experience success. One successful example is LSI's Rapid Chip.
Like FPGAs, however, SAs have a rigid structure that reduces the possibility of their use in productions. Also, there is a longer design time associated with SAs (typically 2–6 months) than there is with FPGAs (typically 1–3 months). In general, SAs do not provide great added advantage relative to FPGAs and, consequently, have not been the subject of widespread acceptance in the industry. This may change as cost of development and performance issues take on even greater weight.
ASIC Design Flow
Design and manufacturing services are provided by major chip manufacturers such as IBM, TI, ST, Phillips, etc. System houses normally provide specifications for Application Specific Integrated Chips (ASICs) to these ASIC providers. ASIC providers deliver finished products according to the specification. ASIC design flow has been gaining momentum recently because it minimizes the risk factors associated with advanced technologies, required knowledge and the availability of IP. The primary issues associated with ASIC flow are the cost of production, which relatively few manufacturers can afford, and the transferability of the finished ASIC to a COT flow (described below). Hence, ASIC design flow is primarily used where cost of production is secondary to minimizing risk, and the design is used in a system that does not require market validation.
Customer Owned Tooling (COT)
COT is the most commonly used design flow for high performance products that have demanding time-to-market requirements. In a typical COT flow, a system house works directly with a pure-play foundry for silicon manufacture. A COT flow generally means that the system house takes its design with all the associated risk all the way through to physical implementation. The resulting GDSII representation of the design is, in theory, ready for silicon fabrication and packaging.
COT flow has been shown to deliver the highest performance and smallest die size. COT data pathways typically have 30–50% faster performance and 25–50% smaller die size relative to an equivalent ASIC. COT design flow, from the IC specification, typically involves the steps of RTL codification, synthesis, static timing analysis and place and route. Of importance, and a major contributing factor to the typical design cycle time of 12–24 months, COT design flow also requires the steps of IP design, acquisition, integration and floor planning.
The greatest advantage provided by COT flow is control: the chip designer is exclusively in control of the process and makes its own decisions about tools, flows, etc. The chip designer has complete control over the timetable and may intervene at any stage in the process without significant loss of time. In an ASIC flow, by contrast, information must be exchanged between different organizations, and the timing and availability of such interventions is at the mercy of the ASIC vendor. Once the initial investment in the COT flow is made, production volume and turnaround times are greatly enhanced. Another significant advantage of COT flow is that all design experience, IP and knowledge is internally owned.
Along with the high rewards of COT flow comes high risk. In COT flows, the chip design and integration of IP are not guaranteed to work properly on the first revision of the silicon, as in ASIC flow. This exposes system houses to a tremendous amount of financial and product introduction risk. In most cases, in order to get the silicon working properly, system houses must iterate the IC design 1–3 times, which adds development costs and delays product introduction. The cost of developing an IC via a COT flow requires a significant and costly infrastructure investment. It takes more tools, personnel and expertise to manage the end-to-end flow. A broad knowledge base is required. Hence, the shortcomings of COT flow include acquiring the knowledge for different aspects of the design, acquiring or developing the required IP, management of risk and cost, and inadequate support for concept and market validation, which results in higher risk and potential need for multiple redesigns.