The present invention generally relates to switched capacitor circuits, and more particularly to a switched capacitor summing circuit that is independent of the mismatch and non-linearity characteristics of the signal capacitors.
The ubiquitous switched capacitor charge transfer circuit has long been used in a wide range of signal processing applications. Switched capacitor circuits are a class of discrete-time systems that are often used in connection with filters, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other analog/mixed signal applications. Conventional switched capacitor circuits are based on creating coefficients of a transfer function by transferring charge from one input capacitor C1 to a second capacitor C2 in the feedback loop of an amplifier via the virtual node of that amplifier so as to create a transfer of C1/C2.
However, finite amplifier DC gain and bandwidth results in incomplete charge transfer from C1 to C2. This, together with inaccuracies in the matching of the capacitors C1 and C2, results in the creation of an inaccurate transfer function. Many applications, such as ADCs, accurate high-Q filters, etc. require very high accuracies in the transfer function, such as accuracies exceeding 0.1%. This kind of accuracy is virtually impossible using conventional circuits in modern day CMOS processes. Often, the values of the capacitors are trimmed at manufacture, or some active calibration routines are executed, switching in and out small value capacitors in order to create an accurate transfer. Such schemes are expensive for high volume manufacture. To reduce capacitor mismatch problems, special capacitors such as double poly or Metal-Insulator-Metal (MiM) capacitors may be used, but the capacitor mismatch problem is not eliminated. Further, such circuits that employ voltage-to-charge and charge-to-voltage translations via the virtual earth node have limited immunity to extraneous noise sources, as the virtual earth node is a well known pick-up point for unwanted noise.
The present invention addresses these and other shortcomings of the prior art, and provides a solution to the problems exhibited by prior art switched capacitor summing circuits.
In various embodiments, the present invention provides a method and apparatus for summing a plurality of input voltage signals and providing optional level shifting, where the resulting transfer function is independent of capacitor mismatch and non-linearity.
In accordance with one embodiment of the invention, a circuit is provided for adding a plurality of input signals. The circuit includes an amplifier having first and second input terminals and an output terminal. A first capacitance is coupled to receive a first input signal and to store a corresponding first voltage in response to a first clock phase, and a second capacitance is coupled to receive a second input signal and to store a corresponding second voltage in response to the first clock phase. In response to a second clock phase, a first switch circuit is coupled to the first capacitance to provide the first voltage to the first input terminal of the amplifier, and to couple the output terminal of the amplifier to the first capacitance via a feedback loop. A second switch circuit is coupled to the second capacitance to provide the second voltage to the second input terminal of the amplifier in response to the second clock phase. In this manner, the amplifier outputs a voltage signal corresponding to a sum of the first and second input signals that is independent of a ratio of the first and second capacitances.
In accordance with another embodiment of the invention, a method is provided for adding input voltage signals. First and second input voltage signals are respectively sampled onto first and second capacitors during a first clock phase. In response to a second clock phase, the first sampled input voltage that is held on the first capacitor is coupled to the negative input terminal of an amplifier, and the second sampled voltage held on the second capacitor is coupled to the positive terminal of the amplifier. A feedback voltage is provided from the amplifier output to the negative amplifier input via the first capacitor during the second clock phase. The first and second input voltage signals are added at the amplifier during the second clock phase to output the sum in response to the sampled input voltage signals and the output feedback, whereby the resulting transfer function is independent of capacitor mismatch and non-linearity.
It will be appreciated that various other embodiments are set forth in the Detailed Description and Claims which follow.