1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus and, more particularly, to a precharge control circuit capable of improving operational stability of a semiconductor memory apparatus.
2. Related Art
A conventional semiconductor memory apparatus receives commands to perform active and precharge operations. An active operation typically includes a read or write operation. A conventional semiconductor memory apparatus outputs data from a memory cell during a read operation and inputs data to the memory cell during a write operation. When one active operation is finished, the data signals still remain on bit lines and data I/O lines, which performed data I/O operations. Thus, for smooth performance of the next active operation, the signal lines should be precharged to a predetermined level. Therefore, the semiconductor memory apparatus includes a precharge control circuit to precharge each signal line during an interval between active operations.
In a conventional semiconductor apparatus, a precharge control circuit automatically generates a precharge signal a predetermined time after an active operation is completed. The time between the performance of the active operation and the generation of the precharge signal is determined by delay elements, which are included in the precharge control circuit.
A conventional precharge control circuit includes delay elements that provide a constant delay regardless of a clock frequency. Thus, if the clock frequency is changed, then the precharge signal may not be generated at the correct time. Further, when the precharge operations for consecutive write operations are performed, a precharge control signal, which should be generated once, may be generated twice due to the signal timing change, which is caused by the change of the clock frequency. If the precharge signals are generated twice, then waiting time for the write operation can be increased significantly.
Since a conventional precharge control circuit cannot properly cope with a change in the clock frequency, particularly when the clock frequency is high, high speed operation can be limited. Also, since a conventional precharge control circuit cannot properly control the precharge timings for consecutive write operations, it can fail to provide operational stability.