1. Field
Embodiments relate to semiconductor devices and methods of fabricating the same and, more particularly, to semiconductor devices including fin field effect transistors (fin-FETs) and methods of fabricating the same.
2. Description of the Related Art
A field effect transistor (FET) may include an active region, a gate electrode crossing over the active region, and source and drain regions formed in the active region at both sides of the gate electrode. The active region under the gate electrode may be used as a channel region of the FET.
Widths of the gate electrode and the active region are being reduced with high integration of the semiconductor device. Since the width of the gate electrode is reduced, a channel length (i.e., a distance between the source region and the drain region) of the channel region is also reduced in the FET. Thus, short channel effects (e.g., a drain induced barrier lowering (DIBL) phenomenon and/or a punch-through phenomenon) may be exhibited in the FET. Additionally, since the width of the active region is reduced, a channel width of the channel region is also reduced. Thus, a narrow width effect (e.g., reduction of a drain current) may be exhibited in the FET.
Recently, fin field effect transistors (fin-FETs) having vertical channel regions have been suggested. In a fin-FET, a gate electrode controls three surfaces of a channel region. Thus, the short channel effects may be effectively improved in the fin-FET. Additionally, since the fin-FET has a vertical channel region, a channel width of the fin-FET may be increased in a limited area. Thus, the narrow width effect may be improved in the fin-FET.