Most integrated circuits include various combinations of memory, combinational logic and sequential logic. As part of the process of making integrated circuits, these various components are tested to ensure that the circuits are operating as intended before the chips are cut from a wafer and packaged for use. As will be understood by those skilled in the art, one way to test the combinational logic is to configure the sequential logic such that the individual sequential logic elements (e.g., flip-flops, latches, and other such memory elements) can be serially coupled to one another to form a number of scan chains that provide inputs to the combinational logic. During testing, a circuit tester loads sequences of logic values (sometimes referred to as “test patterns”) into the scan chains and records the behavior of the combinational logic circuits in response to the sequences. Any discrepancies between what was expected from the integrated circuit after being tested with a particular test pattern and what was actually observed are stored in a failure log. From the failure log, test engineers attempt to diagnose the location and type of defect causing the faulty behavior so that adjustments can be made to the manufacturing process or circuit design.
Because scan chains are used to detect defects in the combinational logic, it is desirable to confirm during testing that the scan chains themselves are operating correctly. If there is an error in the scan chain, it is desirably detected and corrected in the manufacturing process. Embodiments of the disclosed technology are directed to reducing the time is takes to correctly identify faults in one or more scan chains in an integrated circuit.