1. Field of the Invention
This disclosure relates to the manufacturing of semiconductor devices, and more particularly, to a method of manufacturing an FinFET by a damascene process.
2. Description of the Related Art
Metal oxide semiconductor field effect transistors (MOSFET) have been increasingly miniaturized for higher performance and integration. For an integration increase of such a device, new techniques have been constantly proposed. This has brought about a development of devices prominent in their aspects of operation and size.
A technique to enhance an integration of a fin field effect transistor (FinFET) has been proposed. In this FinFET, a body region of a transistor is formed by a vertical structure in such a way that a shape of the transistor is similar to a fish's dorsal fin, thus providing the name of a FinFET.
Such a FinFET uses all upper parts and both side faces of a fin as a channel, in comparison with the existing transistor that uses only one face, thus increasing electrical current by three times than that of the existing transistor. A gate has a structure surrounding a fin, thus increasing a current control capability of a gate for a device, and solving problems such as a short channel effect, etc., caused in the existing transistor.
However, there are several problems if such a fin transistor structure is actually applied to a memory device. In a tri-gate structure in which a gate is formed on an upper part and both side faces of the fin, a driving capability of the gate formed on the upper part of the fin is lowered compared with a gate formed on both side faces. In a pre-doping of a gate electrode, to prevent degradation of device current characteristic caused by gate depletion, etc., when forming an SRAM (Static Random Access Memory), etc., gate heights of upper portions and both side portions of the fin are different, thus a sufficient doping effect cannot be guaranteed. To solve these problems, a double gate fin transistor in which a gate is formed only on both side faces of the fin has been developed. A conventional technique of forming the double gate fin transistor has been disclosed in U.S. Pat. No. 6,642,090.
In forming a gate electrode according to the conventional technique, a fin is formed and then an etching process for a device isolation film surrounding the fin is performed to expose a predetermined portion of a fin type active region. Then, a conductive layer is deposited. The conductive layer is etched in a predetermined pattern to form a gate electrode. Such a process of forming the gate electrode not only increases an absolute etch amount necessary for the formation of the gate electrode, but may also bring about a short between gate electrodes caused by a marginal gate electrode separation. An active region is formed in a fin type, thus an area of source and drain regions is reduced and this influences a contact and silicide formation. This also causes a resistance increase, lowering a current improvement of a fin transistor.