1. Field of the Invention
This invention relates generally to non-volatile dynamic random access memories (DRAM). More particularly, this invention relates to methods and circuits for operating non-volatile DRAM's.
2. Description of Related Art
Non-volatile memories, such as FLASH and Electrically Erasable Programmable Read-Only Memory (EEPROM), are commonly used for providing a more permanent storage. The data state of non-volatile memory cells are retained when the power supply voltage source is removed. In general, the non-volatile memories have smaller silicon foot-print and lower cost per bit than other semi-conductor memory.
The alternative to the non-volatile memories are volatile memories such as Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). The volatile memories generally have a greater accessing speed. A DRAM has faster random access speed than a non-volatile memory, however, it cannot retain data without a periodic refresh process.
These different characteristics between the non-volatile memory and the volatile memory cause each type of memory to have different applications in computer systems. As a result, many types of systems include both non-volatile and volatile memories in the differing applications. Because the non-volatile and volatile memory have these different characteristics, interface and control of non-volatile and volatile are substantially different and resulting in more complicated system design. Therefore, it is desirable to have a memory device that offers fast random access of a volatile memory and the capability of permanently retaining data of a non-volatile memory with substantially the same cost of a DRAM.
A combination of a non-volatile memory and a volatile memory is known in the art as illustrated in “A New Architecture for the NVRAM—An EEPROM Backed-Up Dynamic RAM”, JSSC vol. 23, 1988, pp.86-90, Terada et al. It describes a nonvolatile DRAM with a cell formed by merging a three-transistor EEPROM cell with a one-transistor-one-capacitor DRAM cell. The resultant cell contains 4 transistors and 1 capacitor. Fowler-Nordheim tunneling is used to program and erase the EEPROM portion of the cell.
“An Experimental 256 Mb Non-Volatile DRAM with Cell Plate Boosted Programming Technique”, Ahn et al.—ISSCC, Digest of Technical Papers IEEE International Solid-State Circuits Conference—2004, February, 2004, Vol. 1, pp. 42-43 & 512-519 describes a one transistor and one capacitor cell. The transistor contains a SONOS (silicon-oxide-nitride-oxide-silicon) structure in the gate for non-volatile data retention. Hot-hole injection is used to inject holes to the traps in the gate dielectric and Fowler-Nordheim tunneling is used to remove the holes from the traps. In the non-volatile mode operations, the memory is erased and programmed in blocks and thus behaving like a Flash memory.
“High Density 5 Volt-Only Compatible Non-Volatile RAM Cell”, Guterman, Technical Digest of International Electron Devices Meeting, IEEE, December, 1982, Vol. 28, pp. 728-732, teaches a nonvolatile DRAM cell formed by merging a 1T-1C DRAM cell with a non-volatile cell formed by a transistor with a floating poly gate and a control poly gate. The resultant cell consists of 4 transistors and 2 capacitors.
“Challenges for the DRAM Cell Scaling to 40 nm”, Digest of IEDM, 2005, by W. Mueller et al., Technical Digest International IEEE Electron Devices Meeting, December 2005, pp. 4 reviews the concepts, status and challenges for the DRAM scaling down to 40 nm. The technologies that are discussed are the DRAM cell capacitor structures and materials, as well as the cell transistor structures. The DRAM cell capacitor structures illustrated are the stacked capacitor and the trench capacitor.
U.S. Pat. No. 5,181,188 (Yamauchi et al.), presents a memory cell formed by merging a DRAM cell and an Electrically Eraseable Programmable Read Only Memory (EEPROM) cell. The cell consists of 3 transistors and 1 capacitor. One of the transistors is used to isolate the DRAM portion of the cell from the EEPROM portion of the cell during DRAM operation or EEPROM operation. The transistor is turned on, however, when data is transferred from the EEPROM portion to the DRAM portion.
U.S. Pat. No. 6,798,008 (Choi) describes a memory cell that includes a non-volatile device and a DRAM cell. The cell consists of two transistors and one capacitor. One of the transistors is the non-volatile transistor which has a split-gate structure.
European Patent EP0557581 (Acovic-581) and U.S. Pat. No. 5,331,188 (Acovic-188) are directed to a one-transistor-one-capacitor non-volatile DRAM cell having a two layer floating gate to allow the contents of a storage capacitor to be transferred to the floating gate during power interruptions. The first layer of the floating gate is separated from a storage node of the storage capacitor by a tunnel oxide to allow electron tunneling between the floating gate and the storage capacitor. In one implementation, a dual electron injector structure is disposed between a one layer floating gate and the storage node to allow electrons to be injected between the floating gate and the storage node. An erase gate is implemented to remove the charge on the floating gate. The erase gate can be separated from the floating gate by a tunnel oxide or a single electron injector structure to allow electrons to travel from the floating gate to the erase gate.
U.S. Pat. No. 5,153,853 (Eby, et al.) teaches a method and apparatus for measuring threshold voltages associated with the EEPROM portion of a non-volatile DRAM (NVDRAM) memory cell.
U.S. Pat. Nos. 5,973,344 and 6,924,522 (Ma) describe a floating gate transistor formed by simultaneously creating buried contact openings on both EEPROM transistor gates and DRAM access transistor source/drain diffusions.
Conventional DRAM process steps are used to form cell storage capacitors in all the buried contact openings, including buried contact openings on EEPROM transistor gates. An EEPROM transistor gate and its associated cell storage capacitor bottom plate together forms a floating gate completely surrounded by insulating material. The top cell storage capacitor plate on an EEPROM transistor is used as a control gate to apply programming voltages to the EEPROM transistor. Reading, writing, and erasing the EEPROM element is analogous to conventional floating-gate tunneling oxide (FLOTOX) EEPROM devices. In this way, existing DRAM process steps are used to implement an EEPROM floating gate transistor nonvolatile memory element.
U.S. Pat. No. 6,754,108 and U.S. Patent Application 2006/0274580 (Forbes) teach DRAM cells with repressed floating gate memory with low tunnel barrier interpoly insulators. The memory cells have a volatile and a non-volatile component in a single memory cell. The memory cells include a first source/drain region and a second source/drain region separated by a channel region in a substrate. A storage capacitor is coupled to one of the first and the second source/drain regions. A floating gate opposes the channel region and is separated from the channel region by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The memory cell is adapted to operate in a dynamic mode of operation and a repressed memory mode of operation.
U.S. Pat. No. 6,996,007 (Ahn et al.—007) describes a non-volatile DRAM cell that contains a floating transistor and a storage capacitor. The floating gate pass transistor includes a charge storage floating gate that serves as temporary data storage when the memory transits from the non-volatile mode to the DRAM mode. The transition goes through a recall and a normalization process. The recall/normalization process is similar to the recall/erase operation described in Acovic-188. During the normalization process, data stored in the floating gate of all the memory cells is erased. Like the memory described in Acovic-188, during programming, the data stored in the storage capacitors of the memory cells is transferred to the floating gates, accomplished by injecting hot electrons from the source of the floating transistor connecting to the storage capacitor. In this scheme, the hot-electron injection is carried out by driving the common capacitor plate from 0.0V to 2.5V. Since the common capacitor plate connects to the storage capacitors of the all the cells in the same memory array. The programming is carried out in memory pages.
U.S. Pat. No. 7,099,181 (Ahn, et al.—181) provides a method for operating a non-volatile dynamic random access memory (NVDRAM) device having a plurality of memory cells, each cell having a capacitor and a transistor incorporating a floating gate. The memory cell of the NVDRAM device includes a control gate, a floating gate, two insulating layers, a transistor and a storage capacitor. The capacitor has a plate node, connecting to the plate nodes of the capacitor of other cells in the same array. The capacitor plate is coupled to a plate line with controllable plate line voltage for injecting and removing charge from the floating gates of the memory cells.