This invention relates to a baud-rate sampled-data system and, more particularly, to a method and circuitry for achieving timing recovery in such a system.
Timing recovery in digital synchronous data systems is a critical function. In the receiver of such a system, timing signals must be continuously adjusted in frequency and phase to compensate for drift that typically occurs between clocks utilized in the transmitter and receiver of the system. In that way, the respective sampling instants of successive received data signals can be optimized. With such optimization, the likelihood of being able to accurately reconstruct high-speed data received from a lossy transmission channel is significantly enhanced.
For a Nyquist-rate sampled-data system, conventional timing recovery techniques are available. Moreover, techniques have been proposed for achieving timing recovery in a baud-rate sampled-data system. These latter techniques are described, for example, in "Timing Recovery in Digital Synchronous Data Receivers", by K. H. Mueller and M. Muller, IEEE Transactions on Communications, Vol. COM-24, No. 5, May 1976, pp. 516-531, and in "A Digital Hybrid for Two-Wire Digital Subscriber Loops", by P. T. Nielsen and M. W. Gram, National Telecommunications Conference, 1978, pp. 21.2.1-21.2.7. These known baud-rate techniques are based on the assumption that the so-called post-cursor response of the channel is relatively invariant and predictable. But for a data system that includes a dispersive channel, such as an unloaded twisted-pair with bridged taps (of the type employed in a telecommunications network), this assumption is often an undependable basis for reliable timing recovery. In such a network, the post-cursor behavior of the channel is typically variable and unpredictable.
Accordingly, workers in the art have continued to search for reliable approaches on which to base timing recovery in a baud-rate sampled-data system of the type that includes a dispersive channel. It was recognized that such a search, if successful, would be one of the keys to realizing a high-speed full-duplex data system having considerable practical importance.