1. Field of the Invention
The present invention relates to a device for performing arithmetic operations of digital signal processing ("DSP") when provided with a fixed number of input/output data bits, and more particularly to an improved arithmetic operating device and method capable of enhancing a speed and accuracy thereof, wherein an overflowed data bit is employed during the arithmetic operation, and the overflowed data bit is eliminated upon completion of the arithmetic operation, for thereby carrying out a saturation only once on the basis of a resultant value of the arithmetic operation.
2. Description of the Prior Art
In a DSP algorithm, a multiplication and an accumulation are successively performed. Widely known DSP algorithms such as Finite Impulse Response Filter, Discrete Transform and Convolution, can be generalized as a summation operation, .SIGMA..sub.i c.sub.i f.sub.i. As indicated by the summation expression, a multiplication and an accumulation are carried out in consecutive steps.
During such an arithmetic operation, a resultant value in each step may exceed the size of a storage register, and this is called an overflow condition. When there occurs an overflow, there is carried out a saturation in which the data value that causes the overflow is replaced by the largest value within a plus (+) or minus (-) range of the overflowed value.
For example, assuming that the number of input/output data bits is 4, the MSB (most significant bit) is a sign bit, and fixed point arithmetic is adopted, and the numerical values which are to be expressed by the data bits range from -8 to +7, under such an assumption, when the binary values 0100.sub.2 and 0100.sub.2 are added up, there is obtained a binary value 1000.sub.2 which represents -8 instead of +8, so that the value 1000.sub.2 is converted to the largest value that is to be expressed within the fixed data size. That is, the value 1000.sub.2 is converted to 0111.sub.2 which is the largest positive value +7 capable of being expressed in the fixed data size.
FIG. 1 is a block diagram of an arithmetic operating device for a digital signal processing according to the conventional art. As shown therein, an adder 11 adds up an externally applied data DATA.sub.-- IN and a feedback data DATA.sub.-- OUT. An overflow detection unit 12 detects an overflow condition with regard to a data signal outputted from the adder 11. A saturation logic unit 13 saturates the data signal outputted from the adder 11 in accordance with a signal OF outputted from the overflow detection unit 12. An accumulator 14 accumulates a present output data signal and a previous output data signal which are outputted from the saturation logic unit 13, and the accumulated data DATA.sub.-- OUT is externally outputted and at the same time fed back to the adder 11.
With reference to FIG. 2 illustrating a detailed circuit view of the saturation logic unit 13, as shown therein, a converter 21 receives the MSB (most significant bit) from the data outputted from the adder 11 and carries out a saturation. A multiplexer 22 selects and outputs one of the data outputted from the converter 21 and the data outputted from the adder 11, in accordance with the output signal OF from the overflow detection unit 12.
The thusly constituted conventional arithmetic device for a digital signal processing will now be described.
Assuming that each of the input/output data DATA.sub.-- IN, DATA.sub.-- OUT are four bits, the most significant bits therein each becomes a sign bit. Therefore, in the case of using a 2's complement system, an expressible number with regard to the data ranges from -8 to +7.
When the input data DATA.sub.-- IN is 0100.sub.2, and the fed-back data DATA.sub.-- OUT is 0100.sub.2, the adder 11 adds up the input data DATA.sub.-- IN and the fed-back data DATA.sub.-- OUT and outputs a resultant data 1000.sub.2. The overflow detection unit 12 compares the respective MSBs of the two data DATA.sub.-- IN, DATA.sub.-- OUT with the MSBs of the data outputted from the adder 11. That is, when the respective MSBs of the two data DATA.sub.-- IN, DATA.sub.-- OUT are equal, and the respective MSBs of the two data DATA.sub.-- IN, DATA.sub.-- OUT are not identical to those of the output data, it is determined that an overflow error has occurred, and if the respective MSBs of the two data DATA.sub.-- IN, DATA.sub.-- OUT are equal, and the respective MSBs of the two data DATA.sub.-- IN, DATA.sub.-- OUT are identical to those of the output data, it is determined that an overflow error did not occur.
Returning to the above example, the MSBs of the two data DATA.sub.-- IN, DATA.sub.-- OUT which are applied to the adder 11 are respectively "0", and to the contrary, the MSB of the output data 1000.sub.2 is "1", thereby resulting in an overflow. Accordingly, the overflow detection unit 12 outputs a high level output signal OF to the saturation logic unit 13.
When the output data AR having a value of 1000.sub.2 is applied to a second input terminal IN2 of multiplexer 22 of the saturation logic unit 13, the MSB "1" of the output data AR is inputted to the converter 21. Then, the converter 21 receives the MSB "1" and outputs a value of 0111.sub.2 which is contrary to that of the data AR applied to the first input terminal IN1 of the multiplexer 22.
That is to say, the inverter INV in the converter 21 inverts the MSB "1" to "0". The buffer BUF receives the MSB "1" and outputs the remaining three bits except for the MSB "0" in the form of "1", thereby incurring a time delay.
The multiplexer 22 receives 0111.sub.2 through its first input terminal IN1 and 1000.sub.2 through its second input terminal IN2.
Because the output signal OF from the overflow detection unit 12 is at a high level, the multiplexer 22 selects and outputs the data 0111.sub.2 applied to its first input terminal IN1.
The accumulator 14 accumulates the output data 0111.sub.2 from the saturation logic unit 13 and the output data from the previous step, and the resulting output data DATA.sub.-- OUT is externally outputted and at the same time fed back to the adder 11.
However, when there does not occur an overflow in the adder 11, that is, when the output data from the adder 11 is less than 1000.sub.2, the overflow detection unit 12 outputs the output signal OF at a low level, and accordingly the multiplexer 22 in the saturation logic unit 13 passes the output data of the adder 11.
As described above, each time an arithmetic operation is performed, an overflow is detected for and a saturation is carried out if necessary, so that if a hundred arithmetic operations need to be performed so as to obtain a final resultant value, a hundred overflow detections and saturations must also be performed.
Likewise, the disadvantages of the conventional art are that there must be carried out an overflow detection and a saturation for each arithmetic operation, and it takes a considerable time in the buffer BUF of the converter 21 during the saturation.
Further, due to a consecutive saturation during the arithmetic operation, the more frequent the saturation, the worse becomes the accuracy of the final output value.
In order to avoid a time delay caused by such a saturation, there may be employed a technique for increasing the bit numbers in the adder by predicting the overflow frequency.
For example, if it is assumed that an input value is 32 bits and that there may occur four overflows on a maximal basis, the bit number of the output value is determined as 34 bits, whereby a saturation is not required without regard to an overflow generation.
If such a conventional technique employed in a particular hardware for a multiplication and a accumulation, then it is not necessary to consider an overflow. It is notable that although the bit number is increased to 34, the actual speed increase is significantly small. However, when such a conventional technique is applied to a DSP device, the size of an external device such as a memory device may be undesirably increased.