1. Field of the Invention
The present invention relates to a test quality evaluating and improving system provided for a semiconductor integrated circuit to evaluate and improve the test quality of the semiconductor integrated circuit, and a test quality evaluation and improvement method for the semiconductor integrated circuit.
2. Background Art
In recent years, various new failure modes have appeared in response to finer processes and an increasing number of wiring layers. Thus test quality demanded by customers has become hard to achieve only by test patterns generated for stuck-at faults (models) in LSIs of the prior art.
For example, the occurrence rate of short circuits between signal wires increases and thus it is necessary to consider bridge faults (models). Further, as LSIs become faster, the occurrence of abnormal delay increases with an increasing resistance on a via having the minimum size (hereinafter, will be simply referred to as VIA). Thus delay faults (models) have also become important.
However, when all fault models are considered and test patterns corresponding to the respective models are generated, resources and patterns are considerably increased (the test cost is also increased).
Thus in the presence of a number of failure modes, it is necessary to precisely estimate a failure rate at a customer (and a rejection rate in a system test before shipment) according to a test pattern applied to an LSI. In other words, for this estimation, it has become quite important to obtain a general test quality measure or a failure remaining rate in the LSI.
In other words, it is expected that test quality can be efficiently improved and test patterns can be effectively reduced by introducing a reliable test quality measure.
In the prior art, an LSI test quality measure belonging to the oldest category represents the relationship among a fault coverage, a failure remaining rate, and a yield.
For example, a defect level (failure remaining rate) “DL” is expressed by formula (1) (Williams-Brown model, for example, see T. W. Williams and N. C. Brown, “Defect Level as a Function of Fault Coverage”, IEEE Trans. Comp., Vol C-30, pp. 978-988, December, 1981).DL=1−Y(1−FC)  (1)where “Y” is a yield and “FC” is a fault coverage.
In formula (1), it is assumed that the probability of occurrence of faults is independently obtained as the same value “p”.
On the assumption that “m” faults are detectable out of all the assumed faults “n” of a device under test (DUT) (that is, FC=m/n is established), the following will examine event A: all the “n” faults are not defective and event B: all the “m” faults are not defective. In these events, a conditional probability “P” (A|B)′ is expressed by formula (2).P(A|B)=P(A∩B)/P(B)=(1−p)n/(1−p)m  (2)
In this case, DL=1−P(A|B) and Y=(1−p)n are established. Thus the defect level “DL” is expressed by formula (3).DL=1−Y(1−m/n)=1−Y(1−FC)  (3)
For example, when specific values are substituted into formula (3), the following result is obtained.
In the case of Y=70% and FC=99%, the failure remaining rate “DL” is 0.35% (3500 ppm).
In the case of Y=90%, it is necessary to set “FC” at 99.9% to achieve DL=100 ppm.
Formula (3) is valuable in that the fault coverage “FC” is correlated with the yield “Y” and the failure remaining rate “DL”. However, it is known that formula (3) is determined based on the total number of assumed faults in an LSI and an obtained result does not always perfectly match with an actual result (may be different by one digit). Thus some improvements are obviously necessary. For example, formula (4) is used as an empirical equation.DL=1−Y(1−√FC)  (4)
It is known that correlation between a failure remaining rate and a failure occurrence rate is improved to a certain extent by formula (4). However, this method lacks definite grounds and a result of the introduction of two or more fault models is not clear.
The yield “Y” can be also expressed by, for example, formula (5) on the assumption that just a few pieces of dust fall onto a chip and formula (5) complies with Poisson distribution.Y=exp[−A·D0]  (5)where “A” is an area of a target portion and “D0” is a density of dust.
By combining formula (3) and formula (5), relational expression (6) is obtained as follows:DL=1−exp[−A·D0·(1−FC)]  (6)
In formula (6), when an exponential term is close to 0 (in other words, when the dust level is low and the fault coverage “FC” is high), formula (6) is approximated as expressed by formula (7) below.DL≈A·D0·(1−FC) or DL≈A·D0·(1−√FC)  (7)
In recent years, efforts have been made to improve accuracy by using not only overall dust information but also dust information corresponding to the critical area (CA) of each layer. However, correlation between a fault and a failure mode is insufficient and thus high correlation cannot be expected between the failure remaining rate “DL” and the fault coverage “FC”.
Thus a weighted fault coverage obtained by adding a layout weight to each fault has been recently used in response to finer processes.
Further, in the test quality evaluation of the prior art, for example, attention is given to a fact that each fault can be correlated with a failure occurring on each layout element. A layout element corresponding to a failure is weighted, the achieved fault coverage of each fault model is determined based on relative failure occurrence rate information obtained by mainly accumulating a number of failure analysis results, and test patterns are efficiently generated. Thus required test quality can be achieved by the test pattern close to the minimum (for example, see Japanese Patent Laid-Open No. 2006-10351).
However, the prior art does not disclose how each resultant weighted fault coverage is quantified as an actual test quality measure of an LSI.
As described above, in the estimation of a failure remaining rate in an LSI, the rate being highly correlated with a failure (or rejection) rate in a market and so on, layout information directly correlated with a failure occurrence rate has been used in some techniques.
However, a proper relational expression has not been proposed yet. In other words, when calculating the level of failures remaining in a product after a shipping test, the calculation is based on a theoretical formula including an unclearly defined yield. Thus even when using a fault coverage and the like obtained by adding the weight of a layout element, the failure remaining rate in the product cannot be obtained with high accuracy.
Therefore, high correlation is hardly expected between a failure remaining rate and a failure (or rejection) rate in a market or an actual use, so that test quality is hard to improve in the prior art.