The demand for higher operating speeds and increased functionality of semiconductor integrated circuit devices have driven designs to extreme integration densities and extremely small minimum feature sixes near the limits of lithographic mask image resolution, principally due to diffraction distortion effects, and the capability of lithographic processes to produce structures with adequate shape fidelity to the lithographic resist exposure to avoid significant chip-to-chip variation in electrical characteristics or reliability. Smaller electronic element (e.g. transistors) size and increased proximity allows higher circuit density and often requires operation at reduced voltages and currents which reduces power consumption and allows more devices to be fabricated on a single chip of given dimensions and lithographic process costs while increased proximity of electrical elements reduces signal propagation time and reduces susceptibility to noise.
This same demand has necessitated the development of numerous sophisticated lithographic exposure processes in order to extend the limits of lithographic resolution and shape fidelity of lithographic processes. For example, lithographic resists have been developed which can be exposed by energy of very short wavelengths such as ultraviolet light, X-rays and electron beam exposures in order to increase resolution. So-called phase shift masks have also been developed to provide a degree of control over diffraction distortion effects. Masks having “pre-corrected” shapes have also been developed to more accuracy produce intended shapes at sizes where diffraction distortion effects occur and are referred to as optical proximity correction (OPC) masks. Additionally, several techniques have been developed for multiple exposures of one or more resists, sometimes in conjunction with a so-called hard mask, that have achieved some degree of success in improving lithographic exposure resolution and/or fidelity but which do so at the expense or increased process/complexity and cost; significantly for the design and preparation of multiple masks for the respective exposures. Further* each of the multiple exposures is subject to registration or “overlay” errors which can compromise manufacturing yield.
Image reversal resists are also Known and provide some degree of improvement in image fidelity. Essentially, image reversal resists: cause initially exposed areas soluble and subject to development in the manner of a normal positive resist. However, if the exposed resist is then balked instead of being developed, the initially exposed areas become substantially inert due to cross-linking that occurs during the baking process while leaving unexposed areas unaffected. If the resist is exposed again with an unpatterned, so-called “flood” exposure, the initially-unexposed areas become soluble and can be developed and removed in the normal manner with a suitable developer; leaving the initially exposed areas of the resist, which have been rendered inert by the baking process, in place; a result similar to the use of a negative resist but with improved properties of resistance to many lithographic processes and thus capable of producing improved shape fidelity of the structures formed by those lithographic processes. Known commercially available image reversal resists include AZ 5214E, TI 35E, TI 35ES, Ti Plating, TI xLift, TI Spray and AZ nLof 2070, all of which are available from Clariant AZ Electronic Materials Corp.