As semiconductor devices become more integrated, the design rule in next generation ultra-high integrated semiconductor devices becomes more and more fine.
In semiconductor devices having very fine design rules, the wiring or pitch between electrodes is often very small. This can lead to the problem that capacitance between the wirings is generally quite large.
The increase of the capacitance between the wirings typically leads to an increase in RC delay, thereby decreasing the operating speed of the device.
Thus, there exists a need in the art for an improved metal wiring and forming method thereof.