1. Field of the Invention
This invention relates to a solid-state multiple-layer photonic-electronic circuit board package family, having interconnected layers of photonic circuitry and electronic circuitry.
2. Description of Related Art
Significant advances in the last two decades in semiconductor microelectronics technologies have resulted in memory chip capacities exceeding one Gigabyte and logic chip speeds exceeding one GigaHertz. Systems studies have continuously shown that on-board interconnects between chips are the bottleneck in achieving a board-level performance that is comparable to the intra-chip data rates. As minimum feature sizes fall below 100 nm, the clock rates of leading-edge microprocessors are expected to exceed 10 GHz in the next few years, further emphasizing the need for faster chip-to-chip interconnects. It is well recognized that a doubling of transistor density in a chip increases the on-board interconnect complexity by a factor greater than two. The ever-increasing complexity of the devices is also leading to the need for a larger number of interconnect layers.
Photonic data transmission between chips is a potential solution to this fundamental problem of on-board interconnect complexity, but several technological hurdles have prevented implementation of this approach. These include the co-existence of multiple photonic and electronic layers in a single circuit board, optical vias to transport light between different photonics layers, and an all-lithographic fabrication technology that can use mutually compatible planar processing steps to build the entire circuit board. This patent application addresses these key barriers through innovative fabrication processes, materials, and photonic devices. This address enables integration of very high-density optical interconnect structures in a low-profile, planar format to achieve the goal of realizing cost-effective, high-performance photonic printed circuit boards.
Two major photonic interconnect approaches exist for next generation data transmission needs: free-space, and embedded, planar interconnects. The free-space approach uses VCSELs (vertical cavity surface emitting lasers) to direct signals out of the board towards micro-optics (such as micro-lenses, micromirrors, and gratings), which then redirect the signals. These micro-optical components must protrude 10 to 20 mm above the surface of the circuit board in order to send and receive light in a plane parallel to the board surface. This approach has the potential to increase the data rate significantly because it eliminates cross-talk and allows use of 2D channel arrays. Another advantage is that the interconnect scheme is reconfigurable, i.e., the communication between processors can be reprogrammed according to the specific task at hand by redirecting the laser signals. The major disadvantages of this approach are that it requires extremely tight alignment tolerances for the placement of the micro-optical components, the thickness of the board is very large (tens of mm), and it is sensitive to vibration, contamination, and other environmental effects.
Several organizations have conducted research in embedded photonic interconnect techniques that overcome many of the above-stated problems. For example, technology has been developed for embedding fixed-position micromirrors in waveguide layers in order to redirect a guided beam from horizontal to vertical, or to achieve a bend in the horizontal plane. One approach is based on a slow, multistep, silicon-wafer-based process, which includes for example, chemical mechanical polishing, a step which would likely be far too time consuming for a mass-produced item. Another approach is based on an embossing technique, which, in addition to being quite time consuming to produce, lacks both resolution and alignment precision.
While these technologies have the potential to overcome the limitations of the free-space method, the fabrication processes are not suitable for high-throughput production. In addition to the throughput and alignment challenges mentioned here, other key challenges that must be addressed are transmission and coupling losses as well as the, currently, low levels of integration.
Efforts to improve the fabrication process for photonic interconnects have included a demonstration of a hybrid electrical-optical circuit board (EOCB) using a hot embossing technique to fabricate an optical foil and then laminating this foil into a PCB. This technique, while inexpensive, does not yield smooth channel walls and is difficult to implement on large, non-planar substrates. Other work has developed photonic backplanes using a hybrid approach, employing laser diodes and discrete components such as micro-lenses to send signals to a backplanes that has embedded polymer waveguides. Prototypes having data rates of 1 Gb/s across distances of less than 100 cm have been successfully tested.
Guided by the lessons learned from integrated circuit technology, it is likely that the best solution to the optical interconnect challenge is an all-lithographic planar fabrication process. New patternable polymer materials have recently been developed that exhibit excellent transparency over a large wavelength range and offer the potential to achieve very high level of optical integration, at high throughputs and with high resolution.
A primary barrier to the realization of high-speed optical chip-to-chip interconnection has been the numerous optical signal losses that plague present transmission, insertion, and coupling techniques. These losses have arisen due to lack of process technologies that enable high-yield fabrication of the required devices in the desired configurations and relative orientations. In the case of waveguide structures, high-speed, single-mode (or even multi-mode) waveguides have not been manufactured for runs of large distances due to, for example, the scattering losses that arise from the stitching of the waveguide structures. In the current state of planar photonic interconnect technology, the overall level of integration is low, the number of discrete components used is high, and the alignment precision is poor. Furthermore, the sizes of integrated elements are coarse and the number of integrated optical elements is low. As a result, achievable data rates as well as channel densities have been limited.
Compared to this prior art, this invention provides a platform of manufacturing processes that enables the fabrication of novel photonic interconnect structures leading to high-density, heterogeneous integration of photonic and electronic devices. This invention will enable the design and manufacture of photonically interconnected systems transmitting data at speeds of at least 10 GHz (extendable to >50 GHz) with channel densities of at least 16 channels/mm (extendable to >100 channels/mm) over distances of at least 300 mm (extendable to >1 m). Such systems, in a multilayer planar format, provide a low-profile interconnect structure (<25 mm thick, extendable to <10 mm). Fabrication of such systems can be achieved on large areas (>1000 cm2), at high throughputs (up to 4 sq. ft./min.), and on a variety of substrates (including flexible materials).
These photonic interconnect structures may include long planar waveguides, splitters, embedded 45° mirrors, and optical vias (connecting two photonic layers), among others. These photonic interconnect structures are fabricated by lithography, photoablation, or image-wise refractive index modulation using large-area, high-resolution, seamless patterning technologies. The materials for these structures may be polymer-based, hybrid materials, nanocomposites, and self-assembled structures.
The result is alignment-tolerant fabrication of integrated, photonic circuit optical layers on large-area boards and/or flexible substrates.