1. Field of the Invention
This invention relates generally to semiconductor memories, and particularly to a system for blocking multiple memory read port activation.
2. Description of Background
The operation of semiconductor memory systems with multiple outputs (or “read ports”) for each memory cell can be enhanced by preventing the simultaneous activation of multiple read ports from the same memory cell, which improves performance and/or decreases power consumption. Such enhancements are generally accomplished by detecting data requests from multiple (e.g., two or more) read ports for the same memory location (or “address”) and blocking the activation of the control inputs (or “word lines”) to the non-preferred read port(s), which are then fed the data from the activated preferred read port through a connecting switch.
However, this detecting (or “comparing”) function can limit the performance of such enhanced memory systems, thereby defeating the enhancement benefits. For example, the blocking of multiple word line activation can be delayed as a result of the delay involved with completing the comparing function, which can counteract the improved performance and decreased power consumption benefits. Thus, a more efficient alternative to the comparing function is desirable to further promote the benefits of blocking multiple read port activation from the same memory address.