Advancements in semiconductor manufacture have led to increases in the density and miniaturization of microelectronic circuits. As an example, the manufacture of 16 Mb DRAMs is now possible and 64 Mb and 256 Mb prototypes are currently being developed. A key requirement for achieving such high device packing density is the formation of suitable storage capacitors.
With the increased packing density of memory cells, however, the area available for storage capacitors (i.e storage nodes) has decreased. This has necessitated the development of storage capacitors having an increased capacitance. In general, storage capacitors can be formed as stacked structures or as trench structures. The present invention is concerned with stacked capacitors having a high storage capacity.
Typically a thin film stacked storage capacitor includes a lower electrode, an upper electrode, and a dielectric layer which is sandwiched between the electrodes. This capacitor structure is stacked on an insulating layer of a substrate. The insulating layer may be formed of insulating materials such as SiO.sub.2 and Si.sub.3 N.sub.4 that are compatible with a silicon process. The lower electrode of the capacitor is connected to an FET transistor formed on the substrate. In the past, a polycrystalline silicon layer has been used as the lower electrode of a capacitor. Such a polysilicon layer is sometimes referred to as a polysilicon (or silicon) electrode.
One way for increasing the capacity of this type capacitor is to use a dielectric layer formed with a high dielectric constant material. These high dielectric constant materials include inorganic non-metallic oxides in the paraelectric or ferroelectric phase such as BaSrTiO.sub.3 (BST), BaTiO.sub.3, SrTiO.sub.3, PbZrO.sub.3 and others. (Better insulating inorganic metal oxides are sometimes also used). Such high dielectric constant materials have a dielectric constant larger than 100. This is an order of magnitude larger than traditional dielectric materials, such as SiO.sub.2 and Si.sub.3 N.sub.4, which have dielectric constants of less than 10.
A problem with this type of high capacity capacitor is that in general, high dielectric constant films cannot be formed directly over a polysilicon electrode. This is because an interface layer of silicon dioxide forms between the dielectric film and the polysilicon electrode. Such an interface layer reduces the effective dielectric constant the dielectric material and defeats its purpose. For this reason the lower electrode structure is typically formed as a stack comprising a barrier layer formed on the polysilicon electrode and then the lower electrode formed on the barrier layer.
The barrier layer is typically formed of a conductive material such as tantalum (Ta) or titanium nitride (TiN). Such a barrier layer in addition to preventing oxidation of the polysilicon electrode also functions to prevent silicon diffusion into the lower electrode. Such silicon diffusion would increase the resistivity of the lower electrode and could lead to the formation of a thin SiO.sub.2 layer on top of the lower electrode.
Another problem associated with the use of high dielectric constant films is that these films must be deposited at relatively high temperature (i.e. 600.degree.-700.degree. C.). Because of the high process temperatures that are required, the lower electrode of such a capacitor is typically formed of a high melting point, non-oxidizing metal such as platinum, palladium or rhodium or of a conducting oxide such as ruthenuim oxide, iridium oxide, osmium oxide or rhodium oxide. A non-oxidizing material is required for the lower electrode because a traditional electrode material such as aluminum, titanium, nichrome or copper will oxidize at the high temperatures increasing the resistivity of the electrode.
One such improved high capacitance capacitor is described in the technical article entitled "A Stacked Capacitor With (Ba.sub.x Sr.sub.1-x)Tio.sub.3 For 256M DRAM") by Koyama et al. in IEDM 91-823 at pgs. 32.1-4. Such a stacked capacitor is shown in FIG. 1 and generally designated as 10. A memory array includes many of these capacitors arranged in a matrix.
With reference to FIG. 1, a semiconductor substrate 12 includes an FET transistor (not shown) formed with a pair of insulated gate electrodes 14, 16. An insulating layer 18 (i.e. SiO.sub.2) is formed over the FET transistor and gate electrodes 14, 16. The capacitor 10 is stacked on this insulating layer 18. A polysilicon plug 20 (or polysilicon electrode) is formed in a contact hole placed through the insulating layer 18 to the source or drain region 30 of the FET transistor.
The capacitor 10 includes a lower electrode 22, an upper electrode 24, and a dielectric film 26 formed between the lower electrode 22 and the upper electrode 24. The dielectric film 26 comprises a nigh dielectric constant material such as BaSrTiO.sub.3. The capacitor 10 also includes a barrier layer 28 formed between the lower electrode 22 and the polysilicon plug 20. The barrier layer 28 is preferably formed of a conducting material, such as Ta or TiN.
As previously explained, the barrier layer 28 is required to prevent the oxidation of the polysilicon plug 20 and the formation of an interfacial oxide. In addition, the barrier layer 28 prevents the reaction of the lower electrode 22 with the polysilicon plug 20.
Such a stacked capacitor represents the state of the art for high capacitance stacked capacitors. This capacitor structure, however, is subject to several limitations.
A first limitation is that the dielectric layer 26 must be formed over the stepped or non-planar surface contour provided by the stack formed by the lower electrode 22 and barrier layer 28. Poor step coverage of the dielectric material 26 over the lower electrode 22 promotes charge leakage at the corners 32, 33 of the dielectric material 26 in the completed capacitor structure. For this reason an insulating material such as SiO.sub.2 is sometimes deposited over the outside corners of the dielectric film 26.
Another limitation of this type of high capacity capacitor 10 is that the sidewalls 34, 36 of the barrier layer 28 are exposed to oxidation during deposition of the dielectric film 26. Accordingly, the high temperatures encountered during the dielectric deposition process will cause the sidewalls of the barrier layer 28 to oxidize. Such an oxide will increase the contact resistance of the barrier layer 28. In addition, with an oxide formed on the sidewalls 34, 36 of the barrier layer 28, the lower electrode 22 will not adhere as well to the barrier layer 28. This may cause the lower electrode 22 to lift off and separate from the barrier layer 28.
Finally, if the barrier layer 28 does not completely overlap the polysilicon plug 20, then the surface of the polysilicon plug 20 will oxidize during deposition of the dielectric material 26 . A critical alignment of the barrier layer 28 with the polysilicon plug 20 is thus required.
In view of these problems, there is a need in the art for a stacked capacitor structure which is not subject to these limitations. Accordingly, it is an object of the present invention to provide an improved high dielectric constant capacitor and a method for manufacturing such a capacitor. It is a further object of the present invention to provide a high dielectric constant capacitor in which a dielectric layer is formed with a smooth geometry so that current leakage from the dielectric layer is minimized. It is a further object of the present invention to provide a high dielectric constant capacitor in which a barrier layer of the capacitor is protected from oxidation during manufacture. It is yet another object of the present in invention to provide a high dielectric constant capacitor which a polysilicon electrode for the capacitor is protected from oxidation during manufacture. Finally, it is an object of the present invention to provide a method for forming a high dielectric constant capacitor that is adaptable to large scale semiconductor manufacture.