Embodiments of the present invention generally relate to a semiconductor device comprising of a fin-type gate, and more specifically, to a semiconductor device and a method for manufacturing the same that can effectively reduce the resistance of a source and drain of an active region.
Due to the high integration of semiconductor devices, a process margin for forming an active region and a device isolation region has been reduced. Specifically, as a semiconductor device is manufactured with lower-power or higher-speed elements, a gate width has been narrowed and a channel length has been reduced. This reduction will degrade an electrical characteristic of the semiconductor device and result in a short channel effect. As a result, methods to improve the reliability of the device have been required.
Of these methods, a multi-channel field effect transistor (McFET) such as a recess gate and a fin-type gate has been used. The recess gate is obtained by etching a given depth of a semiconductor substrate of a gate expected region to increase a channel length. The fin-type gate increases the contact area between the active region and the gate to improve the driving capacity of the gate and the electrical characteristics of the device.
A fin-type transistor has a fin channel structure where a three-side gate surrounds a channel. A fin channel structure does not go beyond the established manufacturing technique but can be manufactured to have a three-dimensional structure. Due to its structural characteristic, the fine channel structure has a good gate control capacity to reduce the short channel effect, thereby minimizing the effect between the drain region and the source region. Additionally, the fin channel structure can reduce the channel doping concentration, thereby preventing leakage current through a junction region.
In order to form the fin-type transistor, a damascene method such as a method of exposing both sides of the active region has been is generally used. The process includes forming a device isolation region to set the active region and recessing a partial surface of the device isolation region. A gate line is formed in a recess groove formed in the device isolation region so that the gate may be disposed on both side surfaces of the active region.
Meanwhile, the entire resistance of the fin-type gate is determined by the channel resistance and resistance in the source and drain region. Generally, the resistance of the source and drain region of the fin-type gate is determined by an interface between metal silicide and silicon formed in a silicon part of the source and drain region.