The invention relates to transistor structures, particularly useful in MOSFETs, in which the conductive channel is formed on the A-face of the semiconductor body. The problems addressed by this invention include (i) reducing channel resistance in the on-state for optimal current output and (ii) minimizing field crowding effects to maximize the reverse voltage blocking capabilities within the device.
Over the last twenty years, transistor designs have been optimized to achieve a controlled current flow in the on-state while simultaneously having the ability to block certain voltages in the off-state. The development of better semiconductor materials, including silicon carbide and the Group III nitrides, has led to extraordinary advancements in transistor design that allow greater control over transistor performance in both the on-state (e.g., higher current output) and the off-state (higher voltage blocking with less leakage current). Silicon carbide has been of particular interest due to its electrical characteristics in a variety of crystal structures.
Silicon carbide's crystal structure is often described by the elemental configuration of the layer being used. A cross section of a silicon carbide substrate shows either a layer of carbon atoms directly on top of a layer of silicon atoms, or vice versa. The silicon layer is often polished and used for forming devices thereon, and it is known as the silicon face. If the carbon layer is exposed, it is known as the carbon face. See Zetterling, Carl-Mikael, Process Technology for Silicon Carbide Devices, Institute of Electrical Engineers (2002), Page 3.
The axes of alignment for the silicon carbide crystal also play important roles in choosing the orientation for forming a semiconductor device. Traditionally, for hexagonal crystal structures, four principal axes are commonly used: a1, a2, a3, and c. All of the a-vectors are in the same plane (“the a-plane), and the c-vector is in the c-plane that is perpendicular to the a-plane. Ibid.
Prior researchers have attempted to use different planes, or faces, of the silicon carbide crystal to achieve various performance characteristics in the resulting device. Yano, et al., for example, disclose the channel mobility characteristics of MOSFETS formed on the c-face and improved results for inversion layer mobility on the a-face of a 4H—SiC substrate. See Yano, Kimoto, Matsunami, Asano, and Sugawara, “High Channel Mobility in Inversion Layers of 4H—SiC MOSFETs by Utilizing (11 20) Face,” IEEE Electron Device Letters, Vol. 20, No. 12 (December 1999), Pages 611-613.
Yano et al. formed two types of MOSFETs with currents perpendicular to one another on the same substrate. Drain current for the MOSFET formed on the (11 20) face improved substantially, showing a significant increase in channel mobility by using the a-face (11 20) of the silicon carbide. Yano's design, however, is not preferable in vertical power devices because the Yano devices have a lower critical field and conduct under reversed bias at lower gate voltages than desired. The sole technique of developing the MOSFET on the a-face, without additional parameters being adjusted as well, has not proven to be the best answer in the context of optimizing performance in power MOSFETs.
Previous efforts to maximize current flow in power MOSFETs have addressed the channel resistance of the silicon carbide devices, as channel resistance creates a significant part of the total MOSFET on-resistance, especially for low voltage (<2 kV) silicon carbide MOSFETs. Approaches to reducing the channel resistance have focused on (1) improving channel mobility, (2) reducing device cell pitch, and (3) reducing channel length. Although research efforts have studied these approaches extensively, DMOSFETs (double diffused metal oxide semiconductors FETs) and UMOSFETs (trench gated metal oxide semiconductor FETs) of the prior art have shown only marginal improvements in achieving the desired increase in channel mobility. For example, known UMOSFETs show an increased carrier density in the conductive channel, but these same devices suffer from the electrical field crowding at the trench gate corners under reverse bias.
FIGS. 1 and 4 show a prior art DMOSFET (5) and a prior art UMOSFET (28) respectively. A traditional DMOSFET (5) includes source, gate, and drain contacts (10, 11, 12) positioned on a semiconductor body (18) with the gate contact (11) atop an oxide layer (15) insulating the gate region. The DMOSFET (5) includes a p+ type well (19) implanted into the semiconductor to a depth of about 0.5 microns and doped to about 1e20 cm−3. An n+ source region (20) doped to about 1e20 cm−3 is adjacent the p+ well (19) and positioned between the p+ well (19) and the buried channel (21). The buried channel (21) extends across portions of the source (20), the p+ well (19) and the semiconductor body (18) between active regions, i.e., the JFET region (23). The buried channel (21), the JFET region (23), and the supporting drift region (24) of the DMOSFET (5) are doped to about 1e16 cm−3. In a typical prior art DMOSFET, the fabrication process controls the channel surface by using ion implantation instead of doping during layer growth. Ion implantation is difficult to achieve accurately in DMOSFETs, and the resulting devices are limited in channel mobility.
The channel resistance of the DMOSFET (5) of FIG. 1 is set forth in the forward voltage v. current curves of FIG. 2. As shown therein, the DMOSFET (5) of FIG. 1 achieves channel mobility of 40 cm2/Vs and a specific on resistance of about 4.62 mΩ·cm2. Accordingly, FIG. 3 shows the forward current distribution of the prior art DMOSFET (5) of FIG. 1. These values are in line with known DMOSFETs that achieve a typical channel mobility of between about 25 to 50 cm2/Vs. As shown in FIG. 3, the current distribution in the drift region (24) of the device is far less than the optimal current in the upper portion (23) closer to the gate. FIG. 3 shows that the current is not spreading as desired for maximum flow through the device to the drain (12).
The prior art UMOSFET (28) of FIG. 4 suffers similar current restrictions. As set forth in the drawing, UMOSFET (28) includes the standard source (30), gate (31), and drain (32) with the gate (31) atop an oxide layer (33) lining a trench (36). The buried channel (38) of the UMOSFET (28) extends across the source (30) and down into the trench (36) such that the buried channel (38) is between the epitaxial layers of the p-n junction (40, 41) and the oxide layer (33). The problem with the prior art UMOSFET is that the corner of the trench (42) exhibits a noted crowding of the electric field at the corner of the trench, inhibiting current flow through the drift region (43) and the substrate (44) down to the drain (32). The field crowding also results in a lower sustained gate voltage during reverse bias operation.
The UMOSFET of FIG. 4 also requires a trench that is greater than 2 microns for proper gate placement and operation. Given that reactive ion etching is often the method of choice for forming a trench in a UMOSFET, the trench wall is so severely damaged in the fabrication process that the conductive channel is constricted. Uniform results are difficult to achieve when subjecting silicon carbide to reactive ion etching, and the resulting devices are not reliable. The damage caused by the etching also deteriorates the oxide quality formed thereon for insulation purposes. These factors combine in prior art UMOSFETs to require an on-voltage of up to 30 volts for forward conduction.
Prior art DMOSFET and UMOSFET devices of FIGS. 1 and 4 illustrate the common need for modifications to transistor design that increases maximum current flow in the on state with the ability to block incident voltages in reverse biased operation.
U.S. Pat. No. 5,976,936 (Miyajima 1999) shows another example of a prior silicon carbide MOSFET developed with the goal of increasing current in the channel while controlling the threshold voltage and blocking characteristics for the device. The Miyajima '936 patent utilizes a vertical layer of silicon carbide along the gate trench wall for the channel layer. The vertical channel layer is quite thin—about 1000 to 5000 angstroms. The Miyajima '936 design, however, still suffers the problem of current crowding at the edges of the trench. Miyajima, furthermore, makes no reference to using the a-face of the silicon carbide crystal to enhance channel mobility.
Published U.S. Patent Application 20020185679 (Baliga 2002) addresses some of the same issues in simultaneously supporting large voltages and operating in a current saturation mode. The Baliga '679 patent application uses deep well extensions (P+ implants), which could arguably alleviate the current crowding at the trench corners. Previous research into these well extensions, however, showed that the deep wells typically resulted in a high JFET resistance, thereby requiring a deeper trench. Baliga actually encourages the JFET effect by using deep P+ wells to deplete the region adjacent the wells. Baliga then uses the JFET effect to operate the depleted region of the device as a field effect transistor while the drain region is in current saturation mode. The problem of the JFET region constricting the current flow to the drain is still evident in Baliga's device.
Prior efforts to achieve a power transistor with high current output in the on-state and reduced current crowding at the gate trench under reversed bias have been largely unsuccessful. The prior art has been unsuccessful in addressing the competing factors of decreasing channel resistance along a gate trench sidewall and increasing the capacity of the device to spread the electric field across the semiconductor device under reversed bias.