One of the fastest growing segments of the semiconductor industry is the manufacture of multi-chip modules (MCM). Multi-chip modules are being increasingly used in computers to form PC chip sets and in telecommunication items such as modems and cellular telephones. In addition, consumer electronic products such as watches and calculators typically include multi-chip modules.
With a multi-chip module, non-encapsulated dice (i.e., chips) are secured to a substrate using an adhesive. Electrical connections are then made directly to the bond pads on each die and to electrical leads on the substrate. The multi-chip module is favored because it provides significant cost and performance characteristics over packaged dice. It has been estimated that by the year 2000, 25% of all dice will be utilized in their bare or unpackaged form.
In view of the trend towards multi-chip modules, semiconductor manufacturers are required to supply unencapsulated dice that have been tested and certified as known good die (KGD). This has led to the development of test apparatus suitable for testing individual or discrete semiconductor die. As an example, test apparatus for conducting burn-in tests for discrete die are disclosed in U.S. Pat. No. 4,899,107 to Corbett et al. and U.S. Pat. No. 5,302,891 to Wood et al., which are assigned to Micron Technology, Inc. Other test apparatus for discrete die are disclosed in U.S. Pat. No. 5,123,850 to Elder et al., and U.S. Pat. No. 5,073,117 to Malhi et al., which are assigned to Texas Instruments.
With this type of test apparatus, a non-permanent electrical connection must be made between the bond pads or other contact locations on a bare, discrete die and the external test circuitry of the test apparatus. The bond pads provide a connection point for testing the integrated circuitry of the die. Bond pads on semiconductor dice are typically formed of either aluminum, gold or solder using different pad metallurgies. Furthermore, a bond pad may have a flat planar configuration or it may be formed as a raised bump.
The test apparatus for discrete die employ different techniques for making a non permanent connection to the bond pads of the die. As an example, the previously cited Wood et al. device employs a die contact member that utilizes non-bonded TAB (tape automated bonding) technology. The Elder et al. device utilizes a flexible interconnect member having an arrangement of probe bumps or members for contacting the bond pads. The Malhi et al. device uses an arrangement of cantilevered probe tips to contact the bond pads.
Alternately, non permanent wire bonding may be employed to effect the electrical connection. U.S. Pat. No. 5,173,451 to Kinsman assigned to Micron Technology, Inc. describes a method in which each die is mounted in a carrier and bond wires are non permanently attached to the bond pads using ultrasonic wedge bonding. The carrier and die are placed in the test apparatus and the bond wires are connected to external test circuitry for testing the integrated circuits on the die. Following completion of the test procedure, the temporary bond wires are separated from the bond pads and the die is separated from the carrier.
In addition to wire bonding, TAB connections and probe tips, other interconnect structures have been used to connect the bond pads on a die with the circuitry of a test apparatus. As an example, U.S. Pat. No. 5,177,439 to Liu et al., describes a test apparatus that includes a probe card for making electrical contact with the bond pads of a die. The probe card is an interconnection structure formed of a semiconducting material such as silicon. The Liu probe card includes pointed silicon protrusions coated with a conductive film for contacting the bond pads. U.S. Pat. No. 5,207,585 to Byrnes et al. describes an interconnect structure formed as a flexible pellicle having electrodes for making a temporary connection with bond pads formed as a flat pad or as a conductive bump.
Regardless of which bond pad connection technique is employed, it is desirable to effect a connection that causes as little damage as possible to the bond pad. If the temporary connection to a bond pad damages the pad, the entire die may be rendered as defective. This is difficult to accomplish because the connection must also produce a low resistance or ohmic contact with the bond pad. A bond pad typically includes a metal oxide layer that must be penetrated to make an ohmic contact. Some prior art interconnect structures, such as probe cards, scrape the bond pads which wipes away this oxide layer and causes excessive damage to the bond pads. Probe tips may pierce both the oxide layer and the metal bond pad and leave a deep gouge. Other interconnect structures, such as probe bumps, may not even pierce the oxide layer preventing the formation of an ohmic contact.
Another important consideration in KGD testing is the effect of thermal expansion during the test procedure. During burn-in testing, a die is heated to an elevated temperature. This causes thermal expansion of the die and test fixture. If the bond pads and the interconnect structure expand by a different amount, stress may develop between these components and adversely effect the electrical connection there between. This may also lead to excessive damage of bond pads.
In general, current physical testing apparatus for testing discrete semiconductor die have become the limiting factor in providing KGD at optimal yields. As is apparent, improved testing methods and structures for discrete die are needed in the art that are cost effective and that can be incorporated into the existing technology of large scale semiconductor manufacture.
Accordingly, it is an object of the present invention to provide an improved method for fabricating temporary interconnects for testing discrete semiconductor dice. It is a further object of the present invention to provide an improved method for fabricating temporary interconnects that is compatible with large scale semiconductor manufacture and that provides an improved interconnect structure. It is yet another object of the present invention to provide an improved method for fabricating temporary interconnects that are characterized by contact members having a conductive tip and a low resistance conductive trace for connection to external test circuitry.