1. Field of the Invention
The present invention relates to a delay characteristic analyzing method for analyzing the delay characteristic of a custom LSI precisely in the EDA (electronic design automation) for custom LSIs that is used for elaborate designing on the transistor level.
To design a custom LSI that exhibits necessary performance reliably, a transistor-level design technology makes it possible to design a custom LSI by combining a wide variety of transistors freely is required.
To evaluate correctly whether a full custom LSI that has been designed elaborately on the transistor level exhibits necessary performance, a delay characteristic analyzing method for analyzing its delay characteristic very accurately and a delay characteristic analyzing system using such a delay characteristic analyzing method are indispensable.
2. Description of the Related Art
Among the paths connecting an input node and an output node of an LSI, paths along which a signal reaches the output node with a shortest delay time and a longest delay time are called critical paths, respectively. The critical paths and their delay times are part of the important indices that are used to judge whether a designed LSI exhibits intended performance and to identify portions where design modification is needed. The timing analysis methodology is used widely in the custom LSI designing to extract critical paths.
In fields where elaborate transistor-level designing is needed, the dynamic timing analysis using an electrical circuit simulation is performed on the entire net list that indicates a connection between transistors to estimate precisely a delay time of signal transmission along every conceivable path.
However, for LSIs having a large scale, the dynamic timing analysis that is performed on the entire net list is not a realistic method for the following reasons.
First, as the LSI scale increases and the number of input and output nodes increases accordingly, naturally the number of combinations of input signals (hereinafter referred to as xe2x80x9ctest vectorsxe2x80x9d) to be prepared for an electrical circuit simulation increases. Second, as the number of output nodes of the LSI increases, the number of combinations of loads that are assumed as loads to be connected to the LSI increases. Third, as the number of transistors constituting the LSI increases, naturally the time that is taken to perform an electrical circuit simulation for each test vector becomes longer and hence an enormous amount of time becomes necessary as a whole to estimate delay times of all the necessary paths.
On the other hand, the static timing analysis can analyze a large-scale net list in a much shorter time than in the above-described dynamic timing analysis, by estimating the delay time in each path according to the delay characteristics of each unit of a circuit, called cell, and the relation between cells. For this reason, the static timing analysis has been used conventionally in such fields as designing of large-scale gate arrays.
However, for the following reasons, it is very difficult to use the static timing analysis itself as a timing analysis methodology for the transistor-level custom LSI designing.
First, to provide the degree of freedom that is necessary in the transistor-level custom LSI designing, it is necessary to construct a large-scale cell library in which a delay characteristic of each of an enormous number of kinds of transistors is registered.
Even if a cell library of such a large scale is prepared, the static timing analysis does not satisfy the accuracy as required in the transistor-level custom LSI designing as long as the static timing analysis employs a method in which the transistor is regarded as a linear resistance and an approximate delay time is determined using an RC product of the linear resistance and a load capacitance. Further, data that is registered in a cell library is just a delay characteristic that was determined in advance for a combination of several typical slew rates and output loads. Therefore, for an input slew rate and an output load that deviate from the above typical values, the accuracy of a delay characteristic obtained by the static timing analysis would be even lower.
Further, in the static timing analysis, a delay time of each path connecting an input node and an output node is estimated individually by accumulating delay times of respective cells on the path. Therefore, in principle, an obtained result does not reflect influences of traveling of signals along other paths on traveling of a signal along the subject path.
For example, consider a case of performing a delay analysis on paths from an input node Al to an output node X in a circuit that is represented by a logic circuit shown in FIG. 25. Delay time accumulation is performed indiscriminately even for cases where a signal is never transmitted actually along a path to be analyzed as in a case where truth values are inputted at both input nodes A2 and B2 or where a false value at the input node A2.
Therefore, even an invalid path along which no signal is transmitted actually is detected as a critical path when an obtained delay time is longest or shortest.
To prevent misidentifications such as an invalid path from being detected as a critical path, a method has been proposed in which critical path candidates are extracted based on delay times of respective paths obtained by the static timing analysis and an electrical circuit simulation is performed by generating test vectors for those paths.
However, determining a true critical path using the above method still requires much labor and processing time.
This is for the following reason. According to simple calculation, the number of test vectors that are necessary to determine a correct delay time for one critical path candidate is equal to the square of a number obtained by subtracting 1 from the number n of external input terminals, that is, (nxe2x88x921)2. In addition, as the number of stages of transistors along the path candidate increases, an electrical circuit simulation for each test vector comes to take longer time; the total processing time becomes very long. Naturally, the number of test vectors can be decreased by using an automatic test vector generation method. The advantage of the automatic test vector generation method may not be fully utilized in a case where the subject LSI has a complex circuit configuration containing many pass transistors and has many external input terminals.
In the conventional dynamic timing analysis, an electrical circuit simulation is performed on the entire circuit. And in the conventional static timing analysis, a subject of delay characteristic analysis is a path from an input terminal to an output terminal.
Therefore, whichever delay characteristic analyzing method is used, when the design of a custom LSI is modified, a dynamic timing analysis is performed on the entire circuit or a static timing analysis is performed on every conceivable path in the same manner as in the case of analyzing a new net list irrespective of the range where the modification has influence. It is impossible to quickly cope with a partial modification to a net list.
An object of the present invention is to provide a delay characteristic analyzing method capable of shortening the processing time while maintaining a high degree of freedom of LSI designing and high accuracy of critical path determination in transistor-level full custom LSI designing.
Another object of the invention is to provide a delay characteristic analyzing method that enables quick and precise delay characteristic analysis by utilizing a result of an analysis that was performed on a circuit before the change where there is partial modification of a net list (the circuit design or the conditions relating to signal transmission) in full custom LSI designing.
Another object of the invention is to obtain very quickly an analysis result with incomparably higher accuracy than a conventional, simple timing analysis by analyzing the dynamic delay characteristic of each circuit portion that are obtained by dividing a custom LSI including an enormous number of transistors into proper scales (hereinafter referred to as xe2x80x9ccircuit blocksxe2x80x9d) and then, by making use of the result of analysis, performing a static timing analysis on the custom LSI in such a manner as to regard it as a set of those circuit blocks.
Another object of the invention is to eliminate limitations on circuit elements included in each circuit block and thereby assure the degree of freedom of designing that is necessary for designing a full custom LSI.
Another object of the invention is to obtain a highly accurate electrical circuit simulation result by employing, in forming circuit blocks as subjects of electrical circuit simulation, conditions for combining that a circuit block should include a transistor that is connected to a power supply terminal or a ground terminal and that the number of circuit blocks having a node pair where an input signal varies simultaneously (hereinafter referred to as xe2x80x9csimultaneous-varying inputted node pairxe2x80x9d) should be minimized.
Another object of the invention is to greatly increase the accuracy of an analysis result of a dynamic timing analysis on a circuit block having a simultaneous-varying inputted node pair.
Another object of the invention is to determine a dynamic delay characteristic of a circuit block to be analyzed precisely and quickly, considering influences by downstream circuit blocks when performing an electrical circuit simulation on an expanded circuit, which is the circuit block to be analyzed added a downstream circuit block.
Still another object of the invention is to quickly obtain a highly accurate electrical circuit simulation result in performing a dynamic timing analysis on each circuit block.
Yet another object of the invention is to flexibly cope with a case that, for example, when the use of invalid input signals is found in the test vector used in electrical circuit simulations in part of the circuit blocks after construction of a delay characteristic library of the net list that is already done, a static timing analysis using dynamic delay characteristics obtained by using a new test vector which has no invalid input signals can be quickly performed.
A further object of the invention is to delay-characteristic analyze a new net list with minimum processing by effectively using an enormous amount of data obtained by delay characteristic analysis on an old net list.
According to one aspect of the invention, a read-out net list is divided into unit cells, and circuit blocks each of which is within a predetermined scale are formed by coupling of unit cells to each other according to a predetermined condition by the block forming procedure. A dynamic timing analysis is performed on each circuit block. A delay characteristic library including obtained analysis results is generated and used in a static timing analysis. By this, the transmission delay of a desired signal path is analyzed by considering the circuit to be analyzed that is indicated by the net list to be a set of the above circuit blocks.
In the above delay characteristic analyzing method, since a static timing analysis is performed based on analysis results obtained by performing a dynamic timing analysis on each circuit block, the delay characteristic of a custom LSI can be analyzed in a much shorter time than in a case where the entire, undivided net list is subjected to an electrical circuit simulation.
According to another aspect of the invention, in forming circuit blocks by coupling unit cells together, conditions are employed that a circuit block should include a transistor that is connected to a power supply terminal or a ground terminal and that a unit cell that is a factor of causing a simultaneous-varying inputted node pair such as an inverter having a particular connection should be coupled to an immediately upstream or downstream circuit block.
According to the above circuit block forming procedure, reduction in accuracy that would be caused by performing an electrical circuit simulation while handling a circuit block as an independent circuit that is separated from the entire net list can be prevented. Further, removing simultaneous-varying inputted node pairs makes it possible to obtain a correct result of an electrical circuit simulation.
According to another aspect of the invention, in forming circuit blocks by coupling unit cells together, an inverter block that is connected to an external output terminal is made a single, independent circuit block.
With this circuit block forming procedure, a problem unique to an electrical circuit simulation on a circuit block that is connected to an external output terminal can be solved, that is, increase in the number of simulations that would otherwise be caused by the necessity of performing simulations by assuming plural kinds of output loads can be prevented, whereby the time necessary for the electrical circuit simulation can be shortened.
According to another aspect of the invention, in a dynamic timing analyzing procedure, in a case where circuit blocks are selected as subjects to be analyzed in order from the circuit block closest to an external input terminal and a circuit block concerned has a simultaneous-varying inputted node pair, its phase difference is estimated by performing a static timing analysis, a test vector that reflects the estimated value is generated, and the generated test vector is applied to an electrical circuit simulation.
In this dynamic timing analyzing procedure, a phase difference that occurs when each input signal reaches simultaneous-varying inputted node pair is estimated with very high accuracy and an electrical circuit simulation on the circuit block concerned is performed by using the estimated value. Therefore, a highly accurate analysis result can be obtained even for a circuit block having a simultaneous-varying inputted node pair.
According to another aspect of the invention, in a dynamic timing analyzing procedure, an average value or an expected value of a phase difference obtained by a statistical method or a value that is input by a user is used in an electrical circuit simulation as a phase difference that occurs when each input signal reaches simultaneous-varying inputted nodes.
This dynamic timing analyzing procedure makes it possible to make much shorter the time necessary for preprocessing of an electrical circuit simulation than in a case of using an estimated value obtained by a static timing analysis.
According to another aspect of the invention, in a dynamic timing analyzing procedure, prior to an electrical circuit simulation on each circuit block, a maximum loading simulation vector and a minimum loading simulation vector are determined for each of downstream circuit blocks that are connected to the circuit block concerned. When an electrical circuit simulation is performed on an expanded circuit including the circuit block to be analyzed and its downstream circuit blocks, the maximum loading simulation vectors or minimum loading simulation vectors are applied to the respective downstream circuit blocks.
This dynamic timing analyzing procedure makes it possible to quickly determine a delay characteristic of a circuit block to be analyzed while taking into account influences of downstream circuit blocks connected to it.
According to still another aspect of the invention, in a dynamic timing analyzing procedure, an electrical circuit simulation is performed on a circuit block to be analyzed in which the circuit blocks to be analyzed are selected in order from the circuit block closest to an external input terminal and approximated waveforms obtained by dynamic timing analyses on upstream circuit blocks are used as input signal waveforms to perform circuit simulation on the circuit block to be analyzed. Approximated waveforms that reflect features of output signals of the circuit block to be analyzed are generated and used for an electrical circuit simulation on a downstream circuit block.
In this dynamic timing analyzing procedure, dynamic timing analyses on respective circuit blocks can be performed under conditions that provides an environment that is very close to an environment that each circuit block is connected to upstream circuit blocks, though the dynamic timing analyses are independent from each other. Therefore, a highly accurate analysis result can be obtained for each circuit block.
According to a yet another aspect of the invention, in a delay characteristic analyzing method, after a delay characteristic library is generated, an electrical circuit simulation is retried on a specified circuit block by excluding a specified vector. If there is a non-negligible variation from a result of a previous electrical circuit simulation, a dynamic timing analysis is retried on each circuit block included in a range that is influenced by an output signal of the specified circuit block. A delay characteristic library is reconstructed based on obtained analysis results.
This delay characteristic analyzing method makes it possible to perform reconstruction of a delay characteristic library only in a range that is influenced by variation of the dynamic delay characteristic of a specified circuit block.
According to a further aspect of the invention, for each of circuit blocks that have been formed for a newly read net list, it is judged whether the delay characteristic obtained for a circuit block constituting the delay-characteristic analyzed net list is usable. If it is reusable, the existing delay characteristic is used. In the case of a new circuit block, a dynamic timing analysis is performed on the circuit block concerned and a delay characteristic indicated by an analysis result is registered in a delay characteristic library.
According to this delay characteristic analyzing method, in a case where delay characteristic analysis is performed on a new net list obtained by changing part of a delay-characteristic analyzed net list, the entire new net list can be delay-characteristic analyzed by only considering a small number of new circuit blocks and dynamic timing analyses are performed on only those circuit blocks.