The present invention relates to multilayer parallel plate capacitors with extremely low inductance.
Multilayer parallel plate capacitors find ubiquitous use in electronics for filters, decoupling of high speed circuitry and integrated circuits (IC's), and energy storage. However, these capacitors, whether made of multilayer ceramic, multilayer laminate, thick or thin-film metallization, or other materials, are limited in the frequency range of their usefulness due to inductive effects associated with their structure. Since charging and discharging of a capacitor involves the flow of electrons through the conductor plates, the resulting current gives rise to an effective inductance, L, called the Equivalent Series Inductance (ESL), which is dependent on the geometry of the conductor plates and the direction of the current through the plates. This inductance limits the useful frequency range of a capacitor with capacitance C to a frequency less than a resonance frequency, Fr:Fr=1/2π√LC. 
Rapid increases in clock speeds of microprocessors, digital signal processors and other IC's are driving the need for faster filtering and decoupling, i.e., capacitive devices with lower inductance, L, and therefore higher Fr.
For capacitors used as energy storage devices in the output of power supplies for high-speed IC's, this inductance gives rise to a switching noise voltage, ΔV:ΔV˜Ldi/dt,
where di/dt is the rate of change of the current drawn by the IC. The magnitude of di/dt increases with increasing transistor count and increasing clock speed. This is driving the need for high-capacitance energy storage capacitors with lower inductance, L, in order to keep the noise voltage, ΔV, to acceptable levels, particularly as supply voltages decrease. It is clear that there is a need for capacitors whose structure allows for a lower inductance than capacitors of the prior art, while retaining the same level of capacitance.
Conventional multilayer parallel plate capacitors typically comprise a structure in the form of a rectangular parallelepiped that includes several pairs of rectangular composite layers stacked vertically in a parallel configuration, each composite layer of a pair comprising a dielectric substrate and a conductor plate thereon. Plates on consecutive composite layers are connected to terminal electrodes of opposite polarity. FIGS. 1A and 1B show two rectangular composite layers 10A and 10B that comprise a pair of consecutive composite layers of a conventional multilayer capacitor. Composite layer 10A comprises a dielectric substrate 11A and a conductor plate 12A. The conductor plate 12A includes a main portion 13A and a lead portion 14A extending to an edge of the substrate to enable connection to an external terminal electrode. Consecutive composite layer 10B comprises a dielectric substrate 11B and a conductor plate 12B. Plate 12B includes a main portion 13B and a lead portion 14B. Each main plate portion 13A and 13B has a longitudinal dimension Dx and a transverse dimension Dy.
With reference to the coordinate system shown in FIGS. 1A and 1B, the longitudinal dimension Dx is along the x-axis, and the transverse dimension Dy is along the y-axis. Generally, Dx is greater than Dy. For a given thickness of the dielectric substrates 11A and 11B, and for a given dielectric constant, the capacitance of the structure is proportional to the area of the plates, A=D×Dy. The lead portions 14A and 14B are disposed along the transverse dimension, or y-axis. When a positive potential is applied to plate 12A, and a corresponding negative potential is applied to plate 12B, the charging process gives rise to electron currents through the plates in the x-direction, as shown by the arrows 15A and 15B.
The inductance, L, associated with this structure is a combination of the self inductance, Ls, of each plate, and the mutual inductance, M, between the plates. Since the currents flow in the x-direction, the self inductance is that of a conductor of length Dx. Further, since the current in each of the plates flows in the same direction, the mutual inductance is additive in nature. Thus the inductance of the structure is given by:L˜Ls+M.
Typically, the inductance of such conventional parallel plate capacitors, made with multilayer ceramic, is in the range of 1000 pH.
Prior art techniques aimed at reducing the inductance of multilayer parallel plate capacitors have taken two main approaches: (i) reducing Ls and M concurrently by reducing the length of the plates in the direction of current flow; and (ii) arranging for the currents through plates in consecutive composite layers to flow in opposite directions, thereby rendering the mutual inductance between the plates to be subtractive in nature.
The first approach is illustrated in FIGS. 2A and 2B, which show two rectangular composite layers 20A and 20B that comprise a pair of consecutive composite layers of a low inductance multilayer capacitor of the prior art. Composite layers 20A and 20B comprise dielectric substrates 21A and 21B and conductor plates 22A and 22B respectively. Plates 22A and 22B each include main portions 23A and 23B and lead portions 24A and 24B respectively. Like the conventional multilayer capacitor of FIGS. 1A and 1B, the main plate portions have dimensions of Dx and Dy along the x and y-axes. The area of the plates, and hence the capacitance, is the same. Unlike the capacitor of FIGS. 1A and 1B, the lead portions 24A and 24B are disposed along the longitudinal dimension, or x-axis. When a positive potential is applied to plate 22A, and a corresponding negative potential is applied to plate 22B, the charging process leads to electron currents through the plates in the y-direction, as shown by the arrows 25A and 25B. Since the inductance of a conductor of length l is given by:L˜l(ln l),
and the length of the plates, Dy, in the y-direction, is less than that, Dx, in the x-direction, both Ls and M, and hence the inductance L, are lower than the conventional multilayer capacitor. However, this approach, although it has resulted in inductance reductions to the 500 pH level for multilayer ceramic capacitors, is limited by practical constraints of minimizing Dy while retaining the plate area DxDy.
Examples of the second approach are disclosed, recently, in U.S. Pat. Nos. 5,880,925, 6,243,253B1, and 6,795,294B2, and previously, in U.S. Pat. Nos. 4,419,714, 4,430,690, and 5,369,545. This approach is illustrated in FIGS. 3A and 3B, which show two rectangular composite layers 30A and 30B that comprise a pair of consecutive composite layers of a low inductance multilayer capacitor of the prior art. Composite layers 30A and 30B comprise dielectric substrates 31A and 31B, and conductor plates 32A and 32B respectively. Plates 32A and 32B each include main portions 33A and 33B respectively, each with longitudinal dimension Dx along the x-axis, and transverse dimension Dy along the y-axis, with reference to the coordinate system shown. Plate 32A additionally includes at least one, and typically two or more, lead portions 34A disposed along one of the longitudinal edges of the plate, and at least one, and typically two or more, lead portions 35A disposed along the opposed longitudinal edge.
Plate 32B additionally includes at least one, and typically two or more, lead portions 34B and 35B disposed along each of the corresponding longitudinal edges of the plate. The lead portions 34A and 34B are positioned such that they are offset from each other in an alternating pattern when the composite layers are stacked vertically. The lead portions 35A and 35B are positioned in a similar fashion. Each of the lead portions 34A and 34B, and 35A and 35B, extend to the corresponding longitudinal edge of the substrates 31A and 31B to enable connection to external terminal electrodes. As shown, the multilayer capacitor of FIGS. 3A and 3B is an 8 terminal device, with 4 terminal electrodes along each longitudinal edge, alternating in polarity. When a positive potential is applied to plate 32A, and a corresponding negative potential is applied to plate 32B, the charging process leads to electron currents through the plates in the directions shown by the arrows 36A and 36B. Since each plate has terminations on opposing longitudinal edges, roughly half the current in each plate traverses a length that is roughly half of Dy, depending on the symmetry of the external circuitry connected to these opposing terminations. This leads to a decrease in both Ls and M. Further, the currents in plate 32A are roughly opposed in directions to the currents in plate 32B. The mutual inductance between the plates is thus subtractive in nature, and the inductance of the structure is:L˜Ls−M.
Although this inductance is generally lower than that of the capacitor of FIGS. 2A and 2B, the effectiveness of this approach is limited by the extent to which the magnitude of the mutual inductance M can be made to match the self inductance Ls. This is determined by the degree to which the currents in the consecutive plates are opposite to each other, in both magnitude and direction, over the expanse of the plates, i.e., by the degree to which the currents in any section of one plate are matched by equal and opposite currents in the corresponding section of the other plate. As shown by the arrows 36A and 36B, this matching of the currents in plates 32A and 32B is only partial. Although the matching can theoretically be improved by greatly increasing the number of terminations along each edge, practical considerations put a limit on the number of terminations in a viable device. Thus, this approach has resulted in inductance reductions only to the 100 pH level for multilayer ceramic capacitors.
Further examples of the second approach, in the case of multilayer capacitors with single-sided terminations, are disclosed in U.S. Pat. Nos. 4,419,714, 4,430,690, and 5,369,545, and discussed in U.S. Pat. Nos. 5,880,925, 6,243,253 B1, and 6,795,294 B2. This approach is illustrated in FIGS. 4A and 4B, which show two rectangular composite layers 330A and 330B that comprise a pair of consecutive composite layers of a low inductance multilayer capacitor of the prior art. Composite layers 330A and 330B comprise dielectric substrates 331A and 331B, and conductor plates 332A and 332B respectively. Plates 332A and 332B each include main portions 333A and 333B respectively, each with longitudinal dimension Dx along the x-axis, and transverse dimension Dy along the y-axis, with reference to the coordinate system shown. Plate 332A additionally includes at least one, and typically two or more, lead portions 334A disposed along one of the longitudinal edges of the plate.
Plate 332B additionally includes at least one, and typically two or more, lead portions 334B disposed along one of the longitudinal edges of the plate. The lead portions 334A and 334B are positioned such that they are along the same longitudinal edge and are offset from each other in an alternating pattern when the composite layers are stacked vertically. Each of the lead portions 334A and 334B extend to the longitudinal edge of the substrates 331A and 331B to enable connection to external terminal electrodes.
As shown, the multilayer capacitor of FIGS. 4A and 4B has four terminal electrodes, positioned along a longitudinal edge, and alternating in polarity. When a positive potential is applied to plate 332A, and a corresponding negative potential is applied to plate 332B, the charging process leads to electron currents through the plates in the directions shown by the arrows 335A and 335B. The currents in plate 332A are roughly opposed in directions to the currents in plate 332B. The mutual inductance between the plates is thus subtractive in nature, and the inductance of the structure is:L˜Ls−M.
Although this inductance is generally lower than that of the capacitor of FIGS. 2A and 2B, the effectiveness of this approach is limited by the extent to which the magnitude of the mutual inductance M can be made to match the self inductance Ls. This is determined by the degree to which the currents in the consecutive plates are opposite to each other, in both magnitude and direction, over the expanse of the plates, i.e., by the degree to which the currents in any section of one plate are matched by equal and opposite currents in the corresponding section of the other plate. As shown by the arrows 335A and 335B, this matching of the currents in plates 332A and 332B is only partial. Although the matching can theoretically be improved by greatly increasing the number of terminations, practical considerations put a limit on the number of terminations in a viable device. Thus, this approach has resulted in inductance reductions only to the 100 pH level for multilayer ceramic capacitors.
A third approach aimed at reducing the inductance of multilayer capacitors, as disclosed in U.S. Patent Application Publication Nos. US 2004/0179325 A1 and US 2004/0184202 A1, arranges for the currents through the plates on a composite layer to flow in opposite adjacent directions within the layer, as well as in opposite directions with respect to a consecutive composite layer. Shaping of the conductor plate on a composite layer to enable current flow in opposite adjacent directions within the layer results in more than doubling the length of the plate. The concomitant increase in the self inductance, Ls, of the plate places a greater reliance on the subtractive effect of the mutual inductance, M, between plates on consecutive layers in order to reduce the overall inductance, L, of the structure. This has limited the effectiveness of this approach to inductance reductions to the level of 100 pH for multilayer ceramic capacitors.
The disclosures of the foregoing U.S. Pat. Nos. 4,419,714, 4,430,690, 5,369,545, 5,880,925, 6,243,253 B1, and 6,795,294 B2, and U.S. Patent Application Publication Nos. 2004/0179325 A1 and 2004/0184202 A1, are each hereby incorporated into this application by reference.