The concept “system LSI” of a plurality of large-scale integrated circuits (LSIs) on a common substrate has recently been brought in and various methods of designing system LSIs have also been proposed. System LSIs in particular have the advantage of being realized as a wide variety of multifunctional semiconductor devices on an extremely large scale of integration in such a manner that a memory such as a dynamic random access memory (DRAM), a logic LSI, an analog circuit such as a high-frequency circuit, etc., are mounted in one semiconductor device.
As a method for testing each of such LSIs to determine whether the LSI is correctly formed, a built-in self-test (BIST), a scan test and a boundary scan test, for example, are known.
FIG. 24 is a block diagram for explaining a conventional ordinary built-in self-test (BIST). As shown in FIG. 24, a pattern generator for generating a test pattern, a result compressor and a control circuit are provided as BIST means in an LSI. The control circuit makes the test pattern generator generate a test pattern in response to a start signal and input the generated test pattern to a logic circuit which is a test object (DUT), and make the result compressor obtain a testing signal output from the test object and output the testing signal out of the LSI. An external instrument (tester) determines whether the test object logic circuit is operating normally. According to this testing method, a test can be automatically made without generating a pattern in a tester. This method has the advantage of using a smaller number of pins and imposing only an extremely small load on the tester.
FIG. 25 is a block diagram schematically showing an ordinary boundary scan test circuit. As shown in FIG. 25, the boundary scan test circuit has a scan chain formed by successively connecting flip flops (FFs) attached to external terminals of an LSI from an input test terminal (TDI) to an output test terminal (TDO). A test pattern is input to the scan chain to enable use of the boundary scan test circuit for determination as to whether connections between one LSI-A and an adjacent LSI-B are correctly made.
FIG. 26 is a block diagram showing an example of a configuration of a scan chain used in an ordinary scan test. Ordinarily, in a scan-in method, a scan chain test pattern is externally supplied and data output from a test object is immediately output from the test chain. That is, in ordinary cases of scan tests of internal circuits, no test pattern generator and no result compressor exist in the configuration shown in FIG. 24. However, scan-in may be used as a means for realizing a BIST.
FIG. 27 is a block diagram showing an example of a configuration of a flip flop provided in a boundary test circuit or a scan chain for a scan test of internal circuits.
The above-described conventional system LSIs are confronted with problems described below in actually forming devices.
The first problem resides in difficulty in reducing the device manufacturing cost. This is due to a high cost of development of system LSIs and a limited manufacturing yield.
The second problem resides in a considerable increase in wiring delay. In general, the height of devices is reduced in accordance with a shrinkage rule. With the reduction in sectional area of pieces of wiring, the wiring delay determined by RC (R is a resistance, and C is a parasitic capacitance) is increased. That is, as regards the wiring delay, the disadvantage of a design by a finer rule prevails over the advantage of the same. As a means for solving this problem, a buffer may be provided in wiring. However, if a buffer is provided, another problem arises in that the area occupied by a device and the power consumption of the device are increased.
The third problem resides in difficulty in reducing noise. If the power supply voltage is reduced, the current is increased and it is difficult to limit the increase in noise level corresponding to the increase in current. The S/N ratio becomes lower in proportion to the third to sixth power of the shrinkage rate. Thus, an increase in noise cannot be avoided when a finer design rule is used. That is, the point is how the power supply impedance is limited.
It is conceivable that a semiconductor device suitable for reduced-variety mass production is realized by mounting chip intellectual properties (IP) which are formed as integrated circuits by a plurality of various devices on a semiconductor wiring substrate having a wiring layer, e.g., a silicon wiring substrate. The chip IPs can be used as a means for realizing a semiconductor device incorporating multiple kinds of semiconductor devices having multiple functions while maintaining a large wiring piece sectional area.
However, there are no established means for mounting such chip IPs on a wiring substrate and for inspecting LSIs in the chip IPs. As mentioned above, the BIST method, the scan test method and the boundary scan test are known as conventional test methods. However, in a case where one of these test methods is used for testing of an IP On Super-Sub (IPOS) device, it has the drawback of requiring a considerably long test time if each of LSIs in chip IPs is separately tested after mounting of the chip IPs, and the drawback of being incapable of determination of defective/nondefective condition of wiring since there are no devices for receiving a signal on the wiring substrate before the chip IPs are provided.