This invention relates to charge pump circuits, and more particularly relates to charge pump circuits capable of high voltage operation.
The charge pump is a type of DC-DC voltage converter circuit that uses capacitors to store and transfer energy, typically in order to generate a higher voltage than that supplied to the circuit. They are used in a variety of applications. They are commonly used, for example, to generate the higher voltages required for the writing and erasing operations of non-volatile memories such as flash memories. They are also used to achieve higher gate drive voltages (Vgs) on MOSFETs to obtain a lower resistance from drain-to-source while the device is on (Rdson) for a same size device. They are also used as a supply in low voltage applications. The foregoing list of applications is not exhaustive.
A charge pump is typically constructed in a series of stages that step up the voltage created by the charge stored in one stage to a higher voltage in the next. FIG. 1 is a circuit diagram of an exemplary prior art two-phase charge pump circuit 10. The circuit includes metal oxide semiconductor field effect transistors (xe2x80x9cMOSFETs,xe2x80x9d or, simply xe2x80x9cFETsxe2x80x9d) T1-T12, capacitors C1-C6, and an inverter, connected as shown. The circuit has three identical stages 14, 15, 16, each stage including four FETs (T1-T4, T5-T8 and T9-T12, respectively), and two capacitors (C1 and C2, C3 and C4 and C5 and C6, respectively), connected as shown. A high voltage VH is provided to the first stage 14, while a square wave clock signal CLK is provided to one side of all stages, and its inverse, generated by inverter 12, is provided to the other side of all stages, as shown.
Each stage operates in similar manner, with increasing voltage being provided successively at the output of each stage, in a manner well known in the art. Thus, in successive half cycles of CLK, FETs T1-T12 operate in complementary fashion to pump charge onto the plates of capacitors C1-C6, creating a voltage across the capacitors, and then to use that voltage, which is raised during the transfer cycle by the voltage of the clock signal, to elevate the voltage across a capacitor in a next stage that is on the same side of the circuit by that voltage, less the threshold voltage of a connecting FET. The last stage provides an output voltage VOUT.
However, as the voltage generated by each stage increases, the threshold voltages of the transferring FETs can increase, due to the well-known backgating effect. This causes a successively lower voltage increase from one stage to the next. In fact, the threshold voltage of a transferring FET can become the same as the voltages of the clock signals driving the pump, at which point no further boosting is possible. To avoid this, in the charge pump circuit 10 the backgate is tied to the source on each FET, as shown. Thus, Vsb=0. This requires isolation of the circuit.
In addition, there is a significant challenge in designing a charge pump that can work over a large voltage range. One reason for this is that the charge pump voltage is usually referenced to the supply in some way, and as the supply voltage increases so too does VOUT. However, the capacitors are typically diffusion capacitors, which have a specific voltage tolerance. When the clock signal switches from the supply voltage in its high phase to a low voltage in its low phase, the voltage tolerance of a capacitor can be exceeded, causing breakdown of the capacitor. Thus, in designing a high voltage charge pump that can work over a very wide supply range, one must solve the problem of how to clock it, but not exceed the voltage tolerance of the capacitors.
U.S. Pat. No. 6,157,242, which issued on Dec. 5, 2000, to Haruyasu Fukui, et al., and was assigned to Sharp Kabushiki Kaisha, proposes a charge pump circuit arrangement to allow operation at a wide range of power supply voltages. In their scheme, normal clock signals are provided to early stages of a charge pump, but in order to overcome the problem associated with increasing transferring FET threshold voltage, and thus allow a higher output voltage to be generated, a clock signal boost circuit is provided for boosting voltages of the clock signals of later stages. In order to address the problem of having the charge pump work over a very wide range and still stay within the tolerances of the capacitors, they propose having their clock boosting capable of being enabled and disabled. For lower supply voltages, clock boosting would be enabled, while for higher supply voltages clock boosting would be disabled, to protect the capacitors against breakdown. However, this proposed solution provides a limited output voltage.
Another prior art solution, shown in FIG. 2, utilizes a conventional ring oscillator 17, with transfer circuitry 17a providing the oscillator signal to high voltage level shifters 18 to raise both the high and low voltage levels of the clock signals CLK and {overscore (CLK)}, in order to provide a higher output voltage, and using high voltage components in the charge pump (not shown). In this solution, high voltage references VH1 and VH2 are referenced linearly to supply, and provided to the level shifters, as shown. For example, VH1 could be at supply voltage, Vsupply, such as 5 volts, and VH2 at some specified voltage below Vsupply, with both rising and falling with Vsupply, but holding the difference in their voltages to close tolerance. While this solution does not limit the output voltage, as in the arrangement disclosed in U.S. Pat. No. 6,157,242, it does require a relatively large integrated circuit area to implement, as it requires the additional area for the level shifters, and for high voltage components used in the design. In addition, the approach shown in FIG. 2 is limited in clocking frequency because of the high voltage level shifters 18. The FET devices in that circuit are, of necessity, large and have high intrinsic capacitance, and so do not switch rapidly.
In accordance with the present invention there is provided a high voltage integrated circuit operable in a system having a low voltage reference, a high voltage reference, and a ground, for providing an output voltage higher than the high voltage reference. The integrated circuit includes a high voltage ground reference circuit, operable to provide a high voltage ground reference node. Also included is an oscillator, operable to provide a clock signal, the oscillator being connected to the high voltage reference and to the high voltage ground reference node. An isolated charge pump circuit is provided, operable to generate the output voltage and isolated in the integrated circuit from other circuitry.
These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.