1. Field of the Invention
The present invention relates generally to processes and methods for forming electronic devices and the like. More particularly, the present invention pertains to methods and apparatus for effecting the creation of via holes in semiconductors and other thin substrates and, more specifically, to methods and apparatus for forming insulative coatings of via holes. The present invention also pertains to the use of stereolithography techniques to form insulative coatings with small diameter via holes extending therethrough.
2. Background of Related Art
Over the past decade or so, a manufacturing technique which has become known as “stereolithography” and which is also known as “layered manufacturing” has evolved to a degree where it is employed in many industries.
Basically, stereolithography, as conventionally practiced, involves utilizing a computer, typically under control of three-dimensional (3-D) computer-aided design (CAD) software, to generate a 3-D mathematical simulation or model of an object to be fabricated. The computer mathematically separates or “slices” the simulation or model into a large number of relatively thin, parallel, usually vertically superimposed layers. Each layer has defined boundaries and other features that correspond to a substantially planar section of the simulation or model and, thus, of the actual object to be fabricated. A complete assembly or stack of all of the layers defines the entire simulation or model. A simulation or model which has been manipulated in this manner is typically stored and, thus, embodied as a CAD computer file. The simulation or model is then employed to fabricate an actual physical object by building the object, layer by superimposed layer. Surface resolution of the fabricated object is, in part, dependent upon the thickness of the layers.
A wide variety of approaches to stereolithography by different companies has resulted in techniques for fabricating objects from various types of materials. Regardless of the material employed to fabricate an object, stereolithographic techniques usually involve disposition of a layer of unconsolidated or unfixed material corresponding to each layer of the simulation or model. Next, the material of a layer is selectively consolidated or fixed to at least a partially consolidated, partially fixed, or semisolid state in those areas of a given layer that correspond to solid areas of the corresponding section of the simulation or model. Also, while the material of a layer is being consolidated or fixed, that layer may be bonded to a lower layer of the object which is being fabricated.
The unconsolidated material employed to build an object may be supplied in particulate or liquid form. The material may itself be consolidated or fixed. Alternatively, when the unconsolidated material comprises particles, a separate binder material mixed therein or coating the particles may facilitate bonding of the particles to one another, as well as to the particles of a previously formed layer.
Surface resolution of the features of a fabricated object depends, at least in part, upon the material being used. For example, when particulate materials are employed, resolution of object surfaces is highly dependent upon particle size, whereas when a liquid is employed, surface resolution is highly dependent upon the minimum surface area of the liquid which can be consolidated or fixed and the minimum thickness of a material layer that can be generated. Of course, in either case, resolution and accuracy of the features of an object being produced from the simulation or model is also dependent upon the ability of the apparatus used to consolidate or fix the material to precisely track the mathematical instructions indicating solid areas and boundaries for each layer of material.
Toward that end, and depending upon the type and form of material to be fixed, stereolithographic fabrication processes have employed various fixation approaches. For example, particles have been selectively consolidated by particle bombardment (e.g., with electron beams), disposition of a binder or other fixative in a manner similar to ink-jet printing techniques, and focused irradiation using heat or specific wavelength ranges. In some instances, thin, preformed sheets of material may be superimposed to build an object, each sheet being fixed to a next lower sheet and unwanted portions of each sheet removed, a stack of such sheets defining the completed object.
Early on in its development, stereolithography was used to rapidly fabricate prototypes of objects from CAD files. Prototypes of objects might be built to verify the accuracy of the CAD file defining the object (e.g., an object or negative of a mold to be machined) and to detect any design deficiencies and possible fabrication problems before a design was committed to large-scale production. Stereolithographic techniques have also been used in the fabrication of molds. Using stereolithographic techniques, either male or female forms on which mold material might be disposed could be rapidly generated.
In more recent years, stereolithography has been employed to develop and refine object designs in relatively inexpensive materials. Stereolithography has also been used to fabricate small quantities of objects for which the cost of conventional fabrication techniques is prohibitive, such as in the case of plastic objects that have conventionally been formed by injection molding techniques. It is also known to employ stereolithography in the custom fabrication of products generally built in small quantities or where a product design is rendered only once. Finally, it has been appreciated in some industries that stereolithography provides a capability to fabricate products, such as those including closed interior chambers or convoluted passageways, which cannot be fabricated satisfactorily using conventional manufacturing techniques. It has also been recognized in some industries that a stereolithographic object or component may be formed or built around another, pre-existing object or component to create a larger product.
Conventionally, stereolithographic apparatus have been used to fabricate freestanding structures. Such structures have been formed directly on a platen or other support system of the stereolithographic fabrication apparatus, which is located within the fabrication tank of the stereolithographic apparatus. As the freestanding structures are fabricated directly on the support system, there is typically no need to precisely and accurately position features of the stereolithographically fabricated structure. As such, conventional stereolithographic apparatus lack machine vision systems for ensuring that structures are fabricated at certain locations.
Moreover, conventional stereolithographic apparatus lack support systems, handling systems, and cleaning equipment which are suitable for use with relatively delicate structures, such as semiconductor substrates and semiconductor devices that have been fabricated thereon.
Recently, improved stereolithographic apparatus have been configured to form structures on fabrication substrates, such as semiconductor substrates and semiconductor device components, and include systems for accurately positioning the fabricated structures, supporting and handling the fabrication substrates, and cleaning excess and residual material from the fabrication substrates.
In the construction of semiconductor devices and the like, apertures may be formed into or through the object for various reasons. For example, apertures known as “via holes” may be formed in various components of an electronic device for the purpose of forming electrical conductors, or “vias,” that extend within the aperture, typically in a direction which is generally perpendicular to a plane in which a surface of the component is located. Where the component itself is electrically conductive, the via must be insulated from the component to avoid short-circuiting. In state-of-the-art semiconductor devices, the vias are formed to have a very small diameter, generally about 17 μm to about 150 μm. In some cases, the via hole length is significantly greater than the diameter thereof, whereby the hole is said to have a high aspect ratio. While higher circuit densities are possible where the via hole diameter is very small, suitably filling high aspect ratio via holes with a conductive metal is difficult.
Where a via is to be formed in a semiconductive material, such as silicon, gallium arsenide, or indium phosphide, or a conductive material, such as a metal, a first or precursor hole is typically formed by a so-called “trepan” process, whereby a very small bit of a router or drill, a laser beam or other energy beam, or the like is moved in circular paths of increased distance to create the precursor hole. The precursor hole is larger in diameter than the desired completed via to be formed. Following precursor hole formation, a thin silicon oxide or other insulating layer is formed on the inner surface of the hole by exposure of the inner surface to an oxidizing atmosphere. When a polymeric insulative coating is desired, a thin oxide layer may be formed prior to vapor depositing a suitable polymer, such as parylene resin, over the substrate and within each precursor hole. Oxidation or adhesion promotion of the inner surfaces of the precursor hole is required because adhesion of polymer directly to silicon is relatively poor compared to adhesion to an oxide or adhesion promoter. A negative pressure (e.g., a vacuum) may be applied to an end of each precursor hole to draw the polymer therein. The polymer is then cured or otherwise hardened or permitted to harden. Next, a small via hole of desired diameter is drilled (e.g., by percussion drill or continuous laser) or otherwise formed in the hardened polymer. The via hole is then filled with a conductive material, such as conductively doped polysilicon, a metal, a metal alloy, or a conductive or conductor-filled elastomer, to form a via that provides a conductive path through the via hole, which conductive path may extend between opposed surfaces of the substrate. The polymer insulates the conductive via from the substrate.
The steps taken in the prior art to form a via in a semiconductive or conductive substrate are depicted in the flowchart of FIG. 1. A substrate, such as a full or partial silicon wafer, is subjected to a first hole-forming process, at reference character 10. The first hole-forming process may be effected by a laser, drill, or router in a so-called “trepan” process, in which a bit of the drill or router is rotated and moved laterally along a plurality of circular paths of increasing diameter to form a precursor hole of a desired diameter, which is greater than the desired diameter for the final via hole. The substrate is then cleaned to remove any debris, as indicated at reference character 11.
Next, as shown at reference character 12, the substrate is then exposed to a passivating (e.g., oxidizing or nitridating) atmosphere to passivate the inner surfaces of the precursor hole. For example, silicon may be oxidized to form silicon dioxide, nitridated to form a silicon nitride, or otherwise passivated to form a silicon oxynitride, all as known in the art. Passivation is useful for providing an adhesion base for an insulative polymer since the adhesion of many polymers to various materials, including unoxidized silicon, may be poor.
Next, at reference character 14, an insulative resin polymer is deposited in the precursor hole, such as by a chemical vapor deposition (CVD) technique or in a dissolved, atomized form. A pressure may be required to force the polymer into the precursor hole. Typically, the precursor hole is completely filled with polymer. In addition, the polymeric resin forms a coating over the exposed major surfaces of the substrate, from which it must be cleaned.
The substrate is then subjected to thermal curing, as indicated at reference character 16, to cure and, thus, solidify the polymer within the precursor hole. Then, at reference character 18, the substrate surfaces are cleaned of polymer. In addition, the chamber in which the insulative coating is formed (e.g., a CVD chamber) requires cleaning of polymer and polymer condensation products from its interior surfaces. At reference character 20, a final via hole is formed through the hardened polymer by a small diameter drill such as a laser drill.
After cleaning debris from the substrate following the drilling process, as indicated at reference character 21, the final via hole is filled with a conductive material, as shown at reference character 22. The conductive material forms the conductive via between opposite surfaces of the substrate.
When the substrate in which the via hole and via are formed comprises a different type of material, such as the resin of a printed circuit board (PCB), for example, the surface oxidation step may not be required to increase adhesion of the via hole-lining polymer to the surface of the via hole.
Inasmuch as most semiconductor devices are formed as part of a multicomponent substrate, it is advantageous to form vias in such devices prior to separation (e.g., by use of a singulation saw) of the devices from the wafer.
Current methods of forming vias in conductive or semiconductive materials are time-consuming, are cumbersome, and waste resin. Thus, application and curing of the parylene resin or other nonconductive polymer creates a solid layer over the entire substrate, and the walls and other surfaces within the application chamber become covered with the polymer and pyrolysis products thereof. Thus, the substrate and the chamber require extensive cleaning.
Moreover, parylene resin is relatively expensive. Nonetheless, a majority of the applied parylene resin is not applied to the surfaces of the via holes, where application is actually desired, but is deposited onto surfaces from which it will subsequently be removed, then discarded.
Accordingly, there is a need for an improved method for lining the surfaces of via holes with electrically insulative materials, particularly via holes that have been formed in substrates which comprise semiconductive or conductive materials.