Many systems require digital processing even when the input and/or output signals are analog signals. This is often the case, for example, in the context of conventional speed or transmission (e.g., engine transmission) sensing systems. In at least some such conventional sensing systems, speed is sensed by detecting zero crossings of a magnetic field that occur as magnetic teeth on a wheel rotate past a magnetic sensor (e.g., a Hall sensor, an anisotropic magnetoresistance (AMR) sensor, a tunnel magnetoresistance (TMR) sensor, or a giant magnetoresistance (GMR) sensor) and induce change(s) in the output voltage of the magnetic sensor. In such embodiments, after each zero crossing, the supply current of the sensor is set to a new level. Additionally, in such embodiments, all calculations on the incoming signal are performed digitally, so the supply current can only change after an edge of the internal clock signal. This limits the accuracy of the zero-crossing detection, and the quantization in the time domain adds to the overall jitter of the system.
Referring to FIG. 1, a first graph 100, second graph 102, and third graph 104 collectively illustrate how variations in the timing of a clock signal relative to the timing of an input signal 106 can result in significantly different output signals and corresponding jitter. More particularly, the first graph 100, second graph 102, and third graph 104 respectively illustrate a first clock signal 108, second clock signal 110, and third clock signal 112, respectively. Although the first, second, and third clock signals 108, 110, and 112 share in common the same frequency, the three clock signals are slightly out of phase relative to one another. Consequently, as shown in the first, second, and third graphs 100, 102, and 104, the first, second, and third clock signals 108, 110, and 112 respectively have first, second, and third values 114, 116, and 118, respectively that differ from one another at a time 120 at which the input signal 106 crosses zero occurs. More particularly, the first value 114 of the first clock signal 108 is a minimum value of that clock signal at the time 120, the third value 118 of the third clock signal 112 is a maximum value of that clock signal at the time 120, and the second value 116 of the second clock signal 110 is a transitional (downward edge) value of that clock signal at the time 120 that can be considered to be in between (e.g., a zero value) of the second clock signal 110.
Because of this variation in the relative timing of the first, second, and third clock signals 108, 110, and 112 relative to one another and relative to the input signal 106, as further illustrated in FIG. 1 virtual phase error is introduced into output signals generated based upon the interplay of the input signal 106 and the clock signals 108, 110, and 112. More particularly, in the first graph 100, it can be seen that a first output signal 122 is step-shaped and includes a series of steps 124 that are each of equal height and width relative to the preceding step, that a first step 126 of the series of steps 124 occurs a first time differential 128 after the time 120, and that the series of steps has an effective slope represented by a dashed line 130. By comparison, in the second graph 102, it can be seen that a second output signal 132 also is step-shaped and includes a series of steps 134 that are each of equal height and width relative to the preceding step, that a first step 136 of the series of steps 134 occurs a second time differential 138 after the time 120, and that the series of steps has an effective slope represented by a dashed line 140. Additionally by comparison, in the third graph 104, it can be seen that a third output signal 142 also is step-shaped and includes a series of steps 144 that are each of equal height and width relative to the preceding step, that a first step 146 of the series of steps 144 occurs a third time differential 148 after the time 120, and that the series of steps has an effective slope represented by a dashed line 150.
In view of these considerations, as further illustrated in FIG. 1, the first, second, and third output signals 122, 132, and 142 are not in phase within one another even though the three output signals are all generated based upon the same input signal, namely, the input signal 106. More particularly, it can be seen from the first graph 100 that a first virtual starting point 152 of the first output signal 122, namely, the point at which the dashed line 130 crosses an initial (e.g., zero) level 154 of the first output signal, occurs a first time amount 156 in advance of the time 120. By contrast, it can be seen from the second graph 102 that a second virtual starting point 162 of the second output signal 132, namely, the point at which the dashed line 140 crosses an initial (e.g., zero) level 164 of the second output signal, occurs a second time amount 166 in advance of the time 120 that is less than the first time amount 156. And further by contrast, it can be seen from the third graph 104 that a third virtual starting point 172 of the third output signal 142, namely, the point at which the dashed line 150 crosses an initial (e.g., zero) level 174 of the third output signal, occurs a third time amount 176 in advance of the time 120 that is less than each of the first time amount 156 and the second time amount 166. Accordingly, because of the differences in the timing of the clock signals 108, 110, and 112, the output signals 122, 132, and 142 are out of phase relative to one another, and such differences correspond to the producing of jitter in the overall output signal during operation in which a given clock signal varies in its phase over time.
Although efforts have been made to develop modified systems and methods for signal processing to alleviate such concerns, such modified systems and methods have other disadvantages. For example, one manner of addressing the above-discussed problems relating to jitter and associated inaccuracy involves increasing the clock frequency to a level at which the clock is no longer the dominant jitter source. However, this strategy can result in increased total power consumption and necessitate higher timing constraints on the digital signal processing, neither of which are desirable.
For at least these reasons, therefore, it would be advantageous if one or more improved systems and methods for signal processing could be developed that addressed one or more of these concerns or disadvantages relating to jitter, and/or one or more other concerns or disadvantages.