Digital and analog circuits, when processing signals, must often store a signal at one instant to be made available at a later instant. In many such signal processing circuits the signal is stored for a long time. A basic storage requirement includes maintaining the signal's original voltage or current magnitude. Digital circuits generally present a simple problem since the voltage levels stored typically have one of two magnitudes, i.e., a binary zero or a binary one. Some attenuation of a binary signal over time is not problematic since the voltage magnitude is easily restored to its original magnitude by a simple buffer circuit. Commonly used digital storage circuits include dynamic random access memory (DRAM) and shift registers. Analog signal storage, on the other hand, often presents a more difficult problem since the stored analog signals can have a continuum of voltage or current magnitudes. Attenuation of a stored analog signal is therefore undesirable. Many sample-and-hold circuits exist for temporarily storing an analog voltage signal. Semiconductor integrated circuits provide high quality capacitors and switches that are useful for capturing and storing voltages. A simple voltage mode sample-and-hold circuit includes a switch for coupling and decoupling a voltage to be sampled to a capacitor. The switch may be a metal oxide field effect transistor (MOSFET) which appears as an open circuit while in an off state and as a short circuit while in an on state (ideally). A capacitor is made available, for example, by a metal layer separated from a polysilicon or diffusion layer by an insulator such as silicon dioxide.
The MOSFET is turned on coupling an input voltage to be sampled to the capacitor, and the capacitor in turn charges to the magnitude of the input voltage. At the moment the input voltage is to be sampled the MOSFET is turned off, thereby decoupling the capacitor from the input voltage. The capacitor continues to store the charge thus holding the sampled input voltage. Leakage currents inherent in the capacitor insulating materials and switching device, cause charge attenuation over time. The attenuation limits the useful period for accurately holding the sample. Further refinements to the simple voltage mode sample-and-hold circuit include adding amplifiers at the input and output for providing a high impedance at the input and a low impedance at the output. An input buffer improves bandwidth since the capacitor can charge faster, i.e., a reduced RC time constant. A low output impedance reduces loading effects.
A voltage mode sample-and-hold circuit, disclosed by Hands, et al., in U.S. Pat. No. 3,469,112, consists of a dual stage unity gain operational amplifier having a storage capacitor connected to an inverting input. The storage capacitor charges to an input voltage level defined by an input signal applied to a non-inverting input. The storage capacitor subsequently drives an output load directly. The sample-and-hold circuit taught by Hands et al, therefore, is a voltage-in, voltage-out type of sample-and-hold circuit. Furthermore, the storage capacitor is buffered from the input signal and forms part of a feedback loop. There are numerous voltage-in, voltage-out sample-and-hold circuits disclosed that are similar to that disclosed by Hands, et al. Kurcharewski, for example, in U.S. Pat. No. 4,185,211, discloses a circuit which uses a transconductance amplifier with feedback for similarly charging the storage capacitor.
Another similar voltage mode sample-and-hold circuit is set forth in U.S. Pat. No. 4,321,488 by Srivastava, wherein the input voltage is sampled by switching off the bias supply to isolate the storage capacitor during the hold mode. Murayama, et al., provide a variation on Srivastava's circuit wherein low voltage operation is made possible by incorporating a folded current mirror as disclosed in U.S. Pat. No. 5,004,935. A voltage mode sample-and-hold circuit taught by Thompson, in U.S. Pat. No. 3,643,110, uses one of two differential amplifiers as a switch for discharging the storage capacitor. Thompson thus teaches using separate charge and discharge paths for the storage capacitor. Different variations on the voltage mode sample-and-hold circuit are disclosed by Saito in Japanese Patent 63-109661, and by Matsuura in Japanese Patent 63-304099. Saito and Matsuura each teach coupling the storage capacitor directly to the input signal to be sampled, i.e., in an open loop operating mode. The output voltage, on the other hand, is isolated from the storage capacitor to increase control of the output voltage.
While there are many voltage mode sample-and-hold circuits available, storing analog signals as currents is also very desirable. A current mode sample-and-hold circuit can potentially offer improved accuracy and increased bandwidths since the currents are less affected by stray capacitances and IR (current * resistance) drops. A very simple current mode sample-and-hold circuit would include a switch coupled to an inductor, wherein the inductor would temporarily store a current flowing through the inductor. There exists several limitations, including short storage times, and destructive voltage spikes due to rapidly changing current flow. Additionally, inductors are not readily available in monolithically integrated form.
Alternately, a current mode sample-and-hold circuit may be realized by sampling an input current, linearly converting the sample into a voltage and storing the voltage across a storage capacitor, and finally, converting the stored voltage to an output current. FIG. 1 depicts a proposed current mode sample-and-hold circuit that converts a current into a voltage and back into a current again. This circuit, however, introduces errors in the conversion process and limits frequency to the performance of the operational amplifiers. Removing the operational amplifiers can enhance frequency response, but the sample-and-hold circuit would then have increased conversion inaccuracies and undesirable loading effects.
A current mode sample-and-hold circuit that converts an input current into a voltage and then converts the voltage into an output current is described by Hughes in U.S. Pat. No. 5,012,133. Hughes' invention consists of a collection of current conveyors, wherein a current conveyor is a three terminal device similar to a current mirror but having a low input impedance. Each current conveyor samples an input current and converts the sampled current to a voltage for storage. By providing a plurality of current conveyors, a current sample of a previous period may be added to a current sample of a later period. In Hughes' implementation, however, a bias current is added to the sampled current which must be subtracted. Furthermore, the input current acquisition is made in an open loop mode, and no buffering or amplification of the input current is provided.
Thus what is needed is a current mode sample-and-hold circuit for acquiring an input current in a closed loop mode, and directly converting that input current into a representative output current.