As integrated circuit technologies continue to push into higher densities, a number of transistor types have become popular which involve one or more narrow channel structures wrapped with a gate electrode. The channel structures are often called fins, and transistors that include them are sometimes called FinFETs, described for example in D. Hisamoto et al., IEDM, 1998; and N. Lindert et al., IEEE Electron Device Letters, p. 487, 2001, both incorporated by reference herein for their teachings. The fins comprise semiconductor bodies usually arranged in parallel on the substrate, so that they project vertically upwards from the substrate. A gate dielectric layer overlies the sides and top of the fins, and a gate conductor, which can be implemented using metal or polysilicon for example, extends across the fins and over the gate dielectric layer. On either side of the gate conductor, source and drain regions are implemented in the fins. The FET transistors that result have source, channel and drain regions in the fins, and a gate overlying the fins. Such transistors are often called multi-gate transistors, because the gate conductor wraps around three sides of the fins, and as a result increases the effective width of the channel.
FinFET transistors are commonly made from a silicon fin on a silicon oxide support, or a silicon fin on a silicon support. In the case of a silicon fin on a silicon oxide support, the crystalline silicon fin is on an amorphous silicon oxide support. The amorphous silicon oxide does not influence the crystalline lattice properties of the crystalline silicon fin. In the case of a silicon fin on a silicon support, both the fin and the silicon fin are made of the same crystalline silicon with the same bandgap, same lattice constant, etc. So FinFET transistors have not been made from different crystalline materials in the fin and fin support. Such different crystalline materials require that the lattice constant and bandgap of both crystalline materials be compatible. Moreover, the feasibility of CMOS-like logic with such different crystalline materials requires that the lattice constant and bandgap of both crystalline materials be compatible for both n-type and p-type devices. Such issues discourage FinFET transistors made from different crystalline materials in the fin and fin support.
The fins used to implement the FinFET transistors can be quite narrow. As a result of the multi-gate gate structure and the narrow widths of the fins, FinFET transistors have excellent performance characteristics and small layout areas. But even with such narrow fins, the electric field generated by the gate control voltage can be limited in depth and may not extend sufficiently into the cross-sectional middle of the fin. In the off-state, this causes leakage through the middle of the fin. In the on-state, this causes lowered current through the middle of the fin. The wider the fin, the worse the decreased gate voltage control in the middle of the fin, as the middle of the fin becomes more distant from the gate. Manufacturers can reduce this problem by narrowing the fin further, but this solution is difficult to implement because the mechanical instability and line edge roughness of such a narrow fin can cause yield loss.
Fringing electric fields generated from the gate near a crystalline fin support are not expected to solve the issue of decreased gate voltage control in the middle of the fin. Conductors terminate electric field lines, and insulators support electric fields. Because a crystalline fin support is not an insulator, the crystalline fin support is expected to terminate the electric field lines from such fringing electric fields.
Accordingly, there is a need for better ways to improve FinFET transistors with different crystalline materials in the fin and fin support. Also, there is a need for better ways to improve gate control voltage in FinFET transistors.