In large-scale digital logic designs in the field of data communications, sometimes in order to enhance the processing capacity of a logic circuit or to match the bit widths of buses on both sides of the logic circuit, it is needed to perform bit width conversion on data path of the logic circuit. Taking into account that the total bandwidths on both sides of the logic circuit are not necessarily the same, or a congestion condition may occur on one side, the logic circuit also needs to be able to cache the data to be transmitted.
For example, such an application scenario is as shown in FIG. 1. On the uplink side, data are input by a data bus on one side and transmitted to Y (Y is an integer equal to or greater than 1) channels on the other side, and on the downlink side, the data are aggregated from the Y channels according to a scheduling indication and then transmitted to the data bus to output. For the data transmitted on the data bus, each data is only for one channel; in order to efficiently use the bandwidth of the respective channels, only the valid data are transmitted on the respective channels. Bit width of the data bus is A, the bus width of each device is B, and A is N times (N is an integer large than or equal to 1) B. Taking into account that the bandwidth of the data bus is not necessarily equal to the total bandwidth of respective channels and a congestion condition is likely to occur on both the data bus and respective channels, caches need to be provided on both the uplink and downlink transmission paths.
In this regard, generally the logic circuit as shown in FIG. 2 can be used to implement the data cache and bit width conversion, wherein FIFO (First In First Out) is used to perform the data cache, and a separate bit width converting and splitting circuit is used to implement the data bit width conversion. On the uplinkside, a channel identification and distribution circuit distributes the data together with the valid bit field indication of the data to the input FIFOs having a bit width of “A+the valid bit field indication width of the data” in one-to-one correspondence to respective channels according to the destination of the data on the input data bus; when a corresponding channel can receive the data input, the data are read out from the input FIFO, and the valid portion of the data is converted by the bit width converting and splitting circuit into a data stream with a bit width of B according to the valid bit field indication of the data, and sent to the corresponding channel. On the downlink side, the bit width converting and splicing circuit first converts the data transmitted from the respective channels into data with a bit width of A, and then writes the data into the output FIFOs in one-to-one correspondence to the respective channels; when the data bus can receive data, the data selection and aggregation circuit reads out the data from the respective output FIFOs according to a scheduling order, and aggregates and outputs the data to the output data bus.
Wherein, the bit width converting and splitting circuit which implements the data bit width conversion mainly consists of a de-multiplexer (DMUX) whose working mode is as follows:
For each channel, after the data with a bit width of A and the valid bit field indication of the data are read out from the input FIFOs, they are first stored in a register. The bit width converting and splitting circuit selects and outputs the data with a width of B in its first portion in the first cycle, and outputs the data with a width of B adjacent to the last data in the second cycle, and until all the valid data are scheduled to output, the bit width converting and splitting circuit turns to the next data read out from the input FIFOs, and continues to perform the bit width conversion according to the abovementioned mode.
The bit width converting and splicing circuit basically is a reverse process of the bit width converting and splitting circuit, and mainly consists of a multiplexer (MUX) whose working mode is as follows:
For each channel, after the data with a bit width of B are output from the channels, they are spliced together by the bit width converting and splicing circuit into data with a width of A according to the outputting order, and written into the corresponding output FIFOs.
In this method, if only a portion of bit fields in the data input by the uplink side data bus or the data (with the bit width all being A) output from the respective channels on the downlink side and spliced together by the bit width converting and splicing circuit are valid, when being stored into the FIFO, this data still needs to occupy a width of “A+the valid bit field indication width of the data”, which is exactly the same as the case where all the bit fields of this data are valid, resulting in its relatively low cache utilization.
In addition, taking into account the specific implementation of the circuit: if the FPGA (Field Programmable Gate Array) mode is used to implement this circuit, because the bit width of the Block RAM (block random access memory) for achieving the FIFO in the FPGA is limited, and its length is much greater than its width (take the Virex-5 FPGA in Xilinx for example, the maximum configuration bit width of a 36 kb Block RAM can only reach 36 bits), taking into account that this method needs to use Y FIFOs with the bit width of “A+valid bit field indication width of the data”, when the data bus width A is relatively large, using the FPGA mode needs to splice the bit widths of a plurality of Block RAMs to achieve each FIFO. So a considerable amount of Block RAM resources will be consumed and a large design area will be occupied, especially when the number of channels Y is relatively large. Even if the ASIC is used to implement the related logic circuit, the FIFO with such a large bit width will bring pressures to the back-end in terms of layout and timing delay and also occupy a large design area.