The present invention generally relates to a semiconductor memory device, and particularly to a large capacity semiconductor memory device suitable for a storage device in a large-scale computer system. More particularly, the present invention is concerned with a semiconductor memory device having information indicative of the presence of defective memory cells (bits).
Conventionally, much effort to improve the production yield of semiconductor devices is being made. Presently, a technique which realizes 100% production yield is not available. It is possible to use only semiconductor memory devices having no defective memory cells. However, the number of defective memory cells increases with an increase in storage capacity and thus it is difficult to obtain a large number of semiconductor memory devices having no defective memory cells. From this point of view, a semiconductor memory device having redundant bits has been proposed. Such a semiconductor memory device has a memory cell array which is divided into a main memory cell array and a redundant memory cell array. Memory cells in the main memory cell are investigated by a conventional wafer probing test, and defective memory cells are detected. The detected defective memory cells are stored in a ROM (read only memory) provided in the semiconductor memory device. When a defective memory cell in the main memory cell array is addressed, a redundant bit in the redundant cell array is actually accessed instead of the addressed defective memory cell.
FIG. 1 is a block diagram of a conventional semiconductor memory device. The semiconductor memory device in FIG. 1 includes a memory cell array 10, which is divided into a main memory cell array 10a and a redundant memory cell array 10b. The main memory cell array 10a is accessed by a column decoder 11 and a row decoder 12a. The redundant memory cell array 10b is accessed by a redundant row decoder 12b and the column decoder 11. Normally, an address signal from an external circuit (not shown) such as a central processing unit (CPU) is supplied to the column decoder 11, and the row decoder 12a through a controller 13 and a switching circuit 14. Data are read out from or written into memory cells of the main memory cell array 10a corresponding to the address signal. The controller 13 compares the address signal with addresses stored in a read only memory (ROM) 13a. When it is determined that the address signal indicates a group of memory cells including a defective memory cell, the switching circuit 14 supplies the address signal from the controller 13 to the redundant row decoder 12b. A group of memory cells to be substituted for the group of memory cells having the defective memory cell is accessed by the column decoder 11 and the redundant row decoder 12b. Such a replacement is carried out in a row unit.
Memory cells forming the redundant memory cell array 10b must have no defective cells. Thus, the redundant memory cell 10b array is configured by only a limited number of memory cells having no defect. As a result, the redundant memory cell array 10b can save a limited number of defective memory cells in the main memory cell array 10a. In order to provide a large capacity less-expensive semiconductor memory device for use in a large-scale computer system, it is desired that a semiconductor memory device having a large number of defective memory cells be used. The conventional configuration shown in FIG. 1 cannot satisfy such a desire. In some cases, a large number of the elements each having the configuration shown in FIG. 1 is used for providing a large capacity semiconductor memory. In this arrangement, each element has the controller 13, the ROM 13a and the switching circuit 14. This prevents the memory device from being compactly made and operating at high speeds.