1. Field
Exemplary embodiments of the present invention relate generally to a memory device and a method for fabricating the same, and more particularly, to a non-volatile memory device in which memory cells are stacked over a substrate and a method for fabricating the same.
2. Description of the Related Art
Non-volatile memory devices such as flash memories retain the stored data even when the power supply is cut off.
A non-volatile memory device includes a cell region having the memory cells and a peripheral circuit region having diverse circuits of unit elements needed to perform the operations for accessing the memory cells.
Memory cells in a cell region have a stacked structure of tunnel insulation layer, a floating gate, a charge blocking layer, and a control gate.
The diverse circuits in the peripheral circuit region include various unit elements such as transistors, capacitors, resistors, etc. For example, a voltage dividing circuit as shown in FIG. 1 which includes at least one resistor may be disposed in the peripheral circuit region.
FIG. 1 illustrates a conventional voltage dividing circuit.
Referring to FIG. 1, a voltage applying circuit 110 outputs a predetermined voltage, e.g., high voltage VPP, to the first output node D1. A voltage dividing circuit 120 formed of serially connected first and second resistors R1, R2 at a second output node D2 divides the high voltage VPP provided to the first output node D1. The first resistor R1 is coupled between the first output node D1 and a second output node D2, and the second resistor R2 is coupled between the second output node D2 and a ground. The first resistor R1 and the second resistor R2 divide the high voltage VPP applied to the first output node D1 based on the resistance ratio of R1 and R2 and output dividend voltages VPPI to the second output node D2.
Therefore, in order to form a voltage dividing circuit in the peripheral circuit region, a resistor body needs to be formed over a portion of the substrate in the peripheral circuit region. The resistor body for voltage division is referred to as “a voltage dividing resistor body,” hereafter.
Conventionally, a polysilicon layer is used as a voltage dividing resistor body. The polysilicon layer for use as a voltage dividing resistor body is formed when forming a polysilicon layer for a floating gate in a cell region, or when forming a polysilicon layer for a lower layer of a control gate in a cell region.
However, when a voltage dividing resistor body is formed nearer the substrate together with a lower structure element such as a floating gate or a control gate, the resistance of the voltage dividing resistor body changes greatly. This is due to the changes in the impurity doping concentration of the polysilicon layer as a result of performing many diverse subsequent processes such as a thermal treatment or an etch process.
In a two dimensional memory device, memory cells are formed over a silicon substrate in a single layer. To overcome the technical limitations associated with further improving the level of high integration in a two-dimensional memory device, a non-volatile memory device having a three-dimensional structure in which a plurality of memory cells are stacked perpendicularly to a silicon substrate has been proposed.
FIG. 2 is a cross-sectional view illustrating a typical three-dimensional structure in a non-volatile memory device.
Referring to FIG. 2, the conventional three-dimensional non-volatile memory device includes a lower selection transistor (LOWER ST), a plurality of memory cells (MC), and an upper selection transistor (UPPER ST).
The lower selection transistor LOWER ST and the upper selection transistor UPPER ST correspond to a drain selection transistor (or a source selection transistor) and a source selection transistor (or a drain selection transistor) of a conventional two-dimensional non-volatile memory device, respectively, and they are selection transistors for selecting a target page PAGE during a program/read operation of the non-volatile memory device. Each of the lower selection transistor LOWER ST and the upper selection transistor UPPER ST includes a channel layer 14 protruded vertically to a substrate 10, a gate electrode-forming conductive layer 12 disposed on the sidewalls of the channel layer 14, and a gate insulation layer 13 disposed between the channel layer 14 and the gate electrode-forming conductive layer 12.
A plurality of memory cells MC is stacked vertically between the lower selection transistor LOWER ST and the upper selection transistor UPPER ST. The memory cells MC include the channel layer 14 protruded vertically to the substrate 10, a structure disposed on the sidewalls of the channel layer 14 and including the gate electrode-forming conductive layer 12 and an inter-layer dielectric layer 11 alternately stacked, and a charge blocking layer 15, a charge trapping layer 16 and a tunnel insulation layer 17 disposed between the stacked structure and the channel layer 14.
The three-dimensional non-volatile memory device also requires a resistor body such as a voltage dividing resistor body to be formed in a peripheral circuit region.