The present invention relates a method for programming multi-level non-volatile memories by controlling the gate voltage. The invention specifically refers to non-volatile memories formed of floating gate cells (EPROM, EEPROM, flash) in which the cells programming is performed by modifying the threshold voltage of the cells, that is modifying the amount of the charge stored in the floating gate region. The present method however can be applied also to memory cells of a different type (for example MNOS, i.e., Metal-Nitride-Oxide-Semiconductor technology cells).
For a better understanding, FIG. 1 shows the electric diagram of a typical floating gate memory cell having a drain terminal D, a source terminal S, a control gate terminal (herein below also defined gate terminal) CG and a body terminal B. FIG. 1 further shows the floating gate region FG. FIG. 2 shows the symbol of a different memory cell, the so called xe2x80x9csplit-gatexe2x80x9d.
Currently, to increase the data storage density and therefore reduce the physical memories array sizes, multi-level programming techniques are being studied, wherein the threshold voltage for each memory cell can be programmed to one among m predetermined levels. If m=2n, a memory cells is able to store a number of information bits equal to n=log2m, with clear advantages in terms of density with respect to conventional two level memories, allowing programming of two levels only (xe2x80x9chighxe2x80x9d level and xe2x80x9clowxe2x80x9d level), and therefore storing a single bit per cell (m=2 and therefor n=1).
The programmable threshold levels must be placed to a certain mutual distance, in order to be able to be recognized without errors when read. Moreover, the threshold voltage cannot be programmed exactly at the desired value: every level corresponds in practice to certain threshold voltage interval, as shown by the comparison between FIG. 2a and FIG. 2b related to four-level programmable cells. FIG. 2a shows the ideal case in which it is supposed to obtain a precise programming of each of four threshold voltage levels, while FIG. 2b shows a more realistic case, in which every logic value corresponds to a certain threshold voltage interval. FIG. 2a also shows the correspondence assigned, as an exemplificative but non limiting example, between the different threshold voltage values and programmed levels (respectively 0, 1, 2 and 3).
The threshold voltage interval corresponding to each programmable level must be sufficiently reduced so that the intervals corresponding to adjacent levels can be placed at such a mutual distance as to guarantee safe maintaining and recognizing of data stored into the cells, without having to use a global interval excessively wide to allocate all desired logic levels. In fact, there are both a lower limit and an upper limit for this global interval, dictated by practical reasons and reliability reasons. In order to compute the optimum distance between threshold voltage intervals corresponding to different stored levels, effects such as reading and programming circuits inaccuracy and environmental conditions variations, degrading time of the stored charge and reading and programming noises must also be taken into account, since they create an undesired stored charge variation, as known to the skilled person.
To obtain an adequate cell programming, generally the multi-level cell programming is performed through the technique defined as xe2x80x9cprogram and verifyxe2x80x9d. According to this technique, a programming operation is performed through a succession of programming pulses and, after having applied each programming pulse, it is verified whether the programmed cell threshold voltages reached the respective desired value, as schematically shown in FIG. 3: if a certain cell has reached the desired threshold level, it does not receive any further programming pulses. Verifying is usually performed simultaneously for all cells in a group of cells (one or more words) that are programmed in parallel and for any desired programming level, it consists in comparing, directly or indirectly, a cell threshold voltage with preset reference values Vref,i. Programming and verifying continue until all cells in a group have been programmed at the respective desired level.
It has been demonstrated (see for example: xe2x80x9cTechnological and design constraints for multilevel flash memoriesxe2x80x9d by C. Calligaro, A. Manstretta, A. Modelli, G. Torelli, Proceedings of Internal Conference on Electronic Circuits and Systems, Rhodes, Greece, pp. 1003-1008) that if a set of programming pulses with constant time length is applied to a non-volatile memory cell, the drain terminal voltage is kept constant and the gate terminal voltage is increased by a constant value xcex94VGP at every pulse (stepped gate voltage), after a first transient step (lasting, generally, few pulses if during the first pulse an adequate voltage supplied to the gate terminal), the cell threshold voltage is subjected to an increase xcex94VTH equal to xcex94VGP for every pulse. Thus, after the initial transient step, we have:
xcex94VTH=xcex94VGPxe2x80x83xe2x80x83(1)
This relationship is valid if the programming pulse has a time length greater than a minimum value that depends on the type of process and cell and that for typical cells can be included between some hundreds of ns and 1 xcexcs.
Relationship (1) is valid for any cell, but the relationship between the voltage value applied to the cell gate terminal during the last programming pulse, and the threshold voltage value VTH reached by the cell at the end of such pulse cannot be determined a priori for a specific cell. In other words, relationship (1) shows the threshold voltage increase upon every programming pulse, but not its absolute value. Such absolute value in fact depends on different factors linked to the manufacturing process (for programmable cells through hot channel electron injection, for example, it depends firstly on the effective cell channel length).
This is schematically shown in FIG. 4, that shows the behavior of the threshold voltage Vth obtained by representing along the ordinate the threshold voltage after applying each programming pulse N (shown along the abscissa) and connecting the points thereby obtained, for three different cells (in particular, curves A, B, and C refer to cells having respectively increasing channel lengths). As can be noted, after a first initial step, the threshold voltage increases linearly, with increments xcex94VGP upon every programming pulse, along three mutually parallel straight lines. In practice, from relationship (1) it is not possible to know on which of the three straight lines the threshold voltage of a specific cell is moving during programming and therefore is not possible to compute the absolute threshold voltage value Vth reached after each pulse.
By applying such principles to the programming and verifying technique, the memory cells are programmed by applying programming pulses with a constant length, constant drain voltage, and progressively increasing gate voltage with a constant increase equal to xcex94VGP between two subsequent pulses. Therefore the gate terminal voltage plot as shown in FIG. 5 is obtained. Under ideal conditions, with this technique the width of the intervals corresponding to programmed levels (hereinbelow called program level width) is equal to xcex94GP. In fact, during programming, the (jxe2x88x921)-th programming pulse, preceding the one in which the threshold voltage corresponding to the desired programming level (i-th level) is reached and whose comparison reference level during verifying is equal to Vref,i, determines a threshold voltage that is less than Vref,i but next to this one, while when j-th programming pulse is provided, the threshold voltage goes to a value equal to the previous value plus xcex94VGP, so that it will not be greater than Vref,i,+xcex94VGP. In practice, the threshold voltage for the program cells at level VTH,i exceeds the reference value Vref,i, by an amount included between 0 and xcex94VGP.
Consequently, though there are other effects causing widening of the programmed levels, such as for example inaccuracy of the reading circuits used during verify, generally a reduction in the increase xcex94VGP of the programming voltage applied to the cell gate terminal brings about a decrease in the width of the programming levels, allowing to better allocate the levels themselves within the predefined interval as mentioned above.
On the other hand, the reduction in the increase xcex94VGP requires a corresponding increase of the number of programming and verifying pulses necessary to reach a preset final threshold voltage starting from a predetermined initial value.
The increase of the number of programming and verifying pulses generates an increase of the global time necessary to program a memory cell at a preset threshold level. In fact, the time necessary for a complete programming and verifying step is decisely greater than the time for a single programming pulse, above all in the case of short time programming pulses (1 xcexcs or less). Between each programming pulse and the following verifing step, in fact, it is necessary to deactivate the programming circuitry, activate the reading circuitry inside the integrated circuit and wait for the reading voltages to be applied to cells to reach the desired value with a sufficient accuracy, which requires a certain length of time. Moreover the accuracy required for bias voltages increases along with a decrease in the distance between threshold voltages corresponding to adjacent programmed levels (the cell current when reading, and, therefore, when verifying strictly depends on the value of voltages applied to drain and gate terminals).
Similarly, when a verifying step is followed by a programming step, it is necessary to deactivate the reading circuitry and to activate the programming circuitry with a further loss of time. The time for a complete programming and verifying step is therefore equal to TGP(1+xcex7), wherein TGP is the length of a programming pulse and xcex7 is greater than 0 and generally can be of the order of one.
Depending on specific needs, it is therefore necessary to perform a compromise choice between programmed level accuracy (low increase xcex94VGP and therefore high number of complete programming and verifying steps) and the global programming operation speed.
According to principles of the present invention, a programming method for non-volatile memory cells is provided. A complete programming operation is carried out with a plurality of programming pulses not followed by a verify step. Only after a plurality of pulses have been applied is the first verify performed to determine the programmed level. This allows an improvement in the compromise between accuracy and global programming time.