(a) Field of the Invention
The present invention relates to a method for manufacturing a three-dimensional semiconductor device and a semiconductor wafer suited to the method.
(b) Description of the Related Art
Smaller thickness and planar size of electronic equipment has been achieved mainly by using the parts thereof having smaller dimensions. The microfabrication technology of LSI has largely contributed to the smaller planar size of semiconductor devices used in the electronic equipment However, introduction of a further-advanced microfabrication technology requires a huge amount of investment, and does not satisfy the request for a lower production cost of the semiconductor devices. A three-dimensional mounting technique which stacks a plurality of semiconductor chips in a thickness direction to form a three-dimensional semiconductor device may solve the above technical subject of smaller planar size.
In the three-dimensional mounting technique, penetrating electrodes extending perpendicularly to a semiconductor wafer may be provided for coupling together the semiconductor chips in the thickness direction. The penetrating electrodes are associated with coupling terminals such as pad. electrodes or bumps, which connect together penetrating electrodes of adjacent semiconductor chips. Patent Publication JP-2006-261403A, for example, describes such a three-dimensional mounting technique.
In the three-dimensional mounting technique for the semiconductor device, the fabrication process first prepares a semiconductor wafer on which a plurality of semiconductor chips and penetrating electrodes are formed, pad electrodes and bumps are then formed, followed by separating the wafer into the plurality of chips and stacking the same one on another. The stacking process uses adhesive between the chips for bonding. However, the adhesive may cause the problem of insufficient mechanical force between the stacked chips in the three-dimensional semiconductor device, as will be detailed hereinafter.
First, the adhesive is difficult to spread uniformly around the chips due to a relatively larger planar size of the chips. Second, a smaller height of the coupling terminals, such as bumps, reduces the gap between the stacked chips and prevents the adhesive from spreading uniformly in the gaps. Third, a large number of coupling terminals reduce the horizontal space for introducing the adhesive between the stacked chips, which may incur occurring of a void within the adhesive due to clog of the adhesive.
As a countermeasure for the above problems, it may be considered to form in advance the bumps or pad electrodes on the chips of the wafer, the wafer is then separated into the chips, and the chips are stacked one on another and applied with a higher pressure against one another for electrical and mechanical connection after the chips are coated with the adhesive. Patent Publication JP-1999-204939A, for example, describes a technique for electrical connection using heat and pressure between the chips coated with adhesive after forming the coupling terminals. This technique removes the adhesive from the contact surface of the coupling terminals by the heat and pressure while leaving the adhesive in the other area of the gap between the chips, thereby assuring the electrical connection as well as the mechanical strength.
FIG. 5 shows a conceivable example or comparative example using the above technique in the stacked chips on which smaller-size coupling terminals are formed. In this example, an adhesive layer 16 may be left between the contact surfaces of the coupling terminals due to the smaller size and smaller pitch of the coupling terminals, e.g., between the bumps of the chips. More specifically, the technique described in JP-1999-204939A is not suited to mechanically coupling together the semiconductor chips having smaller-size and smaller-pitch coupling terminals without incurring an insufficient electrical connection.