The invention relates to non-volatile memories, and more particularly to, memory cells using a dielectric layer for storage of charge.
One of the difficulties in non-volatile memories (NVMs) is a sufficiently fast erase time. Erase time needs typically to be less than 1 second. NVMs that use a dielectric layer, typically silicon nitride, as the structure for storing charge provide a significant cost benefit over NVMs using conventional floating gates. In the case of NVMs with a silicon nitride storage layer, there is a bottom dielectric between the substrate and the silicon nitride layer. This dielectric is typically silicon oxide because of its ability to experience tunneling with minimal destructive effect and its good interfacial qualities. The difficulty is that this layer is preferably thin for erase performance but preferably thick to avoid leakage of charge from the silicon nitride layer that is storing charge. Thus, there is a tradeoff between the erase time and leakage. The result can be that there is no satisfactory point at which there is both an adequately fast erase time and a sufficiently low leakage.
One solution has been to use hot hole injection (HHI) to neutralize electrons in the nitride layer. This allows for a thicker oxide while still achieving relatively fast neutralization of the trapped charge in the silicon nitride layer. One problem is that hot holes are generated in a relatively localized area and may be limited in area where the trapped charge can be neutralized so trapped charge outside of this limited area may not be neutralized. This makes the erasure incomplete and perhaps provides insufficient differential between programmed and erased states. Another problem is that hot hole injection tends to be more damaging to the oxide between the silicon nitride and the substrate than tunneling. The damage results in lower endurance.
Thus there is a need for a NVM cell, of the type having a dielectric layer that acts as the storage element, with an improved erase characteristic.