The present application claims priority to Japanese Application No. P2000-233321 filed Aug. 1, 2000, which application is incorporated herein by reference to the extent permitted by law.
1. Field of the Invention
The invention relates to a memory device for holding data by storing in a storage region an electric charge transferred from a conduction region, a method of manufacturing the same, and an integrated circuit on which the memory devices are integrated.
2. Description of the Related Art
Conventional memory devices, typified by an EEPROM (electric erasable-programmable read only memory), a flash memory and the like, comprise one gate electrode; a source region, a conduction region and a drain region, which are made of a semiconductor; and a storage region having two-dimensional space, which is provided between the gate electrode and the conduction region with an insulating film in between. The memory device operates by a quantum mechanical tunnel effect allowing the transfer of an electric charge between the conduction region and the storage region. That is, the writing of data is performed by storing in the storage region an electric charge transferring from the conduction region to the storage region, whereas the erasing of data is performed by the transfer of an electric charge previously stored in the storage region to the conduction region. The reading of data is performed by measuring the conductivity of the conduction region for an electric potential of the gate electrode and the amount of electric current passing through the conduction region. A series of above-mentioned functions of the memory device (the writing, erasing and reading of data, and so on) is made executable by applying a predetermined electric potential to one gate electrode according to the above-mentioned functions.
However, the conventional memory device has the following malfunction because the memory device is operated by the application of an electric potential to one gate electrode. That is, for example, when an electric potential is applied to one gate electrode at the time of the reading of data, the action of the application of the electric potential causes a change in an electric potential between the conduction region and the storage region. In this case, the change in the electric potential between the conduction region and the storage region causes the transfer of an additional electric charge from the conduction region to the storage region, or the transfer of a part of electric charge previously stored in the storage region to the conduction region. Therefore, the writing or erasing of data is unintentionally performed at the time of the reading of data, so that written data cannot be accurately read out.
The invention is designed to overcome the foregoing problem. It is an object of the invention to provide a memory device capable of accurately reading out data, a method of manufacturing the same, and an integrated circuit.
A memory device of the invention comprises an underlayer portion made of an insulator; a first control electrode provided on a surface of the underlayer portion; a conduction region made of a semiconductor, provided so as to correspond to the first control electrode; a second control electrode provided in a region opposite to a region in which the first control electrode is provided, with the conduction region between the first and second control electrodes; a first impurity region provided adjacent to the conduction region; a second impurity region provided apart from the first impurity region and adjacent to the conduction region; a storage region provided in either a region between the first control electrode and the conduction region or a region between the second control electrode and the conduction region, the storage region for storing an electric charge transferring from the conduction region; a tunnel insulating film provided in a region between the storage region and the conduction region; a first control insulating film provided between the first control electrode and the conduction region; and a second control insulating film provided between the second control electrode and the conduction region. Incidentally, an arrangement of the first control electrode includes not only the above-mentioned arrangement in which the first control electrode is formed on a surface of the underlayer portion, but also an arrangement in which the first control electrode is formed in a concave portion provided in a part of the underlayer portion.
In the memory device of the invention, an electric potential is applied to at least one of the first control electrode and the second control electrode, whereby an electric charge transfers between the conduction region and the storage region, so that the writing or erasing of data, or the like is performed. The conductivity of the conduction region for the electric potential of at least one of the first and second control electrodes and the amount of electric current passing through the conduction region are measured, whereby the reading of data is performed. Since the reading of data is performed in a state in which an electric potential is applied to the first control electrode, a change in an electric potential between the conduction region and the storage region is prevented.
A method of manufacturing a memory device of the invention includes the steps of forming a first control electrode on an underlayer portion made of an insulator; forming a conduction region made of a semiconductor so as to correspond to the first control electrode; forming a second control electrode in a region opposite to a region in which the first control electrode is provided, with the conduction region between the first and second control electrodes; forming a first impurity region adjacent to the conduction region; forming a second impurity region apart from the first impurity region and adjacent to the conduction region; forming a storage region made of a plurality of dispersed particles in either a region between the first control electrode and the conduction region or a region between the second control electrode and the conduction region; forming a tunnel insulating film in a region between the storage region and the conduction region; forming a first control insulating film between the first control electrode and the conduction region; and forming a second control insulating film between the second control electrode and the conduction region. Incidentally, the above-mentioned first control electrode is formed not only on the underlayer portion as mentioned above, but also in a concave portion provided in a part of the underlayer portion.
In the method of manufacturing a memory device of the invention, the first control electrode and the second control electrode are formed in such a manner that the conduction region and the storage region are sandwiched in between the first control electrode and the second control electrode.
In an integrated circuit of the invention on which a plurality of memory devices are integrated, each of the memory devices has an underlayer portion made of an insulator; a first control electrode provided on a surface of the underlayer portion; a conduction region made of a semiconductor, provided so as to correspond to the first control electrode; a second control electrode provided in a region opposite to a region in which the first control electrode is provided, with the conduction region between the first and second control electrodes; a first impurity region provided adjacent to the conduction region; a second impurity region provided apart from the first impurity region and adjacent to the conduction region; a storage region provided in either a region between the first control electrode and the conduction region or a region between the second control electrode and the conduction region, the storage region for storing an electric charge transferring from the conduction region; a tunnel insulating film provided in a region between the storage region and the conduction region; a first control insulating film provided between the first control electrode and the conduction region; and a second control insulating film provided between the second control electrode and the conduction region.
Incidentally, an arrangement of the first control electrode includes not only the above-mentioned arrangement in which the first control electrode is formed on a surface of the underlayer portion, but also an arrangement in which the first control electrode is formed in a concave portion provided in a part of the underlayer portion.
The integrated circuit of the invention uses the memory device of the invention. Since the reading of data is performed in a state in which an electric potential is applied to the first control electrode, a change in an electric potential between the conduction region and the storage region is prevented.
Other and further objects, features and advantages of the invention will appear more fully from the following description.