1. Field of the Invention
The present disclosed system relates to field-programmable gate arrays (FPGAs), and more particularly, to a field programmable gate array (FPGA) tile intra-tile buffer system.
2. Description of the Related Art
A field-programmable gate array (FPGA) is an integrated circuit (IC) that includes a two-dimensional array of general-purpose logic circuits, called cells or logic blocks, whose functions are programmable. The cells are linked to one another by programmable buses. The cell types may be small multifunction circuits (or configurable functional blocks or groups) capable of realizing Boolean functions of a few variables. The cell types are not restricted to gates. For example, configurable functional groups (xe2x80x9cFGsxe2x80x9d) typically include memory cells and connection transistors that may be used to configure logic functions such as addition, subtraction, etc., inside of the FPGA. A cell may also contain at least one flip-flop. Some types of logic cells found in FPGAs are those based on multiplexers and those based on programmable read only memory (PROM) table-lookup memories. Erasable FPGAs can be reprogrammed repeatedly. This technology is convenient when developing and debugging a prototype design for a new product and for small-scale manufacture.
FPGAs typically include a physical template that includes an array of circuits, sets of uncommitted routing interconnects, and sets of user programmable switches associated with both the circuits and the routing interconnects. When these switches are properly programmed (set to on or off states), the template or the underlying circuit and interconnect of the FPGA is customized or configured to perform specific customized functions. By reprogramming the on-off states of these switches, an FPGA can perform many different functions. Once a specific configuration of an FPGA has been decided upon, it can be configured to perform that one specific function.
The user programmable switches in an FPGA can be implemented in various technologies, such as ONO antifuse, M-M antifuse, SRAM memory cell, Flash EPROM memory cell, and EEPROM memory cell. FPGAs that employ fuses or antifuses as switches can be programmed only once. A memory cell controlled switch implementation of an FPGA can be reprogrammed repeatedly. In this scenario, an NMOS transistor is typically used as the switch to either connect or disconnect two selected points (A, B) in the circuit. The NMOS"" source and drain nodes are connected to points A, B respectively, and its gate node is directly or indirectly connected to the memory cell. By setting the state of the memory cell to either logical xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, the switch can be turned on or off and thus point A and B are either connected or disconnected. Thus, the ability to program these switches provides for a very flexible device.
FPGAs can store the program that determines the circuit to be implemented in a RAM or PROM on the FPGA chip. The pattern of the data in this configuration memory (xe2x80x9cCMxe2x80x9d) determines the cells"" functions and their interconnection wiring. Each bit of CM controls a transistor switch in the target circuit that can select some cell function or make (or break) some connection. By replacing the contents of CM, designers can make design changes or correct design errors. The CM can be downloaded from an external source or stored on-chip. This type of FPGA can be reprogrammed repeatedly, which significantly reduces development and manufacturing costs.
In general, an FPGA is one type of programmable logic device (PLD), i.e., a device that contains many gates or other general-purpose cells whose interconnections can be configured or xe2x80x9cprogrammedxe2x80x9d to implement any desired combinational or sequential function. As its name implies, an FPGA is xe2x80x9cfield-programmablexe2x80x9d, meaning that the device is generally programmed by designers or end users xe2x80x9cin the fieldxe2x80x9d via small, low-cost programming units. This is in contrast to mask programmable devices which require special steps in the IC chip-manufacturing process.
A field-programming unit typically uses design software to program the FPGA. The design software compiles a specific user design, i.e., a specific configuration of the programmable switches desired by the end-user, into FPGA configuration data. The design software assembles the configuration data into a bit stream, i.e., a stream of ones and zeros, that is fed into the FPGA and used to program the configuration memories for the programmable switches or program the shift registers for anti-fuse type switches. The bit stream creates the pattern of the data in the configuration memory CM that determines whether each memory cell stores a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d. The stored bit in each CM controls whether its associated transistor switch is turned on or off. End users typically use design software to test different designs and run simulations for FPGAs.
When an FPGA that has been programmed to perform one specific function is compared to an application specific integrated circuit (ASIC) that has been designed and manufactured to perform that same specific function, the FPGA will necessarily be a larger device than the ASIC. This is because FPGAs are flexible devices that are capable of implementing many different functions, and as such, they include excess circuitry that is either not used or could be replaced with hard-wired connections when performing one specific function. Such excess circuitry generally includes the numerous programmable transistor switches and corresponding memory cells that are not used in implementing the one specific function, the memory cells inside of functional groups, and the FPGA programming circuitry. This excess circuitry is typically eliminated in the design of an ASIC that makes the ASIC a smaller device. An ASIC, on the other hand, is not a flexible device. In other words, once an ASIC has been manufactured it cannot be reconfigured to perform a different function, which is possible with an FPGA.
Designers of FPGAs (as well as other PLDs) often provide their circuit designs to IC manufacturers who typically manufacture the FPGAs in two different ways. First, an FPGA design may be manufactured as its own chip with no other devices being included in the IC package. Second, an FPGA design may be embedded into a larger IC. An example of such a larger IC is a system on a chip (SOC) that includes the embedded FPGA as well as several other components. The several other components may include, for example, a microprocessor, memory, arithmetic logic unit (ALU), state machine, etc. In this scenario the embedded FPGA may be only a small part of the whole SOC.
The invention relates to an intra-tile buffering system for a field programmable gate array. The field programmable gate array comprises a field programmable gate array tile comprising a number of rows and a number of columns. Each row has a left end and a right end, and each column has a top end and a bottom end. Each row comprises a plurality of functional groups with an interface group located at said right end and said left end. Each column comprises a plurality of functional groups with an interface group located at said top end and said bottom end. A primary routing structure is coupled to said functional groups and interface groups and configured to receive primary output signals, route primary output signals within said at least one field programmable gate array tile, and provide primary input signals to said functional groups and interface groups. Each functional group is configured to receive a primary input signal, perform a logic operation, and generate a primary output signal. Each interface group is configured to transfer signals from said primary routing structure to outside of said at least one field programmable gate array tile, and includes a plurality of input multiplexers configured to select signals received from outside of said at least one field programmable gate array tile and provide signals to the primary routing structure inside said at least one field programmable gate array tile. Said primary routing structure comprises a horizontal bus coupled to each row of functional groups, a vertical bus coupled to each column of functional groups, a horizontal buffer coupled to each horizontal bus and spaced every Nth column of functional groups, where N is an integer, and a vertical buffer coupled to each horizontal bus and spaced every Mth row of functional groups, where M is an integer.
A better understanding of the features and advantages of the present disclosed system will be obtained by reference to the following detailed description of the disclosed system and accompanying drawings which set forth an illustrative embodiment in which the principles of the disclosed system are utilized.