1. Field of the Invention
The present invention relates to a data processor having a bus-sizing function, more particularly to a data processor capable of accessing data buses having bus widths different from each other according to a bus-sizing function.
2. Description of Related Art
Some data processors are capable of approximately accessing a memory system by switching the effective width of the data bus using a bus-sizing function when data is read/written during memory access.
The bus-sizing function includes dynamic bus-sizing and static bus-sizing. Dynamic bus-sizing as the capability of changing a bus width by designating a bus width every time memory is accessed. In static bus-sizing the bus width is fixed to a constant value after designating a bus width when the whole unit is reset.
In the following, an explanation will given of one example of a conventional data processor having a bus-sizing function as mentioned above and also having a cache.
FIG. 1 is a block diagram showing construction of a conventional data processor. This data processor is composed of a microprocessor 1 and an external memory 6 connected thereto by an external data bus 10 and an external address bus 11. Though the bus width of the external data bus D (0:63) 10 is 64 bits, using a static bus-sizing function, the bus width can be designated as either 64-bit width or 32-bit width. In the case where the external data bus 10 is used in a 32-bit width, accessing is carried out by using only lower 32 bits D (32:63) of the external data bus 10. The bit width of the external address bus A (0:31) 11 is fixed at a 32-bit width.
The microprocessor 1 is composed of a bus interface 2 and internal function circuits. The internal function circuits include an alignment circuit 3, a cache memory 4, an internal data operation circuit 5 and so on. Both the alignment circuit 3 and the cache memory 4 are connected to the bus interface 2 by a D bus 12, which is an internal data bus. The alignment circuit 3 and the internal data operation circuit 5 are connected with each other by an S bus 13, while the cache memory 4 and the alignment circuit 3 are connected with each other by a bus 14.
The data obtained over the external data bus 10 according to read-accessing from the external memory 6 is transferred to the alignment circuit 3 and the cache memory 4 through the bus interface 2 and the D bus 12. The read data is registered in the cache memory 4 as well as aligned by the alignment circuit 3. In the case where the data to be read is registered in the cache memory in advance, the data is transferred to the alignment circuit 3 from the cache memory 4 through the bus 14. The data having been aligned by the alignment circuit 3 is transferred to the internal data operation circuit 5 through the S bus 13. The respective bus width of the D bus 12, S bus 13 and bus 14 in the microprocessor 1 is 64 bits.
FIG. 2 is a circuit diagram showing a circuit for a data transferring system of the bus interface 2. This circuit is composed of tri-state buffers 30, 31 and buffers 32, 33. The bus 10H (which is the higher 32 bits of the external data bus 10) is connected to the bus 12H (which is the higher 32 bits of the D bus 12) through the buffer 32 and the tri-state buffer 30, and the bus 10L (which is the lower 32 bits of the external data bus 10) is connected to the bus 12L (which is the lower 32 bits of the D bus 12) through the buffer 33 and the tri-state buffer 31.
FIG. 3 is a schematic diagram showing logical levels of control signals 3A, 3B of the aforementioned tri-state buffers 30, 31 in reading data. In this state, the logical levels of the control signals 3A, 3B are always "1". Accordingly, data is ouputted from the bus 10H to the bus 12H and data is outputted from the bus 10L to the bus 12L.
FIG. 4 is a block diagram showing construction of the alignment circuit 3. In the alignment circuit 3, an 88-bit register 400 comprising a 4A register 40 of 32 bits, a 4b register 41 of 32 bits, a 4C register 42 of 24 bits is provided in order to store non-alignment data inputed from the D bus 12. A shifter 43 for aligning data stored in the 88-bit register 400 and a 64-bit register 44 for preserving data aligned by the shifter 43 are also provided.
The alignment circuit 3 is so constructed as to be able to align respective data of 8 bits, 16 bits, 32 bits and 64 bits. 64-bit data crosses a 32-bit boundary of memory space of the external memory 6 two times at most. Therefore 88 bits in total are necessary for the sizes of the 4A, 4B, 4C registers 40, 41, 42 storing non-alignment data.
FIG. 5 is a schematic diagram showing how data on the D bus 12 is taken into the 4A, 4B, 4C registers 40, 41, 42 shown in FIG. 4. The condition for the data being taken in is determined by the bus width of the external data bus 10 being used and the value of the third bit from the lower side of the address.
FIG. 6 is a block diagram showing a construction of the cache memory 4. The cache memory 4 is composed of a data registering register 50 of 256 bits, a data reading register 52, a cache memory data unit 51, a shifter 53 taking out 88 bits from 256 bits, a tag registering register 54, a cache memory tag unit 55, a tag reading register 56 and so on.
The data registered in one line of the cache memory 4 is 256 bits. External bus access for registering in the cache memory 4 is performed according to burst transfer access in which one line of data can be accessed at high speed. The data registering register 50 is composed of eight 32-bit registers 5A, 5B . . . 5H. The respective registers 5A, 5B . . . 5H are connected to the bus 12H and to the bus 12L.
FIG. 7 is a schematic diagram showing construction of a part of the memory space to be processed by the microprocessor 1 shown in FIG. 1. Addresses shown in FIG. 7 are byte addresses. The addresses shown in FIG. 7 are the lower 16 bits of 32-bit addresses and are indicated in hexadecimal.
FIG. 8 and FIG. 9 are timing charts showing timings for a burst transfer access. FIG. 8 shows the case where the external data bus 10 has a 64-bit width and FIG. 9 shows the case where it has a 32-bit width, respectively.
Burst transfer access is a transferring method in which four bus cycles are combined as a set. FIG. 8 and FIG. 9, reference symbol (a) designated clock CLK, (b) data on the external address bus A (0:31), (c) bus start signal #BS, (d) address strobe signal #AS, (e) data strobe signal #DS, and (f) designates a read/write signal R/#W respectively. All of these signals are outputted by the microprocessor 1. Preference symbol (g) designates a data-transfer completion signal #DC and (h) designates data on the external data bus D (0:63) 10. These signals are inputted to the microprocessor 1. Further, reference symbol (i) designates an access start signal indicating the start of the burst transfer access and (j) designates a bus cycle finishing signal indicating an end of each cycle of burst transfer. These signals indicate the states of the bus cycles to the internal data operation circuit 5 form the bus interface 2.
Next, an explanation will be given of the operation of such a conventional data processor as mentioned above.
The microprocessor 1, at first, accesses the built-in cache memory 4 when data reading of the memory is necessary. In the case where a cache miss occurs, that is, where data to be accessed is not stored in the cache memory 4, the bus cycle is started to the external memory 6 to read data by a burst transfer access. When data is read after accessing the external memory 6, the alignment circuit 3 aligns the data and at the same time the data is registered in the cache memory 4. The next time accessing is performed to the same address, since data is already registered in the cache memory 4, (that is, since there is a cache hit), the time required for accessing is shortened because there is no necessity for accessing the external memory 6.
Since the microprocessor 1 has a static bus-sizing function as aforementioned, it can operate by changing the bus width of the external data bus 10.
In the following, an explanation will be given of how the operation in the cache where a cache miss occurs and data is read by a burst transfer access is different due to various bus widths of the external data bus 10 being used.
First an explanation will be given of the case where the external data bus 10 is operated with the bus width thereof being 64 bits. At the time that a cache miss occurs, a burst transfer access is started for reading data for one line of the cache. Reading data for 256 bits is performed by performing only one burst transfer access, composed of four bus cycles with the bus width of the external data bus 10 being 64 bits.
An explanation will now be given of operation for reading data using a burst transfer access in the case where the required first data 701 has addresses in the range shown in FIG. 7, (for example, the address thereof being "000A" and the data length thereof being 64 bits) and a cache miss occurs. FIG. 8 is a timing chart of the operation.
At the first cycle of burst transfer access data within the bounds of a 64-bit group, in which the first data 701 exists and whose head addresses is "0008" are accessed. In the following accesses, the remaining data within the bounds of the 256-bit group having the first data 701, are successively accessed by wrapping around. Accordingly, burst transfer access is executed in the order of addresses: "0008".fwdarw."0010".fwdarw."0018".fwdarw."0000".
The data given to the external data bus D (0:63) 10 and the D bus 12 shown in FIG. 8(h) and FIG. 8(k) are 64-bit data 801, 802, 803, 804, and 811, 812, 813, 814, respectively, starting from addresses "0008", "0010", "0018", "0000" in order.
The alignment circuit 3 is operated according to the case in FIG. 5 where there is a 64-bit data bus width, the third bit from the lower side of the address being "0". The higher 32 bits of the D bus 12, in the first cycle accessing the address "0008", are latched by the 4A register 40 of the 88 bit register 400, and the lower 32 bits thereof are latched by the 4B register 41 of the same, respectively. The higher 32 bits of the D bus 12 in the second cycle accessing the address "0010" are latched by the 4C register 42.
The bus cycle finishing signal shown in FIG. 8(j) indicates that effective data is on the D bus 12, as well as indicating one end of a bus cycle. The data is latched by registers in the alignment circuit 3 and the cache memory 4 while the signal is asserted. According to the operation, the first data 701 is held by the 4A, 4B, 4C registers 40, 41, 42 which make up the 88-bit register 400, and the 88-bit data is then aligned by the shifter 43 and latched by the register 44 to be outputted to the S bus 13.
In the cache memory 4, the data having been read by a burst transfer access is latched in order by the data registering register 50. Since the addresses to accessed is in order of "0008".fwdarw."0010".fwdarw."0018".fwdarw."0000", the higher 32 bits of the D bus 12 in the first cycle are latched by register 5C of the data registering register 50, the lower 32 bits are latched by register 5D, the higher 32 bits of the D bus 12 in the second cycle are latched by register 5E, the lower 32 bits are latched by register 5F, the higher 32 bits of the D bus 12 in the third cycle are latched by register 5G, the lower 32 bits are latched by register 5H, the higher 32 bits of the D bus 12 in the fourth cycle are latched by register 5A, and the lower 32 bits are latched by register 5B.
Since the bus cycle finishing signal shown in FIG. 8(j) indicates that effective data is on the D bus 12 as well as indicating the end of a bus cycle, the data are latched by each register while the signal is asserted.
When the fourth cycle is finished, the data is registered in the cache memory 4. Accordingly, within the bounds of data the 256-bit group including the first data 701 are registered in the cache.
In the following, an explanation will be given of operation for reading data according to a burst transfer access in the case where the second required 702 has data addresses in the range shown in FIG. 7, (for example, the address thereof being "000E" and the data length thereof being 64 bits) and a cache miss occurs. In the first cycle of the burst transfer access, data within the boundary of the 64-bit group in which the second data 702 exists and whose address is "0008" are accessed by wrapping around. This case is identical to the case where the first data 701 is read. The method for registering in the cache memory 4 is also the same. But the operation of the alignment circuit 3 is different.
The alignment circuit 3 is operated according to the case in FIG. 5 where there is a 64-bit data bus width and the third bit from the lower side of the address is "1". The lower 32 bits of the D bus 12 in the first cycle accessing the address "0008", are latched by the 4A register 40 The higher 32 bits of the D bus 12 of the second cycle accessing the address "0010" are latched by the 4B register 41, and the lower 32 bits are latched by the 4C register 42. According to this operation, the second data is held by the 4A, 4B, 4C registers 40, 41, 42 configuring the 88-bit register 400. The 88-bit data held by the data registering register 50 is aligned by the shifter 43 and then latched by the register 44 to be outputted to the S bus 13.
In the following, an explanation will be given of the case where the bus width of the external data bus 10 is 32 bits. At the time that a cache miss occurs, burst transfer accesses are started two times in order to read data for one line of the cache. Two burst transfer accesses, each composed of four bus cycles with the bus width of the external data bus 10 being 32 bits, allows a read data of 256 bits.
An explanation will next be given of the operation for reading data according to burst transfer accesses in the case where the first data required 701 has addresses in the range shown in FIG. 7 (for example, the address thereof being "000A" and the data length thereof being 64 bits), and a cache miss occurs. FIG. 9 is a timing chart showing the operation.
At the first cycle of the first burst transfer access data within the bounds of the 32-bit group, in which the remaining first data 701 exists and whose head address is "0008", are accessed. In the following accesses the remainder of data within the 128-bit group is successively accessed by wrapping around.
At the first cycle of the second burst transfer access, data within the bounds of the 32 bit group, in which the remaining first data exits and whose head address is "0010", are accessed In the following accesses, the remainder of data within the bounds of the 128 bit group are successively accessed by wrapping around.
Accordingly, the first burst transfer access is performed in the order of addresses: "0008".fwdarw."000C".fwdarw."0000".fwdarw."0004" and the second burst access is performed in the order of addresses: "0010".fwdarw."0014".fwdarw."0018".fwdarw."001C", respectively.
The data 901 through 908 and 911-918 given to the external data bus D (0:63) 10 and D bus 12 shown in FIG. 9(h) and (k), respectively, are 32-bit data starting from "0008", "000C", "0000", "0004", "0010", "0014", "0018", and "001C". Each of the data 901-908 is on the buses 10L and 12L, i.e., the lower 32-bits of the data buses.
The alignment circuit 3 is operated according to the case in FIG. 7 where there is a 32-bit data bus width. The lower 32 bits of the D bus 12 in the first cycle of the first burst transfer access where the address "0008" is accessed, is latched by the 4A register 40. The lower 32 bits of the D bus 12 in the second cycle where the address "000C" is addressed, are latched by the 4B register 41. The lower 32 bits of the D bus 12 in the first cycle of the second burst transfer access where the address "0010" is accessed, are latched by the 4C register 42.
The bus cycle finish signal shown in FIG. 9(j) indicates that effective data is on the D bus 12, as well as indicating the end of a bus cycle. The data is latched by registers in the alignment circuit 3 and the cache memory 4 while this signal is asserted. According to this operation, the first data 701 is held by the 4A, 4B, 4C registers 40, 41, 42 which make up the 88-bit register 400. This 88-bit data is latched by the register 44 after it is aligned by the shifter 43 to be outputted to the S bus 13.
In the cache memory 4, the data read during burst transfer access is latched sequentially in the data registering register 50. Since the order of the addresses to be accessed in the first burst transfer access is "0008".fwdarw."000C".fwdarw."0000".fwdarw."0004", the lower 32 bits of the D bus 12 in the first cycle are latched by register 5C of the data registering register 50, the lower 32 bits of the D bus 12 in the second cycle are latched by register 5D, the lower 32 bits of the D bus 12 in the third cycle are latched by register 5A, and the lower 32 bits of the D bus 12 in the fourth cycle are latched by register 5B. Since the order of the addresses to be accessed in the second burst transfer access is "0010".fwdarw."0014".fwdarw."0018".fwdarw."001C" the lower 32 bits of the D bus 12 in the first cycle are latched by register 5E of the data registering register 50, the lower 32 bits of the D bus 12 in the second cycle are latched by register 5F, the lower 32 bits of the D bus 12 in the third cycle are latched by register 5G and the lower 32 bits of the D bus 12 in the fourth cycle are latched by register 5H.
The bus cycle finish signal shown in FIG. 9(j) indicates that effective data is on the D bus 12 as well as indicating an end of a bus cycle. The data is latched in the register while this signal is asserted.
When the fourth cycle of the second burst transfer access is finished, data is registered in the cache memory 4. Thus, data within the bounds of the 256-bit group, including the first data, 701 is registered in the cache.
An explanation will next be given of the operation in which data is read by a burst transfer access in the cache where required second data 702 has addresses in the range shown in FIG. 7, the address thereof being "000E" and the data length thereof being 64 bits and where a cache miss occurs.
At the first cycle of the first burst transfer access data within the bounds of the 32-bit group, in which the first data 701 exists and whose head address is "000C", is accessed. In the succeeding accesses, the remaining data within the bounds of the 128-bit group having the first data 701 are sequentially accessed by wrapping around. Accordingly, the first burst transfer access is performed in the order of addresses: "000C".fwdarw."0000".fwdarw."0004".fwdarw."0008". The second burst transfer access is the same as the case of the first data 701. Since the order of the addresses in the first transfer accessing is different, the operation at the alignment circuit 3 and the operation of registering to the cache memory 4 are also different.
The alignment circuit 3 is operated identically to the case where there is a 32-bit data bus width, shown in FIG. 5. The lower 32 bits of the D bus 12 during the first cycle of the first burst transfer access, where the address "000C" is accessed, is latched by register 4A (40). The lower 32 bits of the D bus 12 in the second cycle of the second burst transfer access where the address "0010" is accessed, is latched by register 4B (41). The lower 32 bits of the D bus 12 during the second burst transfer access where the address "0014" is accessed, is latched by register 4C (42).
In the cache memory 4, the data read by burst transfer access is sequentially latched in the data registering register 50. Since the order of the addresses to be accessed in the first transfer access is "000C".fwdarw."0000".fwdarw."0004".fwdarw."0008", the lower 32 bits of the D bus 12 during the first cycle are latched by register 5D of the data registering register 50, the lower 32 bits of the D bus 12 during the second cycle are latched by register 5A, the lower 32 bits of the D bus 12 during the third cycle are latched by register 5B, and the lower 32 bits of the D bus 12 during the fourth cycle are latched by register 5C. Since the order of the addresses to be accessed in the second burst transfer accessing is "0010".fwdarw."0014".fwdarw."0018".fwdarw."001C", the lower 32 bits of the D bus 12 during the first cycle are latched by register 5E of the data registering register 50, the lower 32 bits of the D bus 12 during the second cycle are latched by register 5F, the lower 32 bits of the D bus 12 during the third cycle are latched by register 5G, and the lower 32 bits of the D bus 12 during the fourth cycle are latched by register 5H.
When the fourth cycle of the second burst transfer access is finished, data is registered in the cache memory 4. Thus, data which is within the bounds of the 256-bit group including the second data 702 are registered in the cache.
In the conventional data processor, the controlling method of the internal function circuits such as alignment circuit, cache memory, and internal data operation circuit, is changed to correspond to the bus width of the external data bus (which can be changed according to the static bus-sizing function). And, as aforementioned, in order to read only the data required for registering to the cache memory, the data processor is so operated as to change the number of times burst transfer access is performed, responsive to the bus width of the external data bus. The internal data operation circuit transmits addresses to the bus interface to request accessing. The internal data operation circuit, however, so controls as to request only one access when the bus width of the external data bus to be used is 64 bits and to request two accesses when the bus width thereof is 32 bits.
Accordingly, in the conventional data processor, it is necessary for the internal function circuit of the microprocessor to be operated under the control of different procedures corresponding to the bus width of the external data bus indicated by the bus-sizing function. Because of this, the internal function circuit is complicated.