1. Field of the Invention
The present invention relates generally to the fabrication of integrated circuit devices, and more particularly to a technique for reducing junction capacitances in field effect transistors.
2. Description of the Prior Art
Integrated circuit device geometries well below one micron feature sizes continue to become increasingly common. In general, the use of smaller devices on integrated circuit chips results in better performance and high packing density, thereby reducing cost while increasing performance. However, with such small feature sizes device performance is significantly adversely impacted by physical effects which can be largely ignored with larger devices. Therefore, transistor reliability becomes an important issue in the sub-micron regime.
One problem which is important for small geometry devices is known as the hot electron effect. This effect refers generally to the injection of energetic electrons from the channel region into the gate, causing degradation at transistor parameters such as threshold voltage and transconductants, therefore resulting in worse performance. The effect is more pronounced for n-channel devices. Numerous transistor designs have been proposed and investigated in order to solve the hot electron injection problem.
One approach to dealing with the hot electron effect utilizes lightly doped drains (LDD) and a halo implant. Halo implants are moderately doped implants of the same conductivity type as the well or substrate in which the transistor is formed, and which lie in a thin layer generally along the source/drain to substrate/well junctions. A combination of LDD structures and halo implants has proven to achieve good device performance and reliability. However, due to the extra impurities used to form the halo in the junction areas, higher junction capacitances are obtained. This is true for both n-channel and p-channel devices. These increased junction capacitances tend to adversely impact transistor switching speeds.
It would be desirable to provide a method for fabricating integrated circuit transistors which provides good protection from hot electron effects. It is further desirable for such a method to minimize source/drain capacitances to improve operating speeds for the device.