1. Field of the Invention
The present invention relates to a manufacturing method and device of a semi conductor integrated circuit device.
2. Description of the Related Art
The manufacture of semiconductor integrated circuit devices requires meticulous and careful attention to circuit planning and production procedures. To assist in the development of semiconductor devices having greater circuit density and integration, a large scale integration design tool such as a computer aided design program (hereinafter referred to as CAD), etc., is utilized during a circuits's planning stage. During the planning stage, it is common for the CAD to automatically determine a particular circuit cell's location on a semiconductor chip. The CAD's positioning of numerous cells is usually determined as a function of cell terminal and input signal location. More particularly, cell placement is determined by the CAD's calculation of a maximum delay time misalignment value. This value is set by considering signal transmission delay between the input and output terminals of associated circuit cells.
Theoretically the signal delay for of the each planned calls should never exceed a maximum misalignment value. Despite the use of current CAD tools, however, delay time misalignment still exists. Even with carefully planned circuit cell placement, therefore, optimizing the placement of wiring between associated circuit cells can be a difficult problem to overcome during the circuit's planning stage.
The present invention was developed in consideration of the foregoing conditions. It is a primary objective of the present invention to realize a properly assigned wiring length in the design of circuit cells for integrated semiconductor circuits that optimizes cell placement and the timing of the input signals to the individual circuit cells.