Many DC-to-DC power converters may be conceptualized by the circuit illustrated in FIG. 1A, where electrical power from a source having a supply voltage VIN is provided to load 102 such that the load voltage is regulated to some voltage less than VIN. A feedback path is provided from node 103 to controller 104, where controller 104 controls the duty cycle of high-side switch 106 and low-side switch 108 to regulate the load voltage. A second-order low pass filter comprising inductor 110 and capacitor 112 couples load 102 to switch point 114 so as to smooth output ripples. In practice, the circuit components in FIG. 1, except for inductor 110, capacitor 112, and load 102, are integrated on a single silicon die. The operating principles for the circuit of FIG. 1 are well known to those skilled in the art of power converters, and need not be repeated here.
For some consumer applications, the supply voltage VIN may peak to several hundred volts, in which case the voltage drop across switch 106 or 108 may also peak to several hundred volts. Accordingly, for such applications, switches 106 and 108 should be designed to operate under such high voltage drops.
Some circuit components within controller 104 may need to derive their power from the supply voltage VIN, but are designed to operate only over voltage drops on the order of ten volts. A JFET (Junction Field Effect Transistor) may serve as a voltage source for such low voltage components, where the JFET is powered by the supply voltage VIN. A generic application is illustrated in FIG. 1B, where the drain of JFET 116 is at the supply voltage VIN, and its source is connected to load 118. The source voltage developed at node 120 (the source terminal or port) is denote as VS. With gate 122 grounded, the source voltage developed at node 120 is such that the load current through load 118 matches the drain-source current through JFET 116. Stated more formally, if the drain-source current IDS of JFET 116 is given by IDS=f(VGS, VDS) where VGS is the gate-to-source voltage and VDS is the drain-to-source voltage of JFET 116, and if the load current IL through load 118 satisfies IL=Y(VS), then the source voltage VS is such that Y(VS)=f(−VS, VIN−VS).
A JFET that can withstand a drain-source voltage drop of several hundred volts, but prevent its source terminal from exceeding a voltage in the range of tens of volts above ground potential, has utility in DC-to-DC power converters, as well as in other applications.