1. Field of the Invention
The invention relates to integrated circuitry for writing data to a magnetic medium, and more particularly to techniques for generating a precompensation delay in the path of the data stream.
2. Description of Related Art
Data is recorded on magnetic media, such as floppy disks and hard disks, in the form of present or absent flux reversals. These flux reversals have a minimum linear separation which is dependent upon the data rate, the encoding format and the speed with which the medium moves past the write head.
The pattern of flux reversals is generated from an incoming data stream by an encoder, which may use any of several standard encoding formats to generate the pattern. Two popular encoding formats are known as FM and MFM, each of which generate an outgoing pulse stream divided into bit cells consisting of a clock pulse and/or a data pulse for each bit of the incoming data stream. As used herein, a pulse stream is merely one type of data stream. In FM encoding, a bit cell always begins with a clock pulse. If the incoming data bit is a 1, a data pulse is also inserted in the middle of the bit cell. If the data bit is 0, no data pulse is inserted. For FM encoding, therefore, a clock pulse and a data pulse can both be present within the bit cell. Since each pulse causes a flux reversal on the disk, the minimum linear separation between flux reversals is one-half the bit cell length.
In MFM encoding, like FM encoding, a data pulse is inserted in the middle of the bit cell if and only if the incoming data bit is 1. Unlike FM encoding, however, a clock pulse is inserted at the beginning of a bit cell if and only if both the present and previous incoming data bits are 0. The minimum linear separation between flux reversals for MFM encoding therefore is one full bit cell length. Because of this, MFM-encoded data is usually given twice the bit cell density and data rate as FM-encoded data recorded on the same medium.
A double density floppy disk typically operates at a data rate of 500 kbits/sec with MFM-encoded data, and has a bit cell time of 2.mu.S. A hard disk may operate at about 5 Mbits/sec, yielding a bit cell time of 200nS.
For higher bit density media, nearby flux changes may interact with each other and cause them to move farther apart. This creates a timing uncertainty which can cause errors when data is read. To overcome this problem, the outgoing data stream may be precompensated before being written. That is, the direction of each shift may be anticipated and the pulse in the outgoing data stream moved in the other direction before being sent to the write head. Typical precompensation periods in present use are 2-20nS for hard disks and 50-150nS for 5-1/4" floppy disks.
In the past, precompensation was typically accomplished by feeding the outgoing pulse stream into a fixed, center-tapped delay line external to the chip which performed the encoding. a data selector was then used to select the signal from either the input, center tap, or output of the delay line, depending on whether the pulse was to be written early, nominal or late, respectively. This technique is described, for example, in Szejnwald, "Simplify Hard-Disk Interfaces With a VLSI Controller," EDN, Nov. 24, 1982, pp. 133-147, at 136-138, with respect to the NEC .mu.PD7261. The technique is disadvantageous, however, because it requires the designer to know in advance exactly what precompensation delay period will be used in terms of an absolute number of nanoseconds. It does not permit easy electronic adjustment of the precompensation delay period. For example, bit shifting is more serious on inner tracks of a disk than on outer tracks because the flux reversals are closer together. The NEC technique does not permit easy adjustment of the delay period to compensate for this as the write head changes tracks on the disk. Nor can the NEC technique be used with constant density recording, which requires the delay period to change dynamically as a function of the bit rate.
In Stout, "Winchester Electronic Functions Fit on Four High-Speed Chips," Electronics, June 16, 1982, pp. 117-123, at 122, there is described a National Semiconductor chip which generates a precompensation delay internally, with a period which is externally programmable for 0 to 20nS in 2nS steps. External programmability alleviates some problems with the NEC chip, but the delay period is still specified in terms of an absolute number of nanoseconds which does not change as a function of the bit rate. The National technique also requires many I/0 pins to implement and requires the use of an external reference frequency source. The method by which the delay is actually generated is not disclosed.