1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having a capacitor and a method of manufacturing the same.
2. Description of the Prior Art
As one of nonvolatile memories that can store information after the power supply is turned OFF, FeRAM (Ferroelectric Random Access Memory) having a ferroelectric substance is known. Since FeRAM has a structure that stores the information by utilizing the hysteresis characteristic of the ferroelectric substance and can be operated at high speed at a low consumption power, its further development is expected in the future as the nonvolatile memory which is subjected to a large number of writing operations.
FIG. 1 shows an example of a circuit diagram of a memory cell of FeRAM. This view is a circuit diagram of a 1T1C-type memory cell that employs one transistor To and one capacitor Co to store 1-bit information.
The 1T1C-type memory cell needs a reference capacitor C1 that generates a reference voltage to decide the charge read from the memory cell is “1” data or “0” data. The polarization of the reference capacitor C1 is reversed every time when the data are read. The decision of data is executed based on the level of potential of a capacitor C0 of each memory cell with respect to potential of the reference capacitor C1. The reference capacitor C1 is connected to an end portion of each bit line BIT. It is preferable that ideally the potential of the reference capacitor C1 should be set to an intermediate value between a voltage V1, which is used to write “1” into the memory cell, and a voltage V0, which is used to write “0” into the memory cell.
As the memory cell, there is a 2T2C-type memory cell in addition to the 1T1C-type memory cell. The 2T2C-type memory cell is of the type that employs two transistors and two capacitors to store 1-bit information. Such 2T2C-type memory cell has a circuit configuration that executes a complementary operation such that “1” or “0” data is stored in one capacitor and opposite data is stored in the other capacitor, and reads polarized states of both capacitors upon deciding the data to execute the decision of data by using a difference between them.
The 1T1C-type memory cell can reduce a cell area to about half rather than the 2T2C-type memory cell.
Next, a configuration of the 1T1C-type memory cell will be explained hereunder. FIG. 2 is a plan view of the 1T1C-type memory cell, and FIG. 3 shows a sectional view taken along a I-I line in FIG. 2. In this case, illustration of interlayer insulating films on a semiconductor substrate is omitted in FIG. 2.
In FIG. 2 and FIG. 3, a plurality of active regions (wells) 103, each of which is surrounded by an element isolation layer 102, are formed vertically and horizontally at an interval on a surface layer of a semiconductor substrate 101. Two gate electrodes 105, which are also used as word lines WL extended in the Y direction, are formed on each active region 103 via a gate insulating film 104. The word line WL is formed to extend onto the element isolation layer 102. In each active region 103, first to third impurity diffusion regions 107a, 107b, 107c are formed on both sides of two gate electrodes 105.
One gate electrode 105 and the impurity diffusion regions 107a, 107b on both sides of the electrode constitute one MOS transistor To, and the other gate electrode 105 and the impurity diffusion regions 107b, 107c on both sides of the electrode constitute another MOS transistor To. That is, two transistors are formed in each active region 103.
The transistor To and the element isolation layer 102 are covered with an insulating cover film 108. Also, a first interlayer insulating film 109 is formed on the insulating cover film 108.
A plurality of stripe-like capacitor lower electrodes 111 that extend in the Y direction are formed on the first interlayer insulating film 109 and over the element isolation layer 102 in the X direction at an interval. Then, ferroelectric films 112 each having the substantially same shape as the capacitor lower electrode 111 are formed on the capacitor lower electrodes 111. Then, a plurality of capacitor upper electrodes 113 are aligned on each ferroelectric film 112 in the Y direction. One capacitor upper electrode 113, the underlying ferroelectric film 112, and the capacitor lower electrode 111 constitute one capacitor Co.
Also, a second interlayer insulating film 114 is formed on the capacitor Co and the first interlayer insulating film 109. Then, first to third contact holes 114a, 114b, 114c are formed in the first and second interlayer insulating films 109, 114 and the insulating cover film 108 on the first to third impurity diffusion regions 107a, 107b, 107c in the active region 103. Then, first to third conductive plugs 115a, 115b, 115c are formed in the first to third contact holes 114a, 114b, 114c respectively. Then, fourth contact holes 114d are formed in the second interlayer insulating film 114 on the capacitor upper electrodes 113, and then fourth conductive plugs 115d are formed in the fourth contact holes 114d. 
A first metal wiring 116a that connects the first contact hole 114a and the neighboring fourth conductive plug 115d is formed on the second interlayer insulating film 114. Also, a second metal wiring 116c that connects the third contact hole 114c and the neighboring fourth conductive plug 115d is formed on the second interlayer insulating film 114.
Accordingly, a plurality of capacitor upper electrodes 113, which are aligned over each capacitor lower electrode 111, are connected to MOS transistors To on the silicon substrate 101 on a one-by-one basis respectively.
In this case, a metal pad 116b is formed in the second interlayer insulating film 114 on the second conductive plug 115b. A bit line 117 that is formed over the metal pad 116b via a third interlayer insulating film (not shown) is connected to the metal pad 116b. The bit line 117 extends in the direction that intersects orthogonally with the word line WL and the capacitor lower electrode 111 respectively.
Meanwhile, the above capacitor is formed by methods described in the following.
The first method is such a method that a first conductive film, a ferroelectric film, and a second conductive film are formed sequentially on the first interlayer insulating film 109, then the capacitor upper electrodes 113 are formed by patterning the second conductive film, and then the ferroelectric films 112 and the capacitor lower electrodes 111 are formed by patterning the ferroelectric film and the first conductive film while using the same mask.
The second method is such a method that the first conductive film, the ferroelectric film, and the second conductive film are formed sequentially on the first interlayer insulating film 109, then the capacitor upper electrodes 113 are formed by patterning the second conductive film and the ferroelectric film while using the same mask, and then the capacitor lower electrodes 111 are formed by patterning the first conductive film.
The third method is such a method that the first conductive film, the ferroelectric film, and the second conductive film are formed sequentially on the first interlayer insulating film 109, and then the capacitor upper electrodes 113, the ferroelectric films 112 and the capacitor lower electrodes 111 are formed by patterning individually the first conductive film, the ferroelectric film, and the second conductive film while using separate masks respectively.
According to the first, second, and third methods, since the capacitor lower electrodes 111 are formed after the capacitor upper electrodes 113 are formed, there is a chance that areas of the capacitor upper electrodes 113 are reduced by the displacement of the mask that is used to pattern the capacitor lower electrodes 111. In order to prevent the reduction of the capacitor upper electrodes 113, the capacitor lower electrodes 111 may be formed widely. But this structure disturbs the higher integration of the memory cell regions.
Also, according to the second method, since the capacitor lower electrodes 111 are exposed from the ferroelectric films 112 in regions between the capacitor upper electrodes 113 on the capacitor lower electrodes 111, there is a chance that reduction of the capacitors is accelerated by the catalytic action of platinum that constitutes the capacitor lower electrodes 111.
In addition, according to the third method, since the capacitor upper electrodes 113, the ferroelectric films 112, and the capacitor lower electrodes 111 are formed by using separate masks, throughput is lowered.