ESD protection has been a main concern in the reliability of integrated circuit (IC) products in submicron complimentary metal-oxide-silicon (CMOS) technologies. For example, drain diffusion regions in N-type metal-oxide-silicon (NMOS) and P-type metal-oxide silicon (PMOS) transistors in output buffers of a CMOS IC are often directly connected to output pads of the IC in order to drive external loads of the IC, causing the CMOS output buffers to be vulnerable to ESD damage.
Lateral semiconductor-controlled rectifier (SCR) devices have been widely used in ESD-protection structures for input protection in submicrometer CMOS IC's. See R. N. Rountree, et al., “A Process-Tolerant Input Protection Circuit for Advanced CMOS Processes,” 1988 EOS/ESD Symposium Proceedings, p. 201. For the output buffers, a low-voltage triggering SCR (LVTSCR) with an inserted NMOS transistor in a lateral SCR structure has been used to provide a much lower trigger voltage than a conventional SCR. As shown in FIG. 1, such a device comprises a PNP transistor 110, an NPN transistor 120 and an NMOS transistor 130 with the base of the PNP transistor connected to the collector of the NPN transistor, the base of the NPN transistor connected to the collector of the PNP transistor and the source and drain of the NMOS transistor connected between the collector and emitter of the PNP transistor. The inserted NMOS transistor in the LVTSCR is designed with its gate grounded to provide a low breakdown voltage for the drain-substrate diode at the gate edge. The low breakdown voltage leads to a low trigger voltage for the LVTSCR. Thus the ESD trigger voltage of the LVTSCR device is equivalent to a snap-back trigger voltage of the inserted short-channel NMOS transistor, which is typically much lower than a switching voltage of the original lateral SCR device. See A. Chatterjee, et al., “A Low-Voltage Triggering SCR for On-chip ESD Protection at Output and Input Pad,” IEEE Electron Device Letters, Vol. 12, No. 1, January 1991, p. 21. However, the LVTSCR device can have a higher than desirable capacitance due to the usage of the NMOS transistor as the trigger device.
Several additional triggering arrangements are disclosed in M. P. J. Mergens et al., “Diode-Triggered SCR (DTSCR) for RF-ESD Protection of BiCMOS SiGe HBTs and CMOS Ultra-Thin Gate Oxides,” IEEE (2003) and U.S. Pat. No. 6,850,397. These include a stack of diodes connected across the emitter and collector of the PNP transistor. The use of diode triggers, however, raises many issues in circuit design. Diodes have a very strong temperature dependence which could lead to different results at different temperatures. The diodes must be used in increments of one forward biased diode voltage drop which does not allow for fine tuning of the trigger voltage. The number of diodes used in a stack must be small enough to ensure that the SCR triggers before oxide breaks down at room temperature; but if the number of diodes used is too small, excessive leakage will occur under normal operation conditions at high temperatures.