1. Field of the Invention
The present disclosure generally relates to techniques for testing semiconductor devices, and, more particularly, to techniques for testing integrated circuits that include logic circuitry portions and embedded memory portions with memory built-in self-test logics connected thereto.
2. Description of the Related Art
In manufacturing semiconductor devices including relatively complex circuitry, the testing of the device may represent a part of the manufacturing process which is frequently underestimated in terms of cost and effort required to obtain reliable data with respect to proper functionality and reliability of the device. One reason in failing to meet performance specifications of the integrated circuit may reside in design errors that may be identified and remedied by circuit verification on the basis of software simulation and/or prototype testing prior to mass production of the integrated circuits under consideration. An improper functionality of the integrated circuit may further be caused by the manufacturing process itself when the completed circuitry does not correspond to the verified circuit design owing to process fluctuations in one or more of the very large number of process steps. Although measurement and test procedures are incorporated at many points in the manufacturing process, it is nevertheless extremely important to ascertain the correct functioning of the final semiconductor device, since, according to a common rule of thumb, the costs caused by defective chips increase with each assembly phase by approximately one order of magnitude. For example, the costs caused by a defective circuit board including a faulty chip are typically significantly higher than identifying a defective chip prior to shipping and assembling the circuit board. The same holds true for a system, when a failure thereof is caused by one or more defective circuit boards, as a downtime of an industrial system may result in averaged costs of approximately several hundred dollars per minute compared to a price of a few dollars for an integrated circuit chip having caused the defect.
Hence, there is a vital interest in developing test procedures to identify as many defects as possible in completed integrated circuits while not unduly increasing the total manufacturing costs. In particular, with the demand for more features and lower costs of circuits, there is a tendency to integrate a plurality of different circuit portions into a single chip to provide a complete system on a chip (SOC). A semiconductor device comprising various functional blocks may typically include, in addition to one or more logic blocks, one or more embedded memory portions, such as are used as on-chip cache for CPUs or as buffers for data packets that are transferred between different clock domains.
As discussed above, economic constraints force semiconductor manufacturers to not only minimize the defect level of the total manufacturing process, but also to provide, in combination with a reduced defect level, a high fault coverage so as to reduce the delivery of defective chips at reasonable cost for appropriate test procedures and techniques. For moderately complex integrated circuits, it has become standard practice to develop the basic design of the circuit while taking into consideration a plurality of constraints posed by effective test procedures. Moreover, typically, additional hardware resources are provided in the chip that may enable the identification of faulty circuit components for a broad class of operating conditions, wherein the additional hardware resources, in combination with design specifics of the basic circuit and sophisticated test procedures and test patterns, substantially determine the fault coverage of the test procedure.
In many circuit designs, the functional logic portion is tested by so-called scan chains, which represent a chain of flip-flops connected to a specific area of the functional logic in such a way that the functional logic or a specific area thereof may be initialized with a desired state that has previously been entered into the scan chain. Moreover, upon providing one or more clock signals to the functional logic, the state thereof, that is the state of each logic gate connected to a dedicated flip-flop of the scan chain, may then be stored in the scan chain and may be shifted out by supplying respective shift clock signals to the scan chain. Depending on the bit pattern or input vector entered into the scan chain for initializing the functional logic, corresponding faulty logic gates may be identified. However, the fault coverage, i.e., the potential for identifying any error within the functional logic, significantly depends on the design, selection and number of appropriate scan chains and suitable input vectors. In principle, such scan test techniques may also be modified to include the testing of memory portions, wherein, however, only for small memories, appropriate scan test patterns, i.e., the number and size of appropriate input vectors, may exhibit a size that allows the testing of memory portions within acceptable time intervals.
For this reason, frequently, a so-called memory built-in self-test (MBIST) logic is provided as an additional hardware resource within a chip to implement a memory test procedure requiring fewer clock cycles and supporting the testing of important extended fault models that are specific to memories. With reference to FIGS. 1a-1c, the configuration and the test procedures for a representative conventional semiconductor device including functional logic and a memory portion are described in more detail so as to more clearly illustrate the problems involved.
FIG. 1a schematically shows a circuit diagram of a semiconductor device 100 including a functional logic circuitry 110, which may be connected to a memory portion 120 via write lines, read lines and control lines that are commonly referred to as lines 121. The device 100 further comprises an MBIST logic 130 including, for instance, a finite state machine 131 for implementing a desired algorithm for testing the memory portion 120. The MBIST logic 130 further comprises all components required for disconnecting the memory portion 120 from the functional logic 110 so as to enable the operation of the memory portion 120 fully under control of the MBIST logic 130 when operating the logic 130 for the memory test.
On the other hand, when disabled, the MBIST logic 130 is “transparent” for the lines 121 to allow proper operation of the logic circuitry 110 in combination with the memory portion 120. The MBIST logic 130 comprises a first control input 132, which is also referred to as MBIST-start, and a second control input 133, also indicated in the drawing as MBIST-enable. Moreover, a first output 134, also referred to in the drawing as MBIST-good, and a second output 135, also indicated as MBIST-done, are provided in the MBIST logic 130. It should be noted that, for convenience, any additional inputs or outputs of the logic 130, such as clock inputs, reset inputs and other control lines, are not shown.
When operating the device 100 in a memory test mode, the MBIST logic 130 may be enabled by providing a corresponding signal at the input 133 (MBIST-enable) to disconnect the memory portion 120 from the surrounding logic circuitry 110. By supplying a corresponding signal at the input 132 (MBIST-start), the circuit portion 130 is started to generate address values and to write data into the memory portion 120. The circuit 130 may also include a comparator, which may be configured to check if the data written into the memory 120 may be correctly read back from the memory, and which may provide a corresponding value at the output 134 (MBIST-good). For instance, the value of the output 134 may show logic “0” as long as no error occurs in writing data into the memory 120 and reading back the data, while the output 134 may be set to a logic “1” once a mismatch between the actually read data and the expected data is detected. After the test of the memory 120 is completed, a corresponding signal may be presented at the output 135 (MBIST-done), for instance, the output 135 may be switched from logic “0” to logic “1” if the test is completed.
FIG. 1b schematically illustrates the semiconductor device 100 which may comprise a plurality of embedded memories 120A, 120B that are connected to corresponding portions of the built-in test circuitry. For example, each of the memory portions 120A, 120B may be connected to a corresponding “glue logic” 140A, 140B, which may provide control and data signals to the memory 120A, 120B during a corresponding test phase and which may provide the desired transparency of the built-in test circuitry in a standard operating mode, as previously discussed. Moreover, corresponding circuit portions 160A, 160B may connect to the glue logics 140A, 140B, respectively, in order to provide appropriate control signals and test data patterns as required by the test algorithm under consideration. For convenience, the circuit portions 160A, 160B may also be referred to as “slaves,” which in turn may be controlled by an MBIST controller 138, which in turn may be configured to provide appropriate operation code sequences for performing a desired sequence of memory operations in each of the memories 120A, 120B and which may also provide the required test data patterns. It should be appreciated that a plurality of test algorithms are presently used, each of which may provide a certain degree of fault coverage with respect to individual memory cells and also corresponding circuit components for controlling the memory arrays. For example, test algorithms may be applied in which each memory cell may be written to and may be read out according to a specified addressing scheme, while in other cases appropriate patterns may be written into the memory array, such as a checkerboard pattern and the like, in order to determine the static and dynamic behavior of the memory area and the associated circuitry for performing the read and write operations. It should be appreciated that respective test algorithms may be specifically designed for certain types of memories, technology standards used for actually fabricating the memories and the like, so that, with a change in memory design, technology and the like, appropriately adapted test algorithms may be required. Consequently, in many built-in test circuits, a certain degree of flexibility may be provided so as to allow the employment of different types of test algorithms, if required.
During operation, the semiconductor device 100 in a memory test operating mode, the controller 138 may instruct one or more of the slaves 160A, 160B to initiate a memory self-test by providing a corresponding sequence of instructions, such as memory addresses and respective control signals in combination with the desired test data pattern, which may be accomplished by conveying the signals via bus lines 150A, 150B, which may also include appropriate bus lines for conveying a failure signal from the glue logic 140A, 140B to the slaves 160A, 160B. It should be appreciated that the signal transmission via the busses 150A, 150B may typically be associated with a certain latency, i.e., the transport of the signal may require a specified number of clock cycles corresponding to the number of pipeline stages that may typically be used in order to relax time constraints as may typically occur in sophisticated semiconductor devices, which may be operated with clock frequencies of several hundred megahertz and significantly higher. Consequently, the point in time of issuing a certain memory operation from the slave 160A, 160B to the glue logic 140A, 140B may differ from the point in time when a corresponding memory operation may actually be served in the memory 120A, 120B. Upon executing the memory operations, for instance writing a specified data pattern into the memory array 120A, 120B and reading back the corresponding data according to a specified test algorithm, a comparison may be made between the originally written bus data and the data read out from the memory 120A, 120B and thereby detecting corresponding memory failures depending on the test algorithm used. The comparison result, for instance, obtained on the basis of a comparing logic 141A may then be forwarded to the slave 160A, 160B, which may also require a certain number clock cycles, depending on the overall configuration of the buses 150A, 150B, as previously explained. For an enhanced evaluation of any memory failures that may be detected during the test algorithm under consideration, at least the correspondence between a failure signal obtained in the slave 160A, 160B and a corresponding memory operation causing the failure signal may have to be determined, which, however, requires an appropriate adaptation of the various time delays involved in transferring the operation code instructions, the test data patterns and the failure signals from the slave 160A, 160B to the glue logic 140A, 140B and back to the slave. Moreover, in many cases, additional information is obtained, for instance, the form of each of the comparison results 141A obtained from the memory 120A at the point in time where a certain memory failure, for instance a read memory failure, is detected. For example, this information may be read out and may finally be transferred to the controller 138, from which the single global failure signal 135 may be obtained, for instance for an external test equipment, and also a corresponding bitmap 138A may also be supplied to an external test equipment via any appropriate interface system.
FIG. 1c schematically illustrates a portion of the semiconductor device 100 including the memory portion 120A and the glue logic 140A, the control and data busses 150A and the slave circuit 160A. As illustrated, the slave circuit 160A comprises a decode unit 166, which represents any appropriate circuit for providing control and operating code data 161 to the glue logic 140A. For example, addresses and control signals may be provided so as to perform a predefined sequence of memory operations, for instance, writing a specific data pattern into the memory 120A, reading specified memory locations and the like. The data 161 is transmitted through the bus 150A, thereby experiencing a certain degree of latency, which may be caused by the presence of a specific number of pipeline stages 151, which may be required in view of timing constraints and the like. Additionally, appropriate test data 162 are provided by the slave circuit 160A, for instance by operating a specified logic circuitry, which may evaluate a sequence of data, by receiving appropriate test data patterns from memory and the like. The data 162 is also transferred to the glue logic 140A through bus 150A including the specified number of pipeline stages 151. The control data 161 may be supplied to the memory 120A in order to initiate a corresponding sequence of memory operations, such as a sequence of write operations using the test data 162, that is supplied to the memory 120A by means of any appropriate circuit, such as a multiplexer 142, and the like. At the same time, the test data 162 may also be supplied to a latency adaptation stage 143, which may thus impart a specified latency to the test data that is equal to the latency experienced by the test data when subjected to corresponding memory operations initiated by the control and address data 161. Consequently, the data 162 as output by the adaptation stage 143 may be considered as reference data that can be compared to memory data 162M that are obtained by performing respective read operations in accordance with the test algorithm under consideration. For example, the comparison may be performed on the basis of exclusive OR gates 141A, 141B, thereby obtaining a comparison result for a portion of the data 162M. It should be appreciated that, due to the increased width of sophisticated memories, such as memory 120A, typically each item of the data 162M, 162R may represent an appropriate number of individual bit values, which may individually be compared, thereby providing a corresponding bitmap, which may be considered as the entirety of bit values representing the result of the comparison between the data 162M and 162R. For example, the corresponding result data or bitmap may be stored in a register 141C. Consequently, for a definition as used above, each logic 1 in the register 141C may represent a corresponding memory failure at a given point in time, thereby obtaining a topographical overview of the memory 120A for each global failure state, which may be indicated by a failure signal 141D obtained on the basis of an OR gate 141E, which may therefore assert the signal 141D upon occurrence of one or more individual failure bits in the register 141C. The failure signal 141D is then applied to the slave circuit 160A via a corresponding line 152, which in turn may also comprise a specific number of pipeline stages. The failure signal 141D may trigger a failure counter 164 in order to monitor the number of memory failures obtained during the corresponding test algorithm. The failure counter 164 in turn may lock an operation counter 163, which may count the number of operations issued to the glue logic 140A after starting the test algorithm under consideration. Consequently, the value of the counter 163 is indicative of the number of memory operations that resulted in the generation of a corresponding global failure indicated by the signal 141D. However, due to the various latencies induced by the pipeline stages 151, 152, the value of the counter 163 may not directly indicate the specific read operation that causes the failure under consideration. In order to obtain a reliable correspondence between the value of the counter 163 and a corresponding memory operation under consideration for a specified memory failure, respective design measures may have to be taken, such as appropriately adapting the pipelines 151 and 152, inserting a predefined number of wait cycles in the counter 163 in order to balance any latency differences of the corresponding signal line and the like. As previously discussed, during the design and verification of complex integrated circuits, it may frequently be desirable to add additional pipeline stages, for instance in view of superior signal routing and the like, in particular where semiconductor devices are considered that are operated based on high clock frequencies, which, however, may require a total redesign for a built-in self-test circuit in order to provide the required consistency between the bitmap obtained on the basis of the register 141C and the corresponding failure signal 141D. That is, by adding additional pipeline stages in a late design state, the corresponding delicate balancing of the pipelines 151, 152 required for appropriately associating a memory operation with a corresponding bitmap, or the incorporation of appropriate wait cycles, and the like may no longer be appropriate, thereby requiring the redesigned pipelines stages.
In view of the situation described above, the present disclosure relates to semiconductor devices and methods for operating the same in which flexibility in designing memory built-in self-test circuits may be enhanced by avoiding or at least reducing the effects of one or more of the problems identified above.