Circuit designers of multi-Gigabit systems face a number of challenges as advances in technology mandate increased performance in high-speed components. At a basic level, data transmission between high-speed components within a single semiconductor device or between two devices on a printed circuit board may be represented by the system 10 shown in FIG. 1. In FIG. 1, a transmitter 12 (e.g., a microprocessor) sends data over a transmission channel 14 (e.g., a copper trace on a printed circuit board or “on-chip” in a semiconductor device) to a receiver 16 (e.g., another processor or memory). When data is sent from an ideal transmitter 12 to a receiver 16 across an ideal (lossless) channel, all of the energy in a transmitted pulse will be contained within a single time cell, which is an example of a unit interval (UI).
However, real transmitters and real transmission channels do not exhibit ideal characteristics, and the effects of transmission channels are becoming increasingly important in high-speed circuit design. Due to a number of factors, including, for example, the limited conductivity of copper traces, the dielectric medium of the printed circuit board (PCB), and the discontinuities introduced by vias, the initially well-defined digital pulse will end to spread or disperse as it passes over the transmission path. This is shown in FIG. 2. As shown, a single pulse of data 15a is sent by the transmitter 12 during a given UI (e.g., UI 3). However, because of the effect of the channel 14, this data pulse 15b becomes spread over multiple UIs at the receiver 16, i.e., some portion of the energy of the pulse is observed outside of the UI in which the pulse was sent (e.g., in UI 2 and UI 4). This residual energy outside of the UI of interest may perturb a pulse otherwise occupying either of the neighboring UIs in a phenomenon referred to as intersymbol interference (ISI).
Due to several factors associated with the complexity in designing, building, and testing such circuitry, it is a common practice in the art of integrated circuit design to simulate the operation of a circuit using a computer system. Simulation software allows the circuit designer to verify the operation and margins of a circuit design before incurring the expense of actually building and testing the circuit. Simulation is particularly important in the semiconductor industry, where it is generally very expensive to design and produce a given integrated circuit. Through the use of simulations, design errors or risks are hopefully identified early in the design process, and resolved prior to fabrication.
The challenge associated with simulating channel-affected signals is highly correlated to the characteristics of the degradation imposed by the transmission channel. As will be discussed in greater detail, signals in any transmission medium experience both random and deterministic degradation. Random degradation, in the form of random Gaussian distributed voltage noise and timing noise (which is often referred to as “jitter”) stemming from thermal and shot noise, requires statistical quantification. Similarly, deterministic voltage noise and timing jitter are linked to several sources, including power supply noise, inter-channel crosstalk, impedance discontinuities, component variance, and at high frequencies the response of the channel, resulting in a variety of observable characteristics, from periodicity to uncorrelated-bounded randomness. To model these noise components correctly requires the ability to designate their probabilities during the noise generation stage and consequently apply or superimpose these effects onto the underlying signal in a way that reflects what occurs in the actual system. The final success or robustness of a particular design is dependent, to a large measure, on the achieved realism of the simulation environment. To date, industry standard simulators do not provide the level of noise and jitter generation control needed to accurately model a realistic communication link.
Another challenge simulating realistic signaling environments is tied to the underlying statistical assumption that sufficient samples of the behavior to be characterized are readily available. As such, it is becoming necessary to include more and more cycles with each simulation. At the same time, the relative size of each individual noise component, be it amplitude noise or timing jitter, is very small with respect to the overall signal amplitude and/or cycle period, implying that fine voltage and timing resolution are also necessary. When fine simulated resolution is coupled with a large number of simulated cycles, the result is an enormous amount of data and prohibitively lengthy simulation times. It is not uncommon for transistor-level transient (time-based) simulations to run for hours or even days. It is likewise not uncommon for such a simulation to fail due to a lack of memory resources.
Because simulation time and memory requirements associated with transistor level evaluation are prohibitive, a large portion of high-speed link design and verification is carried out at the system level with programs like Matlab. These tools allow the designer to take a more statistical look at the link behavior. Statistical models are often used to predict data eye closure at low bit error rates (BERs) because it is simply not practical to simulate to a standard BER, such as 1×10−12. Statistical simulation requires the circuit designer to make a number of assumptions, such as the noise characteristics of the power supply or reference voltage (Vref). Further, most statistical methods are based on the system pulse response, which is typically obtained through either the system impulse response or the system step response. One shortcoming of such an approach is that the measured system responses correspond to a specific circuit bias configuration, while the circuit biasing varies over time. Finally, and perhaps most restrictively, statistical analysis rests on the assumption of system linearity, while the majority of present-day systems still contain nonlinear elements.
At the lower data rates of the past, voltage noise was the dominant concern, leading to signal-to-noise ratio (SNR) boosting circuits like the matched filter and ISI canceling channel equalizers. But at multi-Gigabit/second (Gb/s) data-rates, the inherently short symbol period (i.e., unit interval (UI)) has shifted attention from voltage to time. And whereas noise budgets were once an essential part of the initial design specification, jitter budgets are now the more common focus. White this trend may appear to justify the independent analysis of amplitude noise and timing jitter when one of the two is the more dominant performance limiter, increased accuracy is still achieved when both noise components are considered simultaneously. Accordingly, an improved signal simulation technique would at least generate a full signal with both amplitude noise and timing jitter.
Another argument for developing full signals with amplitude noise and timing jitter, rather than maintaining independent noise and jitter models, is the impact of ISI. While unbounded Gaussian noise and jitter lead to long term bit errors, depending upon the bandwidth of the channel, ISI and the corresponding data-dependent jitter (DM) may dominate the short term signal degradation.
Finally, to be able to incorporate the anticipated impact of the channel directly into the input stimulus waveform at the time of signal generation can reduce simulation time significantly, as the mathematical process for computing the impact of the channel on the signal (convolution) is computationally intensive. Therefore, it would benefit circuit designers to avoid repeating such a calculation with each simulation. The disclosed techniques achieve such results in a manner implementable in a typical computerized system or other computerized circuit simulation software package.