The present invention is directed to ISDN communications and, particularly, to methods and apparatus that facilitate access to the "on-board" memory of an network interface card (NIC) or other ISDN interface device.
Network interface cards, or NICs, provide an interface between ISDN lines and host processing equipment, such as, personal computers, videoconferencing equipment, telephony equipment, and the like. NICs receive data over the ISDN lines from other nodes (e.g., other teleconference participants), reformat it, and send it to the host, e.g., via a serial bus as an MVIP bus or an H100 bus. Likewise, NICs accept data from a host, repackage the data, and transmit it to the ISDN lines for transfer to other network nodes.
NICs typically have an on-board memory that is used to temporarily store data exchanged between the ISDN lines and the host. Thus, for example, receive data from the ISDN lines is written to the on-board memory prior to transfer to the host. Likewise, transmit data from the host is written to that memory prior to transfer out over the ISDN lines.
Access to the on-board memory is typically controlled by a communications processor within the NIC, i.e., an on-board communications processor. Some of the reformatting and repacking operations referred to above are performed by the communications processor directly on the data while it is stored in memory. Other operations are performed through joint action of communications processor and other components of the NIC, e.g., line transceivers. These joint operations require that the communications processor strobe address and control lines of the memory at appropriate times and in appropriate sequences to insure that data are transferred to and from desired locations in memory.
The memory control circuitry of a communications processor is usually separate and distinct from the basic instruction processing circuitry. In the case of processors such as Motorola MPC860, by way of non-limiting example, this facilitates control of the NIC's on-board memory by additional or "external" devices, notably, the host processing equipment. Depending on which device (e.g., the communications processor or the host) is mastering the bus during any given cycle, the memory control circuitry responds to that device for purposes of strobing reads or writes to/from memory.
A memory controller may permit different modes of memory access. The most common is "single beat" mode, wherein a single byte or word of data transferred to/from a specified location in memory per bus cycle. In a single-beat read transaction, for example, the bus master drives an address onto the system bus at the outset of the cycle. The memory controller applies that address to the memory, along with control signals that cause it (the memory) to transfer data from the addressed location to the bus. In a single-beat write transaction, the bus master drives an address, then data, onto the bus. The memory controller applies these to the memory, along with the requisite control signals, causing the data to be stored at the addressed location in memory.
Burst mode transactions are used to transfer larger blocks of data. In these transactions, the bus master need not drive an address onto the bus for each word to be written to, or read from, memory. Instead, the bus master specifies only a start address. A burst or continuous sequence of data follows, with the memory controller computing and supplying addresses directly to memory. In a burst mode read transaction, for example, the bus master drives an address onto the system bus. The memory controller applies that and a successive sequence of addresses to the memory, along with the requisite control signals to cause data to be read from memory onto the bus. In a burst mode write transaction, the bus master drives an address, then a successive series a data, onto the bus. The memory controller generates a successive series of addresses and applies them to the memory, causing the data to be stored at successive locations in memory.
Though not a feature of the Motorola MPC860, other memory controllers support still other modes of memory access, e.g., so-called "direct" memory access.
Notwithstanding the versatility of memory controllers, restrictions imposed by NIC (or other interface apparatus) architectures or by other factors may limit the modes with which they are called upon to access memory. Thus, for example, unless a host is coupled to a NIC via a bus that supports variable width cycles, the host cannot participate in a burst mode transaction. Such is the case of hosts that are coupled to NICs via the so-called ISA ("industry standard architecture") bus, which does not permit variable width "cycles" and which requires that addressing information be applied to the bus during each cycle.
While it is always desirable to access memory in the most efficient manner possible, one prior art solution has been to apply a "least common denominator" approach to NIC memory access. Thus, if architectural or other limitations limit the host to accessing the NIC memory single-beat mode, the NIC memory controller is configured to limit all devices (including the on-board processor) to that mode of access. While this has the advantage of simplicity, it can adversely impact NIC performance.
An object, therefor, of this invention is to provide improved methods and apparatus for ISDN communications and, more particularly, for accessing memory in NICs and other ISDN interface devices.
A further object is to provide such methods and apparatus as can be implemented with existing components and without undue manufacturing expense.
A further object is to provide such apparatus and methods that operate robustly and with minimal power consumption.