This invention relates to methods and apparatus for manufacturing semiconductor devices, and, in particular, for depositing alloys at the bottom of high-aspect ratio contact holes.
In the fabrication of semiconductor integrated circuits (ICs), active device regions are formed in semiconductor substrates, isolated from adjacent devices. Specific electrical paths connect such active devices, using high-conductivity, thin-film structures. Such structures make contacts with active devices through openings, or contact holes, in the isolating material. Of primary concern is the formation of low-resistivity contacts, in order to ensure devices perform properly. As ICs are scaled down in size, so are the devices which make up the ICs. Increases in resistance are associated with increasing circuit density and adversely affect device performance. Ways to decrease the overall resistance of ICs, including contacts, are crucial to continued successful device performance.
One way in which circuit resistance is decreased is by creating low-resistance, ohmic contacts at the device level. Ohmic contacts exhibit nearly linear current-voltage characteristics in both directions of current flow. Various factors affect the type of contact which is maintained. Increasing dopant concentration in the semiconductor contact area decreases contact resistance, up to the solubility of the dopant at the temperature at which it is introduced. Unclean semiconductor surfaces (i.e., those which contain a native oxide film) increase contact resistance. Native oxides are a problem due to silicon""s rapid oxidation rate when exposed to an oxygen ambient. The most widely used method for removal of such oxides is by dipping the wafer in a hydrofluoric acid solution. However, this does not perfect cleaning of the semiconductor substrate because some native oxide forms between the time of the hydrofluoric acid dip and the deposition of metal contacts. Sputter etching has been used in an attempt to alleviate this imperfection, but it falls short because more oxide is introduced onto the semiconductor substrate than is removed.
Conventional process steps for formation of ohmic contacts to semiconductor substrates include the following: formation of heavily doped regions where contacts are to be made, etching a contact hole in the isolating oxide layer which covers the semiconductor substrate, cleaning the semiconductor surface to remove native oxide, depositing a metal film over the wafer by physical vapor deposition (PVD), and annealing to improve the metal-to-semiconductor contact. During the metal deposition step, obtaining good bottom step coverage is very important in maintaining the overall ohmic contact. High-aspect ratio (ratio of height-to-opening of a contact hole) holes make it even more difficult to achieve good bottom step coverage. Such holes are much deeper than they are wide, preventing good bottom step coverage by the conventional process steps.
The type of film deposition has an effect on the resulting step coverage. Chemical vapor deposition (CVD) processes are more likely to fill high-aspect ratio holes than physical vapor deposition (PVD) processes. However, some films cannot be deposited using CVD, due to contamination introduced by CVD processes. CVD is often accompanied by a significant amount of carbon, chlorine, oxygen, and other contaminants that are detrimental to device performance. Forming films that are free from contamination is even more important as devices decrease in size. Defects resulting from such contamination are even more dominant in thinner films, which are present in smaller devices.
Different types of metal layers are used to improve ohmic contacts. The most commonly used metals are reacted with underlying silicon to form silicides. Titanium silicide is the most commonly used metal silicide due to its superior qualities, one being its ability to getter oxygen. Titanium silicide forms good ohmic contacts with both polysilicon and single-crystal silicon doped contact areas. Silicides, in general, are preferred for contact formation due to their ability to reduce native oxide remaining on semiconductor substrates. This reduction occurs because titanium reacts with native oxide to form titanium oxide and titanium silicide. The oxide layer remains on top of the silicide layer after annealing, separated from the underlying silicon.
As an effect of shrinking IC devices, device source/drain junction depths become shallower. When metals are deposited and then annealed to form a silicide, silicon is consumed from the shallow source/drain regions, to react with the metal to form a silicide. When shallow source/drain regions are depleted of silicon, they are more prone to junction leakage. Thus, consumption of silicon during annealing to form silicide must be as small as possible to prevent junction leakage. In general, for a particular thickness of deposited metal, a proportional thickness of silicon substrate is consumed, depending on the stoichiometry of the silicide formed. In particular, for a given thickness of deposited titanium, the amount of silicon consumed is approximately two times as thick, to form titanium silicide (TiSi2).
A primary method for depositing films by PVD is sputtering. Sputtering is a method by which atoms on a target are displaced to a desired surface, where they form a thin film. One possible solution to the problem of over consumption of silicon in shallow junctions is to use a PVD process to deposit a metal/silicon alloy, like titanium suicide. When the deposited material is an alloy, the target is generally a composite target consisting of two or more materials mechanically arranged in a selected ratio, to yield a film of the desired alloy composition.
One of the major problems associated with obtaining good bottom step coverage utilizing PVD is material xe2x80x9coverhangxe2x80x9d at the xe2x80x9cshoulderxe2x80x9d (i.e., the corner of a sidewall and the top surface) of contact openings. This is a result of imperfect lines of incidence traveled by sputtered target atoms, because, in general, sputtered atoms travel following the law of cosines. Doming of the sputtered material commonly occurs in the bottom of the contact hole due to material overhang. This results in poor bottom corner step coverage, which often leads to contact failure.
Even with the use of collimated sputtering, techniques of collimating the sputtering beam are not perfect to enable precision in angles of incidence on a substrate. Thus, excess sputtered metal forms at the top of the opening, such that the geometry of the metallized opening does not generally match the geometry of the underlying opening in the substrate.
There is a need to maintain adequate alloy bottom step coverage of contact holes and to decrease contact area resistance to prevent device failure. There is a further need to control the composition of such alloys, without significant consumption of silicon from the bottom of the contact hole.
A recess feature is defined by an upper and a lower surface. An alloy is deposited in a recess feature of a semiconductor substrate by sputtering an alloy or composite target onto the semiconductor substrate to form a layer of deposited material on the upper surface. After a period of time, a negative bias voltage is applied to the substrate, initiating a resputtering scheme, which operates simultaneously with the sputtering step. The layer of deposited material is resputtered, to redeposit the layer of deposited material onto the lower surface as a first layer of resputtered material having a different stoichiometry than that of the deposited material. The resulting recess has improved bottom step coverage, which results in improved ohmic contacts.
Use of physical vapor deposition (PVD) to deposit alloys solves the problem of silicon depletion of shallow source/drain junction depths, as experienced using multiple-step, prior art techniques of siliciding source/drain regions by depositing a metal and annealing to form a silicide. In such prior art techniques, silicon is consumed from underlying source/drain regions, in a ratio of two atoms of silicon per atom of deposited titanium, to react with the deposited metal to form a silicide. Silicon is not over consumed from shallow junctions in this invention because the sputter-deposited titanium silicide already contains a significant portion of silicon. Subsequent chemical reactions, which deplete silicon in source/drain regions, are not needed to form the silicide. Furthermore, using PVD eliminates the problems associated with contamination introduced into the deposited film when using chemical vapor deposition (CVD).
In this invention, titanium silicide is deposited from an alloy or composite target into a high-aspect ratio contact hole. When the target material comprises titanium silicide, the ratio of silicon to titanium in the titanium silicide is approximately between 2.0:1 to 2.7:1, or another ratio, if required. Higher ratios of silicon to titanium are used when greater thermal stability is required, as when numerous subsequent heat cycles are needed to form a device. A target is used with a ratio of silicon to titanium equal to, or greater than that of any deposited or resputtered layer. However, as the desired stoichiometry of the resputtered material layers increasingly deviates from the stoichiometry of the target used, it becomes more difficult to make large stoichiometry changes between the target and resputtered layers. Therefore, a target is selected that has a stoichiometry which does not differ from that of resputtered layers to such an extent that it is impossible to obtain the desired stoichiometry in the resputtered layers.
The layer of deposited material has a ratio of silicon to titanium of between approximately 1.0:1 and 2.0:1. However, a ratio of 1.8:1 provides an optimum proportion of titanium, which reduces native oxides. When using a ratio of 1.8:1, very little silicon is consumed from the underlying substrate. By depositing a titanium-rich silicide film in the bottom corners of a contact hole, native oxides are reduced during a subsequent anneal step, decreasing the resistivity of the contact. A negative-bias voltage is applied to the substrate to form this resputtered layer, through low energy resputtering, using a low, grazing angle of incidence on the side of the material overhang, within the contact hole.
A low energy (low negative bias voltage) resputtering regime is defined in an area when the low energy is not larger than the lowest sputtering threshold energy of any constituent of an alloy or composite target. Typically, the threshold energy of a constituent is four times as much as its heat of sublimation. In this regime, resputtering yield increases dramatically with decreasing angle of ion incidence.
A low grazing angle also increases resputtering yield. Large angle resputtering is insignificant. Small angle or grazing angle resputtering is so dominant that a significant portion of resputtered material can reach the bottom corners of the contact hole. This reduces the doming effect, which arises when sputter depositing material (even with a collimated or long throw process), using conventional PVD processes. Reducing the doming effect improves bottom step coverage by making it more uniform.
Also, in this low energy, low grazing angle resputtering regime, in general, heavier elements of a sputtered species sputter at a faster rate than lighter elements. The substrate bias voltage is adjusted to achieve a desired resputtered material stoichiometry, according to the mass of the elements present in the sputtered alloy, or composite. In general, small changes (e.g. 10%) of stoichiometry are much easier to achieve using this low negative bias method. For instance, a 10% change of TiSix, x=2.0, stoichiometry gives rise to x=1.8, which is titanium-rich silicide, optimum for reducing native oxide on a silicon substrate surface.
In one embodiment of the invention, a collimated PVD setup is used to obtain a low grazing angle during resputtering. In a second embodiment of the invention, a long-throw process is used to obtain a low, grazing angle during resputtering. A long-throw process utilizes a non-collimated PVD apparatus. During a long-throw process, spacing between a target and substrate is so large that only a portion of target material, having a small trajectory angle, with respect to the normal direction of the target, can reach the bottom of a contact hole. Note that in the case of resputtering material overhang, the normal direction of the target (material overhang) is measured, extending radially into the contact hole, in the plane of the substrate. The resulting material deposition rate and bottom step coverage are improved using this embodiment, due to the low energy and low angle mechanisms described previously.
In a further embodiment of the invention, a sputtering chamber ambient atmosphere comprises argon and a nitrogen concentration of between approximately 0.1 to 3.0 percent by volume. Furthermore, in yet another embodiment of the invention, the resputtering step is followed by resputtering of at least one layer of material with a different stoichiometry than that of the first resputtered material layer, to form a xe2x80x9cgradedxe2x80x9d stoichiometry of material deposited in the contact hole. Using a nitrogen ambient increases the ion-to-neutral ratio, which increases the resputtering rate. Therefore, the resulting material deposition rate and bottom step coverage are improved using this embodiment.