1. Field of the Disclosure
The present disclosure relates generally to electronic devices, and more particularly to data processing devices.
2. Description of the Related Art
A data processing device such as a microprocessor often includes cache memory in addition to a central processing unit. Cache memory increases the computational performance of a data processing device by providing local storage for information that the data processing device is manipulating. The central processing unit is able to access data that is stored in a local cache memory considerably faster than it can fetch the data from an external memory device.
Cache memory at the microprocessor typically is organized using levels. A level-one (L1) cache memory contains relatively few data entries, and is the memory that can provide needed data to the central processing unit most efficiently. The ability to access data from each subsequent level of cache is less efficient than respective previous levels. For example, desired data stored at the L2 cache will be provided to the central processing unit if a miss occurs in the L1 cache, though the desired data may not be provided to the data processor as quickly from the L2 cache as from the L1 cache. Higher-level caches are typically larger than lower-level caches. For example, a L3 cache memory typically is configured to store a relatively large number of data entries as compared to the L2 or L1 caches. In order to provide a large-capacity L3 cache memory without the cache occupying an unacceptably large portion of the IC die area, the individual transistors and storage capacitor that make up the L3 cache memory bit-cell are usually relatively small. Unfortunately, the small size of the transistors and capacitors can make the L3 cache memory more susceptible to data corruption, resulting in an increased error rate compared to the L1 and L2 cache memories.
A memory error can include either a hard error or a soft error. A hard error can result from a marginally or fully defective transistor or by signal noise that causes a data value to be improperly stored or retrieved. A soft error can result from the interaction of ionizing radiation with the memory bit-cell. Radiation can include neutrons that typically originate in outer space, or alpha particles that originate from materials present in the integrated circuit package. A data processing device can implement error detection and error correction protocols in order to increase the reliability of the data processing device.