SIMD processors are best suited to performing the same operation on multiple pieces of data simultaneously. Typically, parallel processing portions of a single arithmetic logic unit (often viewed as individual parallel ALUs) operate on portions of operands simultaneously.
Certain calculations used in digital signal processing, on the other hand, repeatedly calculate the outcome of an operation applied to data that is shifted in time.
For example, shift invariant convolutions are often used in digital signal processing, to apply a frequency domain filter to a time domain representation of a signal. Specifically, the Nth order shift-invariant convolution of two discrete time signals h(n) and q(n) can be expressed mathematically asz(n)=h(0)*q(n)+h(1)*q(n−1)+ . . . +h(N−1)*q(n−N+1)where N is the order of the convolution, q(n), n=0, 1, 2, . . . is the sequence of samples input to the filter and h(i), i=0, 1, . . . , N−1 is the impulse response of the filter and z(n), n=0, 1, 2, . . . is the output from the filter. In general the length of the sequence of input samples need not be bounded, if output samples are produced as input samples are received. For example given an impulse response h(i), i=0 . . . N−1 and the subsequence of N input samples starting from discrete time t0−N+1:q(t0−N+1), . . . , q(t0−1), q(t0)the value of the convolution between h(i) and q(n) can be computed at discrete time t0. Further, given an impulse response h(i), i=0 . . . N−1 and the longer subsequence of N+k−1 input samples starting from discrete time t0−N+1, for some value of k>1:q(t0−N+1), . . . , q(t0−1), q(t0), . . . , q(t0+k−1)the value of the convolution between h(i) and q(n) can be computed at k discrete times t0 . . . t0+k−1.
For convenience, and without loss of generality, we define a new representation of the impulse response as a(i), i=0 . . . P−1 wherea(i)=h(N−1−i) for i<Na(i)=not defined, N≦i<P and N≦P.Specifically a(0)=h(N−1), a(1)=h(N−2), . . . , a(N−1)=h(0)
Similarly without loss of generality we define a representation of the subsequence of N+k−1 input samples starting from discrete time t0−N+1 as x(n), n=0 . . . P−1 wherex(n)=q(n+t0−N+1) for n<N+k−1x(n)=not defined, N+k−1≦n<P In a similar vein we lastly define a representation of the subsequence of k output samples starting from discrete time t0 as y(n), n=0 . . . k−1 wherey(n)=z(t0+n), 0≦n<k 
With these definitions in place an alternate representation of the convolution can be expressed as:y(n)=a(0)*x(n)+a(1)*x(n+1)+ . . . +a(N−1)*x(n+N−1), n=0 . . . k−1
Conventional processors calculate shift-invariant convolutions, y(n) by executing a sequence of basic arithmetic operations such as multiply, add and multiply-and-accumulate.
As a further example, pattern matching techniques often require a processor to assess a best match of a series of target values (referred to as a target) and reference samples sequential in time or spatial position. Expressed mathematically, it is often desirable to assess j, for which the dissimilarity between the target a(0)a(1) . . . a(N−1) and reference samples x(j)x(j+1) . . . x(j+N−1) is minimized. It is often similarly desirable to find a pattern match of the target to interpolated samples of the reference. Again, conventional processors perform such pattern matching operations by executing a sequence of basic arithmetic operations.
Clearly, a SIMD processor capable of calculating shift invariant convolutions for multiple values of n concurrently would be beneficial, particularly in computationally intensive applications that benefit from high speeds. Similarly, a processor capable of performing several pattern matching operations concurrently would provide benefits.