This application claims the benefit of the Korean Application No. P2000-78487 filed on Dec. 19, 2000, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a synchronous transport module (STM) and, more particularly, to variably simplexing/duplexing multiple STM links.
2. Background of the Related Art
Due to the rapid growth of the multi-media field, a communication network providing digital transmission of a wideband signal, such as a video signal, is in demand. A B-ISDN has been developed to meet this demand. The B-ISDN can meet a variety of service requirements of users, and particularly, the motion picture transmission made available by the B-ISDN has built a foundation for realizing a futuristic dream of an information society.
The B-ISDN requires an asynchronous transport mode (ATM) switching technology, in which ATM fixed length (53 byte) information blocks, called cells, are transferred by an ATDM method. When the ATM is used, an ATM communication device has a standard connection protocol between an ATM layer and a physical layer, providing versatility for different transmission media. Accordingly, even if the physical layer has a variety of forms, it is easy to connect to a Segmentation And Reassembly Sublayer (SAR) layer, if the protocol is followed.
The Universal Test & Operation & Physical Interface for ATM (UTOPIA), a standard interface for connecting the ATM layer and the physical layer, provides a cost saving by defining a common and standardized interface between the ATM layer and the physical layer. Moreover, the UTOPIA interface standard permits use of a first in first out (FIFO) memory between the ATM and the physical layer, which have different speeds, and supports 100 Mbps to 155 Mbps data rates, by a common interface of 8-bit data communication.
The UTOPIA interface standard is classified into application specific classes. A UTOPIA level-1 is based on an 8-bit data transmission and UTOPIA level-2 is based on a 16-bit data transmission.
In general, port duplexing of STM interface chips (or links) in an existing board is fixedly made to particular blocks. State information, such as an alarm signal, for each link is provided to duplex a plurality of links between boards.
A background art port duplexing of STM interface chips will be explained with reference to the attached drawings. FIG. 1 illustrates a block diagram of a background art STM, in which particular blocks are fixedly duplexed.
Referring to FIG. 1, the background art STM is a chip for processing an ATM cell. The STM is provided with a UTOPIA interface chip 16, which is a UTOPIA level-2 interface. The UTOPIA FIFO 14 transfers an ATM cell from the interface chip 16 to the transmission buffer 12, according to a FIFO method. The transmission buffet 12 transmits the ATM cell from the UTOPIA FIFO 14 to one of the STM interface chips 10 and 11, duplexed according to control signals (SOC, TCA, RCA, RXEN, TXEN) and a data signal (8-bit data) in the UTOPIA interface standard.
The STM interface chips 10 and 11 receive the ATM cells from the transmission buffer 12 and transmit externally received ATM cells to the reception buffer 13, at a rate of 155 Mbps. The reception buffer 13 receives the ATM cells from the STM interface chips 10 and 11 and transfers them to the bus-matching FIFO memory 15, according to control signals and data. The bus-matching FIFO 15 converts 8-bit parallel data received from the reception buffer 13 into 16-bit parallel data and transfers the converted data to the UTOPIA interface chip 16.
UTOPIA is an interface standard between a lower layer, like the physical layer supported by the STM interface chip (or link), and an upper layer, like the ATM layer. The UTOPIA level-2 interfaces the ATM layer and 16 physical layers, and UTOPIA level-1 interfaces the ATM layer and the physical layer, in a one-to-one relationship.
The bus-matching FIFO 15 converts 8-bit ATM cell data, received from the STM interface chips 10 and 11 and through the reception buffer 13, into 16-bit ATM cell data and forwards it. The STM interface chips 10 and 11 convert the 8-bit parallel data into a differential signal and transmit the differential signal at 155 Mbps.
The port duplexing operation of FIG. 1 will be explained below. The ATM cell is transferred from the UTOPIA interface chip 16 to the STM interface chip, according to the UTOPIA interface standard. The STM interface chips 10 and 11 are duplexed, as shown in FIG. 1, to enhance the transmission reliability.
Communication of the control signals SOC, TCA, RCA, RXEN, and TXEN in the UTOPIA interface standard and the 8-bit data are carried out by the transmission buffer 12, reception buffer 13, and the STM interface chips 10 and 11. The transmission buffer 12 and reception buffer 13 open paths to the first STM interface chip 10 and close paths to the second STM interface chip 11, using the control signals in a normal state. In the normal state, if the first STM link (or the interface chip) fails during operation of the board, the first STM interface chip 10 issues an alarm. When the first STM interface chip 10 issues an alarm, links between the first STM interface chip 10 and the transmission buffer 12 and the reception buffer 13 are cut off, and links between the second STM interface chip 11 and the transmission and reception buffers 12 and 13 are formed.
The background art STM has the following problems. First, when data (or an ATM cell) is transferred from the UTOPIA interface chip to the STM interface chip, the data is transferred from the UTOPIA interface chip to one of the duplexed STM interface chips. Effective management of the duplexed STM interface chips is difficult because the STM chips are fixedly duplexed.
Second, when the UTOPIA interface chip receives data from the STM interface chip, since the bus-matching FIFO is required to receive the data from the STM interface through the reception buffer, the reception of data can be troublesome when the reception buffer fails.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.