This invention relates generally to semiconductor memories.
Semiconductor memories generally include an array of cells arranged in rows and columns. A sense amplifier coupled to a column detects the state of a selected cell coupled to the column. Generally, the cell is selected through a word line coupled to the cell.
Examples of semiconductor memories include random access memories (RAMs), such as static random access memories (SRAMs) and dynamic random access memories (DRAMs). Examples of read only memories (ROMs) include erasable programmable read only memories (EPROMs), electrically erasable read only memories (EEPROMs) and flash memories. Both ROMs and RAMs include a number of cells coupled to columns with sense amplifiers to determine the state of a selected cell.
Memories using columns of cells coupled to sense amplifiers are subject to increasing capacitance as the density or number of cells increases. More capacitance means that the memory is slower. Thus, memories that store more information need more cells, but more cells means slower speeds in reading information from the memory or writing information into the memory (when possible).
SRAMs are advantageous in a number of environments largely because they do not require that the memory cells be refreshed. SRAMs may enjoy a higher speed and lower standby or static power dissipation in some environments. Thus they are particularly applicable to battery-operated systems. SRAMs may use complementary metal oxide semiconductor (CMOS), bipolar, BICMOS, and gallium arsenide technologies, as examples.
It is desirable that the power dissipation of any memory be as low as possible. Particularly in memories, such as SRAMs, which are often used in battery-powered applications, the need for low power dissipation is acute.
In addition, there is a need for higher speed memories. As microprocessors become ever faster, the memories used with such microprocessors need to keep pace. Thus relatively faster memories are always needed. As the density of memories increases, this adds more capacitance to the word lines, bit lines and sense lines, slowing these memories. Thus, advances which enable ever more dense memories also inherently decrease the speed of those memories.
A number of efforts have been made to improve the speed of SRAMs. For one thing, address transition detection (ATD) has been adopted. In ATD, the bit lines are equalized prior to a new access. This reduces the needed voltage swing. Also, advanced technologies use ever-faster sense amplifiers.
A number of SRAMs use so-called short bit lines. In a short bit line the chip is laid out at 90 degrees to that used in the past. This results in shorter bit lines, lowering the bit line capacitance. As a result, higher speed signals may be developed.
Thus, there is a need for even faster memories which may consume less power and take up substantially the same or less integrated circuit space.