FDDI or TPDDI type data transmission networks are used more and more frequently and are broadly defined in documents prepared by international standardization boards like ANSI (American National Standard Institute), under reference X3T9-5. These standards are also adopted by the I.S.O., Organization Internationale de Normalisation (International Standard Organization). They define a set of physical and electrical characteristics of the network. These transmission networks have the advantage of having reached a high number of bits transmitted, on the order of 100 Mbits/s.
It is known that information messages emitted by the various stations are made up of a multiplicity of frames. The frame is constituted by usable data framed in time by command characters placed at the head and tail of the frame. In type FDDI or TPDDI networks, the length of the frames is 4 kilobytes and there are two main types of frames, defined by the standard, namely, frames of type LLC and frames of type SMT. Type LLC frames are actually made up of useful data to be transmitted and they are those most commonly used on the network. Frames of SMT type are special frames called "station management", or even station administration, for verification of proper operation of each one of the stations connected to the network. Furthermore, we know that all the operational components of a computer (processor, memory, controller, etc...) are arranged on a card assembly of standardized dimensions. These latter are linked to the same bus, generally of parallel type, guaranteeing communications among themselves and the various cards together with the carrying of data and the electric power supply.
One of the most commonly used buses is the MULTIBUSII (brand registered by the INTEL Company and commonly known as PSB or Parallel System Bus) standardized according to the IEEE1296 (Institute of Electrical and Electronic Engineers) norm.
Such a computer bus is linked to the network (FDDI or TPDDI) by the intermediary of a data transmission system (which may also be called a connection bridge device) whose function is to adapt conditions for transmission of data on the MULTIBUSII to transmission conditions on the network. In fact, the methods of data transmission concerning the rate of data transmission, transmission protocols used, entry codes, data, format, command characters, etc . . . , on the PSB bus on the one hand and the network on the other, are totally different.
The general physical structure of a data transmission system is shown in FIG. 1. It is described in more detail, together with the various methods of carrying out the operation, in either one of the applications for patent No. 91 08908 filed on Jul. 15, 1992 by BULL S.A. under the title "Universal device for connecting a computer bus to a controller of a group of peripherals" and No. 91 08907 filed on the same day by the same applicant under the title "Operating system for universal device for linking a computer bus to a specific network connection".
FIM, such a system of data transmission, is composed of two parts, that is, a universal coupling device GPU (English acronym for General Purpose Unit) and an adapter device DEA.
The device GPU is linked to PSB by an MPC coprocessor, type VL 82c389 manufactured by the INTEL Company, which communicates by message mode with the computer ORD (not shown in order to simplify FIG. 1), this mode being defined in the aforementioned IEEE 1296 standard.
The device DEA can be physically arranged on the same card as the universal coupling GPU. In addition, it is linked physically to the network RE in a manner such as that described in U.S. Pat. No. 5,237,659 entitled "Bridge device for connection of a computer bus to a fiber optic network in ring form", issued Aug. 17, 1993.
The GPU device is comprised of the following various essential components:
the MPC coprocessor already mentioned, PA1 the microprocessor CPU.sub.1 actually constituting the central unit of the GPU, equipped with an internal bus BI.sub.1 for carrying commands to the adapter device DEA. This microprocessor is associated respectively with a programmable erasable memory EPROM.sub.1, a read/write memory SRAM.sub.1 and an interruption manager, or MFP.sub.1. All these elements EPROM.sub.1, SRAM.sub.1, MFP.sub.1 are connected to internal bus BI.sub.1, PA1 the double port video-RAM memory designated as VRAM, PA1 the direct access memory DMAC controller connected on the one hand to bus B.sub.2, linking it to the VRAM memory, and on the other hand, to bus B.sub.3, linking it to the coprocessor MPC, PA1 bus B.sub.1 which links the VRAM memory to the adapter DEA, the components of which will be described subsequently.
The microprocessor CPU.sub.1 is, in the production example described here, of type 68030 manufactured by the MOTOROLA Company. The internal bus BI.sub.1 is a non-multiplexed bus of 32 bits for data and 32 bits for addresses.
The erasable read-only memory EPROM.sup.1, for example, has a capacity of 256 kilobytes and contains the self-testing and initialization programs of the universal linking device GPU.
The operating system of the microprocessor CPU.sub.1 (Operating System) designated by GPOS (English acronym for General Purpose Operating System) is contained in static memory SRAM.sub.1 and is charged with initialization of the coupling device GPU. The capacity of this memory is, for example, 1 megabyte. GPOS is described in aforementioned claim No. 91 08907.
In FIG. 1 we can see that the direct access controller DMAC is serially connected on the one hand between the memory VRAM and the coprocessor MPC and on the other hand between this latter and bus BI of the microprocessor CPU.sub.1.
A detailed description of the structure and operation of the controller DMAC is given in the application for French patent No. 91 15814 filed on Dec. 19, 1991 by the applicant company under the title "Controller of transfer of multiple data between a multiplicity of memory and a computer bus" from which a corresponding United States patent will issue from PCT application PCT/FR92/01202.
The microprocessor CPU.sub.1 is the brain of the coupling device GPU: it initializes the transfer of data, carries out the adaptation of protocols, implements its operating system and transfers data between DEA and the computer ORD and vice versa while dialoguing with the DEA with which it exchanges commands and statuses as described farther on in the description of the invention.
The detailed description of the role and operation of other components of the coupling device is given in the three previously mentioned patent applications.
Examples of the invention of an adapter device like DEA are known. One such example is described in aforementioned U.S. Pat. No. 5,237,659, issued Aug. 17, 1993. Such a device comprises a transfer management controller CT, a network access controller DAR and a device for physical adaptation to the network DAPR.
The role of the transfer management controller CT is to organize the transfer of frames between the GPU apparatus and the adapter device and the network RE and vice versa while, at the same time, exchanging commands with the microprocessor CPU.sup.1 of the GPU. The network access controller permits the physical transfer of data from the bus B.sub.1 to the network RE via the physical adaptation device DAPR and the bus B.sub.4 which is physically connected to B.sub.1. The network access controller CAR and the device for physical access to the network DAPR are, for instance, constituted by components DP83265, DP83261, 83251 or 55, 83231, 83241 of Societe National semi-conductors.
The controller CT is comprised of a microprocessor CPU.sub.2, a memory EPROM.sub.2, a storage memory SRAM, and an interruption manager MFP.sub.2. All these components are linked by internal bus BI.sub.2 of the transfer controller CT. It is quite evident that the microprocessor CPU.sub.2 is the central element of the transfer controller CT and it is that that organizes the dialogue with the microprocessor CPU.sub.1 through the intermediary of commands in a manner that will be described relative to the invention farther on in the text.
According to previous design, in the adapter device DEA, data and commands pass through the intermediary of two separate buses, with the commands passing through the intermediary of the internal bus BI.sub.2 of the transfer controller CT. Otherwise, commands and data pass between the adapter device DEA and the coupling device GPU through the intermediary of a transfer interface composed of memories FIFO, one for data and one for commands (not shown in FIG. 1).
The presence of such an interface between the coupling device GPU and the adapter device DEA, diminishes the performances of the data transmission system with regard to speed of transfer of information of the DEA component to the GPU component and vice versa. Moreover, due to the presence of the FIFO elements, interruptions are generated (by configuration) at each exchange of commands between the two microprocessors CPU.sub.1 and CPU.sup.2.