The present invention relates to a semiconductor integrated circuit, particularly to a semiconductor integrated circuit applicable to LSI for a general use processor, a signal processing processor, an image processing processor or the like partially including logical operation circuits.
Conventionally, in realizing a large scale logical operation circuit, there has widely been used systems of gate array, standard cell (or cell base integrated circuit) and the like. In these integrated circuits, a partial circuit referred to as cell is prepared previously. A cell signifies a small scale logical operation circuit in which layout of a mask pattern has been completed, normally, a plurality of them are arranged on the same chip. In respect of a cell, normally, other than mask layout, positions and areas of input and output terminals, an operational speed, power consumption and the like are prepared. A cell library stores information with regard to the cell in a storage device for assisting design of an integrated circuit. There has been known a design system using such cells, which is combined with a circuit referred to as a pass transistor circuit.
Pass transistor circuits have been introduced as xe2x80x9cDifferential Pass-transistor Logicxe2x80x9d in IEEE Journal of Solid-State Circuits, Vol. sc-22, No. 2, April 1987 pp216-pp222 (hereinafter, referred to as a first conventional technology) and as xe2x80x9cComplementary Pass-transistor Logicxe2x80x9d in IEEE Journal of Solid-State Circuits, Vol. sc-25, No. 2, April 1990 pp388-pp395 (hereinafter, referred to as a second conventional technology).
Further there has been shown a circuit design method in which a pass transistor circuit is combined with a standard cell system, mentioned above, in Custom Integrated Circuits Conference 1994 Digest pp603-pp606 (hereinafter, referred to as a third conventional technology).
Further, there has also been introduced a design method in which a pass transistor circuit is combined with the standard cell system by utilizing a logical expressing method referred to as xe2x80x9cBinary Decision Diagramxe2x80x9d in Proceedings of the 1994 IEICE fall conference (basic and boundary region) of the Institute of Electronics, Information and Communication Engineers (IEICE), pp64 (hereinafter, referred to as a fourth conventional technology).
Further, there has been shown a logical operation circuit cell using a pass transistor circuit in Japanese Patent Laid-Open No. 130856/1995 (hereinafter, referred to as a fifth conventional technology).
FIG. 10 and FIG. 11 illustrate plane views (a) for explaining layout of cells of conventional CMOS logical operation circuits and circuit diagrams thereof (b). Notations p1001 through p1003, n1001 through n1003, p110 through p1103 and n1101 through n1103 designate transistors. According to the layout of a cell of a CMOS logical operation circuit which has widely been used in a conventional gate array or standard cell system shown by FIG. 10 or FIG. 11, it is general to regularly arrange on a straight line input and output terminals In1001 through In1003 and In1101 through In1103 for outputting a signal to outside of the cell. This is because in the case of a CMOS logical operation circuit, a portion of a gate can be enlarged on an insulating film (not formed with transistor) present between a first type of a field effect transistor (for example, P-channel MOS) and a second type of a field effect transistor (for example, N-channel MOS) which are in a complementary relationship and accordingly, input and output terminals (In1001, In1002, In1003 and Out10 in FIG. 10, In1101, In102, In1103 and Out11 in FIG. 11) can easily be enlarged therefrom by a conductor layer.
In the meantime, a pass transistor logical operation circuit cell is constituted by one set or more of pairs of two pass transistors, a gate of each of which responds to a complementary signal and an output signal amplifier. It is a significant feature of a pass transistor logical operation circuit cell that a logical circuit portion and an amplifying circuit portion are separated in this way. In cell layout of such a pass transistor circuit, when input and output terminals are arranged on a straight line similar to a cell of the conventional CMOS logical operation circuit, there poses a problem in which an area efficiency is deteriorated by a restriction of a design rule concerning a conductor layer. Accordingly, in a pass transistor logical operation circuit cell, it is not well known how these input and output terminals are to be arranged.
Further, in laying out a pass transistor logical operation circuit having the above-described constitution, it has not been well known with regard to a problem of how to arrange the output signal amplifier and the pairs of pass transistors.
Further, in the case of laying out a pass transistor logical operation circuit cell having the above-described constitution and a CMOS logical operation circuit cell on the same chip, it has not been well known with regard to how to arrange a semiconductor region surrounding each transistor and having a type reverse to a type of the transistor (for example, n well in the case of pMOS transistor) in the cell.
Further, it has not been well known with regard to at which portion in a layout inside of a cell as well as outside of a cell, a circuit for generating complementary signals provided to respective gates in a pair of two pass transistors in the above-described pass transistor logical operation circuit cell, is to be arranged.
Further, in laying out field effect transistors constituting respectives of a signal polarity inverting circuit for forming complementary signals provided to respective gates of a pair of two pass transistors of the above-described pass transistor logical operation circuit and the above-described output signal amplifier, it has not been well known with regard to at which positions and in what magnitude relationship they are to be laid out.
Therefore, it is an object of the present invention with regard to a cell using a pass transistor circuit, to provide a semiconductor integrated circuit having a layout arrangement of input and output terminals, an output signal amplifier, pairs of pass transistors, well regions and a complementary signal generating circuit capable of reducing an area, reducing a delay time period and facilitating wirings outside of the cell.
In order to achieve the above-described object, a semiconductor integrated circuit according to the present invention is laid out under the following thought.
According to the present invention, there is used a cell having a portion constituted by at least one pass transistor circuit for forming a logic and at least one output signal amplifier. In this case, as a typical example of the present invention, an explanation will be given of a pass transistor logical operation circuit cell in the case in which three of pass transistor circuits are present in respect of a single output signal amplifier. As will be shown later in an embodiment of FIG. 1 through FIG. 3, each pass transistor circuit includes a first input node, a second input node and a third input node, an output node, a field effect transistor of a first type or a second type, a source/drain path of which is connected between the first input node and the output node and a field effect transistor of the first type or the second type, a source/drain path of which is connected between the second input node and the output node.
In this case, an output signal amplifier includes a circuit comprising an input node, an output node, a field effect transistor of a first type, a drain/source path of which is connected between the output node and first potential and a gate of which responds to the input node and a field effect transistor of a second type, a drain/source path is connected between the output node and second potential and a gate of which responds to the input node.
The output node of the pass transistor circuit is connected to the input of the output signal amplifier, an input signal is applied from outside of the cell to the third input node of the pass transistor circuit and the input signal from outside cell is applied to at least two of all of the first input node and the second input node of the pass transistor circuit.
The output node of the output signal amplifier operates to output an output signal to outside of the cell. One aspect of the thought of the present invention is characterized in arranging respective terminals by a conductor layer for drawing an input signal from outside of the cell and an output signal to outside of the cell. These are arranged as follows. That is, when a coordinate system (coordinate axes) is determined in a direction of running a supply line of the first potential and a supply line of the second potential and a direction orthogonal thereto, the terminals are arranged to include terminal grid points disposed at constant intervals in the coordinate system and at least one of terminal grid coordinates of the respective terminals differ from terminal grid coordinates arranged with at least two or more of the terminals other than the above terminals.
According to the above-described semiconductor integrated circuit of the present invention, when the coordinate system is disposed in the running direction of the potential supply line and the direction orthogonal thereto, input and output terminals are not disposed on the same coordinates. In other words, the input and output terminals are not aligned in a row, more specifically, these are not aligned in a row in a direction in parallel with the potential supply lines or a boundary line (contour) of the cell. Therefore, by providing an input to the gate of the pass transistor and an input to the source/drain of the pass transistor in directions of the coordinate system under the space rule of the conductor layer, the size of the cell can be reduced with regard to the direction of potential supply lines. In this case, the space rule refers to a rule of a minimum distance to prevent shortcircuit from causing in consideration of a deviation in matching a mask and a deviation in a process fabrication accuracy. Generally, with regard to the direction orthogonal to the direction of running the potential supply lines, the size of the cell is determined commonly in respect of all of cell groups used in blocks in the chip and accordingly, being capable of reducing the size in the direction of the potential supply lines, signifies being capable of reducing the area of the cell. Further, when wirings are provided among cells at an upper layer, the wirings need to draw from the input and output terminals and also in this case, since the input and output terminals are not disposed on the same coordinates, the wirings can be drawn from the respective terminals not only in the longitudinal direction but also in the transverse direction and there is achieved an advantage of promoting the degree of freedom of wirings.
According to a preferable embodiment of the present invention, when the coordinate system is determined in the direction orthogonal to the direction of running the supply line of the first potential and the supply line of the second potential, a terminal from outside of the cell for inputting an input signal applied to the third input node of the pass transistor circuit, is arranged to shift to a larger side or a smaller side in view of the coordinate system than a terminal from outside of the cell for inputting an input signal applied to the first input node and the second input node of the pass transistor circuit.
That is, according to the above-described semiconductor integrated circuit of the present invention, as will be explained later in the example of FIG. 1 through FIG. 3, the layout can be conducted reasonably since a wiring drawn from source/drain of a transistor of the pass transistor circuit to an input terminal and a wiring drawn from gate to the input terminal do not intersect with each other, whereby the size of the cell can be reduced.
Further, according to other preferable embodiment of the present invention, when two types of field effect transistors constituting the output signal amplifier determine the coordinate system in the direction of running the supply line of the first potential and the supply line of the second potential, the transistors are arranged to shift to at least one of the boundaries of the cell on a side where the coordinate values are minimized or on a side where the coordinate values are maximized.
That is, according to the above-described embodiment of the present invention, the output signal amplifier is arranged to shift to the cell boundary with regard to the direction of running the potential supply line and accordingly, even when a plurality of the pass transistor circuits are present, the output signal amplifier does not hinder wire connection among the plurality of pass transistor circuits and accordingly, the cell can reasonably be laid out to a small area.
Further, according to other preferable embodiment of the present invention, when a plurality of pass transistors circuit are present, the pass transistor circuits are developed to arrange successively in the direction of running the supply line of the first potential and the supply line of the second potential.
According thereto, even when the plurality of pass transistor circuits are present, a number thereof can be increased flexibly in the developing direction and accordingly, even when the number of the pass transistor circuits is increased, a cell library can regularly be laid out. Thereby, a time period consumed in layout design of the pass transistor logical operation circuit cell can be reduced.
Further, when the plurality of pass transistor circuits are present and the pass transistor circuits are developed to arrange in the direction of running the supply line of the first potential and the supply line of the second potential, a width of a source/drain region of a field effect transistor constituting the pass transistor circuit in the direction of running the supply line of the first potential and the supply line of the second potential is changed in accordance with locations in the same source/drain region. That is, the width is widened at a portion having contact and is narrowed at a portion having no contact.
According to the above-described constitution, the layout can be conducted such that the width of the source/drain region becomes a necessary source/drain width simply for constituting the transistor rather than a width prescribed by source/drain including contact and accordingly, in applying a space rule between source and drain (referred to as SD space rule), a source/drain region of a contiguous pass transistor circuit is made contiguous to the source/drain region of a portion having no contact by which the size in the running direction of the potential supply line can be reduced.
Further, the above-described cell is preferably constituted as follows. When a field effect transistor of a first type and a field effect transistor of a second type are arranged contiguously to a CMOS logical operation circuit cell constituting a logic by coupling them in a complementary relationship, the following constitution is preferable.
That is, a boundary of a semiconductor region of the second type surrounding the first type of the field effect transistor constituting the CMOS logical operation circuit and a semiconductor region of the first type surrounding the second type of the field effect transistor, and a boundary of a semiconductor region of the second type surrounding the first type of the field effect transistor constituting the pass transistor logical operation circuit and a semiconductor region of the first type surrounding the second type of the field effect transistor, are constituted to linearly connect at a connecting portion.
According to the above-described semiconductor integrated circuit of the present invention, when the cells are contiguous to each other, the well boundaries are linearly connected and therefore even when a minimum width of a region surrounding a transistor (referred to as a well minimum width) prescribed by the design rule, is not satisfied by a single cell, the rule can be satisfied by contiguously arranging a plurality of cells. Accordingly, as a result, the cell area can be reduced. When the embodiment according to the present invention is not used, in the case of arranging a pass transistor logical operation circuit cell and a CMOS logical operation circuit cell within the same block on the same chip, design rule error may be caused, for example, at a location where a single cell which cannot satisfy the rule of the well minimum width is arranged isolatedly. However, when the cell layout according to the present invention is carried out, the problem is resolved.
Further, as will be explained later in reference to FIG. 4 and FIG. 5, other preferable aspect of the present invention is characterized in that a boundary (referred to as well boundary) of a semiconductor region of the second type (referred to as second well) surrounding a field effect transistor of the first type constituting the pass transistor logical operation circuit and a semiconductor region of the first type (referred to as first well) surrounding the field effect type transistor of the second type, is brought to a side of the first semiconductor or to a side of the second semiconductor at inside of the cell and is arranged to be nonlinear at inside of the cell.
Thereby, regions of the field effect transistors constituting the pass transistor circuit can effectively be provided within the cell. That is, according to the CMOS logical operation circuit cell, normally, a transistor of the first type and a transistor of the second type are in a complementary relationship and their numbers coincide with each other. Therefore, transistors having the same numbers can be laid out on both sides of a well boundary drawn linearly with no problem. However, in the case of the pass transistor logical operation circuit cell, a number of transistors of a type the same as a type of transistors constituting the pass transistor circuit, is larger than a number of transistors of a type different therefrom. Meanwhile, when the boundary of the well is linearly laid out in the cell to be linearly connected to the CMOS logical operation circuit cell, even when there is constituted a distribution ratio of the first well and the second well suitable for the CMOS logical operation circuit, it becomes a distribution ratio which is not suitable for the pass transistor logical operation circuit cell in which a number of one type is larger than a number of other type. However, when the above-described embodiment of the present invention is used, a region for a transistor constituting the pass transistor circuit can be widened at inside of the cell and accordingly, a difference in the numbers of transistors can successively be realized.
Further, as will be explained in details in reference to FIG. 2, the semiconductor integrated circuit according to the present invention uses a cell comprising a pass transistor logical operation circuit having at least one set of pairs each of a pass transistor circuit and an inverter circuit of the signal polarity and at least one output signal amplifier. According to the pass transistor operation circuit of the logical operation circuit, there are provided a first input node, a second input node and a third input node, an output node, a field effect type transistor of a first type or a second type, a source/drain path of which is connected between the first input node and the output node and a field effect transistor of the first type or the second type, a source/drain path of which is connected between the second input node and the output node.
In this case, the signal polarity inverting circuit includes a circuit comprising, for example, an input node, an output node, a field effect type transistor of a first type, a drain/source path of which is connected between the output node and first potential and a gate of which responds to the input node and a field effect transistor of a second type, a drain/source path of which is connected between the output node and the second potential and a gate of which responds to the input node.
In this case, the output signal amplifier includes a circuit comprising an input node, an output node, a field effect transistor of a first type, a drain/source path of which is connected between the output node and first potential and a gate of which responds to the input node and a field effect transistor of a second type, a drain/source path of which is connected between the output node and second potential and a gate of which responds to the input node.
Further, the output node of the pass transistor circuit is connected to the input of the output signal amplifier. In this way, it signifies that by inserting the signal polarity inverting circuit to inside of the cell, one of input terminals constituting signal connection to outside of the cell is reduced in respect of a set of a pair of the pass transistor circuits and the signal polarity inverting circuit. This signifies that an amount of wiring at outside of the cell is reduced in comparison with the case in which the signal polarity inverting circuit is laid out at outside of the cell and connected therefrom to two of the input terminals of one pass transistor circuit and wiring is easy to carry out since a crowdedness of wiring at outside of the cell can be reduced, which is effective. Further, it is preferable that a difference between delay times of complementary signals which are to be inputted to two input terminals of one pass transistor circuit, is small. Because, when the difference between the delay times is large, although the above-described pass transistor circuits are originally fabricated by assuming that only one of them is made ON, there causes a case in which both are made ON or the case both are made OFF. Now, when gate inputs of two pass transistors to which the above-described complementary signals are inputted, are drawn to outside of the cell independently from each other, it is conceivable that complementary signals are transmitted to these two inputs by using separate wirings. In such a case, when there is considerable discrepancy in arrival times of signals by reason in which lengths of the separate wirings differ, there can be brought about an unpreferable situation in which both are made ON or both are made OFF as mentioned above. However, according to the semiconductor integrated circuit of the above-described embodiment of the present invention, the signal polarity inverting circuit is inserted to inside of the cell and accordingly, the difference between the delay times to the gate inputs of the two pass transistors can be restrained to a small value of only a delay time of the signal polarity inverting circuit at most.
Further, as in later detailed explanation of a constitution in reference to FIG. 1 and FIG. 2, in a cell comprising a pass transistor logical operation circuit having at least a set of pairs each of a pass transistor circuit and a signal polarity inverting circuit and at least one output signal amplifier, the signal polarity inverting circuit in the logical operation circuit includes a circuit comprising an input node, an output node, a field effect transistor of a first type, a drain/source path of which is connected between the output node and first potential and a gate of which responds to the input node and a field effect transistor of a second type, a drain/source path of which is connected between the output node and second potential and the gate of which responds to the input node.
The output signal amplifier in the logical operation circuit includes a circuit comprising an input node, an output node, a field effect transistor of a first type, a drain/source path of which is connected between the output node and first potential and a gate of which responds to the input node and a field effect transistor of a second type, a drain/source path is connected between the output node and second potential and a gate of which responds to the input node.
The output node of the pass transistor circuit is connected to the input of the output signal amplifier, the first type of the field effect transistor constituting the output signal amplifier is provided with a gate width larger than that of the first type of the field effect transistor constituting the signal polarity inverting circuit and the second type of the field effect transistor constituting the output signal amplifier is provided with a gate width larger than that of the second type of the field effect transistor constituting the signal polarity inverting circuit.
One aspect of the present invention clearly provides a guiding principle in how to design the channel width of the field effect transistor constituting the signal polarity inverting circuit. That is, a circuit outside of the cell driven by the output signal amplifier is not known at a time point of the layout, in consideration of fan-out or a wire capacity at outside of the cell, there must be assumed a case of driving a comparatively large load capacity, in contrast thereto, the signal polarity inverting circuit may only drive the gate of the pass transistor circuit at inside of the cell. When the channel width of the field effect transistor constituting the signal polarity inverting circuit is made larger than the channel width of the field effect transistor constituting the output signal amplifier, regardless of the relationship of the load capacity, large capacity is driven by a small transistor and small load capacity is driven by large capacity, as a result, there poses a problem in which a delay time period of a total is increased. In contrast thereto, by conducting layout such that the channel width of the field effect transistor constituting the signal polarity inverting circuit is made smaller than the channel width of the field effect transistor constituting the output signal amplifier, the respectives can be constituted by transistor sizes pertinent to driven load capacities and the delay time period can be reduced.
Further, according to a preferable embodiment of the present invention, the output node of the pass transistor circuit is connected to the input of the output signal amplifier and the field effect transistor constituting the pass transistor circuit, is arranged between field effect transistors of a first type and a second type constituting the signal polarity inverting circuit with regard to a direction orthogonal to a direction of running a supply line of the first potential and a supply line of the second potential.
By arranging them in this way, the space rule in view of layout between the source/drain region and the semiconductor region (well or substrate) surrounding thereof is not adopted unnecessarily, wire connection among pass transistor circuits and installation of an electricity feeding line to the source of the signal polarity inverting circuit can reasonably be carried out and accordingly, as a result, the cell area can be reduced.
Further, preferably, the output signal amplifier in the logical operation circuit includes a circuit comprising an input node, an output node, a first field effect transistor of a first type, a drain/source path of which is connected between the output node and first potential and a gate of which responds to the input node, a second field effect transistor of a second type, a drain/source path of which is connected between the output node and second potential and a gate of which responds to the input node and a third field effect transistor of the first type, a drain/source path of which is connected between the input node and the first potential and a gate of which responds to the output node. Further, according to the output signal amplifier, wire connection from the drain of the third field effect transistor to the gates of the first field effect transistor and the second field effect transistor is realized by passing the wire connection below a first potential supply line by using a material for the gate terminal of the transistor.
In this way, by using the gate material as a wiring, the portion below the potential supply line can effectively be utilized and accordingly, there can be resolved a problem in which wiring operation becomes difficult which is caused when wirings at vicinities of the first field effect transistor and the third field effect transistor of the output signal amplifier are crowded.
Other objects and novel characteristics of the present invention will become apparent by the following embodiments.