1. Field of the Invention
This disclosure relates to a semiconductor memory device, and more particularly to a semiconductor memory device which can uniformly change a voltage level of an internal voltage generating line and a layout method thereof.
2. Description of Related Art
An internal voltage generating circuit of a conventional semiconductor memory device includes an internal voltage generating circuit for a memory cell array and an internal voltage generating circuit for a peripheral circuit.
Each of the internal voltage generating circuits includes a standby internal voltage generating circuit which operates in both a standby mode and an active mode and an active internal voltage generating circuit which operates in only an active mode.
The active internal voltage generating circuit of the internal voltage generating circuit for a memory cell array supplies an internal voltage to a PMOS bit line sense amplifier which senses and amplifies a voltage of a bit line.
FIG. 1 is a block diagram illustrating a layout of a conventional semiconductor memory device. The semiconductor memory device of FIG. 1 includes a memory cell array 10, a column decoder 12, a column control circuit 14, a row decoder 16, a standby internal voltage generating circuit 18, an active internal voltage generating circuit 20, and drivers 20-1 to 20-3.
In FIG. 1, SIVC stands for the standby internal voltage generating circuit 18, AIVC stands for the active internal voltage generating circuit 20, D stands for the drivers 20-1 to 20-3, and 22 represents an external voltage applying pad 22. WL stands for one representative word line, BL stands for one representative bit line, and CSL stands for one representative column selecting line.
In FIG. 1, the memory cell array 10 includes four memory cell array blocks 10-1 to 10-4. Each of the memory cell array blocks 10-1 to 10-4 includes four sub memory cell array blocks MCA. A sub word line driver SWD is arranged between two adjacent memory cell array blocks MCA that are vertically aligned, and a bit line sense amplifier SA is arranged between two adjacent memory cell array blocks MCA that are horizontally aligned. Since the bit line sense amplifier SA is shared by the memory cell array blocks MCA arranged on its right and left sides, there is no need that it is arranged between all memory cell array blocks MCA. Each of the drivers 20-1 to 20-3 is arranged on a left side of the memory cell array 10 adjacent to the respective sub word line drivers SWD (i.e., location opposite to the column decoder 12), and each of internal voltage generating lines VINTA1 to VINTA3 is arranged to extend from an area where the respective sub word line drivers SWD is arranged. The internal voltage generating lines VINTA1 to VINTA3 are commonly connected to an internal voltage generating line VINTA.
However, since the active internal voltage generating circuit 20 and the drivers 20-1 to 20-3 of the conventional semiconductor memory device shown in FIG. 1 are arranged on one side of the memory cell array 10, the resistance of the internal voltage generating lines VINTA1 to VINTA3 becomes greater as the distance from the drivers 20-1 to 20-3 increases. Therefore, when the drivers 20-1 to 20-3 supply an internal voltage to the internal voltage generating lines VINTA1 to VINTA3 in an active mode, the farther it is from the drivers 20-1 to 20-3, the more a level of the internal voltage VCCA drops.
The internal voltage VCCA supplied to the internal voltage generating lines VINTA1 to VINTA3 are applied to the bit line sense amplifiers SA in an active mode and is used to amplify data of the bit line to an internal voltage VCCA level in a write/read mode. However, if the level of the internal voltage generating lines VINTA1 to VINTA3 is not raised up to an internal voltage VCCA level in an active mode, there is a problem in that data of the bit line cannot be amplified up to an internal voltage VCCA level in a write/read mode.
However, in the conventional semiconductor memory device of FIG. 1, the voltage level of the internal voltage generating lines VINTA1 to VINTA3 drops the further the line becomes from the drivers 20-1 to 20-3, and thus the sensing ability of the bit line sense amplifier SA arranged at a location far from the drivers 20-1 to 20-3 is degraded.
For the foregoing reasons, when a semiconductor memory device is designed that places the bit line sense amplifier SA far from the drivers 20-1 to 20-3, there is a problem in that a time period (tRCD) from a time point that an active command is applied to perform an active operation to a time point that a write/read command is applied to perform a write/read operation (an internal time period until a column selecting line CSL can be selected after a word line is enabled) becomes lengthy. That is, the semiconductor memory device is designed such that a write/read operation is performed after a level of the internal voltage generating lines VINTA1 to VINTA3 arranged at a location far from the drivers 20-1 to 20-3 reaches a desired internal voltage level. This delay becomes a significant obstacle in designing a high speed semiconductor memory device.
Embodiments of the invention address these and other disadvantages of the prior art.