This invention relates to a method and apparatus for decoding bi-phase encoded data such as data from a magnetic stripe card. More particularly, the present invention decodes data stored on magnetic stripe cards to control operation of another device, such as an electronic lock.
Magnetic stripes on magnetic stripe cards have magnetically encoded data in the form of a series of flux reversals on the stripes. These flux reversals have two functions. A first function is a clocking transition, and a second function is a data transition. The linear distance between two clocking transitions on a stripe is called a bit cell. When the bit cell contains no intermediate data transition or flux reversal, the bit cell is assigned the binary value zero. When the bit cell includes an intermediate flux reversal or data transition between the two clocking transitions, the bit cell is assigned the binary value one.
Problems occur as the speed at which the stripes move through the decoder varies. As the speed at which the magnetic stripe card is moved through the read head changes, the time between flux reversals representing length of the bit cell also changes. Therefore, one key to decoding data on magnetic stripe cards is to determine the bit cell length so that intermediate data transitions signifying a logical value one are not confused with an end transition of the bit cell. Since the bit cell both begins and ends with a clocking transition, it is difficult to determine whether a given transition represents the closing clocking transition of a zero value cell, or the interim data transition in a logical one value cell.
Prior art decoders use the concept of averaging at least the preceding two bit cell lengths to estimate the probable length of the current bit cell. One prior art decoder disclosed in U.S. Pat. No. 4,626,670 to Miller calculates two-thirds of the average time length and then uses this value as an optimum test time for determining whether a data transition has occurred in the current bit cell. If a data transition has occurred before the optimum test time expires, the decoder disclosed in the '670 patent assumes the bit cell has a logic value one. If no data transition has occurred prior to the optimum testing time, the '670 patent decoder assumes that the bit cell has a logic value zero.
Two problems associated with decoding data from magnetic stripe cards include acceleration and jitter. As the magnetic card is accelerated through a read head, time intervals between detected flux reversals change. Jitter results from inconsistencies in the magnetic recording material. Both acceleration and jitter can result in decoding errors. However, jitter causes substantially more problems than acceleration when decoding data from magnetic stripe cards. An object of the apparatus and method of the present invention is to reduce inaccuracies in decoding data from magnetic stripe cards caused by jitter.
The decoder of the present invention does not calculate the optimum time to test whether a data transition has occurred within the current bit cell from a predicted bit cell time length. Instead, the decoder of the present invention uses a novel "look-ahead" approach to decoding bi-phase data. In one embodiment of the present invention, the decoder uses the length of the previous bit cell as a predicted bit cell length for the next bit cell to determine whether the next edge transition or whether the next two edge transitions are most likely to be a bit cell. If the length from a previous edge transition to the next edge transition is closer to the predicted bit cell length, then the bit cell is assigned a logic value zero. If the length from the previous edge transition to the second edge transition is closer to the predicted cell length, then the bit cell is assigned a logic value one.
The decoder of the present invention advantageously checks the lengths of both of the next two edge transitions in order to choose the length which most accurately reflects the predicted bit cell length. Therefore, the present invention uses a quantitative approach to decode data from the magnetic stripe cards, as opposed to a predictive approach disclosed in the '670 patent.
According to one aspect of the present invention, a method is provided for decoding bi-phase encoded data. The method includes the steps of establishing a predicted bit cell length for a bit cell, detecting a leading clocking edge transition of the bit cell, detecting a first edge transition after the leading clocking edge transition, and calculating a first time interval from the leading clocking edge transition to the first detected edge transition. The method also includes the steps of detecting a second edge transition after the leading clocking edge transition, calculating a second time interval from the leading clocking edge transition to the second detected edge transition, comparing both the first time interval and the second time interval to the predicted bit cell length, assigning a logical zero value to the bit cell if the first time interval is closer to the predicted bit cell length than the second time interval, and assigning a logical one value to the bit cell if the second time interval is closer to the predicted bit cell length than the first time interval.
In one embodiment of the present invention, the step of establishing the predicted bit cell length includes the steps of calculating an average length of a plurality of previous bit cells and setting the predicted bit cell length equal to the average length. In another embodiment, the step of establishing the predicted bit cell length includes the steps of calculating a length of a previous bit cell and setting the predicted bit cell length equal to the length of the previous bit cell.
In the illustrated embodiment, the method further includes the steps of setting a predicted bit cell length for a next bit cell equal to the first time interval if the bit cell is assigned a logical zero value during the assigning step. The method also includes the step of setting a predicted bit cell length for a next bit cell equal to the second time interval if the bit cell is assigned a logical one value during the assigning step.
The illustrated method includes the steps of setting the first detected edge as the leading clocking transition for a next bit cell and setting the second detected edge as the first detected edge for the next bit cell if the first time interval is closer to the predicted bit cell length than the second time interval. The method also includes the step of setting the second detected edge as the leading clocking transition for a next bit cell if the second time interval distance is closer to the predicted bit cell length than the first time interval.
According to another aspect of the present invention, an apparatus is provided for decoding bi-phase encoded data. The apparatus includes a read head for reading data from a magnetic stripe card. The read head generates an output signal including a plurality of edge transitions corresponding to a plurality of flux reversals on the magnetic stripe card. The apparatus also includes means for detecting a leading clocking edge transition of a bit cell, a first edge transition after the leading clocking edge transition, and a second edge transition after the leading clocking edge transition from the output signal. The apparatus further includes means for establishing a predicted bit cell length for a bit cell, means for calculating a first distance from the leading clocking edge transition to the first detected edge transition, means for calculating a second distance from the leading clocking edge transition to the second detected edge transition, and means for comparing both the first distance and the second distance to the predicted bit cell length. The apparatus still further includes means for assigning a binary data value to the bit cell. The assigning means assigns a logical value zero to the bit cell if the first distance is closer to the predicted bit cell length than the second distance. The assigning means assigns a logical value one to the bit cell if the second distance is closer to the predicted bit cell length than the first distance.
In one illustrated embodiment, the means for establishing a predicted bit cell length includes means for calculating an average length of a plurality of previous bit cells, and means for setting the predicted bit cell length equal to the average length. In another illustrated embodiment, the means for establishing a predicted bit cell length includes means for calculating a length of a previous bit cell, and means for setting the predicted bit cell length equal to the length of the previous bit cell.
In the illustrated embodiment, the apparatus includes means for setting a predicted bit cell length for a next bit cell equal to the first distance if the assigning means assigns a logical zero value to the bit cell. The apparatus also includes means for setting a predicted bit cell length for a next bit cell equal to the second distance if the assigning means assigns a logical one value to the bit cell.
Also in the illustrated embodiment, the apparatus includes means for setting the first detected edge as the leading clocking transition for a next bit cell and means for setting the second detected edge as the first detected edge for the next bit cell if the assigning means assigns a logical zero value to the bit cell. The apparatus also includes means for setting the second detected edge as the leading clocking transition for a next bit cell if the assigning means assigns a logical one value to the bit cell.
Additional objects, features, and advantages of the invention will become apparent to those skilled in the art upon consideration of the following detailed description of a preferred embodiment exemplifying the best mode of carrying out the invention as presently perceived.