1. Technical Field
The present invention relates generally to logic circuits for use in adders and comparator units wherein the functional signals propagate, generate and zero are used. More specifically, the present invention relates to an improved logic circuit that merges more than two groups of propagate, generate, and zero functions, thereby reducing the number of required levels. It also relates to an improved logic circuit that forms the propagate, generate, and zero functions of a two-bit group. It also relates to an improved comparator that is comprised of these circuits.
2. Description of the Related Art
Digital logic circuits are well known in the art. They are used in such circuits as adders and comparators. In an adder circuit, the first level of adders typically forms the functions propagate, generate and zero (P, G, and Z, respectively). The next level of logic merges these functions for two-bit groups and subsequent levels merge pairs of these functions from the previous level to form the P, G, and Z functions of larger and larger groups, doubling at each level. One way of reducing the number of levels in the adder is to be able to merge more than two groups at a time.
Another commonly used digital circuit is a magnitude comparator. Magnitude .comparators compare two numbers, A and B, and activate one of three output signals corresponding to whether A is greater than B, A is equal to B, or A is less than B. In many cases, it is important that this circuit be fast. It is also desirable that it be small, thus occupying a small portion of chip real estate. One method of minimizing the size of the comparators is to reduce the number of transistor devices used.
Accordingly, what is needed in the art is an improved digital logic circuit that has a faster operation time, reduces the amount of chip real estate required, and is simple in design. What is further needed is an adder circuit or magnitude comparator, which relies on the improved logic circuit.