1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to the fabrication of small semiconductor features, such as floating gate or other semiconductor memory device structures.
2. Description of the Related Art
As the size of semiconductor device is scaled down, the requirements for device design and fabrication continue to be tightened in order to fit more circuitry on smaller chips. To achieve higher device packing densities, smaller and smaller sizes are required for device features, such as gate electrodes, interconnect lines, spacing and diameter of contact holes, and the surface geometry, such as corners and edges of various features. In addition, the spacing between adjacent features of an integrated circuit is also reduced in order to obtain higher packing densities.
Prior approaches used high resolution photolithographic processes in order to achieve small feature by improving the control of the length or width and placement of device features, such as the floating gates used in non-volatile memory (NVM) cells. For example, with NVM devices, the printing and etching of spaces in a floating gate poly layer is becoming more and more difficult as the poly-to-poly space shrinks. Conventional approaches for defining and separating the floating gates have required high resolution photolithographic processes to pattern and etch a space in a previously deposited polysilicon layer. With this process, the unetched polysilicon layer located over the active region serves as the floating gate(s) for the NVM bitcell. However, the selective etching of the polysilicon layer can result in overetching effects, such as mouse bites in the upper surface of a floating gate where the reduced width of the floating gate does not allow enough photoresist to protect the floating gate. Another overetching effect from conventional approaches is that the etched floating gates are too small, which can degrade device performance from the reduced charge storage capacity of the overetched floating gate.
Accordingly, a need exists for a smaller device features that are fabricated with a controlled process. There is also a need for a controlled fabrication process that reliably produces reduced spacing between device features. In addition, there is a need for improved semiconductor device structure and manufacturing process to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.