1. Field of the Invention
The present invention is related to a solid-state image capturing element, such as a MOS solid-state image capturing element, constituted of a semiconductor element for performing a photoelectric conversion on and capturing an image of image light from a subject, and an electronic information device, such as a digital camera (e.g., a digital video camera or a digital still camera), an image input camera (e.g., a monitoring camera), a scanner, a facsimile machine, a television telephone device and a camera-equipped cell phone device, including the solid-state image capturing element as an image input device used in an image capturing section thereof.
2. Description of the Related Art
The conventional MOS solid-state image capturing element of this kind is capable of being driven by a single power supply with low electric power consumption, thereby economically far more advantageous compared to a CCD solid-state image capturing element. However, the MOS solid state image capturing element has a small electric potential modulation under a transfer gate owing to a low power supply voltage. Owing to this fact, the MOS solid state image capturing element has a disadvantage of difficulty in complete electric charge transferring of signal charges from a photodiode PD of a light receiving section to a floating diffusion FD, the light receiving section being for performing a photoelectric conversion on incident light and generating the signal charges.
In order to solve the problem, Reference 1 proposes a way of providing a channel constituting layer under a transfer gate to improve controllability of the degree of electric potential modulation, thereby achieving the complete electric charge transferring.
FIG. 12 is a longitudinal cross sectional view schematically illustrating an exemplary essential part structure of the conventional solid-state image capturing element disclosed in Reference 1.
In FIG. 12, a conventional solid-state image capturing element 100 includes a well region 102, in which, for example, p-type impurities are diffused, formed on a silicon substrate 101. The impurity concentration of the well region 102 is as low as the order of E15 (E15 being 10 to the power of fifteen). N-type impurities are injected into the well region 102 as a photodiode 103 to form an n-type region 103a. A p+ surface layer 103b is formed on the n-type region 103a for the protection thereof. The photodiode 103 is constituted of the n-type region 103a and the p+ surface layer 103b. 
A detection node section 104 is formed by the injection of the n-type impurities next to the photodiode 103 with the well area 102 of a predetermined distance in the surface direction interposed therebetween. A transfer gate 105, which constitutes a reading transistor for accumulating and reading signals, is formed on a substrate between the detection node section 104 and the n-type area 103a. The transfer gate 105 has a positional structure extending over the n-type area 103a and the detection node section 104, thereby constituting a MOS transistor with the detection node section 104 as a drain area and the n-type area 103a as a source area. Such a MOS transistor is capable of allowing signal charges X generated in the n-type area 103a to flow towards the detection node section 104 by controlling the voltage of the gate electrode 105. In the case where a gate of an amplifying transistor, for example, is connected to the detection node section 104, the signal charges X from the photodiode 103 can be provided to the gate of the amplifying transistor as a detection voltage by the controlling of the transfer gate 105.
In addition, a channel stop region 106 for separating elements is formed in a substrate surrounding an element area, being from the photodiode 103 through under the transfer gate 105 to the detection node section 104, as a unit pixel area. In addition, a channel implant (n-type penetration channel layer 107) is formed in the channel region under the transfer gate 105 and in an upper surface region of the detection node section 104, for setting a threshold value of the transfer gate 105 and the detection node section 104.
An element separating region is defined as the channel stop region 106 (high concentration p-type layer) herein; however, the element separating region may be separated by a LOCOS (Local Oxidation of Silicon) region, which is a thick oxide layer. In FIG. 12, the channel stop region 106 is represented by a high concentration p-type layer.
The concentration of the impurities in the n-type region 103a is at an intermediate level between the impurity concentration of the well region 102 and the impurity concentration of the p+ surface layer 103b. Further, since it is necessary to accumulate the signal charges, which are generated in the photodiode 103, in the n-type region 103a, it is necessary to set them to a positive electric potential. However, doing so will result in the extension of a depletion layer to a surface (upper surface) the n-type region 103a, definitely. When the depletion layer reaches the surface (upper surface) of the n-type region 103a, leakage current increases. This leads to the increase of the display irregularity during a dark instance. Therefore, it is necessary to design the impurity concentration of the p+ surface layer 103b formed on the surface (upper surface) of the n-type region 103a to be the highest.
In such a structure of the p+ surface layer 103b, the n-type region 103a is formed by a complete depletion. Therefore, the signal charges X generated by a photoelectric conversion corresponding to the amount of light received in the n-type region 103a, are accumulated in the substrate without being leaked.
The high concentration p+ surface layer 103b extends to below the transfer gate 105 definitely by heat treatment after ion implantation in a semiconductor manufacturing process. Therefore, once the high concentration p+ surface layer 103b extends to below the transfer gate 105, it becomes impossible to increase the electric potential below the transfer gate 105 even by applying a predetermined voltage to the transfer gate 105 to excite a channel layer below the transfer gate 105 (state of electrical conduction) by a high concentration p region. As a result, it becomes highly difficult to easily read out the signal charges X from the photodiode 103.
Further, if the channel length L of the transfer gate 105 is shortened by the low concentration p well region 102, the depletion layer extends from the n-type region 103a, which corresponds to a source region, and the detection node section 104, which corresponds to a drain region, resulting in punch-through.
If punch-through occurs in the transfer gate 105, a “channel length modulation effect (drain modulation effect)” occurs, which is the phenomenon of the electric potential of the drain region (detection node section 104) modulating the channel electric potential. As a result, problems occur, such as the worsening of the linearity of the signal light quantity and the electric charge output characteristics.
Thus, in a unit cell (unit pixel section) of the conventional solid-state image capturing element 100 comprising: the p-type well region 102 formed on the silicon substrate 101; the photodiode 103 constituted of the n-type region 103a and the high concentration p+ surface layer 103b; the transfer gate 105 proximal to the photodiode 103; and the detection node section 104 proximal to the other side of the transfer gate 105, it is structured such that a p-type barrier layer 108 is formed in the substrate below the transfer gate 105, the p-type barrier layer 108 having a higher concentration than the p-type well region 102, and further, the n-type region 103a and the n-type penetration channel layer 107 are included, n-type penetration channel layer 107 being formed below the transfer gate 105 proximal to the n-type area 103a. 
That is, in order not to cause the channel length modulation effect (drain modulation effect) or punch-through, the p-type barrier layer 108, which is the same type as the p-type well region 102 and has a higher concentration than the p-type well region 102, is provided below the transfer gate 105 and the p-type barrier layer 108 is provided in such a manner to be connected to both the n-type region 103a and the detection node section 104, herein. As a result, the depletion layers extending from both the n-type region 103a and the detection node section 104 can be suppressed. In addition, owing to the influence of the high concentration p-type barrier layer 108, there is a possibility of not being capable of reading out the signal charges of the n-type region 103a. As a countermeasure, a channel forming layer 109 is provided on the upper side of the p-type barrier layer 108. The channel forming layer 109 is positioned at the upper side of the p-type barrier layer 108 and is formed such that a part thereof protrudes from the n-type region 103a to below the transfer gate 105. The space of the channel forming layer 109 is small, and it occupies a proximal location in a part of the substrate below the transfer gate 105 and also in the n-type region 103a. 
With the structure as described above, the channel forming layer 109 acts as part of a signal reading path 110, thereby securing the signal reading path 110. Therefore, the signal charges X generated in the n-type region 103a is read out from the channel forming layer 109 along the n-type penetration channel layer 107 towards the detection node section 104.
FIG. 13 is a longitudinal cross sectional view schematically illustrating an exemplary essential part structure of a conventional solid-state image capturing element disclosed in Reference 2.
In FIG. 13, a conventional solid-state image capturing element 200 includes, as a unit pixel section 200a thereof a p-type well region 202 formed on an n-type semiconductor substrate 201; a photodiode 203 consisted of an n-type impurity region 203a and a high concentration p+ surface layer 203b on a front surface side of the n-type impurity region 203a; a transfer gate 204 for transferring signal charges accumulated in the photodiode 203; and a read out region 205 constituted of an n-type impurity region. A low concentration n-type impurity region 206 is provided extending from under the n-type impurity region 203a to the read out region 205. Further, a p-type impurity region 207 is formed at a location below the transfer gate 204. Note that 208 denotes a LOCOS oxide region for separating elements, and 209 denotes a gate oxide layer.
Reference 1: Japanese Laid-Open Publication No 11-284166
Reference 2: Japanese Laid-Open Publication No. 2003-31787