Field of the Invention
The invention relates to a magneto-resistive random access memory (MRAM) configuration containing at least two memory cell arrays. In each of the memory cell arrays, memory cells are provided at the crossovers between word lines and bit lines, at least one line type containing the word lines and bit lines is provided with line driver circuits.
As is known, the memory effect of MRAMs is based on a variable resistance of the individual memory cells of the memory. A MRAM memory cell is situated at the crossover point of two lines, namely in particular between a word line and a bit line. The memory cell itself contains two magnetic layers isolated from one another by a thin dielectric layer.
The value of the electrical resistance of such an MRAM memory cell depends, then, on the polarization of the magnetic layers. If both layers are polarized in the same direction, a low value resistance is present in the memory cell, whereas a high value resistance of the electrical resistance is obtained in the event of mutually opposite polarization of the two magnetic layers. In other words, depending on the polarization of the magnetic layers, a high (↑) or low (↓) resistance results for the memory cell containing the two magnetic layers and the intervening dielectric layer.
Of the magnetic layers, one layer is composed of a soft-magnetic material, whereas the other layer is produced from a hard-magnetic material. The soft-magnetic material is chosen such that its polarization can be reversed by a writing current on the word line and the bit line while such polarization reversal by the writing currents is not intended to be possible in the case of the hard-magnetic material.
In order, then, that the magnetic layer made of soft-magnetic material can be polarized in two opposite directions, it is necessary that at least one of two programming currents through the bit line or through the word line can flow in both directions through the respective line. For only then can it be ensured at the crossover point between the word line and the bit line that, given correspondingly directed programming currents at the crossover point, the magnetic field for polarization reversal in the magnetic layer made of the soft-magnetic material is strong enough for the polarization reversal.
The currents which flow through the memory cell are tunneling currents through the thin dielectric layer, so that a xe2x80x9cmagnetic tunnel junctionxe2x80x9d or xe2x80x9ctunnel junctionxe2x80x9d is present, which is why the MRAM memory cell is also referred to as a magnetic tunnel junction (MTJ) memory cell.
In the MRAM configuration, high parasitic currents occur on a selected word line or bit line, the currents ultimately being brought about by the numerous crossover points between a selected word line, for example, and the bit lines that cross it. On account of these high parasitic currents, therefore, a large MRAM configuration can only be constructed from a plurality of smaller memory cell arrays. Therefore, however, that, for each memory cell array containing, for example, m word lines and n bit lines, a total of 2m+n or 2n+m line driver circuits are required. For the MPAM configuration in its entirety, containing 1 memory cell arrays for example, 1(2m+n) or 1(2n+m) line driver circuits are then required. For the line driver circuits, however, a large area is required on a chip containing the MRAM configuration, which is extremely undesirable.
It is accordingly an object of the invention to provide a MRAM configuration which overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the area requirement for the line driver circuits is reduced by effective assignment of the latter, thereby obtaining a space-saving architecture.
With the foregoing and other objects in view there is provided, in accordance with the invention, a magneto-resistive random access memory (MRAM) configuration. The MRAM configuration contains at least two memory cell arrays. Each of the memory cell arrays has word lines, bit lines crossing the word lines, and memory cells disposed at crossover points between the word lines and the bit lines. Connecting nodes are provided, and one of the connecting nodes is disposed between and connecting each of the memory cell arrays to each other. Line driver circuits are connected to at least one of the word lines and the bit lines. The line driver circuits are respectively connected to the connecting nodes between the memory cell arrays. Switching transistors are provided. One of the switching transistors is disposed between one of the memory cell arrays and one of the connecting nodes so that the line driver circuits are respectively assigned to different ones of the memory cell arrays.
In the case of the MRAM configuration of the type mentioned in the introduction, the object is achieved according to the invention by virtue of the fact that the line driver circuits are respectively connected to connecting nodes between two memory cell arrays and a respective switching transistor is present between the connecting node and the two memory cell arrays.
In principle, the configuration of the MRAM configuration effects a departure from an obvious solution to the above problems which is based on respectively placing a current source or current sink at each end of a memory cell array. Rather, in the MRAM configuration according to the invention, the line driver circuits are disposed in such a way that they can be assigned to different memory cell arrays, which results in that the line driver circuits required in total are approximately halved compared with the prior art. Equally, it is possible to reduce the outlay for the current sources in the line driver circuits since a current source is allocated to two memory cell arrays in the present invention.
A development of the invention provides for the connecting node between two memory cell arrays to be connected to ground potential via an element having an adjustable voltage drop. As a result, a writing current, having traversed a memory cell array, readily passes to the ground potential via the output side connecting node of the memory cell array and the element having an adjustable voltage drop. By way of example, the adjustable voltage drop can be produced by a variable resistor, a variable transistor diode or an adjustable voltage source. The resulting adjustable voltage ensures that parasitic currents through the memory cells connected to the selective word or bit line can be minimized.
A respective series circuit containing a current source and a writing driver transistor is advantageously used for the line driver circuits. In this manner, the current source is assigned to two of the memory arrays. By way of example, an n-channel MOS field-effect transistor may be chosen for the writing driver transistor, and, moreover, this also applies to the switching transistor and the transistor diode.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a MRAM configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.