1. Technical Field
The present disclosure relates to memory refresh operations in general, and in particular to a method for scheduling refresh operations in high-density memories.
2. Description of Related Art
Dynamic random-access memories (DRAMs) are widely employed in a variety of applications. A typical DRAM has multiple blocks of memory cells, and each memory cell includes a capacitor and an access transistor. The capacitor stores a charge related to the value of data stored in a memory cell, and the access transistor selectively couples the capacitor to a bitline for reading from or writing to the memory cell.
Because of various leakage paths, a charge stored within a capacitor of a memory cell will typically dissipate in less than few tens of milliseconds. In order to maintain the integrity of data stored in a memory cell, the memory cell needs to be periodically refreshed by reading the data in the memory cell and rewriting the read data back into the memory cell before the stored charge has had the opportunity to dissipate.
According to the JEDEC standard, a DRAM device maintains an internal counter that designates the next segment of the DRAM device to be refreshed, and a memory controller issues an address-less Refresh command to the DRAM device. Two key JEDEC parameters that are closely associated with refresh operations are tREFI and tRFC. Parameter tREFI specifies the interval at which Refresh commands must be sent to a DRAM device, and parameter tRFC specifies the amount of time that a DRAM device interface is being tied up by each refresh operation.
Most conventional memory controllers simply send refresh operations whenever tREFI (which dictates a refresh timer) expires. This is sufficient for older computer systems where each refresh operation can be completed quickly such that read and/or write operations do not need to be delayed for a very long time. However, for high-density DRAM chips, such as 4-Gbit and 16-Gbit DRAM chips, a refresh operation generally takes quite some time to complete. The net effect is a measurable increase in effective memory latency when read and/or write operations are frequently required to be stalled in order to accommodate refresh operations.
Consequently, it would be desirable to provide an improved method and apparatus for performing refresh operations in high-density memories.