1. Field of the Invention
The present invention relates to a transistor in a semiconductor device and method of manufacturing the same, and more specifically, to a transistor in a semiconductor device having a VDMOS (Vertical Diffused MOS) structure suitable for a high-voltage operation, and method of manufacturing the same.
2. Discussion of Related Art
A transistor used in a high-voltage device is fabricated in a structure different from a common transistor. For example, a transistor is manufactured to have an EDMOS (Extended Drain MOS) or LDMOS (Lateral Diffused MOS) structure so that the transistor can operate stably at high voltage. Of them, a transistor of the LDMOS structure (hereinafter, referred to as “LDMOS transistor”) will be described.
FIG. 1 is a cross-sectional view for explaining the structure of a transistor in a semiconductor device in the related art.
Referring to FIG. 1, a LDMOS transistor includes a gate oxide film 104, a gate 105, dielectric film spacers 106 formed at the sidewalls of the gate 105, a source 107 and a drain 108. At this time, the source 107 has a low-concentration impurity region 107a and a high-concentration impurity region 107b, and the drain 108 has a low-concentration impurity region 108a and a high-concentration impurity region 108b. Unexplained reference numeral 102 indicates a well, 103 designates an isolation film and 109 indicates a well junction.
In the above, assuming that the size (LLDMOS) of the LDMOS transistor is from the edge of the high-concentration impurity region 107b included in the source 107 to the edge of the high-concentration impurity region 108b included in the drain 108, the size (LLDMOS) of the LDMOS transistor can be expressed into the following Equation 1.LLDMOS=2LD+2LDO+LGATE1  [Equation 1]where LD is a width from the edge of the high-concentration impurity region to the edge of the gate.LDO is a width that the low-concentration impurity region and the gate are overlapped.LGATE1 is a channel width.
In the above, in order for the LDMOS transistor to stably operate even at high voltage, the low-concentration impurity regions 107a and 108a have to be extended in the horizontal direction. Thus, the size of the transistor is increased. For example, in order for the LDMOS transistor to stably operate even at about 40V, it is required that LD be at least 1.5 μm and LGATE1 be at least 3 μm. At this time, assuming that LDO is 0.5 μm, the size of the LDMOS transistor becomes 7 μm.
If the channel width LGATE1 is reduced, the size of the LDMOS transistor can be reduced but the electrical properties of the transistor can be degraded due to a short channel effect.
For this reason, it is difficult to apply the conventional LDMOS transistor to a high-integration circuit. In particular, there is a problem that the conventional LDMOS transistor is difficult to implement SOC (System On Chip).