The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having main and sub bit lines.
One trend in recent semiconductor memory devices is toward larger storage capacity. Semiconductor devices having a large capacity have a plurality of memory cells connected to a single bit line. The memory cell in a flash memory, a read-only-memory (ROM), or an erasable and programmable read-only-memory (EPROM) typically comprises an MOS transistor. A drain of the MOS transistor is connected to the bit line. A parasitic capacitance exists between the drain and a semiconductor substrate on which the semiconductor memory device is formed. In addition, a small quantity of leak current flows from the drain to the semiconductor substrate. The parasitic capacitance and the leak current are not a problem for semiconductor memory devices having a small capacity. However, the sum total of the parasitic capacitance on and the leak current through the single bit line is not negligible for the semiconductor memory devices having a large capacity.
The bit line is typically connected to a sense amplifier. The sense amplifier discriminates information stored on the memory cell and produces a discrimination result as a signal of "0" or "1". The larger parasitic capacitance or leak current has disadvantages that the current for precharging the bit line increases and that a feeble signal read out of the memory cell cannot be discriminated by the sense amplifier.
Various semiconductor memory devices have been developed to solve the above-mentioned problems. More specifically, an example includes those having memory cells connected to a single bit line and divided into a several number of blocks. The memory cells of one block are connected to a sub bit line and a block selection transistor is placed between the sub bit line and a main bit line to connect them with each other. In other words, the semiconductor memory device of the type described comprises a plurality of sub bit lines each connected to the main bit line through the block selection transistors. The sub bit lines are connected to a plurality of memory cells. The main and sub bit lines are electrically connected to or disconnected from each other through the block selection transistors.
It looks as if the bit line is connected to the block selection transistors and to the memory cells in a selected block. This contributes to significant reduction of the parasitic capacitance and the leak current.
An example of this semiconductor memory device is disclosed in Japanese Patent Laid-open No. 8-204158. To be exact, the semiconductor memory device comprises a plurality of sub bit lines connected to memory cell transistors and a main bit line to which the sub bit lines are selectively connected. The semiconductor memory device also comprises an auxiliary wiring layer that is formed in the same conductive layer as a conductive layer for the main bit line and is electrically isolated from the main bit line. The auxiliary wiring layer is connected to the sub bit line. Thus the resistance of the sub bit line is restricted in the semiconductor memory device as represented by DINOR flash memories where the bit line is divided into the main and sub bit lines, which in turn results in higher level of integration as well as faster operation speed of the memory.
The sub bit line generally has its own resistance that restricts the length of the sub bit line and the number of memory cells per sub bit line that is connected to one block selection transistor. Twelve memory cell transistors are typically connected to one sub bit line. On the other hand, the above-mentioned restriction in the resistance of the sub bit line allows for thirty-two or more memory cell transistors to be connected to the single sub bit line. However, this configuration is not wholly beneficial in the above-mentioned semiconductor memory device where around a half of the sub bit line is formed with a polycide interconnection that has a high sheet resistance. The semiconductor memory device of this type has limitations in view of memory operation speed and level of integration. This is a drawback for the current semiconductor memory devices used in microcomputers that are very small computer systems where notable improvement in performance has been achieved because there has been a significant demand towards semiconductor memory devices much faster than those conventionally used. Nevertheless, a larger semiconductor memory device comprises longer bit lines. Such a configuration increases the parasitic capacitance and the resistance, badly affecting the speed to read information out of the memory. This means further restriction of the resistance of the bit line has been required, that is difficult to achieve by the conventional semiconductor memory devices.