The invention relates to a semiconductor device with a MOS transistor of the depletion type comprising a semiconductor body with a substrate of a first conductivity type provided with a layer of the opposed, the second conductivity type adjoining a surface of said semiconductor body, in which layer a source zone of the second conductivity type, a drain zone of the second conductivity type, and an interposed channel region of the second conductivity type are defined, while a gate electrode is provided above the channel region, electrically insulated therefrom by an insulating layer, and the semiconductor body is further provided with a zone of the first conductivity type which forms a pn junction with the channel region and which adjoins the surface for the removal of minority charge carriers from the channel region. Such a device is known inter alia from the patent document U.S. Pat. No. 4,868,620.
Such transistors, often referred to as deep depletion MOST, may be used to advantage in high-voltage circuits, for example for deriving a lower voltage from the high supply voltage while connected as a source follower, which lower voltage may be used as a supply voltage for a low-voltage portion which is often present in an integrated high-voltage circuit.
In the semiconductor device known from the U.S. patent cited above, the semiconductor layer adjoining the surface is formed by an n-type epitaxial silicon layer provided on a p-type silicon substrate. An island is defined in the epitaxial layer by deep p-type insulation zones, in which island the source and drain are formed as strongly doped n-type zones, separated from one another by an n-type channel region with a lower doping level and an adjoining drift region. A gate electrode, separated from the channel by an oxide layer, is provided above the channel layer.
The current between source and drain in such a transistor is controlled by means of a depletion region which is induced in the channel by the voltage at the gate. At higher voltages, the operation may be hampered by the generation of minority charge carriers (holes in the case of an n-channel transistor), which form an inversion layer below the gate and screen off the latter from the channel, so that it is no longer possible inter alia to bring the transistor into the pinch state. To prevent an inversion occurring below the gate, the patent document U.S. Pat. No. 4,868,620 proposes the provision of a discharge for minority charge carriers in the form of a p-type surface zone. A suitable low voltage is applied to this zone via an electrical connection such that holes are removed across the blocked pn junction. To prevent punch-through between this discharge zone and the subjacent p-type substrate, a strongly doped n-type buried layer is provided below the zone between the epitaxial layer and the substrate, screening off the substrate from the epitaxial layer locally.
The zone forming a discharge for minority charge carriers in this known transistor is provided in the current path between source and drain and accordingly influences various electrical properties of the transistor to a non-negligible degree, for example its resistance, which is undesirable from a viewpoint of design technology. In addition, the construction of the transistor requires the availability of an epitaxial layer because of the presence of a buried layer, which means that it is not or hardly possible to provide the semiconductor layer, for example, in the form of an implanted layer.
The invention has for its object inter alia to provide a semiconductor device of the kind described in the opening paragraph in which the transistor is provided with a charge removal facility for minority carriers which is not situated in the current path between source and drain. The invention further has for its object to provide a transistor with a construction which allows of a higher flexibility in the manufacturing process than does the known transistor.
According to the invention, a semiconductor device of the kind mentioned in the opening paragraph is for this purpose characterized in that the channel region comprises two or more sub-regions which are mutually separated by said surface zone of the first conductivity type, which surface zone extends from the surface transversely across the thickness of the layer of the second conductivity type up to the substrate of the first conductivity type. The current path between source and drain in this device does not run below the removal facility for minority charge carriers, but instead next to this zone or between two zones in the case of several discharge zones distributed over the width of the channel, so that the resistance of the channel is substantially defined by the channel width. Since the removal zone for minority charge carriers is connected to the substrate of the same conductivity type, it is not necessary to provide the removal zone with a connection to the surface of the semiconductor body, but the minority charge carriers can be discharged via the substrate. In addition, it is not necessary to form a buried screening zone between the removal zone for minority charge carriers and the substrate, so that the semiconductor layer may be formed not only by epitaxy but also by means of ion implantation.
An embodiment which has the advantage that the pinch voltage is defined by the vertical depletion region induced by the insulated gate and not by the lateral depletion region induced by the surface zone is characterized in that the sub-regions of the channel region have a width which is greater than the thickness of the channel region and in comparison with said thickness is so great that the transistor is pinched by the depletion region induced by the gate.
Although alternative designs may also be used to advantage, special advantages are obtained in embodiments wherein a subdivided channel region and a subdivided surface zone of the first conductivity type in conjunction form a closed structure around the drain (or the source), as seen at the surface, while the source (or the drain) zone is situated outside this closed structure. A preferred embodiment of such a device is characterized in that the channel region, seen in plan view, has the shape of a polygon in which that portion of the semiconductor layer which is enclosed by the polygon comprises the drain and that portion of the semiconductor layer which is situated outside the polygon comprises the source, while a number of surface zones of the first conductivity type are present for the removal of minority charge carriers, which surface zones are present at the corners of the polygon, and the sub-regions of the channel region are situated at the lateral sides of the polygon. Preferably, the polygon is formed by a regular polygon, for example a square. A further embodiment is characterized in that the lateral sides of the polygon are each provided with at least one further surface zone of the first conductivity type which extends transversely across the thickness of the semiconductor layer for the purpose of removal of minority charge carriers.