Capacitors used in a semiconductor device are generally classified as a PIP (poly/insulator/poly) structure or a MIM (metal/insulator/metal) structure. Use of either of the PIP and MIM structures is based on the application in which a capacitor is used. The MIM structure is often used for high frequency semiconductor devices or applications. This is because in the case of a high frequency device undergoing a variation of characteristics due to a RC delay, it is preferable to employ the MIM structure using metals having superior electrical properties.
Conventional techniques for forming capacitors using the MIM structure are disclosed in U.S. Pat. Nos. 6,468,858, 5,406,447 and 6,597,068.
FIG. 1 shows a general MIM structure. As shown in FIG. 1, the MIM structure comprises a first metal layer 11, an insulation line 12 and a second metal layer 13, which are stacked in order. The first metal layer 11 includes two Ti/TiN films and an AlCu film sandwiched between the Ti/TiN films, for example. The second metal layer 13 includes one Ti/TiN film, for example. The insulation film 12 is located between the first and second metal layers and is formed of a nitride film, for example.
A metal reactive ion etching (RIE) process is commonly used to fabricate the capacitor using the above-described MIM structure. However, in this process, nitride residues 14 are roughly or unevenly formed on a surface of the nitride film.
The formation of the rough nitride residues 14 is due to the use of a thin nitride film and the inadequacy of process conditions, which result in small etching margin and application disability of process conditions prominent in removal capacity of nitride.
In addition, the rough nitride residues are not removed in subsequent processes as the property of the nitride film is changed in a metal cleaning process. If etching time is increased to remove the nitride residues, a lower layer may be exposed in a plurality of locations. This causes pattern defects, which is a factor of a pattern short, in a subsequent patterning process. Therefore, there is a practical limit to the amount that the etching time can be increased.