1. Field of the Invention
The present invention is related to processing systems and processors, and more specifically to techniques for controlling resources allocated to hardware threads by measuring rates of instruction completion for multiple threads.
2. Description of Related Art
Allocation of resources to hardware threads executing within a simultaneous multi-threaded (SMT) processor has been controlled by a variety of techniques. Typically, various priority values are set by either properties of the programs to which threads belong and the functions of the threads, in order to allocate more resources to high-priority threads and less resources to lower-priority threads. Also typically, the mechanism for controlling the resources allocated to a thread is implemented by controlling the relative instruction fetch rate for the threads. More recently, control of the instruction decode rate for each thread has been used to control relative thread priority.
The input to thread priority control schemes has been determined from various metrics that indicate whether or not a thread will execute efficiently. For example, a thread that is generated a large number of cache misses or translation look-aside buffer (TLB) misses may be throttled to improve performance, e.g., by reducing the fetch rate or decode rate for that thread. Other techniques measure the average memory latency for a thread, or the number of branches present in a thread, as the number of branches is a predictor of how many stalls or speculative instructions may be encountered in execution of a thread, which is a predictor of thread performance. Further, in processors supporting speculative execution of instructions, the speculatively executed instructions are sometimes executed at a lower priority in order to reduce the impact of mis-speculation on performance.
However many of the above techniques require multiple metrics to control thread priority may measure irrelevant events, such as cache misses in non-taken branch paths, and in some cases the events on which thread priority control is based can be difficult to measure.
Therefore, it would be desirable to provide thread scheduling control from single metric that is easy to measure and that has a strong relationship to actual thread performance.