1. Field of the Invention
This invention relates to arrays of logic gates capable of being programmed and reprogrammed. In particular, this invention relates to programmable logic arrays employing electrically erasable fuses for the programming capability.
2. Background of the Invention
Programmable logic arrays are arrays of logic gates, typically an array of AND gates leading into an array of OR gates, interconnected so as to allow implementation of a large number of logic equations. Fuses are employed at the interconnections between the logic gates and inputs to allow programming of the array by blowing selected fuses. A one-time programmable logic array circuit of this type is disclosed in U.S. Pat. No. 4,124,899 to Birkner et al. The term programmable logic array or PLA is generally used to refer to logic arrays where a programmable array of AND gates is connected to a fixed array of OR gates and the term programmable read only memory or PROM usually refers to an array having a fixed array of AND gates and a programmable OR array. The term programmable logic array or PLA as used here, however, refers to any programmable array of logic gates and thus encompasses both programmable AND arrays and programmable OR arrays.
Programmable logic arrays have many applications stemming from their capability to implement a wide variety of logic equations on a single integrated circuit. In particular, such programmable logic arrays make effective interfaces between large scale integrated circuits and the specific circuit board requirements of a design engineer. A disadvantage of systems employing blown fuses for programming, however, is their one-time only programmability. For example, if a mistake is made in the original programming of the logic array the entire integrated circuit is useless and has to be discarded. Also in a design environment flexibility to try different logic designs is desired. In a one-time programmable logic array a new integrated circuit logic array must be used for each new design choice with resultant expense.
Another shortcoming of the prior art one-time programmable logic array is the relatively high voltage needed to blow the fuses in the programming of the array. Such programming requires a high voltage to be applied to selected pins of the programmable logic array integrated circuit requiring a special programming device. One time programmable logic arrays cannot be completely tested prior to delivery to customers by the manufacturer, since doing so would destroy programmability.
A class of reprogrammable logic arrays is known in the prior art in the form of so-called erasable programmable read only memories, or EPROMs. EPROM logic arrays utilize programmable transistors instead of fuses to program the logic array. In the case of EPROMS the programmable array is an array of OR gates and, as the name implies, such arrays are used as memory devices. Such EPROM devices typically employ a floating gate MOSFET transistor which may be programmed into a conducting or nonconducting state. The programmable floating gate transistors may be either erased by application of ultraviolet light or by applying an electrical signal to remove the charge from the floating gate. The latter are referred to as electrically erasable PROMs or E.sup.2 PROMs. The above noted two types of reprogrammable logic arrays generally suffer from a primary disadvantage of speed in programming and speed in operation of the logic functions. The ultraviolet erasable type usually suffers from a long time period required to erase the programmable transistor. Furthermore, in ultraviolet erasable logic arrays the entire array is typically erased simultaneously. Both types also suffer from delay due to the turning on of the floating gate transistor which often has a much higher capacitance, and is accordingly much slower, than a normal MOSFET transistor. Another disadvantage of currently available reprogrammable logic arrays is the lack of an implementation having an effective architecture for controlling programming and erasing of arrays with large numbers of gates.
The electrically erasable transistor fuse has also been suggested for other types of logic arrays than EPROMs in IEEE publication CH1616-2, 1980, Electrically Alterable Programmable Logic Array (EAPLA) by Li N. Chsieh, R. A. Wood and P. P. Wang. This reprogrammable logic array, however, utilizes a different form of electrically erasable transistor than is common in the art and its reliability and effectivenss are unclear. The fuse employed also would be quite slow due to the effect of the high capacitance of the floating gate transistor during read operations. Also, the architecture for programming the array is not shown in detail but appears to require a relatively large number of lines to program and read the array and have considerable power consumption and space requirements.