The present invention relates to a semiconductor memory device, and more particularly, to a flash memory device having reliable initialization data and a method of providing the same.
Semiconductor memory devices are largely classified into volatile semiconductor memory devices and non-volatile semiconductor memory devices. The volatile semiconductor memory devices are characterized by fast reading and writing speeds, but stored contents disappear when no external power is applied. On the other hand, the non-volatile semiconductor memory devices retain stored contents even when no power is applied. Therefore, the non-volatile semiconductor memory devices are used to store vital contents, which must remain regardless of power supply. Examples of the non-volatile semiconductor memory devices include a mask read-only memory (MROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), and an electrically erasable programmable read-only memory (EEPROM).
Since erase and write operations are relatively complicated in MROM, PROM and EPROM, typical users may not be able to update memory contents. In comparison, erase and write operations can be performed electrically in EEPROM, which is therefore used extensively for system programming or auxiliary memory devices, which require continuous updating. A flash EEPROM, in particular, has a higher degree of integration as compared to a typical EEPROM, and is therefore used in high-capacity auxiliary memory devices. With respect to flash EEPROMs, a NAND-type flash EEPROM (hereinafter referred to as a NAND flash memory) has a higher degree of integration, as compared to other types of flash EEPROM.
A typical memory device is an integrated circuit that stores information and reads the stored information, when necessary. A flash memory device includes multiple rewritable memory cells, each of which stores one-bit data or multi-bit data. The flash memory device can improve functionality through its high degree of integration, high capacity storage and an increase of chip size. As a result, circuit line widths decrease proportionately, and manufacturing steps and associated complexity tend to increase, causing a reduction in a yield of chips.
In response to such limitations, a semiconductor memory device may include a redundancy memory cell to replace defective memory cells. Additionally, the semiconductor memory device may include various means to switch an address of a defective cell to that of a redundancy memory cell. When detecting defective memory cells during a test, for example, an address of a defective cell may be changed to that of a redundancy cell through a series of processes for cutting a fuse in a fuse box. Accordingly, even if there is a defective cell in one chip, it can be replaced with non-defective cell(s), thereby increasing yield. However, there are technologies for storing an address of a defective cell on a non-volatile memory not on a fuse program, and reading the cell while powering-up, in order to perform a repair operation.
Exemplary redundancy circuits are disclosed in U.S. Pat. No. 6,118,712, entitled “REDUNDANCY FUSE BOXES AND REDUNDANCY REPAIR STRUCTURES FOR SEMICONDUCTOR DEVICES” (issued Sep. 12, 2000), and in U.S. Pat. No. 6,850,450, entitled “FUSE BOX INCLUDING MAKE-LINK AND REDUNDANT ADDRESS DECODER HAVING THE SAME, AND METHOD FOR REPAIRING DEFECTIVE MEMORY CELL” (issued Feb. 1, 2005), the respective subject matter of which are incorporated herein by reference.
FIG. 1 is a block diagram illustrating a structure of a typical flash memory device switching a row or column address of a defective cell into row redundancy or column redundancy. When a power-up detector 160 detects power input, a repair address stored in a memory cell is read and provided to a repair controller 150. The repair controller 150 stores the repair address on a register. The repair controller 150 compares an address input during a normal program or read operation with the repair address. When the input address is the same as the repair addresses, the repair controller 150 controls a column selector 140 or a row decoder 120 to switch the input address to the row redundancy or the column redundancy.
As described above, in a typical flash memory device, the reading and storing of a repair address are performed during a power-up operation interval right after power is applied. During the power-up operation interval, because the power supply of the flash memory device is not yet stabilized, operations of logic circuits determining or maintaining logic 0 or logic 1 are unstable. However, the flash memory device 100 reads a repair address from a cell array 110 during this time. The flash memory device needs a high voltage during a read operation, and if the high voltage is not sufficient, reliability of the read data is reduced. A page buffer 130, having multiple latch circuits, detects and latches data of a cell array when there is an unstable voltage supply state. Latch operations of logic 1 or logic 0 are not reliable during an unstable state. Furthermore, a progressive defect may exist in the cell array 110, regardless of power level. Due to the above limitations, the repair address read during the power-up operation interval may include an error, which deteriorates the operational reliability of the flash memory device.
According to the above incorporated references, there is no technology that provides a reliable repair address read during an unstable voltage supply state.