In the design of non-volatile memories, such as flash memory, there is a continuing process of improving these memories by increasing their storage density, increasing their performance, and reduce power consumption. Improvements in one of these requirements will often negatively affect one of the others. For example, to improve storage density, flash memory with multiple levels per cell can be used to replace the binary chips; however, the speed of operations can be slower in multi-state memories, such as in the case of writing data where the tolerances between states become stricter. Consequently, the performance level of memories having multi-level cells has much scope for improvement.
These and related problems, along with additional background information, is given in the Background section of US patent application publication numbers US-2006-0221704-A1 (now U.S. Pat. No. 7,206,230) and US-2007-0109867-A1 (now U.S. Pat. No. 7,577,037). The following US patent application publication numbers also provide additional background information: US 2006-0233023-A1 (now U.S. Pat. No. 7,619,922); US 2006-0233021-A1 (now U.S. Pat. No. 7,609,552); US 2006-0221696-A1 (now U.S. Pat. No. 7,447,078); US 2006-0233010-A1 (now U.S. Pat. No. 7,480,181); US 2006-0239080-A1 (now U.S. Pat. No. 7,463,521); and US 2007-0002626-A1 (now U.S. Pat. No. 7,486,558). As noted below, all of these are fully incorporated herein by reference.
Therefore there is a general need for high performance and high capacity non-volatile memory. In particular, there is a need for a compact non-volatile memory with enhanced read and program performance having an improved processor that is compact and efficient, yet highly versatile for processing data among the read/writing circuits.