1. Field of the Invention
The present invention relates to a process for producing an integrated circuit, including coating a substrate provided with wiring channels with a coating liquid for integrated circuit formation containing a component for conductive fine particle formation and/or conductive fine particles to thereby form an electrical circuit on the substrate, wherein the coating liquid for integrated circuit formation while being exposed to ultrasonic waves is applied to the wiring channels. The present invention also relates to a substrate with integrated circuit produced by this process.
2. Description of the Prior Art
Various integrated circuits are used in computers and other various electronic equipments. An increase of circuit density and an enhancement of circuit performance are demanded in accordance with the trend toward miniaturization and sophistication of such equipments.
In particular, for example, semiconductor integrated circuits will be specified. It is common practice to use, for example, a multilayer wiring circuit as shown in FIG. 5 for the purpose of increasing the integration of semiconductor integrated circuit. FIG. 5 is a schematic sectional view of semiconductor integrated circuit. The process for producing such an integrated circuit will be described below. A thermal oxidation film as the first insulating film 32 is formed on substrate 31 of silicon or the like. The first wiring layer 33 consisting of an aluminum film or the like is formed on the surface of the first insulating film 32. Interlayer insulating film 34 consisting of a silica film, a silicon nitride film or the like is provided by coating thereon according to, for example, the CVD method or plasma CVD method. Silica insulating film (planarizing film) 35 for planarizing the interlayer insulating film 34 is formed on the interlayer insulating film 34. The silica insulating film 35 is coated with the second insulating film 36 if necessary. Thereafter, the second wiring layer (not shown) is formed thereon, and the surface of the second wiring layer is coated with an interlayer insulating film, a planarizing film and an insulating film according to necessity.
However, in the wiring by means of an aluminum film, the aluminum constituting the wiring layer is oxidized at the sputtering performed in the forming of multilayer wiring to thereby increase the resistance value of wiring layer, occasionally resulting in conductive failure. Further, because of the difficulty in reducing the wiring width, there has been a limit in the forming of integrated circuits of higher density. Still further, in recent years, there is a new problem such that, with respect to long-distance wiring such as a clock line or a data bus line, the wiring resistance is increased in accordance with an increase of chip size, thereby causing an increase of propagation delay time of electrical signal (RC delay time=resistance×capacity) Therefore, it is now needed to use a material of lower resistance in wiring layers.
Accordingly, it has been proposed to perform Cu wiring in place of the conventional wiring with Al or Al alloys. For example, it has been proposed to first provide an insulating film superimposed on a substrate with wiring channels and subsequently deposit Cu in the wiring channels according to the electroplating method, CVD method, etc. so as to form an intended wiring. However, in this technique, it has been difficult to accomplish satisfactory deposition of Cu in minute wiring channels and connecting holes with the intent to densify wiring. Furthermore, it has been difficult to obtain deposit films with satisfactory planarity. Still further, it has been experienced that the deposit films are not dense films and have holes formed therein.
For coping with these problems, it has been proposed to employ a method (SOM method) wherein a solution containing ultrafine particles of Cu is applied onto a substrate provided with wiring channels according to the spin coating method to thereby form a circuit on the substrate (ULVAC TECHNICAL JOURNAL, No. 51, 1999, p. 15). However, in this technique, the thickness of deposit film which can be formed by one application is so small that the application must be repeated for realizing wiring with all the wiring channels filled up. Further, the spin coating method has a drawback in that, when it is intended to uniformly apply the solution containing ultrafine particles of Cu onto the entire surface of substrate, portion of the solution containing ultrafine particles of Cu would be applied outside the substrate, thereby causing the ratio of utilization of the solution containing ultrafine particles of Cu to be low.
Moreover, the deposition of metal fine particles, such as Cu fine particles, is effected by the weight of metal fine particles themselves, so that the closest packing with metal fine particles may not be realized. Thus, it has been experienced that the interparticulate resistance cannot be reduced to thereby disenable obtaining a circuit of satisfactorily low wiring resistance.