I. Field of the Invention
The present invention relates in general to a technique for compensating for clock skew in a data-processing system. More particularly, the invention relates to a clock skew compensation system for use in pipelined processors.
II. Background Discussion
In implementing a pipelined processor there is typically provided multiple sequential stages each including a pipeline or staging register. These registers are triggered by separate clock signals and typically have a datapath between them comprising combinatorial logic. With the use of high-speed digital logic circuitry, errors have been created when clocking data from one stage to the next. The errors are brought about because the separate clock signals may have an inherent skew relationship there-between. If this skew delay is greater than the minimum time required to propagate through the stage, erroneous data is registered in the staging register.
The clock skew that occurs can be attributed to a number of different factors. For example, there may be variations in the manufacturing process of the clock driver. There may be variations in skew that occur with temperature and fluctuations in voltage. In addition, each clock driver can have a different delay associated therewith based on, for example, when it was manufactured. Another component of clock skew is the difference between the physical distance each clock signal travels on the circuit board before reaching the corresponding staging register.
As digital logic becomes faster, the internal component delays become significantly faster than the on or off chip (clock driver) delays. This exaggerates the skew problem because the stage clocks derived from the clock driver are experiencing greater relative delays while the propagation delay of the internal stage logic is reduced. This trend makes it difficult to manage the problem of guaranteeing that the data from the staging register at the beginning of the stage does not change, propagate through the stage and reach the staging register at the other end of the stage, before the previous state information is registered. This skew problem is most difficult if the two staging registers and the stage logic are all resident in the same VLSI component.