The present invention is generally related to doped contact structures for amorphous silicon field effect transistors (FETs). More particularly, the present invention is directed to an FET device with a n-doped amorphous silicon layer which reduces the intrinsic source and gate capacitance and which does not degrade the performance of the device by introducing voltage drops at the source or gate contact. The resulting FET device is particularly useful in matrix addressed liquid crystal displays (LCDs).
Amorphous silicon FETs provide an attractive choice for high contrast flat panel type television displays. These displays typically include liquid crystal material disposed between conductive electrodes arranged in a horizontal and vertical array so as to provide a large plurality of picture elements (pixels). Application of voltages to the electrodes orients the liquid crystal material so as to affect the transmission of light through the material. Since at least one set of electrodes (and its corresponding substrate) is transparent, a visible image is thereby displayed. In the process, each one of the pixel elements operates very much like to an electrical capacitor. In fact, an effective liquid crystal capacitance C.sub.LC is associated with each pixel element. Ideally, in a FET addressed liquid crystal display (LCD), when a FET is turned on, the liquid crystal pixel capacitor C.sub.LC charges to the data or drain line voltage. When the FET is turned off, the data voltage is stored on C.sub.LC. However, there are many parasitic capacitances in the display structure which are not negligible when compared to C.sub.LC. Two important parasitic capacitances are the source to drain capacitance, C.sub.SD, and the source to gate capacitance, C.sub.SG or C.sub.GS. In particular, the source to gate capacitance is of particular concern herein.
Consider the effect of the source to drain capacitance, C.sub.SD. The worst case condition is when one element in a column of the display is turned off and all other elements in the column are turned on. In this case, the desired voltage across the pixel element capacitor, V.sub.LC should be zero while the voltage V.sub.LC across all of the other pixel elements in the column should be V.sub.O. The rms voltage on the data line is then approximately V.sub.O and the voltage induced on the "off" pixel element is .delta.V.sub.LC =V.sub.O C.sub.SD /C.sub.LC. For the off pixel element to remain off, the sum of the induced voltages from this and all other parasitic capacitances must be less than the threshold voltage of the liquid crystal material, namely, V.sub.th. The effect of C.sub.SD on a gray-scale display is much more critical. If V.sub.LC is set at an intermediate level on one pixel (V.sub.th &lt;V.sub.LC &lt;V.sub.max) the value of V.sub.LC can vary by .delta.V.sub.LC depending upon the state of the other elements in the column.
The effect of the gate source capacitance C.sub.GS is similar except that voltage waveforms on the gate line couple through C.sub.GS to produce an additional undesirable voltage on the pixel electrode. Only the part of the gate line waveform for which the gate voltage is less than the threshold voltage couples through since, above the threshold voltage, the FET is sufficiently conducting to hold the pixel voltage at the data line voltage.
The parasitic capacitances in an LCD display can be divided into two groups: those that are dependent on the FET structure and those that are dependent upon the overall matrix structure. The parasitic capacitances which depend on the FET structure include the source to drain capacitance and the source to gate capacitance. The parasitic capacitances which are dependent upon the matrix structure include the capacitances between the pixel electrode and the gate and data lines. These latter capacitances are minimized by choosing structures with appropriate address line widths, spacings between pixel elements, cell thickness, and liquid crystal material. The FET capacitances, which are the ones of primary interest herein, are minimized by making the area of the gate, source, and drain electrodes as small as possible. This leads to FET designs with small overlap area between the gate and the electrode which contacts the indium tin oxide (ITO) pixel.
A conventional thin film FET structure with the contact on the opposite side of the silicon from the induced electron channel has many processing advantages. For LCD devices, it has the additional advantage that the data and scan line crossover insulation is obtained without extra processing. However, this structure can result in reduced drain currents and a contact voltage drop which complicates applications to gray scale displays. The nature of this contact structure also requires larger contact area which undesirably increases the parasitic capacitances associated with such FET devices.
Plots of drain currents versus drain voltage for conventional FET devices generally indicate non-ideal characteristics at low drain voltages. At these voltages, the dependence is nearly parabolic resulting in a non-exponential charging characteristic for the LCD pixel capacitor. An ideal device is generally linear in the drain voltage versus source voltage characteristic at low drain voltages. Non-ideal behavior results in the introduction of a contact drop voltage, V.sub.c. This drop is undesirable. However, the effect that the contact drop has on decreasing the drain current in the FET is less obvious. The contact drop at higher drain currents is generally larger than V.sub.c. This reduces the actual gate and drain voltages applied to the internal device structure and hence reduces the drain current compared to that which would be otherwise obtainable.
In order to minimize the source to gate capacitance, C.sub.SG, it is generally desired to minimize the overlap between the source and gate electrodes. However, this reduction results in an increase in the contact drop, V.sub.c.
Accordingly, it is an object of the present invention to provide amorphous silicon FETs which strike a critical balance between minimum parasitic capacitance and contact voltage drop.
It is also an object of the present invention to provide FET structures which are useful in liquid crystal display devices, particularly in gray scale level devices.
It is also an object of the present invention to reduce the parasitic source to gate capacitance in a thin film FET device.
It is yet another object of the present invention to reduce contact voltage drops in thin film FET devices.
Lastly, but not limited hereto, it is an object of the present invention to achieve improved performance in amorphous silicon FETs by doping the amorphous silicon layer in conjunction with control of overlap dimensions for the source and gate electrodes.