1. Field of the Invention
The present invention generally relates to a semiconductor device. More specifically, the present invention relates to a dynamic random access memory, hereinafter referred to a DRAM.
Priority is claimed on Japanese Patent Application No. 2008-278797, filed Oct. 29, 2008, the content of which is incorporated herein by reference.
2. Description of the Related Art
In semiconductor devices such as DRAMs, local input/output (I/O) lines extend in parallel to each other. The local input/output (I/O) lines are adjacent to each other with a small distance between those. In some cases, four local input/output (I/O) lines are placed side by side. A coupling noise is caused by two adjacent local input/output (I/O) lines. In some cases, a first local input/output (I/O) line may be adjacent to second and third local input/output (I/O) lines. Namely, the first local input/output (I/O) line may be disposed between the second and third local input/output (I/O) lines. In this case, the first local input/output (I/O) line may in general cause coupling noises with the second and third local input/output (I/O) lines. It has been desired to suppress or reduce the coupling noises between two adjacent local input/output (I/O) lines. A typical method of suppressing such a coupling noise has been proposed. There is disposed a shield wiring line which is adjacent to a signal line that receives a coupling noise.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2003-7860 discloses a technique of disposing signal lines, which have an electric potential that is fixed to the power supply potential or ground potential, on both sides.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2005-332903 discloses a technique of disposing wiring lines, which have a predetermined fixed electric potential during a period for which a coupling noise is received, on both sides.