1. Field of the Invention
The present invention relates to a semiconductor device comprising a transistor, and more particularly, it relates to a semiconductor device comprising a transistor capable of suppressing dispersion of the current amplification factor of the transistor.
2. Description of the Prior Art
An exemplary conventional semiconductor device comprising transistors employed for diving/controlling a motor or an air bag for a car, for example, is described. In this type of semiconductor device, a bipolar transistor and MOS transistors are formed on the same semiconductor substrate. The structure of a portion forming the bipolar transistor is now described.
Referring to FIG. 12, an nxe2x88x92 epitaxial layer 4 is formed on a p-type silicon substrate 1. An n+ diffusion layer 2a and a p+ diffusion layer 3 are formed between the p-type silicon substrate 1 and the nxe2x88x92 epitaxial layer 4. A p+ diffusion layer 5a and LOCOS oxide films 6 for electrically isolating this portion from another element region (not shown) are formed on the nxe2x88x92 epitaxial layer 4.
A p diffusion layer 6 is formed on the surface of the nxe2x88x92 epitaxial layer 4 and in the vicinity thereof. An nxe2x88x92 diffusion layer 8b and an n+ diffusion layer 9b are formed on the surface of the p diffusion layer 7 and in the vicinity thereof. A p+ diffusion layer 100 for attaining contact with the p diffusion layer 7 is formed on the p diffusion layer 7.
Further, an nxe2x88x92 diffusion layer 8a and an n+ diffusion layer 9a for attaining contact with the nxe2x88x92 epitaxial layer 4 are formed on the surface of the nxe2x88x92 epitaxial layer 4 and in the vicinity thereof.
The nxe2x88x92 epitaxial layer 4 defines a collector region in the bipolar transistor, the p diffusion layer 7 and the p+ diffusion layer 100 define a base region, and the nxe2x88x92 diffusion layer 8b and the n+ diffusion layer 9b define an emitter region.
An interlayer insulation film 11 is formed to cover the p diffusion layer 7 and the LOCOS oxide films 6. A contact hole 12a exposing the surface of the n+ diffusion layer 9a is formed in the interlayer insulation film 11. Further, a contact hole 12b is formed to expose the surface of the p+ diffusion layer 100. In addition, a contact hole 12c is formed to expose the surface of the n+ diffusion layer 9b. 
A collector electrode 13a electrically connected with the n+ diffusion layer 9a is formed in the contact hole 12a. A base electrode 13b electrically connected with the p+ diffusion layer 100 is formed in the contact hole 12b. An emitter electrode 13c electrically connected with the n+ diffusion layer 9b is formed in the contact hole 12c. 
Other semiconductor elements such as MOS transistors are formed on another element forming region (not shown) electrically isolated from this region formed with the bipolar transistor by the LOCOS oxide films 6 and the like.
A method of fabricating the semiconductor device having the aforementioned bipolar transistor is described along with a method of fabricating MOS transistors. Referring to FIG. 13, prescribed n+ diffusion layers 2a and 2b, the p+ diffusion layer 3 and the nxe2x88x92 epitaxial layer 4 are formed on the p-type silicon substrate 1. Phosphorus is injected into a prescribed region of the nxe2x88x92 epitaxial layer 4, thereby forming an nxe2x88x92 diffusion layer 14 for forming a p-channel MOS transistor.
Further, boron is injected into other prescribed regions of the nxe2x88x92 epitaxial layer 4, thereby forming a p+ diffusion layer 5b for forming an n- channel MOS transistor and a p+ diffusion layer 5a for element isolation.
Then, the LOCOS oxide films 6 are formed on prescribed regions of the nxe2x88x92 epitaxial layer 4. A gate electrode 19a formed by a polysilicon film 16a and a tungsten silicide film 17a is formed on the nxe2x88x92 diffusion layer 14 through a gate insulator film 151a. At the same time, a gate electrode 19b formed by a polysilicon film 16b and a tungsten silicide film 17b is formed on the p+ diffusion layer 5b through a gate insulator film 151b. 
Then, boron is injected into a prescribed region of the nxe2x88x92 epitaxial layer 4, thereby forming the p diffusion layer 7 partially forming the base region of the bipolar transistor.
The gate electrode 19b and a prescribed photoresist pattern (not shown) are employed as masks for injecting a prescribed impurity, thereby forming the nxe2x88x92 diffusion layers 8a and 8b and nxe2x88x92 diffusion layers 8c and 8d respectively. Side wall insulator films 18a are formed on both side surfaces of the gate electrode 19a, and side wall insulator films 18b are formed on both side surfaces of the gate electrode 19b. 
The gate electrode 19b, the side wall insulator films 18b and a prescribed photoresist pattern 200 are employed as masks for injecting a prescribed impurity, thereby forming the n+ diffusion layers 9a and 9b and n+ diffusion layers 9c and 9d respectively.
Referring to FIG. 14, the photoresist pattern 200 is removed and heat treatment is performed in a nitrogen atmosphere. Referring to FIG. 15, a photoresist pattern 202 exposing part of the surface of the p diffusion layer 7 and the surface of the nxe2x88x92 diffusion layer 14 is formed on the nxe2x88x92 epitaxial layer 4.
The photoresist pattern 202 is employed as a mask for injecting a prescribed impurity, thereby forming the p+ diffusion layer. 100 on the surface of the p diffusion layer 7 and in the vicinity thereof. P+ diffusion layers 10b and 10c are formed on the nxe2x88x92 diffusion layer 14. Thereafter the photoresist pattern 200 is removed.
Thus formed is a bipolar transistor T1 having the collector region defined by the nxe2x88x92 epitaxial layer 4, the base region defined by the p diffusion layer 7 and the p+ diffusion layer 100 and the emitter region defined by the nxe2x88x92 diffusion layer 8b and the n+ diffusion layer 9b. Further, a p-channel MOS transistor T2 is formed with source/drain regions defined by the p+ diffusion layers 10b and 10c. In addition, an n-channel MOS transistor T3 is formed with source/drain regions defined by the nxe2x88x92 diffusion layers 8c and 8d and the n+ diffusion layers 9c and 9d.
Referring to FIG. 16, the interlayer insulating film 11 formed by a silicon oxide film, for example, is formed on the nxe2x88x92 epitaxial layer 4 by CVD or the like. A prescribed photoresist pattern (not shown) is formed on the interlayer insulating film 11.
The photoresist pattern is employed as a mask for anisotropically etching the interlayer insulating film 11, thereby forming the contact holes 12a, 12b and 12c and contact holes 12d, 12e, 12f and 12g respectively. Thereafter the electrodes 13a to 13c and prescribed electrodes 13d to 13g are formed in the contact holes 12a to 12g respectively.
A principal part of the semiconductor device comprising the bipolar transistor T1 and the MOS transistors T2 and T3 is completed through the aforementioned steps.
However, the semiconductor device obtained in the aforementioned method has the following problem: When evaluating collector current dependency of a current amplification factor hFE particularly in the bipolar transistor T1 in the aforementioned semiconductor device, the current amplification factor hFE proved to remarkably disperse in the wafer plane. This problem is now described.
FIGS. 17B to 17F are graphs showing values of the current amplification factor hFE of the bipolar transistor T1 evaluated on five points of the wafer plane shown in FIG. 17A respectively. It is understood from these graphs that the values of the current amplification factor hFE for a specific collector current vary and disperse in the wafer plane.
The current amplification factor hFE is defined as the ratio (IC/IB) of the collector current to a base current. In order to investigate the cause for such dispersion of the current amplification factor hFE, base-to-emitter voltage dependency of the collector current and base-to-emitter voltage dependency of the base current were evaluated respectively.
Referring to FIG. 18 showing partial results of the evaluation, results on the points 5 and 3 exhibiting the largest changes among the five points in the wafer plane are plotted on the same graph. As shown in FIG. 18, the curves are substantially consistent with each other as to the base-to-emitter voltage dependency of the collector current, and it is conceivable that dispersion of the collector current in the wafer plane is extremely small.
Noting the curves showing the base-to-emitter voltage dependency of the base current, it is understood that the curves at the points 5 and 3 are inconsistent with each other. In other words, it is understood that the base current disperses in the wafer plane. Thus, it is conceivable that dispersion of the current amplification factor hFE results from such dispersion of the base current.
The present invention has been proposed in order to solve the aforementioned problem, and an object thereof is to provide a semiconductor device comprising a transistor, in which dispersion of a current amplification factor is reduced by suppressing dispersion of a base current.
The semiconductor device according to the present invention comprises a transistor. The transistor includes a first conductivity type collector region, a second conductivity type base region, a first conductivity type emitter region and a second conductivity type base contact region. The collector region is formed on a semiconductor substrate. The base region is formed on the surface of the collector region and in the vicinity thereof, and has a first impurity concentration. The emitter region is formed on the surface of the base region and in the vicinity thereof. The base contact region is formed on the surface of the base region and in the vicinity thereof, and has a second impurity concentration, higher than the first impurity concentration, for attaining contact with the base region. The base contact region and the emitter region are arranged at a prescribed interval while the base contact region extends toward the emitter region so that dispersion of values of a current amplification factor of the transistor is within a prescribed range.
According to this structure, the base contact region having a relatively high impurity concentration formed on the surface of the base region reduced in impurity concentration due to out diffusion of the impurity during the fabrication steps extends toward the emitter region for supplying a sufficient amount of the impurity to the base region as compared with the conventional semiconductor device. The base contact region and the emitter region are arranged at a prescribed interval for reducing dispersion of the base current, thereby reducing dispersion of the values of the current amplification factor of the transistor within the prescribed range.
As to the range of dispersion of the values of the current amplification factor, the value of average absolute deviation of the current amplification factor on five points in the wafer plane is preferably not more than 5 as a representative value.
If the value of average absolute deviation of the current amplification factor is not more than 5, it is conceivable that dispersion of the current amplification factor of the transistor is very small.
The prescribed interval between the base contact region and the emitter region is preferably at least 0.2 xcexcm and not more than 0.5 xcexcm.
If the interval is shorter than 0.2 xcexcm and not more than 0.5 xcexcm, the value of average absolute deviation of the current amplification factor disadvantageously exceeds 5. Therefore, the interval is preferably at least 0.2 xcexcm and not more than 0.5 xcexcm.
The base contact region is preferably formed to enclose the emitter region on the surface of the base region while keeping the prescribed interval between the same and the emitter region.
In this case, flows of electrons or holes in the base region and the emitter region are uniformalized for stabilizing operations of the transistor.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.