Non-volatile memory cells that are electrically programmable and erasable can be realized as charge-trapping memory cells, which comprise a memory layer sequence of dielectric materials, which is provided for charge-trapping in a memory layer that is arranged between confinement layers. The confinement layers have a larger energy band gap than the memory layer. The memory layer can be silicon nitride, while the confinement layers are usually silicon oxide. The memory layer sequence is arranged between a channel region that is located within a semiconductor body and a gate electrode that is arranged above the channel region and is provided to control the channel by means of an applied electric voltage. Charge carriers moving from source to drain through the channel region are accelerated and gain enough energy to be able to pass the lower confinement layer and to be trapped in the memory layer. The trapped charge carriers change the threshold voltage of the cell transistor structure.
A publication by B. Eitan et al., “NROM: a Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell” in IEEE Electron Device Letters, volume 21, pages 543 to 545 (2000), describes a charge-trapping memory cell with a memory layer sequence of oxide, nitride and oxide, which is especially adapted to be operated with a reading voltage that is reverse to the programming voltage (reverse read). This publication is incorporated herein by reference. The oxide-nitride-oxide layer sequence is especially designed to avoid the direct tunneling regime and to guarantee the vertical retention of the trapped charge carriers. The oxide layers are specified to have a thickness of more than 5 nm. Two bits of information can be stored in every memory cell.
The ONO (oxide-nitride-oxide) sequence is grown or deposited onto a main surface of a semiconductor substrate in such a fashion that it extends over the complete area provided for the memory cell array before other method steps are performed. These further method steps include a deposition and structuring of wordline stacks comprising the gate electrodes and an implantation of the source and drain regions. The effective channel width of the charge-trapping memory cells is crucially affected by the final top width of the shallow trench isolations, which are provided to electrically insulate columns of memory cells within the array. Other important factors are the step height of the trench fillings and the thickness of the ONO layer. There is a plurality of other process steps that also affect the performance of the memory cells. These concern the exact dimensions of the insulating trenches and the thickness of the trench filling as well as several method steps by which auxiliary or sacrificial layers are removed or structured. Inevitable variations of the process parameters result in problems of a threshold voltage distribution that is too large and in degraded retention-after-cycling values (RAC). A further miniaturization of the memory devices will probably aggravate these problems.