The present invention relates to a semiconductor integrated circuit and its method of fabrication, particularly to a technique effectively applied to a semiconductor integrated circuit having a CMIS (Complementary Metal Insulator Semiconductor) for preventing thermal runaway during testing, as well as latch-up and fluctuation of the operation speed due to fluctuation of substrate potentials
In recent years, various studies have been made of semiconductor integrated circuits in an effort to attain high integration, greater speed, and low power consumption. Particularly, in the case of a semiconductor integrated circuit having a MOS FET (Metal Oxide Semiconductor Field Effect Transistor) device, it has been necessary to further refine the sizes of devices and wirings in order to improve the degree of device integration and the operation speed and, therefore, the reduction in size of such semiconductor integrated circuits has progressed rapidly.
The present inventor has studied the scaling of a semiconductor integrated circuit. That is, scaling of a semiconductor integrated circuit, such as an LST (Large Scale Integrated circuit) includes two types of scalingxe2x80x94constant-voltage scaling and constant-electric-field scaling. In the case of a CMOS semiconductor integrated circuit including a CMOS FET as a component, constant-electric-field scaling is mainly employed for the purpose of securing the reliability of a gate oxide film. In this case, it is also necessary to lower the power supply voltage proportionally to effect reduction of the device size from the viewpoint of securing the stability of the device operating characteristic.
The literature on the fabrication of a CMOS semiconductor integrated circuit includes, for example, W. MALY xe2x80x9cZUSETSU CHO ERUESUAl KOCAKU (transliterated)xe2x80x9d, pp. 167-191, issued by KEIGAKU SHUPPAN (transliterated) Co., Ltd. on Dec. 15, 1990. An original text of the above-transliterated publication is xe2x80x9cAtlas of IC Technologies: An Introduction to VLSI Processesxe2x80x9d by W. Maly (Copyright(copyright) 1987 by The Benjamin/Cummings Publishing Company Inc.).
In the case of the above-disclosed CMOS semiconductor integrated circuit, to make a scaling rule practically effective, it is necessary to lower the threshold voltage in proportion to the device size. This is because a voltage component contributing to the circuit operation can be represented by the expression xe2x80x9cpower supply voltagexe2x88x92threshold voltagexe2x80x9d. However, because lowering of the threshold voltage causes an increase in leakage current, a leakage current test (I ddq test) widely used for testing a semiconductor integrated circuit cannot be performed, and, moreover, in the case of an aging test, the temperature is excessively raised due to an increase in the leakage current and, thereby, a problem of thermal runaway occurs.
FIG. 29 illustrates the mechanism of thermal runaway in the case of an aging test. In FIG. 29, the x-axis shows the set junction temperature (junction temperature Tj1) of a semiconductor integrated circuit and the y-axis shows the temperature (junction temperature Tj2) obtained by adding a temperature rise due to the total leakage current of a semiconductor integrated circuit produced due to the junction temperature Tj1 increasing relative to the ambient temperature. Normally, the junction temperature Tj2 and the junction temperature Tj1 are stabilized at an equal temperature. However, when a leakage current component increases, the temperature is excessively raised due to the leakage current and, resultingly, thermal runaway occurs.
By applying a back bias to the well of a MOS FET in order to solve the above problem, it is possible to control the threshold voltage. In the case of this technique, however, the well potential may fluctuate due to noise under practical use (under normal operation) and a problem may occur in which a forward current is applied between the well and the source/drain to produce a so-called latch-up phenomenon.
One way of decreasing the leakage current by using a back bias is described in, for example, the official gazette of Japanese Patent Laid-Open No. 6-334010/1994, which discloses a structure in which the substrate node of a low-threshold-voltage field effect transistor, constituting a group of logic circuits, is connected to a power supply line, and a dummy power supply line, connected to the group of logic circuits, is connected to a power supply line through a high-threshold-voltage field effect transistor. In the case of this arrangement, the field effect transistor, whose substrate node is connected to the power supply line, can perform a normal operation at a low threshold voltage by turning on the high-threshold-voltage transistor under normal operation of the semiconductor integrated circuit, while the low-threshold-voltage field effect transistor can temporarily have a high threshold voltage by turning off the high-threshold-voltage field effect transistor and applying a test voltage to the dummy power supply line. However, this circuit has a problem in that the circuit impedance increases and, thereby, the general operation speed of the semiconductor integrated circuit lowers because the high-threshold-voltage field effect transistor is connected in series between the group of logic circuits and the power supply.
Moreover, the official gazette of Japanese Patent Laid-Open No 8-17183/1996 discloses a way of using switching means for making the substrate potential of a MOS FET variable as a means for controlling the threshold voltage of the MOS FET. This arrangement makes it possible to switch the switching characteristic and the sub-threshold current characteristic because the switching means switches the back gate bias of the MOS FET to a first potential or second potential and the absolute values of the threshold voltage of the MOS FET. In the case of this proposal, however, the source and n-well of a p-channel MOS FET are short-circuited each to the other through an n-channel MOS FET. Therefore, problems occur in that (1) it is necessary to generate a voltage higher than the power supply voltage under normal operation, and (2) the device characteristics are deteriorated because the high voltage in the above Item (1) is applied to the MOS FET and, thereby, the thickness of the gate oxide film of the MOS FET must be increased
It is an object of the present invention to provide a high-performance CMOS semiconductor integrated circuit which is capable of preventing the latch-up phenomenon, and its fabrication method.
Moreover, it is another object of the present invention to provide a way of preventing the latch-up phenomenon of a CMOS semiconductor integrated circuit from occurring under normal operation of the semiconductor integrated circuit and of preventing a leakage current from being generated during a test of the circuit.
Furthermore, it is still another object of the present invention to provide a way of improving the reliability of a CMOS semiconductor integrated circuit under normal operation and under test, without lowering the operation speed of the semiconductor integrated circuit under normal operation of the circuit. Furthermore, it is still another object of the present invention to provide a way of improving the reliability of a CMOS semiconductor integrated circuit under the normal operation and test of the circuit without deteriorating the device characteristics.
The above and other objects and novel features of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings.
That is, a semiconductor integrated circuit of the present invention has a first power-supply-voltage line connected to a CMOS FET and a second power-supply-voltage line to which a voltage lower than that of the first power-supply-voltage line is applied, and moreover has a third power-supply-voltage line and a fourth power-supply-voltage line, independent of the first and the second power-supply-voltage lines, which makes it possible to supply power to a first-conductivity-type well through the third power-supply-voltage line according to necessity and a second-conductivity-type well through the fourth power-supply-voltage line according to necessity.
Moreover, in the case of a semiconductor integrated circuit of the present invention, a first switching transistor comprising a MOS FET is connected between a first power-supply-voltage line and a third power-supply-voltage line, and a second switching transistor comprising a MOS FET is connected between a second power-supply-voltage line and a fourth power-supply-voltage line, which makes it possible to short-circuit the first power-supply-voltage line and the third power-supply-voltage line by operating the first switching transistor according to necessity, and to short-circuit the second power-supply-voltage line and the fourth power-supply-voltage line by operating the second switching transistor according to necessity.
Thereby, under the normal operation of a semiconductor integrated circuit, for example, it is possible to control the fluctuation of substrate potentials of the first- and second-conductivity-type MOS FETs by turning on first- and second-switching transistors and supplying the first and second power-supply voltages to the first- and second-conductivity-type wells. Therefore, it is possible to prevent the latch-up phenomenon due to fluctuation of substrate potentials.
Moreover, during the test of a semiconductor integrated circuit, for example, it is possible to decrease the leakage current by turning off the first and second switching transistors and applying a voltage suitable for the test to the first- and second-conductivity type wells from the third and fourth power-supply-voltage lines. Therefore, it is possible to control thermal runaway due to a leakage current.
Furthermore, a semiconductor integrated circuit fabrication method of the present invention comprises the steps of:
forming first- and second-conductivity-type wells on the surface of a semiconductor substrate;
forming a second-conductivity-type MOS FET for constituting a CMOS FET and a first switching transistor having a MOS FET different from the second-conductivity-type MOS FET in the first-conductivity-type well;
forming a first-conductivity-type MOS FET for constituting a CMOS FET and a second switching transistor having a MOS FET different from the first-conductivity-type MOS FET;
forming a first power-supply-voltage line so as to be connected with the source of the second-conductivity-type MOS FET for constituting the CMOS FET;
forming a second power-supply-voltage line so as to be connected with the source of the first-conductivity-type MOS FET for constituting the CMOS FET;
forming a well feeding line so as to be connected with the source of the first switching transistor and the first-conductivity-type well;
forming a well feeding line so as to be connected with the source of the second switching transistor and the second-conductivity-type well;
forming a control signal line so as to be connected with the gate electrode of thexe2x80x94first switching transistor; and
forming a control signal line so as to be connected with the gate electrode of the second switching transistor; wherein
the first switching transistor is set adjacent to the source of the second-conductivity-type MOS FET in the same semiconductor region and the second switching transistor is set adjacent to the source of the first-conductivity-type MOS FET in the same semiconductor region.
Thereby, it is possible to decrease the areas occupied by the first and the second switching transistors and thus, it is possible to improve the efficiency of layout.
Furthermore, a semiconductor integrated circuit fabrication method of the present invention comprises the steps of:
forming a first-conductivity-type well and a second-conductivity-type well on the surface of a semiconductor substrate;
forming a second-conductivity-type MOS FET for constituting a CMOS FET in the first-conductivity-type well and a first switching transistor having a MOS FET different from the second-conductivity-type MOS PET;
forming a first-conductivity-type MOS FET for constituting a CMOS FET in the second-conductivity-type well and a second switching transistor having a MOS FET different from the first-conductivity-type MOS FET;
forming a first power-supply-voltage line so as to be connected with the source of the second-conductivity-type MOS FET for constituting the CMOS FET;
forming a second power-supply-voltage line so as to be connected with the source of the first-conductivity-type MOS FET for constituting the CMOS FET;
forming a well feeding line so as to be connected with the source of the first switching transistor and the first-conductivity-type well;
forming a well feeding line so as to be connected with the source of the second switching transistor and the second-conductivity-type well;
forming a control signal line so as to be connected with the gate electrode of the first switching transistor; and
forming a control signal line so as to be connected with the qate electrode of the second switching transistor; wherein
the step of forming the well feeding line so as to be connected with the source of the first switching transistor and the first-conductivity-type well and the step of forming the well feeding line so-as to be connected with the source of the second switching transistor and the second-conductivity-type well are performed in the same step, and
the step of forming the control signal line so as to be connected with the gate electrode of the first switching transistor and the step of forming the control signal line so as to be connected with the gate electrode of the second switching transistor are performed in the same step.
Thereby, by forming a first switching transistor, its well feeding line and its control signal line, and a second switching transistor, its well feeding line and its control signal line, in the same step, it is possible to fabricate a semiconductor integrated circuit having a first switching transistor, a second switching transistor, well feeding lines, and control signal lines.
Moreover, a semiconductor integrated circuit of the present invention is fabricated by providing a set of the first and second switching transistors for a plurality of logic gates, respectively. Thereby, it is possible to decrease the entire switching-transistor occupied area compared to the case of providing a first switching transistor and a second switching transistor for each logic gate. Therefore, it is possible to prevent the chip size from increasing due to addition of switching transistors and to prevent the device integration degree from decreasing.
Furthermore, a semiconductor integrated circuit of the present invention is fabricated by constituting the third power-supply-voltage line and the fourth power-supply-voltage line with a conductor wiring, providing a connecting portion for connecting a conductor wiring for the third power-supply-voltage line with the first-conductivity-type well, and providing a connecting portion for connecting a conductor wiring for the fourth power-supply-voltage line with the second-conductivity-type well for each cell region to which each of the logic gates is set. Thereby, because a well feeding voltage can be supplied from the vicinity of each logic gate, it is possible to stably supply a potential to each logic gate.
Moreover, a semiconductor integrated circuit of the present invention is fabricated by providing a switching control section for dividing a control signal in a control signal line into two control signals having a potential different from each other and transmitting each divided control signal to each of the first and the second switching transistors for the front stages of inputs of the first and the second switching transistors. Thereby, it is possible to turn on/off the switching transistors using one control signal line.
Furthermore, a semiconductor integrated circuit of the present invention is fabricated by providing the first switching transistor and the second switching transistor in an available space in which power-supply-voltage lines are arranged. In this way, it is possible to effectively use available space in the principal plane of a semiconductor chip and prevent the area of the chip from increasing, compared to the case of providing switching transistors in an area other than the wiring arranging area.
In this specification any reference to a MOS FET or MOS FETs shall be considered to be inclusive of IGETs (Insulated-Cate Field-Effect Transistors) or MISFETs (Metal-Insulated-Semiconductor Field Effect Transistors), in general.