1. Field of the Invention
The present invention relates to a self-timing control circuit for generating a control clock synchronized in a prescribed phase relationship to a master clock; and to a self-timing control circuit with a simple circuit structure which can lock on in a short time and which can carry out highly precise timing control for a high speed clock.
2. Description of the Related Art
Synchronous DRAM is one of the latest high speed memory devices. Such a high speed device is supplied command signals, address signals, data signals, and the like in synchronized with a clock by a controller; outputs a data signal in synchronized with the clock. As noted above, high speed operations are realized through the use of the clock as a strobe signal.
In such a device, an external clock is input once into the device and a control signal, being a strobe signal, is generated; in such a case, the phase of the control signal becomes unmatched with the supplied clock due to the delay characteristics of the internal circuitry. For this reason, a self-timing control circuit, to generate a control clock, synchronized in a prescribed phase relationship to a master clock, is established within the device.
Conventional self-timing control circuits utilize a delay locked loop circuitry (DLL circuitsry below) for generating a control clock delayed by one or more cycles of the supplied clock.
FIG. 1 shows the DLL circuitry constituting a conventional self-timing control circuit. In FIG. 1, the external clock signal CLK is supplied by means of an input buffer 1 to a variable delay circuit 2 and a variable delay circuit 4, and is supplied as a first input for a phase comparison circuit 7 at the same time. A delay clock signal d-i-clk is generated from the clock signal c-clk, which is input to the variable delay circuit 4, passes through a dummy data output buffer 5 and a dummy input buffer 6. This delay clock signal d-i-clk is supplied as a second input to the phase comparison circuit 7. The phase comparison circuit 7 compares the phases of the two input signals c-clk and d-i-clk and outputs the results of the comparison to the delay control circuit 8. The delay control circuit 8 controls the amount of the delay of the variable delay circuit 2 and variable delay circuit 4 according to the phase comparison results. The amount of the delay, controlled by the delay control circuit 8, is applied to the clock signal c-clk input to the variable delay circuit 2, the clock signal c-clk is supplied to the data output buffer 3 as a control clock n0. The data output buffer 3 is synchronized with the control clock signal n0 supplied thereto, takes up data DATA, and outputs this data externally as the data output data Dout.
Moreover, the dummy data output buffer 5 is unnecessary when the control clock n0 is used as a strobe signal for the input buffer.
Such DLL circuits are noted in detail in Japanese Patent Application No. 8-339988 (Dec. 19, 1996 application, Japanese Patent Laid-open Publication No. 10-112182, laid open Apr. 28, 1998), for which the present applicants have already applied.
In the aforementioned DLL circuits, however, the variable delay circuits 2, 4 comprise a plurality of serially connected unit delay circuits. Consequently, highly precise control of the timing of the control clock generated requires that the amount of the delay of the unit delay circuits be small and the number of those circuits be large. As a result, the variable delay circuits become large in scale and occupy increased area on the chip, whereby the variable delay circuits become an obstacle to higher integration of integrated circuit devices.
Furthermore, highly precise timing control is necessary in order to have operating speeds in excess of 100 MHz, for example. Even with large scale variable delay circuits, the device cannot handle timing control with finer precision than the amount of delay of the unit delay circuits, as long as digitally control the timing wherein the amount of delay of the unit delay circuits is a variable unit.
Also, a problem is that locking on requires a long period of time when power is turned on or when the device is returning from a powered down state, because the conventional DLL circuits are reset once and then perform a feedback operation for phase matching.