A teletext decoder of the type defined in the opening paragraph is described in Steve A. Money, Teletext and Viewdata, Butterworth & Co Ltd, 1979, pages 35-45. In teletext transmission it is customary to protect a portion of the teletext information from transmission errors by adding a (n-k)-bit Hamming code to k data bits by means of Hamming coding. This provides n-bit code sequences in which the occurrence of one bit error can be corrected and the occurrence of two bit errors can be detected. To that end the error detection and correction circuit of the known teletext decoder is preceded by a series-parallel converter in order to enable the simultaneous processing of the n-bits of a received code sequence. In the prior art circuit predetermined bits of the code sequence are simultaneously applied to as many (n-k)parallel modulo-2 adders as there are protection bits in a code sequence. For that purpose the predetermined bits are branched off by means of a wiring network from the corresponding output of the series-parallel converter. The outputs of the modulo-2 adders form a (n-k)-bit syndrome word which indicates the presence and position of a bit error in an encoded form. The syndrome word is decoded by a network which in response thereto generates a parallel k-bit correction signal whose individual bits are applied in parallel to k exclusive-OR gates. These exclusive-OR gates, denoted controlled inverters in the sequence of this description, each receive a data bit from the series-parallel converter and thereafter apply possibly inverted data bits to the page acquisition and page memory circuit of the teletext decoder.
With the prior art teletext decoder the corrected data bits are processed in parallel. This processing operation includes inter alia the storage of teletext information in a memory which for that purpose is in the form of a 8-bit wide static memory. However, in contempory teletext decoders, for reasons of cost price, the use of 1-bit wide dynamic memories is preferred. Moreover it is useful to incorporate a teletext decoder in two integrated circuits (IC's), an acquisition IC and a display IC with integrated memory, the latter IC optionally being separately suitable for the display of so-called On-Screen-Display images. With such a split-up of the teletext decoder a lowest possible amount of parallel connection wires between the two IC's is the aim. Consequently, it is advisable to convey the data signal serially again after error correction. It is then inconvenient to use, only for the purpose of error detection and correction, series-parallel conversion and to serialize thereafter the corrected data. Furthermore the error detection and correction circuit in the prior art teletext decoder is fully structured as a combinatorial network, which has the disadvantage that on integration in an IC a relatively large portion of the chip surface is occupied by the large number of parallel connection conductors which require much space. The previously mentioned wiring network in particularly was found to occupy much space.