This application claims the priority benefit of Taiwan patent application number 104141341, filed on Dec. 9, 2015.
1. Field of the Invention
The present invention relates to charge pump technology, and more particularly, to a charge pump based on a clock generator integrated chip for use in a touch panel, which has a transistor set of a chip thereof electrically coupled to a first input end and at least three second input ends that are arranged in two rows subject to odd number and even number, and then coupled to a package substrate and a circuit board in a similar arrangement and also electrically coupled to a clock generator, enabling the traces in the chip to be arranged in a staggered manner with the first circuit and second circuit of the circuit board spaced apart without intersection, minimizing generation of parasitic capacitance.
2. Description of the Related Art
A touch panel can be joined with a display screen to create a touchscreen for use in a notebook computer, tablet computer, smart phone or any other electronic device as an input interface for sensing any touch input in the display zone. The sensing circuit of a touch panel has a charge pump circuit incorporated therein and configured to amplify input voltage for generating a high level output voltage to enhance the anti-noise capability of the touch panel.
FIG. 4 is a circuit diagram of a charge pump according to the prior art. This design of charge pump comprises a chip X, a package substrate Y and a circuit board Z. The chip X is mounted on the package substrate Y. The package substrate Y is mounted on the circuit board Z. The chip X comprises a transistor set X1, and a clock generator X2 disposed at one lateral side relative to the transistor set X1. The transistor set X1 consists of seven transistors. Further, the chip X has nine connection ends X3 respectively disposed to face toward the clock generator X2 and the transistors of the transistor set X1. Two of the nine connection ends X3 are respectively electrically coupled to the clock generator X2. The other connection ends X3 are respectively electrically coupled to the transistors of the transistor set X1. The package substrate Y comprises a plurality of pins Y1 respectively electrically coupled to the pins at the connection ends X3. The circuit board Z comprises a first circuit Z1, a second circuit Z2, six capacitors Z3, and a logic high/low power supply Vdd. The logic high/low power supply Vdd is electrically coupled to the connection end X3 that is electrically coupled to the first transistor of the transistor set X1. The first circuit Z1 and the second circuit Z2 have the respective one ends thereof respectively electrically coupled to the two connection ends X3 that are electrically coupled to the clock generator X2, and the respective opposite ends thereof shunted and electrically coupled to the capacitors Z3 and then the connection ends X3 of the other transistors of the transistor set X1 excluding the first transistor. Because the clock generator X2 provides a pulse signal CK and a negative pulse signal CKB through the two connection ends X3 and because the transistors that receive the pulse signal and the negative pulse signal must arranged in rows and spaced from one another, points of intersection Z4 are created after shunting of the first circuit Z1 and the second circuit Z2.
Due to creation of the points of intersection Z4 after shunting of the first circuit Z1 and the second circuit Z2, the circuit board Z needs to provide an extra layer for the arrangement of traces, increasing the number of layers and complexity of the structure of the circuit board Z and resulting in increased circuit board cost. Further, the arrangement of long and large area traces in the circuit board brings relatively larger parasitic capacitance, lowering the charge pump operating efficiency and resulting in negative pulse signal interference.
Therefore, it is desirable to provide a charge pump that eliminates the drawbacks of the aforesaid prior art design.