A. Field of the Invention
This invention relates to the testing of integrated circuits and, more particularly, to methods and apparatus to test for electric current flowing through CMOS integrated circuits.
B. Description of the Prior Art
1. CMOS Circuit Testing
"Stuck-at" fault testing is a traditional technique used to check for defects in CMOS circuits. This technique generally identifies functional input-output related errors and involves setting a series of input test vectors which should result in a known sequence of output vectors from the device under test (DUT). If a particular output of the circuit is improperly "stuck" at a "0" or "1," inconsistent with circuit inputs, a defective circuit can be identified. The stuck-at fault technique originally became popular when bipolar technology testing techniques were established. Testers have continued to use the stuck-at fault model to verify CMOS circuits.
2. I.sub.DDQ
CMOS integrated circuits are popular for their low power consumption characteristics. If the design is static, the current should be nearly zero in an ideal CMOS circuit during standby or a quiescent state. Thus, when a CMOS circuit is not switching states, only a small amount of current should drawn by the circuit. This quiescent current, commonly referred to as I.sub.DDQ, is composed primarily of leakage current. I.sub.DDQ is the IEEE symbol for the quiescent power supply current in MOS circuits. A faulty CMOS circuit may draw a significantly larger amount of current than a properly functioning CMOS circuit when in the quiescent state.
An abnormally high I.sub.DDQ may result from a variety of problems which include defects such as gate-oxide shorts, inter-connect bridging shorts, and inter-connect open circuits. By measuring the I.sub.DDQ of a CMOS circuit and comparing it with the I.sub.DDQ of a known properly functioning CMOS circuit, a faulty circuit can be detected. FIG. 1 illustrates how a defect, such as a gate-oxide short, can increase the I.sub.DDQ of a simple CMOS inverter circuit 101. In FIG. 1, a generalized CMOS integrated circuit has a gate-oxide defect 103 in a p-channel transistor 105. When the input, V.sub.IN 107 to the inverter circuit 101 changes from "1" to "0," I.sub.DDQ 109 changes from a low value to a high value. Normally, as shown in FIG. 1, I.sub.DDQ 108 would drop back to the initial low level once the inverter circuit 101 stabilized. With the gate-oxide defect 103, however, I.sub.DDQ 109 Current remains abnormally high.
An interesting point to note is that these types of faults, which result in an abnormally high I.sub.DDQ, do not necessarily result in a functional circuit failure. Instead, defects often materialize as infant mortality or reliability problems in CMOS circuits. One explanation for the lack of functional failures is that gate-oxide shorts are often high resistance defects which cause only small leakage currents. In addition, CMOS circuits usually have a large noise margin. As a result, small amounts of leakage current may not effect the ultimate output value of the circuit. Since these types of faults to do not always result in functional failures, these defects will not always be identified with traditional stuck-at fault testing.
To detect chips with high resistance caused leakage problems, burn-in is often used as an acceleration technique. Burn-in is a method used to accelerate failures in a device if there is a weak feature or defect that is sensitive to extended operation of the device. Defects such as weak oxides, narrow silicon or metal lines, small resistive contacts, or other similar defects usually become more apparent with burn-in and are therefore more readily identified and may, therefore, fail "stuck at" testing. A tradeoff with burn-in, however, is the substantial time and cost that may be involved depending on the type of device being burned-in.
I.sub.DDQ test measurements are used on CMOS circuits as a supplemental technique to identify these defects. To conduct I.sub.DDQ current measurements, testers use a variety of techniques. First, off-chip equipment is connected to the CMOS circuits to measure electric current. These methods may include interfacing automated testing equipment (ATE) precision measuring units to the device under test. A problem using these techniques, however, is that test times are slow. Long pauses are often necessary for currents to settle and for the measurement systems to recover from the high switching currents. Depending on some of the capacitance values involved, up to 40 milliseconds may be required to make a single I.sub.DDQ measurement. Since thousands of tests may be needed to screen modern VLSI chips effectively, these current measurements may add many seconds to overall test time.
Another off-chip test method used to measure I.sub.DDQ involves connecting an external series resistor to the CMOS circuit to monitor the I.sub.DDQ. By measuring the voltage drop across the resistor between circuit state transitions, I.sub.DDQ can be determined. Using this test method, tests may be conducted at rates in the 10's of KHz.
Other off-chip I.sub.DDQ measurement techniques include the Keating-Meyer Method proposed by Keating and Meyer in 1987, and the QuiC-Mon method, proposed by Wallquist, Righter, and Hawkins in 1993. For detailed descriptions of these prior art I.sub.DDQ measurement methods, see Kenneth M. Wallquist et al., "A General Purpose I.sub.DDQ Measurement Circuit," Proceedings From the International Test Conference 1993, Baltimore, Md. (1993). Using these techniques, I.sub.DDQ measurement rates in the range of 100's of KHz may be achieved.
On-chip I.sub.DDQ measurement techniques have also been designed which require providing I.sub.DDQ measurement circuitry on the substrate containing the CMOS integrated circuit. By using on-chip techniques, I.sub.DDQ tests can be performed without external ATE. Unlike the present invention, all of these on-chip techniques generally involve inserting a series resistance in the power supply line and measuring the voltage drop across the on-chip series resistance to determine I.sub.DDQ. I.sub.DDQ test circuitry is also included on-chip to output a normal logic value when normal I.sub.DDQ is measured in the CMOS circuit and a fault condition logic value if I.sub.DDQ is abnormally high. For a detailed discussion of prior art on-chip I.sub.DDQ measurement techniques, see Miura et al., "Circuit Design for Built-In Current Testing," Proceedings from the International Test Conference 1992, IEEE, P.O. Box 1331, Piscataway, NJ 08855, p.873 (1992).
Problems with these on-chip methods result from the series resistance. For a typical integrated circuit, the dynamic range of current, from the high level of switching, to the low level of quiescence, is several orders of magnitude. Circuits designed to give a good sense of level at the low level of current, have a prohibitively high voltage drop during the cycle when the device is switching. This is due to the invasive nature of the series resistor. Thus, considering the added voltage of the resistive connections, on-chip series resistance techniques may be fine for a device having low currents when switching, but are unacceptable for devices having a large number (e.g. millions) of transistors.
Advances in very large scale integrated circuit technology have created additional problems with prior art I.sub.DDQ measurement techniques. Normal leakage for many millions of good transistors may reduce the measurement range between a good and bad chip to a point where traditional measurement techniques are not reliable.
Because of the above-described problems with prior art I.sub.DDQ measurement techniques, an improved technique is needed to measure I.sub.DDQ.