The problem of latch-up is a concern in the operation of integrated circuit devices that use CMOS technology. A description of latch-up in CMOS circuitry is given in Eaton, Jr. U.S. Pat. No. 4,571,505 entitled METHOD AND APPARATUS OF REDUCING LATCH-UP SUSCEPTIBILITY IN CMOS INTEGRATED CIRCUITS, issued Feb. 18, 1986 to INMOS Corporation of Colorado Springs, Colo., which patent is incorporated herein by reference and to which attention is invited for reference. Generally, latch-up results from (usually parasitic) devices such as PNP and NPN transistors that are formed unintentionally and which respond to such events as rapid changes in power supply voltage, light, radiation, input and output over-voltage, and on-chip capacitive disturbances.
In driving an output node or pin of an integrated circuit to a full power supply level (such as may be referred to as "VCC"), the prior art has heretofore used a P-channel transistor with its gate electrode driven from VCC to zero volts, or an N-channel transistor with its gate electrode driven from zero volts to some voltage above VCC. A bootstrapped driver can be used to achieve such elevated voltage. If the P-channel transistor is used, then latch-up may occur if the output is forced above VCC. If an N-channel transistor is used, then a speed loss and/or reliability problem can occur due to the need to drive the gate electrode to a voltage above VCC. Also, even with the gate electrode of the N-channel transistor at zero volts, if the output is forced to a negative voltage (such as -1.0 volt), the transistor will turn on, causing substrate current and possible reliability problems.
The aforesaid Eaton U.S. Pat. No. 4,571,505 provided a method and apparatus which involved a circuit for sensing a power supply transition, clamping the substrate to ground in response to sensing the transition, and thereafter releasing the clamp.