This invention relates generally to the field of data communications, and more specifically to a system and method for communicating data using modified header bits to identify a port.
Telecommunication systems are ubiquitous in our society. The development of new technologies and investment in new infrastructure has increased the connectivity and availability of data service to consumers. One common data communication protocol called asynchronous transfer mode (ATM) communicates data in relatively small portions known as cells. In a particular embodiment, these cells may then be included in a synchronous transport signal (STS) associated with a variety of networks having a linear or ring topology, such as a synchronous optical network (SONET).
These networks may include a multiplexer or other communication device that supports a variety of interface cards for receiving data signals from the network and forwarding these data signals to other components in the network. The multiplexer also includes a switch fabric that receives these data signals from the interface cards, determines their destination, and forwards the data signals to the interface cards for communication to other components in the network. The ports of the switch fabric may operate at a higher rate than the ports of the interface cards.
In accordance with the present invention, a system and method for communicating data is provided that substantially eliminates or reduces disadvantages or problems associated with previously developed systems and methods. In particular, the present invention contemplates a communication device having at least one input card that modifies header bits of a received data signal to identify a corresponding input port. This identification of the input port for the data signal allows for a more efficient and effective operation of the underlying switch fabric of the communication device.
In one embodiment of the present invention, a communication device includes a first card that receives a data signal at an input port and modifies header bits of the data signal to identify the input port. A switch fabric coupled to the first card receives the data signal and modifies the header bits to identify an output port of a second card. The second card couples to the switch fabric and transmits the data signal on the output port.
In another embodiment of the present invention, a communication device includes a first card that receives a data signal at an input port and modifies header bits of the data signal to identify the input port. A timeslot interchange couples to the first card and maps the data signal to a higher speed signal having other data signals from other input ports to produce an aggregate signal. A switch fabric couples to the timeslot interchange and receives the data signal in a timeslot associated with the first card. This switch fabric modifies the header bits to identify an output port of a second card, and the second card transmits the data signal on the output port.
In still another embodiment of the present invention, an interface card of a communication device includes a first port that receives a data signal having header bits. A processor couples to the first port and modifies the header bits to identify the first port. A second port transmits the data signal with the modified header bits.
Technical advantages of the present invention include a system and method that modify the header bits of a data signal to perform effective and efficient switching of the signal. In a particular embodiment, the present invention is applied to a communication device in a data network, such as an add/drop multiplexer, that includes interface cards and a switch fabric. The interface cards modify and recognize header bits to identify input and/or output ports for the data signals. In addition, the switch fabric may modify the same or other header bits to identify interface cards that receive and/or transmit the data signals. Due to the port and/or card identification function, the position of each interface card is slot independent relative to the position of the switch port. This allows maximum flexibility for slot positioning for interface cards within one or more shelves of the communication device. Also, the identification of ports using modified header bits maximizes utilization of higher speed switch ports by allowing for aggregation of lower speed signals received from the interface cards into higher speed signals for presentation to the switch fabric.
Further advantages of the present invention include adapting these inventive techniques to communicate asynchronous transfer mode (ATM) cells by modifying the general flow control field (GFC), the virtual path identifier (VPI), the virtual channel identifier (VCI), or any other header bits or fields of the ATM cell. Within an add/drop multiplexer or other communication device, the interface cards may support, for example, STS-1 or STS-3c signals carrying ATM cells whereas the ATM switch fabric may support STS-12, STS-48, or higher speed signals. In such a case, modification of header bits allows the device to aggregate lower speed signals received at the interface cards into a higher speed aggregate signal for presentation to the ATM switch fabric. This aggregation of signals from multiple ports, multiple interface cards, or both provides for a more efficient and effective operation of the ATM switch fabric. Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.