1. Technical Field
This disclosure relates to a semiconductor memory test device and a test method using the same, and more particularly to semiconductor memory test devices that are capable of performing a high-speed memory test using various test data, and test methods using the same.
2. Description of the Related Art
Generally, a memory device is used to temporarily or permanently storing data and/or commands for computers, communication systems, image processing systems and so on. Examples of the memory device include semiconductor memory devices, tapes, magnetic disks and optical disks. Currently, the semiconductor memory device is the predominant memory device.
According to a data storage method, the semiconductor memory device is categorized into a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, and a read only memory (ROM). The storage capacities and operating speeds of these semiconductor memory devices are rapidly increasing.
Typically, in order to produce the semiconductor memory device, a circuit design process, a manufacturing process, and a test process are sequentially performed. The test process determines an increase or decrease in product reliability. In order to perform the test process on the semiconductor memory device, a predetermined test pattern is written to a cell of the semiconductor memory device, and then, the cell where the predetermined test pattern is written is read. By comparing the written test pattern with the read test pattern, the cell of the semiconductor memory device may be categorized as a defective cell or a non-defective cell.
An external test device inputs an external clock signal to the semiconductor memory device, receives the read test pattern from the semiconductor memory device, and determines whether the corresponding cell of the semiconductor memory device is defective or non-defective.
In order for the external test device to exactly determine whether data errors are being received from the semiconductor memory device, a clock frequency of the semiconductor memory device should be identical to a clock frequency of the external test device. The clock frequencies of semiconductor memory devices are typically much larger (faster) than the clock frequencies of the external test devices.
In particular, since there is a rapidly increasing trend for high-speed memory products that exceed 500 MHz in clock frequency, and because manufacturing costs for the external test device are high, it is difficult to efficiently maintain the affordability of external test devices that have a clock frequency that can match that of the high-speed semiconductor memory devices.
For example, if the maximum clock frequency of the external test device is about 250 MHz and the maximum clock frequency of the semiconductor memory device is about 500 MHz, it is a common practice to downwardly adjust the clock frequency of the semiconductor memory device to match the clock frequency of the external test device during the test process.
In order to efficiently raise the clock frequency of the external test device without having to replace the external test device, a clock doubling test mode has been proposed. The clock doubling test mode enables the semiconductor memory device to be internally tested with a high frequency clock by multiplying the external clock provided from the external test device using an exclusive-OR operation or a phase-locked loop (PLL) circuit.
FIG. 1 is a timing diagram illustrating a conventional process of frequency multiplication during a clock doubling test mode. Referring to FIG. 1, an external clock signal CLK and an inverted clock signal CLKB are provided as inputs of the exclusive-OR operation during the clock doubling test mode. The inverted clock signal CLKB has a phase difference of about 90 degrees with respect to the external clock signal CLK.
An internal clock signal INTERNAL CLOCK is generated by performing the exclusive-OR operation, and an operating frequency of the internal clock signal INTERNAL CLOCK is two times greater than that of the external clock signal CLK. Alternatively, the PLL circuit may be used so that the operating frequency of the external clock signal CLK is multiplied.
Although the clock doubling test mode may raise the operating frequency by multiplying the external clock signal CLK, the clock doubling test mode may not raise a bit-rate on a data input.
FIG. 2 is a timing diagram illustrating a conventional process of test data generation during a clock doubling test mode.
Referring to FIG. 2, the frequency of an internal clock signal INT CLOCK is two times greater than that of an external clock signal CLK. However, test pattern data D0 and D1 exist during both a rising edge and a falling edge of a data strobe (DS) signal, which is synchronized to the external clock signal CLK. Thus, in view of the internal clock signal INT CLOCK, it may regarded that the test pattern data D0 and D1 exist only during a rising edge of the internal clock signal INT CLOCK.
The inputted test pattern data are generated as test data D0, D0, D1 and D1. That is, the first and second test data are identical to each other, and the third and fourth test data are identical to each other.
In the conventional method, although the clock frequency of the internal clock signal may be increased, it is not possible to generate various test data used for performing the test of the semiconductor memory device. As a result, it is difficult to effectively utilize the advantage of a high-rate operating frequency of the internal clock signal.
Embodiments of the invention address these and other disadvantages.