1. Field of the Invention
The present invention relates to masking members for forming fine electrodes and manufacturing methods therefor, methods for forming electrodes, and field effect transistors, and more particularly, relates to a technique capable of forming finer electrodes usable, for example, as gate electrodes of field effect transistors.
The present invention is advantageously applied to the fields of field effect transistors having hetero structures, which are operated in microwave or milliwave bands, and integrated circuit devices formed by integration thereof with other components.
2. Description of the Related Art
In recent years, concomitant with the advancement of information technology (IT), higher capacity and higher speed communication systems have been increasingly requested, and improvements in transmission speed of communications have been further desired. In addition, in radio communications, radar and fixed communication systems used in milliwave bands have been increasingly demanded.
Under these industrial circumstances, for example, a compound semiconductor field effect transistor (FET) having a higher operation speed has been desired in recent years. In general, in order to improve the operation speed of an FET, in addition to increasing the electron speed in an active layer material, it can be highly effective to decrease the gate length of an FET.
In the past, gate lengths of approximately 500 nm and approximately 200 to 100 nm have frequently been used in a microwave band (up to several GHz) and a quasi-milliwave band (up to 30 GHz). However, in recent years, because of advancements in exposure methods and in fine processing techniques for resist material, by using an electron beam exposure method, for example, a gate length of 100 nm or less (a sub-hundred nanometer range of approximately 20 to 50 nm) has been realized. Actually, an FET using an extremely short gate has been experimentally formed, and high-speed properties and high-gain properties thereof have been confirmed in a milliwave band.
A gate electrode having the sub-hundred nanometer range described above is generally formed by a lithographic technique using an electron beam exposure method as described above, and in order to obtain a fine opening width using an opening pattern capable of forming a shape in conformity with a gate electrode to be formed, a resist material having a high electron beam sensitivity is used, and in order to form a gate electrode having a cross-sectional T-shape, a multilayer resist structure is used. The gate electrode is generally formed by deposition/lift-off, sputtering, or the like.
In the electron beam exposure method described above, since electron beams serve as the exposure source, and since the diameter of a convergent spot can be decreased by this method, it has been believed that the electron beam exposure method is most suitable for forming an extremely fine opening pattern having a length in the sub-hundred nanometer range.
However, according to this electron beam exposure method, since electron beams are converged and are then radiated, direct drawing must be performed at a position at which an opening portion is desired to be formed. That is, several thousand to several tens of thousands of areas at which gate electrodes of FETs are to be formed are present on one wafer, and all the areas mentioned above must be sequentially irradiated with electron beams to draw the patterns. In addition, if two or more gate electrodes are to be formed in one FET, it is easily estimated that an extremely long period of time is necessary to complete the exposure on one wafer.
On the other hand, according to a light exposure method, since exposure can be simultaneously performed in more than one chip area formed on a wafer, in contrast to the electron beam exposure method, exposure can be performed in an extremely short period of time.
However, in the light exposure method, since a light source having a wavelength of several hundred nanometers is used as an exposure source, the dimensions of an opening pattern to be formed are liable to be influenced by this wavelength, and hence it has been believed that the formation of a very fine pattern cannot be advantageously performed by a light exposure method.
Under the circumstances described above, attempts have been made to use a light exposure method for forming very fine patterns. According to a light exposure method using a conventional type of photomask (reticle), the limitation of fine pattern formation is approximately 300 nm; however, when an excimer laser (ArF or KrF) which is a short wavelength light source, a phase shift mask, a dummy gate process, or the like is used, the formation of a fine opening pattern having a length in the 100 to 200 nm range can be achieved even when a light exposure method is used.
In addition, according to patent publication 1, a method for decreasing an opening width of an opening pattern has been disclosed. The method comprises the steps of forming an opening pattern in a photoresist film formed on a semiconductor substrate by a photolithographic technique, and then performing heat treatment of the photoresist film at a temperature higher than a conventional post-baking temperature so that sidewall portions of the opening pattern formed in the photoresist film are distorted by being heated sufficiently to flow.
Furthermore, according to patent publication 2, a method has been disclosed in which a wall angle of a patterned resist film is controlled to be inclined by performing heat treatment of the patterned resist film. The purpose of this method is that when a gate electrode is formed by deposition, the opening formed in the resist film is not blocked by a gate metal material.
Patent publications 1 and 2 described above are Japanese Unexamined Patent Application Publication Nos. 6-104285 and 6-53251, respectively.
However, in the light exposure method, even when the technique described above capable of forming a finer pattern is used, opening dimensions having the sub-hundred nanometer range have still not been obtained as is the case in the past.
In particular, according to the technique disclosed in patent publication 1, since the side wall portions of the opening pattern are approximately uniformly distorted by heat, the thickness of an upstanding portion of the gate electrode is decreased, whereby disconnection of the gate electrode is liable to occur in the height direction, and in addition, the gate resistance may also be increased in some cases.
In addition, according to the technique disclosed in patent publication 2, since the wall angle of the resist film is controlled to be inclined, the opening width of the opening pattern formed in the resist film may be undesirably increased in some cases, and as a result, the object of forming finer electrodes cannot be obtained.
Accordingly, the present invention was made to solve the problems described above, and is able to provide a masking member (hereinafter referred to as xe2x80x9cfine electrode-forming masking memberxe2x80x9d) for forming fine electrodes and a manufacturing method therefor, a method for forming electrodes, and a field effect transistor.
According to the present invention, although a light exposure method is used, a fine electrode-forming masking member having an opening width of 100 nm or less can be obtained, and when this fine electrode-forming masking member is used, a finer electrode, such as a gate electrode used for a field effect transistor or the like, can be formed without substantial increase in disconnection or resistance.
First, the present invention is used for forming fine electrodes on a substrate and relates to a method for manufacturing a fine electrode-forming masking member having opening patterns in conformity with the shape of the fine electrodes.
In order to solve the technical problems described above, the method of the present invention comprises a step of forming a first masking member having penetrating portions to be formed into the opening patterns on the substrate using a photosensitive resin; and a step of heat treating the first masking member so that parts of sidewalls, which are in contact with the substrate, of the penetrating portions formed in the first masking member, are extended along the substrate by the heat treatment to form extension portions. As a result, the widths of the penetrating portions at the bottom surface side are decreased so as to form the opening patterns.
The step of forming the first masking member described above may comprise a step of forming dummy patterns in conformity with the shape of the penetrating portions on the substrate; a step of forming a second masking member on the substrate except for regions covered with the dummy patterns; and a step of removing the dummy patterns for forming the penetrating portions.
The second masking member described above preferably comprises a negative type photosensitive resin, and the dummy pattern preferably comprises a positive type photosensitive resin.
In addition, after the step of forming the second masking member, a step of performing heat treatment of the negative type photosensitive resin and the positive type photosensitive resin is preferably performed so that mixed layers each composed of both the negative type photosensitive resin and the positive type photosensitive resin are formed along the boundaries between the second masking member and the dummy patterns.
In the method for manufacturing the fine electrode-forming masking member, according to the present invention, each of the penetrating portions formed in the forming step preferably has a width of 0.1 to 0.2 xcexcm between sidewalls opposing each other.
In the heating step for decreasing the widths of the penetrating portions at the bottom surface side, each of the extension portions preferably has an extension width of 0.01 to 0.05 xcexcm along the substrate.
In addition, each of the opening patterns obtained in the heating step preferably has a width of 0.1 xcexcm or less at the bottom surface side.
The heating step for decreasing the widths of the penetrating portions at the bottom surface side is preferably performed at a temperature of 160 to 200xc2x0 C.
The present invention may also be applied to the fine electrode-forming masking members manufactured by the methods described above. In this fine electrode-forming masking member, the opening patterns each have a small width at the bottom surface side as compared to that at the open end side.
The present invention is also applied to a method for forming fine electrodes using the fine electrode-forming masking member described above. The method for forming the fine electrodes of the present invention comprises a first step of preparing one of the fine electrode-forming masking members described above; a second step of forming fine electrodes on regions of the substrate exposed through the opening patterns while the substrate is masked with the fine electrode-forming masking member; and a third step of removing the fine electrode-forming masking member.
Before the second step is performed, a step of performing recess etching may be further performed on the regions of the substrate exposed through the opening patterns while the substrate is masked with the fine electrode-forming masking member.
The method for forming the fine electrodes described above is preferably applied to the formation of gate electrodes for field effect transistors. In this case, the substrate may be a semiconductor substrate, and the fine electrode may be a gate electrode used in a field, effect transistor.
Furthermore, the present invention is applied to a field effect transistor using the gate electrode formed by the method for forming the fine electrodes described above.
Other features and advantages of the present invention will become apparent from the following description of embodiments of the invention which refers to the accompanying drawings.