As semiconductor technology has advanced, the amount and speed of logic available on an IC, such as an FPGA, has increased more rapidly than the number and performance of I/O connections. As a result, IC die stacking techniques have received renewed interest to address the interconnection bottleneck of high-performance systems. In stacked IC applications, two or more ICs are stacked vertically and interconnections are made between them. Such a stacked arrangement is referred to as a system-in-package (SIP).
Through die vias (TDVs) can be employed to establish interconnections between stacked ICs. A TDV is a metal via that extends through a die of one IC for coupling to interconnect of another IC. In the design of stacking-friendly ICs, regions in the device layout are dedicated to TDVs. Typically, the dedicated TDV regions in a layout do not allow any metal or active layers within a predefined distance of the TDVs. As a result, there can be low metal pattern density around the TDVs of a stacking-friendly IC. Such a low metal pattern density can result in low chemical metal polishing (CMP) efficiency and variation in interconnect height among the metal layers of the interconnect. In particular, the metal height variation can accumulate over several metal layers, which can cause port depth of focus around TDVs during optical lithography.
Accordingly, there exists a need in the art for a method and apparatus for customizing metal pattern density in ICs configured for use in die stacking applications.