With a microcomputer for a low-speed operation, as shown in FIG. 5, a sampling clock 502 operating at frequencies higher than a clock 501 before compensation is inputted from an external input, for the purpose of testing, thereby working out a duty (duty cycle). High/Low is decided on a resolution-by-resolution basis, the resolution being determined by the sampling clock 502, and because, for example, four High periods, and eight Low periods are present, duties are computed to be on the order of about 30% to thereby executing duty compensation. Such an example has been described in Japanese Unexamined Patent Application Publication No. 2001-124813.