In power electronics devices, as switching elements for controlling power supply to loads such as motors, insulating gate type semiconductor devices, such as an IGBT (Insulated Gate Bipolar Transistor) and a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), are widely used. As one of vertical MOSFETs for power control, there is a trench-gate type MOSFET in which a gate electrode is embedded into a semiconductor layer (for example, the following Patent Documents 1 and 2). In general, in a trench-gate type MOSFET, heightening of withstand voltage and lowering of on resistance establish a trade-off relationship.
On the other hand, an attention is paid to a MOSFET and an IGBT using a wide band gap semiconductor of silicon carbide (SiC) or the like as next-generation switching elements that can implement high withstand voltage and low loss, and it is highly expected that they are applied to a technical field that treats high voltage of about 1 kV or more. Besides SiC, for example, gallium nitride (GaN) materials and diamond are used for wide band gap semiconductors.
In a trench-gate type MOSFET using wide band gap semiconductors, avalanche field intensity at a PN junction between a base region and a drift layer is equivalent to dielectric breakdown field intensity of a silicon oxide film to be used for a gate insulating film. For this reason, when a high voltage is applied to a MOSFET, the highest electric field is applied to a gate insulating film at a bottom portion of a trench into which a gate electrode is embedded, and dielectric breakdown of the gate insulating film might occur on that portion.
Patent Documents 1 and 2 propose that in each of n-channel trench-gate type MOSFETs, a p-type diffusion layer (protective diffusion layer) is provided to a bottom portion of a trench in a drift layer in order to protect a gate insulating film at a bottom portion of a trench of the gate electrode. The protective diffusion layer enhances depleting of an n-type drift layer at the time of turning off a MOSFET, and relieves concentration of the electric field to the bottom portion of the trench of the gate electrode. In Patent Documents 1 and 2, the protective diffusion layer is electrically connected with a base region (body region) of the MOSFET, and an electric potential of the protective diffusion layer is fixed, thereby further relieving the concentration of the electric field to the trench bottom portion.
For example, in Patent Document 1 (FIG. 3), a trench of a gate electrode is formed into a line shape, a p-type diffusion layer (p−− layer) with low density is extended on a side surface at the end of a longitudinal direction of the trench, and a protective diffusion layer at a bottom portion of the trench is electrically connected to a base region on an upper layer via this p−− layer.
Further, in Patent Document 2 (FIGS. 1 and 2), a trench of a gate electrode is formed into a lattice shape, and a contact that connects a protective diffusion layer at a bottom portion of the trench and a source electrode on the upper layer of the gate electrode is provided onto an intersection of the gate electrode so as to penetrate the gate electrode. The protective diffusion layer is electrically connected to the base region via the contacts and the source electrode.
When a MOSFET that switches a high voltage is turned off, a drain voltage abruptly rises (for example, changes from 0 V to a several hundred V). In a MOSFET having a protective diffusion layer at a bottom portion of a trench of a gate electrode, when a drain voltage abruptly rises, a displacement current is applied to the protective diffusion layer via a parasitic capacitance between the protective diffusion layer and a drift layer. This displacement current is determined by a fluctuation (dV/dt) in an area of the protective diffusion layer and a drain voltage (V) with respect to time (t) (Patent Document 3).
Like Patent Documents 1 and 2, when a protective diffusion layer is connected to a base region, a displacement current applied to the protective diffusion layer is applied to a base region. At this time, a voltage drop occurs in a resistance component between the protective diffusion layer and the base region, and this also causes dielectric breakdown of the gate insulating film.