The incorporation of increasing numbers of devices into progressively smaller integrated circuits remains an important challenge in Very Large Scale Integration (VLSI). Effective electrical isolation of the devices in the integrated circuit may be achieved by a variety of methods, including generating dielectric layers of suitable thickness, and/or by increasing the relative spacing of devices in the integrated circuit. Since the foregoing isolation methods typically occupy relatively large portions of the available “real estate” in the integrated circuit, the desirable objective of increasing integration density conflicts with the need to provide suitable electrical isolation for selected devices and regions in the integrated circuit.
One example of an integrated circuit requiring suitable electrical isolation are various semiconductor memory devices, such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, as well as other known memory devices. In each of these devices, a memory array is provided that includes a plurality of memory cells that are suitably arranged in rows and columns. Typically, a plurality of conductive word lines are positioned along the rows of the array to couple cells in respective rows, while a plurality of conductive bit lines are positioned along columns of the array and coupled to cells in the respective columns. The memory cells in the array generally include one or more transistors, and may also include a storage device, such as a capacitor, that are operable to store information by establishing logic levels (corresponding to a ‘1’ or a ‘0’) in the cells of the array. Information may be accessed from the cells when desired by activating various peripheral circuits that are coupled to the cells through the word lines and bitlines to retrieve the stored information.
The devices within cells of the array of the foregoing memory devices generally require electrical isolation from the peripheral circuits, since the voltages employed in the peripheral circuits may be significantly higher than the voltages typically used in the memory array. Although shallow trench isolation (STI) structures may be formed between the memory array and the peripheral circuits of a memory device in order to achieve electrical isolation, STI structures may not be suitably configured to provide adequate isolation in many instances. In particular, the STI structures may not be formed deeply enough in a substrate portion of the memory device to provide suitable isolation. Accordingly, what is needed in the art are devices having improved isolation structures and methods of forming the isolation structures.