Previous logic systems, such a boolean logic systems, have employed clocking signals to regulate the sequential processing of binary logic signals. Typically, a sequential logic circuit will respond to multiple inputs to generate an output. As input logic signals propagate through the sequential circuit, the sequential circuit output is unreliable for a period of time corresponding to worst case propagation delays through the individual logic gates. Typically, the output signal is sampled at a time when the output is stable, often by latching the output into a register. The sampling time is set according to an independent clock signal, i.e., one that is not derived from the states of the logic gates themselves.
While these traditional synchronous circuits have become the dominant class of logic, a substantial amount of design analysis is necessary to avoid a variety of timing-related problems, such as race conditions. In addition, the fraction of power and real estate that must be devoted to clocking has become substantial, and in certain instances has become a limiting factor to the total amount of circuitry that can be integrated onto a single chip.