1. Field of the Invention
The present invention relates to an apparatus and a method for analyzing circuit specification description design, and specifically to an apparatus and a method for analyzing circuit specification description design for designing a semiconductor integrated circuit using circuit specification description.
2. Description of the Related Art
Heretofore in the design of a semiconductor circuit, the circuit specifications are described using a natural language or a property description language, and on the basis of the description, the semiconductor circuit is designed.
When the circuit specification description is described using a natural language, the polysemy, or ambiguity of the natural language causes discrepancy in recognition between designers, resulting in problems, such that the designed circuit does not operate. Although part of the polysemy, or ambiguity of the description can be solved by describing circuit specifications using a property description language (such as SVA and PSL), complete solution cannot be obtained.
For example, when circuit specifications are described as “when ‘req’ is asserted, ‘ack’ is asserted” using a natural language is described using a property description language, the property cannot be described if the number of cycles between ‘req’ and ‘ack’ remains ambiguous. Therefore, these ambiguities are normally solved when the natural language is translated into the property description language.
However, even if circuit specifications are described using a property description language, it cannot be said that the polysemy, or ambiguity of the circuit specification description is completely solved. For example, when circuit specifications are described as “when ‘req’ is asserted, ‘ack’ is asserted” using anatural language is described using SVA, which is a property description language, a“req | => ack”, it cannot be known whether ‘req’ is 1 or 0 in the cycle next to the cyclewherein ‘req’ becomes 1, or whether ‘ack’ is 1 or 0 in the cycle before the cycle wherein ‘ack’ becomes 1. When the circuit specifications of “req | =>ack” is accurately described in the natural language, it means that “when ‘req’ is 1, ‘ack’ becomes 1 after a cycle.” Furthermore, it cannot be known whether the status of ‘req’ in the cycle before the cycle wherein ‘req’ becomes 1 is 1 or 0.
In other words, even in the circuit specifications described using a property language as described above, there can be a plurality of signal patterns (hereafter referred to as “path patterns”) for one circuit specification description. However, since the designer has no means to know how much polysemy is present in the circuit specifications described by the designer, the designer's intention is not accurately conveyed in many cases, leading to the occurrence of problems as described above.
For example, Japanese Patent Application Laid-Open No, 5-101132 proposes a logic circuit operation verifying apparatus that smoothly and efficiently verify a circuit to be designed. However, even in the proposal, no methods to know how much polysemy is present in the circuit specifications described by the designer are disclosed.