1. Technical Field of Invention
The present invention relates to a power regulator for providing precisely regulated power to a microelectronic device such as a microprocessor. Improved power regulation is accomplished by optimizing the power efficiency of the power regulator. In particular, in a multiphase system, the number of active phases is increased or decreased to achieve optimum power efficiency.
2. Background of the Invention
Regulated power supplies or voltage regulators are typically required to provide the voltage and current supply to microelectronic devices. The regulator is designed to deliver power from a primary source to an electrical load at the specified current, voltage, and power efficiency. Switching power converters (SPC) also referred to as Buck regulators are commonly used voltage regulators due to their high efficiency, high current capability, and topology flexibility. In addition, they can be designed to provide very precise voltage and current characteristics required by devices such as microprocessors, microcontrollers, memory devices, and the like.
Power requirements for emerging leading edge technology microprocessors have become very difficult to satisfy. As the speed and integration of microprocessors increases, the demands on the power regulation system increase. In particular, as gate counts increase, the power regulation current demand increases, the operating voltage decreases and transient events (e.g. relatively large voltage spikes or droops at the load) typically increase in both magnitude and frequency. Some emerging microprocessors are expected to run on less than 1.3 volts and more than 100 amperes.
SPC's utilizing step-down multi-phase Buck converters have been the preferred topology to meet the low voltage and high current requirements of microprocessors. With the advent of increasingly complex power regulation topologies, digital techniques for power converter control, specifically in multiphase designs, can improve precision and reduce the system's total parts count while also supporting multiple applications in the same power system through digitally programmable feedback control.
Power consumption and thermal management are a major problem in today's computer systems. In systems with many processors, many of the processors are often in idle or less than full power states. When one or more of the processors are in this low power state, it is desirable to reduce the power consumption of the power supply so that the total system power consumption and dissipation is minimized.
One drawback to multiphase buck DC-DC converters is that considerable power is used during light load conditions to switch the multiple buck conversion phases (channels). As a result, the efficiency of multiphase converters can be poor at light loads. In addition, as more phases are added to improve full load efficiency, the light load efficiency becomes worse. The most efficiency sensitive applications such as blade servers often use more phases to improve the full load efficiency but sacrifice medium load and light load efficiency. In many applications, processors spend a majority of the time operating in the medium load range and only use peak load current for short durations. The result is that systems are over designed resulting in higher costs for cooling, AC-DC power supplies, and AC power used.
At medium and lighter loads, fewer phases (channels) of buck conversion can be used to provide the load current. This will make the DC-DC converter more efficient at the typical processor load currents. One problem however is that modern processors can change the load demand very quickly (within microseconds) so that the DC-DC converter must be able to respond to this change in current without an overload (too much current) condition in any of the phases (channels).
In analog multiphase controllers, phase dropping (aka phase shedding) has been implemented to extend battery life. In these applications, a signal is typically used to tell the controller when to enter and exit this more efficient state. There is typically one high efficiency state (1 phase) so the efficiency is not optimized over the entire range. In these controllers the phases cannot be added back fast enough to respond to the current slew rates seen in desktop or server microprocessor chips (1000 Amps/microsecond). Known analog controllers do not have the ability to implement autonomous phase drop/add with adaptive non-overlap control to optimize efficiency over a wide range of load currents and meet the transient requirements of modem microprocessors.