(1) Field of the Invention
The present invention teaches a method of forming trench openings in a dual damascene trench and via etch process by using a two component hard mask layer, termed a bi-layer, over different intermetal dielectrics, IMD, to solve dual damascene patterning problems, such as, fencing and sub-trench formation.
(2) Description of Related Art
Related patents and relevant literature now follow as Prior Art.
U.S. Pat. No. 6,603,204 B2 entitled “Low-K Interconnect Structure Comprised of a Multilayer of Spin-On Porous Dielectrics” granted Aug. 5, 2003 to Gates et al. describes a two layer hard mask structure, but lacks processing details for forming a low-k dielectric metal conductor interconnect structure having no micro-trenches present therein. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions.
U.S. Pat. No. 6,309,962 B1 entitled “Film Stack and Etching Sequence for Dual Damascene” granted Oct. 30, 2001 to Chen et al. teaches that two or three layers of hard mask are not needed in this process using an etch stop layer. A process for forming a dual damascene cavity in a dielectric, particularly a low k organic dielectric, is described. The dielectric is composed of two layers separated by an etch stop layer. Formation of the damascene cavity is achieved by using a hard mask that is made up of two layers of silicon oxynitride separated by layer of silicon oxide. For both the trench first and via first approaches, the first cavity is formed using only the upper silicon oxynitride layer as the mask. Thus, when the second portion is patterned, little or no misalignment occurs because said upper layer is relatively thin. Additional etching steps result in a cavity and trench part that extend as far as the etch stop layer located between the dielectric layers. Final removal of photoresist occurs with a hard mask still in place so no damage to the organic dielectric occurs. A final etch step then completes the process.
U.S. Pat. No. 6,605,874 B2 entitled “Method of Making Semiconductor Device Using an Interconnect” granted Aug. 12, 2003 to Leu et al. discloses a multiple hard mask layer process with no etch stop layer. The invention includes an embodiment that relates to method of forming an interconnect. The method includes the effect of reducing electromigration in a metallization. An article achieved by the inventive method includes a first interconnect disposed above a substrate; a first conductive diffusion barrier layer disposed above and on the first interconnect; an upper interconnect, that is either landed or unlanded and that is disposed above the first interconnect; and an upper conductive diffusion barrier layer disposed above and on the upper interconnect.
U.S. Pat. No. 6,472,306 B1 entitled “Method of Forming a Dual Damascene Opening Using CVD Low-K Material and Spin-On-Polymer” granted Oct. 29, 2002 to Lee et al. describes a single hard mask layer and no etch stop layer. Specifically, a method of forming a dual damascene opening, consisting of the following steps: a semiconductor structure having at least one exposed metal line is provided. A spin-on-polymer layer is formed over the semiconductor structure and the metal line. A CVD low-k material layer is formed over the spin-on-polymer layer. The CVD low-k material layer is patterned to form a CVD low-k material layer via over the metal line. The spin-on-polymer layer is patterned to form a spin-on-polymer layer via opening continuous and contiguous with the CVD low-k material layer via and exposing a portion of the metal line. The CVD low-k material layer adjacent the CVD low-k material layer via is patterned to form a CVD low-k material layer trench. The spin-on-polymer layer via opening and the CVD low-k material layer trench forming a dual damascene opening.