The invention pertains to methods for modifying inner-layer circuit features of printed circuit boards.
Printed circuit boards (PCBs) used in the electronic industry comprise a number of layers. Some of the layers comprise conductive traces, while other layers are non-conductive but for, perhaps, conductive vias joining traces found on other layers. Together, the layers of a PCB serve to route electrical signals between the various electrical components that are mounted to the PCB. The layers may also route signals to and from the PCB via traces that terminate at edge connectors, flex connectors, and other various contacts and connectors).
The layers of a PCB, as well as the pattern of conductive traces formed within each layer, are typically based on Computer Aided Design (CAD) data. The CAD data, in turn, is based on various design requirements and constraints that a designer inputs to the CAD system.
A significant problem with newly designed PCBs is that there is no easy way to test their functionality until their layers are fully assembled. Thus, in situations where an inner-layer layout error is detected during test, any repair effort must not only repair the inner-layer defect, but do so without endangering other surrounding circuit features. Unfortunately, this limits the available repair options.
When a choice is made to repair an inner-layer defect, the defect is typically repaired by means of a cutting tool such as a diamond cutter or laser. In order to position the cutting tool over the defect, two quantities must be estimated: 1) the coordinates of the defect, and 2) the depth of the defect. Unfortunately, PCB manufacturing variances make both of these quantities difficult to estimate. Estimating the coordinates of a defect can be difficult due to manufacturing variances in the alignment of layers, the tight spacing of traces within a layer and variations therein, etc . . . Manufacturing variances can also make it difficult to map the coordinates of a defect to a visible reference marker that can be used for the purpose of navigating a cutting tool over the defect. Estimating the depth of a defect is difficult in that the layers of a PCB are very thin and also subject to manufacturing variances. If a cutting tool penetrates a PCB too deep, or at the wrong location, it is likely that other circuit features of the PCB will be damaged.
In light of the above limitations of current PCB repair methods, there is no feasible way to repair an inner-layer defect of a PCB in significant quantities (i.e., when a large number of PCBs are found to carry the same inner-layer defect). As a result, the defective PCBs are typically scrapped; the inner-layer defect is fixed at the CAD level; a new lot of PCBs are assembled; and the test process is then repeated. One can therefore appreciate that an unanticipated inner-layer defect in a PCB is often associated with significant product development delays, and significant losses of time and money.
In one embodiment of the invention, a method for modifying an inner-layer circuit feature of a printed circuit board commences with the identification of a trimming point on the inner-layer circuit feature using an x-ray inspection system. The coordinates of the trimming point are then related to the coordinates of a visible reference marker on the printed circuit board. Next, the relationship between the visible reference marker and the trimming point is used to position a cutting tool over the trimming point. Finally, the cutting tool is used to make one or more cuts into the printed circuit board, until the inner-layer circuit feature is acceptably modified at the trimming point.