As is well known in the field of integrated circuit design, layout and fabrication, the manufacturing cost of a given integrated circuit is largely dependent upon the chip area required to implement desired functions. The chip area, in turn, is defined by the geometries and sizes of the active components such as gate electrodes in metal-oxide-semiconductor (MOS) technology, and diffused regions such as MOS source and drain regions and bipolar emitters and base regions.
Device structures are constantly being proposed with the objective of producing higher response speeds, higher device yields and reliability, lower power consumption and higher power handling capability. Many of the device improvements are achieved by scaling down or miniaturizing the devices. One approach is to simply scale down all process variables, dimensions and voltages. This approach includes, among other factors, for example for the typical MOS device, scaling dielectric thicknesses, channel lengths and widths, junction widths and doping levels. With this approach, the number of devices per unit area increases, threshold voltages decrease, delay time across channels decreases and power dissipated per area decreases. All device parameters, however, do not need to be scaled by the same constant. A design or process engineer may scale some device parameters independently of others which would optimize device operation. This more flexible approach would allow for a choice in geometries to fit with various tradeoffs for device optimization, rather than choosing a more strict scaling approach.
One of the more critical parameters that needs to be scaled to produce a highly reliable semiconductor device is the thickness of the dielectrics, for example the dielectrics used to form a gate dielectric of a MOS transistor, as an SRAM or DFAM, or a tunnel dielectric of floating gate memories or MNOS devices. Scaling dielectrics to produce highly reliable gate dielectrics has proven to be difficult. For example, gate dielectrics are typically made of pure silicon dioxide (SiO.sub.2), thermally grown or deposited. The integrity of silicon dioxide decreases as the thickness of the layer decreases producing more defects, for example, pinholes. The inability to produce uniform and reliable, scaled pure SiO.sub.2 gate oxides causes device failures and makes thinning of these layers impracticable.
In addition to the geometries and sizes of active components and the ability to scale process variables, the chip area also depends on the isolation technology used. Sufficient electrical isolation must be provided between active circuit elements so that leakage current and low field device threshold voltages do not cause functional or specification failures. Increasingly more stringent specifications, together with the demand, for example, for smaller memory cells in denser memory arrays, places significant pressure on the isolation technology in memory devices, as well as in other modern integrated circuits.
A well-known and widely-used isolation technique is the local oxidation of silicon to form a field oxide region between active areas, commonly referred to as LOCOS. The LOCOS process was a great technological improvement in reducing the area needed for the isolation regions and decreasing some parasitic capacitances. This process though is subject to certain well-known limitations, such as the lateral encroachment of the oxide into the active areas, known as "birdbeaking", additional topography added to the integrated circuit surface and undesired nitride spots forming along the interface of the silicon substrate and silicon oxide regions, known as the "Kooi" effect. Thermally grown gate oxides formed subsequent to the formation of the field oxide are impeded in the region of these nitride spots. Typically, these nitride spots are removed before gate oxides are formed, as with the well-known sacrificial oxide process as described more fully in U.S. Pat. No. 4,553,314 issued on Nov. 19, 1985 to Chan et al. However, this process of removing the nitride spots increases complexity and thus additional manufacturing costs as well as adding additional topography to the wafer causing step coverage problems at later stages. It would be desirable to have a high integrity scaled dielectric, for example, one that is used in association with gate electrodes for MOS transistors and which is formed in a manner to reduce subsequent processing steps.
It is therefore an object of the present invention to provide a method of forming improved dielectrics in active areas for scaled semiconductor devices.
It is a further object of the present inventon to provide the scaled dielectrics for improving the gates of transistors.
It is a further object of the present invention to provide a method of forming the gate dielectrics adjacent to isolation regions which requires significantly fewer subsequent processing steps thereby decreasing the manufacturing complexity and produce higher yields and reliability.
It is yet a further object of the present inventon to provide a method of forming improved gates of transistors increasing the planarity of the surface of the wafer thereby minimizing subsequent step coverage problems.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.