1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device having a plurality of semiconductor chips stacked to each other and electrically connected to each other by using penetration electrode penetrating through the semiconductor chips.
2. Description of Related Art
A stacked semiconductor device including a plurality of stacked semiconductor chips has been recently proposed. In this type of semiconductor device, penetration electrodes or through silicon visa are formed in the semiconductor chips, and signals and power are supplied through the penetration electrodes. For example, a semiconductor device having a configuration in which three semiconductor chips are stacked on a substrate is shown in FIG. 20 of Japanese Patent Application Laid-open No. 2005-136187. In this semiconductor device, supply of signals and power is performed from the side of the substrate, which means that the signals and power are supplied from a lowermost semiconductor chip to an uppermost semiconductor chip.
However, in the semiconductor device indicated in Japanese Patent Application Laid-open No. 2005-136187, the planar position of the penetration electrodes provided in each semiconductor chip is different for every semiconductor chip. Therefore, in order to connect corresponding penetration electrodes, wiring extending in planar direction is necessary. The wiring extending in planar direction has large electrical resistance compared with a penetration electrode. When power was supplied through such wiring, there was a problem that power supply voltage drops in the more upper semiconductor chip