In one aspect, the present inventions described and illustrated herein relate to an integrated circuit device having a memory cell array including error checking and correcting (ECC) circuitry and/or column redundancy, and techniques for programming, configuring, controlling and/or operating such device. More particularly, in one aspect, the present inventions relate to an integrated circuit having random access memory (“RAM”) array having a plurality of memory cells (for example, memory cells having an electrically floating body in which an electrical charge is stored) arranged in a matrix of rows and columns wherein the integrated circuit includes an ECC architecture and/or a column redundancy architecture including at least one redundant column to substitute or replace a column of memory cells having at least one defective memory cell.
Briefly, with reference to FIG. 1A, memory cell array 10 typically includes a plurality of memory cells 12 arranged in a matrix of rows 14 (each typically having a common word line 16) and columns 18. A row address decoder 20 enables one or more rows to be read by sensing circuitry 22 (for example, a plurality of sense amplifiers). A column decoder 24, in response to an address, selects one or more of the outputs of the sensing circuitry 22.
One technique to improve the reliability of the data stored and/or output by dense memories is to employ ECC techniques. ECC techniques (for example, techniques to correct or reduce the impact of alpha particle induced soft error rate and/or errors caused by random defects in memory structures due to, for example, various complex fabrication processes) generally require the implementation of exclusive OR gates (“XOR”) to calculate the parity of the ECC word. A longer ECC word requires the calculation of parity of more bits and hence requires “wider” XOR gates. Conventional schemes for parity calculation using wide XOR gates must address the challenges associated with wiring the various bits (sometimes from across the width of memory array 10) to the inputs of XOR gates. Notably, conventional techniques tend to employ a XOR tree in the read path (Read XOR Tree) and write path (Write XOR Tree). (See, FIG. 1B).
In addition, conventional implementations of the Single Error Correction (SEC) scheme using Hamming code often have a critical path for speed that begins from the bits read from the memory array (data and check bits), through the wide XOR gates to calculate the “syndrome” vector, which is then decoded to identify the position of the erroneous bit in the “ECC word”. This information is used to correct the error during the read operation. During the memory write operation, wide XOR gates are used to calculate the parity and produce the “check bits” for the ECC word, which are then written into the array along with the data.
In order to improve, enhance and/or maintain a predetermined manufacturing yield of a memory cell array and/or device, one or more redundant columns 18r are often incorporated into memory array 10 to logically “replace” one or more columns 18 having one or more defective memory cells 12 and/or sense circuitry 22.
In one conventional technique, column redundancy is implemented by including a redundant column address decoder 24r which is programmed or mapped to logically replace a defective column (i.e., a column of memory cells having one or more defective memory cells and/or defective sense circuitry 22) with spare, replacement, redundant or another column 18r of memory cells 12r in memory array 10 (i.e., redundant column 18r of memory cells 12r). The individual address comparators (not illustrated) of redundant column decoder 20r are programmed to “enable” spare or redundant data sense circuitry 22r when the “applied” address matches the address of the defective column (which is fixed/stored in redundant column address decoder 24r). In this regard, the address of the defective column 18 is programmed into address comparators of redundant column decoder 24r during wafer testing. In this way, the redundant column address comparators enable a spare or redundant data sense circuitry 22r to be active when a set of column address signals match the address of a defective column 18 which is programmed into redundant column address decoder 24r. 
One conventional redundancy technique employs a set of fuses to program or configure redundant column decoder 24r. In this regard, spare or redundant columns are programmed by selectively “blowing” fuses (not illustrated) within redundant column decoder 24r to “match” or correspond to the address of the columns having defective memory cells. Such fuses are often programmed prior to packaging, during the wafer testing stage, or immediately after packaging, during the device testing stage. In this way, spare or redundant data sense circuitry 22r (and data output path corresponding thereto) is enabled when the address matches the address programmed into redundant column decoder 24r. 
A multiplexer may be employed in the data output path that responsively selects between the data from normal column and a spare column. Under normal operation, the multiplexers select the data from normal column. The multiplexer associated with the defective column may be enabled to select the data from the spare column which thereby incorporates the data from the spare or redundant column into the output path. A multiplexer may also be implemented on the write input path, where the data slated to be written into the defective column is “steered” to the spare or redundant column.
Notably, disabling circuitry may be implemented in memory array 10 to disable the data sense circuitry corresponding to the defective column when the address matches the address programmed into redundant column decoder 24r. As such, in response to a “match” between the applied column address and the address programmed in redundant column decoder 24r, normal data sense circuitry 22 (and data output path corresponding thereto) associated with the defective column is disabled and redundant data sense circuitry 22r (and data output path corresponding thereto) is enabled.