1. Field of the Invention
This invention concerns a method for manufacturing a semiconductor device having a multilevel interconnection structure.
2. Description of the Prior Art
Conventionally, a Boron-doped Phospho Silicate Glass layer is used as an insulating layer between a lower wiring layer and an upper wiring layer. Since the Boron-doped Phospho Silicate Glass layer (BPSG) layer is easily smoothened by a heat treatment, it is preferable to use the BPSG layer as an interlayer between the lower and the upper wiring layers for preventing a formation of concave depression which sometimes causes a break in the upper wiring layer.
FIGS. 1A to 1F are cross sectional views illustrating a conventional method for manufacturing a semiconductor device having a PSG layer as an insulating layer between a lower wiring layer and an upper wiring layer.
At first, as shown in FIG. 1A, a semiconductor substrate 10 having a main surface is prepared. Then insulating layer 11 is formed on the semiconductor substrate 10. Next, a polysilicon layer and a refractory metal silicide layer, such as molybdenum silicide, are deposited successively on the insulating layer 11, and are selectively removed to form lower wiring layers made of the polysilicon layer 12 and the refractory metal silicide layer 13.
Then, as shown in FIG. 1B, an oxidizing treatment is performed to form an oxide layer 14 at the exposed portion of the polysilicon layer and the refractory silicide layer 13 so as to control the resistivity of the lower wiring layer. Then, a silicon oxide layer 15 is deposited by a Chemical Vapor Deposition (CVD) as an insulation layer or a passivation layer.
Next, as shown in FIG. 1C, a Boron-doped Phospho Silicate Glass layer (BPSG) 16 and a Phospho Silicate Glass layer (PSG) 17 are deposited successively. In the following description, the term "Phospho Silicate Glass" is used as a generic term which includes both the PSG and the BPSG, and the PSG and the BPSG are distinguished each other, for convenience.
Then, as shown in FIG. 1D, a heating treatment is performed in an ambient environment to which a Phosphorus, in the form of POCl.sub.3 has been added, so as to smoothen the BPSG layer 16 and the PSG layer 17. This process is called reflow process.
Then, the PSG layer 17 is removed using, e.g., an ammonium fluoride (NH.sub.4 F) etchant. (FIG. 1E)
Next, an upper wiring layer 20 of, e.g., aluminum (Al), is deposited. (FIG. 1F)
In the conventional process if the step coverage of the BPSG layer 16 is poor, a space or a void 18 is sometimes formed and remains even though the reflow process of the BPSG layer has been carried out, as shown in FIG. 1C and FIG. 1D. Due to the high density of components required in large scale integration, the pitch between the adjacent lower wiring layers becomes narrow. Thus, the step coverage of the BPSG layer can become unsatisfactory. Furthermore, when the PSG layer 17 is removed, a hole 19 is sometimes formed due to an invasion of etchant into the void 18, as shown in FIG. 1E. Thus, the upper wiring layer 20 becomes thin at the step portion, and tho upper wiring layer 20 is sometimes broken.
If the etching at the hole 19 progresses to a large extent, the insulating layers 15 and 14 may also become etched. Thus, a short circuit between the upper wiring layer 20 and the lower wiring layer 12, 13 is sometimes formed.
Furthermore, in the conventional process, the oxidation process of the lower wiring layer and the heat treatment for the reflow process are performed individually. Thus, there is a problem that the time required for the production process for the semiconductor device becomes excessively long.
Moreover, the refractory metal silicide layer is directly exposed to the oxidizing ambient. Thus, the amount of molybdenum (Mo) in the refractory metal silicide layer is significantly influenced by the change of the oxidation condition. Thus, the delicate control of the resistivity of the refractory metal silicide is difficult.