a. Field of Invention
The present invention generally relates to integrated circuit devices, and particularly to forming facet-less epitaxially grown regions at isolation region edges.
b. Background of Invention
Due to the nature of epitaxial growth and certain structural features of integrated circuit devices, epitaxially grown regions may exhibit undesirably formed shapes that impact device performance and reliability. For example, the formation of epitaxially grown raised source/drain regions at the edge of shallow trench isolation (STI) regions of semiconductor devices may cause the raised source/drain regions to have facetted shapes at the STI region edges. The facetted shape of these raised source/drain regions may reduce the surface area of the raised source/drain regions. This reduced surface area in turn may undesirably increase the resistance between the raised source/drain regions and any formed contacts that are operable to provide device connectivity. Thus, since within integrated circuits a vast number of connections are needed, any degradation in connection resistance may compromise device operation within the integrated circuits and, therefore, lead to a reduction in device yield.
The following illustrated and described examples highlight some of these challenges involving the formation of epitaxially grown raised source/drain regions at the edge of shallow trench isolation (STI) regions in semiconductor devices.
FIGS. 1A-1H refer to processes directed at forming shallow trench isolation (STI) regions as is known in the art. In particular, FIGS. 1A-1F illustrate STI divot formation, which occurs naturally during typical STI processes. Although FIG. 1A shows an example silicon-on-insulator (SOI) wafer 100, similar problems may exist when this process is carried out on bulk wafers.
Referring to FIG. 1A, semiconductor wafer 100 may include a pad nitride layer 102 that is formed on a pad oxide layer 104 having a thickness of about 2-8 nm. The pad oxide layer 104 is formed on a SOI substrate 106.
A photo-resist stack 108 is formed over the pad nitride layer 102. A photo-resist stack such as stack 108 may use multiple layers. For example, an ARC (Anti-Reflective Coating) layer may be added under a photo-resist layer. Also, another form of organic under-layer material may be added under the ARC layer for planarization purpose. RIE (Reactive Ion Etching) etching utilizes multiple steps in order to etch the ARC and the organic under-layer of the photo-resist stack 108, the pad nitride layer 102, the pad oxide layer 104, and the SOI substrate 106. As illustrated, using a photo lithographic process on photo-resist stack 108, and subsequent RIE etching, trench region 110 is formed.
Referring to FIG. 1B, the photo-resist stack 108 (FIG. 1A) is first stripped by either a wet chemical or a dry strip process and is followed by performing STI fill 114 of region 110 (FIG. 1A) with HDP (High Density Plasma) oxide.
Referring to FIG. 1C, CMP (Chemical Mechanical Polishing) is performed on the structure shown in FIG. 1B in order to remove the excess STI oxide located on top of the upper surface 118 of the pad nitride 102 such that the remaining STI oxide 116 fills the STI region 110 up to the upper surface 118 of the pad nitride 102. It may be possible to lose some of the pad nitride during the CMP process.
Referring to FIG. 1D, an HF solution is used to remove some of the HDP oxide corresponding to STI oxide 116 (FIG. 1C). Thus, HDP oxide is removed from region 120 of the STI region 110, leaving remaining STI oxide 122. The amount of oxide removal depends on the remaining pad nitride, the amount of wet etch budget (up to gate insulator deposition), and STI step height target at the gate insulator deposition step.
Referring to FIG. 1E, the pad nitride 102 (FIG. 1D) is removed. As shown in FIG. 1F, the pad oxide 104 (FIG. 1D) is subsequently stripped. During the pad oxide 104 (FIG. 1E) removal process, there are several HF wet steps, which cause the removal of the HDP oxide corresponding to the STI oxide 122 and, therefore, result in the formation of STI divot. This is because the amount of removed HDP oxide from the STI 122 is greater than the thickness of the pad oxide 104. For example, due to the isotropic nature of wet chemistry, oxide is removed from all direction during the pad oxide 104 removal. As illustrated in FIG. 1G, small divots 124a, 124b are produced at the Si-STI interfaces 126a, 126b, respectively, as a result of additional pad oxide 104 (FIG. 1E) removal. The divot is created based on the silicon at the Si-STI interfaces 126a, 126b not being removed by the HF solution used in the etching process. The oxide etch step may be from a gate oxide pre-cleaning step, which removes native oxide located on the silicon surface. The pre-cleaning step may in addition remove native oxide on the wafer surface, further etching the STI oxide as well.
As shown in FIG. 1H, further oxide etching generates bigger divots 130a, 130b at Si-STI interfaces 126a and 126b, respectively.
FIGS. 2A-2K refer to processes associated with growing epitaxial regions at the edges of STI regions formed on an SOI substrate as is known in the art. In particular, FIGS. 2A-2K illustrate growing source/drain regions for nFET and pFET devices at the edge of an STI region that includes divots which are formed based on above processes described in relation to FIGS. 1A-1H.
As shown in FIG. 2A, STI isolation region 202 can be provided using the processes described and illustrated in relation to FIGS. 1A-1H. As illustrated, a centrally located poly Si or amorphous Si 208 gate electrode may be formed as a dummy gate 207 over the created STI region 202, which may correspond to region 122 as shown in FIG. 1H. A gate dielectric film 204 is formed by oxidation as either a dummy insulator or high K dielectric material. Gate 206 patterning is accomplished by poly Silicon (Si) or amorphous Si deposition 208 with optional electrode doping using Phosphorous (P) or Arsenic (As) ion implantation. Hard mask regions 210 are formed on top of the above-mentioned poly Si or amorphous Si 208 forming the gate electrodes. A typical hard mask material includes a single layer or a combination of oxide and nitride. A hard mask layer (not shown) is etched with resist patterning in order generate hard mask regions 210.
A photo-resist stack 212 may be used to cover some of the transistors in a process of forming spacers 216 of some other transistors. The photo-resist stack 212 may be formed to include multiple other layers including organic layers (not shown). By covering the nFET region using photo-resist stack 212 preceded by nitride deposition, spacers 216 are formed by spacer RIE of layer 209 in the pFET region. Multiple spacer technology may be used for device performance in modern technology. As such, spacer 216 is another spacer used in addition to spacer 214.
FIG. 2B illustrates the resulting structure following the removal of the photo-resist stack 212 (FIG. 2A), prior to or after, creating source/drain recesses 220 and 222 in the silicon layer 224 of the pFET region 225. The photo-resist stack 212 (blocking nFET region 221) may be stripped by a sulphuric acid/hydrogen peroxide solution. The source/drain recesses 220 and 222 within the silicon layer 224 may be produced by an etch process using HBr containing plasma. As illustrated, the controlled sloped profile of the produced recesses, as defined by 226a-226c, are intentionally provided for strain engineering to maximize device performance by increasing strain in the transistor channel for higher electron mobility.
Referring to FIG. 2C, epitaxial SiGe source/drain regions 228 and 230 are epitaxially grown in recesses 220 and 222, respectively. As illustrated, the resulting epitaxial profiles of the grown source/drain regions 228, 230 may have facets 232a-232d, whereby epitaxial faceting is a known phenomenon associated epitaxial processes. Accordingly, a facet is formed due to the crystalline growth (epitaxy) nature associated with directional growth properties at different surface atom concentrations. The reduced surface region S1′ of source/drain region 228 compared to surface region S2′ of source/drain regions 230 presents a less desirable area for contact formation.
As illustrated in FIG. 2C, at the STI-Si boundary 238 a divot 240 is created. As previously described, the divot 240 may be formed due to HF containing cleaning process steps associated with pre-gate electrode level cleaning processes. The divot 240 depth may be about 20-40 nm from the silicon surface 242. Within the STI-S1 boundary 238, since the epitaxial growth of source/drain region 228 stops at an epitaxial boundary 244 with the divot 240, the grown source/drain region 228 includes a non-symmetric shape having a relatively large facet 232a compared to source/drain region 230.
Referring to FIG. 2D, a protective layer 248 is formed within nFET region 221 in order to prevent any epitaxial growth in subsequent process steps. A typical material for the protective layer may be silicon nitride having a thickness in the range of about 5-30 nm. Photo-resist stack 250 is then provided for resist pattering in order to block pFET region 225.
Referring to FIG. 2E, spacers 254 are formed via a RIE process in the nFET region 221 only once protective layer 248 (FIG. 2D) is removed. As illustrated, the pFET region 225 is protected by photo-resist stack 250. As with FIG. 2C, in FIG. 2E, source/drain recesses 260 and 262 may be formed within silicon layer 264 of the nFET region 221. Photo-resist stack 250 may be stripped using the same or a similar process to that described in relation to FIG. 2C, either prior to or after creating the source/drain recesses 260, 262.
Referring to FIG. 2F, within nFET region 221, epitaxial Carbon doped source/drain regions 270 and 272 are epitaxially grown in recesses 260 and 262, respectively. As shown, the shape of facet 276 within nFET region 221 is the same as facet 232a (FIG. 2C) within the pFET region 225 (FIG. 2C). Facet 276, which is formed at the edge of divot 280 of STI-S1 interface 278, has a relatively larger facet that results in non-symmetrically shaped source/drain regions 270 and 272. The reduced surface region S1 of source/drain region 272 compared to surface region S2 of source/drain regions 270 presents a less desirable area for contact formation. The epitaxial source/drain regions 270, 272 may also be doped using, for example, Arsenic or phosphorus.
Referring to FIG. 2G, a MOL (Middle Of Line) liner 282 is deposited over the structure of FIG. 2F in order to protect the surfaces of epitaxially grown source/drain regions 228, 230, 270, and 272 during subsequent thermal oxidation steps.
Referring to FIG. 2H, an insulator material 284 is deposited over the structure of FIG. 2G followed by a CMP planarization step.
FIG. 2I refers to a resulting structure with typical subsequent process steps. Details of gate electrode structures are not shown in this drawing. However, any gate electrode structure may be utilized. For example, the gate electrode structure can be a RMG (Replacement Metal Gate) structure. The RMG process may include polishing insulator 284 (FIG. 2H) down to the cap nitride surface 210 (FIG. 2A), and further opening of the cap nitride by RIE or another appropriate process. An n-type device and p-type device gate is opened using a resist mask. Once the gate poly regions are exposed and removed, high K material, band gap engineered material, and metal electrode material are filled in the gate region 286. Contacts 290a-290d may be formed after RMG with insulator deposition, contact lithography, RIE, and contact metal fill process steps.
As previously described, based on the created facets 276, 232a that result from the formed divots 280, 240 associated with STI region 202, source/drain regions 230 and 270 include reduced contact surfaces S1 and S1′ for connecting to contacts 290b and 290c, respectively. The reduced surfaces may establish a poor electrical connection with the contacts 290b, 290c. Poor electrical connections cause increased contact resistance and, therefore, a potential device operation failure. As illustrated, source/drain regions 228 and 272, which are not located adjacent the STI region 202, are not effected by the STI region's 202 formed divots 280, 240 and, therefore, do not exhibit the faceting observed at source/drain regions 230 and 270.
FIG. 2J shows an extreme case with under fill due to the formation of excessively large facets 292 and 293 associated with source/drain regions 297 and 298, respectively. These excessively large facets 292 and 293 may be caused by deeper STI divots 295 and 296, respectively. Thus, little to no contact is established between source/drain regions 297 and 298, and contacts 299a and 290b, respectively.
FIG. 2K shows an example of a local level (intermediate) metal connection 294 for providing electrical connectivity between the nFET and pFET region 221, 225 devices for the structure of FIG. 2I. Thus, any contact resistance degradation between surfaces S1 and S1′ of source/drain regions 230 and 270, and contacts 290b and 290c, respectively, will impact the connectivity provided by metal connection 294. Since, for example, in the order of about a billion contacts and connections may be used in modern semiconductor chips, the above described connection issues may result in a significant product yield reduction. Thus, alternative isolation processes may be proposed.