As integrated circuit feature sizes decrease, other device dimensions also decrease to maintain the proper device operation. For example, as gate conductor widths decrease, the thickness of the gate dielectric needs to decrease to provide proper capacitance to control the transistor.
To meet the requirements of sub-100 nm devices, an equivalent oxide thickness (EOT) of less than 1.5 nm is needed. Using SiO2 as the gate dielectric, it is difficult to maintain its dielectric property below about 2 nm thickness due to the high tunneling leakage.
High-k materials, i.e., dielectric materials having higher dielectric constant k than that of SiO2 (k˜3.9), can provide high capacitance with higher thickness, and thus have been studied as replacement for SiO2. For example, a high-k value of 20, which can be obtained with various transition metal oxides such as hafnium oxide, can be about five times thicker than a SiO2 film with similar capacitance value. The thicker gate dielectric layer of high-k material can reduce tunneling leakage current through the gate, enabling sub-100 nm MOSFET devices.
The fabrication of high-k gate dielectric layers can provide difficulty in realizing the full benefits of the high dielectric constant. For example, processing high-k dielectric layers in the presence of oxygen at elevated temperatures, e.g., high-k deposition or subsequent anneal processes, can form a SiO2 interfacial layer between the silicon substrate and the high-k layer. The SiO2 interfacial layer can increase the effective oxide thickness, reducing the capacitance of the gate dielectric layer. Further, high-k gate dielectrics can contain a greater number of bulk traps and interface traps than thermally growth SiO2 gate dielectrics. The traps can degrade the device performance, such as sub-threshold slope, threshold voltage, flatband voltage shift, and Frenkel-Poole tunneling leakage.
Thus there is a need to develop improved methods and structures involving high-k gate dielectrics and related semiconductor devices.