1. Field of the Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for utilizing a flash EEPROM memory array as a supplement to main memory in a computer.
2. History of the Prior Art
Recently, flash electrically-erasable programmable read-only memory (EEPROM) storage devices have been used in arrays as a new form of long term storage. A flash EEPROM memory array is constructed of a large plurality of floating-gate metal-oxide-silicon field effect transistor devices arranged as memory cells in typical row and column fashion with circuitry for accessing individual cells and placing the memory transistors of those cells in different memory conditions. Such memory transistors may be programmed by storing a charge on the floating gate. This charge remains when power is removed from the array. This charge (typically, a "zero" or programmed condition) or its absence (a "one" or erased condition) may be detected when the device is read.
These arrays may be designed to accomplish many of the operations previously accomplished by other forms of memory in digital systems and especially in computer systems. For example, flash memory is being used to replace various read-only memories (ROM) such as the basic input/output startup (BIOS) memory of a computer system. The ability to program flash memory in place offers substantial advantages for BIOS memory over more conventional EPROM memory which must be removed from the system to be reprogrammed for changes to system components. More recently, flash memory has been used to provide a smaller lighter functional equivalent of an electro-mechanical hard disk drive. Flash memory is useful for this purpose because it may be read more rapidly and is not as sensitive to physical damage as an electro-mechanical hard disk drive. Flash hard drive memories are especially useful in portable computers where space is at a premium and weight is extremely important.
Although flash EEPROM memory arrays have been used for ROM type storage and to replace electromechanical hard disk drives, they have not been successfully adapted to use on the memory bus for storing changing data.
There are a number of reasons that it is desirable to use flash EEPROM or other non-volatile memory arrays to supplement main memory. Flash and other non-volatile memory requires no refresh cycle and do not expend power or time on such cycles. A non-volatile memory on the memory bus would allow programs stored therein to be retained when power was removed from the system. Such programs would be available for execution when power was applied without having to be copied to memory. The system BIOS could be stored in and executed from such memory to provide much faster start ups and to eliminate the need for main memory DRAM to shadow the BIOS. Application programs and other processes could also be stored in and executed directly from the non-volatile memory array. To do so would eliminate the transfer of those application programs between long term memory and main memory and thereby relieve most of the page swapping and attendant loss of speed caused by congestion in the limited space available in DRAM main memory. It would also allow applications to begin running more rapidly when they were called.
It would seem simple to place flash memory storing an application program on the memory bus. However, all known prior art flash EEPROM memory arrays which store changing data have been designed to utilize what is referred to as a "command-centric interface." Such an interface is specifically designed to require a command to place the flash memory array into a particular mode before any command may be executed.
Typically the command-centric interface includes a control center which receives commands from a host and runs the necessary processes to access the flash media as dictated by the command. Thus, for example, when the host processor directs a write command to a flash EEPROM memory array and furnishes data and an address, the control center stores the command and starts a sequence of processes to first determine if the array is in the proper state to receive the command. The control center is typically able to execute a number of commands such as "read," "write," "erase," and "provide status." Because of the number of individual operations which are carried out to accomplish any of these commands, a command is executed only if the flash EEPROM memory array is in a mode in which a commanded operation is allowed. A write to an address in a block being erased cannot be processed, for example; and an error signal will be returned. On the other hand, when the flash EEPROM memory array is in a proper state, the control center causes the data furnished with a write command to be written to the specified address. Such an interface was designed to automate the very complicated processes of writing and erasing the flash media, processes which often affect large amounts of data. These processes are typically conducted by state machines under control of the control center. All other commands directed to a flash EEPROM memory array including read commands are similarly handled. In one flash EEPROM memory array, if a read command is directed to an array functioning in an incorrect mode to carry out the command, the array automatically provides status data.
In order to execute processes out of memory on the memory bus, memory must immediately respond whenever a read access is attempted by providing the addressed data to the processor. To assure that this is accomplished, DRAM main memory on the memory bus is adapted to respond immediately to a row address strobe (RAS) followed by a column address strobe (CAS) and output enable signals furnished by a memory controller to provide the data on the memory bus from an address provided by a host processor. Similarly, when a host processor writes to DRAM on the memory bus providing data and an address, the memory responds to row address strobe (RAS) and column address strobe (CAS) signals generated by the memory controller to store that data at the addressed position.
Even when flash memory is designed to be accessed as a row and column array so that it may be positioned on the memory bus, the command-centric interface eliminates the ability of the array to respond absolutely to a read command by providing the addressed data. The interface may provide the data if the mode is proper or instead provide status if the mode is improper. A memory controller is not equipped to deal with other than the read data so a status report would cause a system failure. It might be possible to place circuitry between the memory bus and the command centric interface which would cause the interface to automatically respond to a read which produced a status result by completing any running operations within the flash memory, shifting the mode of the flash memory to read, and then furnishing the read data on the memory bus. However, although such circuitry would produce the addressed data in response to a read, it could not possibly do so in a time frame which would allow the processor to function without an inordinate number of wait states.
In addition to its command-centric interface, a flash EEPROM memory array inherently responds more slowly to write operations. The level of charge required to write a flash device is quite high so that writing even to unused flash memory takes somewhat longer than writing to DRAM. Moreover, that time to write a flash EEPROM memory array is further increased because with such arrays modified information is written to a clean memory area rather than being written over old data; and the old data is marked as invalid. Because changed data may not be directly written over invalid data in a block of flash memory but must be written to an unused area, the old data invalidated, and the block with invalid data ultimately erased, the average time to write to flash memory is increased by this erase time.
Thus a flash EEPROM memory array cannot be guaranteed to respond to operations at a rate or with a result which will allow its use on the memory bus to store processes which may be directly executed from that flash memory.
It is desirable to be able to utilize flash memory to supplement main memory in a computer system by providing an interface which allows flash memory to respond rapidly to read operations on the memory bus while still protecting data stored.