1. Field of the Invention
Embodiments of the invention generally relate to integrated circuits. In particular, embodiments of the invention relate to circuits that facilitate the identification of defective circuits.
2. Description of the Related Art
Integrated circuit (IC) devices are typically tested for defects at various stages of production. Typically, the tests become more complete as the chip progresses through production. While virtually all IC devices are eventually tested thoroughly, it is desirable to catch defects as early as possible, for example, before the die is assembled in a package. Dies for an integrated circuit can also be delivered prior to packaging. For example, multiple memory chips are frequently packaged together in a single package. In addition, multiple dies are frequently combined and assembled in a single package known as a hybrid.
It can be difficult to test an integrated circuit at the die level. For example, physical test equipment limitations, such as the number of test equipment probes available to make contact with pads on the die, can limit the testing of an integrated circuit 100 to spot checks. As illustrated in FIG. 1, a particular test probe 102 may make contact with only one pad 104 of the integrated circuit 100, leaving other pads untested. Time constraints for testing may render it impractical to move the test probe 102 to other pads. While test equipment usually has multiple test probes, the number of pads on a die typically greatly exceeds the number of test probes. Accordingly, only selected pads, such as 1 of 30 or 1 of 100 pads, are typically tested at the die level. Thus, defects can go undetected, and defective die can be delivered, packaged, combined with other chips, or the like.