1. Field of the Invention
The present invention relates to a layout designing apparatus, a layout designing method and a semiconductor device, and more particularly, to a layout designing apparatus outputting a layout pattern including a dummy pattern, a layout designing method, and a semiconductor device manufactured using the same.
2. Description of the Background Art
Conventionally, a photolithographic processing technology has been used for forming predetermined interconnections, electrodes and so forth in the process of manufacturing a semiconductor device. In the photolithographic processing technology, a resist film is formed on the surface of a semiconductor substrate, and thereafter transfers a pattern to be transferred (hereinafter referred to as xe2x80x9ctransfer patternxe2x80x9d) formed on a photomask onto this resist film by exposure and development processes.
Here, the resist film onto which the transfer pattern is transferred is formed on an interlayer insulating film or the like formed on the surface of the semiconductor substrate. A substructure such as interconnections or electrodes are generally formed under the interlayer insulating film. Because of such a substructure, an irregular portion may be formed on the upper surface of the interlayer insulating film. Existence of such an irregular portion forms a resist-film irregular portion corresponding to the irregular portion on the upper surface of the resist film formed on the interlayer insulating film. In a region where such a resist-film irregular portion is formed, the distance between the photomask and the upper surface of the resist film will be locally varied in the exposure step of transferring the transfer pattern of the photomask onto the resist film. This has caused problems such that the dimension of the transfer pattern transferred onto the resist film is varied, or that the transfer pattern is not resolved.
To prevent such problems from occurring, a step of planarizing the upper surface of the interlayer insulating film by the CMP (Chemical Mechanical Polishing) method is carried out before forming of the resist film. However, when the density of interconnections or the like in the substructure is not uniform and steps in the irregular portion on the upper surface of the interlayer insulating film are large, it was sometimes difficult to sufficiently planarize the upper surface of the interlayer insulating film by the CMP method.
Therefore, conventionally, a method has been employed in which dummy interconnections are formed in a region where no interconnection exists as the substructure to make the density of structures such as the interconnections uniform in the substructure in order to reduce the steps in the irregular portion (to increase the flatness) on the upper surface of the interlayer insulating film. To form such dummy interconnections, a layout designing method as described below is executed in a layout designing step in the manufacturing process of a semiconductor device.
FIG. 30 is a flow chart for illustrating a conventional layout designing method. Further, FIG. 31 is a schematic view showing a layout pattern obtained by the layout designing method shown in FIG. 30. Referring to FIGS. 30 and 31, the conventional layout designing method will be described.
Referring to FIGS. 30 and 31, in a dummy pattern arrangement method of the conventional layout designing method, first, the step of entering circuit patterns 101a to 101c such as interconnections constituting a circuit of the semiconductor device (S110) is executed. In this step of entering the circuit patterns (S110), data of the coordinates of circuit patterns 101a to 101c are entered and held in a memory of a computer system in which a software executing the layout designing method is installed.
Next, the step of producing dummy patterns 103a and 103b (S130) on the entire surface of a chip region in which circuit patterns 101a to 101c are arranged is executed. In the step of producing dummy patterns (S130), dummy patterns 103a and 103b are arranged in a matrix with a predetermined pitch. Further, the size of dummy patterns 103a and 103b are also predetermined. These dummy patterns 103a and 103b are the patterns for forming dummy interconnections.
Subsequently, the step of extracting dummy patterns 103a (S140), which are located in regions that are not overlapping with circuit patterns 101a to 101c and are spaced by predetermined distances from circuit patterns 101a to 101c, is executed.
Thereafter, the step of outputting a layout pattern (S150), including dummy patterns 103a extracted in the step of extracting the dummy patterns (S140) and circuit patterns 101a to 101c, is executed. Thus, the layout pattern can be obtained in which dummy patterns 103a indicated by the solid line are arranged in the regions where none of circuit patterns 101a to 101c is formed, as shown in FIG. 31.
Then, the transfer pattern of a photomask is formed based on such a layout pattern. Moreover, interconnections and dummy interconnections are formed on the semiconductor substrate based on this transfer pattern by the photolithographic processing.
The above-described conventional layout designing method had a problem as described below. In the conventional layout designing method, values that were predetermined irrespective of circuit patterns 101a to 101c were used for the size and the pitch of dummy patterns 103a and 103b in the step of producing dummy patterns (S130). In such a case, the pitches with which circuit patterns 101a to 101c are formed and the pitch with which dummy patterns 103a and 103b are formed may be different. Thus, circuit patterns 101a to 101c and dummy patterns 103a and 103b would overlap with each other more than necessary as shown in FIG. 31, and hence the number of dummy patterns 103b not extracted in the step of extracting dummy patterns (S140) would be increased. As a result, there were some cases in the layout pattern obtained in the step of outputting the layout pattern (S150), such that dummy patterns were not arranged in portions with enough spaces for the dummy patterns to be arranged (e.g. the region between circuit pattern 101b and circuit pattern 101c), and the uniformity of the pattern density were insufficient.
As such, when the pattern density is not sufficiently made uniform, not enough dummy interconnections will be arranged around the interconnections in the structure of the semiconductor device formed based on this layout pattern. This results in formation of an irregular portion on the upper surface of the interlayer insulating film formed on the structure of such interconnections or the like, which was sometimes impossible to be planarized by the CMP method.
It is an object of the present invention to provide a layout designing apparatus and a layout designing method capable of improving uniformity of the pattern density of a layout pattern in which a dummy pattern is formed, and to provide a semiconductor device manufactured using the layout designing method.
A layout designing apparatus according to one aspect of the present invention includes an entry unit for entering a plurality of circuit patterns of a semiconductor device; a recognition unit for recognizing positional data of the entered plurality of circuit patterns; a dummy pattern arrangement unit for producing a dummy pattern group including a plurality of dummy patterns, each of the plurality of dummy patterns being arranged per repetitive distance determined based on the recognized positional data of the circuit patterns; an extraction unit for extracting a final dummy pattern including a dummy pattern located in a region other than a region overlapping with the circuit patterns, from the dummy pattern group; and an output unit for outputting a layout pattern including the extracted final dummy pattern and the circuit patterns.
A case is now considered where dummy patterns are arranged between two adjacent circuit patterns spaced such that the dummy patterns can be arranged in between. When the repetitive distance and the arrangement of the dummy patterns are determined independent of the circuit patterns as in the conventional case, even if a plurality of dummy patterns were arranged between the circuit patterns as described earlier, all of the dummy patterns would be partially overlapped with the circuit patterns, which may result that no dummy pattern would be arranged between these circuit patterns in the final dummy pattern. However, according to the present invention, the repetitive distance of the dummy patterns is determined based on the positional data of the circuit patterns, so that the repetitive distance can be selected such that the dummy patterns can be arranged between two circuit patterns so as not to overlap with the two circuit patterns. Thus, the dummy patterns can reliably be arranged between the two circuit patterns in the final dummy pattern. Therefore, the region, in which no dummy pattern is arranged even though there is a space for dummy patterns to be arranged, can be reduced. As a result, a layout pattern having a more uniform pattern density compared to that of the conventional case can be attained using the layout designing apparatus according to the present invention.
In the layout designing apparatus according to the above-described one aspect of the present invention, the recognition unit may include a pitch recognition unit for recognizing a pitch in one direction of the circuit patterns, and the dummy pattern arrangement unit may include a unit for determining a submultiple distance of the recognized pitch as the repetitive distance.
In this case, the dummy patterns can be arranged with a pitch smaller than the pitch of the circuit patterns in one direction of the circuit patterns, so that the dummy patterns can reliably be arranged between the circuit patterns. Thus, the size of the region where no dummy pattern is arranged between the circuit patterns can be reduced in the final dummy pattern. As a result, the pattern density can be more uniform in the layout pattern.
In the layout designing apparatus according to the above-described one aspect of the present invention, the dummy pattern group may include a plurality of additional dummy patterns located between the plurality of dummy patterns, and the final dummy pattern includes the additional dummy patterns located in a region other than a region overlapping with the circuit patterns.
In this case, the additional dummy patterns will be arranged at positions displaced from the dummy patterns by a distance smaller than the repetitive distance.
Here, a case is considered where convex or concave portions are locally formed in the two-dimensional geometry of the circuit patterns. In a region near such convex or concave portions, it may be difficult to sufficiently improve the pattern density by the dummy patterns alone that are arranged with the above-described repetitive distance. Specifically, in the portion where, for example, a convex portion is formed in a circuit pattern, the distance between dummy patterns and the convex portion of the circuit pattern would be shorter, or the convex portion and the dummy patterns are partially overlapped with each other, resulting that no dummy patterns can be arranged in the final dummy pattern. Further, in the portion where, for example, a concave portion is formed in a circuit pattern, the distance between the dummy patterns and the concave portion of the circuit pattern would be larger, decreasing the pattern density compared to the other portions.
Thereat, application of the additional dummy patterns in such a region is considered, that are arranged at positions displaced from the dummy patterns as described above. For example, in the region where a convex portion is formed in a circuit pattern, application of the additional dummy patterns displaced from the dummy patterns in the direction away from the convex portion allows the additional dummy patterns to be arranged in this region so as not to overlap with the convex portion, in such a case that the dummy patterns are partially overlapped with the convex portion. Moreover, in the region where the concave portion is formed in the circuit pattern, the application of the additional dummy patterns displaced from the dummy patterns in the direction approaching the concave portion allows reduction of the distance between the concave portion and the additional dummy patterns. Furthermore, in a case where only one of the dummy patterns arranged per repetitive distance can be arranged in the region described above, application of the additional dummy patterns allows arrangement of more additional dummy patterns in the region. Thus, more uniform pattern density can be attained in the layout pattern.
In the layout designing apparatus according to the above-described one aspect of the present invention, each of the plurality of dummy patterns is preferably arranged per repetitive distance using positions of the circuit patterns as a reference.
In this case, the dummy patterns can reliably be arranged between the circuit patterns by using the positions of the circuit patterns as a reference. This can reduce the number of dummy patterns that are partially overlapping with the circuit patterns. Therefore, the region where dummy patterns are formed can be increased in the final dummy pattern, so that a layout pattern having an improved uniformity of the pattern density can be obtained.
In the layout designing apparatus according to the above-described one aspect of the present invention, the dummy pattern arrangement unit may arrange the dummy patterns in a partial region including the circuit patterns, of a region forming a layout pattern, and the output unit may output a layout pattern including a partial layout pattern for the partial region.
As for the layout designing, in a portion of a region forming the layout pattern (hereinafter referred to as a chip region) of a semiconductor device of which the layout is designed, the layout of a partial region, i.e. a part of the chip region, may be determined using an automatic arrangement/interconnection software. Moreover, one chip region may have a plurality of such partial regions arranged therein. Furthermore, the pitch with which the circuit patterns are formed may be different for each partial region. In such a case, optimal dummy patterns can be obtained for each of the partial regions if a layout pattern is to be output per partial region. As a result, generation of the region having a non-uniform pattern density can be prevented in the layout pattern.
In the layout designing apparatus according to the above-described one aspect of the present invention, the output unit may output a layout pattern including a peripheral dummy pattern located in a region other than a region occupied by the partial layout pattern, of the region forming the layout pattern.
In this case, the arrangement of the dummy patterns can be optimized in the partial region (the region occupied by the partial layout pattern) in a region forming the layout pattern, and the pattern density can be made uniform for the entire region forming the layout pattern by arranging the peripheral dummy pattern also in the region other than the partial region.
In the layout designing apparatus according to the above-described one aspect of the present invention, the peripheral dummy pattern is arranged based on a repetitive distance determined independently of a distance between the plurality of circuit patterns.
In this case, the repetitive distance or the like can be predetermined for the peripheral dummy pattern, so that the arrangement step of the peripheral dummy pattern can be simplified. Therefore, the time needed for the layout designing using the layout designing apparatus according to the present invention can be shortened.
A layout designing method according to another aspect of the present invention includes the steps of entering a plurality of circuit patterns of a semiconductor device; recognizing positional data of the entered plurality of circuit patterns; producing a dummy pattern group including a plurality of dummy patterns, each of the plurality of dummy patterns being arranged per repetitive distance determined based on the recognized positional data of the circuit patterns; extracting a final dummy pattern including a dummy pattern located in a region other than a region overlapping with the circuit patterns, from the dummy pattern group; and outputting a layout pattern including the extracted final dummy pattern and the circuit patterns.
A case is now considered where dummy patterns are arranged between two adjacent circuit patterns spaced such that the dummy patterns can be arranged in between. In such a case, according to the present invention, the repetitive distance of the dummy patterns is determined based on the positional data of the circuit patterns, so that the repetitive distance can be selected such that the dummy patterns can be arranged between two circuit patterns so as not to overlap with the two circuit patterns. Thus, the dummy patterns can reliably be arranged between the two circuit patterns in the final dummy pattern. Therefore, the region, in which no dummy pattern is arranged even though there is a space for dummy patterns to be arranged, can be reduced. As a result, the pattern density of the layout pattern can be improved while being made uniform.
In the layout designing method according to the above-described another aspect of the present invention, the step of recognizing may include a step of recognizing a pitch in one direction of the circuit patterns; and the step of producing the dummy pattern group may include a step of determining a submultiple distance of the recognized pitch as the repetitive distance.
In this case, the dummy patterns can be arranged with a pitch smaller than the pitch of the circuit patterns in one direction of the circuit patterns, so that the dummy patterns can reliably be arranged between the circuit patterns. Thus, the size of the region where no dummy pattern is arranged between the circuit patterns can be reduced in the final dummy pattern. As a result, the pattern density can be more uniform in the layout pattern.
In the layout designing method according to the above-described another aspect of the present invention, the dummy pattern group may include a plurality of additional dummy patterns located between the plurality of dummy patterns, and the final dummy pattern may include the additional dummy patterns located in a region other than a region overlapping with the circuit patterns.
In this case, the additional dummy patterns will be arranged at positions displaced from the dummy patterns by a distance smaller than the repetitive distance. When convex or concave portions are locally formed in the circuit patterns, it may be difficult to sufficiently improve the pattern density by the dummy patterns alone that are arranged with the above-described repetitive distance, in a region near the portion in which the convex or concave portions are formed as described above.
Thereat, the additional dummy patterns that are arranged at positions displaced from the dummy patterns as described above are applied in such a region. For example, in the region where a convex portion is formed in a circuit pattern, application of the additional dummy patterns displaced from the dummy patterns in the direction away from this convex portion allows the additional dummy patterns to be arranged in this region so as not to overlap with the convex portion, in such a case that the dummy patterns are partially overlapped with the convex portion as described above. Moreover, when a concave portion is formed in the circuit pattern, the additional dummy patterns can be arranged near the concave portion as described above. Thus, more uniform pattern density can be attained in the layout pattern.
In the layout designing method according to the above-described another aspect of the present invention, each of the plurality of dummy patterns is preferably arranged per repetitive distance using positions of the circuit patterns as a reference.
In this case, the dummy patterns can reliably be arranged between the circuit patterns by using the positions of the circuit patterns as a reference. This can reduce the number of dummy patterns that are partially overlapping with the circuit patterns. Therefore, the region where dummy patterns are formed can be increased in the final dummy pattern, so that a layout pattern having an improved uniformity of the pattern density can be obtained.
In the layout designing method according to the above-described another aspect of the present invention, the step of producing the dummy pattern group may include arrangement of the dummy patterns in a partial region including the circuit patterns, of a region forming a layout pattern, and the step of outputting may include outputting of a layout pattern including a partial layout pattern for the partial region.
As for the layout designing, in a portion of a region forming the layout pattern (chip region) of a semiconductor device of which the layout is designed, the layout of a partial region, i.e. a part of the chip region, may be determined using an automatic arrangement/interconnection software. Moreover, one chip region may have a plurality of such partial regions arranged therein. Furthermore, the pitch with which the circuit patterns are formed may be different for each partial region. In such a case, optimal dummy patterns can be obtained for each of the partial regions if a layout pattern is to be output per partial region.
In the layout designing method according to the above-described another aspect of the present invention, the step of outputting may include outputting of a layout pattern including a peripheral dummy pattern located in a region other than a region occupied by the partial layout pattern of the region forming the layout pattern.
In this case, the arrangement of the dummy patterns can be optimized in the partial region (the region occupied by the partial layout pattern) in a region forming the layout pattern, and the pattern density can be made uniform for the entire region forming the layout pattern by arranging the peripheral dummy pattern also in the region other than the partial region.
In the layout designing method according to the above-described another aspect of the present invention, the peripheral dummy pattern may be arranged based on a repetitive distance determined independently of a distance between the plurality of circuit patterns.
In this case, by predetermining the repetitive distance or the like for the peripheral dummy pattern, the arrangement step of the peripheral dummy pattern can be simplified. Therefore, the time needed for the layout designing using the layout designing apparatus according to the present invention can be shortened.
A semiconductor device according to a further aspect of the present invention is manufactured using the layout designing method according to the above-described another aspect of the present invention.
In such a manner, the pattern density can be made uniform in the layout pattern, and hence interconnections corresponding to the circuit patterns and dummy interconnections corresponding to the dummy patterns can be made more uniform in the interconnection layer or the like corresponding to the layout pattern in the semiconductor device. As a result, when an interlayer insulating film is formed on the interconnections and the dummy interconnections, the flatness of the upper surface of the interlayer insulating film can be improved.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.