This invention relates to programming memory controllers for computer systems.
In computer system operations, a memory controller (MC) driven by a Central Processing Unit (CPU) interacts with an outside memory. A CPU in a single integrated circuit chip is often referred to as a microprocessor. A memory controller may be outside of the microprocessor chip or it may reside inside. An MC resident inside the microprocessor chip can operate at the speed of the processor clock, which indicates the computer speed. In modern, high performance computer systems, synchronous dynamic random access memory (SDRAM) is typically used as the outside memory. The clock for the SDRAM operates at a speed many times lower than the processor clock.
Signals passing between the MC and the SDRAM take a finite time to travel, and both the MC and the SDRAM take a finite time to respond. Thus, time delays are associated with the finite speed of signal travel and the finite response time of a device or a system. These time delays have their origins in the physical processes involved in the construction and operation of electronic devices that make up the computer system. Therefore, various time delays encountered in computer operations can be minimized or optimized, but cannot be eliminated. Reliable computer design must take into account all significant time delays affecting computer operation.
Certain time delays are always significant, and thus must be taken into account in the design of the MC for input/output operations. Significance of some other time delays is measured with respect to the time period of the processor clock. Therefore, as the computer speed increases, various additional time delays have to be taken into account to ensure reliable operation of the MC. In computer input/output operations involving an MC and a SDRAM, signals originating in the MC do not appear instantaneously at the SDRAM, and vice-versa, due to propagation delays. Further, various time delays associated with a SDRAM depend on that specific SDRAM and its actual physical layout in the computer circuit board. Thus, the signaling delays between an MC and a SDRAM vary from system to system due to different types of system configurations and memory performance specifications.
Computer operations such as the input/output (I/O) operations are synchronized with the processor clock. The I/O operations take place around precise digital transitions in logic gates and flip flops constituting digital devices and systems. In order to make computer operations reliable, (e.g., a data read from a memory) it is necessary to hold a participating signal (e.g., a command signal) stable for a short time before and after the precise transition moment. Such time considerations, together with the various time delays mentioned earlier, constitute a significant fraction of the clock time period.
A memory controller in a digital computer typically will have the capability of generating a replica of the processor clock signal delayed by half a time period. This creates a digital time delay unit of half a processor clock period. This digital time delay unit along with the aforementioned analog time delays inherently present in the computer system dictates the programmed design of the MC for reliable input/output operations with the SDRAMs.
Digital signals for communications between the MC and the SDRAM fall into three categories: clock signals; command signals; and data signals. In a computer system, multiple signal lines constitute both the command and data paths. All communicating I/O signals must be designed to flow in concert in order to produce the right digital transitions at the right time. Precise timing designs of all these signals may be done, for example, by xe2x80x9cFirmwirexe2x80x9d, which is an embedded software contained in an erasable Programmable Read Only Memory (EPROM) or a flash memory. The present technique of MC programming design has been to use a spreadsheet to store all possible timing combinations and to manually design suitable solutions. Such exercises are specific for a particular system configuration. This becomes more difficult as the number of time delay elements to be considered increases with the increase in processor clock speed, and design may not be optimized for highest achievable performance. It has become necessary, therefore, to define the design problem with mathematical precision and create a general algorithm to solve it.
In one aspect, the invention relates to a method for programming a controller of a memory unit comprising: inputting a plurality of initialization parameters of the memory unit; calculating a clock delay and a command delay for each initialization parameter; calculating a set of read command delays for each pair of clock delays and command delays; calculating a set of write command delays for each pair of clock delays and command delays; calculating a system performance for each pair of clock delays and command delays; selecting the initialization parameter that offers the optimum system performance.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.