1) Field of the Invention
This invention relates generally to the fabrication of capacitors in a dynamic random access memory (DRAM) cell and more particularly to a method and process for fabricating capacitors with a large capacitance.
2) Description of the Prior Art
In dynamic semiconductor memory storage devices, it is essential that storage node capacitor cell plates be large enough to retain an adequate voltage level in spite of parasitic capacitances and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density continues to increase at a fairly constant rate. The issue of maintaining storage node capacitance is particularly important as the density of DRAM cells continues to increase for future generations of memory devices.
Semiconductor manufacturing technologies must develop the capabilities to densely pack storage cells while maintaining the required storage capacitances if future generations of expanded memory array devices are to be successfully manufactured.
The array of storage cells on a dynamic random access memory (DRAM) chip is one such circuit element experiencing electrical limitations. These individual DRAM storage cells, usually consisting of a single metal-oxide-semiconductor field-effect-transistor (MOS-FET) and a single capacitor are used extensively in the electronic industry for storing data. A single DRAM cell stores a bit of data on the capacitor as electrical charge. The decrease in cell capacitance caused by reduced memory cell area is a serious obstacle to increasing packing density in dynamic random access memories (DRAMs). Thus, the problem of decreased cell capacitance must be solved to achieve higher packing density in a semiconductor memory device, since decreased cell capacitance degrades read-out capability and increases the soft error rate of the memory cell as well as consumes excessive power during low-voltage operation by impeding device operation.
Generally, in a 64 MB DRAM having a 1.5 .mu.m.sup.2 memory cell area employing an ordinary two dimensional stacked capacitor cell, sufficient cell capacitance cannot be obtained even though a higher capacitor dielectric constant material, e.g., tantalum oxide (Ta.sub.2 O.sub.5), is used. Therefore, stacked capacitors having a three-dimensional structure have been suggested to improve cell capacitance. Such stacked capacitors include, for example double-stacked, fin-structured, cylindrical, spread-stacked, and box structured capacitors. In order to increase the surface area of the capacitor, there have also been proposed methods of forming a capacitor with a pin structure extending throughout a multi-layer structure of the capacitor to connect the layers with one another and methods of forming a capacitor using a hemispherical grain polysilicon (HSG) process using polysilicon grains.
One problem with current methods of fabricating capacitors having a non-planar topography is that metal "stingers" form between on polysilicon lines after polysilicon etch back steps. Metal stringers often remain behind at the foot or sides of a steep step when an anisotropic etching is used to pattern the polysilicon or metal layers. These stringers can cause shorting problems and can reduce yields.
Workers in the art are aware of the limitations of capacitors and have attempted to resolve them. U.S. Pat. No. 5,451,539 (Ryou) forms a T shaped storage electrode, but uses a photo-etch process to define the storage electrode. U.S. Pat. No. 5,399,518 (Sim) teaches a method of forming a T-shaped storage electrode by using a photo-etch step. U.S. No. 5,364,809 (Kwon et al.) teaches a method of fabricating a multi-chamber type capacitor. A stacked capacitor having a concave area is formed by coating an insulation layer with polysilicon, filling the central cavity with photo resist and etching back the polysilicon on the of the insulation layer to form a storage electrode. Kwon goes on to form multi-chambers in the capacitor. However, many of the prior art methods require substantially more processing steps or/and planar structures which make the manufacturing process more complex and costly. Therefore, it is very desirable to develop processes that are as simple as possible and maximize the capacitance per unit area. There is a challenge to develop methods of manufacturing these capacitors that minimize the manufacturing costs and maximize the device yields. In particular, there is a challenge to develop a method which minimizes the number of photoresist masking operations and provides maximum process tolerance to maximize product yields.