1. Field of the Invention
The present invention relates to a display device and a driving circuit of the display device. More specifically, the present invention relates to an active matrix display device having a thin film transistor (TFT) that is formed on an insulator and to a driving circuit of the active matrix display device.
2. Description of the Related Art
In recent years, semiconductor manufacture technologies have advanced and become capable of handling even more minute devices. Accordingly, LSI thus reduced in size is applied to small equipment such as portable information terminals and is required to cut power consumption. The current mainstream LSI is a low power voltage drive LSI that can be driven at about 3.3 V. On the other hand, LCDs (liquid crystal displays), which have lately been in increasingly greater demand as display units for portable information terminals and as computer monitors, drive their liquid crystals often with a signal having a voltage amplitude of 10 V to 20 V, and a driving circuit for driving them has at least a circuit portion driven at an accordingly high power voltage. When a controller LSI driven at a low power voltage around 3.3 V is connected to a liquid crystal driving circuit driven at a high power voltage, a level shifter that changes the amplitude of signal voltage is therefore indispensable.
Demands for reduced drive voltage is strong not only in LCDs but also in EL (electroluminescence: here including both singlet excitation light emission and triplet excitation light emission) displays, which have been developed recently.
FIG. 6 shows an example of a circuit diagram of a source signal line driving circuit in a display device. This source signal line driving circuit has level shifters 601 to 604, an input signal buffer 605, shift registers 606, NAND circuits 607, buffers 608, first latch circuits 609, and second latch circuits 610. The driving circuit is connected to a pixel 611. The buffers 608 may be omitted or arranged so as to suit the logic of a signal. A start pulse, a clock signal, a digital video signal and the like are inputted to the display device from the external. These signals are supplied from the controller LSI described above (not shown) and, therefore, generally have a low voltage amplitude around 3.3 V when supplied. In the driving circuit shown in FIG. 6, signals inputted from the external controller LSI, such as a clock signal, a start pulse, and a digital video signal, are subjected to voltage amplitude conversion (level conversion) in the level shifters 601 to 604 immediately after they are inputted. The input signal buffer 605 is placed near a point where the clock signal is inputted in order to prevent dulled waveform due to a large load on a clock signal line. Another measure to prevent dulled clock signal is to subject the clock signal to a level conversion in level shifters (denoted by 701 in FIG. 7) that are placed immediately before the shift registers of the respective stages.
The operation of the driving circuit will be described. Since the circuit structures shown in FIGS. 6 and 7 are identical with each other except the clock signal level conversion measures, the description on the operation will be given referring only to FIG. 6. The shift registers 606 output pulses in response to a clock signal and a start pulse and pulses of adjacent two stages are inputted to the NAND circuit 607. The NAND circuit 607 outputs a pulse obtained by logical addition of the inputted two signals and the pulse serves as a first latch pulse. The first latch pulse passes through the buffers 608 and is inputted to the latch circuit 609. In accordance with an input-timing of the first latch pulse, a latch operation of a digital video signal that has been subjected to level conversion by the level shifter 603 is carried out. After the latch operation is completed for the first stage through the last stage, a second latch pulse is inputted to an input terminal 7 during a retrace period and the digital video signals equivalent of one horizontal period which have been held in the first latch circuits 609 are all sent to the second latch circuits 610 at once. Then the signals are written in the pixel 611 and other pixels on the same row where a gate signal line (gate line) is selected, whereby an image is displayed.
FIG. 3A shows an example in which conventional level shifters are used for the level shifters 601 to 604 in FIG. 6 and for level shifters 701 to 704 in FIG. 7. In FIG. 3A, ‘In’ denotes an input signal and ‘Out’ denotes an output signal. ‘Inb’ denotes an inversion signal of the input signal and the inversion signal is generated from the In signal by an inverter or the like. In the thus structured level shifters, when the voltage amplitude of the input signals (In and Inb) is as small as 3.3 V, normal level conversion may be inhibited by the influence of the threshold of TFTs constituting the level shifters.
Then level shifters structured as shown in FIG. 3B are employed. The level shifters in FIG. 3B use a differential amplifier for level conversion, so that level conversion is performed on input signals without fail even when the input signals have a small voltage amplitude. Therefore they are very effective in reducing the drive voltage of the circuit.
However, the level shifters utilizing a differential amplifier need a constant current source 301 (Sup.) as shown in FIG. 3B so that a constant current is kept supplied during the circuit is in operation. These level shifters thus consume larger power than conventional level shifters and are disadvantageous as components mounted to mobile equipment etc. Another drawback of them is that they require a large-sized buffer to be arranged downstream. In various mobile equipment, whose popularity has surged lately, the need for smaller-sized and lighter-weight equipment has never been more pressing and to let power consumption and circuit area increase by employing a device capable of lowering drive voltage is putting the cart before the horse.