FIGS. 19(a) is a plan view of a prior art semiconductor device including a high-frequency and high-output GaAs field effect transistor (hereinafter referred to as GaAs FET), and FIG. 19(b) is a sectional view taken along line 19b--19b of FIG. 19(a). In these figures, a semiconductor device 500 comprises a die pad 500a having a surface plated with Au or the like and a GaAs FET chip 500b soldered to the surface of the die pad 500a using AuSn solder 8.
The GaAs FET chip 500b includes a GaAs substrate 1 having opposite front and rear surfaces. An n type active layer 2 is disposed within the GaAs substrate 1 reaching the front surface. Spaced apart source electrodes 3a and 3b comprising an Au-containing alloy are disposed on the front surface of the substrate 1. A drain electrode 4 comprising an Au-containing alloy and a gate electrode 5 having portions 5a and 5b are disposed on the substrate 1 so that the portions 5a and 5b of the gate electrode are interposed between the drain electrode 4 and the source electrodes 3a and 3b, respectively. Dome-shaped via-holes 6 penetrate through portions of the substrate 1 from the rear surface, opposite the respective source electrodes 3a and 3b. A back plate 7 is disposed on the rear surface of the GaAs substrate 1 and on the internal surfaces of the dome-shaped via-holes 6, partially contacting the source electrodes 3a and 3b. The back plate 7 comprises an electroplated Au layer. The GaAs FET chip 500b is mounted on the die pad 500a via AuSn solder 8. Reference numeral 9 designates a lead, numeral 10 designates an insulating ring, and numeral 11 designates a bonding wire. In this structure, the dome-shaped via-holes 6 and the back plate 7 on the internal surfaces of the via-holes 6 are for grounding the GaAs FET chip 500b and radiating heat generated in the FET chip.
FIGS. 20(a) and 20(b) are sectional views illustrating a part of the semiconductor device 500 in the vicinity of the via-hole 6 before and after the die-bonding process, respectively. In these figures, the same reference numerals as in FIGS. 19(a) and 19(b) designate the same or corresponding parts. Reference numeral 6a designates a space in the via-hole 6, and numeral 1a designates a crack produced in the GaAs substrate 1 during the die-bonding process.
In the conventional die-bonding process of a semiconductor device, AuSn solder is generally used because it has good adhesion and heat radiating properties. However, when the GaAs FET chip 500b having the via-hole 6 at the rear surface of the substrate 1 is bonded to the die pad 500a using the AuSn solder 8 which is melted by heating, the melted AuSn solder 8 enters into the space 6a of the via-hole 6 (FIG. 20(b)). When the solder 8 is cooled and hardened, a thermal stress is applied to the boundary between the solder 8 and the substrate 1 due to a difference in linear expansion coefficients between the solder and the substrate. The thermal stress causes a crack 1a in a thin part of the substrate 1 in the vicinity of the via-hole 6. This results in semiconductor devices with poor performance and reliability. In addition, the production yield is very poor.
The inventor of the present invention proposed a die-bonding method for suppressing the cracking in Published Transactions of Engineering No. 91-11870 of Japan Inventor's Society.
FIG. 21 is a sectional view schematically illustrating a part of a semiconductor device after die-bonding process for explaining the die-bonding method. In the figure, the same reference numerals as in FIGS. 20(a)-20(b) designate the same or corresponding parts. Reference numeral 3 designates an electrode pad, numeral 24 designates a plated Ni--P layer formed by electroless plating, and numeral 500c designates a semiconductor chip.
In this die-bonding method, as illustrated in FIG. 21, a part of the back plate 7 disposed on the internal surface of the via-hole 6 is covered with the electroless-plated Ni--P layer 24 which is poorly wetted by the AuSn solder. Therefore, when the semiconductor chip 500c is soldered to the die pad 500a using the AuSn solder 8, the Ni--P layer 24 prevents the AuSn solder 8 from entering in the space 6a of the via-hole 6. The electroless-plated Ni--P layer 24 is formed in the following process. That is, portions of the back plate 7 on the rear surface of the substrate 1, other than the internal surface of the via-hole 6, are masked with a resist film, followed by electroless plating.
The die-bonding method proposed by the inventor of the present invention shown in FIG. 21 significantly reduces the incidence of cracks in the vicinity of the via-hole 6, compared to the prior art die-bonding method shown in FIGS. 20(a)-20(b). However, since the electroless plating does not ensure a favorable growth of a layer on a narrow region, it is difficult to selectively grow the Ni--P layer 24 on the very narrow region of the internal surface of the via-hole 6 by electroless plating using a resist mask. In addition, resist scum produced in the photolithography for forming the resist mask adversely affects the growth of the plated film. Actually, via-holes with no Ni--P plated layers are produced at a rate of 10.about.20% in a wafer. Although this percentage is small, semiconductor devices with cracks in the vicinity of the via-hole are still manufactured in this prior art method.
Furthermore, in the die-bonding method shown in FIG. 21, since the electroless-plated Ni--P layer 24 disposed over the internal surface of the via-hole 6 prevents the AuSn solder 8 from entering into the via-hole, the large space 6a remains in the via-hole 6. However, in the above-described semiconductor device including the GaAs FET chip 500c or in a high-power GaAs MMIC (Monolithic Microwave IC) including a plurality of FETs, since the heat radiating property of the device significantly affects performance, the dimensions of the space 6a that reduces the heat radiating property must be held to the minimum of a range for preventing cracking in the semiconductor substrate. In the above-described die-bonding method of FIG. 21, however, the space 6a remaining inside the via-hole 6 is too large to secure a desired heat radiating property of the device.
Meanwhile, Japanese Published Patent Application No. Hei. 2-162735 discloses a die-bonding method similar to the method of FIG. 21. However, also in this prior art method, the heat radiating property of the device is not considered at all, and the space inside the via-hole remains as it is after the die-bonding process. Therefore, this method cannot solve the above-described problem.