1. Field of the Invention
An embodiment of the present invention is related to a stackable wafer level package and a fabricating method thereof.
2. Description of the Related Art
An increasing demand for small-sized, lightweight and high-performance electronic devices has motivated the development of small-sized, lightweight and high-performance electronic components. This motivation has led to the development of semiconductor design and manufacturing technologies and significant advances in various packaging technologies. Representative examples of such advanced packages are ball grid array (BGA) packages, flip-chip packages and chip size packages (CSPs), which are based on area array and surface mount packaging technologies. Chip size packages (CSPs) have received considerable attention due to the possibility that the size may be reduced to that of actual chips. Particularly, wafer level chip size packages (WLCSPs), which are fabricated at a wafer level, have the advantage of greatly reduced packaging cost because of an increase in the number of semiconductor chips produced from one wafer. Therefore, when WLCSP technologies are applied to the production of wafers, e.g., 300 mm wafers featuring high chip production yield per wafer, the fabrication cost of packages can be greatly reduced. In recent years, there has been an increasing interest in the development of WLCSP technologies in view of packaging cost.