1. Field of the Invention
The present invention relates to intermediate voltage generating circuits having low output impedance, and more particularly, to an intermediate voltage generating circuit for generating, based on externally supplied first and second voltages, an intermediate voltage of a level between the voltages at a predetermined output node.
2. Description of the Background Art
In a DRAM (Dynamic Random Access Memory) which is a semiconductor integrated circuit device, an intermediate voltage generating circuit is included for generating a voltage lower than an external power supply voltage V.sub.cc, for example, a voltage (1/2).V.sub.cc, which is half the external power supply voltage V.sub.cc, in order to supply a bit line precharge voltage, a cell plate voltage and the like.
FIG. 6 is a schematic diagram of a circuit showing one example of an intermediate voltage generating circuit shown in U.S. Pat. No. 4,788,455.
Referring to FIG. 6, the intermediate voltage generating circuit includes a first reference voltage generating circuit 1 for generating a first reference voltage, a second reference voltage generating circuit 2 for generating a second reference voltage, and an intermediate voltage output stage 3 for providing an intermediate voltage (1/2).V.sub.cc upon receiving these reference voltages.
First reference voltage generating circuit 1 includes resistors R1 and R2, and diode-connected N channel MOS transistors Q1 and Q2. Resistors R1, R2 and transistors Q1, Q2 are connected in series between the power supply voltage V.sub.cc and the ground GND.
Second reference voltage generating circuit 2 includes resistors R3 and R4, and diode-connected P channel MOS transistors Q3 and Q4. Resistors R3, R4 and transistors Q3, Q4 are connected in series between the power supply voltage V.sub.cc and the ground GND.
Intermediate voltage output stage 3 includes an N channel MOS transistor Q5 receiving at its gate the first reference voltage generated at a node NO1 of first reference voltage generating circuit 1, and a P channel MOS transistor Q6 receiving at its gate the second reference voltage generated at a node NO4 of second reference voltage generating circuit 2. Transistors Q5, Q6 are connected in series between the power supply voltage V.sub.cc and the ground GND.
Operations of the intermediate voltage generating circuit will now be described.
In first reference voltage generating circuit 1, when resistance values of resistors R1 and R2 are made equal to each other and characteristics of transistors Q1 and Q2 are made equal to each other, the voltage (1/2).V.sub.cc which is half the external power supply voltage V.sub.cc is generated at a node NO2. Therefore, a voltage (1/2).V.sub.cc +V.sub.THN is generated at node NO1 which is higher than the voltage (1/2).V.sub.cc of node NO2 by a threshold voltage V.sub.THN (&gt;0) of N channel MOS transistor Q1.
On the other hand, in second reference voltage generating circuit 2, when resistance values of resistors R3 and R4 are made equal to each other, and characteristics of transistors Q3 and Q4 are made equal to each other, the voltage (1/2).V.sub.cc which is half the power supply voltage V.sub.cc is generated at a node NO3, similar to the above. Therefore, a voltage (1/2).V.sub.cc -.vertline.V.sub.THP .vertline. is generated at a node NO4 which is lower than the voltage (1/2).V.sub.cc of node NO3 by an absolute value .vertline.V.sub.THP .vertline. of a threshold voltage V.sub.THP (&lt;0) of P channel MOS transistor Q4.
Resistance values of resistors R1, R2, R3 and R4 are set so large that only a little current flows in first and second reference voltage generating circuits 1 and 2.
In intermediate voltage output stage 3, the first reference voltage (1/2).V.sub.cc +V.sub.THN is applied to the gate of N channel MOS transistor Q5, so that, when an output voltage V.sub.OUT is lower than the intermediate voltage (1/2).V.sub.cc, N channel MOS transistor Q5 is turned on, whereby the output voltage V.sub.OUT is pulled up to attain the intermediate voltage (1/2).V.sub.cc. On the other hand, the second reference voltage (1/2).V.sub.cc -.vertline.V.sub.THP .vertline. is applied to the gate of P channel MOS transistor Q6, so that, when the output voltage V.sub.OUT is higher than the intermediate voltage (1/2).V.sub.cc, P channel MOS transistor Q6 is turned on, whereby the output voltage V.sub.OUT is pulled down to attain the intermediate voltage (1/2).V.sub.cc.
More specifically, when the output voltage V.sub.OUT is higher or lower than the intermediate voltage (1/2).V.sub.cc, the output voltage V.sub.OUT is pulled up or down to the intermediate voltage (1/2).V.sub.cc to finally reach the same.
In a steady state where the output voltage V.sub.OUT attains the intermediate voltage (1/2).V.sub.cc, both N channel MOS transistor Q5 and P channel MOS transistor Q6 are slightly turned off. More specifically, these transistors Q5 and Q6 are not completely but slightly in an off state. Therefore, little current flows in intermediate voltage output stage 3.
As described above, in a conventional intermediate voltage generating circuit, when the output voltage V.sub.OUT is lower or higher than the intermediate voltage (1/2).V.sub.cc, transistor Q5 or Q6 of intermediate voltage output stage 3 is turned on, causing the output voltage V.sub.OUT to be pulled up or pulled down to (1/2).V.sub.cc. In such a non-steady state, both transistors Q5 and Q6 are only slightly turned on. Therefore, when the voltage at an input node of a circuit to which the output voltage V.sub.OUT is applied fluctuates heavily, intermediate voltage output stage 3 does not supply sufficient current, making it impossible to maintain the output voltage V.sub.OUT at the intermediate voltage (1/2).V.sub.cc. In other words, there was a problem that the output impedance of the conventional intermediate voltage generating circuit is high.
As one example of the conventional intermediate voltage generating circuit having an improved response speed of a transistor in an intermediate voltage output stage, an intermediate voltage generating circuit as shown in FIG. 7 has been disclosed in IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April, 1991.
The intermediate voltage generating circuit is likely to operate as follows. In the description hereinafter, the external power supply V.sub.cc is 5 V, and the threshold voltage V.sub.THN and .vertline.V.sub.THP .vertline. of N channel and P channel MOS transistors is 1 V.
FIG. 8 is a graph showing how the output voltage V.sub.OUT and voltages of nodes NO5 and NO6 of MOS transistors M11 and M3, respectively, both configuring a push-pull output stage 4, change in accordance with the lapse of time.
Referring to FIG. 8, when the output voltage V.sub.OUT is lower than (1/2).V.sub.cc (2.5 V) (t.sub.0 to t.sub.1), an N channel MOS transistor M8 configuring a push-pull current mirror amplifier 5 is turned on, causing a current flow .DELTA.i to be produced in transistor M8. As a result, a current mirror configured of P channel MOS transistors M9 and M10 operates so that a current flow i is produced in transistor M10. Since P channel and N channel MOS transistors M1 and M12 configuring push-pull current mirror amplifier 5 is turned off at this time, N channel MOS transistor M2 is also turned off which configures a current mirror together with transistor M12. Therefore, the current flow i is entirely used for charging the gate electrode of an N channel MOS transistor M11 because there is no path to the ground.
As a result, N channel MOS transistor M11 is turned on (t.sub.1), causing the output voltage V.sub.OUT to be pulled up. In order to make it possible for N channel MOS transistor M11 to be sufficiently turned on, the voltage of a gate node NO5 of transistor M11 must be pulled up to a voltage sufficiently higher than (1/2).V.sub.cc.
As a result, even at a timing (t.sub.2) when the output voltage V.sub.OUT attains the intermediate voltage (1/2).V.sub.cc, a high voltage is still maintained at node NO5. Therefore, N channel MOS transistor M11 is maintained in an on state for a while (t.sub.2 to t.sub.3).
On the other hand, when the output voltage V.sub.OUT exceeds the intermediate voltage (1/2).V.sub.cc (t.sub.2), another P channel MOS transistor M1 and N channel MOS transistor M12 configuring push-pull current amplifier 5 are turned on, whereby N channel MOS transistor M2 configuring a current mirror together with transistor M12 is turned on. As a result, a current path is formed for discharge from node NO5. When the voltage of node NO5 is decreased to the voltage higher than the output voltage V.sub.OUT by the threshold voltage V.sub.THN of transistor M11, transistor M11 is turned off.
Ideally, a voltage V.sub.THN +.vertline.V.sub.THP .vertline. which is the sum of the threshold voltage V.sub.THN of the N channel MOS transistor and the absolute value .vertline.V.sub.THP .vertline. of the threshold voltage of the P channel MOS transistor is always maintained between node NO5 and node NO6. Therefore, when N channel MOS transistor M11 is turned off (t.sub.3), P channel MOS transistor M3 is turned on.
As described above, the output voltage V.sub.OUT converges to the intermediate voltage (1/2).V.sub.cc at timings t.sub.2, t.sub.4, t.sub.6 and t.sub.8 after it crosses over the boundary, once at least, of the intermediate voltage (1/2).V.sub.cc.
Accordingly, it is considered that the intermediate voltage generating circuit has at least three problems as in the following.
A first problem is occurrence of overshoot or undershoot. Transistors M11 and M3 configuring push-pull output stage 4 are controlled by supply of charge to the gate electrodes. Therefore, even at a timing when transistor M11 or M3 may not be turned on, the charge stored at the gate electrodes is not immediately discharged, whereby overshoot or undershoot never fails to occur.
A second problem is occurrence of oscillation. Since the intermediate voltage generating circuit easily oscillates, it is necessary to appropriately specify the size of each transistor to prevent the same from oscillating.
A third problem is high output impedance. In the intermediate voltage generating circuit, since transistors M11 and M3 configuring push-pull output stage 4 are only slightly turned on in a non-steady state, the output impedance is high.