1. Field of the Invention
This invention is related to the field of digital communications and, more particularly, to error detection in a First-In-First-Out (FIFO) buffer.
2. Description of the Related Art
Digital electronics frequently require the communication of data between systems (or components thereof) of varying clock frequencies. In such a case, one system may have the ability to transmit data at a faster rate than another system is capable of receiving and processing. Also, various components may have clocks which originate from different sources or clock domains. Such clock signals may have the same frequencies, but have phase differences. In order to compensate for a disparity in transmission rates between sender and receiver, First-In-First-Out (FIFO) buffers are frequently used. A FIFO is a memory buffer which may store data and returns that stored data in the same order in which it was received. A FIFO typically comprises a fixed number of memory storage locations and circuitry for selecting read and write locations. By storing received data in a FIFO, a slower system may receive data at a rate which is higher than the rate at which it can process data, or data may be synchronized between different clock domains.
As is well known, because spikes, transients, glitches and other noise may exist within an electrical system, circuitry which reads from and writes to a FIFO may operate incorrectly. Consequently, a write to a full FIFO or a read from an empty FIFO may occur. Alternately, data may be read from or written to a wrong location in a FIFO. As a result, data which is assumed to be correct, but is actually erroneous, may be read from the FIFO.
The problems outlined above are in large part solved by a FIFO and method as described herein. Additional circuitry is included which enables a read from a FIFO to compare a value stored with the data to an expected value. When a mismatch between the stored value and expected value occurs, an error is detected. Advantageously, greater confidence may be had in the data which is read from a FIFO and the incidence of the transmission of erroneous data may be reduced.
Broadly speaking, a FIFO is contemplated. The FIFO includes a number of locations for storing data, each having an associated verification bit. Upon initialization, the verification bits are set to an alternating sequence of binary values. Also included is write circuitry which may write data to an entry of the FIFO. When data is written to an entry in the FIFO, the verification bit associated with that entry is toggled.
Also contemplated is a method. The method includes initializing a number of verification bits to an alternating sequence of binary values, where each verification bit corresponds to a storage location in a FIFO. Data may be written to a storage location of the FIFO and the corresponding verification bit toggled in response to that write.
Also contemplated is a FIFO which includes a number of verification bits and read circuitry. Each of the verification bits corresponds to a storage location. The read circuitry may read data from a storage location and the verification bit which corresponds to that storage location. The read circuitry includes an expected value bit which is compared to the verification bit on reads of data from the FIFO. Based on this comparison, errors may be detected. In addition, the expected value bit is toggled in response to reads. Though in the case where the FIFO has an even number of locations and it is the last entry which is read from the FIFO, the expected value is not toggled.
Finally, a method of error detection in a FIFO is contemplated. The method includes reading data and a corresponding verification bit from the FIFO, detecting an error in the FIFO by comparing the verification bit to an expected value bit, and toggling the expected value bit in response to a read and a first condition.