1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device including a floating gate electrode and a control gate electrode.
2. Description of the Related Art
NAND flash memories are typical as a large-capacity high-density nonvolatile semiconductor memory device. A memory cell structure of the NAND flash memory device employs a self-alignment shallow trench isolation (STI) structure which provides highest density integration. In the STI structure, for example, an element isolation trench is formed in a silicon substrate. An insulating film such as a silicon oxide film is buried in the trench. The insulating film serves as an element isolation insulating material.
A channel region on the silicon substrate is isolated by an element isolation region of the STI structure. A tunnel insulating film is formed on an entire channel region. The tunnel insulating film is rendered as thin as possible so that a tunnel current can flow therethrough. A floating gate electrode is formed on the tunnel insulating film. The floating gate electrode serves as a charge accumulation layer. The floating gate electrode has a side end with the same width as the element forming region. The element isolation insulating film is in contact with the floating gate electrode. A part of the floating gate electrode projects so as to be located higher than an upper surface of the element isolation insulating film. An upper surface of the floating gate electrode faces the control gate electrode with an intergate insulating film being interposed therebetween. A vertical profile control is applied to the control gate electrode and the floating gate electrode so that side ends of the electrodes are trued up in a self-alignment manner. An n-type diffusion layer is formed in a surface layer of the silicon substrate located between the adjacent gate electrodes.
In the above-described structure, the trench is formed and the element isolation insulating film is buried in the trench after films for the floating gate electrode have been deposited. Accordingly, an end of the gate electrode is not exposed. Furthermore, since the floating gate electrode is completely isolated in the element isolation region, the floating gate electrode need not be cut into a slit-like shape on the element isolation region. As a result, widths of an element region and an element isolation region can be refined up to minimum rules. On the other hand, in order that a capacity between the floating gate electrode and the control gate electrode may be increased, the floating gate electrode is structure to face the control gate electrode on a side of a charge accumulation layer.
The memory cell of the above-described structure has no structure more refined than periodic widths of the channel region and the element isolation region. Accordingly, highest density integration can be realized. However, since a coupling ratio of the memory cell depends upon an exposed height of the floating gate electrode, exposed height variations due to process variation result in an increase in characteristic variations. In particular, since variations in the coupling ratio causes fluctuations in writing voltage, a threshold distribution is spread. This is disadvantageous both in high-speed operation and in reliability of the semiconductor device. A parasitic capacity between floating gate electrodes of adjacent memory cells cannot be ignored as a cause for characteristic variations with progress of refinement. The above-described structure includes a region opposed to the floating gate electrode with the element isolation insulating film being interposed therebetween. This results in occurrence of parasitic capacity, whereupon an amount of discharge accumulated in the floating gate electrodes of the adjacent memory cells. As a result, the threshold distribution setting cannot be provided with a sufficient margin for a charge retention characteristic.
In view of the above-described problem, publication JP-A-H08-125148 discloses a structure which can overcome the above-described problem of variations in the coupling ratio. More specifically, the publication employs a side wall transfer transistor (SWATT) structure. In the disclosed SWATT structure, an element isolation insulating film is located lower than an upper surface of a silicon substrate. A floating gate electrode has all sidewalls opposed to a control gate electrode with a gate insulating film being interposed therebetween. Consequently, an entire sidewall height of the floating gate electrode contributes to the coupling ratio, whereupon fluctuations in the coupling ratio can be suppressed.
However, the insulating film sandwiched between the silicon substrate and the control gate electrode is an intergate insulating film. Accordingly, when a writing voltage is applied to the control gate, the writing voltage of, for example, 20 V is also applied to an intergate insulating film. As a result, an insulation breakdown occurs in the intergate insulating film, resulting in breakdown of the element or device.
As obvious from the foregoing, the conventional memory cell with the self-alignment STI structure is devoid of means that can improve the coupling ratio and suppress variations in the coupling ratio, and can ensure the breakdown voltage of the memory cell. As a result, the conventional memory cell cannot achieve both high reliability and high densification.