This invention generally relates to floating gate semiconductor devices, and is specifically concerned with a floating gate photosensor operable in either an enhanced sensitivity mode or an enhanced transit speed mode.
Floating gate photosensors are known in the prior art. Generally, such photosensors are made up of three contiguous sections: a light gathering section where light impinging on the device is converted into photocharges which generate a signal current, a floating gate section which senses variations in the current of the photocharges, and a drain section which serves as a signal charge collection point. Structurally, these sensors are made up of photosensitive semiconductor material with an n-type (or p-type) buried channel over an opposite type substrate. The purpose of the buried channel is to provide a subsurface flow path for the signal charge. The depth of the channel is determined by the relative concentration of the n and p regions and the junction depth of the buried channel. The principal advantage of such a photosensor is its ability to detect a signal charge without destroying it, thereby leaving the signal charge intact for further processing.
While the foregoing device has proven to be satisfactory in many respects, the applicants have noted two major limitations in its design that impairs its overall usefulness. The first limitation arises from the fact that two important operating parameters, the responsivity and the signal transmit time (or equivalently, the bandwidth) are determined by the depth of the buried channel which is fixed at the time of manufacturing. Moreover, the device may have either a high responsivity or a high bandwidth (or low signal transit time), but not both as a high responsivity is achieved by having the signal flow channel close to the surface while a short signal transit time is achieved by having the signal flow channel far from the surface. Hence, it is difficult for a single photosensor device of this type to perform well in an environment where the light signals vary greatly in amplitude. If the light signals fall below a certain level of amplitude, then the voltage sensitivity of the device may not be adequate to process the resulting signal charge. Of course, such a device could be replaced with a photosensor whose flow channel was closer to the surface of the n-type outer region. However, the increase in voltage sensitivity would come at a price of an increase in the transit time required for the photocharges to traverse the n-type region before they enter the drain. Consequently, such a device would . operate unnecessarily slowly to process light beam signals carried over relatively strong light beam intensities. A second limitation that the applicants have observed is that there have been, generally, two choices in the methods of constructing the resistive and floating gates, either of which had shortcomings. In the first method, one could use a single level to define the gate material. This meant that in order to isolate the resistive gate from the floating gate, a gap of several microns had to be inserted between the gates. This creates a potential pocket or well in the channel for signal charge flow which in turn, retards the response time of the detector at low signal levels. In the second method, a two level polysilicon process is used to define the gates. This allows one to overlap the gates and avoid the problem of an intergate potential pocket, while isolating the gates electrically. Unfortunately, such overlapping of the gates has been found to introduce an unacceptably large overlap capacitance between the gates. Moreover, using a two level polysilicon process increases the complexity of processing and decreases the processing yield.
Clearly, there is a need for a photosensor which may be operated in either a voltage sensitive mode or a low transit time mode so as to be able to optimally process signals carried over light beams of broadly varying intensities. Moreover, it would be desirable if such a photosensor had a means for eliminating the charge flow retarding potential well that exists between the resistive gate and the floating gate in prior art structures without the addition of unwanted capacitances.