The present invention generally relates to semiconductor devices and more particularly to a high-dielectric capacitor, a semiconductor having such a high-dielectric capacitor, and a fabrication process thereof.
With the advancement in the art of device miniaturization, the integration density of semiconductor integrated circuits, in which a number of semiconductor devices are integrated on a common substrate, is increasing every year. With this, device miniaturization is going on also for the individual semiconductor devices and the operational speed of the semiconductor devices is increasing also. In the case of memory semiconductor devices having a capacitor such as a DRAM, the device miniaturization also brings forth an increase of the amount of information stored in the memory semiconductor device.
On the other hand, in the semiconductor memory device such as a DRAM which store information in a memory cell capacitor in the form of electric charges, it should be noted that excessive device miniaturization causes a decrease in the electric charges held in the memory cell capacitor due to the decrease of the memory cell capacitance. Thereby, stable retention of information tends to become difficult. While it is possible to compensate for such a decrease of the capacitance to some extent by reducing the thickness of the capacitor insulation film, it is necessary to reduce the thickness of the capacitor insulation film to the order of several nanometers or less in the DRAMs of sub-micron or sub-quarter micron size, as long as a conventional SiO.sub.2 film or an SiN film is used for the capacitor insulation film. As will be easily understood, formation of such an extremely thin capacitor insulation film is difficult, as it is required in a capacitor that the capacitor insulation film is perfectly free from defects such as pin holes. Further, the use of such a thin capacitor insulation film tends to cause the problem of increased tunneling leakage current.
Meanwhile, it has been proposed to use a Ta.sub.2 O.sub.5 film for the capacitor insulation film of a DRAM memory cell capacitor.
FIGS. 1A-1D show the fabrication process of a MIS capacitor that uses a conventional Ta.sub.2 O.sub.5 capacitor insulation film.
Referring to FIG. 1A, a capacitor region is defined on a Si substrate 11 by a field oxide film 12, and a polysilicon pattern 13 and an SiN pattern 14 are formed on the foregoing capacitor region in the step of FIG. 1B by depositing a polysilicon film and an SiN film consecutively and further by applying a patterning process, wherein the polysilicon pattern 13 forms a lower electrode of the capacitor. Typically, the SiN pattern 14 is formed with a thickness of 2 nm.
Next, in the step of FIG. 1C, a Ta.sub.2 O.sub.5 film is deposited on the structure of FIG. 1B typically with a thickness of about 8 nm, followed by a patterning process to form a Ta.sub.2 O.sub.5 capacitor insulation film 15. Further, the step FIG. 1D is conducted in which an upper electrode pattern 16 of Pt, and the like, is formed on the capacitor insulation film 15.
Because Ta.sub.2 O.sub.5 is a simple oxide, it is possible to form the Ta.sub.2 O.sub.5 capacitor insulation film 15 stably and with reliability in the step of FIG. 1C by a sputtering process or a CVD process. On the other hand, it is known that the bulk crystal of Ta.sub.2 O.sub.5 has a dielectric constant of 30-40, and this value of dielectric constant is obtained also in the case of a Ta.sub.2 O.sub.5 film. It should be noted that the foregoing dielectric constant is, while larger than the dielectric constant of SiO.sub.2 or SiN, distinctly smaller than that of a perovskite complex oxide such as PZT (Pb(Zr,Ti)O.sub.3) or STO (SrTiO.sub.3) by a factor of 10.
Thus, if a method is found to realize a large dielectric constant in a Ta.sub.2 O.sub.5 film, which is a simple oxide film, with a magnitude of the dielectric constant comparable to the dielectric constant of a perovskite complex oxide, the fabrication process of a large-capacitance memory cell capacitor would become substantially simplified and the cost of the semiconductor memory device using such a memory cell capacitor would be reduced.