The invention relates to semiconductor device fabrication and, more particularly, to techniques for enhancing the performance of bipolar devices.
A bipolar device is a semiconductor device, the operation of which is based on the use of both majority and minority carriers (also referred to as “charge carriers”). The majority and minority carriers are either electrons or holes, depending on the polarity of the device.
An example of a bipolar device is the bipolar junction transistor (BJT) which is a transistor having three semiconductor regions referred to as emitter, base and collector. The emitter is a very high conductivity region which acts as a source of free carriers which are injected into the adjacent base region. The collector is a region which collects carriers from the base. The base region is sandwiched between the emitter and collector regions and generally controls the flow of free carriers between the emitter and the collector. A lesser flow of carriers of opposite polarity to those flowing from emitter to collector flows from the base to the emitter.
A conventional BJT is fabricated using one semiconductor material (Si) with differently doped regions. A heterojunction bipolar transistor (HBT) utilizes more than one semiconductor material, taking advantage of the different properties (e.g., bandgap) of the different materials—for example, SiGe in combination with Si. The additional (other than Si) material is formed as an epitaxial layer, typically using MBE (molecular beam epitaxy), RTCVD (rapid-thermal chemical vapor deposition), or LPCVD (low-pressure chemical vapor deposition) techniques.
A bipolar transistor comprises an emitter layer (or region) containing an impurity of a first conductivity type, a base layer (or region) containing an impurity of a second conductivity type, and a collector layer (or region) containing the impurity of the first conductivity type.
Bipolar transistors are typically of two distinct types, or polarity—either n-p-n (having n-type emitter and collector, and having p-type base), or p-n-p (having p-type emitter and collector, and having n-type base).
The “type” (p or n) is determined by impurities which are implanted or deposited during epitaxy into the semiconductor material. The impurity for p-type is boron (B) and for n-type, phosphorous (P), arsenic (As), antimony (Sb).
For a n-p-n type bipolar transistor, the free carriers injected from the emitter are electrons, and the carriers flowing from the base to emitter are holes. For a p-n-p type bipolar transistor, carrier types are the opposite. Often, electrons are preferred as the majority charge carriers rather than holes, since for carrier mobility (μ) μn>μp, and for saturation velocity (v) vn>vp. Hence, n-type bipolar devices are typically preferred, where possible.
FIG. 1 illustrates, generally, an n-p-n type BJT of the prior art comprising a neutral emitter, a neutral collector, and a neutral base disposed between the neutral emitter and neutral collector, illustrating the path of electrons from neutral emitter to neutral collector, via the base, and illustrating the path of holes from the neutral base to the neutral emitter. An emitter-base space charge layer (region) is formed between the neutral emitter and the neutral base. A base-collector space charge layer (region) is formed between the neutral base and the neutral collector. (For a p-n-p polarity BJT holes traverse between neutral emitter and neutral collector and electrons traverse between neutral base to neutral emitter.
Lattice strain is known to affect carrier mobility and saturation velocity. Various methods have been shown to cause strain in field effect transistors (FETs). For instance, films which cause tensile strain in the direction of current flow (and sometimes in the direction perpendicular to the direction of current flow) can improve the electron mobility and saturation velocity in FETs. It should be understood that FETs operate fundamentally differently than BJTs. For one thing, there is charge flow in only one direction, which is parallel to the wafer surface. In addition, FETs have a single carrier (electrons for NFET and holes for PFET), and so the application of lattice strain is straightforward to create strain in principally one direction for the single carrier type.
Some examples of employing strain techniques in FETs can be found in the following articles:
“A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors”, T. Ghani et al., Portland Technology Development, Intel Corp., Hillsboro, Oreg., 0-7803-7873 3/03 (c) 2003, IEEE describes the details of a strained transistor architecture which is incorporated into a 90 nm logic technology on 300 mm wafers.
The strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions. Dramatic performance enhancement relative to unstrained devices is reported. Ghani FIG. 1 shows a PMOS transistor with a strained epitaxial SiGe film embedded into the source drain region to induce compressive strain in the channel region.
“Enhanced Hole Mobilities in Surface-channel Strained-Si p-MOSFETs”, K. Rim et al, Solid State Electronics Laboratory, Stanford University, Stanford, Calif. 94305, 0-7803-2700-4, (c) 1995, IEEE describes the strain dependence of the hole mobility in surface-channel p-MOSFETs employing pseudomorphic, strained-Si layers. The hole mobility enhancement is observed to increase roughly linearly with the strain as the Ge content in the relaxed Sil-xGex buffer layer increases.
“Fabrication and Mobility Characteristics of Ultra-thin Strained Si Directly on Insulator (SSDOI) MOSFETs”, K. Rim et al, T. J. Watson Research Center, Yorktown Heights, N.Y. 10598 0-7803-7873 3/03, IEEE discloses a tensile-strained Si layer transferred to form an ultra-thin (<20 nm) strained Si directly on insulator (SSDOI) structure. MOSFETs were fabricated, and electron and hole mobility enhancements were demonstrated on strained Si directly on insulator structures with no SiGe layer present under the strained Si channel.