Peripheral Component Interconnect (PCI) architecture is currently used to provide primary input/output (I/O) functionality in most classes of computers and servers. In addition, a PCI bus, which enables most I/O functionality, is one of the most widely utilized interconnects. In fact, the PCI bus still proves viable for most desktop computer functions. It should be noted that the term “computer” used herein refers to devices containing a processor and memory.
Unfortunately, devices using a standard PCI bus architecture may be quite limited in performance and reliability. A standard PCI bus architecture requires that devices connected to the PCI bus share a finite amount of bandwidth. In addition, as additional devices and/or ports are added to the PCI bus, the overall bandwidth afforded to each device proportionally decreases. Currently, multiple parallel signal routes are added at the PCI bus topology level to enable additional devices to share the PCI bus. The negative effect produced by the addition of parallel signal routes is a large I/O pin count that is required to enable proper device operation. Still further, servers are approaching and surpassing upper bandwidth limits of shared bus architectures, such as the PCI bus.
To address the limitations associated with PCI architecture, InfiniBand architecture (IBA) was introduced. The IBA defines a switched communications fabric allowing multiple devices to concurrently communicate with high bandwidth and low latency in a protected and remotely managed environment. FIG. 1 is a block diagram illustrating a prior art IBA network 102. Four end nodes 104, 106, 108, 112 and an IBA fabric 114 are located within the IBA network 102. As known by those of ordinary skill in the art, an end node may represent a number of different devices, examples of which include, a processor end node, a router to a network, or an I/O device, such as a redundant array of independent disks (RAID) subsystem. The IBA fabric 114 comprises logical devices that utilize the IBA for communication.
The IBA network 102 may be subdivided into sub-networks, also referred to as subnets, that are interconnected by routers. Within the IBA network 102, end nodes may connect to a single subnet or multiple subnets. FIG. 2 is a block diagram illustrating a prior art subnet 122. The IBA subnet 122 of FIG. 2 contains end nodes 124, 126, 128, 132, switches 134, 136, 138, 142, 144, a router 146 and a subnet manager 148. Multiple links can exist between any two devices within the IBA subnet 122, an example of which is shown by connections between the router 146 and switch 144.
The switches 134, 136, 138, 142, 144 connect the end nodes 124, 126, 128, 132 for communication purposes. Each connection between an end node 124, 126, 128, 132 and a switch 134, 136, 138, 142, 144 is a point-to-point serial connection. Since the connections are serial, four separate connections are required to connect the end nodes 124, 126, 128, 132 to switches 134, 136, 138, as opposed to the requirement of a wide parallel connection used within a PCI bus. It should be noted that more than four separate connections are shown by FIG. 2 to provide examples of different connections within the IBA subnet. In addition, since each point-to-point connection is dedicated to two devices, such as an end node 124, 126, 128, 132 and a switch 134, 136, 138, 142, 144, the full bandwidth capacity of each connection is made available for communication between the two devices. This dedication eliminates contention for a bus, as well as delays that result from heavy loading conditions on a shared bus architecture.
The switches 134, 136, 138, 142, 144 transmit packets of data based upon a destination address, wherein the destination address is located in a local route header of a data packet. However, the switches 134, 136, 138, 142, 144 are not directly addressed in the traversal of packets within the IBA subnet 122. Instead, packets traverse switches 134, 136, 138, 142, 144 virtually unchanged. To this end, each destination within the IBA subnet 122 is typically configured with one or more unique local identifiers, which represent a path through a switch 134, 136, 138, 142, 144. Data packet forwarding by a switch 134, 136, 138, 142, 144 is typically defined by forwarding tables located within each switch 134, 136, 138, 142, 144, wherein the table in each switch is configured by the subnet manager 148. Each data packet contains a destination address that specifies the local identifier for reaching a destination. When individual data packets are received by a switch 134, 136, 138, 142, 144, the data packets are forwarded within the switch 134, 136, 138, 142, 144 to an outbound port or ports based on the destination local identifier and the forwarding table located within the switch 134, 136, 138, 142, 144.
The router 146 forwards packets based on a global route header located within the packet, and replaces the local route header of the packet as the packet passes from subnet to subnet. While intra-subnet routing is provided by the switches 134, 136, 138, 142, 144, the router 146 is the fundamental routing component for inter-subnet routing. Therefore, routers interconnect subnets by relaying packets between the subnets until the packets arrive at a destination subnet.
As additional devices, such as end nodes, are added to a subnet, additional switches are normally required to handle additional packet transmission within the subnet. However, it would be beneficial if additional switches were not required with the addition of end nodes, thereby reducing the expenditure of resources associated with the purchase of additional switches.