1. Field of the Invention
The present invention relates to a reference voltage generator, which provides a reference voltage, for example, an intermediate voltage of a power source voltage as a reference voltage.
2. Description of the Related Art
With lowering of power source voltage of semiconductor integrated circuits proceeding year by year, semiconductor integrated circuits used for portable information terminal devices are required to operate at a low power source voltage of for example 1.5V or less. On the other hand, as for non-portable/fixed machine, operating at a power source voltage of approximately 3.3V is desired, because of the easiness of parts at a low power source voltage inside the devices to communicate through an interface with other IC""s.
In recent years, low voltage differential signaling (LVDS) was developed as one of the high-speed digital signal transmission technologies. Although drivers and receivers used for LVDS are achieved with analogue circuits, functionally they are operating as digital circuits for processing digital signals. In such analogue circuits, when built in semiconductor integrated circuits, it is desirable to operate properly as the other digital circuits, for example, even if the operation speed becomes slower when the power source voltage is different by two times and more.
It is necessary to provide an intermediate voltage of the power source voltage as a reference voltage to transfer a digital signal by using LVDS. Up until now, various configuration examples of reference voltage generators for generating the intermediate voltage of the power source voltage have been proposed. For example, reference voltage generators are disclosed in each of the following patent document xe2x80x9cJP. Pat. Publication No. S56-108258xe2x80x9d, xe2x80x9cJP. Pat. Publication No. H10-63361xe2x80x9d and xe2x80x9cJP. Pat. Publication No. 2000-56846xe2x80x9d.
FIGS. 22 to 24 show circuit examples of the reference voltage generator disclosed in the above patent document.
FIG. 22 shows an example of the configuration of a reference voltage generator disclosed in xe2x80x9cJP. Pat. Publication No. S56-108258xe2x80x9d. As illustrated in FIG. 22, in this example, a reference voltage generator is constituted by diodes formed by MOS transistors connected in series between the supply line of the power source voltage Vdd and the common electric potential VSS.
FIG. 23 shows another example of the configuration of a reference voltage generator disclosed in xe2x80x9cJP. Pat. Publication No. H10-63361xe2x80x9d. As illustrated in FIG. 23, in this reference voltage generator, diodes, diodes constituted by MOS transistors, and voltage dividing resisters are provided, and the intermediate voltage Vref1 of the power source voltage Vdd is generated by the voltage dividing circuit constituted by these circuit elements. Furthermore, a high reference voltage Vref2, which is higher in level than the intermediate voltage Vref1, is generated by the voltage dividing resisters.
Furthermore, FIG. 24 shows another example of the configuration of a reference voltage generator disclosed in xe2x80x9cJP. Pat. Publication No. 2000-56846xe2x80x9d. As illustrated in FIG. 24, in this example, diodes constituted by MOS transistors are connected in parallel, to constitute a voltage dividing circuit, whereby the intermediate voltage Vref of the power source voltage Vdd is generated by the voltage dividing circuit.
FIG. 25 shows a most general reference voltage generator constituted by voltage dividing resisters. Generally, in a semiconductor integrated circuit manufactured by a process without high resistance that may be microscopically processed, a very large layout area is necessary for a Vdd/2 voltage generator constituted by resisters. On the other hand, a layout area which is only several tenths of that of the case constituted by resisters is sufficient to an intermediate voltage generator using diodes constituted by MOS transistors.
However, in the reference voltage generator using diodes constituted of the MOS transistors described above, as a power source voltage for operation, a power source voltage Vdd (Vddxe2x89xa72Vth) that is twice of the threshold voltage Vth of the MOS transistors or higher is necessary.
Therefore, it is able to operate without any problem at a power source voltage that is equal to 1.5V or higher, near 3.3V. However, when there is a demand to operate at a low power source voltage of, for example, a low power source voltage equal to or less than 1.5V, the minimum value of the power source voltage Vdd will be Vdd≈2Vth in a poor condition such as a low temperature, and when the driving current becomes equal to or lower than several hundreds of nA, it suffers from a disadvantage that a stable reference voltage can not be supplied any more. Inversely, when the circuit is designed to operate at a low power source voltage that is 1.5V or higher, while maintaining a driving current of several xcexcA, a current of several mA passes through the MOS diodes at the power source voltage near 3.3V, so there is a disadvantage that the power consumption grows very large.
As shown in FIG. 25, in the reference voltage generator constituted by the resistors, although there is no problem of the driving current increasing when the power source voltage is near 3.3V, there is a disadvantage that the layout area becomes large to form resistance elements on the substrate.
The present invention was made in consideration with the circumstance and an object thereof is to provide a reference voltage generator capable of stable operating at a low power source voltage, and supplying a stable reference voltage while suppressing the increase of the power consumption at a high power source voltage, and capable of suppressing the increase in the layout area in minimum.
To attain the above objects, according to the present invention, there is provided a reference voltage generator comprising a first MOS transistor and a first resistance element connected in series between a first power supply line and an output terminal; a second MOS transistor having a same conductivity type as the first MOS transistor, a second resistance element, and a third MOS transistor having a different conductivity type from the first MOS transistor connected in series between the output terminal and a second power supply line, wherein the third MOS transistor has a first threshold voltage, and the first and second MOS transistors have a second threshold voltage which has a lower absolute value than that of the first threshold voltage, and an intermediate voltage of the first power supply and the second power supply line is output from the output terminal.
Preferably, in the present invention, a source and a channel forming region of the first MOS transistor are connected to the first power supply line, a source and a channel forming region of the second MOS transistor are connected to the output terminal, and a source and a channel forming region of the third MOS transistor are connected to the second power supply line.
Preferably, in the present invention, a gate of the first MOS transistor is connected to the output terminal, and a voltage of the first power supply line is supplied thereto during standby, a voltage of the second power supply line is supplied to a gate of the second MOS transistor during operation, and the voltage of the first power supply line is supplied thereto during standby, and the voltage of the first power supply line is supplied to a gate of the third MOS transistor during operation, and the voltage of the second power supply line is supplied thereto during standby.
Preferably, in the present invention, a voltage of the output terminal is supplied to a gate of the first MOS transistor during operation and the voltage of the second power supply line is supplied thereto during standby, the voltage of the second power supply line is supplied to a gate of the second MOS transistor during operation and the voltage of the first power supply line is supplied thereto during standby, and the voltage of the first power supply line is supplied to a gate of the third MOS transistor during operation and the voltage of the second power supply line is supplied thereto during standby.
Preferably, in the present invention, the gate of the first MOS transistor is connected to the drain thereof, the drain voltage of the second MOS transistor is supplied to the gate of the second MOS transistor during operation and the voltage of the first power supply line is supplied thereto during standby, the voltage of the first power supply line is supplied to the gate of the third MOS transistor during operation and the voltage of the second power supply line is supplied thereto during standby, and the output terminal is connected to the first power supplied line during standby.
Preferably, in the present invention, a drain voltage of the first MOS transistor is supplied to the gate thereof during operation and the voltage of the second power supply line is supplied thereto during standby, a drain voltage of the second MOS transistor is supplied to the gate thereof during operation and the voltage of the first power supply line is supplied thereto during standby, and the voltage of the first power supply line is supplied to the gate of the third MOS transistor during operation, and the voltage of the second power supply line is supplied thereto during standby.
Furthermore, according to the present invention, there is provided a voltage generator comprising a first MOS transistor, a first resistance element, and a second resistance element connected in series between a first power supply line and an output terminal; a second MOS transistor having a same conductivity type as the first MOS transistor, a third resistance element, a fourth resistance element, and a third MOS transistor having a different conductivity type from the first MOS transistor connected in series between the output terminal and a second power supply line; wherein the third MOS transistor has a first threshold voltage, and the first and second MOS transistors have a second threshold voltage which has a lower absolute value than that of the first threshold voltage, and an intermediate voltage of the first power supply line and the second power supply line is output from the output terminal.
Preferably, in the present invention, the source and the channel forming region of the first MOS transistor are connected to the first power supply line, the source and the channel forming region of the second MOS transistor are connected to the output terminal, and the source and the channel forming region of the third MOS transistor are connected to the second power supply line.
Preferably, in the present invention, the gate of the first MOS transistor is connected to the connection point of the first resistance element and the second resistance element, the voltage of the connection point of the third resistance element and the fourth resistance element is supplied to the gate of the second MOS transistor during operation and the voltage of the first power supply line is supplied thereto during standby, the voltage of the first power supply line is supplied to the gate of the third MOS transistor during operation and the voltage of the second power supply line is supplied thereto during standby, and the output terminal is connected to the first power supplied line during standby.
Preferably, in the present invention, the voltage of the connection point of the first resistance element and the second resistance element is supplied to the gate of the first MOS transistor during operation and the voltage of the second power supply line is supplied thereto during standby, the voltage of the connection point of the third resistance element and the fourth resistance element is supplied to the gate of the second MOS transistor during operation and the voltage of the first power supply line is supplied thereto during standby, the voltage of the first power supply line is supplied to the gate of the third MOS transistor during operation and the voltage of the second power supply line is supplied thereto during standby.
Furthermore, according to the present invention, there is provided a reference voltage generator comprising a first MOS transistor and a second MOS transistor having a same conductivity type, and a first resistance element connected in series between a first power supply line and an output terminal; a third MOS transistor having a same conductivity type as the first MOS transistor, a second resistance element, and a fourth MOS transistor having a different conductivity type from the first MOS transistor connected in series between the output terminal and a second power supply line; wherein the first and the fourth MOS transistors have first threshold voltages of approximately equivalent absolute values, and the second and the third MOS transistors have a second threshold voltage which has a lower absolute value than that of the first threshold voltage, and an intermediate voltage of the first power supply line and the second power supply line is output from the output terminal.
Preferably, in the present invention, the source and the channel forming region of the first MOS transistor are connected to the first power supply line, the source of the second MOS transistor is connected to the drain of the first MOS transistor, and the channel forming region of the second MOS transistor is connected to the first power supply line, the source and the channel forming region of the third MOS transistor are connected to the output terminal, and the source and the channel forming region of the fourth MOS transistor are connected to the second power supply line.
Preferably, in the present invention, the voltage of the second power supply line is supplied to the gate of the first MOS transistor, the gate of the second MOS transistor is connected to the output terminal, the voltage of the first power supply line is supplied to the gate of the second MOS transistor during operation, the voltage of the second power supply line is supplied to the gate of the third MOS transistor during operation and the voltage of the first power supply line is supplied thereto during standby, and the voltage of the first power supply line is supplied to the gate of the fourth MOS transistor during operation and the voltage of the second power supply line is supplied thereto during standby.
Furthermore, according to the present invention, there is provided a reference voltage generator comprising a first MOS transistor of a first conductivity type, a second MOS transistor of the same first conductivity type, and a first resistance element connected in series between a first power supply line and an output terminal; a third MOS transistor of the first conductivity type, a second resistance element, and a fourth MOS transistor of a second conductivity type different from that of the first MOS transistor connected in series between the output terminal and a second power supply line; a fifth MOS transistor of the first conductivity type, a third resistance element, and a sixth MOS transistor of the second conductivity type connected in series between the first power supply line and the output terminal; a fourth resistance element, a seventh MOS transistor of the second conductivity type, and an eighth MOS transistor of the second conductivity connected in series between the output terminal and the second power supply line, wherein the first, the fourth, the fifth and the eighth MOS transistors have first threshold voltages of approximately equivalent absolute values, and the second, the third, the sixth and the seventh MOS transistors have a second threshold voltage which has a lower absolute value than that of the first threshold voltage, and an intermediate voltage of the first power supply line and the second power supply line is output from the output terminal.
Preferably, in the present invention, the voltage of the output terminal is supplied to the gate of the second MOS transistor, the voltage of the second power supply line is supplied to the gate of the third MOS transistor, the voltage of the first power supply line is supplied to the gate of the sixth MOS transistor and the voltage of the output terminal is supplied to the gate of the seventh MOS transistor.
Further, in the present invention, preferably, the voltage of the second power supply line is supplied to the gate of the first and the fifth MOS transistors during operation and the voltage of the first power supply line is supplied thereto during standby, and the voltage of the first power supply line is supplied to the gate of the fourth and the eighth MOS transistors during operation and the voltage of the second power supply line is supplied thereto during standby.
Furthermore, according to the present invention, there is provided a reference voltage generator comprising a first MOS transistor of a first conductivity type, a second MOS transistor of the same first conductivity type, and a first resistance element connected in series between a first power supply line and an output terminal; a third MOS transistor of the first conductivity type, a second resistance element, and a fourth MOS transistor of a second conductivity type different from that of the first MOS transistor connected in series between the output terminal and a second power supply line; a third resistance element and a fifth MOS transistor of the second conductivity type connected in series between the connection point of the first MOS transistor and the second MOS transistor and the output terminal; a fourth resistance element and a sixth MOS transistor of the second conductivity type connected in series between the output terminal and the connection point of the second resistance element and the fourth MOS transistor, wherein the first and the fourth MOS transistors have first threshold voltages of approximately equivalent absolute values, the second, the third, the fifth and the sixth MOS transistors have a second threshold voltage which has a lower absolute value than that of the first threshold voltage, and an intermediate voltage of the first power supply line and the second power supply line is output from the output terminal.
Preferably, in the present invention, the voltage of the output terminal is supplied to the gate of the second MOS transistor, the voltage of the second power supply line is supplied to the gate of the third MOS transistor, the voltage of the first power supply line is supplied to the gate of the fifth MOS transistor and the voltage of the output terminal is supplied to the gate of the sixth MOS transistor.
Preferably, in the present invention, the voltage of the second power supply line is supplied to the gate of the first MOS transistor during operation and the voltage of the first power supply line is supplied thereto during standby, and the voltage of the first power supply line is supplied to the gate of the fourth MOS transistor during operation and the voltage of the second power supply line is supplied thereto during standby.