Super twisted pneumatic (STN) liquid crystal displays are passive matrix LCD displays which are substantially less expensive to produce than comparably sized active matrix LCD displays, such as thin film transistor (TFT) LCD displays. As a result, STN displays have significant appeal to the makers of low and medium priced laptop and notebook personal computers. Unfortunately, while STN displays provide substantial cost advantages, they do present unique operational problems which must be accounted for during display data processing.
One of the most significant problems with STN displays is the short data retention time of the display elements. Consequently, the display elements (pixel) must be refreshed (scanned) at a rate significantly higher than the refresh rate of comparable active matrix LCD display elements in order to insure that the maximum allowable time between refresh is not exceeded. This in turn requires that the associated display processor be capable of streaming display data to the display at a rate high enough to support the higher refresh rate.
Dual scan super twisted pneumatic (DSSTN) displays attempt to handle the problem of short data retention time by dividing the display screen into two simultaneously scanned regions or areas. During the refresh of each frame, one area is refreshed with current data from the primary frame buffer space while the other area is refreshed with data recycled from the last scan of that area, as retrieved from an independent buffer space in the frame buffer memory. On the next refresh cycle, the first panel is refreshed with recycled data from the independent buffer during the previous scan and the second panel is refreshed with current data from the frame buffer. In other words, display data for a given panel is used twice.
The dual scan-dual buffering scheme advantageously allows the display processor to meet the minimum refresh data requirements of STN displays. However, such a scheme also has substantial disadvantages. Among other things, the demands on the frame buffer system are significantly increased. Specifically, three different types of operations are required for display refresh alone. First, reads are required from the primary frame buffer space to support refresh of the screen area being refreshed with current data. Second, reads are required from the independent buffer space to support refresh of the area being refreshed with recycled data. Finally, writes of the current data into the independent buffer space are required to store data for recycling during the next refresh cycle. All these operations must be performed in view of all the other demands made on the frame buffer memory subsystem by the CPU and display controller. Among other things, the frame buffer must also provide for CPU access for data updates, bit-block transfers (BLTs), cursor generation, and allow the display controller to perform such operations as basic graphics functions and DRAM refresh.
An additional problem arises since the buffering of the data being recycled requires additional capacity in the frame buffer. The dynamic random access memories (DRAMs) most often used to construct frame buffers are only manufactured in fixed capacities and fixed word widths. Consequently, the capacity of memory subsystems supporting a given data bus width can typically be varied only in corresponding fixed incrementations. Thus, depending on the capacity already required to support traditional frame buffer operations and the size of the memory devices used, the additional storage capacity required for recycling may force the use of the next largest incrementation of memory. The next incrementation however may have substantially more capacity than required to meet both the needs of the traditional and the additional frame buffers. As a result, memory space is wasted and unnecessary costs incurred.
Thus, the need has arisen for circuits, systems and methods for implementing dual scan displays. In particular, such circuits, systems and methods should reduce frame buffer subsystem overhead and reduce wasted memory space and the associated costs.