The semiconductor industry has continually improved the speed and power of integrated circuits (ICs) by reducing the size of components (e.g., transistor devices) within the ICs. In large part, the ability to scale the size of components within an integrated chip is driven by lithographic resolution. However, in recent technology nodes tool vendors have been unable to decrease the wavelength of photolithography exposure tools (e.g., to successfully implement EUV lithography), so that developing technology nodes often have minimum feature sizes smaller than the wavelength of illumination used in the photolithography tools.
Double patterning lithography (DPL) has become one of the most promising lithography technologies for printing critical design layers (e.g., polysilicon, thin metal routing, etc.) in sub-22 nm technology nodes. However, some double patterning technologies (e.g., litho-etch, litho-etch) suffer from misalignment and overlay problems that degrade integrated chip performance. In recent years, self-aligned double patterning (SADP) has emerged as a double patterning technology that is able to avoid such misalignment and overlay errors.