1. Field of the Invention
The present invention relates generally to the field of semiconductor fabrication and, more particularly, to the field of fabricating p-channel and n-channel transistors with different characteristics on a common substrate.
2. Description of Related Art
In complementary metal oxide semiconductor (CMOS) fabrication, p-channel and n-channel transistors are fabricated on the same semiconductor substrate. To achieve transistors of both polarities (conductivity types), it is necessary that at least some process is steps differentiate between p-type and n-type transistors. Separate implant steps, for example, are needed to define n-well and p-well structures and to dope the source/drain regions of n-channel and p-channel transistors. Whenever possible, however, it is generally desirable to use a single process step to define transistor features regardless of the transistor type. Single process steps imply a single mask step, which is always desirable to reduce load on the photolithography processing. Moreover, a single step generally minimizes undesirable variations between the p-channel and n-channel transistors. Imagine, for example, that a particular design has been optimized under the assumption that the thickness of the gate oxide (or other dielectric) is the same on n-channel and p-channel transistors. The best way to ensure that the assumption is correct is to form the relevant feature for p-channel and n-channel transistors simultaneously.
In some cases, however, it may be desirable to process n-channel and p-channel transistors separately to account for differences in the characteristics of the respective transistor types. As an example, there is an asymmetry in the sub-micron behavior of p-channel and n-channel transistors. For sub-micron p-channel transistors, the high diffusivity of its boron carriers causes sub-threshold leakage current to be of paramount concern. For n-channel transistors, the drive current or saturated drain current (IDS), which is an important performance parameter, is strongly influenced by the effective length of the source/drain extension region due to the parasitic resistance that it creates. Whereas it would be desirable to have shorter extensions to increase the n-channel drive current, it would be desirable to have longer extensions to reduce the p-channel sub-threshold leakage current. It would therefore be desirable to implement a process that simultaneously addressed these concerns without substantially increasing the cost or complexity of the process.