1. Field of Invention
The present invention relates generally to the field of testing of semiconductor logic, in particular to scan chain testing.
2. Description of Related Art
Fabrication of microchips inherently introduces defects into some percentage of manufactured devices, which necessitates a thorough test of the chips to ensure defective devices are not shipped. In a scan-based design of a microchip, test data is input to the microchip when in test mode, and the output is observed and compared to a predicted output. Registers, such as flip-flops or latches, are connected in one or more scan chains, which are used to gain access to internal nodes of the microchip. Test patterns are shifted into the microchip via the scan chain(s), with clock signals pulsed to test the circuit during the “capture cycle(s).” The results of the capture cycles are then shifted out to the microchip output pins and compared against predicted results. Variance between actual output and predicted output indicates a failure.
Thus the most prevalent test architecture is scan path, wherein the flip-flops of the circuit of the microchip are chained together or stitched to form one or more scan chains. There are two methods of implementing scan path: partial scan, wherein only a subset of flip-flops are chained together, and full scan, wherein all relevant flip-flops are chained together. Each flip-flop that becomes part of a scan chain is called a scan flip-flop.
Using the scan path architecture, the state of every scan flip-flop can be set to a desired value simply by shifting in a particular test pattern, or test vector. Thus, test of the complicated sequential design of a microchip is reduced to shifting in a test pattern, testing combinationally, and then shifting out the response.
An unfortunate result of using prior art scan path architecture to test a device is excess power consumption and often increased temperature beyond normal levels achieved during functional mode. Shifting data into the scan chains causes an excessive amount of switching, or toggling, of circuit nodes, much greater than the switching level achieved during functional mode. Excess power and temperature during test can cause good devices to fail and can reduce device reliability.
Excess power consumption is further aggravated by routine test optimizations aimed to reduce test cost and increase test coverage. Shifting in each test pattern is a slow process due to the length of the scan chains. For example, given a design with 500K flip-flops that make up 32 scan chains, there are 500K/32=16K flip-flops per scan chain, meaning it takes 16K clock cycles to shift in a single test pattern. Typical test sets consist of tens of thousands of such patterns. To reduce test cost (tester memory requirements and test time), compaction and compression is used to reduce the total number of test patterns, but this increases the switching activity caused by each test pattern. Furthermore, the data is shifted into the scan chains at as high a clock frequency as possible (albeit this clock frequency is much lower than the functional clock frequency due to the unoptimized scan paths).
At times, bits that need not be specified in a given test pattern to detect the targeted fault or faults, called “don't care” bits, are filled with random values to increase the amount of toggling that occurs when the test pattern is combinationally applied to the circuit. It is well known that such random filling helps detect more defects, specifically defects that are otherwise untargeted or undetectable under the fault model used to generate the test patterns. Such fortuitous defect detection is called collateral coverage.
Regarding test power, there are many things to consider when talking about power consumption during test. Peak power consumption is important when power and ground lines are sized to handle peak power drawn by the device during functional mode. If peak power consumption during test exceeds the rating of the power and ground lines, large current spikes can flow that damage the device. Average power consumption is important when packaging and heat dissipation ability is determined by the functional mode switching, or activity levels. If the activity levels during test exceed the levels expected during functional mode, the device can overheat and damage can occur.
There are two periods of increased activity during test: 1) shifting in test patterns and shifting out responses (generically called shifting), and 2) capturing test responses. Reducing power consumption during capture is a relatively new concept, which primarily relies mostly on filling the don't care bits in a given test pattern—those bits whose values are irrelevant in detecting the targeted fault or faults—such that fewer circuit nodes switch during capture. It was also shown in Wen et al., “A New ATPG Method For Efficient Capture Power Reduction During Scan Testing,” Proc. VLSI Test Symp., pp. 58-63, (2006), that test patterns can be generated with switching activity in mind to reduce capture power consumption.
Besides the obvious method of decreasing the shift clock frequency, there are several methods to decrease the power consumption during shifting. The order in which the scan flip-flops are stitched together to form scan chains can be altered. Test patterns can be reordered according to the switching activity caused by each pattern. The don't care bits in a given test pattern can be filled such that fewer flip-flops change state during shifting (for example all-zero fill, all-one fill, last-specified-bit-value fill, etc.). Scan chains whose flip-flop values are unimportant for detecting a particular targeted fault or faults, or whose flip-flop values need not be updated, can be frozen, or turned off, during shifting. Finally, logic gates can be inserted on the scan paths (and the test patterns modified accordingly) such that fewer flip-flops change state during shifting.
Not only is excess power consumed by toggling of scan flip-flops, but the combinational logic connected to the Q output of each flip-flop may also toggle. Thus, logic gates can be inserted on the functional path (Q output) to block switching activity from propagating to the combinational logic. However, the added logic gate or multiplexer on the functional path, called blocking logic, increases the delay of the functional path, which is undesirable.
What is lacking in the prior art is a method and apparatus for an improved process to minimize the toggling during shifting in and shifting out of test patterns, and at the same time keep the randomness of the “don't care” bits of the test pattern, to decrease shift power and increase collateral coverage, such as taught in the present invention.