1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and in particular, relates to a memory device which is capable of storing analog or many-valued data at high speed and with a high degree of accuracy.
2. Description of the Related Art
In recent years, in concert with the development in computer technology, the progress in the field of data processing technology has been truly remarkable. However, when attempts were made to realize the flexible type of data processing conducted by human beings, it was almost impossible to obtain the results of such calculations in real time using present computers. The reasons advanced for this are that the data which human beings process in the course of their daily lives are analog data, so that there is firstly an enormous amount of such data, and moreover, these data are inexact and vague. It is thus a problem in present data processing systems that the extremely redundant analog data are all converted into digital values, and rigorous digital operations are conducted one by one.
An example of this is image data. For example, if one screen is incorporated into a 500.times.500 two dimensional array, then the total number of pixels is 250,000, and when the strength of the three colors red, green, and blue for each pixel is expressed in terms of eight bits, then the amount of data in one stationary image reaches 750,000 bits. In moving images, the amount of image data increases with time. Even if a present day supercomputer is used, it is impossible to manipulate the large amount of (1)/(0) data and conduct picture recognition and understanding in real time.
On the other hand, attempts have been made to realize data processing approximating that of human beings by accepting real world data, which are analog values, in an unchanged form and conducting calculations and processing on these analog values, in order to overcome the problems described above. As a result, a number of memory devices have been invented.
As one of these devices, the present inventors have proposed, in Japanese Patent Application No. Hei 7-2944, a memory device which is capable of writing desired analog values using simple circuitry such as that shown in FIG. 9 (title of the invention: Nonvolatile semiconductor Memory, date of application: Jan. 11, 1995). First an explanation of the cell of this technology will be made.
Reference 901 indicates an NMOS transistor, while reference 902 indicates a floating gate formed from, for example, N.sup.+ polysilicon; this controls the ON and OFF state of NMOS 901. NMOS drain 903 is connected to power source line 904, while source 905 is connected to an external capacity load 906; the structure is such that the circuit operates as a source follower circuit and reads out a potential V.sub.FG of the floating gate 902 to the exterior as V.sub.OUT. Reference 907 indicates an electrode which is capacitively coupled with floating gate 902; in this example, it is grounded. The capacitive coupling coefficient thereof is represented by C.sub.1. Reference 908 indicates a charge transfer electrode; it is connected with the floating gate via a tunnel junction 909 which is an oxide film of approximately 10 nm. The capacitance of this tunnel junction 909 is represented by C.sub.2. Charge transfer electrode 908 is connected to writing high voltage application electrode 911 via a capacitance 910 (the size thereof is represented by C.sub.3). Reference 912 indicates an NMOS transistor; the ON and OFF state thereof is controlled by the output line 913 of the inverter. NMOS transistor 914 serves to connect the input 915 of a control circuit constructed using an inverter to a memory cell. The input 915 of the control circuit is capacitively coupled with input of inverter 916, and the input of inverter 916 and output 917 are connected via NMOS transistor 918. Output 917 controls the ON and OFF state of NMOS transistor 912 via a further stage inverter.
The readout principle is simple; NMOS 914 is placed in an OFF state, and the memory cell is cut off from the control circuit, and transistor 901 is then conducts a source follower operation in the state in which electrode 911 is grounded, and the contents of the floating gate are read out as an analog value.
The writing principle will next be explained. During writing, after a reference value is first inputted into input 915 of the control circuit, NMOS transistor 918 is first turned ON and is then turned OFF, and the reference value is stored in the input portion of inverter 916, which has been placed in a floating state, as a charge, and next, when the reference value is inputted into the control circuit, the control circuit outputs the power source voltage to the output line 913. This reference value represents the addition of an offset voltage to the voltage of the data which are to be written, and since the offset voltage has a value particular to each circuit, the reference value is easy to determine.
Next, NMOS 914 is placed in an ON state so that the control circuit may monitor the output of the source follower. After this, a high voltage of approximately 20 V is applied to electrode 911, a strong electric field is produced in the tunnel junction 909, and a Fowler-Nordheim current is caused to flow. The electrons are drawn from the floating gate and writing commences, and the voltage of the floating gate during this writing is inputted into the control circuit via transistor 901 during the source follower operation. When the output of the source follower has become equal to the reference value, the power source voltage is outputted to the output line of the control circuit and transistor 912, which was in an OFF state, is allowed to conduct. When this is done, electrode 908 is discharged, the strong electric field generated in tunnel junction 909 disappears, and writing is completed. At this time, the voltage of the object data is written into the floating gate.
Furthermore, a variety of circuit structures are employed as the control circuit, and only one example thereof is discussed here.
FIG. 10 is a circuit diagram showing a plurality of such cells arranged so as to form an actual memory. The circuit shown in FIG. 9 is employed in an unchanged manner as the control circuit. Of course, other circuits maybe employed in some cases.
The reason that a plurality of cells need to be arranged in this way is so that writing may be conducted in such a manner that only the cell into which writing is to be conducted is selected. References 1001, 1002, and 1003 are writing high voltage application electrodes of the cells, respectively, while references 1004, 1005, and 1006 are NMOS transistors used for reading selection. In writing selection, a high voltage is applied only to the writing voltage application electrode of the cell into which writing is to be conducted, while the electrodes of other cells are set to the ground potential, and only the reading selection transistor of the cell into which writing is conducted is placed in an ON state, so that the control circuit may monitor only the contents of the cell into which writing is to be conducted. By proceeding in this manner, it is possible to cause a tunnel current to flow only in the cell in which writing is to be conducted, and it is possible to read out the state of only that cell into which writing is conducted to the control circuit.
This memory realizes accurate writing with simple control circuitry; in addition, there is sufficient selectively in writing and reading, although there is a problem in that the degree of integration does not increase.
The reason for this is as given below.
C.sub.2 represents the capacitance formed in the tunnel oxide film and since an extremely thin oxide film is employed, although this capacitance becomes rather large, it is necessary to set C.sub.1 and C.sub.3 so as to be larger than C.sub.2. The reasons that the design must be accomplished in this manner are as follows:
(1) In order to apply a large voltage to C.sub.2, it is necessary that C.sub.2 be shown to be small in comparison with C.sub.3 and C.sub.1 ; PA1 (2) C.sub.1 must be made large in comparison with C.sub.2 and C.sub.3 in order to suppress the rise in voltage in the floating gate resulting from capacitive coupling when a high voltage is applied during writing; PA1 (3) It is necessary to set the value of C.sub.3 so as to be considerably larger than the sum of C.sub.1 and C.sub.2 in order to reduce the voltage drop across C.sub.2 resulting from the movement of charge during writing. As an example, appropriate examples are C.sub.1 :C.sub.2 : C.sub.3 =5:1: 25. At this time, the size of the tunnel oxide film is set to 1.5 .mu.m on a side and the thickness thereof is set to 10 nm, and if C.sub.1 is formed between the substrate and the first polysilicon layer, then the thickness of the oxide film between these is 50 nm, and the area is 7 .mu.m.sup.2, while 16 .mu.m.sup.2 is necessary for C.sub.3. In a structure in which this type of conventional cell is employed, a large capacitance load such as C.sub.3 is provided for each cell as shown in FIG. 10 and this is undesirable. It is clear that as a result of this capacitance alone, the size is not different from present DRAM or EEPROM, so that the degree of integration does not increase.
Furthermore, attempts have been made to omit output selection transistors such as 1004, 1005, and 1006 in order to further reduce the number of elements. At this time, when power sources 1007, 1008, and 1009 are all in operation, output line 1010 is set to the maximum value maintained by the floating gate at all times, and selectivity is lost with respect to reading and with respect to the cell which is monitored during writing. Furthermore, if only the power line of the cell which is to be operated is set to the power source voltage, and only one cell is read out, as a result of the voltage rise of voltage line 1010, the power source side of cells which are not to be read out becomes the source, and in this state, they enter an ON state, and this is undesirable. The source follower transistors of the cells which are to be read out also include these and charging is necessary, so that this leads to a decline in the read out speed.
Accordingly, stratagems are necessary to reduce the number of elements.
FIG. 11 shows a circuit in which the outputs of the cell group shown in FIG. 10 are connected one by one to source follower buffer circuits having a CMOS structure. During actual use as a memory, it is necessary that the memory data be conveyed as far as the operating portions, so that the source follower of the cells must drive comparatively long wiring. For this reason, it was necessary to connect buffer circuits such as those conventionally employed to the memory output portions, as shown by 1101, 1102, and 1103; however, the attachment of buffer circuits to each of the memory outputs further increases the number of elements required for a memory cell, and thus an increase in the degree of integration can be anticipated. Furthermore, as a result of variation in the buffer, or the thermal characteristics of the MOS threshold, there were cases in which an accurate readout could not be conducted.
The present invention was created in light of the above circumstances; it has as an object thereof to provide a nonvolatile semiconductor memory which is capable of a high degree of integration and can conduct the writing of analog data at high speed and with a high degree of accuracy.