1. Field of the Invention
The present invention relates to an integrated circuit package, and more particularly, to an integrated circuit package with a balanced-part structure.
2. Description of the Prior Art
The integrated circuit formed on a semiconductor structure to form an integrated circuit chip is used to be set in a package, i.e. the Quad Flat Package, QFP. The flat package includes leads connected with a lead frame for contacted with the integrated circuit chip. The chip is packaged inside an electric-isolating stable plastic including mechanical support. The leads are soldered on a Printed Circuit Board, PCB.
Many integrated circuit packaging technologies are very important and are improved for packaging the smaller integrated circuit element including million transistor circuits, i.e. the circuits and the dies. The integrated circuit is formed on a silicon wafer through many processes, i.e. the etching process, the implanting process, the depositing process and the cutting process. A silicon wafer includes integrated circuit chips, i.e. dies, wherein each die is an independent integrated circuit. After the silicon wafer is cut to be many chips, each chip must be packaged to form an integrated circuit package with leads. Chips could be packaged to be different types according to the layout of the integrated circuit packages, i.e. M Dual-In-Line-Package, M-Dip. The leads of the M-Dip extend from the bottom of the M-Dip to contact with and fasten on the PCB in two parallel rows. A PCB including more integrated circuit may be a Single-In-Line-Package, SIP, or a Small Outline J-leaded, SOJ.
According to the amount of chips, the Single Chip Package, SCP, method and the Multi-chip Package, MCP, method are the main packaging types of the integrated circuit packaging technologies, wherein the MCP method includes the Multi-chip Module, MCM, method. According to the contacting styles between leads and a PCB, the integrated circuit packages include the Pin-Through-Hole, PTH, packages and the Surface Mount Technology, SMT, packages. Leads of a PTH package are acicular leads or sheet leads to pin through the sockets or the holes on the PCB for fastening and soldering. A SMT package is fastened on a PCB by soldering. An advanced and improved packaging method is the Direct Chip Attach, DCA, packaging method. The DCA packaging method directly attaches and fastens chips on a substrate, and then connects the chips and the substrate for electrical connection to shrink the size of the whole integrated circuit package.
The problems about mechanical stress and thermal mechanical stress of the integrated circuit packages become obviously as more as the integrated circuit packages are smaller. A little integrated circuit package may get warpage defects of a substrate of the integrated circuit package due to the non-uniform mechanical stress and the non-uniform thermal stress on the substrate while the chips operating. A single chip is fastened on the center of a substrate of an integrated circuit package to balance mechanical stress due to the weight of the chip and the substrate if there is only one chip packaged inside the integrated circuit package. Warpage defect of the substrate and the integrated circuit package does not appear if the stress, i.e. mechanical stress and thermal stress, of the substrate and the whole integrated circuit package balances very well. So that warpage defect of the integrated circuit package with only one chip is usually very small or disappeared because thermal stress inside the integrated circuit package balances very well.
In order to operate an integrated circuit package more effectively and shrink the scale of the integrated circuit package, a plurality of chips are fastened on a substrate of the integrated circuit package for receiving, transmitting and processing a plurality of signals simultaneously by only one integrated circuit package. Of course the chips fastened inside the integrated circuit package may include different material, different size, different weight, etc. according to the functions of the integrated circuit package. The chips with different material, different size, different weight, etc. break the balance of the stress, i.e. mechanical stress and thermal stress of the substrate and the integrated circuit package. Hence warpage defects of the substrate and the integrated circuit package would appear because of thermal stress caused from operating chips. Warpage defects affect the operation of the integrated circuit package and spall or crack the chips fastened on the substrate. Thus, the quality of the integrated circuit package becomes worse because of the unbalanced stress inside the integrated circuit package.
According to the above description, it's necessary to develop an integrated circuit package to prevent warpage defects due to the unbalanced mechanical stress and the unbalanced thermal stress of operating chips to maintain the quality of the integrated circuit package.