The present invention relates to a semiconductor memory and, more particularly, to a technical which may be effectively applied to an address transformation buffer or the like which is included in a memory management unit of a digital processing system adopting the virtual storage method.
The virtual storage method is one means for removing constraints imposed by the physical properties of memories and thus producing a flexible program system. A digital processing system that employs the virtual storage method is provided with a memory management unit 1 for transforming a logical address output from a processing unit into a physical address on a main memory within a bus cycle thereof.
The memory management unit 1 includes an address transformation buffer 5 and an address transformation control circuit 6. The address transformation buffer 5 is arranged to have a necessary and minimum number of entries with which the hit rate is in excess of a predetermined value, and it is controlled by the address transformation control circuit 6. The address transformation control circuit 6 also functions as a so-called DAT controller which executes a paging processing autonomously without the aid of a control program (operating system) when the address transformation buffer 5 mishits.
The memory management unit is described, for example, in "Nikkei Electronics", Dec. 5, 1983, Nikkei McGraw-Hill, pp. 137-152.
The studies conducted by the present inventors has, however, revealed that the prior art suffers from the following disadvantages.
In the memory management unit 1 of the type described above, the address transformation buffer 5 includes a tag memory 11 for storing, for example, tags which are allotted to the corresponding entries, that is, index portions ID of logical addresses, and a frame number memory 12 for storing the frame numbers FN of the physical addresses corresponding to the tags. The tag memory 11 is stored with address validity flags F each of which represents whether or not the corresponding entry is valid. Further, the tag memory 11 and the frame number memory 12 are respectively provided with parity bits used to judge whether or not readout data is normal.
In the tag memory 11 and the frame number memory 12, the index portions ID and the frame numbers FN are respectively input and output in units of address. The address validity flags F in the tag memory 11 are also usually input and output in units of address together with the index portions ID, but there are cases where the address validity flags F are partially rewritten independently of the index portions ID and the parity bits because of the necessities to reset all the addresses simultaneously at the time, for example, of switching over programs from one to another in the digital processing system and to achieve high efficiency of the address management. Accordingly, it is necessary, in order to hold the validity of the parity bits, to read out the contents of the relevant addresses from the tag memory 11 and rewrite the parity bits correctly every time the above-described reset operation or partial rewriting operation is conducted, which complicates the processing conducted in the memory management unit 1, resulting in a lowering in the throughput thereof, and which also complicates the circuit configuration of the memory management unit 1 and thus constitutes one of the causes of prevention of lowering in the cost thereof.