1. Field of the Invention
The present invention relates to a voltage controlled oscillator (VCO) of a ring type and a charge pump circuit, each integrated in a semiconductor chip, oscillating and outputting a stable high frequency.
2. Description of the Prior Art
Conventionally, voltage controlled oscillators are incorporated into many devices and applied to a wide range of application fields such as a phase locked loop (PLL), communication field, computer field, image and audio device field, and the like. In recent years, there is a requirement in those fields to provide a voltage control oscillator oscillating and outputting a more stable and higher frequency for various types of devices and systems that may operate at a higher speed.
When a PLL and a controller to control the delay time of a signal are integrated on a semiconductor chip, ring oscillators are used as voltage controlled oscillators (VCO). Ring oscillators control the magnitude of a current flowing through an odd number of inverter circuits that are electrically connected in a ring. Although this demand may be achieved by using a fine technique in semiconductor fabrication processes, this decreases stable oscillation due to parasitic capacitances in a semiconductor integrated circuit designed to output a higher frequency.
FIG. 1 is a circuit diagram showing a conventional voltage controlled ring oscillator. In FIG. 1, the reference numbers 61, 62, 63, 64, . . . , and n (n is an odd number) designate inverter circuits that are connected electrically in an odd number of stages in a ring, and the reference number 65 denotes a current control circuit. This conventional voltage controlled oscillator shown in FIG. 1 comprises the current control circuit 65 andthe inverter circuits 61, 62, 63, 64, . . . , n in the odd number of stages. Each of the inverter circuits 61, 62, 63, 64, . . . , n comprises current source transistors P1 and N1 whose operation is controlled by a voltage, switching transistors P2 (P channel type transistor) and N2 (N channel type transistor) for switching a current supplied from each of the current source transistors P1 and N1. Those transistors P1, P2, N1, and N2 are electrically connected in series. As shown in FIG. 1, the inverter circuits 62, 63, 64, . . . , and n are connected in a ring shape in order to form complementary circuits.
Next, a description will be given of the operation of the conventional voltage controlled ring oscillator shown in FIG. 1.
Here, the operation of the inverter circuit as only one stage in the conventional voltage controlled ring oscillator will be explained for brevity.
The operation of the current source transistor P1 is controlled by a magnitude of an output voltage from the current control circuit 65. The gate electrodes and the drain electrodes of both the P channel switching transistor P2 and the N channel switching transistor N2 are connected electrically to each other. The gate electrode and the drain electrode of each of the P channel switching transistors P2 and the N channel switching transistors N2 in the inverter circuits in the odd number of stages are electrically connected to each other to form the ring shape, as shown in FIG. 1.
In the same manner as the current source transistor P1, the operation of the current source transistor N1 is also controlled by the output voltage supplied from the current control circuit 65. In addition, like the P channel switching transistor P2, the gate electrode and the drain electrode of the N channel switching transistor N2 in the inverter stage in one stage are electrically connected to the gate electrode and the drain electrode of the inverter circuit in another stage, respectively, in the ring shape.
In general, in voltage controlled oscillators such as the conventional voltage controller having the configuration shown in FIG. 1, current output from each of the current source transistors P1 and N1 is controlled by the output voltage from the current control circuit 65 in order to change a the delay caused in the inverter circuits connected in a ring. This controls an oscillating frequency of the voltage controlled oscillator. In this case, parasitic capacitances CDP and CDN in the drain capacitor and a parasitic capacitor CG in a drain-gate capacitor includes a parasitic capacitor in a wiring capacitor. These parasitic capacitors CDP, CG, and CDN are charged and discharged to the voltage of the power source and to the ground voltage, respectively, while the current source transistors P1 and N1 are in OFF state. These charges move to the gate capacitor CG in the inverter circuit at the following stage through the output terminal of the current inverter circuit. The amount of the moving charges is determined based on the ratio of the parasitic capacitances CDP or CDN and CG. These moving charges act fail to maintain the linearity of the current control by the current control circuit 65, so that oscillation halts or a discontinuous change of the frequency is caused when the output voltage from the current source transistors P1 and N1 crosses the value of the threshold voltage of the inverter circuit at the following stage when the switching transistors P2 and N2 enter ON. This causes an unstable state of the system because the phase lock operation becomes unstable.
FIG. 2 is an explanation diagram showing a case in which the value of the output voltage from the current source transistors P1 and N1 in one inverter circuit becomes lower than that of an input threshold voltage of the following inverter circuit in the conventional voltage controlled oscillator shown in FIG. 1. In FIG. 2, the fine line designates the waveform of the output voltage from the current source transistors P1 and N1 in one inverter circuit in the voltage controlled oscillator as an ideal case where the values of the parasitic capacitors CDP and CDN are zero. In addition, the solid line denotes the waveform of the output voltage from the current source transistors P1 and N1 in one inverter circuit in the voltage controlled oscillator as an actual case where the values of the parasitic capacitors CDP and CDN are not zero.
As shown in FIG. 2, when the value of the output voltage from the current source transistors P1 and N1 in one inverter circuit crosses the threshold voltage of the inverter circuit at the following stage, the phase lock operation becomes unstable based on the ratio of the parasitic capacitances as CDP or CDN and CG, because the characteristic of the ring oscillation circuit becomes bad and the phase lock operation enters an unstable state. This causes a system including the conventional voltage controlled oscillator to enter an unstable state.
Because the conventional voltage controlled oscillator has the configuration described above, when the switching transistors enter the OFF state, the parasitic capacitances are charged or discharged, and these charges decrease the characteristic of the ring oscillation circuit, the phase lock operation becomes unstable and thereby the entire operation of the system also enters an unstable state.