1. Field of the invention
The present invention relates to a method of forming a hard mask, and more particularly, to a method of forming a hard mask having a nitride film.
2. Description of Related Art
A design rule of a semiconductor memory device is on an ever-decreasing trend. Due to the ever-narrowing design rule, the thickness of a photoresist film is unavoidably reduced in the case of a photolithography process. Such decrease in the thickness of the photoresist film causes inevitable erosion of a photolithographic mask since the selectivity of the photoresist film is limited during etching of a multi-layered mask. Such erosion of the mask worsens the resulting thickness variation of the mask following a trench etching process and a subsequent chemical mechanical polishing (CMP) process. Accordingly, there is a need for improving the selectivity of the photoresist film in a mask etching process.
FIGS. 1A to 1F are cross-sectional views illustrating a process of forming a conventional hard mask having a nitride film, and a related process of forming a trench.
Referring to FIG. 1A, a pad oxide layer 20 is formed on a semiconductor substrate 10 comprising silicon. A mask layer is formed on the pad oxide layer 20. The mask layer includes a nitride layer 31 comprising SiN, an oxide layer 32 comprising SiO2, and a nitrogen-oxidation layer 33 comprising SiON, which are sequentially deposited on the pad oxide layer 20. The oxide layer 32 comprises a high temperature oxide layer. A photoresist pattern 40 is formed on the mask layer. In one example, the photoresist pattern has a thickness of 0.30 μm.
Thereafter, the mask layer is etched by dual, separate etching processes. In more detail, referring to FIG. 1B, the oxide layer 32 and the nitrogen-oxidation layer 33 are etched using the photoresist pattern 40 as a mask. Following this, referring to FIG. 1C, the nitride layer 31 is then etched.
Referring to FIG. 1D, the photoresist pattern 40 is removed by an ashing process and a strip process, thereby forming a multi-layered hard mask 30.
Referring to FIG. 1E, the hard mask 30 is used to expose a portion of the semiconductor substrate 10.
Referring to FIG. 1F, the remaining portions of the pad oxide layer 20 and the hard mask 30 are removed, thereby forming a trench 50 in the substrate 10.
Thereafter, an oxide layer is filled in the trench 50 (not shown), and then a CMP process is performed to form an isolation film in the trench which isolates an active region formed on the substrate.
The mask etching process described above is performed using a mixing gas of CHF3/CF4/Ar/O2. In this case, the ratio of the etching rate of the photoresist film to the etching rate of the mask layer is on the order of 1:1.5. In the case of a semiconductor device having a narrow design rule, due to a poor selectivity of the photoresist film, a problem occurs in that when the photoresist film is etched away, a portion of the hard mask is eroded.
Referring to FIG. 2A, at this stage, the photoresist film is removed from the hard mask, and the hard mask is partially removed as well 61. Further, as shown in FIG. 2B, following the trench etching process, the hard mask is eroded even further 62.
In addition, since selectivity of the photoresist film (or the ratio of the etching rate of the hard mask to the etching rate of the photoresist film) is poor, the nitride layer 31, the oxide layer 32 and the nitrogen-oxidation layer 33 are etched using different etching equipment, respectively, as described above, thereby reducing throughput of the process.
Such decreasing of the thickness of the photoresist film resulting from a narrow design rule greatly affects the trench etching process for isolating an active region and the etching process of a gate polysilicon layer of a semiconductor device having a deep trench and a multi-layered structure, such as found in SRAM and non-volatile memory (NVM) devices.