In the field of field-effect transistors there is a continual quest for devices that approximate an ideal switch, that is, devices that have a very low-resistance when they are turned on and a high voltage-blocking capability when they are turned off. Another objective is a size that occupies minimal “real estate” on today's miniaturized semiconductor chips.
In accordance with the Reduced Surface Field (RESURF) principle, it is known to provide an extended “drift” region in a field-effect transistor, which in a MOSFET is an extension of the drain region. The charge in the drain extension must be carefully controlled to obtain a high Vbd. The RESURF principle was advanced in an article titled “High Voltage Thin Layer Devices (RESURF Devices),” by Appels and Vaes, IEDM Tech. Digest, pp. 238-241 (1979). The drift region permits a more gradual voltage drop across the terminals and reduces the possibility of avalanche breakdown in this area of the device. FIGS. 1 and 2 illustrate a MOSFET 10 that includes a drift region. FIG. 1 is a top view of MOSFET 10; FIG. 2 is a cross-sectional view of MOSFET 10 taken at cross-section 2-2 shown in FIG. 1. As shown in FIG. 1, MOSFET 10 is formed in a circular configuration, with the N+ drain region 110 at the center of the circle and the N+ source region 111 surrounding the N+ drain region 110.
As shown in the cross-sectional view of FIG. 2, the device is fabricated in an N epitaxial (epi) layer 119 that is grown on a P− substrate 114. A thick field oxide layer 118B is grown on the surface of N epi layer 119 between N+ source region 111 and N+ drain region 110, typically by a LOCOS (local oxidation of silicon) process. A gate 112, typically made of polycrystalline silicon (polysilicon), is deposited on top of a gate oxide layer 118A and steps up over field oxide layer 118B. A P body region 113 is formed in N epi layer 119, including a channel region 116 that lies directly below a gate oxide layer 118A. A P+ body contact region 115 provides an ohmic contact with P body region 113, which is shorted to N+ source region 111 via a source metal layer 112A. This helps to prevent the parasitic bipolar transistor composed of N+ source region 111, P body region 113 and N+ drain region 110 from turning on.
To increase the voltage-blocking capability of MOSFET 10, an extended drain or drift region 117 is interposed laterally between channel region 116 and N+ drain region 110. Drift region 117 is generally lightly-doped. When MOSFET is turned off, the voltage drop between N+ source region 111 and N+ drain region 110 is partially absorbed in drift region 117, increasing the ability of MOSFET 10 to withstand a large voltage.
This increased voltage-blocking capability comes at a price, however. When MOSFET 10 is turned on, the channel region 116 is inverted and current flows between N+ source region 111 and N+ drain region 110. The presence of the lightly-doped drift region 117 in the current path between N+ source region 111 and N+ drain region 110 increases the on-resistance of MOSFET 10.
U.S. Pat. No. 6,800,903 proposed an alternative solution, which is illustrated in FIG. 3. MOSFET 20 is for the most part constructed similarly to MOSFET 10, but a series of P buried layers 120 and 121 are implanted at different levels in drift region 117. P buried layers 120 and 121 may float electrically, or they may be tied to P− substrate 114, which is normally grounded.
When MOSFET 20 is in the off state, P buried layers 120 and 121 and the portions of N drift region 117 above and below and between P buried layers 120 and 121 are mutually depleted of free carriers. The portions of N drift region 117 that are above and below and between P buried layers 120 and 121 act as parallel JFET channels, and the current is effectively pinched off in these JFET channels when MOSFET 20 is turned off. This feature provides MOSFET 20 with a greater current-blocking capability that it would have if P buried layers 120 and 121 were not present. For this reason, the doping concentration of N drift region 117 can be higher than it would have to be in order to block current if P buried layers 120 and 121 were not present. For example, the '903 patent suggests that the combined charge in the portions of N drift region 117 above and below and between P buried layers 120 and 121 can be as high as 3×1012 cm−2, which reduces the on-resistance of the device to about one-third of what it would ordinarily be. To keep the strength of the electric field at a level below the critical level at which avalanche breakdown occurs, the charge in each of P buried layers 120 and 121 and the portions of N drift region 117 that are above and below and between them is balanced.
P buried layers 120 and 121 are formed by high-energy implants of a P-type dopant such as boron. The dose and energy of the implants are chosen to provide buried layers of the desired depth and charge concentration. Despite efforts to restrict the dopant to the desired location within the substrate, however, in practice the charge in the buried layers tends to diffuse outwards in three dimensions (both laterally and vertically), particularly if the device is subjected to any thermal processing after the buried layers are implanted. This outdiffusion of dopant makes the device difficult to manufacture.
In addition, a structure that includes alternating shallow P-type pillars in the N− drift region has been reported to improve the trade-off between on-resistance and breakdown voltage in lateral high voltage MOSFET's. See II-Yong Park and C.A.T. Salama, “CMOS Compatible Super Junction LDMOST with N-buffer,” Proc. Of 17th ISPSD conference, May 23-26, 2005, Santa Barbara, Calif.
The foregoing article and other ISPSD proceedings in the period 2000-2005 reference many other lateral super junction or charge control techniques for junction and SOI type lateral MOSFET's and IGBT's.
Nonetheless, all of these known charge control methods encounter problems with the dimensional control of PN junctions, especially junctions of the P-type dopant boron, during the subsequent process steps.
Thus it would be desirable to provide a field-effect device which has the current-blocking advantages of spaced regions of opposite conductivity in the drift region but in which the charge within the regions of opposite conductivity is better controlled. In particular, it would be desirable to limit the tendency of the charge to diffuse in at least two dimensions.