1. Field of the Invention
This invention relates generally to electrical current control circuitry and, more particularly, to a MOS integrated circuit (IC) current mirror correction device that permits a current mirror to be operated at high current levels and rapid switching speeds.
2. Description of the Related Art
As current mirrors comprise a basic and fundamental building block of all electronic systems there consequentially exists a significant amount of prior art. Many conventional current mirror circuits exist that can be switched at high-speeds, but require cascode devices to achieve the current accuracy and, thereby, reduce the compliance voltage. Alternately, they describe sources that are truly DC current mirrors whose output cannot be switched at high speeds.
FIG. 1 depicts a type of current mirror that uses an amplifier to force the drain-to-source voltage across the output transistor to be equal to the voltage across a mirroring transistor (prior art). The amplifier correction device permits the current mirror to achieve accurate output currents. This configuration preserves compliance voltage so long as the gate-to-source voltage is not too large. Such an arrangement, however, does not readily lend itself to modulating the output current at high rates of speed due to the settling time of the amplifier and, as such, is really only applicable to DC or very low-speed current mirrors.
FIG. 2 illustrates a cascode transistor current mirror (prior art). This conventional design can be readily switched at high rates, but the available compliance voltage is reduced due to the use of cascode devices to eliminate output conductance errors.
Despite the significant body of prior art, none of the devices describe a current mirror whose output can be switched at a high rate and that maximizes the available compliance voltage. In order to be able to deliver a modulated current, particularly large currents of several milliamps, which can be switched very quickly, it is necessary that very short gate lengths be used to minimize the size of the device. Minimizing the size of the device is required to minimize its capacitance and, consequently, the switching time. Furthermore, minimizing the channel length also minimizes the saturation voltage and, consequently, maximizes the compliance voltage. Unfortunately, the use of short channel length devices results in a significant error in the output current due to the high output conductance of the short channel device. The typical approach to eliminating the output conductance current error is to force the source-to-drain voltage across the output device to be equal to that across the mirror device by means of either an amplifier or a cascode device. These approaches have disadvantages in terms of switching speed and compliance voltage, as described above.
It would be advantageous if a current mirror circuit could be developed that operated at a high switching speed without cascode transistor arrangements that reduce the compliance voltage.
It would be advantageous if a current mirror circuit could be developed that operated over the full range of compliance voltage without the use of amplifier circuitry with reduces the speed at which current can be modulated.
It would be advantageous if a precision current mirror circuit could be developed that could supply large amounts of current at high speeds.
Accordingly, a MOS integrated circuit (IC) current mirror circuit is provided comprising a high-speed current mirror section and a correction section. The high-speed current mirror section advantageously does not use a cascode arrangement of output transistors. Primary and differential reference current are amplified at a first current mirror transistor pair and a second current mirror transistor pair has an output to supply the load current. A correction section is connected to the high-speed current mirror section output and, in response, supplies the differential reference current.
The correction section includes a buffer connected to the high-speed current mirror section output. The buffer supplies a buffered version of the load voltage and outputs an error signal. A replica mirror section accepts the buffered load voltage and a replica reference current. The scaled error current is altered by a cooperating current shaping circuit, and a reference current is generated.
Hence, a method for correcting current supplied from a high speed current mirror MOS IC is provided. The method comprises: providing a primary reference current; in a high-speed current mirror section, amplifying the reference current; in response to the amplified reference current, supplying a load current and load voltage at a high-speed current mirror section output; detecting the load voltage; and, supplying a differential reference current with the primary reference current to correct the load current.
In some aspects of the invention, the method further comprises: supplying a scaled replica reference current; amplifying the replica reference current with replica current mirror section; supplying a replica current mirror section output voltage matching the load voltage; and, in response to matching the load voltage, supplying the differential reference current.