1. Field of the Invention
The present invention relates in generate to a semiconductor device, and in particular to a semiconductor device which includes a first polysilicon resistance film and a second polysilicon resistance film and is improved so that both the resistance films may have equal resistances provided that they have the same pattern. The invention also relates to a manufacturing method of such semiconductor device.
2. Description of the Background Art
FIG. 16 shows an example of a constant voltage circuit used in a bipolar linear circuit. The linear circuit is a kind of monolithic ICs also called as analog IC handling continuous signals. An output voltage V.sub.0 of the constant voltage circuit is a function of resistances R.sub.A and R.sub.B as shown in the following expression. EQU V.sub.0 =(R.sub.A /R.sub.B -1) V.sub.BE
where, R.sub.A and R.sub.B indicate the resistances of resistors formed of polysilicon, and V.sub.BE indicates a forward voltage of a transistor.
FIGS. 17 and 18 show layouts of patterns of the circuit shown in FIG. 16.
FIG. 26 is a cross section of a bipolar linear circuit device in the prior art. FIGS. 19-26 are cross sections showing a manufacturing method thereof. The manufacturing steps and a construction of the bipolar linear circuit in the prior art will be described.
Referring to FIG. 19, an n.sup.+ -type embedded diffusion layer 2 is formed in a surface of a P-type silicon substrate 1. An n.sup.- -type epitaxial layer 3 is formed on the whole surface of the P-type silicon substrate 1.
Referring to FIG. 20, desired regions of the n.sup.- -type epitaxial layer 3 are oxidized by a selective oxidization method to form thin insulating oxide films 4. Thin insulating oxide films 5 are formed in regions other than the thick insulating oxide films 4. The insulating oxide film 5 has a thickness of 50-100 nm, and the insulating oxide film 4 has a thickness of 800-1500 nm.
Referring to FIG. 21, a p.sup.+ -type element isolating layer 6 and a p.sup.+ base layer 7 are formed in regions surrounded by the insulating oxide films 4. Referring to FIG. 22, a polysilicon film 8 of about 50.varies.500 nm in thickness is deposited on the insulating oxide film 4 and thin insulating oxide film 5 by low pressure CVD method at a temperature of 500.degree.-700.degree. C. n-type or p-type impurity is introduced into the polysilicon film 8, e.g., by diffusion or ion implantation, thereby the resistance of polysilicon film 8 is controlled to be in a range from several tens .OMEGA./.quadrature. to several hundreds k.OMEGA./.quadrature..
Referring to FIG. 23, photolithography is used to form a photo resist pattern 9 on the polysilicon film 8. Using the photo resist pattern 9 as a mask, unnecessary polysilicon film is removed by the etching using Freon gas plasma, thereby a first polysilicon resistance film 8b is formed on the thin insulating oxide film 5, and a second polysilicon resistance film 8a is formed on the thick insulating oxide film 4. Thereafter, the photo resist pattern 9 is removed.
Referring to FIG. 24, the CVD method is used to deposit an insulating oxide film 10 on the whole surface of the silicon substrate 1. The photolithography and etching are used to selectively remove the insulating oxide film 10 and thin insulating oxide film 5 located in emitter and collector regions of the bipolar transistor. Thereafter, n-type impurity is diffused to form an n.sup.+ emitter layer 11a and an n.sup.+ collector layer 11b.
Referring to FIG. 25, the photolithography and etching are used to form openings, which reach the P.sup.+ base layer 7, first polysilicon resistance film 8a and second polysilicon resistance film 8b, respectively, in the insulating oxide film 10. Then, metal electrodes 12 are formed, which are connected through these openings to n.sup.+ emitter layer 11a, p.sup.+ base layer 7, n.sup.+ collector layer 11b, first polysilicon resistance film 8b and second polysilicon film 8a, respectively.
Referring to FIG. 26, a plasma nitride film 13 is formed as a final protection film on the whole surface of the silicon substrate 1 by a low-temperature plasma enhanced CVD method at a temperature of 250.degree.-400.degree. C. using gas containing SiH.sub.4 +NH.sub.3. The plasma nitride film 13 obtained by the low-temperature plasma enhanced CVD method contains a large amount of hydrogen ion (H.sup.+).
Although not shown, the photolithography and etching technique are then used to remove the plasma nitride film 13 located on a bonding pad to form the bonding pad. After the subsequent thermal processing at 350.degree. C.-450.degree. C. and a series of manufacturing steps of the semiconductor device, the semiconductor device is completed.
Since the bipolar linear circuit device in the prior art has the construction described above, it has following problems.
FIG. 27 is an enlarged view of a portion in which the first and second polysilicon resistance films 8b and 8a in FIG. 26 exist.
Referring to FIG. 27, the heat treatment is applied to the plasma nitride film 13 deposited on the silicon substrate 3, and the hydrogen ion (H.sup.+) contained in the plasma nitride film 13 is supplied to grain interfaces in the first and second polysilicon resistance films 8b and 8a. In this case, the amounts of the hydrogen ion supplied to the polysilicon resistance films 8a and 8b from the upper side are substantially equal to each other. However, the amounts of the hydrogen ion supplied into the polysilicon resistance films 8a and 8b from the lower sides are different from each other. Specifically, the thin insulating oxide film 5 is disposed under the first polysilicon resistance film 8b, and the thick insulating oxide film 4 is formed under the second polysilicon resistance film 8a. Therefore, a larger amount of hydrogen ion is supplied through the thick insulating oxide film 4 into the second polysilicon resistance film 8a. As a result, the resistance R.sub.A of the second polysilicon resistance film 8a is lower than the resistance R.sub.B of the first polysilicon resistance film 8b. Generally, the resistance R.sub.A is lower than the resistance R.sub.B by approximately 10%.
As stated above, the output voltage V.sub.0 of the constant voltage circuit depends on the resistances R.sub.A and R.sub.B and the forward voltage V.sub.BE of the transistor. Therefore, if the amounts of the supplied hydrogen ion are different from each other, the resistances R.sub.A and R.sub.B unequally change, and thus the output voltage V.sub.0 intended by the circuit design cannot be obtained.