1. Field of the Invention
The embodiments described herein are directed to non-volatile memory devices, and more particularly to the fabrication of embedded non-volatile memory device and CMOS logic devices using the same fabrication process.
2. Background of the Invention
Many non-volatile semiconductor memories are based on the well known MOS-type structure. In other words, they comprise a gate structure separated from a substrate by a dielectric layer. Diffusion regions are implanted in the substrate under the corners of the gate structure. When the appropriate voltages are applied to the diffusion regions and the control gate, a channel can be created in the upper layers of the substrate between the diffusion regions and under the gate structure. Carriers, e.g., electrons, can travel the channel between the diffusion regions.
If a sufficient field component is present in the direction of the gate structure, the carriers, e.g., electrons, can be attracted to the gate structure. If the electrons have enough energy to overcome the barrier height of the dielectric layer, then these carriers can be injected through the dielectric layer.
An example non-volatile memory device is the Flash memory device. Flash memory has been widely adopted for a number of non-volatile memory applications. Flash devices were originally introduces as a replacement for Ultra Violet (UV) erasable Electrically Programmable Read Only Memory (EPROM). Today, however, Flash has not just taken over large parts of the One Time Programmable (OTP) and EPROM markets, but it has also become a significant competitor for Electrically Erasable Read Only Memory (EEPROM) and even for some Random Access Memory (RAM) applications.
Due to Flash's origin as a EPROM replacement, most Flash designs are based on cells derived from EPROM technology or EEPROM technology. Accordingly, many flash cell concepts have drawbacks, especially with respect to embedded applications. These drawbacks include low programming speed, high power consumption, high programming voltages, over erase problems, soft write problems, and high process complexity.
This later issue can be especially problematic for embedded applications where memory cells are often closely integrated with CMOS logic and other circuitry, because not only are Flash processes complex, they are also typically incompatible with conventional CMOS processes. Accordingly, including Flash in an embedded application can significantly increase fabrication time and cost.
Several new memory types have been introduced with the aim of overcoming the disadvantages of Flash memory listed above, especially with respect to embedded applications; however, most of these new designs are still incompatible with conventional CMOS processes. Some newer designs have been introduced that are somewhat compatible with conventional CMOS techniques; however, even these designs still require several additional masks. Accordingly, even these newer designs have increased complexity, time and costs compared with conventional CMOS processes.