This invention generally relates to data processing systems, and more specifically, the invention relates to data processing systems including hardware accelerators.
Accelerators are special hardware functional units designed to perform certain operations efficiently, as compared to a general purpose processor, and hardware accelerators are often included in processor-based systems such as computer systems to perform specific, predefined tasks in hardware rather than in software. Traditionally, accelerators perform complex parallel transformations on relatively small input data, which makes the accelerators very attractive for performance enhancement. Additionally, in some cases, the hardware acceleration can be more power-efficient than performing the same tasks in software. Power efficiency can be even greater if the hardware accelerators are incorporated on the same semiconductor substrate (“on-chip”) as the processors. Particularly, integrating hardware accelerators onto multi-core chips such as chip multiprocessors (CMP) and/or chip multithreaded (CMT) processors can be efficient, because the accelerator can be shared among the cores/threads.
Currently, there is a large amount of software over-head associated with dispatching a task to a shared hardware accelerator (e.g. on the order of tens of thousands of processor clock cycles). Access to the hardware accelerator is typically managed by the lowest-level and most-privileged layer of software in the system. Managing access in this fashion helps ensure that the hardware accelerator is shared in a secure fashion (preventing one thread/core from disrupting, and particularly corrupting, the task issued by another thread/core to the hardware accelerator), and also in a fair fashion so that various threads/cores have the opportunity to take advantage of the hardware accelerator. The OS can implement the fairness and security in a non-virtualized environment. In a virtualized environment, the Hypervisor implements the fairness and security.
Accelerators suffer from several problems when they have to operate on a lot of data. For example, passing all the data via commands is inconvenient, and accessing the data from memory gets complicated, as this requires proper address translations on behalf of the calling context. Also, handling exceptions during execution of the accelerator requires special provisions, and accelerators sharing memory management hardware with the core, tend to adversely pollute the cache/TLB that may degrade the performance.