1. Field of the Invention
The present disclosure generally relates to a method for forming a semiconductor device structure and to a semiconductor device structure. Particularly, the present disclosure relates to forming bulk fins comprising a field inducing structure and to according semiconductor device structures.
2. Description of the Related Art
Transistors, such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors, represent the core building blocks for a vast majority of semiconductor integrated circuits. Generally, a FET includes source and drain regions between which a current flow is controlled by applying a bias to a gate electrode overlying a channel region between the source and drain regions. Conventional integrated circuits (ICs), such as high-performance microprocessors, for example, may include a great number of FETs, usually on the order of millions. For such ICs, decreasing transistor size and, therefore, increasing integration density has traditionally been a high priority in the semiconductor manufacturing industry. Nevertheless, transistor performance must be maintained with decreasing transistor size.
A FinFET is a type of transistor that addresses reducing the transistor size while maintaining transistor performance. In general, FinFETs represent three-dimensional transistors formed by thin fins extending upwardly from a semiconductor substrate. In a FinFET, the transistor channel is formed along the vertical sidewalls of the fin, which is also frequently referred to as a double gate transistor, or along the vertical sidewall surfaces and the upper horizontal surface of the fin, leading to a so-called tri-gate transistor. Double gate transistors and tri-gate transistors have a wide channel and, hence, high performance, which may be achieved without substantially increasing the area of the substrate surface required by the transistors because a transistor's performance, often measured by its transconductance, is proportional to the width of the transistor channel.
When considering bulk fins having a bulk substrate formed below an active fin, the doping of the bulk substrate needs to be self-aligned with regard to the active fin. In case the doping of the bulk substrate is not exactly adjusted, such as not sufficiently well aligned with regard to the active fin, the so-called sub-threshold leakage is not controllable because a leakage current (drift current at a gate-source bias) present in the sub-threshold region (or weak inversion region) depends crucially on the threshold voltage and further also depends on the dopant concentration within the channel region. Conventionally, the doping of the bulk substrate is realized by implanting dopants or out-diffusing dopants into the bulk substrate. However, those concepts result in a dopant profile that reaches into the active fin, which at current advanced technology nodes induces unacceptable variations from required dopant concentration profiles.
For SOI fins, i.e., fins in an active region that is formed in a semiconductor layer on an isolating material substrate (so-called silicon-on-isolator configuration or SOI configuration), an increased variability of the threshold voltage due to sub-threshold leakage is avoided. The reason is that a bottom oxide or BOX layer is present under the fins such that a possible leakage path into the substrate as present in bulk fins is cut off in SOI configurations. In general, the mainstream technology focuses on bulk FinFET technologies, partially relying on the SOI FinFET configurations exhibiting other intrinsic issues.
According to recent approaches, efforts have been made to increase the gate area. As the minimal gate length is mandatory in logic related device technologies, this proposal turned out to lack compatibility with logic devices and is, therefore, only realized in the context of SRAM devices. One reason is that the minimal gate length is mandatory to keep the gate delay low and to enable fast designs for logic devices.
Currently, FinFETs are considered to provide the appropriate technology for future nodes for overcoming important issues for strongly-scaled semiconductor circuit structures, such as short channel effects, and for realizing high density designs which are required in current complex semiconductor applications. In the framework of FinFET technologies, a strong scaling can be realized by the fins providing a fully depleted body together with a multi-gate controlling of the channel regions.
In general, a reliable and precise control of the threshold voltage, and in particular a reduced variability of the threshold voltage across FinFETs formed on a semiconductor wafer, may only be achieved by at least strongly reducing, if not suppressing, random dopant fluctuations migrating into fins. In bulk configurations, the body below an active fin requires to be controlled such that almost no bulk leakage appears, which results in a degraded performance of FinFETs. Conventionally, the bulk leakage is controlled by appropriately doping the bulk below the fins by high doping processes.
However, the accordingly-used high doping of the bulk below the fin unavoidably introduces a source for random dopant fluctuations in the active fin because the required ideal doping profile can only be approximated by a smooth function with a tail reaching into the active portion of each fin, such that the tail affects the doping within the active portions of the fins. To this end, the threshold voltage of the FinFETs under fabrication is negatively affected, i.e., its variability is degraded. Especially for SRAM devices, a tight variability strongly relates to the performance of SRAM devices and conventional highly integrated SRAM devices are, therefore, expected to fail in complying presently-demanded dense standards with regards to performance, operation, speed and the like.
Therefore, it is desirable to provide methods for at least reducing, if not suppressing, random dopant fluctuations in current advanced FinFET structures. In particular, it is desirable to provide processes which avoid a random distribution of dopants within active fins during the processing of the fins.