As the semiconductor industry continues to increase performance of integrated circuit devices, physical limits of feature size are presenting new challenges to further improvement. For example, transistor gate lengths are approaching a value below which quantum effects cannot be neglected. Without new strategies, such challenges threaten to slow the rate of increase in device performance.
One such strategy involves increasing the mobility of minority charge carriers in a transistor so that the switching speed of the transistor may be increased without reducing the channel length of the transistor. A promising emerging technology referred to as “Hybrid Orientation Technology” (HOT) involves producing localized or “locally oriented” domains of crystal orientation on a semiconductor substrate. HOT technology operates on the principle that NMOS transistors can operate faster on one orientation of a substrate active area, such as <100>, while PMOS transistors may operate faster on an active area of a different orientation, such as <110>.
Processes to produce wafers incorporating HOT can use direct silicon bond (DSB) wafers. DSB wafers are formed using a handle wafer of a first silicon crystallographic orientation such as <100> and an overlying, cleaved wafer layer having a second crystallographic orientation such as <110> bonded to the handle wafer. A first portion of the <110> cleaved wafer layer is amorphized, for example using an implant of silicon, while a second portion of the cleaved wafer is not amorphized. The amorphized portion is recrystallized to take on the crystal orientation of the underlying silicon handle wafer, in this case <100>. Exposed surfaces of the resulting wafer assembly thus include <100> regions formed from the amorphized and recrystallized cleaved wafer layer comprising the DSB wafer and <110> regions formed from the original cleaved wafer layer which was not amorphized and recrystallized.
In subsequent processing, NMOS devices can be formed on the wafer assembly surface having the <100> orientation while PMOS devices are formed on the wafer assembly surface having the <110> orientation. Transistors formed in this way can have an increased speed because they benefit from being formed on the type of material most conducive to the flow of either electrons (NMOS devices) or holes (PMOS devices).
A method of forming a semiconductor wafer assembly with reduced defects would be desirable.