The present invention relates to a video signal processing apparatus which converts an analog video signal to a digital signal.
Recently, a liquid crystal display device is mainly developed as a video apparatus to replace a cathode ray tube (CRT) display therewith. Video signals received from a personal computer by a display device such as a liquid crystal display (LCD) device are analog signals, and the signal level thereof changes in the unit of dot period. Therefore, a sampling clock signal matching to the dot period is needed for signal processing when the signal is written to a memory, when the signal is displayed on a matrix display device, and the like. However, most personal computers do not have an output terminal of such a sampling clock signal. Therefore, it is necessary to reproduce the sampling clock signal based on horizontal synchronization signal or the like received from a computer or the like. Further, the analog video signal cannot be obtained correctly if it is not sampled at a timing in a dot period when a stable signal is outputted. Therefore, the sampling timing has to be appropriate. Then, an appropriate timing of the sampling clock signal is set manually.
In a video apparatus, the sampling clock signal can be reproduced with a phase-locked loop (PLL) circuit by multiplying the input horizontal synchronization signal and by making both frequency and phase match to those of the input signal. However, the output signal of the PLL circuit has a phase delay because the timing signal required for display control is generated in a logic circuit at a later stage. Because this phase delay depends on the frequency of the input signal, it can not determined uniquely in a video apparatus which can receive various input signals. Therefore, scattering of the timing signal due to phase delay is a problem, especially on sampling.
In order to optimize the sampling point, a video information apparatus disclosed in Japanese Patent laid open Publication 9-149291 (1997) uses auto-correlation of video signals between frames. That is, a delay time of sampling clock signal is changed successively, and the auto-correlation between frames of video signals after analog-to-digital conversion is determined for each delay time. Then, a point having low correlation is adopted as a point at which the signal is changed. Then, by changing the sampling clock delay, an optimum sampling point is determined at a midpoint or thereabout of the signal-changing point. However, this conventional optimizing circuit needs a frame memory in order to determine the correlation value. Therefore, a complicated memory control circuit and high-speed clock signal are needed. A method using multiple A/D converter circuits is known as a method not using a memory. However, this method has a problem that a plurality of delay circuits for sampling clock are necessary.
An object of the invention is to provide a video signal processing apparatus which optimizes the sampling point when an analog video signal is converted to a digital signal.
A first video signal processing apparatus according to the present invention comprises:
a clock generator which generates a sampling clock signal for digitizing a video signal based on an input synchronization signal;
a phase controller which controls phase of the sampling clock signal at one of a plurality of phases in one period of the sampling clock signal;
a first signal generator which generates a first signal when the input video signal is larger than a threshold level;
a first counter which counts the first signal received from the first signal generator in a predetermined time;
a second signal generator which generates a second signal when the input video signal is larger than another threshold level, at a timing according to the sampling clock signal controlled by the phase controller;
a second counter which counts the second signal received from the second signal generator in the predetermined time; and
a controller which makes the phase controller sequentially change the phase of the sampling clock signal in a period of the sampling clock signal, repeats the phase change over one or more periods of the sampling clock signal and sets the phase of the optimum sampling clock signal based on a difference between the output signals of the first and second counters obtained for each of the changed phases.
For example, the controller set the optimum phase of the sampling clock signal according to a plurality of the subtraction results obtained by the subtractor which performs subtraction between the output signals of the first and second counters. Thus, the phase of the sampling clock signal can be controlled by using a simple structure that the times of the cases when the video signal exceeds the threshold level is counted by the two counters. Further, timing control of the output signal of the binarizer circuit and that of an analog-to-digital converter are not needed. Further, high speed sampling clock signal is not needed to control the phase of the sampling clock signal, so that consumption power can be decreased. Further, because the sampling clock signal is not needed after the output of the binarizer circuit and the analog-to-digital converter, the counters can process a high speed signal. Therefore, this decreases consumption power and is advantageous for fabricating a large scale integrated circuit thereof.
In the video signal processing circuit, the optimum sampling clock timing can be set in various ways. For example, the controller sets a phase of the sampling clock signal, at which an absolute value of the count values of the first and second signals is equal to or smaller than a predetermined value, to the phase of optimum sampling clock signal. Alternatively, the controller sets a phase of the sampling clock signal, at which an absolute value of the count values of the first and second signals is equal to or smaller than a predetermined value and the absolute value is smallest, to phase of optimum sampling clock signal. Alternatively, the controller makes the phase controller change sequentially the phase of sampling clock signal in a period of the sampling clock signal, and when the controller continuously detects a phase of the sampling clock signal, at which an absolute value of count values of the first and second signals is equal to or smaller than a predetermined value, the controller sets a center value of the continuously detected phases of the sampling clock signal to the phase of optimum sampling clock signal. Alternatively, the controller makes the phase controller change sequentially the phase of sampling clock signal in a period of the sampling clock signal, and when the controller detects two or more phases of the sampling clock signal, at which an absolute value of count values of the first and second signals becomes maximum, the controller sets a center value of the two or more phases of the sampling clock signal to the phase of optimum sampling clock signal.
Further, in the video signal processing circuit, the controller preferably stops to control the phase controller when the output value of the first counter is equal to or smaller than a predetermined value. Thus, the phase control is stopped for video signal which does not change much, so that malfunction is prevented when the optimum sampling point is detected.
Further, in the video signal processing circuit, the controller preferably further comprises a threshold level controller which controls the threshold level of the first signal generator, and a comparator which compares the output signal of the second signal generator with a different threshold level. The controller decides whether the output value of the first counter is equal to or smaller than the predetermined level. Then, it decreases the threshold levels of the first signal generator and of the comparator when the output value of the first counter is equal to or smaller than the predetermined value. The output of the first counter is equal to or smaller than the predetermined value when the video signal has low level. Then, in such a case, the level for signal detection is decreased, so that the optimum sampling point can be detected even when the video signal has low level.
In a first video signal processing method according to the invention, a sampling clock signal is generated for digitizing a video signal based on an input synchronization signal, and phase of the sampling clock signal at one of a plurality of phases is changed sequentially in one period of the sampling clock signal. The phase setting is repeated over one or more periods of the sampling clock signal, and for each of the phase setting, a first signal is generated when the input video signal is larger than a threshold level and the first signal is counted in a predetermined time. Further, a second signal is generated when the input video signal is larger than another threshold level at a timing according to the sampling clock signal, and the second signal is counted in a predetermined time. Then, a phase of optimum sampling clock signal is set based on differences between the count values obtained by repeating the phase change.
In the video signal processing method, preferably, the phase control is stopped when the count value of the first signal is decided to be equal to or smaller than a predetermined value.
In the video signal processing method, preferably, when the count value of the first signal is decided to be equal to or smaller than a predetermined value, threshold levels for the first and second signals are decreased.
A second video signal processing apparatus according to the invention comprises:
a signal generator which binarizes an input video signal;
a clock generator which generates a sampling clock signal based on an input synchronization signal;
a phase controller which controls phase of the sampling clock signal at one of a plurality of phases in one period of the sampling clock signal;
a delay circuit which delays an output signal of the signal generator by one sampling period;
a maximum detector which receives the output signal of the signal generator and that of the delay circuit and performs subtraction of the two output signals to provide a maximum value of the absolute value of the subtraction; and
a controller which makes the phase controller sequentially change the phase of sampling clock signal by the phase controller in a period of the sampling clock signal, repeats the phase setting over one or more periods of the sampling clock signal to decide the largest value in distribution of maximum values detected by the maximum detector and sets the phase of the largest value to an optimum sampling point. According to this invention, the sampling timing can be controlled by using a simple structure where subtraction results are obtained on video signal around one sampling, and distribution of absolute value of maximum value is detected. Further, by detecting the distribution of absolute value of maximum value, change in signal level can be detected, and correct sampling phase can be set.
In a second video signal processing method according to the invention, a sampling clock signal which digitizes a video signal is generated based on input synchronization signal, and phase of the sampling clock is changed sequentially at one of a plurality of phases in one period of the sampling clock signal. For each of the phase change, the input video signal is binarized, and the binarized signal is delayed by one sampling period, and the binarized signal. The delayed signal are received in a predetermined time and subtraction of the two output signals is performed to detect a maximum value of the absolute value of subtraction. Then, the largest value is decided in distribution of the detected maximum values, and the phase of the largest value is set to an optimum sampling point.
A third video signal processing apparatus according to the invention comprises:
a clock generator which generates a sampling clock signal based on an input synchronization signal;
a phase controller which controls phase of the sampling clock signal generated by the clock generator;
a signal generator which receives a video signal which changes alternately at a frequency of the sampling clock signal and binarizes the video signal at a timing of the sampling clock signal;
a two-phase processor which subjects an output signal of the signal generator to two-phase processing;
a plurality of level change detectors which detect the existence of level change for a plurality of output signals of the two-phase processor; and
a controller which makes the phase controller change phase of the sampling clock sequentially and sets a phase, at which any of the level change detectors does not detect level change, to an optimum sampling point. Therefore, the sampling clock can be optimized at low speed processing.
In a third video signal processing method according to the invention, a sampling clock signal for digitizing a video signal is generated based on an input synchronization signal, and phase of the sampling clock signal is changed sequentially in a period of the sampling clock signal. The phase change is repeated over one or more periods of the sampling clock signal, wherein for each of phase change, a video signal which changes alternately at a frequency of the sampling clock signal is received, the video signal is binarized at a sampling timing of the sampling clock signal, the binarized signal is subjected to two-phase processing, and the level change is detected for a plurality of the output signals obtained in the two-phase processing. Then, a phase, at which the level change is not detected for any of the output signals, is set to an optimum sampling point.
This summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features.