1. Field of the Invention
The present invention relates generally to non-volatile programmable memory, and specifically to programming an array of electrically programmable non-volatile memory cells.
2. Background Information
Non-volatile programmable memories are well known. One of the earliest non-volatile programmable memories were one time programmable (OTP) memory cells which used a diode or transistor with a fuse or an antifuse to program the cell to indicate a logical one or a logical zero when the cell was addressed. Another initially one time programmable memory cell was an electrically programmable read only memory (EPROM) cell. The EPROM was a transistor that was electrically programmable by storing a trapped charge underneath its gate. The trapped charge underneath the gate changed the gate to source threshold voltage of the EPROM. The gate to source threshold voltage was the voltage level above which the EPROM transistor would turn on to conduct a current between its source and drain. The EPROM cell later became erasable by using ultraviolet light radiating through windows in an integrated circuit to reduce or remove the trapped charge so the threshold voltage would return to normal. The UV erasing of the EPROM cell allowed it to be multiprogrammable. However, UV erasing required removal of the integrated circuit from a printed circuit board. To avoid the UV erasing, an electrically erasable programmable read only memory (EEPROM) cell was introduced. The EEPROM memory cell made it possible to program while it remained in circuit on the printed circuit board. In order to be both electrically erasable and programmable, the EEPROM cell included a transistor that uses a floating gate to store a charge. A charge pump triggered upon programming or erasing was needed in the same circuit to generate a high voltage to apply or erase a trapped charge onto or from a floating gate of an EEPROM cell. For a given voltage level, a programming time period is required that is needed to store and erase the charge from the floating gate. Over an array of memory cells this programming time can become significant causing other circuits to wait which delayed the return to functionality of a system.
To reduce the programming time of an array of non-volatile programmable memory cells, it is desirable to program as many EEPROM cells in parallel together as possible. However, there is a limit to the current that can be supplied by a given charge pump. Because programming the EEPROM cell requires a relatively high programming voltage and current to form the trapped charge, the available charge pump current limits how many cells can be programmed in parallel together.
It is desirable to reduce the programming time of an array of non-volatile programmable memory cells and more efficiently program an integrated circuit containing non-volatile programmable memory cells.