Many techniques have been introduced in processor technology to improve the execution performance of code by processors. One such category of techniques that provide simultaneous, or parallel, processing within a computer is known as pipelining. It refers to overlapping operations by moving data or instructions into a conceptual pipe with all stages of the pipe processing simultaneously. For example, while one instruction is being executed, the computer is decoding the next instruction.
With techniques such as pipelining, an issue that can affect performance is the treatment of branches within code. For example, when an execution engine of a processor reaches a branch instruction within the code, it must decide whether to stop all processing until that branch has been evaluated, or continue on one path or another of the branch. Such issues have been resolved to some extent by various techniques called branch prediction. In branch prediction, a given path of the prediction is initially executed in a speculative manner, until it can be determined that the particular path is indeed the correct path. If it is, processing can continue; otherwise, however, the initial execution is wasted.
Thus, during the execution of a program, the execution engine is rarely surprised by the arrival at a branch. However, once a basic block of code is entered, every instruction in that basic block is enabled for execution. Unfortunately, since branches tend to exist at the bottom of basic blocks, the engine must fetch all intervening sequential (that is, non-branch) instructions before encountering the branch.
One particular type of branch prediction involves the insertion of additional hint instructions in the basic block of code. These additional instructions are problematic, however.
The latency at which these instructions take effect, for example, may vary with the execution engine such that their position in the code should vary also. For these and other reasons, there is a need for the present invention.