This invention relates to a connecting structure of an electronic part, a production method thereof and an electronic device using the structure. More particularly, the present invention relates to a method and a structure for connecting a wiring substrate flexibly with an electronic part such as an LSI chip having a large number of very small connection terminals and to an electronic device structure using the connection method and structure.
Conventional methods of electrical connection of LSI chips can be broadly classified into (1) a wire bonding method, (2) a tape carrier bonding method (or "TAB" (Tape Automated Bonding)) and (3) a flip chip bonding method (Reference 1: Nihei et al., "Semiconductor Handbook", p. 128, published by Science Forum K.K., 1986, Sept. 25).
Among the three connection methods described above, the method (1) and (2) can be applied only to those chips which have a structure wherein the input/output terminals of the LSI chip exist at the peripheral portions of the chip (see Table 3 of Reference 1). The reason in detail will be described later.
On the other hand, the flip chip bonding (3) can be applied to those chips which have a structure wherein connection terminals are disposed not only at the peripheral portions of the LSI chip but also on the entire surface inclusive of the central portion of the chip (hereinafter referred to as a "grid-like terminal disposition"), too.
This method comprises disposing solder bumps at a height of from 100 to 125 .mu.m on the surface of terminals of an LSI chip to be connected, placing this chip on a wiring substrate and re-heating and melting the solder to connect the chip. This method is known by an abbreviation "C-4 method" (Solid Logic Technology) or "CCB method" (Controlled Collapse Bonding).
FIG. 28 of the accompanying drawing (cited from Reference 2: Honda et al., "High Density Packaging Handbook", p. 238, 1986) is a schematic view showing the principle of the connection mechanism of the CCB method. According to this CCB method, a connection medium (a solder 281 in this case) does not extend beyond the size of the LSI chip in its transverse direction (horizontal direction) and one connection medium (or the solder) does not much have extension in the horizontal direction. Therefore, this method is advantageous for connecting and packaging continuously a large number of LSI chips having the grid-like terminal disposition adjacent to one another.
A ultra-high speed electronic computer, for which high density packaging of a large number of chips is required, such as CTM (Thermal Conduction Module) of IBM can be cited as an application example of the connection and packaging of the chips by this CCB method (see FIG. 27, cited from Reference 2, p. 240).
Packaging of LSI chips having a large number of connection terminals is essentially necessary in electronic computers and high-class electronic devices in the same way as in the example described above. In recent years particularly, the number of terminals of logic LSIs has exhibited a remarkable increase as can be seen from FIG. 26 (cited from Reference 1) and the recent trend is to use the chip structure having the grid-like terminal disposition from the aspects of high density disposition of terminals and their power source characteristics.
As described previously, the wire bonding method or the tape carrier bonding method (hereinafter referred to as the "TAB method") cannot be applied to the logic LSI chips whose terminals are disposed in the grid-like form and in a high density for the following reasons.
As shown in FIG. 25 (cited from page 307 of Reference 1), the wire bonding method extends thin wires of Au or Al from the therminals of the LSI chips to its outer periphery in order to make connection. Therefore, (1) a space is necessary in order to extend and connect the leads (wires) to the outer periphery of the chip, and this means that an excessive space for the connection is fundamentally necessary. (2) Connection of the leads is carried out by use of a device referred to as a "wire bonder" but since the lead wires are bare wires having no insulation coating, the wires come into mutual contact if a large number of wires are connected to the terminals at the center of the chip. For this reason, the wire bonding method is not suitable for the connection of the chips having a high density grid-like terminal disposition such as the logic LSI chips described above.
As shown in FIG. 24 (cited from page 277 of Reference 1), the TAB method disposes the leads for wiring on a film (carrier) and connects the chips through the leads by use of this film as a bulk.
According to this TAB method, excessive lead portions as bonding margins must be secured in order to fix the lead wires to the film and it is not easy to shorten the lead length. In other words, in the conventional film carrier, the intermediate portion between the outer leads and the inner leads is elongated and the leads are fixed to the film base at this portion. The inner leads are wired linearly towards the inside. Therefore, the LSIs that can be connected are limited to those LSI chips which have a relatively small number of terminals that are disposed only at the peripheral portions of the LSIs. However, the number of terminals is very great (at least 500 on about 10 mm square) in the logic LSIs. Moreover, the terminals are uniformly disposed in the grid form not only at the peripheral portions of the LSI chips but also at their center, as described already.
Accordingly, the shape wherein the inner leads are linearly wired plane-wise towards the inside as in the TAB method cannot connect the logic LSI chips having the grid-like terminal disposition.
The problems with the above-mentioned two methods can be summarized as follows: (1) an excessive space more than the occupying area of the LSI chip is necessary, and (2) these methods cannot be applied to the chips having the structure wherein the terminals exist in the grid form to the center of the chip as in the logic LSI chips.
For the reasons described above, it is only the flip chip bonding method as typified by the aforementioned CCB method or the like that can connect and package compactly and in a high density the LSI chips having the grid-like high density terminal structure such as the logic LSI chips.
In the flip chip bonding method such as the CCB method, however, connection is made directly by the ball-like solder. Fundamentally, therefore, the method is a method having a rigid (hard) structure. This rigid structure has recently resulted in the following disadvantages. Hereinafter, the situation will be described.
Recently, the development of chip connection technique having a soft or flexible structure has been required in the field of high performance electronic apparatuses such as an enelectronic computer.
In this field, the connection method having the rigid structure such as the CCB method can no longer satisfy the requirement.
The reason why such an LSI chip connection method having the flexible structure is required is, in the case of the electronic computer, associated with the calculation speed which is one of the most important performance factors of the computer. When viewed on the side of hardware (apparatus) of the electronic computer, its calculation speed is determined by the performance of LSI and the performance of a wiring substrate on which the LIS is mounted.
As to this wiring substrate, a multi-layered wiring substrate made of ceramics (alumina, mullite, etc.) and using W (tungsten) and Mo (molybdenum) as the wiring material has recently been developed and put into practical application.
The wiring substrate described above is effective for connecting and packaging the LSI chips in a high density and for shortening the total wiring length of wirings that have been increasing. However, from the aspect of the transmission performance of electrical signals, the following drawbacks are left unsolved.
(1) The ceramic substrates have generally a high dielectric constant (alumin .epsilon.: 9.about.10). Therefore, parasitic charge appears on the interface between the substrate and the wirings and decreases the transmission speed of electrical pulse signals.
(2) W and Mo have electrical resistances greater than those of other wiring materials such as Cu (copper). This deteriorates the waveform of the electrical pulse signal so that it becomes difficult to shorten the time interval between the pulses to be transmitted and this results eventually in the difficulty in increasing the transmission capacity and transmission speed of the pulse signals.
In order to solve these problems, wiring substrates using an organic material having a low dielectric constant such as a polyimide resin (.epsilon..apprxeq.3) or the like and Cu for the wiring material have been developed or these is a trend to use them.
However, the coefficient of linear thermal expansion of the high performance wiring substrate described above is greater than that of a ceramic such as alumina and the difference between the substrate and Si as the principal component of the LSI chips (herein after referred to as the ".alpha. difference") is as great as from 100 to 130.times.10.sup.-7 /.degree.C.
Accordingly, if the LSI chips are directly soldered to the substrate as in the conventional LSI chip connection method, the following disadvantage develops. Namely, if the LSI chips are fixed to the wiring substrate using the organic material and Cu, thermal stress develops at the solder-connection portion because the .alpha. difference is great so that the solder-connection portion cannot withstand the strain due to the thermal stress and is broken, thereby causing disconnection.
Therefore, if the LSI chips are connected to the wiring substrate having a large coefficient of thermal expansion as described above, a method which can either absorb or mitigate the thermal stress-strain resulting from the .alpha. difference between them, that is, the LSI chip connection method having the flexible structure, must be employed.
When the ceramic wiring substrate is used as in the prior art technique, the coefficient of thermal expansion of the ceramic wiring substrate such as alumina (60.about.65.times.10.sup.-7 /.degree.C.) is not in complete matching with the coefficient of thermal expansion of the LSI chips (30.times.10.sup.-7 /.degree.C.) Particularly in recent years, the thermal stress-strain due to the .alpha. difference tends to increase with the increase in the size of the LSI chips (from 10 mm square to 16 mm square), and the strain of the thermal stress cannot be borne by the connection by the solder alone. Therefore, in the case where the LSI chips are connected to the ceramic wiring substrate in accordance with the prior art technique, too, the LSI chip connection method having the flexible structure which can absorb or mitigate the strain resulting from the thermal stress has become necessary.
The state of art described above is altogether shown in FIG. 23. In this drawing, the ordinate represents the size of the LSI chip, the abscissa does the .alpha. difference between the wiring substrate and the LSI chip and oblique line does a limit value of life by the CCB connection method. The drawing is prepared on the basis of the experimental result of the CCB bonding method carried out by the inventors of the present invention.
It is obvious from the description given above that durability has reached the limit by the mere CCB connection method having the rigid structure.
Now, the drawbacks of the heretofore well known chip connection technique will be summarized as follows.
(1) The wire bonding method and the TAB method cannot connect and package the chips compactly in the horizontal direction.
(2) The CCB method cannot connect and package the chips in the flexible structure.
In order to solve the drawbacks of the conventional LSI chip connection technique, particularly the problem of item (2) described above, Ehrfelt proposes a method in Japanese Patent Laid-Open No. 110441/1986.
However, this method involves the following problems.
(1) The method does not provide deformability (freedom) and flexibility (spring property) in a perpendicular (Z) direction at the junctions between the LSI chips and the wiring substrate.
This means that a disadvantage occurs at the contact portion between the back (non-electrical connection surface) of the LSI chip and a heat transfer block after the LSI chips are connected to the wiring substrate. In other words, each of a plurality of LSI chips is ordinarily connected with some corrugation or inclination (or not under the completely horizontal state). Therefore, a gap (or a contact defect) occurs on the contact interface between the chip and the heat transfer block. To solve this contact defect, it is customary to push the back of the chip by a rod equipped with a spring mechanism (a heat radiation stud) from the side of the heat transfer block (see FIGS. 22 and 27 cited from References 1 & 2).
However, this method reduces the cooling effect and makes the structure of the heat transfer block more complicated.
In contrast, a method which provides the LSI chips with flexibility (spring property) in the perpendicular (Z) direction can provide good contactability and can simplify the conventional heat transfer block.
However, the conventional connection method by soldering alone by the CCB method and the Ehrfelt's connection method described above hardly has, or does not have, sufficient flexibility.
(2) The Ehrfelt's connection method needs two junctions per terminal of the LSI chip.
In accordance with the afore-mentioned Japanese Patent Laid-Open No. 110441/1986, each terminal of the chip must be connected at upper and lower two points when the chip is connected to the substrate. This results in the increase in the number of joints and is not preferable from the aspects of the chip connection work, reliability of electrical connection and electrical resistance. This is one of the problems which should be solved as the subject matter of the present invention. In other words, in high density packaging where a large number of chips are mounted to one substrate, one terminal is preferably connected to the substrate electrode at one position. FIG. 21 shows the structure of the coupling elements where one terminal is connected at two position by the Ehrfelt's method (FIG. 21(a) is a perspective view and (b) is a plan view) and the state where the electrode of the chip is connected to the substrate electrode by use of this coupling element (FIG. 21(c) is a sectional view). Here, the coupling element consists of two pins 60a, 60b that are parallel to each other and connected mutually by a leaf spring 60. In FIG. 21(c), one 60b of the pins of the coupling element is connected electrically to a conductor path 65 of the ceramic substrate 62 and the other pin 60a is connected electrically to the electrode 64 of the chip 61 through the solder 63. Due to this structure, one terminal 64 of the chip is connected to the conductor path 65 of the substrate through the two positions of the pins 60a and 60b of the coupling element and the number of joints becomes two.
Accordingly, even if the flexible structure connection method is employed, it is desired that connection of the LSI chip is completed by single soldering work (simultaneously with a large number of terminals) as has been made by the conventional CCB soldering.
According to the Ehrfelt's connection method, high energy (synchrotron radiation rays are used in Japanese Patent Laid-Open No. 110441/1986 described already) is necessary for producing the leaf spring and the entire production process becomes too complicated to practise it easily.
On the other hand, an attempt of connecting the LSI chips much or less in the flexible structure is proposed by Honda in Japanese Patent Laid-Open No. 121255/1982 separately from the Ehrfelt's method described above.
As shown in FIG. 20, this method forms wiring films 71a, 71B on the LSI chip (electrical circuit element) 70 itself, disposes the metal bumps (solder) 72A, 72B at their tips and connects this LSI chip to the wiring substrate 74. According to this proposal, further, a film 73 (PiQ: film of an organic material) referred to as a "spacer" is removed before or after the chip is connected and thermal fluctuation strain (as described in the specification of the reference) is absorbed by the wiring films and the metal bumps.
According to this proposal, the following points (1) to (4) are not sufficiently clear and moreover, there is the drawback in that elongation or stretchability does not exist in a specific horizontal direction as will be described elsewhere.
(1) the shape and size of the wiring films 71A, 71B
(2) formation of the wiring films and the spacer and etching conditions (etachant, etching time, etc.)
(3) definite process conditions inclusive of items (1) and (2)
(4) result of numeric evaluation of the invention
Accordingly, (1) it is not possible to judge what design should be made of the dimension (width, thickness, length and overall shape) of the wiring films 71A, 71B in order to prevent the destruction of solder when "mechanical extension and contraction" (as described in the specification) occurs due to thermal strain of what extent, and (2) it is not easy to set up the plan of the sequence of works such as preparation of chemicals, film formation, etching, and the like, in order to carry out this proposal
Furthermore, assuming that the shape of the wiring films 71A, 71B in FIG. 20 is rectangular, this method involves the drawback of the connecting structure in that stretchability hardly exists in the inner horizontal direction in the drawing. In other words, in the step of connection and cooling where the temperature of the solder bumps 72A, 72B drops from the CCB soldering temperature (from about 270.degree. to about 330.degree. C.) to the room temperature, for example, the wiring films 71A, 71B receive vigorous tension (tensile strength) towards the inside in the drawing and result in disconnection.
Still another method is proposed by Amano (Japanese Patent Laid-Open No. 136830/1988). This method is shown in FIG. 19.
According to this method, too, the solder connection portion inevitably receives strong tensile stress in a specific horizontal direction. In other words, a conductor layer 80 gets elongated greatly in an outer horizontal direction when the substrate 81 is heated by heat dissipation of the chip or the like. However, elongation of the LSI chip 83 is not much great, so that the solder connection portion 82 is pulled in the outer horizontal direction. Accordingly, this method involves the structural drawback in that tensile force develops in the specific horizontal direction in the same way as the Honda's method (though the direction is opposite).
As described above, the methods of Honda and Amano are not free from the drawback of the connecting structure as they do not consider how to mitigate the tension in the specific horizontal direction.
As described above, in the industrial field where the LSI chips are connected electrically and high-class electronic apparatuses are packaged and assembled, (1) the LSI chips having a large number of connection terminals such as the logic LSIs (2) must be disposed continuously in a high density and (3) their connection portions must be connected in the flexible structure in all directions. In contrast, the drawbacks of the conventional connection technique can be summarized as follows.
1. The wire bonding method and the TAB method cannot satisfy the requirements (1) and (2) described above.
2. The CCB method cannot satisfy the requirement (3) for the flexible connecting structure.
3. The Ehrfelt's proposal (Japanese patent Laid-Open No. 110441/1986) does not have freedom or spring property in the vertical direction.
4. The proposals of Honda and Amano (Japanese Patent Laid-Open Nos. 121255/1982 and 136830/1987) do not have sufficient freedom or spring property in the specific horizontal direction.
5. Furthermore, there remain many difficulties in carrying out the Ehrfelt's method.
Hereinafter, the difficult conditions to be overcome, or the technical problems to be solved in order to accomplish the objects of the present invention, will be summarized.