1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device wherein data stored therein can be read out in any selected one of page mode and nibble mode.
2. Description of the Prior Art
One of conventional ways to read out data in dynamic semiconductor memory devices is a so-called page mode. In this mode, one of word lines in a memory array is selected and then a desired one of digit lines is sequentially selected, whereby data are sequentially read out from memory cells at intersections of the selected word lines and digit lines. Referring to FIG. 1 which is a timing chart for operation events in this page mode, the mode will be discussed in detail.
(i) An external row address strobe signal (Ext.RAS) applied to the semiconductor memory device from the external of the device becomes active "low" state, so that an internal row address strobe signal (Int. RAS, referred to as "RAS" hereinafter), or the output of an internal RAS buffer circuit changes from low to high. In response to this change, an internal row address is generated at address buffer circuit (A.sub.O -A.sub.i), and one of word lines corresponding to the row address is selected.
(ii) An external column address strobe signal (Ext. CAS) externally applied to the semiconductor memory device is placed into active "low" state, so that an internal column address strobe signal (Int. CAS, referred to as "CAS" hereinafter) or output of an internal CAS buffer circuit changes from low to high. In response to this change, an internal column address is generated at the address buffer circuits, and one of digit lines which corresponds to the column address is selected. At this stage of operation, the one of the word lines and the one of the digit lines are selected so that data are read out from a memory cell at the intersection of the two lines.
(iii) After that, Ext. CAS is brought into inactive "high" state while the row address is fixed low. Using the transition as a trigger, an internal CAS signal (Int. CAS) outputted from the internal CAS buffer circuit changes from low to high. A column decoder and a data output circuit are reset in response to the change.
(iv) When Ext. CAS becomes low again, a column address different from the previous one is generated to select one of the digit lines corresponding to the new column address. Since the row address is not changed during these operation, data are read out from a memory cell at the intersection of the previously selected word line and currently selected digit line.
In the page mode, data stored in the memory cells which are connected to the selected word line can be sequentially read out by sequentially selecting the digit lines by means of column addresses.
Meanwhile, a new method of reading out data, called "nibble mode", has recently been suggested and studied for practical use. For example, this nibble mode is disclosed in Digest of Technical Papers, IEEE International Solid-State Circuits Conference, 1981, pp. 84 by S. S. Sheffield et al. In the nibble mode, when one of row addresses and one of column addresses are specified, a nibble or 4 bits of data are read out from a memory array. Referring to FIG. 2 showing a timing chart of the operation in the nibble mode and FIG. 3 showing an example of a circuit formed on a 64K bit dynamic RAM for the nibble mode, data reading operation in the nibble mode will be discussed in detail.
(i) Ext. RAS is brought into active "low" state so that the internal RAS buffer circuit RB becomes operable to change its output Int. RAS from low to high. In response to this transition, address buffer circuits (A.sub.0 -A.sub.7) become operable to generate a row address signal which in turn is applied to a row decoder RD which decodes the row address signal to select one of 256 word lines (WL.sub.0 -WL.sub.255).
(ii) Ext. CAS then changes to low. In response to this transition, the internal CAS buffer circuit CB becomes operable to change its output CAS from low to high. The address buffer circuits (A.sub.0 -A.sub.7) become operable in response to such transition to generate a column address signal. Out of the outputs of the address buffer circuits, the outputs of A.sub.0 -A.sub.5 are fed to a column decoder CD which decodes the signal to select four of 256 digit lines. Data are read out from four memory cells MC at the intersections of the one of the word lines selected in (i) above and these four digit lines. The 4 bit data are loaded into data registers (DR.sub.1 -DR.sub.4) by way of four pairs of I/O lines (I/O.sub.1 -I/O.sub.4), respectively. The remaining outputs of the address buffer circuits A.sub.6 and A.sub.7 are fed to data select shift registers (DS.sub.1 -DS.sub.4). These 2 bits select and activate one of the data select registers (DS.sub.1 -DS.sub.4), rendering conductive one of four switches (SW.sub.1 -SW.sub.4) connected to the activated one of the data select registers. The data stored in the data register connected to the switch in such conductive state are outputted through an output buffer circuit OB.
(iii) An indicated in FIG. 2, Ext. CAS changes to high and then to low while Ext. RAS is held low. In response to the output of the CAS buffer circuit the shift register becomes operable and the switch previously in conductive state becomes nonconductive. The next switch then becomes conductive so that data stored in the data register connected to that newly conductive switch are delivered through the output buffer circuit OB. For example, assuming that SW.sub.1 is initially selected and rendered conductive by the outputs of A.sub.6 and A.sub.7, the shift register advances one step through the this procedure and SW.sub.1 becomes nonconductive and SW.sub.2 conductive.
In this manner, the shift registers (DS.sub.1 -DS.sub.4) are operated by changing Ext. CAS in the order of high.fwdarw.low high.fwdarw.low while Ext. RAS is held low, whereby data in the data registers (DR.sub.1 -DR.sub.4) are sequentially read out. The column address need be given at the first step but not every step. In other words, since there is no need to give the column addresses from time to time in the nibble mode unlike the page mode, operation of the internal CAS buffer circuit CB and the address buffer circuits (A.sub.0 -A.sub.7) is not necessary from time to time. The nibble mode allows high speed data reading as compared with the page mode. The nibble mode is however disadvantageous in that only 4 bits of data as selected by the column address at the first step may be read out.
In other words, the page mode and the nibble mode have the inherent advantages and disadvantages, respectively, and it is very convenient if the semiconductor memory device is selectively operable in the page mode or the nibble mode. Although the page mode and the nibble mode are totally different in operational mode in the semiconductor memory device, it is noted from FIGS. 1 and 2 that the timing relationship between Ext. RAS and Ext. CAS in both the modes is completely identical. With the conventional semiconductor memory device, selective use of the two modes is impossible and only one of the two modes is available.