The present invention relates to a testing method for an array substrate for use in an active matrix type liquid crystal display device.
In general, since liquid crystal display devices are light in weight, thin and of low power consumption, they have been widely used as display elements of televisions, portable type information terminals or graphic displays, etc. Especially, since an active matrix type liquid crystal display device (hereinafter referred to as TFT-LCD) employing thin film transistors (hereinafter referred to as TFTs) as pixel switching elements is excellent in high speed response and suited for a high resolution capability, such a structure is focused to be a promising display device for realizing a high quality image, a large display size and a full color image of a display screen.
FIG. 1 is a circuit structural view of an array substrate for use in a general TFT-LCD of a related art. The array substrate 10 is formed with scanning line electrodes G1, G2, . . . Gm (hereinafter generally referred to as G) and video signal row electrodes D1, D2, . . . Dn (hereinafter generally referred to as D) which are wired in a matrix form, with TFTs 11 being formed as pixel switching elements at respective intersecting points between these line electrodes G and row electrodes D. The TFTs 11 have gates commonly connected to the line electrodes G for each line and sources commonly connected to the row electrodes D for each row. Further, drains of the TFTs 11 are connected to pixel electrodes 12 and also connected to supplemental capacitors 13 to which the respective pixel electrodes 12 are electrically connected. The respective supplemental capacitors 13 are commonly connected to a supplemental capacitor electrode 14 and applied with a given voltage potential.
In a subsequent description, a unit of display to be defined in a scale of the pixel electrode 12 is referred to as a pixel element, with a region in which a plurality of pixel elements are located being referred to as a pixel section.
Although not shown in FIG. 1 since FIG. 1 shows an electrode structure of an array substrate prior to assembling the same into a liquid crystal panel, a counter substrate, which is not shown, placed on the array substrate with a given distance in opposed relationship is formed at its entire surface with counter electrodes, with a liquid crystal layer being sandwiched between both the substrates.
In FIG. 1, further, ends of the line electrodes G1, G2, . . . Gm are connected to a line electrode driver circuit 15, and ends of the row electrodes D1, D2, . . . Dn are connected to a row electrode driver circuit 16. The line electrode driver circuit 15, the row electrode driver circuit 16 and the supplemental capacitor electrodes 14 are supplied with various timing signals, image signals and a power supply voltage from an external drive circuit substrate via input and output terminal groups (hereinafter referred to as probing pads) 17.
Control of the TFTs 11 which serve as the pixel switching elements during a normal display mode is carried out in a manner described below. In a liquid crystal panel structured using the above described array substrate, when line election signals are applied to the line electrodes G1, G2, . . . Gm from the line electrode driver circuit 15 in a sequence starting from an upper electrode toward a lower electrode in synchronism with a horizontal scanning cycle, the TFTs 11 are turned on at timings in which the line selection signals are applied to the line electrodes G. When video signals are applied to the row electrodes D1, D2, . . . Dn from the row electrode driver circuit 16 in synchronism with the line selection signals, the video signals applied to the row electrodes D are written in the pixel electrodes 12 via the TFTs 11. As a result, the liquid crystal layer (not shown) sandwiched between both the substrates comes to be applied with a voltage depending on a difference between a signal voltage of the video signal written in the pixel electrode 12 and a counter voltage applied to the counter electrode (not shown), permitting the liquid crystal layer to optically respond in dependence on the magnitude of such a voltage to provide a display.
The above structure shows an example in which respective driver circuits of the line electrodes and the row electrodes are incorporated on the array substrate (glass substrate) and is called as p-Si (polycrystal silicone) TFT-LCD because of semiconductor material used for transistors. In contrast, a structure that uses a-Si (amorphous silicone) as semiconductor material is referred to as an a-SiTFT-LCD.
FIG. 2 is a circuit structural view of an array substrate for use in a general a-SiTFT-LCD of a related art, with like parts bearing the same reference numerals as those of FIG. 1. Since a-Si is inferior to p-Si in a transistor characteristic and, hence, the TFTs can not be minimized in size, it is difficult to incorporate the driver circuits on the array substrate. Accordingly, an array substrate 20 of a-SiTFT-LCD is structured with only a pixel section, with driver circuits being formed as driver ICs on an external drive circuit substrate that is not shown. Electrical connection between the driver circuits and the array substrate 20 are established using a technology such as TAB (Tape Automated Bonding) with probing pads 18, 19 formed on the array substrate 20.
In the meantime, in a later stage when a manufacturing step of the array substrate has been terminated, it is a usual practice to conduct an array test in order to confirm whether the manufactured array substrate properly functions. Such an array test has its own objectives such as: (a) preventing a defective array from being delivered to a cell step (subsequent step); (b) conducting a feed back to provide an improved process in the array step; and (c) providing an improved yield rate through an interlocking operation with a repair device. With the p-Si array substrate set forth above, a test is conducted for the pixel section and the driver circuits contained in the substrate, whereas with the a-Si substrate, only the pixel section is subjected to test. In this connection, typical testing processes for the pixel section are categorized in the following two technologies
(1) an integrator process: of charging the supplemental capacitors (hereinafter suitably referred to as Cs capacitors), discharging the capacitors after an elapse of a fixed time interval, implementing integration of current flowing at that time instant for conversion into the amount of charge stored in the Cs capacitor, and measuring the amount of charge for thereby discriminating a quality of the pixel elements.
(2) a voltage detection process: of charging Cs capacitors forming pixel element capacitors during a test mode, discharging the capacitors after an elapse of a fixed time interval, and measuring a voltage potential difference occurring at the time instant for thereby discriminating a quality of the pixel elements.