The present invention relates to a method and structure for reducing effects of noise coupling in signal lines of Content Addressable Memories (CAM""s), and more particularly to a bit line structure that reduces the impact of noise to improve sensing of CAM cells.
One problem with high integration density in semiconductor memories is that the operation characteristics of the memory device are adversely influenced by the coupling capacitance between bitlines, also referred as coupling noise. A memory array includes a number of word lines and complementary bitline pairs. Sensing amplifiers are provided in association with each bitline pair. As is known coupling capacitance exists between the individual bitlines of a certain bitline pair, and the adjoining bitline pairs. The noise is caused when there is a change in the voltage present in a particular bitline, such as when there is a change in logic value. Due to capacitive coupling, a change in one bitline may cause a similar change in a neighboring bit line, which is not intended to change. Such an undesired change in a bitline caused by capacitive coupling from a neighboring bitline is referred to as coupling noise. When noise appears across neighboring bit lines, the noise may be conducted to the sensing amplifier, and may erroneously be interpreted as data, lack of data, or undesirably modified data
It is well known that by twisting bitline structures in memory arrays such as static random access memories SRAMs, or dynamic random access memories DRAMs, the noise induced into the bitline structure can be effectively lowered or canceled.
A similar problem is found in CAM devices where there is an increasing demand for higher integration density. The smaller dimensions result in an increase in bitline-to-bitline capacitance. In a CAM, however each column of storage cells is coupled to a search line in addition to being coupled to bitlines. The search lines are used for simultaneously comparing the bits of a search word stored in a compare register with the bits of data words stored in the cells. Wile binary CAMs are similar to traditional memories, ternary CAMs store data in pairs of storage elements, each pair called a ternary cell comprised of storage for two binary digits B0 and B1. This allows the ternary cell to store three logic states namely logic xe2x80x9c0xe2x80x9d, logic xe2x80x9c1xe2x80x9d and xe2x80x9cdon""t carexe2x80x9d.
The ternary CAM cell can be of two types namely DRAM or SRAM. In a DRAM-based CAM cell, each column of storage elements is coupled to a single bitline. That is, there are two bitlines per column of ternary CAM cells. In the case of an SRAM-based ternary CAM cell, each column of storage elements is coupled to a complimentary pair of bitlines. Thus the ternary SRAM CAM has two pairs of complementary bitlines per column of ternary CAM cells.
Bitlines also each have an inherent capacitance that varies with their dimensions. Ideally, each bitline is constructed to have essentially the same inherent capacitance in order to allow for consistent sensing across the entire memory.
Simply applying traditional twisted bitline techniques to such ternary CAM cells is not possible. It is known in the art that for ternary cells, to express a ternary logic value in particular, the position of the stored bit is important. The following table represents how the bits are stored in each half of the ternary cell:
If the concept of twisting the bitlines as applied to a binary CAM cell is applied to a ternary CAM cell, the results would be that the bits will be stored in a different position. Since the position of the bit is crucial for the correct performance of the CAM, applying the prior art and by just twisting the bitlines will result in reading wrong data. Someone skilled in the art will notice that a solution to this problem can be twisting the search lines as well. Such solution while possible, is not feasible in a high density device as a CAM, where saving area is a must. For this reason, conventional ternary CAM devices do not employ the twisted bitline architecture as a result.
Accordingly, it is an objective of this invention to provide a method and structure for minimizing noise effects in a CAM device.
It is another objective of the invention to provide a method for structuring bitlines in a manner that ensures equal capacitance between adjacent bitlines.
In accordance with this invention there is provided a method for reducing the coupling noise in a Content Addressable Memory (CAM), the CAM having a first bitline pair and a second bitline pair, both pairs aligned along a first axis; a first memory cell connected to the first bitline pair and a second memory cell to the second bitline pair, having a first match line and a first word line aligned along a second axis, the it match line and the first word line connecting the first and the second memory cells defining a first row in a first column; having a second row adjacent the first row, the second row comprising a third cell and a fourth cell, the third and fourth cells connecting the first and second bitline pairs and a second word line and a second match line, the method comprising arranging the first memory cell in a first orientation and the second memory cell in a second orientation, wherein the second orientation being a first axis mirror image to the first orientation; segmenting the first and second bitline pairs between the first row and the second row; adding a first twisting structure to the first bitline pair and a second twisting structure to the second bitline pair; arranging the third cell in a third orientation, the third orientation being rotated 180 degrees with respect to the first orientation; and arranging the fourth cell in a fourth orientation, the fourth orientation being rotated 180 degrees with respect to the second orientation.
In accordance with another aspect of the invention there is provided a semiconductor memory device having a noise effect reducing structure, said memory device comprising:
a first bitline pair and a second bitline pair, said first and second bitline pairs aligned along a first axis;
a first memory cell connected to said first bitline pair and a second memory cell connected to said second bitline pair;
a first match line and a first word line aligned along a second axis, said first match line and said first word fine connecting said first and said second memory cells defining a first row in a first column;
a second row defined above said first row, said second row comprising a third memory cell and a fourth memory cell, said third and fourth memory cells connecting said first and second bitline pairs and a second word line and a second match line;
said first bitline pair comprising a twisted structure between said first row and said second row;
said second bitline pair comprising a second twisted structure between said first row and said second row;
said first memory cell having a first orientation and said second memory cell having a second orientation, wherein said second orientation is a mirror image of said first orientation;
said third memory cell having a third orientation, said third orientation being rotated 180 degrees with respect to said first orientation; and
said fourth memory cell having a fourth orientation, said fourth orientation being rotated 180 degrees with respect to said second orientation.