1. Field of the Invention
The present invention relates to a semiconductor integrated circuit with cells arranged on a semiconductor substrate and with wiring for the cells, and more specifically to a semiconductor integrated circuit, a cell library and a cell frame standardization program, which reduces operation of replacing a cell, arranged after cell layout, by a cell with the same logic but a different driving capability.
2. Description of the Related Art
In designing a semiconductor integrated circuit of interest in the present invention, arrangement, or layout, of a plurality of cells on a semiconductor substrate is carried out and a semiconductor integrated circuit as a chip is produced. In the layout operation of cells on the chip, first, cells are arranged, while the estimation to prevent timing error is carried out, and wiring between cells is performed.
Later, capacitance between wiring and wiring resistance on the chip is extracted, the amount of signal delay is calculated, and timing error is examined. When the timing error is detected, in order to modify layout, a process of replacing the arranged cell with a cell with the same logic but different driving capability is carried out.
The cells with different driving capabilities are not made to have the same cell size and the terminals are not at the same position though they have the same logic in general. For that reason, when replacing a cell with a cell with high driving capability, or a cell with a large cell size generally, many of those cases require moving of the cell. When moving the cell, or when, though not moving, positions of terminals in the cells are different, it is required to modify wiring connected to the terminals. Then, operation of re-extraction of capacitance between wirings and wiring resistance is required when modifying the wiring. Here, problems raise that operations such as modification of wiring and re-extraction of wiring resistance takes a lot of time, and that the amount of operations for timing error correction increases.
The followings are reference documents of prior technology relating to such designing of a semiconductor integrated circuit and its layout. Patent Document 1: Japanese laid-open disclosure public patent bulletin No. 08-181216 “Library Group and Semiconductor Integrated Circuit Using Library Group” Patent Document 2: Japanese laid-open disclosure public patent bulletin No. 2003-282711 “Semiconductor Integrated Circuit and its Designing Method”
Patent Document 1 describes a technology in which a basic cell is configured by transistors with narrow channel width, providing a library group of functional block and logical gates, which allows designing without re-arrangement, re-wiring or modification of logical gates by making logical gates with the same logic function but different load driving capabilities and position of input/output terminals of a functional block the same.
Patent Document 2 discloses a semiconductor integrated circuit in which function cells are comprised of buffers and inverter cells, when arranging the function cells, the function cells are arranged by making cell size look artificially larger, regions of a wiring prohibiting region etc. are provided on a differential region between the actual cell size of the function cell and the sell size which is made to look artificially larger, and regardless of high or low driving capability, the same logic function cell has a structure of the same size and the same input and output terminal position.
In the above conventional technologies, in order to reduce operation for modifying wiring or re-extracting wiring resistance etc., a method, for making cell size and terminal position the same for cells with the same logic function but different driving capabilities, is employed. However, the range of the driving capability of the cell with the same logic is wide in general. Then, it is an insoluble problem that, when cell size and terminal position are made the same for all cells with the same logic within the range, the cell size becomes extremely large as a result, and chip size also becomes redundantly large. As the chip size becomes large, manufacturing cost rises, and from that point also, it is a problem to be solved to make cell size and terminal position the same for all cells with the same logic.