Field
Embodiments of the present disclosure generally relate to a methodology for detecting process performance in a processing chamber, more particularly, a methodology for detecting process performance in a processing chamber to chamber-to-chamber matching for semiconductor manufacturing and factory management.
Description of the Related Art
In the manufacture of integrated circuits (IC), or chips, patterns representing different layers of the chip are created by a chip designer. A series of reusable masks, or photomasks, are created from these patterns in order to transfer the design of each chip layer onto a semiconductor substrate during the manufacturing process. Mask pattern generation systems use precision lasers or electron beams to image the design of each layer of the chip onto a respective mask. The masks are then used much like photographic negatives to transfer the circuit patterns for each layer onto a semiconductor substrate. These layers are built up using a sequence of processes and translate into the tiny transistors and electrical circuits that comprise each completed chip. Typically, devices on semiconductor substrates are manufactured by a sequence of lithographic processing steps in which the devices are formed from a plurality of overlying layers, each having an individual pattern. Generally, a set of 15 to 100 masks is used to construct a chip and can be used repeatedly.
Between one layer and the next layer that overlays the previous one, the individual patterns of the one layer and the next layer must be aligned. A measurement of alignment marks may be obtained by a metrology tool which is then used by a lithography tool to align the subsequent layers during exposure and again after a lithography process to recheck a performance of the alignment. However, overlay errors (or pattern registration errors) between layers are inevitable, and error budgets are calculated by IC designers for which the manufacturing must meet. Overlay errors of the device structure may originate from different error sources, such as overlay errors from previous exposure tool/metrology tool, current exposure tool/metrology tool, underlying film layer property mismatch, a matching error among metrology tool or processing chambers that may result in deposited film property difference, or mismatched baseline setting of the processing chambers utilized to process different film layers formed on the substrate and the like.
With the shrink of critical dimensions (CD), overlay error in the critical layers of the device structure must be minimal or eliminated in order to reliably produce devices with minimal feature sizes, such as a width of a control gate in a device. To eliminate the likelihood of overlay errors, a single processing chamber dedicated to manufacture certain film layers on the same substrate is often requested in an attempt to eliminate tool to tool manufacturing errors or mismatch. However, this approach often creates logistic problems and adversely increases manufacture cycle time. Furthermore, overlay specifications have become more challenging that the film property mismatch contributions (i.e., film refractive index or extinctive coefficient) to overlay errors may alone exceed the error budget. In semiconductor manufacturing, the production processing equipment used must be controlled with minimum mismatch such that its variables generated from each tool stay within certain operational limits. Failure to remain within operational limits in each processing chambers in the production line can easily cause the loss of, or damage to, the device and/or wafer being processed utilizing different processing chambers at different manufacturing stage.
Therefore, there exists a need for improved methodology to correct and match baseline of the processing chambers in the production line with minimum process variable mismatch so as to improve device performance and maintain predicable product reliability, consistency and yield.