1. Field of the Invention
The present invention relates to a semiconductor memory device, and specifically to a semiconductor memory device suitable for merging with a logic such as a logic device or a microprocessor. More specifically, the present invention is related to an arrangement of a data write/read portion of a logic-merged DRAM (Dynamic Random Access Memory).
2. Description of the Background Art
In recent years, a DRAM built-in system LSI (Large Scale Integration) having a DRAM and a logic device or a microprocessor integrated on the same semiconductor substrate has become widely adopted. The DRAM built-in system LSI has the following advantages over the conventional system having a discrete DRAM and a logic device soldered onto a printed-circuit board:
(1) There is no need to take into account the pin terminals of the discrete DRAM, so that wider space may be used for the data bus between a DRAM and a logic, and an improved data transfer rate is achieved, leading to an improved system performance;
(2) The data bus formed on a semiconductor substrate has a smaller parasitic capacitance than the wire on a printed-circuit board, so that the charge/discharge current of a signal line can be reduced, while the operating current consumed during data transfer can also be reduced; and
(3) The package can be unified, and the data bus wiring and the control signal wiring on the printed-circuit board can be reduced in number so that smaller area is occupied on the printed-circuit board.
FIG. 58 is a diagram representing an example of an arrangement of a conventional DRAM built-in system LSI. In FIG. 58, the DRAM built-in system LSI has a logic circuit LG and a DRAM macro integrated on the same semiconductor substrate chip CH.
The DRAM macro includes memory arrays MA0 and MA1, each having a plurality of memory cells arranged in a matrix of rows and columns; row decoders XD0 and XD1 provided corresponding to memory arrays MA0 and MA1 for selecting addressed rows of the corresponding memory arrays MA0 and MA1; column decoders YD0 and YD1 provided corresponding to memory arrays MA0 and MA1 for selecting addressed columns of memory arrays MA0 and MA1; data paths DP0 and DP1 for communicating data with the memory cell columns selected by column decoders YD0 and YD1; and a control circuit CG for controlling the data access operation to memory arrays MA0 and MA1.
Data paths DP0 and DP1 are coupled to logic circuit LG via data buses DB0 and DB1, and control circuit CG is coupled to logic circuit LG via a control bus CTB. In FIG. 58, each of data buses DB0 and DB1 separately communicates 128-bit write data (D) and 128-bit read data (Q).
In the DRAM built-in system LSI shown in FIG. 58, row decoders XD0 and XD1 are disposed orthogonal to column decoders YD0 and YD1. Upon selecting the columns of memory arrays MA0 and MA1 with column decoders YD0 and YD1, data paths DP0 and DP1 can be coupled to the selected columns of memory arrays MA0 and MA1 in the shortest distance. In addition, since the DRAM macro and logic circuit LG are integrated on the same semiconductor chip CH, data buses DB0 and DB1 are not in any way limited with respect to the pitch condition and number of pin terminals so that a wide bus can be implemented.
FIG. 59 is a schematic representation of an arrangement of memory arrays MA0 and MA1 shown in FIG. 58. Since these memory arrays MA0 and MA1 have identical arrangement, they are generically shown as memory array MA in FIG. 59. Memory array MA includes a plurality of memory cell blocks MCB arranged in a matrix of rows and columns. Though not specifically shown, memory cells are arranged in a matrix of rows and columns within these memory cell blocks MCB.
Local IO line pair groups LIOs are provided corresponding to each of memory cell blocks MCB for communicating data with the corresponding memory cell blocks. A local IO line pair LIO communicates signals complementary one another. Moreover, a sense amplifier group SAs is arranged corresponding to each of memory cell blocks MCB. Sense amplifier group SAs has a shared sense amplifier arrangement and is shared by the memory cell blocks adjacent to one another in the column direction. These sense amplifier groups SAs includes sense amplifier circuits SA provided corresponding to the respective columns of the corresponding memory cell blocks, and perform sense, amplification, and latching of data of the columns of the corresponding memory cell blocks during activation. Sense amplifier group SAs is selectively coupled to the corresponding local IO line pair group LIOs.
Word line group WLs is disposed in common to memory cell blocks MCB arranged in alignment in the row direction. In operation, one word line WL of word line group WLs contained in one row block (or the block consisting of the memory cell blocks arranged in alignment in the row direction) is driven to the selected state.
Global IO line pairs GIO0 to GIO127 that extend in the column direction are disposed in regions between the memory cell blocks adjacent to one another in the row direction and a region outside of the memory cell blocks (these regions hereinafter referred to as inter-block regions). Four global IO line pairs are arranged in common to the memory cell blocks aligned in the column direction. Four local IO line pairs LIO are provided to each memory cell block, and a group of the four local IO line pairs LIOs correspondingly provided to each memory cell block MCB in one row block are coupled to the corresponding global IO line pairs via IO switches IOSW, respectively.
Each of global IO line pairs GIO0 to GIO127 transmits complementary signals, is coupled to a data path shown in FIG. 58, and is coupled to logic circuit LG via a write/read circuit within the data path.
Column select lines CSL are arranged extending in the column direction over memory cell array MA in the same interconnection layer as global IO line pairs GIO0 to GIO127. Column select line group CSLs are shared by memory cell blocks MCB disposed in alignment in the column direction. By IO switches IOSW, local IO line pair groups LIOs of a selected row block are coupled to global IO line pairs GIO0 to GIO127, while local IO line pair groups LIOs of non-selected row blocks are disconnected from global IO line pairs GIO0 to GIO127. Thus, four columns are simultaneously selected in each column block (or the block consisting of the memory cell blocks arranged in alignment in the column direction), and four local IO line pairs LIO are respectively coupled to the corresponding global IO line pairs.
In the array arrangement shown in FIG. 59, global IO line pairs GIO0 to GIO127 are coupled to logic circuit LG via the data paths. Therefore, increasing the bus width of data buses DB0 and DB1 between the DRAM macro and the logic circuit means increasing the number of global IO line pairs. In order to increase the number of global IO line pairs, the number of inter-block regions needs to be increased. A global IO line pair is a complementary signal line pair, and the increase in number of inter-block regions results in the increase in the area occupied by the global IO line pairs in a memory cell array and in the increase in the area of the region occupied by transfer gates connecting global IO line pairs GIO and local IO line pair LIO, which leads to a greater chip area.
FIG. 60 is a schematic representation of another conventional DRAM built-in system LSI. The arrangement shown in FIG. 60 is presented, for instance, by Yabe et al. in Digest of Technical Papers, 1999 IEEE ISSCC, on pp. 72 to 73 and p. 415.
In the DRAM built-in system LSI shown in FIG. 60, row decoders XD0 and XD1 as well as column decoders YX0 and YX1 are disposed in the region between memory arrays MA0 and MA1. Thus, row decoders and column decoders are provided within the same region.
The column decoders are not disposed between memory arrays MA0 and MA1 and data paths DP0 and DP1. Control circuit CG is disposed in the region between data paths DP0 and DP1.
FIG. 61 is a schematic representation of an arrangement of memory arrays MA0 and MA1 shown in FIG. 60. In FIG. 61, memory array MA (MA0, MA1) includes memory cell blocks MCB arranged in alignment both in the row direction and in the column direction. A sense amplifier band SAB including sense amplifier circuits is arranged corresponding to these memory cell blocks MCB. A column select line group CSLG extending in the row direction is arranged in the region of sense amplifier band SAB. A column select line group CSLG includes 8-bit column select lines CSLAi to CSLA(i+7) or CSLBi to CSLB(i+7). A word line group WLG is provided in parallel to these column select line groups CSLG. Word line group WLG includes 512 word lines WLAj to WLA(j+511) or WLBj to WLB(j+511). Here, i=8N and j=512N, and N is 0 or a natural number. 32-bit IO line group IOG extending in the column direction is provided over memory cell blocks MCB aligned in the column direction. For each column block, one spare IO data line pair SIO is provided in parallel to IO data line pair group IOG. Since a row block includes four memory cell blocks MCB, four spare 10 data line pairs SIO0 to SIO3 are provided.
In FIG. 61, the column select lines are divided into two groups of column select lines CSLA0 to CSLA71 and CSLB0 to CSLB71, because two word lines may be simultaneously driven to the selected state in this memory array, and the data of a memory cell connected to one of these two word lines is to be read. Therefore, the sense amplifier band through which column select lines CSLA64 to CSLA71 pass and the sense amplifier band through which column select lines CSLB0 to CSLB7 pass are separately provided so as to allow one word line from word lines WLA3584 to WLA4095 and one word line from word lines WLB0 to WLB511 to be simultaneously driven to the selected state.
In the arrangement shown in FIG. 61, 16 sense amplifiers per memory cell block MCB are coupled via column select gates to the respective IO data line pairs IO0 to IO127. One column select gate (per IO) is rendered conductive by a column select line. Since the column select gate is coupled to an IO data line pair, an IO switch for connecting a local IO line pair and a global IO line pair is not required. In addition, column select lines are disposed orthogonal to IO data line pairs, and the IO data line pairs are arranged extending over the memory cell array, so that there is no need to provide an interconnection region specially for the IO data line pairs, and the chip area can be reduced.
FIG. 62 is a schematic diagram representing an arrangement of a sense amplifier band for one memory cell block MCB. FIG. 62 shows a memory cell block to which column select lines CSLA0 to CSLA15 are provided. For one IO data line pair IO, eight sense amplifier circuits SA are disposed in one sense amplifier band. Each sense amplifier circuit SA is connected to a corresponding IO data line pair via a column select gate YG. While IO data line pairs IO0 and IO1 are shown in FIG. 62, 32-bit IO data line pairs IO0 to I031 are provided to memory cell block MCB. For the 32-bit IO data line pairs, one spare IO data line pair SIO is provided. Eight spare sense amplifier circuits are also disposed in one sense amplifier band for the spare IO data line pair SIO.
When one of column select lines CSLA0 to CSLA7 is driven to the selected state, one sense amplifier circuit is selected from a set of eight sense amplifier circuits as a unit, and the selected sense amplifier circuit is coupled to a corresponding IO data line pair via column select gate YG. Two sense amplifier bands are provided to a memory cell block. Since one of 16 column select lines CSLA0 to CSLA15 is driven to the selected state, 16 sense amplifier circuits are correspondingly provided to one IO data line pair. The same is true for the spare sense amplifier circuits. Thus, 32 columns out of 512 columns are simultaneously selected and connected to the corresponding IO data line pairs in memory cell block MCB by the column select lines. Defective bits repair for an IO data line pair is effected by replacing a set of 16 sense amplifier circuits with a set of 16 spare sense amplifier circuits.
Column select lines CSLA0 to CSLA15 each select the normal sense amplifier circuit and the spare sense amplifier circuit at the same time as shown in FIG. 62, and the data from the normal sense amplifier circuit and the data held by the spare sense amplifier circuit are simultaneously transferred to IO data line pairs and the spare IO data line pair.
As shown in FIG. 62, since a sense amplifier circuit is coupled to an IO data line pair via column select gate YG, the region for disposing transfer gates is no longer necessary. Moreover, since IO data line pairs IO are disposed extending over the memory cell array in the column direction, an increase in the number of IO data line pairs does not in any way require an increase in the area occupied by IO data line pairs.
FIG. 63 is a schematic diagram representing an arrangement of a data path of the DRAM macro shown in FIG. 60. FIG. 63 shows an arrangement of a 32-bit data path, i. e. an arrangement corresponding to one column block.
The data path includes preamplifiers PA0 to PA31, write drivers WDV0 to WDV31, and a spare preamplifier SPA and a spare write driver SWDV provided corresponding to spare IO data line pair SIO.
Preamplifiers PA0 to PA31 and spare preamplifier SPA amplify and output the data on IO data line pairs IO0 to I031 and spare IO data line pair SIO.
Write drivers WDV0 to WDV31 and spare write driver SWDV are activated according to a write driver enable signal WDE to drive the corresponding IO data line pairs IO0 to IO31 and spare IO data line pair SIO according to the received write data.
Write data mask signals /DM0 to /DM3 inhibiting a data write are also provided to write drivers WDV0 to WDV31. Each of these write data mask signals /DM0 to /DM3 inhibits writing of 8 bits of data as a unit. When data mask signals /DM0 to /DM3 and /DMS are activated instructing that the data write is to be masked, the corresponding write drivers attain the output high impedance state.
Preamplifiers PA0 to PA31, spare preamplifier SPA, write drivers WDV0 to WDV31, and a spare write driver SWDV each include a circuit for equalizing the corresponding data line pair according to an IO equalizing instruction signal IOEQ.
The data path further includes a column redundancy control circuit CRC for determining, according to row block address signals RBA0 to RBA3 designating a row block in the selected state, whether a defective column is addressed in a normal memory cell array, and according to the determination result, outputting selecting signals SIOSEL0 to SIOSEL31 designating an IO data line pair to be replaced by spare IO data line pair, and for generating signals SDMSEL0 to SDMSEL3 signaling whether to mask the spare memory cell data according to a data mask signal during a data write; 2:1 multiplexers MUX0 to MUX31 for selecting, according to selecting signals SIOSEL0 to SIOSEL31, one of the signals output from the corresponding preamplifiers PA0 to PA31 and spare preamplifier SPA; read data latches RDL0 to RDL31 provided corresponding to the respective 2:1 multiplexers MUX0 to MUX31 for taking in and outputting output signals RDF0 to RDF31 of multiplexers MUX0 to MUX31 in synchronization with a clock signal CLK; and output buffers QB0 to QB31 provided corresponding to the respective read data latches RDL0 to RDL31 for taking in output data RD0 to RD31 of read data latches RDL0 to RDL31 in synchronization with clock signal CLK to be output as output data Q0 to Q31.
Read data latches RDL0 to RDL31 take in the received data at the fall of clock signal CLK and attain the latching state at the rise of clock signal CLK. Output buffers QB0 to QB31 take in and output the output data of read data latches RDL0 to RDL31 in response to the rise of clock signal CLK.
The data path further includes input buffers DB0 to DB31 provided corresponding to the respective write data D0 to D31 from outside for taking in the received write data in synchronization with clock signal CLK; 32:1 spare multiplexer SMUX for selecting, according to spare IO selecting signal SIOSEL0 to SIOSEL31 from column redundancy control circuit CRC, one of internal write data WD0 to WD31 output from input buffers DB0 to DB31; write data latches WDL0 to WDL31 for taking in internal write data WD0 to WD31 from input buffers DB0 to DB31 in response to write driver enable signal WDE; a spare write data latch SWDL for taking in and outputting internal write data WDS from spare multiplexer SMUX in response to write driver enable signal WDE; write drivers WDV0 to WDV31 for driving IO data line pairs IO0 to IO31 according to output data WDD0 to WDD31 from write data latches WDL0 to WDL31 when activated in response to the activation of write driver enable signal WDE; and a spare write driver SWDV for driving spare IO data line pair SIO according to write data WDDS from spare write data latch SWDL when activated in response to write driver enable signal WDE. Write drivers WDV0 to WDV31 and spare write driver SWDV are set to the output high impedance state during the deactivation of write driver enable signal WDE.
The operation of a data path shown in FIG. 63 will be described with reference to the timing chart shown in FIG. 64. In the following description, a DRAM macro has a multi-bank arrangement.
At the rising edge of clock signal CLK at time T0 or time T1, write command WRITE instructing a data write is taken in along with a column bank address CBK indicating the bank to which a column access is made. At the same time, a column address signal indicating the selected column (not shown) is also taken in. An internal circuit, not shown, stores row block address signals RBA0 to RBA3 indicating a row block in the active state, and applies the stored row block address signals RBA0 to RBA3 to column redundancy control circuit CRC when write command WRITE is provided. An address indicating the IO data line pair to which a defective memory cell is connected for each row block is programmed in column redundancy control circuit CRC. An address signal indicating a defective IO data line pair of the row block is decoded according to row block address signals RBA0 to RBA3 to generate spare IO selecting signals SIOSEL0 to SIOSEL31.
On the other hand, before the result of spare determination becomes definite, input buffers DB0 to DB31 are activated, take in write data D0 to D31 from outside, and generate internal write data WD0 to WD31 that are latched into write data latches WDL0 to WDL31. Spare multiplexer SMUX selects one of the output data from input buffers DB0 to DB31 according to spare IO selecting signals SIOSEL0 to SIOSEL31 from column redundancy control circuit CRC and applies the selected output data to spare write data latch SWDL.
After the output data of write data latches WDL0 to WDL31 and spare write data latch SWDL are made definite, write driver enable signal WDE is driven to the active state or the logic high or xe2x80x9cHxe2x80x9d level, and IO equalizing instruction signal IOEQ attains the inactive state or the logic low or xe2x80x9cLxe2x80x9d level. Responsively, the precharging/equalizing operation of IO data line pairs IO0 to I031 and spare IO data line pair SIO is completed, and write data is transmitted to these data line pairs IO0 to IO31 and SIO.
Moreover, at this time, a column decoder (not shown) performs a column select operation, and a column select line CSL corresponding to the addressed column is driven to the selected state or the xe2x80x9cHxe2x80x9d level. Consequently, data are written into memory cells via IO data line pairs IO0 to IO31 and spare IO data line pair SIO.
When data writing is performed sufficiently, column select line CSL is deactivated, and thereafter, the deactivation of write driver enable signal WDE as well as the activation of IO equalizing instruction signal IOEQ causes IO data line pairs IO0 to IO31 and spare IO data line pair SIO to be equalized and precharged to the power supply voltage level again.
When a read command READ instructing a data read is provided at time T2 or T3, a column bank address CBK and a column address signal (not shown) are taken in at the rising edge of clock signal CLK, as in the data write operation. Row block address signals RBA0 to RBA3 are applied to column redundancy control circuit CRC as in the data write operation according to read command READ and column bank address CBK, and column redundancy control circuit CRC drives one of spare IO line selecting signals SIOSEL0 to SIOSEL31 to the selected state. Along with the spare determination operation in column redundancy control circuit CRC, equalizing signal IOEQ is deactivated, and the equalizing operation for IO data line pairs IO0 to IO31 and spare IO data line pair SIO is completed. When the column decoder drives column select line CSL to the selected state, memory cell data is read out to these IO data line pairs IO0 to IO31 and spare IO data line pair SIO.
After the potentials of IO data line pairs IO0 to I031 and spare IO data line pair SIO have changed sufficiently to reach the voltage levels sufficient for amplification by preamplifiers PA0 to PA31 and spare preamplifier SPA, a preamplifier activating signal PAE is activated and preamplifiers PA0 to PA31 and spare preamplifier SPA amplify and latch the signals on these IO data line pairs IO0 to I031 and spare IO data line pair SIO. Preamplifiers PA0 to PA31 and spare preamplifier SPA each include flip-flop, and maintain and output valid data even after the deactivation of preamplifier activating signal PAE.
When outputs PAO0 to PAO31 and PAOS of preamplifiers PA0 to PA31 and spare preamplifier SPA become definite, preamplifier activating signal PAE is deactivated, and column select signal line CSL is also driven to the inactive state. On the other hand, equalizing signal IOEQ is activated, and IO data line pairs are precharged and equalized to a prescribed power supply voltage level again.
2:1 multiplexers MUX0 to MUX31 perform the selecting operation according to spare IO selecting signals SIOSEL0 to SIOSEL31 from column redundancy control circuit CRC, and one of the output signals PAO0 to PAO31 of preamplifiers PA0 to PA31 is replaced by an output signal PAOS from spare preamplifier SPA when a defective memory cell is addressed.
Thereafter, read data latches RDL0 to RDL31 latch output signals RDF0 to RDF31 of multiplexers MUX0 to MUX31 in response to the rise of clock signal CLK. Output buffers QB0 to QB31 take in data RD0 to RD31 from read data latches RDL0 to RDL31 in synchronization with the clock signal and output the output data Q0 to Q31 to logic circuit LG.
The arrangement where column select lines CSL (CSLA0 to CSLA71 and CSLB0 to CSLB71) are disposed in parallel to the word lines in a sense amplifier band accompanies a column redundant arrangement for one IO data line pair, i. e. it has an arrangement of replacing the IO data line pair with a spare IO data line pair. During a data write, after the spare determination is performed, the IO data line pairs are driven by write driver WDV0 to WDV31 and spare write driver SWDV. Conversely, in a read operation mode during which a data read is performed, column select line CSL is first driven to the selected state and the IO data line pairs are driven by sense amplifier circuits. Then, according to the result of spare determination, the replacement of IO data line pairs is carried out. The timing at which the result of spare determination is made definite is the same for a data write mode and for read mode, and in the data write mode, column select line CSL is driven to the selected state at a timing later than that in the read operation mode during which data read is performed. Therefore, when the read operation is performed in the cycle following the write operation, as shown in FIG. 64, the equalizing time xcex94Teq(wr) for an IO data line pair becomes shorter than the equalizing time xcex94Teq(rr) when a data read is performed in the cycle following the read operation.
When the cycle time is made shorter, the data read would be performed before IO data line pairs IO0 to IO31 and spare IO data line pair SIO are sufficiently precharged and equalized, so that amplification by a preamplifier cannot be accurately performed, resulting in the so-called xe2x80x9cwrite recoveryxe2x80x9d problem. Thus, the cycle time could not be shortened to implement a high-speed operation.
The equalizing time xcex94Teq(wr) may be ensured by delaying the timing at which column select line CSL is activated in the data read operation mode. In this case, however, the activation of preamplifier activating signal PAE is delayed accordingly, and thus, the timing of output data RDF0 to RDF31 of multiplexers MUX0 to MUX31 becoming definite is also delayed. Consequently, read data latches RDL0 to RDL31, in response to the rise of clock signal CLK, have entered the latched state so that there is no margin for the set-up time xcex94Ts of input signals RDF0 to RDF31 to read data latches RDL0 to RDL31 relative to clock signal CLK, and an accurate reading of data cannot be ensured.
As seen from the above, when performing data write and data read into/from a memory cell using a common IO data line in a conventional DRAM macro, the cycle time cannot be made shorter due to the so-called xe2x80x9cwrite recoveryxe2x80x9d problem. In order to perform data read operation a column latency of CL=2, the frequency of clock signal CLK needs to be lowered, so that a high-speed operation could not be performed.
In general, in a logic-merged DRAM, data bit widths differ according to the uses. From the viewpoint of the production cost, it is preferable to form common parts for DRAM macros of various data bit widths, and to change the arrangement of the input/output circuits according to the data bit widths. Therefore, in this case, the same numbers of write drivers and input buffers are provided regardless of the data bit width. The number of input buffers actually used are changed according to the data bit width, and write drivers are selectively coupled to the input buffers being used.
FIG. 65 is a schematic representation of an arrangement of a data write portion of a DRAM macro shown in FIG. 63 where the data bit width is reduced to one-fourth of its original width. In FIG. 65, input buffers DB0 to DB7 are provided for write data bits D0 to D7, respectively. Write drivers WDV0 to WDV31 of 32 bits are provided corresponding to input buffers, where four write drivers as a unit correspond to one input buffer. In addition, input buffer DB0 is coupled to write drivers WDV0 to WDV3, and input buffer DB7 is coupled to write drivers WDV28 to WDV31. These write drivers WDV0 to WDV31 are coupled to IO data line pairs IO0 to IO31, respectively.
Write drivers WDV0, WDV4, . . . WDV28 are activated in response to a write driver enable signal WDE0. Write drivers WDV3, WDV7, . . . WDV31 are activated in response to a write driver enable signal WDE3. A write data mask instruction signal /DM0 is applied to write drivers WDV0 to WDV7. A write data mask instruction signal /DM3 is applied to write drivers WDV24 to WDV31.
Thus, each of write data mask instruction signals /DM0 to /DM3 masks the write data on corresponding eight IO data line pairs as a unit. A data write operation is considered under this condition. Now, consider the situation in which write driver enable signal WDE0 is rendered active and write drivers WDV0, WDV (4k), . . . WDV28 are rendered active. Now, assume that write data mask instruction signals /DM0 to /DM3 are all rendered inactive, and a data write operation is performed.
IO data line pairs IO0 to IO31 are coupled to sense amplifier circuits (S.A) SA0 to SA31 via selected column select gates CSG0 to CSG31, respectively.
Non-selected write drivers are in the output high impedance state. In this case, write drivers WDV0, . . . , WDV (4k), . . . WDV28 transfer data corresponding to write data bits D0 to D7 to sense amplifiers SA0, SA (4k), . . . SA28. On the other hand, IO data line pairs excluding the IO data line pairs IO0, . . . , IO (4k), . . . IO28 are precharged to a power-supply voltage Vcc level (see FIG. 64). Therefore, in this case, a corresponding column select gate CSG is in the conductive state according to a column select signal CSL, and a non-selected sense amplifier circuit (S.A) receives this precharge voltage Vcc so that the latch data of the non-selected sense amplifier circuit (S.A) may possibly become inverted. Thus, with the conventional arrangement in which a write driver is set to the inactive state according to a data write mask instruction signal, an internal data write circuit that accommodates different data bit widths cannot be implemented. Moreover, common chips cannot be used to adapt to the different data bit widths so that each chip will need to be designed individually according to the data bit width, which leads to a problem of higher production cost.
An object of the present invention is to provide a logic-merging DRAM operable in synchronization with a high-speed clock signal.
Another object of the present invention is to provide a logic-merging DRAM capable of performing a data write at a high speed.
A still another object of the present invention is to provide a logic-merging DRAM having a write data masking function that allows an accurate data write masking irrespective of the data bit width.
A still further object of the present invention is to provide a semiconductor memory device having a write data masking function that can accommodate different data bit widths with common chips.
The semiconductor memory device according to a first aspect includes a memory array having normal memory cells arranged in a matrix of rows and columns and spare memory cells for replacing defective normal memory cells among these normal memory cells arranged in a matrix of rows and columns; a defective address program circuit for storing the address of a defective normal memory cell; and a spare determination circuit for determining a match/mismatch between a provided address signal and the defective address from the defective address program circuit. The timing at which the spare determination circuit outputs the result of determination differs in the data write mode and in the data read mode.
The semiconductor memory device according to a second aspect of the invention includes a plurality of memory cells arranged in a matrix of rows and columns, and a plurality of sense amplifier circuits disposed corresponding to a row of memory cells and each for sensing and amplifying data of a memory cell of a corresponding column. The plurality of sense amplifier circuits are divided into a plurality of sense amplifier units, each of the units including a prescribed number of sense amplifier circuits.
The semiconductor memory device according to the second aspect further includes a plurality of internal data lines, a plurality of column select units provided corresponding to the plurality of sense amplifier units and each selecting one sense amplifier circuit from a corresponding sense amplifier unit in response to a column select signal; a plurality of write mask circuits each provided corresponding to a sense block including a predetermined number of sense amplifier units, and each for inhibiting connection between a sense amplifier circuit of a corresponding sense block and a corresponding internal data line in response to a corresponding data mask instruction signal; and a plurality of write drivers provided corresponding to the plurality of internal write data lines for transmitting internal write data to corresponding internal data lines when activated. The plurality of write drivers are divided into a plurality of write driver blocks corresponding to the write mask circuits.
The semiconductor memory device according to the second aspect further includes a plurality of mask gate circuits provided corresponding to the plurality of write mask circuits for providing data mask instruction signals to corresponding write mask circuits in response to a data mask instruction signal. Each mask gate circuit includes a gate circuit for activating a corresponding data mask instruction signal to inhibit a corresponding write mask circuit from being conductive when a corresponding write driver block is inactive.
By varying the timing at which the result of determination is outputted in the data write mode and in the data read mode, the timing for a column select can be optimized for both a data write and a data read, thereby achieving a high-speed access.
In particular, by providing a read data bus and a write data bus separately, the read data and the write data are kept from colliding with one another on the data bus, so that the so-called xe2x80x9cwrite recoveryxe2x80x9d problem does not occur, and the cycle time can be made shorter.
Write drivers are divided into blocks corresponding to the respective write mask circuits, and a write mask circuit inhibits the connection between a sense amplifier circuit and an internal data line. As a result, when a write driver block is in the inactive state, the corresponding write mask circuit is activated and inhibits a data write operation so that the data held by a sense amplifier circuit is kept from being changed, and an accurate data write operation can be performed even when the input data bit width is changed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.