Digital processing circuitry and apparatus, including such circuitry, is pervasive in modern society. The use of digital processing circuitry is advantageous as repetitive functions can be carried out at rates dramatically more quickly than that which can be performed manually. And, because of the rapid speed at which the operations can be performed, activities previously impractical have been readily implemented. The use of digital processing circuitry advantageously permits the processing of large amounts of data. For instance, in a computer system, data is transferred between peripheral devices, and between peripheral devices and a CPU (central processing unit). In such processing of data, data is read from, or written to, data storage, and other locations in successive read and write operations.
In order to carry out the read and write operations, the location of the data to be retrieved in a read operation and the destination to which the data is to be written must be identified. Such locations are sometimes identified by addresses which point to such locations. Such indications are referred to as address pointers. The addresses are sequences of binary bits. In some computer systems, the sequences are fairly lengthy, for example, of 48-bit, bit lengths.
During operation of a computer system, or other system incorporating digital processing circuitry, successive, and non-sequential address locations might need to be accessed at high speeds. Providing the sequences forming the addresses needed to perform the data processing functions becomes unwieldy when the lengths of the address are of lengthy bit lengths.
One conventional manner by which to generate the addresses is to utilize an arithmetic logic unit (ALU) of a bit-size corresponding to the bit lengths of the addresses to be generated. However, such conventional circuitry is of complex construction and requires multi-cycle paths for effectuation. Because of such complexity and the need for multi-cycle paths to effectuate the formation of the bit sequences, the costs of implementing such circuitry is relatively high. When such sequences are to be generated with, e.g., an ASIC (application specific integrated circuit), the circuitry must be operated at a fixed frequency. Existing manners by which to form a lengthy sequence of bits based on combinations of smaller function mechanisms typically permit scaling of clock frequencies of circuitry to implement such functions.
A manner by which better to provide for the formation of bit sequences, such as those used to form address or data pointers, utilizing less complex circuitry would therefore be advantageous.
It is in light of this background information related to digital processing circuitry that the significant improvements of the present invention have evolved.