In order to examine the electrical characteristics of small semiconductor devices (e.g., semiconductor chips in a wafer), a probe card is used as the medium of connection between a tester and a test target, i.e., semiconductor devices. As well known, such a semiconductor device has input/output terminals (also referred to as contact pads) exposed outwardly, and the probe card has probe pins that make a mechanical contact with the input/output terminals and also provide a path for electrical signals. That is, when receiving predetermined signals from the tester through the probe pins being in contact with the input/output terminals, the semiconductor device operates according to the received signals and then outputs the result to the tester through the probe pins.
In general, for a rapid and effective test, such a test process is performed by means of several probe pins that make simultaneous contacts with several terminals of the device. By the way, the size of the device becomes more and more reduced, and the number of the terminals becomes more and more increased. So the pad pitch, namely, the distance between adjacent terminals, also grows more and more decreased. For such reasons, the probe card needs a great number of probe pins that are arranged with a fine pitch corresponding to the pad pitch. However, as the pitch of the probe pins grows reduced, it is very difficult to arrange the probe pins without electrical and mechanical interference between adjacent pins. Additionally, it is important, but actually difficult, to precisely dispose the pins with a high level of coplanarity.
A known conventional solution for fine pitch arrangement of the probe pins is to use MEMS (micro electro-mechanical system) technique. This technique, however, inherently employs semiconductor fabrication process that causes complication and high cost. Therefore, another solution with simpler and cost-reduced process is required for a probe assembly.
On the other hand, a conventional probe assembly has a problem of probe pin contact failure due to a difference in thermal expansion between the wafer and the probe assembly. Generally, a hot test and a cold test are used to test the semiconductor devices in the wafer under extreme conditions. Though there are minor differences in such test conditions between semiconductor manufacturers, a temperature of the wafer is commonly increased to 120° C. in the hot test and decreased to −40° C. in the cold test. The probe pin contact failure often occurs while these tests are performed.
Referring to FIG. 1, since the wafer W and the probe assembly 100 normally differ in a coefficient of thermal expansion, the probe pin 10 may deviate from the contact pad P on the wafer W, that is, from the input/output terminal of the semiconductor device during the hot test or the cold test. This problem may be more serious near edges of the probe assembly 100 as the size of the probe assembly 100 increases.
Another problem associated with a conventional probe assembly is exemplarily illustrated in FIG. 2. Referring to FIG. 2, when the probe pin 10 is in contact with the contact pad P on the wafer W, the surface of the wafer W and the probe pin 10 may be damaged due to a mechanical impact. This problem is generated when equipment that adjusts the contact distance between the contact pad P of the wafer W and the probe pins 10 wrongly operates so that it moves by more than a contact tip height of the pins 10. In this case, roots of the probe pins 10 as well as the surface of the wafer W may be remarkably damaged to cause a serious problem in the elasticity and position alignment of the probe pins 10.
In addition, the conventional probe assembly has various problems. For example, problem assembly manufacturing time increases as the number of probe pins increases and electronic devices are required to be simply formed in the probe assembly together with the probe pins.