The present invention relates to a relates to a method for inhibiting a converter with distributed energy stores having at least two phase modules, which each have an upper and a lower valve branch, which each have a multiplicity of two-pole submodules, which are electrically connected in series and each have a unipolar energy storage capacitor, with which a series circuit of two semiconductor switches which can be turned off, each with a diode connected back-to-back in parallel, is connected electrically in parallel.
The following discussion of related art is provided to assist the reader in understanding the advantages of the invention, and is not to be construed as an admission that this related art is prior art to this invention.
A conventional converter with distributed energy stores is illustrated schematically in FIG. 1. According to FIG. 1, this converter 2 has three phase modules 41, 42 and 43, which each have an upper and a lower respective valve branch P1 and N1, P2 and N2 as well as P3 and N3. These two valve branches P1, N1; P2, N2 and P3, N3 in each phase module 41, 42 and 43, respectively, are connected to form one bridge arm. A junction point between an upper and a lower valve branch P1 and N1, P2 and N2 as well as P3 and N3 is passed out as a respective connection L1, L2 or L3, respectively, on the AC voltage side of the respective phase module 41, 42 or 43. A polyphase motor 6 or a power supply system is connected to these connections L1, L2 or L3 on the AC side. The phase modules 41, 42 and 43 are electrically connected in parallel with one another and are connected to form a DC voltage feed device, which is not illustrated in any more detail but is connected to the DC voltage connections P0 and N0 of the converter 2 with distributed energy stores CSM. A generated DC voltage Udc is present between these DC voltage connections P0 and N0.
This illustration of the converter 2 with distributed energy stores CSM likewise shows that each valve branch P1, N1, P2, N2, P3 and N3 has a multiplicity of two-pole submodules SM1, SM2, . . . , SMn, which are electrically connected in series. Each two-pole submodule SM1, SM2, . . . , SMn, based on the illustration of the submodule SM1, has a unipolar energy storage capacitor CSM, two semiconductor switches S1 and S2 which can be turned off, and two diodes D1 and D2. The two semiconductor switches S1 and S2 which can be turned off are electrically connected in series, and this series circuit is electrically connected in parallel with the unipolar energy storage capacitor CSM. A respective diode D1 or D2 is connected back-to-back in parallel with the semiconductor switches S1 and S2 which can be turned off. These diodes D1 and D2 therefore each form a freewheeling diode. A junction point between the two semiconductor switches S1 and S2 which can be turned off is passed out as the module connection X2. The negative connection of the unipolar energy storage capacitor CSM forms a second module connection X1. When the unipolar energy storage capacitor CSM has been charged, a capacitor voltage USM is dropped across it.
These capacitor voltages USM1, USM2, USMn of the two-pole submodules SM1, SM2, . . . , SMn in each valve branch P1, N1, P2, N2, P3 and N3 are respectively added to form a valve voltage UZP1, UZN1, UZP2, UZN2, UZP3 and UZN3. The addition of in each case two valve voltages UZP1, UZN1 as well as UZP2 and UZN2 as well as UZP3 and UZN3 of a respective phase module 41, 42 or 43 results in the DC voltage Udc which is present between the DC voltage connections P0 and N0.
The configuration of each two-pole submodule SM in the converter 2 with distributed energy stores CSM allows each submodule SM each to be controlled to three switching states, specifically the switching states I, II and III. In the switching state I, the semiconductor switch S1 which can be turned off is in the ON-state, and the semiconductor switch S2 which can be turned off is in the OFF-state. The capacitor voltage USM is therefore present as the terminal voltage UX2X1 at the module connections X2 and X1 of the submodule SM, independently of the direction of a branch current iZ flowing. In the switching state II, the semiconductor switch S1 which can be turned off is in the OFF-state, and the semiconductor switch S2 which can be turned off is in the ON-state, thus resulting in a terminal voltage UX2X1 with the amplitude zero being present at the module connections X2 and X1 of the submodule SM, likewise independently of the direction of a branch current iZ flowing. In the switching state III both semiconductor switches S1 and S2 which can be turned off are in the OFF-state. The amplitude of the terminal voltage UX2X1 of each submodule SM when in the switching state III is dependent on the direction of a branch current iZ flowing. If the branch current is greater than zero, then the amplitude of the terminal voltage UX2X1 of the submodule SM corresponds to the amplitude of the capacitor voltage USM in this submodule SM. In contrast, if the branch current is less than zero, the amplitude of the terminal voltage is equal to zero. If no branch current iZ is flowing and if the voltage split between the semiconductor switches S1 and S2 which can be turned off in the submodule SM is symmetrical, the amplitude of the terminal voltage UX2X1 corresponds to half the amplitude of the capacitor voltage USM in the submodule SM.
In the conventional converter 2 with distributed energy stores CSM, only the switching states I and II of the submodules SM are used during normal operation of this converter 2. The switching state III is used only in the event of defects, for example a short at its DC voltage connections P0 and N0, for a deliberate open circuit (interruption of converter operation) and for negligibly short switching delay times for the semiconductor switches S1 and S2 which can be turned off in a submodule SM, when a switching state change occurs.
It is known that a so-called pulse inhibitor can be activated, in order to turn the converter off in critical operating states, for example overcurrent, overvoltage, failure of a drive, failure of a control system, failure of communications between the converter valve and the modulator, . . . , such that this converter is in a safe state after operation of the pulse inhibitor. This pulse inhibitor can be implemented by inhibiting all the converter valves in the self-commutated converter (inverter). This is preferably done by interruption of the supply voltage, which is derived from an external voltage, for the optocouplers in the associated drive circuits.
When a pulse inhibitor in a converter 2 with distributed energy stores CSM is triggered, then all the drive signals for the semiconductor switches S1 and S2 which can be turned off in all the submodules SM1, SM2, . . . , SMn in all the valve branches P1, N1, P2, N2, P3 and N3 in the phase modules 41, 42 and 43 in the converter 2 with distributed energy stores CSM must be inhibited at the same time, as shown in FIG. 1.
FIG. 2a shows for sake of clarity in more detail only the phase module 41 of the converter 2 with distributed energy stores CSM depicted in FIG. 1. The submodules SM1, . . . , SM4 in the upper and lower valve branches P1 and N1 in this phase module 41 illustrate a switching state distribution during normal operation of this converter 2. Of the four submodules SM1, . . . , SM4 in the upper valve branch P1, the submodules SM2 to SM4 are in the switching state I, and the submodule SM1 is in the switching state II. Of the submodules SM1, . . . , SM4 in the lower valve branch N1, the submodules SM1 to SM3 are in the switching state II, and the submodule SM4 is in the switching state I. The amplitude of the DC voltage Udc which is present at the DC voltage connections P0 and N0 of the converter 2 is therefore Udc=4·USM. The voltage uZP in the upper valve branch P1 with respect to a virtual neutral point is given by uZP=3·USM, while, in contrast, the voltage uZN in the lower valve branch N1 is given by uZN=1·USM.
Once a pulse inhibitor is triggered, all the submodules SM1 to SM4 in the upper and lower valve branches P1 and N1 are switched to the switching state III. The phase module 41 with the submodules SM1 to SM4 in the switching state III is illustrated in FIG. 2b. The pulse inhibitor can be set on the one hand by a fault occurring (for example an overcurrent) by an open-loop and closed-loop control device, which is not illustrated in any more detail, in the converter 2, whereas on the other hand autonomously by the submodules SM1 to SM4 (disturbance with or breakdown of communication, overvoltage). Since the time at which a pulse inhibitor is set cannot be predicted, the voltages uZP and uZN and/or their rates of change duZP/dt and duZN/dt over the valve branches P1 and N1 in a phase module 41 are governed solely by the direction of the corresponding branch current iZP1 and iZN1 when the pulse inhibitor is set.
On the assumption that the sum of the two branch voltages uZP and uZN in a respective phase 41, 42 or 43 corresponds on average to the DC voltage Udc during normal operation, this results in the voltages and voltage changes as shown in the following table after a pulse inhibitor has been set.
Direction of thebranch currentsiZP/iZNpos/pospos/negneg/posneg/neguZPUdcUdc00uZNUdc0Udc0uZP + uZN2 Udc UdcUdc0Δ(uZP + uZN) *+Udc 00−Udc* Assumption: mean sum of the branch voltages before the pulse inhibitor (uZP + uZN) = Udc
It is also assumed that the capacitor voltages USM in each submodule SM on average have a value of USM=Udc/nsub, where nsub represents the number of series-connected submodules SM1, . . . , SMn in each valve branch P1, N1, P2, N2, P3 and N3 in the converter 2 with distributed energy stores CSM.
As can be seen from this table, two worst-case scenarios occur with respect to the voltage change in the branches in one phase when a pulse inhibitor is set. The maximum voltage change in the sum of the branch voltages uZP and uZN in a phase module 41, 42 and 43 is ±Udc and occurs when both branch currents iZP and iZN in a phase module 4 have the same mathematical sign. This state is maintained until one of the branch currents has been commutated down to zero.
Switching on the switching state III results in commutation processes from the semiconductor switch S1 which can be turned off to a diode D2 in said submodules SM2, SM3, SM4 in the upper valve branch P1 and the submodule SM4 in the lower valve branch N1 in the phase module 41, if, before setting of the pulse inhibitor, the sum of the branch voltages uZP and uZN in a phase module 41 is on average equal to the DC voltage Udc between the DC voltage connections P0 and N0, and the branch currents iZP and iZN have a negative mathematical sign. When the switching state III is switched on, no commutation processes occur in the submodule SM1 in the upper valve branch P1 and the submodules SM1, SM2, SM3 in the lower valve branch N1 in the phase module 41 if, before the setting of the pulse inhibitor, the sum of the branch voltages uZP and uZN in a phase module 41 is on average equal to the DC voltage Udc and the branch currents iZP and iZN have a negative mathematical sign since the diode D2 carried the corresponding branch current before switching on the switching state III.
In contrast, commutation processes take place from the semiconductor switch S2 which can be turned off to the diode D1 in said submodules as a result of switching on the switching state III in the submodule SM1 in the upper valve branch P1 and the submodules SM1, SM2, SM3 in the lower valve branch N1 in the phase module 41 if, before setting of the pulse inhibitor, the sum of the branch voltages uZP and uZN of a phase module 41 is on average equal to the DC voltage Udc between the DC voltage connections Po and No, and the branch currents iZP and iZN have a positive mathematical sign. No commutation processes take place when the switching state III is switched on in the submodules SM2, SM3, SM4 in the upper valve branch P1 and the submodule SM4 in the lower valve branch N1 in the phase module 41 if, before setting of a pulse inhibitor, the sum of the branch voltages uZP and UZN of a phase module 41 is on average equal to the DC voltage Udc and the branch currents iZP and iZN have a negative mathematical sign, since the diode D1 carried the corresponding branch current before switching on the switching state III.
A voltage rate of change which, for example, may be 4 kV/μs can be assumed for a semiconductor switch S1 or S2 which can be turned off in each submodule SM, for every voltage change which occurs during a commutation process. This then results in a voltage rate of change across the two valve branches P1 and N1 in the phase module 41 with a value of 16 kV/μs, because there are four submodules SM in the phase module 41 in the switching state I before the setting of a pulse inhibitor. The greater the number of submodules SM which are used in each valve branch P1, N1, P2, N2, P3 and N3 in the converter 3 with distributed energy stores CSM, the higher is the value of the voltage change per phase module 41, 42 and 43.
In order to obtain a respective output voltage uL10, UL20, UL30 with as sinusoidal a waveform as possible at the respective output L1, L2 or L3 of a respective phase module 41, 42 or 43 in the converter 2 with distributed energy stores CSM, twelve or more submodules SM, for example, are used for each valve branch P1, N1, P2, N2, P3 and N3. When there are twelve submodules SM for each valve branch P1, N1, P2, N2, P3 and N3, the voltage rate of change is already 48 kV/μs.
If the DC voltage Udc which is present at the DC voltage connections P0 and N0 of the converter 2 with distributed energy stores CSM is assumed to be constant, then said voltage rate of change acts not only on a branch inductor LZ but also on a parasitic inductor Ldc in the DC voltage circuit. This voltage load on the branch inductor LZ leads to a large physical size, because of the use of reinforced insulation.
With respect to the output voltages uL10, uL20 and uL30 of the converter 2 with distributed energy stores CSM, different worst-case conditions occur in comparison to the converter-internal voltages uZP and uZN. A worst-case situation will be explained below with reference to FIGS. 3a and 3b, with respect to the voltage changes in the phase voltages uL10 in the phase module 41 in the converter 2 as shown in FIG. 1.
Because of the switching state distribution of the submodules SM1 to SM4 in the valve branches P1 and N1 in the phase module 41 in the converter 2 with distributed energy stores CSM as shown in FIG. 1, the submodules SM1 to SM4 in the upper valve branch P1 are all in switching state II. In contrast, the submodules SM1 to SM4 in the lower valve branch N1 are all in the switching state I. The phase voltage uL10, which is equal to half the difference between the valve voltages uZN and uZP, is Udc/2. If a pulse inhibitor is now set, then this results in a voltage change in the phase voltage UL10 which is dependent on the instantaneous current direction of the branch currents iZP and iZN. The following table provides an overview of the voltages and voltage changes over the valve branches P and N in a phase module 4 after a pulse inhibitor has been set.
Direction of thePulsebranch currentsinhibitoriZP/iZNpos/pospos/negneg/posneg/negBeforeuZP0000uZNUdcUdcUdc Udc uL10 Udc/2 Udc/2Udc/2 Udc/2AfteruZPUdcUdc00uZNUdc0Udc 0uL100 −Udc/2Udc/20ΔuL10 −Udc/2−Udc 0−Udc/2Δ(uZP + uZN) *Udc00−Udc * Assumption: Capacitor voltage of a submodule USM, x = Udc/nsub
The worst-case situation with respect to the voltage change in the phase voltage UL10, uL20 or UL30 after setting a pulse inhibitor occurs when the following conditions occur before setting of the pulse inhibitor:                all the submodules in a valve branch, for example in the valve branch N1, in a phase module are in the switching state I        all the submodules in a corresponding valve branch, for example the valve branch P1, in a phase module are in switching state II        the branch current, for example the branch current iZN, in the valve branch with the submodules which are in switching state I has a negative mathematical sign, and        the branch current, for example the branch current iZP, in the valve branch with the submodules which are in switching state II has a positive mathematical sign.        
In these conditions, the phase voltage uL10 jumps from Udc/2 to −Udc/2, or from −Udc/2 to U/dc/2. In these conditions, the change in the phase voltage uL10 is therefore ±Udc. If it is now assumed that a voltage rate of change of, for example, 4 kV/μs occurs across each submodule SM in the phase module 41 in each submodule SM1 to SM4 in each valve branch P1 and N1 in a phase module 41, because of the commutation from a semiconductor switch S1 or S2 which can be turned off to a respective diode D2 or D1 then this results in a value of 16 kV/μs for the voltage rate of change of the phase voltage uL10/dt, uL20/dt and uL30/dt when there are four submodules SM in each valve branch P and N, and in a value of 48 kV/μs when there are twelve submodules SM in each valve branch P and N in a phase module 41.
This means in the worst-case situation, in which two phase voltages change suddenly through ±Udc in opposite senses, for a line voltage uL1L2, that a voltage change of ΔuL1L2=±2Udc and a voltage rate of change of 32 kV/μs occurs across an output impedance (stator winding of a connected polyphase motor 6) when four submodules SM are used in each valve branch P and N in a phase module 41, or of 96 kV/μs when twelve submodules SM are used in each valve branch P and N in a phase module 41. In order to prevent a DC voltage feeder on the power supply system side and a polyphase motor 6 connected on the load side from being excessively damaged when worst-case situations occur, these components must be designed for a very much greater voltage rate of change, thus resulting in additional costs to a not inconsiderable level.
It would therefore be desirable and advantageous to obviate prior art shortcomings and to provide an improved method for inhibiting a converter with distributed energy stores, in which the voltage load in worst-case situations is significantly reduced.