1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of forming Group III-V semiconductor materials on Group IV substrates, and the resulting substrate structures.
2. Description of the Related Art
The most commonly used semiconductor materials are crystalline inorganic solids. Semiconductor materials are typically classified according to the periodic table group of their constituent atoms. Different semiconductor materials have different electrical and mechanical properties. Silicon is the most perfect crystalline material among known semiconductor materials. The abundance of silicon and the capability to fabricate single crystalline silicon wafers as large as 12″ have led to the economical production and domestication of ultra-large scale integrated (ULSI) circuits and integrated circuit products that are used in almost every aspect of daily life.
However, silicon cannot meet the demands of some optical devices or high speed, high power electronics. For example, silicon is an indirect band gap material which makes silicon an extremely inefficient light emitter. Thus, as compared to silicon, compound semiconductors have both advantages and disadvantages. For example, gallium arsenide (GaAs) has about six times higher electron mobility than does silicon, which allows for faster operation, a wider band gap, which allows operation of power devices at higher temperatures, and it is a direct band gap material that has more favorable optoelectronic properties than the indirect band gap of silicon. Moreover, gallium arsenide can be alloyed to ternary and quaternary compositions, with adjustable band gap width, allowing light emission at chosen wavelengths. Gallium arsenide can also be grown in a semi-insulating form, which is suitable as a lattice-matching insulating substrate for gallium arsenide devices. Conversely, silicon is robust, cheap and is readily available in the form of large wafers, whereas gallium arsenide is brittle and expensive. Therefore, it would be desirable to integrate III-V materials on silicon substrates so as to reduce processing costs while still maintaining the functionality of the devices made on the integrated III-V materials.
When depositing a Group III-V material, for example GaAs, epitaxially on a Group IV substrate, for example, a substrate comprised of silicon, germanium or silicon-germanium (SixGe1-x), the formation of the atomic layer sequence of the Group III atoms and the Group V layer atoms is not readily established. Typically, there are boundary regions between these different growth areas that can give rise to considerable structural defects, i.e., so-called anti-phase boundaries, which may adversely affect the performance of the resulting electronic device formed thereon. The reason such anti-phase boundaries are created is because, at an atomic level, there are always “steps” in the surface of the Group IV substrate. Such atomic level steps, especially single-steps, cause undesirable Group III-III bonding and Group V-V bonding.
FIGS. 1A-1B simplistically depict an illustrative example of such an anti-phase boundary. As shown in FIG. 1A, a Group III-V material 14 was epitaxially deposited above the surface 12S of an illustrative Group IV substrate 12, e.g., a crystalline silicon substrate. FIG. 1B is a simplistic, atomic-level depiction of the interface between the Group III-V material 14 and the Group IV substrate 12. As depicted, the Group III atoms (cross-hatched circles) and the Group V atoms (dark circles) are formed above the Group IV atoms (open circles) of the substrate 12. The surface 12S of the Group IV substrate 12 is depicted in FIG. 1B with a dashed line. As can be seen in FIG. 1B, in regions 16, there is anti-phase bonding between adjacent Group V atoms, while in regions 18 there is anti-phase bonding between adjacent Group III atoms. Such anti-phase bonds are problematic in that they tend to be weaker in strength and they also interrupt the period structure of the material. They also lead to the creation of the schematically depicted anti-phase boundary 20—a defect—which can adversely affect the electrical and/or mechanical properties of a device formed above or near the anti-phase boundary 20. For example, a transistor device formed above or near such an anti-phase boundary 20 may exhibit increased leakage currents and/or slower operating speed due to decreased charge carrier mobility at or near the anti-phase boundary 20. The ultimate cause of such anti-phase bonding is believed to be the creation of single (or odd) atomic layer “steps” on the (001) surface of the Group IV substrate 12, as depicted within the dashed line 22 in FIG. 1B.
In an attempt to avoid the undesirable anti-phase bonding, Group III-V materials are sometimes formed above Group IV vicinal substrates (a substrate whose surface normal deviates slightly from a major crystallographic axis) with an off-cut angle ranging from 0-15 degrees, or any other suitable angle. Such vicinal substrates have a higher density of such atomic level steps. However, vicinal substrates can be subjected to an anneal process so as to cause the single atomic level steps on the surface of the Group IV substrate to form double steps to eliminate the undesirable anti-phase bonding. However, if such vicinal substrates are used, the III-V materials grown on top will adopt the surface orientation of the vicinal substrate which will cause fabrication difficulties. In general, the off cut surface of a vicinal substrate is more reactive and surface passivation is more challenging.
The present disclosure is directed to various methods of forming Group III-V semiconductor materials on Group IV substrates, and the resulting substrate structures that may solve or reduce one or more of the problems identified above.