1. Field of the Invention
The present invention relates generally to semiconductor integrated circuits, and more specifically to the formation of self-aligned contacts in an integrated circuit. 2. Description of the Prior Art
In manufacturing high density integrated circuits, improving processing steps to allow for increased utilization of the area on a device is a concern. Masking layers are frequently used in the fabrication of an integrated circuit. When using a mask, it is important to account for errors in alignment between the mask and the device. Typically, this is done by building alignment tolerances into the size of the mask. During the manufacturing process, these tolerances add up such that the amount of available space on the device is reduced.
The self-aligned contact is widely used in high density circuits in order to save area. One approach to forming a self-aligned contact is to use a thick layer of oxide on top of a conductive layer in a gate. The purpose of the thick oxide layer is to protect the conductive layer during subsequent processing steps.
Typically, anisotropic etches are performed when fabricating gates and vias in an integrated circuit. It is common to overetch a layer to ensure complete removal of the material. The thick oxide protects the conductive layer from being etched into during formation of the gates and vias. This prevents the conductive layer from connecting to an active area in the substrate, which would result in shorting out the component.
The thick oxide required in this process, however, increases the severity of the topography of the device. As one skilled in the art will recognize, the severe topography makes subsequent processing steps more difficult. Tall features result in step coverage problems for later interconnect layers.
Therefore, it would be desirable to provide a method for forming self-aligned contacts which results in a more planar topography, without significantly increasing the complexity of the manufacturing process.