1. Field of the Invention
The present invention relates to a column redundancy circuit for a semiconductor memory. In particular, the invention relates to a column redundancy circuit for a semiconductor memory which facilitates the proper operation at high frequency of a high integration semiconductor circuit, whose memory array is divided into a plurality of array units, by selecting one of a normal data and a redundancy data which are outputted from the memory array.
2. Description of the Related Art
A column redundancy circuit using a column address signal as an input and connected to a memory array is known as a conventional column redundancy circuit. FIG. 1 is a block diagram illustrating the conventional column redundancy circuit.
A clock buffer 1 buffers an external clock signal EX_CLK, and outputs the buffered clock to a pulse width control unit 5. An address buffer 2 buffers an external address EX_ADD, and outputs the buffered address to both an address counter 3 and a column predecoder 6. In a burst mode, the address counter 3 counts the buffered external address EX_ADD, and outputs an internal address IN_ADD to a column redundancy unit 4 and the column predecoder 6. The column redundancy unit 4 determines whether to repair each memory array unit according to the external address EX_ADD and the input internal address IN_ADD, and outputs corresponding redundancy information RE_INF to a pulse width control unit 5.
The pulse width control unit 5 serves to output to the column predecoder 6 the internal clock signal IN_CLK for determining a pulse width of a column selecting signal according to the buffered external clock signal EX_CLK, and to output to a column decoder 7 a redundancy clock signal CLK_RE_INF having the redundancy information RE_INF.
The column predecoder 6 enables a normal address path in a non-redundancy mode, i.e., where a repair operation is not performed. Conversely, the column predecoder 6 disables the normal address path in a redundancy mode (i.e., where the repair operation is carried out), predecodes a column address from the address buffer 2, and outputs the predecoded column address Y_ADD to the column decoder 7. A pulse width of the predecoded column address Y_ADD is determined by the external clock signal EX_CLK from the clock buffer 1.
The column decoder 7 determines whether to repair according to the redundancy clock signal CLK_RE_INF, and outputs a normal column selecting signal NYS or a redundancy column selecting signal RYS to a memory array 8. That is, the column decoder 7 outputs the normal column selecting signal NYS when in the non-redundancy mode, and outputs the redundancy column selecting signal RYS when in the redundancy mode. The normal column selecting signal NYS and the redundancy column selecting signal RYS are signals for selecting a sense amplifier (not shown) in the memory array 8.
The memory array 8 consists of a plurality of normal memory cells and a plurality of redundancy memory cells. When the column decoder 7 outputs the normal column selecting signal NYS, the data stored in the normal memory cells of the memory array are read. When the column decoder 7 outputs the redundancy column selecting signal RYS, the data stored in the redundancy memory cells of the memory array 8 are read. The data read are inputted to a main amplifier 9 via an input/output line LIOT/B, amplified and sent to an output buffer (not shown).
FIGS. 2A and 2B are timing diagrams of the circuit in FIG. 1. FIG. 2A is a timing diagram in the non-redundancy mode, and FIG. 2B is a timing diagram in the redundancy mode. As shown in both figures, when the external clock signal EX_CLK is inputted, if a column address strobe signal CAS is inputted, the external address EX_ADD and the internal address IN_ADD change state. When a first predetermined time t1 lapses after the internal address IN_ADD transitions in a non-redundancy mode, the redundancy information signal RE_INF is at a high level, and the redundancy clock signal is also at a high level. That the redundancy information signal RE_INF is at a high level implies that the column redundancy circuit is operating in the non-redundancy mode. That the redundancy information signal RE_INF is at a low level means that the column redundancy circuit is operating in the redundancy mode.
When a second predetermined time t2 lapses after the first predetermined time t1, the normal column selecting signal NYS is enabled in the non-redundancy mode, as shown in FIG. 2A, and the redundancy column selecting signal RYS is enabled in the redundancy mode, as depicted in FIG. 2B.
The second predetermined time t2 is for determining whether the column predecoder 6 and the column decoder 7 operate the column redundancy circuit in the non-redundancy mode or the redundancy mode. This second predetermined time t2 is identical in the normal mode and the redundancy mode.
The second predetermined time t2 is clearly longer than when the normal column selecting signal NYS is outputted without a determination of whether to repair. As the second predetermined time t2 becomes longer, the overall processing speed of the column redundancy circuit is delayed.
In order to overcome such a disadvantage, another conventional redundancy circuit is provided.
FIG. 3 is a block diagram illustrating such a conventional redundancy circuit, As shown therein, the clock buffer 1, the address buffer 2 and the address counter 3 are identical in constitution and operation to those in FIG. 1. A pulse width control unit 31 outputs to a column predecoder 32 an internal clock signal IN_CLK for determining a pulse width of a column selecting signal according to a buffered external clock signal EX_CLK. An externally-inputted column address Y_ADD is inputted to a column decoder 33 via the address buffer 2 and then outputted to the column predecoder 32. The column decoder 33 outputs a column selecting signal YS to the memory array 34. Here, the column address Y_ADD and the column selecting signal YS do not relate to a repair operation. The memory array 34 includes normal memory cells and redundancy memory cells. The memory array 34 is not divided into a plurality of array units, unlike the memory array 8 as illustrated in FIG. 1. The data stored in the normal memory cells are inputted to a main amplifier 35 through a normal input/output line NLIOT/B, and the data stored in the redundancy memory cells are inputted to the main amplifier 35 via a redundancy input/output line RLIOT/B.
The column redundancy unit 36 determines whether to use data from the normal input/output line NLIOT/B or the redundancy input/output line RLIOT/B, and outputs redundancy information RE_INF to the main amplifier 35. According to the redundancy information RE_INF, the main amplifier 35 amplifies and outputs one of the data inputted to the normal input/output line NLIOT/B and the redundancy input/output line RLIOT/B.
As described above, in the circuit as shown in FIG. 3, when the column selecting signal YS (identical to the normal column selecting signal NYS as shown in FIG. 1) is outputted to the memory array 34, whether to repair is not determined prior to output, unlike the circuit in FIG. 1. Accordingly, extra time to determine whether to repair is not necessary. Thus, the circuit in FIG. 3 is faster in operation than the circuit in FIG. 1.
However, in FIG. 3 the memory array is not divided into array units, and thus redundancy efficiency is reduced. In addition, if the memory array is divided into a plurality of array units, and hence the number of the array units is increased, a load of the redundancy input/output line RLIOT/B is also increased. Accordingly, in order to employ the circuit of FIG. 3, the number of the array units must be limited. Thus, this circuit is not suitable for a high integration circuit where the memory array is divided into many array units.
Accordingly, it is an object of the present invention to provide a column redundancy circuit for a semiconductor memory which can improve an operational speed of a high integration semiconductor circuit where a memory array is divided into a number of array units.
In order to achieve the above-described object of the present invention, among others, there is provided a column redundancy circuit for a semiconductor memory, including a memory array including a plurality of array units respectively having a plurality of normal memory cells and a plurality of redundancy memory cells, each array unit outputting a normal data stored in the normal memory cell, and outputting a redundancy data stored in the redundancy memory cell; a column redundancy unit for outputting a redundancy enable signal according to a column address, a row address and a fuse short state; and a switch unit for selecting one of the normal data and the redundancy data from the memory array according to a logical state of the redundancy enable signal, and for outputting the selected data to a main amplifier.
In accordance with another aspect of the invention, a column redundancy circuit for a memory array having a plurality of array units, each array unit outputting a normal data from normal memory cells and a redundancy data from redundancy memory cells, includes a column decoder to output a normal column selecting signal and a redundancy column selecting signal to the memory array based on a column address; a column redundancy unit to output a redundancy enable signal based on the column address; a switch unit to select one of the normal data and the redundancy data output from the memory array based on the redundancy enable signal; and a main amplifier unit to amplify the selected data received from the switch unit.