1. Field of the Disclosure
The present disclosure relates generally to scan testing of integrated circuits and, more particularly, to a method of scan testing integrated circuits whereby the scan patterns shifted into the integrated circuit contain control information that regulate how the scan patterns will be used during the testing of the integrated circuit.
2. Description of Related Art
Semiconductor manufacturers must test integrated circuits they fabricate to determine which ones are good and which ones are bad. Testing of integrated circuits is achieved by having a tester contacts the integrated circuits and apply test patterns to the integrated circuits. Today more and more integrated circuit testing is being performed by low cost testers. Low cost testers are achieved primarily in two ways; (1) decreasing the number of test contacts required between the tester and integrated circuits under test, and (2) including more efficient design for test circuitry in the integrated circuit for interfacing to the tester and executing tests. Decreasing the number of contacts between the tester and integrated circuits enables more integrated circuits to be contacted by the tester and tester in parallel. Including more efficient design for test circuitry in the integrated circuits allows the integrated circuits to be tested more quickly over the reduced contact interface to the tester.