Clock and data recovery (CDR) operations are performed in many communications circuits. Digital communication receivers must sample an analog waveform and then detect the sampled data reliably. The phase of the analog waveform is typically unknown and there may be a frequency offset between the frequency at which the original data was transmitted and the nominal receiver sampling clock frequency. The CDR function is to properly sample an analog waveform such that when the sampled waveform is passed through a data detector, the data is recovered properly despite the fact that the phase and frequency of the transmitted signal are not known. CDR architectures implemented on an integrated circuit chip should not only perform the CDR function robustly but should be area and power efficient.
As illustrated in FIG. 1, a typical serializer/deserializer (Serdes) communication “macrocell” consists of multiple channels (Channel 0, Channel 1, . . . , Channel P), each performing its own CDR function. A common reference clock circuit 102 provides a clock (REFCLK) 104 which is used in each channel to sample the analog waveform 106. The CDR feedback loop must adjust the phase and frequency of the nominal clock to produce a modified clock, a recovered clock 110, which can sample the analog waveform to allow proper data detection 112. A typical data detector 108 might be a simple slicer (decision device based on an amplitude threshold) or a more complicated detector such as a sequence detector. Since the CDR architecture hardware is replicated multiple times, area and power efficiency of the CDR hardware is an important consideration.
Various methods exists in the prior art for performing this CDR function. FIG. 2 illustrates one well known CDR architecture which makes use of an analog loop filter and a voltage controlled oscillator (VCO) to provide the recovered clock. Integral to the depicted analog loop filter 204 is an analog charge pump (not illustrated) which processes the output of phase detector 202 for use by the analog loop filter 204. Another approach is shown in FIG. 3 where digital loop filter 302 controls a phase selection circuit (PSC) 304 which continually adjusts the phase of the reference clock to effectively modify its phase and/or frequency to produce the recovered clock 110. The digital loop filter 302 may consist of one or more sub-filters. One significant drawback to this approach is that the loop filter and PSC must operate at the full high speed data rate. Further, the fixed point arithmetic performed by the digital loop filter must be done with relatively high resolution (more than 9 bits, in some applications 18 bits) and so involves complex fixed point signed arithmetic. Since the complex fixed point arithmetic operates at the full date rate, this results in a relatively large area and power for the digital loop filter and resulting CDR.
More recent prior art CDR architecture has employed a digital loop filter in combination with a VCO. The input to the digital loop filter has been decimated. The process of decimation involves discarding samples so that data can be processed at a lower rate of speed in the digital loop filter where as noted above, complex high resolution fixed point signed arithmetic operations take place. Typically, before discarding samples, they are processed by the decimation filter to minimize the information loss from the phase detector. As used herein, the process of discarding samples is called downsampling and the overall process of decimation filtering and downsampling is called decimation. A high level block diagram of a decimated loop filter is shown in FIG. 4 where downsampling 404 by a factor of D occurs after the decimation filter 402. Consequently, only one out of every D high speed samples is retained and processed by the digital loop filter 302. It should be noted that while the clock sampling phase changes only at 1/Dth of the high speed rate, the recovered sampling clock is a full rate clock.
Although beneficial, the above decimated loop architecture has limitations: (i) It is still fundamentally limited in operating at extremely high speeds as it uses only one sampling clock 110 to provide samples to only one phase detector 202. This means that although the decimation process allows the digital loop filter to work at a lower speed, in a practical implementation a bottle neck will still occur as the phase detector 202 and portions of or the entire decimation filter must operate at the full data rate speed; (ii) a common decimation filter 402 and downsampling factor 404 is necessarily used for the entire loop filter which may limit the area/power tradeoff savings in the loop filter; and, (iii) the architecture uses a VCO 206 instead of a PSC to perform the timing updates.
The present invention overcomes these shortcomings in the prior art and results in a CDR architecture that reduces such processing bottle necks and does so in an manner that is area and power efficient.