1. Field of the Invention
The present invention relates to a method of fabricating a silicon on insulator (SOI) wafer and an SOI wafer fabricated by the same, and more particularly, to a method of fabricating a nano SOI wafer with a device region having a nano thickness and a nano SOI wafer fabricated by the same.
2. Description of the Related Art
In a bulk silicon substrate used for a general silicon integrated circuit, since a junction breakdown occurs in a junction isolation under a supply voltage of plus or minus 30 V when proper doping amount and dimension are provided, it is improper to apply a high voltage. In addition, the junction isolation is not effective under a high radioactivity environment due to a transient photocurrent generated in a p-n junction according to gamma rays. Accordingly, a silicon on insulator (SOI) technique where an insulator completely surrounds a device is developed instead of the p-n junction. A circuit fabricated in such an SOI substrate requires a simpler fabricating process and a simpler resultant structure compared to a circuit fabricated in a bulk silicon substrate so that a chip size may be reduced. In addition, a parasitic capacitance is reduced along with the chip size so that the operation speed of the circuit increases.
Such an SOI technique includes a silicon on sapphire (SOS) technique, where a hetero epitaxial silicon layer is grown on a sapphire, a separation by implanted oxygen (SIMOX) technique, where oxygen ions are implanted into a silicon substrate and annealed to form a buried silicon oxide layer, and a bonding SOI technique, where at least one wafer having a dielectric on a surface and the other wafer are bonded.
A well known example using the bonding SOI technique is a smart-cut process which is used for fabricating a unibond wafer. In the smart-cut process, hydrogen ions are implanted into one of the wafers to be bonded, a fine bubble layer is formed, and a wafer is cleaved with respect to the bubble layer by a thermal process. FIG. 1 illustrates processes for fabricating an SOI wafer using a conventional smart-cut process.
Referring to FIG. 1, a base wafer and a bond wafer, that will be bonded in a subsequent process, are prepared in step S10. The base wafer, referred to as a handling wafer, physically supports an SOI wafer. The bond wafer is a wafer, referred to as a device wafer, on which channels of a semiconductor device will be formed.
Thereafter, a thermal oxidization process is performed on the bond wafer formed of mono-crystalline silicon to form an oxide layer, i.e., a silicon oxide layer, on the surface of the bond wafer in step S12. The silicon oxide layer performs as a buried oxide layer (BOX) in the SOI wafer. Here, the silicon oxide layer may be formed to a thickness of about tens to thousands of A when necessary.
Hydrogen ions of high voltage are implanted into the bond wafer in step S14. Here, the acceleration voltage of the hydrogen ions is about 125 KeV, and a hydrogen dose amount is about 6×1016 cm−2. Accordingly, a hydrogen ion implantation unit having a projection range distance (Rp) is formed under the surface of the bond wafer, beneath the silicon oxide layer, to a predetermined depth.
Next, the base wafer and the bond wafer are cleaned to remove contaminants from the surfaces of the wafers and the wafers are horizontally bonded in step S16. Here, the base wafer is horizontally laid and the silicon oxide layer portion of the bond wafer is placed above the base wafer to be parallel with the base wafer. Thereafter, the bond wafer is lowered at a room temperature so that the surfaces of the wafers simultaneously contact each other and bond together. Here, the wafers are bonded by a hydrogen bond under a hydrophillic condition.
Subsequently, the hydrogen ion implantation portion is cleaved by a thermal process performed at a high temperature in step S18. The thermal process is performed under a nitrogen atmosphere at a temperature of about 550° C. for about one hour. Accordingly, bubbles in the hydrogen ion implantation portion are interacted in the thermal process to form a sufficient amount of blisters and the blisters are spread to generate a flake occurrence so that the cleavage occurs. After the cleavage process, the amount of root mean square roughness (rms) value on the surface of the silicon layer remaining on the bond wafer is about 100 to 120 Å and the thickness of the remaining silicon layer is about 9000 Å.
A chemical mechanical polishing (CMP) is performed on the cleaved surface of the silicon layer in step S20. Here, the CMP is performed until the thickness of the device region, on which channels of the semiconductor device will be formed, becomes a desired thickness.
Meanwhile, as it is required for a semiconductor device formed on an SOI wafer to be highly integrated and operated at a high speed, and use a low amount of electric power, the thickness of a device region or a channel region of a semiconductor device in the SOI wafer becomes smaller. In addition, the thickness of a BOX becomes smaller. Accordingly, a thick SOI wafer with a device region or a channel region in the silicon SOI wafer having a thickness to about more than 1000 nm is used for forming MEMS, sensors, photodiodes, or bipolar power devices, and a thin SOI with a device region having a thickness to about 50 to 1000 nm can be used for forming micro displays or partially depleted CMOSs. However, a fully depleted CMOS, a nano CMOS device, or a single-electron device requires a nano SOI wafer with a device region having a thickness of about less than 50 nm.
A method of fabricating a nano SOI wafer by using a conventional smart-cut process has a plurality of disadvantages as follows.
In the conventional method, a hydrogen ion implantation unit of a bond wafer has to be cleaved, a cleaved surface has to be planarized, and a CMP has to be performed on the cleaved surface until a device region has a desired thickness. However, a CMP is a time and money consuming process, and the thickness of a central portion and the thickness of a peripheral portion of a wafer are deviated by the CMP. In addition, the CMP may generate cracks.
Since hydrogen ions are implanted into a bond wafer in a high-energy voltage environment, the projection range distance of the hydrogen ions remarkably increases so that a thick silicon layer having a thickness of about 9000 Å is remained after a subsequent cleavage process. Accordingly, the CMP requires large amounts of time and silicon layer to fabricate a nano SOI wafer with a device region having a thickness of about 50 nm, i.e., 500 Å.
In addition, a conventional horizontal bonding process, in which a bond wafer and a base wafer are bonded, generates defects such as voids on a bonding surface.