Since the invention of integrated circuits, the semiconductor industry has experienced a continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows for more components to be integrated into a given chip area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvement in lithography has resulted in considerable improvements in 2D integrated circuit formation, there are physical limitations to the density that can be achieved in two dimensions. One of these limitations is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
Three-dimensional integrated circuits (3D IC) are therefore created to resolve the above-discussed limitations. Higher device density has been achieved using 3D IC technology, and allowing the bonding of up to six layers of wafers. As a result, the total wire length is significantly reduced. The number of vias is also reduced. Accordingly, 3D IC technology has the potential of being the mainstream technology of the next-generation integrated circuit.
Conventional methods for forming 3D IC also include die-to-wafer bonding, wherein a plurality of individual dies is bonded to a same wafer. An advantageous feature of the die-to-wafer bonding is that the size of the dies may be smaller than the size of the chips on the wafer. Through-silicon vias, also referred to as through-wafer vias, are used to connect the integrated circuits in the dies and the integrated circuits in the wafer. FIG. 1 illustrates a conventional 3D IC including through-silicon vias. Dies 4 and 6 are stacked on bottom wafer 2, wherein each of the dies 4, 6 and bottom wafer 2 includes integrated circuits. Through-silicon vias 8 are formed in dies 4 to connect the underlying wafer 2 to the overlying dies 6.
After dies 4 and 6 are bonded onto wafer 2, a wafer probing is performed to the stacked dies. Only those stacked dies that pass the probe tests are packaged. By identifying problematic stacked dies at an early stage, packaging costs are saved. Typically, the test programs for probing the stacked dies are generated by merging individual test programs for testing dies 4 and 6, and dies on wafer 2. However, since dies 4 and 6 and wafer 2 are separately manufactured, their test programs may be generated for different platforms. For example, some of the test programs are UNIX-based, and some are Window-based. Merging these test programs thus becomes a very challenging task.
Accordingly, what is needed in the art are test methods and/or test structures for probing stacked dies without incurring difficulties in merging the test programs.