Modern integrated circuits are generally produced by creating several identical integrated circuit dies (usually square or rectangular areas) in an area on a single (usually round) semiconductor wafer, then scribing and slicing the wafer to separate (singulate, dice) the dies (chips) from one another. An orthogonal grid of "scribe line" (kerf) areas extends between adjacent dies, and sometimes contain test structures, for evaluating the fabrication process. These scribe lines areas, and anything contained within them, will be destroyed when the dies are singulated from the wafer. The singulated (separated) dies are then individually packaged, and may be tested after packaging.
Under ordinary circumstances, pressure to maximize the useful, or productive area of a wafer dictates that scribe line area be kept as small as possible. Dies are laid out on a wafer in a pattern that is packed as tightly as possible. Scribe line widths are only large enough to ensure that the dies can be separated without damage to the area of the dies.
Circuits and active elements on the dies are created while the dies are still together (un-singulated) on the wafer by ion deposition, electron beam lithography, plasma etching, mechanical polishing, sputtering, and numerous other methods which are well known to those skilled in the art of semiconductor fabrication. These processes are highly developed and are capable of producing extremely complicated circuits on the dies at a relatively low cost.
The complexity of integrated circuits is limited, in part, by the purity of the semiconductor wafers available. These wafers contain minuscule defects which may be distributed randomly throughout the wafer, especially the surface where integrated circuit elements are fabricated. The larger the integrated circuit (i.e., the greater its "die size"), the greater the probability that it will be affected by such a defect. Integrated circuits which intersect a defect on the semiconductor wafer are generally rendered non-functional, and therefore useless. Improvements in the wafer production process are yielding purer wafers with smaller defect sizes and densities.
By reducing the size of individual circuit elements, e.g. transistors, it has become possible to place more circuitry in the same area (e.g., die site) which would previously have been occupied by larger circuit elements of lesser complexity. However, the same size reductions which enable greater circuit complexity also render the resulting smaller circuits more sensitive to more minuscule defects in the semiconductor wafer.
Trade-offs between circuit complexity (i.e., number of transistors and circuit area) and anticipated yield (i.e., the number of "good" circuits per wafer) are made by integrated circuit manufacturers based upon a number of factors. The higher the yield, the less a circuit costs the manufacturer to produce, permitting a lower market price.
Among the problems faced by integrated circuit manufacturers are packaged chips (dies) which fail in final test and, even worse, chips which pass final test but which have undetected flaws due to an inability to test them completely. The inability to test an integrated circuit completely arises from the fact that while circuit density and complexity has increased dramatically, the number of Input/Output (I/O) pads which can feasibly be disposed to a chip has not increased correspondingly. Generally, pads are much larger than individual circuit elements. This creates serious testing problems, since ever-increasing amounts of test information must be obtained through the use of a relatively limited number of I/O pads (test points).
"Burn-in" is a process whereby a chip (die) is either simply powered up ("static" burn-in), or is powered up and has signals exercising to some degree the functionality of the chip ("dynamic" burn-in). In both cases, burn-in is typically performed at an elevated temperature--the object being to detect chips that are defective. Burn-in is usually performed on a die-by-die basis, after the dies are separated (diced) from the wafer.
Another technique for burning-in dies, prior to dicing (on the wafer), is to mechanically place test probes or bond wires on each die, or on pads associated with each individual die and located in the scribe lines between the dies.
Another technique for burning-in dies, prior to dicing (on the wafer), is to provide a common network of power and ground conductors in the scribe lines, the power and ground lines connected to all of the dies on a wafer. Generally, the power and ground lines simply power up the device for static burn-in, but built-in self test (self-starting, signal-generating) circuitry on the chip can also provide signals on power up to exercise some of the functionality of the chip. This is discussed in copending, commonly-owned U.S. patent application No. 07/933,325, filed Aug. 21, 1992 by Rostoker, et al., entitled METHODS FOR DIE BURN-IN, filed by Rostoker and Dell'Oca.
It should be noted that where "power and ground" are referred to herein, any and all power connections are included. Recent trends in technology have tended to push the design of semiconductor devices in the direction of single voltage supplies, and this terminology reflects this trend. However, herein, the term "power and ground" refers to all required power supply voltages.
Another technique for die burn-in, on the wafer, is discussed in the aforementioned copending, commonly-owned U.S. patent application No. 07/933,325, filed Aug. 21, 1992 by Rostoker, et al. This technique involves bonding wires to the wafer either (1) to bond pads on each die, or (2) to bond pads for each die in adjacent scribe lines.
Generally, for either burn-in or testing, difficulties arise in a few areas:
1) Traditional methods of testing do not provide adequate fault coverage to guarantee that the dies identified as functional ("good") are indeed fully functional;
2) A large number of test points is generally required, necessitating cumbersome expensive equipment to interface with the wafer for testing; and
3) Routing channels for signal interconnections can require a great deal of surface area.
In recent years, a number of schemes have arisen to address the testability problems of large, complex integrated circuits. Some examples of these techniques are known as SCAN or "Scan-path testing" (ref T. W. Williams and K. P. Parker, "Design for Testability--A survey" Proc. IEEE, Vol. 71, pp. 98-112, Jan., 1983), BIST or "Built-in Self-Test" (ref. E. B. Eichelberger and T. W. Williams, "A logic Design Structure for LSI Testing" Proc. 14th Design Automation Conf., June, 1977, 77CH1216-1C, pp. 462-468; also, E. J. McClusky, "Built-In Self-Test Techniques" and "Built-In Self-Test Structures" IEEE Design and Test, Vol. 2, No. 2, pp. 437-452, April, 1985). These techniques deal with testing large integrated circuit structures by incorporating on-chip test facilities (structures) which allow stimuli to be applied to portions of the circuit and responses to be readily read back and observed. SCAN and BIST testing are based on providing a means for accessing the storage elements of a sequential circuit (e.g. flip-flops) and using them to control and/or observe various portions of the integrated circuit to which they are applied.
U.S. Pat. Nos. 3,806,891; 4,293,919; and 4,513,418 (assigned to the IBM Corporation) describe methods whereby the flip-flops of a circuit may be used as test points by re-configuring them into a serial chain (shift-register) and used to shift in test data and to shift out test results.
U.S. Pat. No. 4,340,857 (Fasang) describes the use of linear feedback shift registers (LFSRs) for generating test patterns and for compacting test results.
U.S. Pat. No. 4,423,509 (Feisel) describes yet another use of the flip-flops of an integrated circuit as test points.
Another technique applicable to a broader range of test problems is described in U.S. Pat. No. 4,749,947 (Gheewala), entitled "Grid-Based, `Cross-Check` Test Structure for Testing Integrated Circuits", incorporated by reference herein. The patent is directed to providing a grid of externally--as well as individually-accessible probe lines and sense lines with electronic switches at the crossings of these probe and sense lines. One end of each switch is connected to a test point on a die, which test point is intended to be monitored or controlled during a testing regimen, and the other end of each switch is connected to an associated sense line. The ON or OFF state of each switch is governed by a control input from a probe line. The probe and sense lines are connected to external test electronics. By excitation of an appropriate probe line, and monitoring (or exciting) an appropriate sense line, test signals present at any one of the test points can be monitored (or controlled). Generally, four lines per die are required: power, ground, a plurality of probe lines, and a plurality of sense lines. (In the case of a die requiring multiple supply voltages,
U.S. Pat. No. 4,749,947 also suggests the possibility of cross-checking multiple ICs on a wafer. FIG. 7 therein shows a grid of numerous probe and sense lines criss-crossing multiple ICs. FIGS. 9a and 9b therein also show many ICs being cross-checked on a wafer. In FIG. 9a, the usually unused "kerf area" (scribe line) lying between adjacent ICs is used to place probe points for the probe and sense lines. In FIG. 9b, it is suggested that I/O pads on "other" (typically adjacent) ICs can be used as probe points for cross check testing a particular ICs, when the "other" ICs are not being cross checked.
U.S. Pat. No. 4,937,826 (Gheewala, et al.), entitled "Method and Apparatus for Sensing Defects in Integrated Circuit Elements", incorporated by reference herein, describes an improvement to the technique of the aforementioned U.S. Pat. No. 4,749,947, involving pre-charging the sense lines to adjust detection levels. The patent also discloses a method of reducing test patterns to Boolean expressions, using "path sensitization".
U.S. Pat. No. 4,975,640 (Lipp), entitled "Method for Operating a Linear Feedback Shift Register as a Serial Shift Register with a Crosscheck Grid Structure", incorporated by reference herein, describes a further improvement to the aforementioned U.S. Pat. No. 4,749,947, whereby a linear feedback shift register (LFSR) may be used in combination with the grid based cross check structure to reduce the number of logic structures required to shift data out serially, and to provide increased controllability over the cross check structure with compaction of the test result data while dramatically reducing the number of I/O points required to accomplish the testing.
The techniques of testing, particularly cross-check testing described above are largely per-die-oriented, with little or no teaching of efficient implementation at wafer level.
Similarly, the techniques of static or dynamic burning-in, described above, fail to show efficient implementation at wafer level.
What is needed is efficient techniques for implementing cross-checking (testing) and dynamic burning-in at wafer level. For example, with regard to the cross-check techniques, in order to efficiently test numerous dies on a wafer, it would be desirable to dramatically reduce the number of probe and sense lines required. A reduction on the order of "n"/2:1 where "n" is the number of dies on the wafer is this kind of "dramatic" reduction (i.e., a reduction in the number of probe and sense lines of 50:1 for a wafer with 100 dies on it is a "dramatic" reduction over known cross-check techniques.