Network switches/switching units are at the core of any communication network. A network switch typically has one or more input ports and one or more output ports, wherein data/communication packets are received at the input ports, processed by the network switch through multiple packet processing components and stages in the network switch, and routed by the network switch to other network devices from the output ports according to control logic of the network switch.
When a data packet is routed through the network switch, a copy of the data encapsulated in the packet (packet data) can be temporarily maintained in a memory/buffer of the network switch. Various components of the network switch can access and process the copy of the packet data in the buffer via a buffer manager without having to maintain multiple identical copies of the data by themselves. During their operations, the various components of the network switch may each perform a plurality of operations on the data of the packet, and may each generate one or more pieces of metadata associated with the packet data. Here, the metadata of the packet is information that is of interest to the network switch and can be utilized by the components of the network switch to process the data of the packet. For non-limiting examples, various pieces of metadata of a packet may include length and/or buffering location(s) of the packet, timing constraints on the packet, destination of the packet, reference count to the copy of the data of the packet in the buffer, number of copies of the packet that need to be created or deleted, etc.
During operation of the network switch, various pieces of metadata of the packet are routed along different (metadata) paths among the various components of the network switch, wherein each path includes one or more cells/components and a plurality of segments of interconnect wires/bus connecting these cells/components. Transmitting the pieces of metadata over the metadata path will encounter timing delay, which includes the internal delay of the cells/components on the metadata path and the interconnect delay over the interconnect wires of the segments of the path. For proper operation of the network switch, the various pieces of metadata may be timing correlated or timing dependent on each other. For a non-limiting example, a first piece of metadata of a packet that includes instructions to increase the reference count to the data of the packet must arrive at a component (e.g., buffer manager) before a second piece of metadata that includes instructions to decrease the reference count to the data of the same packet in order to avoid the so called race condition/problem, where copy of the packet data is deleted from the buffer prematurely because reference count is reduced to zero.
It is thus desirable to be able to automatically determine the timing constraints imposed by the metadata of a packet on the network switch and to adjust the metadata paths of a network switch to meet such timing constraints.
The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent upon a reading of the specification and a study of the drawings.