The present invention relates to a Duty Cycle Corrector (DCC), and more particularly, to a technique for correcting duty cycle with one clock to improve characteristics of DCC.
In semiconductor devices that operate based on a clock, a technique of controlling a duty cycle of the clock exactly is important. A clock duty of 50% indicates that a ‘high’ level interval of a clock signal is identical to a ‘low’ level interval of a clock signal.
For a semiconductor memory device, data should be input/output exactly in synchronization with a rising edge and a falling edge of a clock. In such a semiconductor device, if a duty ratio of clock is not exactly 50%, a timing mismatch occurs between the rising edge and the falling edge, which makes data not input/output at exact timing. Therefore, a semiconductor memory device adopts a DCC to correct a duty cycle of clock exactly to 50%.
FIG. 1 is a block diagram illustrating a conventional DCC for correcting a duty cycle of clock by mixing clocks.
In a conventional DCC 130 that corrects a duty cycle by mixing clocks CLK_1 and CLK_2, since the duty cycle is corrected by mixing the two clocks CLK_1 and CLK_2 having synchronized rising edges, a Delay Locked Loop (DLL) of dual loop structure is arranged in front of the DCC 130.
The DLL compensates for skew between an external clock EXTCLK and the internal clocks CLK_1 and CLK_2, and includes a first delay locking unit 110 and a second delay locking unit 120. The first delay locking unit 110 adjusts a delay value of the first clock CLK_1 to synchronize its rising edge with a rising edge of the external clock EXTCLK when there is a delay in the first clock CLK_1 while it passes through a chip. The second delay locking unit 120 adjusts a delay value of the second clock CLK_2 as an inverted clock of the first clock to synchronize its rising edge with a rising edge of the external clock EXTCLK when there is a delay in the second clock CLK_2 while it passes through the chip.
The present invention to be described later relates to the DCC 130 but does not relate directly to the DLL 110 and 120 and, since designing the DLL of dual loop structure is well-known to those skilled in the art, a further description thereon will be omitted herein.
The conventional DCC 130 mixes the first clock CLK_1 with the second clock CLK_2 as output clocks of the DLLs 110 and 120, and generates clocks CLK1_OUT and CLK2_OUT having corrected duty cycle. The first clock CLK_1 and the second clock CLK_2 have opposite duties (e.g., the first clock has a duty ratio of 7:3 and the second clock has a duty ratio of 3:7) and are synchronized with each other at their rising edge. Therefore, mixing the two clocks CLK_1 and CLK_2 may generate the clocks CLK1_OUT and CLK2_OUT having exactly 5:5 duty.
FIG. 2 a timing diagram showing a schematic operation of the conventional DCC 130.
The first clock CLK_1 and the second clock CLK_2 having locked delay values are output from the first delay locking unit 110 and the second delay locking unit 120 of the DLL. Referring to the drawing, it can be seen that the first clock CLK_1 and the second clock CLK_2 have independently locked delay values but have identically aligned rising edges.
The DCC 130 mixes the first clock CLK_1 with the second clock CLK_2. Since rising edges of the first clock CLK_1 and the second clock CLK_2 are aligned with each other, rising edges of mixed clocks CLK1_OUT and CLK2_OUT (upon completion of operation, CLK1_OUT=CLK2_OUT) remain unchanged. However, falling edges thereof have middle values of the falling edge of the first clock CLK_1 and the second clock CLK_2. Thus, the clocks CLK1_OUT and CLK2_OUT whose duties are corrected to 50% are output from the DCC 130.
The conventional DCC described above generates clocks having 50% duty by mixing the two clocks having opposite duties. However, although the two clocks having opposite duties are mixed, rising edges of the two clocks should be aligned with each other. Thus, there is a need for the DLL of dual loop structure in front of the DCC.
In short, since the conventional DCC adopts a technique of combining two clocks to correct a duty cycle of clock, it needs the DLL of dual loop structure in front of the DCC, which increases the overall area of the DLL two times.