The present invention relates to the field of electronic design automation and circuit timing analysis models. In particular, the present invention pertains to the application of layout parasitic data in a hierarchical timing analysis.
Integrated circuits can be represented as netlists within electronic design automation systems. A circuit timing analyzer takes a netlist of a circuit and the associated timing information for a circuit, and abstracts them to get a timing representation (xe2x80x9cmodelxe2x80x9d) of the circuit. The timing model is then used by a circuit analyzer to estimate the overall performance of the circuit, identify critical paths in the circuit, and find timing violations. Prior art circuit analyzers are described by U.S. Pat. No. 5,740,347, entitled xe2x80x9cCircuit Analyzer of Black, Gray and Transparent Elements,xe2x80x9d by Jacob Avidan, issued Apr. 14, 1998, and by U.S. Pat. No. 5,790,830, entitled xe2x80x9cExtracting Accurate and Efficient Timing Models of Latch-Based Designs,xe2x80x9d by Russell B. Segal, issued Aug. 4, 1998, herein incorporated by reference in their entirety.
For analysis purposes, a circuit can be considered as a collection of interconnected functional blocks. A functional block includes the collection of hardware components that make up the circuit as well as the software structures used to represent the circuit, such as nodes (a node being a point of connectivity, including an input or output of the circuit). The circuit can be specified hierarchically, with higher level functional blocks encompassing one or more lower level blocks. A higher level functional block may be a subcircuit composed of other lower level functional blocks that may also be subcircuits. The more the circuit is abstracted, the lower the accuracy of the models becomes.
To facilitate the design and analysis of a complex circuit, a hierarchical timing analysis is typically performed. At the highest level of the hierarchy, the overall circuit is analyzed using a multiplicity of integrated timing models that each represent a functional block at the next lower level. Each of these functional blocks is in turn composed of a multiplicity of timing models that each represent a functional block at the next lower level, and so on.
In practice, the timing modelsare typically created starting at the lowest level of the circuit, from there proceeding level-by-level to the highest level. Each lowest level functional block is designed and analyzed. A timing model is created for each lowest level functional block and these timing models are fed to the next higher level, where the models are integrated and an analysis is performed of an integrated mid-level functional block. Other mid-level functional blocks are similarly formed and analyzed. Each of the mid-level blocks is then represented by a timing model which is fed to the next higher analysis level, and so on until at the highest level the overall circuit can be assembled and analyzed using a multiplicity of integrated timing models each representing relatively large functional blocks.
Prior Art FIG. 1A illustrates a plurality of functional blocks (blocks A, B, C and D) located within a larger functional block 10 (at the highest level, functional block 10 can represent the entire integrated circuit). By way of example, a single wire is shown connecting block A 20 and block D 30. For the purposes of this discussion, the wire is divided into three segments: segment 40a is within block A 20, segment 40b runs between block A 20 and block D 30, and segment 40c is within block D 30.
Blocks A 20 and D 30 (as, well as blocks B and C) are each represented by a timing model. In the prior art, the timing model of the timing arc for block A 20 incorporates the xe2x80x9crawxe2x80x9d layout parasitic data (e.g., R and C) for that block, including that for wire segment 40a. In other words, the layout parasitics are considered when generating the timing arcs for block A 20. The layout parasitics are modeled linearly and incorporated into the timing arc model of block A 20. Similarly, the timing model for block D 30 incorporates the effects of the layout parasitic data for that block, including that for wire segment 40c. As described above, in a hierarchical timing analysis, these timing models are integrated with the other timing models in a circuit analyzer in order to perform the timing analysis at the next highest level (that is, at the level of functional block 10). In the prior art, wire segment 40b is incorporated into the timing analysis at the level of functional block 10.
The prior art is problematic when the lower level models are used in an analysis at a higher level in the hierarchical timing analysis, because the higher level timing analysis has its own layout parasitic data. As a result, the wire from block A 20 to block D 30 inherently has a dual modeling. That is, the parts of the wire inside the lower level timing models (e.g., segments 40a and 40c) are represented linearly (using, for example, a lookup table) while the part of the wire in the higher level timing model, outside the lower level models (e.g., segment 40b), is represented nonlinearly using raw layout parasitic data. Adding the linear representations and the nonlinear representation can yield inaccurate results; this loss of accuracy is particularly acute at lower levels in the timing analysis, where the circuit size is smaller. Thus, a disadvantage to the prior art is that the duality in the models, with regard to the different treatment of layout parasitic data inside and outside of the timing models, can reduce accuracy in the timing analysis.
Prior Art FIG. 1B illustrates an exemplary higher level block (e.g., circuit 50) which includes a lower level block (e.g., subcircuit 55) that is at the transistor level of a circuit. Layout parasitic data are represented by a combination of resistors and capacitors (e.g., 60a, 60b, 61a, 61b, 62a, 62b, 63a, 63b, 64a and 64b). For an analysis at the transistor level, inverter 56 drives the gates of transistors 57, 58 and 59 through the netlist described by 60a, 60b, 61a, 61b, 62a, 62b, 63a, 63b, 64a and 64b. For a hierarchical timing analysis, in the model for subcircuit 55 (represented using dashed lines as model 70), inverter 56 drives pin 65 through the netlist described by 60a and 60b. In this case, a netlist inside model 70 is not visible when running the timing analysis for circuit 50. Instead, the effects of the netlist inside model 70 are incorporated in the model for subcircuit 55. Thus, the layout parasitics that belong to circuit 50 are analyzed differently than the layout parasitics that belong to model 70, introducing accuracy problems in the timing analysis.
In addition, when a circuit analyzer is applied at the transistor level of a circuit (that is, at the lowest level in the hierarchy of the timing analysis), a higher level of accuracy is desired for the circuit analysis. Therefore, a reduction in accuracy due to the prior art technique for modeling layout parasitics at the interface pins is particularly undesirable at the transistor level.
Accordingly, a need exists to resolve the modeling duality caused by the treatment of layout parasitic data at a lower level versus a higher level of a hierarchical timing analysis. A need also exists for a device or method that can be utilized at the transistor level. The present invention solves these needs. These and other objects and advantages of the present invention will become clear to those of ordinary skill in the art in light of the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
The present invention provides a method of generating timing models that addresses the modeling duality caused by the treatment of layout parasitic data at the lower and higher levels in a hierarchical timing analysis. The present invention also provides a method and timing model that can be utilized at the transistor level.
The present invention pertains to a modeling method to improve the accuracy of a circuit timing analysis that more closely models timing information associated with layout parasitics that are connected to interface nodes of a transistor-level subcircuit. The modeling method is for performing a hierarchical timing analysis of a circuit that can include a transistor-level subcircuit.
In the present embodiment, for the timing analysis, a circuit is separated into a higher level block and a lower level block, where the higher level block and the lower level block are mutually exclusive. Certain data (e.g., the layout parasitic data associated with the interface pins or the xe2x80x9cinterface small nodesxe2x80x9d) of the lower level block are set aside. A timing model (timing arc or timing arcs) for the lower level block is created without using these data; that is, one or more timing arcs are generated without using the layout parasitic data connected to the interface pins or the interface small nodes (collectively, the xe2x80x9cinterface nodesxe2x80x9d). The resultant model of the lower level block then includes the timing arcs plus the raw layout parasitic data. This resultant model is then passed up to the timing analysis performed for the next higher level in the hierarchical timing analysis. As a result, the timing analysis of the higher level block is performed with a circuit analyzer that uses the timing model and the layout parasitic data for the interface nodes in the lower level block. Thus, the layout parasitic data associated with the interface nodes in the lower level subcircuit are preserved and used in the higher level circuit timing analysis to provide an accurate non-linear timing analysis of the layout parasitics.
At the lowest level of the hierarchy, the lower level block can comprise one or more transistors.
In one embodiment, the layout parasitic data are represented in the spf format.
In one embodiment, the capacitances for the interface small nodes of the lower level block are saved.
Thus, the layout parasitic data associated with an interface node of a lower level of a circuit (including, for example, the transistor level) are preserved and used in the next higher level circuit timing analysis. The layout parasitics are therefore uniformly modeled along the entire length of, for example, a wire segment, including the interface pins that connect timing models. A non-linear timing computation can be used for the wire segment, improving the overall accuracy of the timing analysis.