Ferroelectric memory arrays are generally well known in the data processing arts and include a plurality of word line rows and a plurality of bit line columns. The rows of word lines normally each include a plurality of metal-oxidesilicon (MOS) access transistors at the juncture of each word line and bit line. In one known type of ferroelectric memory circuit, a ferroelectric capacitor is connected between each access transistor and a plate line, and a sense amplifier is connected to receive two complementary input signals (BIT and BIT) from adjacent bit lines extending from a single cell consisting of two access transistors and two ferroelectric capacitors. When appropriate switching voltages are applied to the gates of the access transistors and to the plate lines common to one word line row, the access transistors in this word line are turned on so that the sense amplifier can then read the binary state of the accessed cells. The BIT and BIT signals are then amplified in the sense amplifier, and the sense amplifier determines the voltage and polarity on each adjacent ferroelectric capacitor within a cell. One such circuit is disclosed, for example, in U.S. Pat. No. 4,873,664 issued to Eaton and is incorporated herein by reference.
One disadvantage of the above approach in Eaton is that each cell requires at least two access transistors and two ferroelectric capacitors to generate the required BIT and BIT complementary inputs into the sense amplifier for determining the logical state of the memory cell. This is because the ferroelectric capacitors must be polarized in opposite states to provide a voltage difference on the BIT and BIT inputs to the sense amplifier. The two different memory states are associated with the two different polarities of this voltage difference. Since the charge on each ferroelectric capacitor varies significantly with temperature, capacitor area and ferroelectric film properties, this means that the charge-dependent sense voltage for each ferroelectric capacitor also varies, so that a fixed reference voltage cannot be used with each cell. That is, if one attempted to use a fixed reference voltage for a single transistor-single ferroelectric capacitor cell, the voltage differential between the fixed reference voltage and a logical "1" and a logical "0" on the ferroelectric capacitor would not be sufficiently large under all conditions of operation, e.g. temperature variations, to be detected by the sense amplifier. Normally, this voltage differential must be about 100 millivolts.
Thus, the prior art approach of Eaton requires twice as many transistors and twice as many capacitors and twice as much chip area as compared to a single transistor-single capacitor cell design, and it is the elimination of these latter requirements to which the reference circuit of the present invention is directed.