The present invention relates to a pad part of a semiconductor device, and more particularly, to a pad part of a semiconductor device that has option capacitors for the fine adjustment of capacitance between pins.
In general, a pin in a semiconductor package indicates a lead, which is connected to a pad of a semiconductor chip, and functions to electrically connect the semiconductor chip to an external substrate.
A typical example of a semiconductor package generally known in the conventional art is shown in FIG. 1.
FIG. 1 is a cross-sectional view illustrating a conventional semiconductor package. Referring to FIG. 1, a semiconductor chip 10 is attached to a die paddle 12 by an adhesive (not shown), and inner leads 14a are electrically connected to the pads 11 of the semiconductor chip 10 by metal wires 13. The semiconductor chip 10, the die paddle 12, the metal wires 13, and the inner leads 14a are molded using a molding material (not shown), such as an epoxy molding compound (EMC). Outer leads 14b, which project out of the molding material, are connected to the electrode terminals of the substrate, such as a printed circuit board (PCB). The reference numeral 15 designates a lead frame.
In the semiconductor package, the leads 14a and 14b connected to the pads 11 of the semiconductor chip 10 have different capacitance values due to: first, a difference in the doping concentration between junction areas, and a difference in the thickness between gate electrodes, etc.; and, second, a difference in the lengths and widths of the metal wires 13 and the leads 14a and 14b connected to the respective pads 11.
The different capacitance between pins creates variances in signal transmission times, and this problem is regarded as significant impediment against the trend toward high speed operations of the highly integrated components of the semiconductor device.
Therefore, the development of new manufacturing methods has focused on methods of reducing the capacitance-difference between pins. In the conventional art, option transistors are formed adjacent to the pads or option capacitors are formed under the pads.
Separate transistors can be formed in electrostatic discharge (ESD) elements connected to pads to function as option transistors. The capacitance values between pins can be adjusted by varying the number of option transistors that are connected to the respective pads.
Regarding the option capacitors formed under the pads, a gate oxide layer pattern acting as a dielectric layer and a gate conductive layer pattern acting as an upper electrode are sequentially formed in the pad region of the semiconductor substrate when forming gates in a cell region. The option capacitors, each of which comprising a stack of substrate, gate oxide layer, and gate conductive layer, are formed. The capacitance values between pins is adjusted by connecting the requisite number of option capacitors to the respective pads in the same manner as described above.
The methods of forming the option transistors and forming the option capacitors may be used together. In general, the capacitance change rate by the option capacitors is relatively finer when compared to a capacitance change rate by the option transistors.
FIG. 2 shows a layout of a conventional semiconductor device in which option capacitors are formed under pads.
Referring to FIG. 2, conventional stack patterns 250 for option capacitors are formed under the pad 280 of a semiconductor device. Each stack pattern 250 has the sectional shape of a bar with the major axis extending in the direction of the “X-axis” as shown in FIG. 2. The stack patterns 250 are parallel to each other and spaced at regular intervals. The stack patterns 250 for option capacitors are connected to the pad 280 through first metal lines M1, second metal lines M2, and option metal lines O/M. The second metal lines M2, the option metal lines O/M and the pad 280 are formed on the same layer.
In FIGS. 2-3, reference numeral 200 designates a quadrangular semiconductor substrate; M1C designates first contacts that connect the stack patterns 250 for option capacitors and the first metal lines M1 to each other; M2C designates second contacts that connect the first metal lines M1 and the second metal lines M2 to each other; and 220 designates a pick-up that is shaped like a picture frame and surrounds the quadrangular pad part. The pick-up 220 is connected to a ground line (VSS) and functions to apply a bias to the pad part of the semiconductor device although this connection is not shown in FIG. 3.
FIG. 3 is a cross-sectional view taken along the line a-a′ of FIG. 2. The pad part of the semiconductor device having the conventional option capacitors includes the semiconductor substrate 200 with a pad forming region; an isolation structure 210 located in the pad forming region of the semiconductor substrate 200; the stack patterns 250 for option capacitors, each of which is shaped like a bar and comprises a stack of a gate insulation layer 230 and a gate conductive layer 240; a first interlayer dielectric 260 that covers the stack patterns 250 for option capacitors' the first contacts M1C, which are formed in the first interlayer dielectric 260, that contact the stack patterns 250 for option capacitors; the first metal lines M1 formed on the first interlayer dielectric 260 and connected to the first contacts M1C; a second interlayer dielectric 270 formed on the first interlayer dielectric 260 that covers the first metal lines M1; the second contacts M2C formed in the second interlayer dielectric 270 that contact the first metal lines M1; the second metal lines M2 formed on the second interlayer dielectric 270 that connect to the second contacts M2C; and the option metal lines O/M that connect the second metal lines M2 and the pad 280 to each other.
In the pad part of the semiconductor device constructed as described above, if a bias is applied to the gate conductive layer 240 and the pick-up 220, the semiconductor substrate 200, the isolation structure 210, the gate insulation layer 230, and the gate conductive layer 240 serve as a capacitor. At this time the capacitance value varies depending upon the number of stack patterns 250 for option capacitors that are connected to the pad 280 by the option metal lines O/M and the size of each stack pattern 250 for option capacitors.
In this regard, a finely tuned method for adjusting capacitance between pins is needed for a highly-integrated and high-speed semiconductor device due to the decrease in the desired pin capacitance and delta capacitance (ΔC).
However, in the conventional method for adjusting capacitance between pins, which uses the option capacitors as described above, since the capacitance adjustment rate by the option capacitors reaches several tens farads (F), it is difficult to finely adjust capacitance.