Priority is claimed on Japanese Patent Application No. 2006-282386, filed Oct. 17, 2006, the content of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a process for forming a resist pattern, and a resist coating and developing apparatus. In particular, the present invention relates to a process for forming a resist pattern for controlling dispersion in the linewidth dimension of a resist pattern, and a resist coating and developing apparatus.
2. Description of the Related Art
Heretofore, in a semiconductor device manufacturing process, a resist pattern is used as a mask when etching silicon oxide, silicon nitride film or polysilicon film, or as a mask during ion implantation of conductive impurities in a wafer formed from silicon or the like. The resist pattern is formed by coating the surface of the wafer with photoresist, exposing the coated photoresist to light of a predetermined pattern, and developing it (that is, a photolithography process).
In recent years, as the detail on semiconductor devices has become finer, the minimum linewidth required for resist patterns has become smaller. From such a background, lasers with short wavelengths, such as KrF, ArF, and the like, have become mainstream as exposure light sources in lithography processes. Furthermore, chemical amplification type photoresist is largely used in association with short wavelength exposure light sources.
This chemical amplification type photoresist is highly reactive to acid and alkali, so there is a possibility of it reacting to a very small quantity of ammonia or the like, for example, thus influencing its characteristics considerably. Therefore, from the point of maintaining its characteristics stably, it is preferable that exposing and developing processing of the chemical amplification type photoresist are performed in a short time in a clean room, in particular, in a clean atmosphere that has passed through a chemical filter or the like.
Therefore, specifically, in a photolithography process in which a chemical amplification type photoresist is used, a so-called in-line resist coating, exposing, and developing apparatus is used in which are incorporated a resist coater for photoresist coating, an exposure apparatus such as a scanner or the like, a baking apparatus for applying heat treatment to the photoresist, a developer for developing, and a carrier device for carrying wafers between the apparatuses.
The in-line resist coating, exposing, and developing apparatus is generally a single wafer processing type apparatus, which is also called a full in-line coating, exposing, and developing apparatus. By using the fill in-line coating, exposing, and developing apparatus, it is possible to form a resist pattern from a chemical amplification type photoresist, for example, within a defined short time. Furthermore, the abovementioned heat treatment process by the baking apparatus is provided for example between the exposure process and the development process. By heat treating after exposure, acid contained in the photoresist is diffused to form a latent image on the resist, and afterwards a resist pattern is formed by developing.
Incidentally, in a multi-product and multistage production line used for manufacturing semiconductor products that require multiple product types and multistage production, depending on the product to be produced and the process, different types of chemical amplification type photoresist are used. For example, there is a case in which semiconductor substrates on which a chemical amplification type photoresist of type “A” (referred to hereunder as “resist A”) is coated, and semiconductor substrates on which a chemical amplification type photoresist of type “B” (referred to hereunder as “resist B”) is coated, are mixed in the same manufacturing line, and the semiconductor substrates are heat treated one by one in succession by the same baking apparatus.
For example, if after semiconductor substrates (prior lot) on which a resist A is coated are heat treated in a baking apparatus, semiconductor substrates (subsequent lot) on which a resist B is coated are heat treated subsequently in the same baking apparatus, there is a problem in that the linewidth dimension of the resist pattern formed by the resist B becomes larger or smaller than a target dimension due to chemical influence received from the solvent component of the resist A.
FIG. 8 is a graph showing the abovementioned existing problem. FIG. 8 shows the variation of the linewidth dimension of the resist pattern in a subsequent lot after heat treatment of semiconductor substrates (prior lot) on which a resist A is coated, has been completed in a baking apparatus, and the semiconductor substrates (succeeding lot) on which a resist B is coated are subsequently heat treated in the same baking apparatus. The linewidth dimension of the resist pattern formed from the resist B is arranged to be normally within a range (referred to hereunder as “target dimension range”) of 80 to 100 [nm].
However, as shown by P in FIG. 8, from the start of the treatment of the succeeding lot after the treatment of the prior lot has been completed until around the sixth wafer (horizontal scale of 6), that is, the semiconductor substrates 1 to 6, there is a tendency for a linewidth dimension of the resist pattern to be out of the target dimension range. Regarding this dispersion in the linewidth dimension, normally there is a tendency for this to be most marked for the semiconductor substrate (horizontal scale of 1) that is treated first by the baking apparatus after the heat treatment of the prior lot is completed, and the dispersion is gradually reduced as the treatment of the succeeding lot progresses.
In this manner, if the linewidth dimension of the resist pattern is far out of the “target dimension range”, the etched shape of the film after being etched with this resist pattern as a mask, and the region of ion implanted impurities, vary. As a result, there is concern that the characteristics of the semiconductor device will vary.
Three apparatuses as described hereunder are offered as examples of a post bake apparatus for semiconductor manufacturing with a function of adjusting the exhaust volume.    (1) A hot plate type baking apparatus (for example, refer to Japanese Unexamined Patent Application, First Publication No. H01-225119), which is an apparatus for baking a mask plate on which a resist is coated, or a coating plate such as a wafer, on a hot plate, comprising; a mechanism for discharging inert gas evenly over the surface of the hot plate on which the coating plate is placed, and a gas flow adjustment mechanism for adjusting the gas flow.    (2) A substrate heat treatment apparatus (for example, refer to Japanese Unexamined Patent Application, First Publication No. H07-321023) having; a gas supply device which supplies gas for surface treatment to a heat treatment atmosphere formed around a substrate mounting plate, and an exhaust device for exhausting the gas in the heat treatment atmosphere, wherein there is provided a control device which controls a first opening and closing device provided in the exhaust device such that the gas in the heat treatment atmosphere is exhausted while the substrate is heat treated, and prevents the gas in the heat treatment atmosphere from being exhausted while the substrate is not heat treated.    (3) A semiconductor manufacturing apparatus (for example, refer to Japanese Unexamined Patent Application, First Publication No. 2000-49084), wherein a plate shaped hot plate is located in a heat treatment unit that takes on a closed structure in order to isolate it from the external environment, a straightening vane which controls the exhaust, is located above the semiconductor wafer at a predetermined spacing, and the straightening vane contains one or more holes and an adjuster mechanism for controlling the spacing from the semiconductor wafer.
Each of the documents in which the above-described apparatuses (1) to (3) are described discloses a method for exhausting gas in a heat treatment atmosphere to the outside of the apparatus by the provision of a characteristic method. However, there is no disclosure at all in these documents of a design for dealing with “dispersion between lots” in the linewidth dimension of a resist pattern as described previously. Furthermore, a problem of “dispersion between lots” occurring is not even recognized.