1. Field of the Invention
The present invention relates to a method of fabricating a strained silicon channel metal oxide semiconductor (MOS) transistor, and more particularly, to a method of fabricating a strained silicon channel MOS transistor by using a mask layer to avoid the defects resulting from etching the recesses and the selective epitaxial growth (SEG) process in the prior art.
2. Description of the Prior Art
The selective epitaxial growth (SEG) process is widely applied in manufacturing numerous kinds of semiconductor devices, such as complementary metal oxide semiconductor (CMOS) transistors having raised source/drain regions and strained silicon channel CMOS transistors. The SEG process is used to form an epitaxial layer on a single-crystalline substrate, in which the crystalline orientation of the epitaxial layer is almost identical to that of the substrate.
Please refer to FIG. 1 to FIG. 3. FIG. 1 to FIG. 3 shows the strained silicon channel CMOS transistors fabricating process by using the SEG process. As shown in FIG. 1, a semiconductor substrate 100 such as a silicon substrate is provided first and the semiconductor substrate 100 has a first active area 102, a second active area 104, and a shallow isolation trench (STI) 106 positioned between the first active area 102 and the second active area 104, and then a first gate structure 112 and a second gate structure 114 are formed on the semiconductor substrate 100. A cap layer 116 is formed on the first gate structure 112, the second gate structure 114, and the semiconductor substrate 100, and a photoresist layer 117 is formed on the cap layer 116 above the second active area 104 and a portion of the STI 106, wherein the thickness of the cap layer 116 is about 500 to 600 angstroms. The first gate structure 112 includes a first gate oxide layer 118, a first gate 120 positioned on the first gate oxide layer 118, a silicon nitride layer 122 positioned on the first gate 120, and a first spacer 124, and the second gate structure 114 includes a second gate oxide layer 128, a second gate 130 positioned on the second gate oxide layer 128, a silicon nitride layer 132 positioned on the second gate 130, and a second spacer 134. In general, the first gate oxide layer 118 and the second gate oxide layer 128 are composed of silicon dioxide (SiO2), and the first gate 120 and the second gate 130 are composed of doped polysilicon. The silicon nitride layer 122 and 132 are used to protect the first gate 120 and the second gate 130 respectively.
As shown in FIG. 2, the first gate structure 112 and the photoresist layer 117 are used as an etching mask to perform an etching process in order to form two recesses 140 within the first active area 102 uncovered by the first gate structure 112, and then the photoresist layer 117 is removed.
Next, as shown in FIG. 3, after a pre-cleaning step is carried out for the first active area 102 of the semiconductor substrate 100, a SEG process is carried out to form an epitaxial layer 142 composed of SiGe in the recesses 140 respectively as SiGe source/drain. A photoresist layer is formed on the second active area 104.
Please note that when performing the etching process and the pre-cleaning step for the recesses 140, the etching gas and cleaning liquid such as diluted HF (DHF), will etch the corners of silicon nitride layer 122 and a portion of the first gate 120 is exposed, as shown in FIG. 2. The SEG process, which is carried out later, will form SiGe bumps 144 on the exposed portion of the first gate 120. Please refer to FIG. 3 and FIG. 4, wherein FIG. 3 is a schematic, cross-sectional diagram, and FIG. 4 is a photograph in reality. This defect will result in spacer leakage current or short problems, and the follow-up processes will be much more difficult. For example, when fabricating the contact plugs of the source/drain regions, the SiGe bumps might contact the contact plugs and become short, i.e. the contact plug process is affected by the SiGe bumps, and the yield is also affected badly.