1. Field of the Invention
The present invention relates to a digital PLL (phase locked loop) circuit.
2. Description of the Related Art
A conventional digital PLL circuit is supplied with a burst data signal. In this case, a phase locking time becomes long, when the data signal has a large phase change due to frequency deviation, duty change and jitter. As a result, an identification error is caused in case of the re-timing of the receive data signal based on a clock signal extracted from the data signal.
Such a problem is solved in a digital PLL circuit disclosed in U.S. patent application Ser. No. 09/083,704 corresponding to Japanese Laid Open Patent application (JP-A-Heisei 10-327068). The disclosure is incorporated herein by reference.
The digital PLL circuit in U.S. patent application Ser. No. 09/083,704 is shown in FIG. 1. A burst data signal has a different jitter quantity and a different duty change quantity for every burst data signal, as shown in FIG. 1. Therefore, a duty determining circuit 908 takes such a burst data signal at periodic change portions to measure the duty. An identified data selecting circuit 909 determines a data selection phase based on a duty data outputted from the duty determining circuit 908 and an average rising edge phase data outputted from an average rising edge phase calculating circuit 907. In this way, a clock signal can be extracted in several bits from the head of the data signal. Also, the data signal can be identified without any error due to jitter. Thus, the data signal subjected to the identification re-timing with no error is outputted.
However, in this reference shown in FIG. 1, the burst data signal is processed in order by a single circuit. Therefore, the signal processing waiting state is caused, when a processing time of a phase synchronizing operation and data identifying operation to the burst data signal becomes long.
In conjunction with the above description, a digital PLL circuit is disclosed in U.S. Pat. No. 5,687,203 which corresponding to Japanese Patent No. 2,773,669 corresponding to Japanese Laid Open Patent Application (JP-A-Heisei 8-237117). In this reference, the digital PLL circuit is composed of a clock extracting circuit for extracting one from N phase clock signals in response to an extraction signal. The N phase (N is equal to or more than 2 integers) clock signals have the same frequency as the burst data signal and phases shifted by 360 degrees/N in order. A sampling circuit samples the burst data signal with the N phase clock signals to produce N sampled data signals. An rearranging circuit sets the extracted clock signal as a first phase clock signal, and sets the remaining clock signals as second to N-th clock signals in order. Then, the rearranging circuit rearranges the sampling data signals in correspondence to the first to N-th phase clock signals as first to n-th sampling data signals. A latch circuit latches said first to N-th phase sampling data signals in response to the first phase clock signal. An edge detecting circuit detects the position of a falling edge based on the levels of adjacent two of the first to N-th phase sampling data signals to generate a data indicative of the detected falling edge position for every period of the said clock signal. Also, the edge detecting circuit detects the number of falling edges and the number of rising edges for every period of the said clock signal. An average calculating circuit calculates an average of the falling edge position data from the past to the current for every period, to output as the extraction signal. A data selecting circuit selects one of the rearranged first to N-th phase sampling data signals based on the detected number of falling edges and the detected number of rising edges. Finally, a re-timing circuit carries out a re-timing operation to the selected sampling data signal in response to the first phase clock signal.
Also, a clock signal supply circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-116425). In this reference, the ON/OFF state of the first and second switch sections are switched oppositely such that an output signal of one of the phase-locked oscillation circuits is given to the other phase-locked oscillation circuit as an input signal, when a fault detection circuit of a currently used phase-locked oscillation circuit detects any trouble, and when the fault detection circuits of both of phase-locked oscillation circuits detects any trouble. Alternatively, when it is detected from the output signals of fault detection circuits of the first and second reference oscillators that one of the reference oscillators had a malfunction, or when the phase-locked oscillation circuit had a malfunction which inputs one of the output signals of these reference oscillators in common through a switch section, a normal reference oscillator or the reference oscillator which is not selected at present is selected.
Also, a clock signal selecting circuit is disclosed in Japanese Laid Open-Patent Application (JP-A-Heisei 9-139733). In this reference, the clock signal selecting circuit selects one of from M series of clock pulse sequences having different phases which synchronizes with a received burst signal in phase, based on the detection timing of the change point of the rising edge or falling edge of the received burst signal. For this purpose, M signal holding sections (1114) hold signals showing the detection timings of the change points of the rising edge or falling edge of the received burst signal. M AND gates (15 to 18) inputs positively transferred signals from the respective signal holding sections (11 to 14) at an input terminal and inputs inverted output signals from the signal holding section (11 to 14) of the next phase (here, the next phase to the M phase is a single phase). Output signals from the AND gates (15 to 18) are outputted to the next stage as phase selection signals.
Also, a digital PLL circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-327068). In this reference, a duty determining circuit 8 takes in a continuously changing data signal at a periodic change point of the data signal and determines a duty. An identified data selecting circuit 9 determines a data selection phase based on average rising edge phase data (108) and a duty data (109).
Also, a frame phase synchronizing circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 4-156022). In this reference, a receiving circuit reproduces a data signal and a clock signal from a received signal and detects a fault such as a synchronization-out of the received data signal. A write address control circuit generates a write address signal of a dual port memory based on a reference clock signal. A read address control circuit generates a read address signal of the dual port memory based on the reference clock signal. A data writing and reading operation is optional in the dual port memory. A frame synchronizing circuit identifies a received frame number from the received data signal. The frame phase synchronizing circuit includes two circuits, each of which has the receiving circuit, the write address control circuit, the read address control circuit, the dual port memory and the frame synchronizing circuit. A phase comparing circuit compares the frame numbers from the two circuits to generate the reference clock signal. A data selecting circuit selects one of the data outputted from the dual port memories based on a data selection signal. A warning control circuit receives synchronization-out signals from the receiving circuits to output the data selection signal. When the synchronization-out is detected by the receiving circuit, the warning control circuit outputs the data selection signal to select a normal one of the data signals. The phase difference between the write address signal and the read address signal is set to be three or more frames of the received data signal.