1. Field of the Invention
The present invention relates generally to an optical disk reproducer for reproducing video and audio information, for example, recorded on an optical disk, and more particularly, to an optical disk device for carrying out reproduction control on the basis of navigation data recorded in the optical disk.
2. Description of the Prior Art
Optical disk reproducers using an optical disk as a recording medium for reproducing digitized information such as audio, video, image, and character information which are recorded on the optical disk has been conventionally put to practical use. One of them is a DAD (Digital Versatile Disc) video player.
In the DAD, navigation data which are reproduction control data for designating the order of reproduction and branching of presentation data stored in a divisional manner in the DAD are recorded in addition to presentation data such as video data, audio data, and data related to a sub-picture (e.g., subtitles) which are main objects of reproducing a movie or the like.
One of the navigation data in the DAD is a data unit referred to as NV_PCK (a navigation pack). The NV_PCK, together with V_PCK (a video pack) on which video data which is presentation data is recorded, A_PACK (an audio pack) on which audio data which is presentation data is recorded, SP_PACK (a sub-picture pack) on which sub-picture data which is presentation data is recorded, constitutes a data unit referred to as a VOBU (Video Object Unit).
On NV_PCK, attributes for controlling the reproduction of a VOBU having the NV_PCK recorded thereon and data used for search and seamless reproduction (such reproduction that video is not intermittent) are recorded. At the time of special reproduction such as fast forward reproduction and backward reproduction of video, for example, reproduction control (seek, buffering, or decoding) is carried out while obtaining an address representing a VOBU to be subsequently reproduced while referring to the NV_PCK (see JP-A-10-322661, for example).
Meanwhile, the data read out of the optical disk such as the DVD is buffered in a memory (stored in a memory) after being subjected to demodulation corresponding to 8/16 modulation. By a DVD decoder, the data is subjected to error correction processing in units of ECC (Error Correcting Code) blocks and is then subjected to error detection processing by an EDC (Error Detection Code). After the error detection processing is performed, NV_PCK reference processing is performed.
In the DVD, the ECC block is composed of 16 sectors, one of the packs, i.e., NV_PCK, V_PCK, and A_PCK corresponds to one sector. Accordingly, a maximum of 16 packs NV_PCK may be included in one ECC block. The head of each of the sectors (16 sectors) in the ECC block is provided with a system header indicating what data is the sector.
The NV_PCK reference processing is performed by first reading the system header attached to the head of each of the sectors (16 sectors) in the ECC block to refer to and detect the NV_PCK, accessing the memory storing the ECC block decoded (which has been subjected to ECC and EDC processing) on the basis of the results of the detection to read out necessary navigation data (data representing the NV_PCK).
As described above, the ECC processing (error correction processing), the EDC processing (error detection processing), and the NV_PCK reference processing in the decoding processing are performed in units of ECC blocks by the DVD decoder. In order to increase the speed and the efficiency of the decoding processing, the buffering, the ECC processing, the EDC processing, and the NV_PCK reference processing of the data read out of the optical disk are performed using pipeline processing having the ECC block as a unit, so that the decoding processing in VOBU units is performed. FIG. 2 shows how the decoding processing is performed.
For example, the m-th ECC block is read out, and is buffered in the memory through demodulation corresponding to 8/16 modulation. When the buffering is terminated, ECC and EDC processing of the m-th ECC block is performed and at the same time, buffering of the (m+1)-th ECC block is started.
When the ECC and EDC processing of the m-th ECC block is terminated, reference processing of NV_PCK in the m-th ECC block is performed, and the results of the processing are outputted at the timing when ECC and EDC processing of the subsequent ECC block is terminated (or NV_PCK reference processing is started). That is, in order to continue to continuously perform such pipeline processing, the NV_PCK reference processing must be completed before the ECC and EDC processing of the subsequent ECC block is terminated (before the NV_PCK reference processing is started). Consequently, a time period allowed for the NV_PCK reference processing is determined by a time period required for the buffering (time periods A and B are approximately equal in FIG. 2).
In a case where a lot of (a maximum of 16) packs NV_PCK are included in one ECC block and a case where the processing speed of a control circuit for performing NV_PCK reference processing is low, however, the NV_PCK reference processing may not be completed before ECC and EDC processing corresponding to the subsequent ECC block is terminated.
For example, when reference processing of NV_PCK in the (m+1)-th ECC block shown in FIG. 2 is not completed before ECC and EDC processing of the (m+2)-th ECC block is terminated, as indicated by a broken line, the reference processing of NV_PCK in the (m+1)-th ECC block is not completed before the timing when the results of the NV_PCK reference processing are outputted, and reference processing of NV_PCK in the (m+2)-th ECC block cannot be also performed.
The reference processing of NV_PCK in the (m+1)-th ECC block is delayed, so that processing in VOBU units cannot be performed, thereby fracturing reproduction control in VOBU units. Accordingly, reproduction such as fast forward reproduction may be delayed. If used as a control circuit (a microcomputer) for performing NV_PCK reference processing is one having a sufficiently high processing speed, the above-mentioned problem can be avoided. However, the control circuit having a high processing speed is higher in cost than a control circuit having a low processing speed, thereby increasing the cost of the device.