1. Field of the Invention
The present invention relates to a semiconductor memory device such as an electrically programmable read only memory (EPROM), more particularly, to an improvement of a sense amplifier in such a semiconductor memory device.
2. Description of the Related Art
In general, in an EPROM or other semiconductor memory device, in the program mode, predetermined data is programmed from a data programming circuit to a selected memory cell by storing, or not storing, electric charges at the floating gate of the cell transistor constituting the selected memory cell. On the other hand, in the read mode, the data programmed in the cell transistor is read out by sensing whether or not such electric charges are stored in the floating gate of the cell transistor constituting the selected memory cell.
When programming data "0" in a selected cell transistor of the memory cell array, electrons are accumulated in the floating gate of the selected cell transistor. When reading the data, the cell transistor does not become conductive even if the selection signal is applied to the control gate. The nonconductive state of the cell transistor is detected by the sense amplifier, whereby the programmed data "0" is read out through the sense amplifier.
On the other hand, when programming data "1" in a selected cell transistor of the memory cell array, electrons are not accumulated in the floating gate of the selected cell transistor. Therefore, in the read mode, when the selection signal is applied to the control gate, the cell transistor becomes conductive. The conductive state of the cell transistor is detected by the sense amplifier, whereby the programmed data "1" is read out through the sense amplifier.
In general, however, in this type of semiconductor memory device, in the read mode, changes in the selected address are accompanied by charging up of the stray capacitance on the bit lines (when the read data changes from "1" to "0") or discharging of the same (when the read data changes from "0" to "1"). To increase the readout speed of the correct data after such address changes, it is necessary to speed up the chargeup or discharging of the stray capacitance. To increase the speed of the chargeup of the stray capacitance, the chargeup transistors must be made larger in size. On the other hand, to increase the speed of the discharging of the stray capacitance (discharging through a selected cell transistor), that cell transistor must be made larger in size.
However, it is not possible to increase the size of the cell transistors that much, as they are provided in large numbers in usual memory cell arrays. Consequently, the speed of discharge of the stray capacitance to the selected cell transistor falls. On the other hand, since the chargeup transistors, which become the load transistors for that cell transistor, are made a size commensurate with the size of that cell transistor, it is not possible to make the chargeup transistors that large either. As a result, the speed of chargeup of the stray capacitance also falls. In consequence, in the sense amplifiers of the prior art, the speed of reading correct data after address changes has been slow.