A system on a chip or system-on-chip (SoC) is an integrated circuit (IC) that comprises several functional units on a single chip. A system on chip may, for instance, be used as an embedded system in, e.g., a motor vehicle, mobile phone, or manufacturing plant. An SoC may notably comprise one or more requestor units in the form of, e.g., one or more microprocessors, direct memory access (DMA) controllers or other bus masters capable of requesting a transaction. The SoC may further comprise a number of subordinate units, e.g., memory blocks or peripheral units (peripherals) arranged to respond to the transaction request; further named responder units. Each requestor unit may be programmable or non-programmable. A programmable requestor unit may comprise or be connected to a program memory and arranged to read program code in the form of executable instructions from the program memory and to execute these instructions. For instance, the SoC may comprise a memory, e.g., a flash memory, the non-volatile memory carrying the program code.
Today's SoCs often comprise a program memory sufficiently large to allow a user or developer to add additional software to the SoC in order to provide additional functions. Such additional functions or add-ons, sometimes referred to as guest programs, may also make use of memory or the peripherals within the SoC. For instance, a manufacturer of a SoC may manufacture a basic SoC that provides a certain number of functions and still has sufficient capacity for allowing a customer to add customer-specific functions to the SoC. In this case, it may be important to shield the original system, i.e., the basic SoC, against such additions to ensure the integrity and stability of the original system.
As computing power has increased, the operating systems supporting the software applications of the SoC have increased in sophistication and complexity such that so-called virtualization can now be employed in the field of embedded computing systems, which find many applications, for example in the automotive industry. In this context, “virtualization” refers to the various techniques, methods or approaches of creating a virtual (rather than actual) version of something, such as a virtual hardware platform. In the field of SoCs, so-called hardware-assisted virtualization techniques are employed, which involves specially designed hardware components for this purpose. These components may assist in reducing the need to modify guest programs. As an example, a memory management unit (MMU) or memory protection unit (MPU) can be used to respond to any access to a shared resource, for example a set of memory regions, or one or multiple hardware blocks, with a software interrupt or exception that can then be used to implement the functionality of a hypervisor, the software used to create virtual machines on host hardware. This implementation is costly, for example there is an IPS (Instructions Per Second) penalty, but it may assist in enabling the running of existing guest programs more or less unmodified on a virtualized hardware platform.
Such a scheme also enables the partition of guest programs in virtual systems, where the software executing within one partition is not permitted to influence the software executing in another partition, and vice-versa. This is especially beneficial for systems targeted towards executing multiple applications where at least one is in a functional safety domain. For such systems, freedom of interference between the various applications running is a key requirement. However, as intimated above, freedom from interference is an issue when accessing hardware blocks, due to the very fine granularity of the partitioning required, which is often at least at the level of individual registers within such a hardware block. The hardware components mentioned above only support the definition of a very limited amount of address ranges as the basis for a corresponding partitioning, where the resulting granularity is often also too coarse to allow a single register to be protected.
Furthermore, the cost of implementing an address range based protection scheme for the hardware-assisted virtualization of one or multiple hardware blocks is prohibitively high. For example, hardware blocks can contain a large amount of registers, often in the range of 100's to 1000's of registers, of varying sizes, usually 8-bit, 16-bit, or 32-bit wide, and sometimes even wider registers are provided. Furthermore, the set of registers related to a certain feature within a single hardware block is often distributed over the memory range occupied by this hardware block. Such a distribution does not always have a consistently discernible mapping to address ranges. With an address range based protection scheme, this could result in the need to use multiple address ranges to protect a single feature. Protecting the multiple features implemented by such a hardware block, could therefore result in the need for a large amount of address ranges for protection purposes. However, the cost of the hardware-assisted protection of a single address range is very high, and so the amount of available address ranges is significantly limited. In this regard, the hardware-assisted protection provided has to accommodate protection information, requiring for example about 50 to 100 flip-flops to store an address range, protection attributes and any other required information. Also, for every access request concurrent checks of all specified protection address ranges are required, resulting in a need to implement a large set of comparators, and this influences hardware design considerations, for example critical timing path considerations within the system.
Additionally, any technique to protect hardware blocks needs to be compatible with existing, address based memory protection capabilities, because it is necessary to avoid re-designing an architecture of an SoC, especially when only a small amount of hardware blocks need to be protected, or when such protection has to be implemented together with other known address based protection capabilities.