1. Field of the Invention
The present invention relates to a method for fabricating bipolar semiconductor integrated circuit device which is adopted for high integration and high density, and is capable of operating at high speed.
2. Description of the Related Art
In order to increase the operational speed of a bipolar semiconductor integrated circuit device, it is necessary to decrease the base resistance and the parasitic, especially base-collector junction capacitance of the transistor element formed therein. The base resistance can be reduced by forming a small sized emitter region to decrease an active base resistance and by placing an inactive base region as close as possible to an emitter region. Also, in order to decrease the base-collector junction capacitance, it is desired to reduce the areas of active and inactive base regions, thus reducing the junction area between the base and collector regions.
To achieve this requirements, some bipolar IC manufacturing methods which employ various self-alignment techniques allowing a high accuracy photoengraving processing have been proposed. For example, one of the prior art methods is disclosed in a paper entitled "High Speed Bipolar ICs Using Super Self-Aligned Process Technology" authorized by Tetsushi Sakai, et al., in the "Japanese Journal of Applied Physics, Volume 20 (1981) Supplement 20-1, pp. 155-159.
The prior art bipolar semiconductor IC device manufacturing process is described herewith with reference to FIGS. 1(a) to 1(h).
In FIG. 1(a), a P-type silicon substrate is prepared which has an N-type buried diffusion layer 2, an N-type epitaxial layer 3 acting a collector region, a P-type element isolation region 4 and an N-type collector contact region 5. Then, multilayers of thermal oxide (SiO.sub.2) film 6, CVD Si.sub.3 N.sub.4 film 7, CVDSiO2 film 8, boron-doped polysilicon and CVD Si.sub.3 N.sub.4 film 10 are in turn formed on the surface of the silicon substrate. Then, the CVD nitride film 10 is partially removed by a photoengraving process to expose the surface of the polysilicon layer 10.
Next, as shown in FIG. 1(b), unnecessary parts of the polysilicon layer 9 are converted into SiO.sub.2 film 11 by a thermal oxidation process. Then, Si.sub.3 N.sub.4 film 10 is partially preserved at the areas corresponding to the base contact window and resistor window.
Next, as shown in FIG. 1(c), the windows for the emitter and the collector are opened by using a photoengraving process. Then a CVD oxide film 8 is side etched.
In FIG. 1(d), an aluminum layer 12 is formed on the entire surface of the structure but under the overhung portion of the polysilicon layer 9 by vacuum evaporation process.
Next, as shown in FIG. 1(e), the nitride film 7 under the overhung portion is completely removed by using the aluminum layer 12 as an etching mask and then boron ions are implanted into the exposed surface of the layer 3 to form an active base region 13 after the removal of the remaining aluminum layer. After the remaining oxide layer 6 is removed to expose the surface of the layer 3, an boron-doped polysilicon layer 9a is deposited over the entire surface of the structure.
In FIG. 1(f), the polysilicon layer 9a is selectively removed by ion milling so as to leave the polysilicon layer 9a under the overhung portion of the polysilicon layer 9.
Next, as shown in FIG. 1(g), the structure is subjected to an oxidation process to form a relatively thick oxide film 14 on the surface of polysilicon layer 9a, while an inactive base region 15 is formed by boron diffusion from the polysilicon 9b. In this step, the nitride films 9 and 10 prevent the oxidation of the polysilicon film 9 thereunder.
Next, as shown in FIG. 1(h), the remaining nitride films 7 and 10 and the thin oxide film 6 are etched off to form the windows for electrodes. Then, both boron-doped polysilicon emitter and collector electrodes 16a and 16b are formed in the windows. An emitter region 17 is formed by impurity diffusion from the polysilicon electrode 16a. Finally, metal electrodes 18 are formed on the surfaces of the polysilicon films 9.
However, the prior art bipolar IC manufacturing process is very complicated. In addition, since it is difficult to reduce the emitter area, there is a limit to further decrease the active base resistance content. The polysilicon base electrode according to the prior art makes it difficult to obtain a further lowered base resistance. Furthermore, it is difficult to further reduce the inactive area, and a side-etching process is employed on the nitride film.