1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to a 3D (three-dimensional) semiconductor apparatus using through vias.
2. Related Art
In order to improve the degree of integration of a semiconductor apparatus a 3D (three-dimensional) semiconductor apparatus has been developed. The 3D semiconductor apparatus typically includes a plurality of chips that are stacked and packaged to increase the degree of integration. In the 3D semiconductor apparatus, since two or more chips are vertically stacked, a maximum degree of integration may be achieved in a same area.
Various methods may be applied to realize the 3D semiconductor apparatus. In one of the methods, a plurality of chips having a same structure are stacked and then the plurality of chips are connected with one another using wires such as metal lines so that the plurality of chips operate as one semiconductor apparatus.
Recently, a TSV (through-silicon via) type semiconductor apparatus has been disclosed in the art, in which through-silicon vias are formed to pass through a plurality of stacked chips so that all the chips are electrically connected with one another. In the TSV type semiconductor apparatus, because the through-silicon vias vertically pass through respective chips to electrically connect the respective chips with one another, the area of a package may be efficiently reduced when compared to a semiconductor apparatus in which respective chips are connected with one another through peripheral wiring.
TSVs are formed by filling a conductive material in via holes which are defined through a dielectric substance. Since the semiconductor apparatus may operate normally only when the TSVs are properly formed, a scan test is performed in a manufacturing process to determine whether or not TSVs properly connect the plurality of chips.
FIG. 1 is a view schematically showing a conventional scan test method of a semiconductor apparatus. In FIG. 1, a semiconductor apparatus includes first to third chips CHIP1, CHIP2 and CHIP3. The first to third chips CHIP1, CHIP2 and CHIP3 are electrically connected with one another through first to eighth TSVs TSV1 to TSV8. The first and second chips CHIP1 and CHIP2 are connected with each other through the first to fourth TSVs TSV1 to TSV4, and the second and third chips CHIP2 and CHIP3 are connected with each other through fifth to eighth TSVs TSV5 to TSV8. The test of the TSVs is performed as follows. First, test data TDATA is applied to the first TSV TSV1. The test data TDATA may be a predetermined voltage or current. The test data TDATA applied to the first TSV TSV1 is transmitted sequentially through the first to eighth TSVs TSV1 to TSV8 as shown in FIG. 1, and finally, a test output signal TOUT may be outputted through the fourth TSV TSV4. Therefore, by measuring the current or voltage of the output signal which is outputted through the fourth TSV TSV4, it is possible determined whether or not the TSVs included in the semiconductor apparatus are appropriately connected with one another.