1. Field of the Invention
The present invention relates to an offset chip-stacked package structure, and more particularly, to an offset chip-stacked package structure with leadframe having multi-pieces bus bar.
2. Description of the Prior Art
In semiconductor post-processing, many efforts have been made for increasing scale of the integrated circuits such as memories while minimizing the occupied area. Accordingly, the development of three-dimensional (3D) packaging technology is in progress and the idea of making up a chip-stacked structure has been disclosed.
The prior art taught that a chip-stacked structure can be formed by firstly stacking a plurality of chips and then electrically connecting the chips to the substrate in a wire bonding process. FIG. 1A and FIG. 1B are cross-sectional views of a prior chip-stacked package structure for chips of same or similar sizes. As shown in FIG. 1A, the prior chip-stacked package structure 100 comprises a package substrate 110, chip 120a, chip 120b, a spacer 130, a plurality of wires 140, and an encapsulant 150. The package substrate 110 is provided with a plurality of pads 112. The chips 120a and 120b are respectively provided with peripherally arranged pads 122a and 122b. The chip 120a is provided on the package substrate 110 while the chip 120b is provided on the chip 120a with a spacer 130 intervened there-between. The chip 120a is electrically connected to the package substrate 110 by bonding two ends of one of the wires 140 to the pads 112 and 122a respectively. The chip 120b is electrically connected to the package substrate 110 in similar manner. The encapsulant 150 is then provided on the package substrate 110 to cover the chips 120a and 120b and the wires 140.
Since the pads 122a and 122b are respectively provided at the peripheral of the chip 120a and the chip 120b, there is a need to apply the spacer 130 to prevent the chip 120b from directly contacting with the chip 120a for performing the subsequent wire-bonding process. However, the spacer 130 is used for increasing the thickness of the prior chip-stacked package structure 100.
Another prior chip-stacked package structure with different-sized chips has been disclosed. Referring to FIG. 1B, another conventional chip-stacked package structure 10 includes a package substrate 110, chips 120c and 120d, the plurality of wires 140, and an encapsulant 150. The package substrate 110 has pads 112 thereon. The size of chip 120c is larger than the chip's 120d. The chips 120c and 120d are respectively provided with peripherally arranged pads 122c and 122d. The chip 120c is provided on the package substrate 110 while the chip 120d is provided on the chip 120c. The chip 120c is electrically connected to the package substrate 110 by bonding two ends of one of the wires 140 to the pads 112 and 122c respectively. The chip 120d is electrically connected to the package substrate 110 in similar manner. The encapsulant 150 is then provided on the package substrate 110 to cover the chips 120c and 120d and the wires 140.
Since the size of chip 120d is smaller than chip's 120c, the pads 122c of chip 120c would not covered by the chip 120d when the chip 120d is stacked on the chip 120c. However, the condition that the size of the upper chip must be smaller than the lower chip that limits number of the chips to be stacked in the chip-stacked package structure 10.
In other words, the above-mentioned chip-stacked package structures have drawbacks of either increasing thickness of chip-stacked package structure 100 as shown in FIG. 1A or limiting number of the chips to be stacked as shown in FIG. 1B in which the size of the upper chip needs to be smaller than the lower chip. Moreover, there are also other problems that may lower reliability and yield of the chip-stacked package structures during processing when wire-jumping or wire-crossing bonding of the chips is considered. For example, a high-pressured mold-flow injection during molding may cause the jumping or crossing wires to shift and become short.