(a) Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device and a method of manufacturing the same, wherein an exposure of a copper line in a scribe lane region can be prevented in a case of forming a plurality of chips in a single wafer.
(b) Description of the Related Art
As semiconductor devices become more highly integrated, a size of a semiconductor chip is reduced. After simultaneously forming a plurality of semiconductor chips on a single wafer, a packaging process is performed to saw each die or chip from the single wafer. To prevent damage to dies or chips during the packaging process, the chips or dies must be separated by a predetermined gap referred to as a scribe lane.
A scribe lane includes align keys for a lithographic process, overlay keys, and monitoring patterns for various processes. A scribe lane also includes electrical test patterns for process monitoring and feedback which are performed after a process. Therefore, a scribe lane includes a plurality of pads for electrical probing of electrical test patterns, and it also includes a plurality of inter-connection lines for connecting between pads or between a pad and a test pattern.
FIG. 1A to FIG. 1E are cross-sectional views showing a conventional method of manufacturing a semiconductor device.
As shown in FIG. 1A, a wafer 100 includes a scribe lane region where a scribe lane is formed and a chip region where a semiconductor chip is formed. A pad 110 and an inter-connection line 111, both of which include a metal, are formed in the scribe lane region of the wafer 100, and a pad 112 including a metal is formed in the chip region. The pad 110, inter-connection line 111, and pad 112 are formed by a metal line process using copper (Cu).
As shown in FIG. 1B, a first insulation layer 120 is deposited on pad 110, inter-connection line 111, and pad 112, and then etched using a mask to expose the pad 110 in the scribe lane region and the pad 112 in the chip region.
Referring to FIG. 1C, a metal pad comprising aluminum (Al) is formed on the pads 110 and 112. A second insulation layer 140 and a third insulation layer 150 are sequentially deposited on first insulation layer 120 and metal pad 130. Second insulation layer 140 and third insulation layer 150 are used as a passivation layer.
As shown in FIG. 1D, a photosensitive layer pattern 160 for exposing metal pad 130 is formed by using a mask. When passivation layers, such as second insulation layer 140 and third insulation layer 150, remain during the sawing process, the sawing process may severely damage the chip region through the passivation layers. Thus, the passivation layers in the scribe region, such as second insulation layer 140 and third insulation layer 150, are generally removed when metal pad 130 is exposed through an etching process. Accordingly, the photosensitive layer pattern 160 is patterned as shown in FIG. 1D to expose second and third insulation layers 140 and 150 on metal pad 130 in the scribe region.
As shown in FIG. 1E, using photosensitive layer pattern 160 as a mask, first insulation layer 120, second insulation layer 140, and third insulation layer 150 are etched so as to expose metal pad 130. In addition, region ‘A’ as shown in FIG. 1E, inter-connection line 111 is also exposed.
If inter-connection line 111 is exposed at room temperature for a long time, copper (Cu) in inter-connection line 111 may be rapidly corroded because through reaction with oxygen in the air, as a result of which inter-connection line 111 may fail or particles may be created in peripheral circuits and chips. Consequently, the yield and reliability of a semiconductor device may be deteriorated.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.