1. Field of the Invention
The present invention relates to a semiconductor storage device comprising a memory cell, a bit line connected to the memory cell, a precharge circuit which steps up a voltage of the bit line up to a power supply voltage, and a step-down circuit which steps down the voltage of the bit line to a voltage level lower than the power supply voltage before data is read from the memory cell.
2. Description of the Related Art
In the field of a semiconductor storage device, there is a conventional technology for improving a data reading speed by stepping down a bitline precharged with a power supply voltage to a voltage level lower than the power supply voltage before data is read so that the power supply voltage level in the bit line can change to a ground level sooner. The change from the power supply voltage level to the ground level in the bit line is detected by a PMO transistor at a subsequent gate. However, when a step-down level in the bit line is below an operation region of a transistor for detection, through current and a data-read error may occur. A similar data-read error also occur in the case where a sense amplifier or a PMOS cross driver is connected to the bit line. Therefore, it is necessary to keep a step-down level of the bit line around a threshold voltage of the PMOS transistor.
In a SRAM circuit where the bit line is precharged with the power supply voltage, charges of the power supply voltage level of the bit line flow into a node at which “L” data of SRAM is retained as soon as a word line is activated, in a non-selected column in which reading or writing is being performed. The inflow of too many charges at the time results in the generation of a data-write error. An indicator called a static noise margin shows a level of resistance against the data-write error. The static noise margin has been reduced in recent years as the semiconductor is increasingly miniaturized, and the data-write error is more likely to occur. In order to respond to the recent trend, there is a technology wherein a potential of the power supply voltage level of the bit line is stepped down so as to reduce the current flow into the node of the memory cell at which “L” data is stored when the word line is activated. When the voltage step-down level in the bit line at that time is not enough, the data-write error occurs due to the reason described above. When the voltage step-down level in the bit line is excessive, an data-write error is caused by charges of “L” level of the bit line which flow into the node at which “H” data of the SRAM is retained. Therefore, it is necessary to step down the voltage of the bit line to such a voltage level that can assure the static noise margin.
Below is described a technology for stepping down the voltage of the bit line in a conventional semiconductor storage device referring to FIGS. 7A and 7B. FIG. 7A is a circuit diagram illustrating a constitution of a conventional semiconductor storage device, and FIG. 7B is a timing chart illustrating an operation of the semiconductor storage device. In FIG. 7A, 11 denotes a SRAM memory cell, 12 denotes a precharge circuit, 13 denotes an equalizing circuit, 14 denotes a reading circuit, 15 denotes a step-down circuit, BL and /BL are complementary bit lines, WL denotes a word line, PC denotes a precharge control signal, DEC denotes a step-down/equalizing control signal, QP31, QP32 and QP 33 denote PMOS transistors constituting the precharge circuit 12, QP34 denotes a PMOS transistor constituting the equalizing circuit 13, QN31 and QN32 denote NMOS transistors constituting the step-down circuit 15, and Inv0 denotes an inverter.
The step-down circuit 15 comprising the step-down transistors QN31 and QN32 is additionally provided in order to step-down voltages of the bit lines BL and /BL prior to the activation of the word line WL. Sources of the step-down transistors QN 31 and QN32 are connected to the ground, drains thereof are directly connected to the bit lines BL and /BL, and gates thereof are connected to a gate of the equalizing transistor QP34 via the inverter Inv0. The gates of the step-down transistors QN 31 and QN32 are driven by the step-down/equalizing control signal DEC.
As shown in FIG. 7B, prior to the activation of the word line WL, the precharge control signal PC is negated and turns to “H” level at a timing t31, the precharge transistors QP31 and QP32 and the equalizing transistor QP33 are turned off, which leaves the bit lines BL and /BL in a floating state.
At a timing t32, the step-down/equalizing control signal DEC is asserted and turns to “H” level, and the step-down transistors QN31 and QN32 in the step-down circuit 15 are turned on. Further, the equalizing transistor QP34 in the equalizing circuit 13 is turned on, charges of the bit line BL and /BL are then discharged, and potentials of the bit lines BL and /BL are stepped down to a predetermined voltage level. A possible example of the predetermined voltage level is VDD−Vth. VDD is a power supply voltage used for the precharge, and Vth is a threshold voltage of the MOS transistors.
When the step-down/equalizing control signal DEC is negated and turns to “L” level at a timing t33, the step-down transistors QN31 and QN 32 are turned off, and the equalizing transistor QP34 is turned off. As a result, the step-down and equalizing operations for the bit lines BL and /BL are halted.
At a timing t34, the word line WL is asserted, and data is read from the memory cell 11. In the case where “0” is stored in the memory cell 11, current flows from the bit line BL into the memory cell 11, and the potential of the bit line BL is lowered; however, the potential of the complementary bit line /BL is not stepped down. The state in which the bit line BL=“L” level and the complementary bit line /BL=“H” level is judged by the reading circuit 14 as “0” data. In the case where “1” is stored in the memory cell 11, the current flows from the complementary bit line /BL into the memory cell 11, and the potential of the complementary bit line /BL is lowered, however, the potential of the bit line BL is not stepped down. The bit line BL=“H” level and the complementary bit line /BL=“L” level is judged by the reading circuit 14 as “1” data. Broken lines denoting the potentials of the bit lines BL and /BL illustrate the potential reduction irrespective of whether the reduction occurs in the bit line BL or the complementary bit line /BL.
At a timing t35, the word line WL is at “L” level, and the data reading operation is terminated. At a timing t36, the precharge control signal PC is asserted and turns to “L” level, and the precharge transistors QP31 and QP32 and the equalizing transistor QP33 are turned on. Then, the bit lines BL and /BL are precharged with the power supply voltage.
In the foregoing description, the step-down levels of the bit lines BL and /BL are adjusted in accordance with a pulse width of the step-down/equalizing control signal DEC. Provided that the step-down level is ΔV, and the pulse width of the step-down/equalizing control signal DEC is Tw, ΔV∝Tw, which means that the step-down level ΔV is substantially in proportion with the pulse width Tw of the step-down/equalizing control signal DEC.
In the conventional technology, since the step-down transistors QN31 and QN32 of the step-down circuit 15 are directly connected to the bit lines BL and /BL, load capacities of the bit lines BL and /BL are increased, which results in the deterioration of a reading time in a data cycle of reading data from the memory cell.
Further, a timing of the termination of the step-down control is likely to vary when the load capacities of the bit lines BL and /BL are increased. As a result, the step-down levels of the bit lines BL and /BL also vary, which may result in a data-read error.