Non-volatile memory devices are used in any application for the storage of information that must be maintained even when the memory devices are not powered. In recent years, the market for integrated non-volatile memories (or embedded non-volatile memory—emNVM) has undergone considerable development. The emNVM are implemented with other devices on a single chip in order to obtain (electronic) Systems-on-Chip (SoC). The emNVM are implemented in the SoCs, for example, to allow calibration/adjustment during post-production (e.g., for analog and/or radio-frequency circuits) by the manufacturer and/or post-production customisation/configuration by the final user. Moreover, the NVM are implemented in SoCs that store a limited amount of data in systems such as radio frequency identification (RFID).
Several technological approaches are available to create an emNVM. Some approaches allow a single programming (or One Time Programmable) of the emNVM, such as a poly-fuse or anti-fuse type emNVM.
Other technological approaches allow the performing more write cycles on the emNVM, such as in the case of EEPROM (Electrical Erasable and Programmable Read-Only Memory) or FLASH emNVMs, which store a datum by trapping electric charges in an insulated, or floating terminal (floating gate), of a storage transistor.
However, these types of memory cells use technologies and processes generally not comprised in the CMOS standard (to provide floating gate transistors) usually used to implement SoCs. In fact, the storage transistors include an additional polysilicon layer to define regions of their floating gates (in addition to that used to define their gate regions of control as in the standard CMOS). This difference adds complexity of design, which significantly increases the manufacturing cost of the memory devices.
In the art, memory cells of floating gate type obtainable using standard CMOS processes have been developed. For example, single-poly EEPROM (or single polysilicon EEPROM) were developed, which may be implemented in standard CMOS technology since they require only one layer of polysilicon.
In these memory cells, the floating gate is made from a single layer of polysilicon shared between a control capacitor, which dominates and controls the potential of the gate terminal of a MOS transistor connected thereto by capacitive coupling. The programming and erasing of the cell may occur by injection of hot carriers (Hot Carrier Injection—HCI), such as channel hot electrons (Channel Hot Electron—WHO), or by Fowler-Nordheim (FN) tunneling in the floating gate in the proximity of the drain region of the floating gate transistor. Italian patent application No. MI2009A002349 by the same Applicant describes an emNVM that implements single-poly type memory cells.
Such memory cells require control circuitry (e.g., row decoders and column, read and write unit, etc.) that are rather complex (and of considerable dimensions on the chip) since they must be able to generate and provide to each cell comprised in a matrix of the emNVM a plurality of different voltages, also of high value (as compared to a supply voltage of the SoC in which the emNVM is integrated).