1. Field
Exemplary embodiments of the inventive concept are directed to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, exemplary embodiments of the inventive concept are directed to a semiconductor device including a through-electrode for an electrical connection and a method of manufacturing the semiconductor device.
2. Description of the Related Art
As device speeds and device integration increase, signal delays may also increase, for example, due to parasitic capacitance introduced by interconnection structures. Advances in integration technology have led to the development of three-dimensional integration, where wafers may be stacked three-dimensionally, in contrast to the conventional two-dimensional approach.
In a three-dimensional wafer stack package (WSP), a structure called a through-silicon via (TSV) can be used to extend the via hole through a substrate so that a conductive via may be formed to vertically extend and completely penetrate through the substrate. Such a TSV structure may provide higher speeds, higher integration, and improved functionality in comparison to a long wire pattern interconnection. For example, the conductive via may be formed using copper (Cu) having a low resistance. However, copper is known to have high diffusivity in silicon.
A conventional TSV may be formed through the substrate before back end processing. In particular, the TSV structure may be formed by forming an opening or hole in a substrate, such as a silicon substrate. An insulation layer may be formed on the substrate and in the opening. A conductive metal layer, such as a copper (Cu) layer, may be formed in the opening, for example, by a plating process or a deposition process. A backside of the substrate may then be recessed to expose at least a portion of the conductive metal layer, thereby forming a conductive via extending through the substrate. In this case, the substrate including the conductive via may be repeatedly exposed during processes such as an etch process. In particular, when a portion of the conductive metal layer is exposed during an etch process, the metal of the conductive metal layer such as copper may diffuse into the substrate to thereby deteriorate a semiconductor device such as a semiconductor chip.