Typical process flows that are performed to form FinFET devices involve forming a plurality of features in a substrate to define the areas where shallow trench isolation (STI) regions will be formed and to define the initial structure of the fins. The features have a target depth that is sufficient for the fin height and deep enough to allow formation of an effective STI region. After the features are formed, a layer of insulating material, such as silicon dioxide, is formed so as to overfill the features. Thereafter, a chemical mechanical polishing (CMP) process is then performed to planarize the upper surface of the insulating material with the top of the fins (or the top of a patterned hard mask). Thereafter, an etch-back process is performed to recess the layer of insulating material between the fins and expose the upper portions of the fins, which corresponds to the final fin height of the fins.
One challenge of fabricating, or etching, the insulating material between the fins is micro-loading between regions of dense features and regions of isolated features. Micro-loading manifests itself as differences in feature profile and etch depth between regions of high feature density and regions of low feature density. For example, regions of low feature density may etch to a depth that is different than an etch depth corresponding to the regions of high feature density. For example, in some cases regions having isolated features may be etched faster (i.e. forward micro-loading) or slower (i.e. reverse micro-loading) than regions having high feature density.
Accordingly, the inventors have provided improved methods of controlling fin recess loading.