1. Field of the Invention
The present invention relates to flash memory. More particularly, the invention relates to a flash memory device capable of operating at multiple speeds.
2. Description of the Related Art
Flash memory is one type of commonly used nonvolatile memory. Nonvolatile memory is distinguished from volatile memory (e.g., Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM)) in its ability to retain stored data in the absence of applied electrical power. As conventionally available, flash memory may be classified into NOR flash memory and NAND flash memory.
FIG. 1 is a block diagram illustrating a portion of an array structure for a conventional flash memory device.
Referring to FIG. 1, a conventional flash memory device includes a memory cell array comprising a plurality of memory blocks (BLK0 through BLKn−1) and a plurality of bit lines (BLei and BLoi, where “i” varies from 0 to m−1). A collection of page buffers is associated with odd and even pairs of bit lines (e.g., BLe0 and BLo0). Each page buffer may be configured to select one or both of the corresponding pair of bit lines. For example, during a bit line setup interval of a program operation, each page buffer may be configured to drive its corresponding pair of bit lines with a pre-charge voltage. Subsequently, each page buffer may be configured to drive either one of its corresponding pair of bit lines with a program voltage (e.g., a ground voltage) or a program-inhibit voltage (e.g., a power supply voltage).
FIG. 2 is a circuit diagram showing a portion of the bit line and memory block arrangement identified by the dotted line shown in FIG. 1.
Referring to FIG. 2, paired bit lines BLe0 and BLo0 are respectively connected in strings of memory cells (MC). Each string includes a string select transistor (SST) having its source connected to a corresponding bit line, a ground select transistor (GST) having its source connected to a common source line CSL. The memory cells, or more particularly the transistors associated with the memory cells (MC31 through MC0), are connected in series between the source of the string select transistor (SST) and the drain of the ground select transistor (GST).
In the foregoing configuration, operation of the string select transistor (SST) is controlled by a voltage applied to a string select line (SSL), and operation of the ground select transistor (GST) is controlled by a voltage applied to a ground select line (GSL). Operation of the memory cells (MC31 to MC0) is controlled by a voltage applied through a corresponding word line (WL31 to WL0). In FIG. 2, one of the bit lines BLe0 and BLo0 may be driven with a program voltage or a program-inhibit voltage by a corresponding page buffer. During such operation, and as is well known in the art, the non-driven bit line in the paired bit lines operates as a shield line. Before being driven with the program or program-inhibit voltage, however, both of the paired bit lines BLe0 and BLo0 may be simultaneously pre-charged with a pre-charge voltage via the corresponding page buffer.
FIG. 3 is a diagram illustrating nominal power consumption as a function of program operation internal within a conventional flash memory device, such as the one illustrated in FIG. 1.
As is well understood in the art, the program operation illustrated in FIG. 3 includes a high-voltage enable interval 10, a bit line setup interval 11, a program execution interval 12, and a verify read interval 13. During the high-voltage enable interval 10, a high voltage required for the program execution interval 12 is generated. In the bit line setup interval 11, both bit lines (BLei and BLoi) are pre-charged by a corresponding page buffer, and then one of the paired bit lines is driven with a program voltage or a program-inhibit voltage via the corresponding page buffer. During the program execution interval 12, a selected word line is driven with a program voltage while unselected word lines are driven with a pass voltage. During the verify read interval 13, a determination is made as to whether the memory cells connected to the selected word line (i.e., the memory cells in the selected page) have been properly programmed (i.e., “programmed normally”). One sequential pass through the foregoing intervals 11 to 13 constitutes “a program loop”, or “a unit loop”, which may be repeated until memory cells in the selected page are programmed normally.
As depicted in FIG. 3, the program operation draws the greatest operating current, and thereby consumes the most power, during the bit line setup interval 11. This result arises from the fact that both of the paired bit lines (BLei and BLoi) are simultaneously pre-charged with the pre-charge voltage. A peak current drain is indicated in FIG. 3 by the level “Imax”. Of note in this regard, the peak amount of current drawn during the bit line setup interval 11 may be limited not to exceed some defined critical limit. Such a critical limit may be defined in relation to any number of system requirements or tolerances within a flash memory device.
For example, in an exemplary case where a flash memory device is characterized by a 2 KByte page depth and an even/odd bit line configuration, a peak current limit (Imax) may arise when 2 KB*2 (4 KB) bit lines are simultaneously pre-charged with a power supply voltage (VCC) during a bit line setup interval. Under these assumptions, the peak current limit (Imax) may reach 60 to 120 mA. This peak current limit may preclude (or greatly inhibit) the use of multiple operating speeds within a flash memory device supporting selectively enabled modes characterized by different operating speeds. In such devices, peak current consumption may exceed a defined peak current limit in one operating mode during its bit line setup interval.
One conventional example of a flash memory device supporting selectively enabled operating modes having different operating speeds is disclosed in U.S. Pat. No. 6,724,682, the subject matter of which is hereby incorporated by reference. In this conventional example, a flash memory device is disclosed having both single and double speed operating modes. Continuing forward with the assumptions stated above, a flash memory device with a single speed operating mode performs a read or program operation in relation to a 2 KB unit, and therefore simultaneously drives 2 KB bit lines. (As will be appreciated by those of ordinary skill in the art, this unit size may alternately be configured (e.g.,) as 512 B, 1 KB, etc.). Thus, in a case where each page buffer is connected to a pair of even and odd bit lines, and although the flash memory device is running in a single speed operating mode, 4 KB (2 KB*2) bit lines must be simultaneously driven.
Where this type of flash memory device is embedded in a portable or mobile host device, the capabilities of the supporting host device battery must be considered, along with other flash memory related system considerations. For example, the effect of simultaneously driving (pre-charging) paired bit lines must be considered. Yet, the possible provision of single and double speed operating modes must also be considered. That is, battery capabilities, peak current limit definition, and global programming intervals must be carefully balanced to allow multiple speed operating modes, such that peak current demanded by one operating mode does not exceed allowable critical limits and/or battery capabilities.