The present disclosure relates to a semiconductor device and, more specifically, relates to a semiconductor device employing a multilayer bus configuration.
In recent years, as the semiconductor manufacturing technique improves, a semiconductor integrated circuit is miniaturized, and “system-on-chip” in which a processor core and a plurality of function blocks are mounted on the same chip is being developed. A system-on-chip mainly employs a multilayer bus configuration in which a plurality of buses are preliminarily provided for functions. With the bus configuration, a plurality of bus masters can access different bus slaves at the same time.
As a semiconductor device employing the multilayer bus configuration, for example, Japanese Unexamined Patent Application Publication No. Hei 10(1998)-228413 (patent literature 1) discloses a device “which arbitrates competition of accesses to buffers related to a plurality of memory banks by arbitrating means by sending data which is read/written from/to the memories by masters via buffers for the respective masters provided for memory banks” (refer to “Abstract”).