More than one semiconductor integrated device may be manufactured on a single wafer to facilitate integrating devices having different electrical characteristics into a semiconductor chip. Such an integrated semiconductor device may be called a multi device. For example, a multi device may include a low voltage metal-oxide semiconductor (MOS) transistor operating at 1.5 V and a high voltage MOS transistor operating at 3.3 V. These two devices may be formed in the same semiconductor chip.
In manufacturing a multi device, an additional masking step may be needed, as compared with a manufacturing process of a single integrated device having devices with common electrical characteristics. One reason may be as follows. To form devices having different electrical characteristics in a multi device, physical characteristics, such as a device size, a thickness of the oxide film, and a concentration of an impurity implanted into the silicon surface, may be different from each other. Generally, it may be difficult to simultaneously form devices having different physical characteristics under optimum process conditions.
For example, in a high voltage MOS transistor, a high voltage may be applied to a gate electrode. To provide for device stability, a gate oxide film may need to be formed thicker than a gate oxide film in a low voltage MOS transistor. In this case, a step may exist between the gate oxide films in the same wafer. It may be difficult to form the gate oxide films having a step in a single process using a known oxidation process. Therefore, after the gate oxide film for the high voltage transistor is formed, the gate oxide film for the low voltage transistor may be formed.
The gate oxide film for the low voltage transistor maybe formed as follows. First, a photosensitive film may be applied. Next, the photosensitive film corresponding to a region where the low voltage transistor is to be formed may be removed by using an exposure process with a mask. Next, the gate oxide film in the region where the low voltage transistor is to be formed may be removed by a predetermined thickness using an etching process. In this way, gate oxide films having a step may be formed. Hence, an additional masking step may be needed.
Devices having different physical characteristics may have different electrical characteristics. In some instances, the devices may need to be manufactured separately. For example, an ion implantation process may be performed to form a lightly doped drain (LDD) structure which may prevent current leakage due to drain induced barrier lowering (DIBL) in a MOS transistor. In a multi device, the ion implantation process may be performed separately for a low voltage MOS transistor and a high voltage MOS transistor to achieve different electrical characteristics.
FIGS. 1A-1C illustrate a related art LDD ion implantation process for a multi device having a low voltage transistor and a high voltage transistor. Referring to FIG. 1A, field oxide film 101 may be formed on and/or over silicon wafer 100. First gate oxide film 102 for a low voltage MOS transistor and second gate oxide film 103 for a high voltage MOS transistor may then be formed. Step 104 may thereby exist between first gate oxide film 102 and second gate oxide film 103 due to a difference in thickness between them.
Gate 105, which may include polysilicon, may then be formed on and/or over first and second gate oxide films 102, 103. An ion implantation process may then be performed, and may result in formation of an LDD structure. The ion implantation process may be performed separately for the low voltage MOS transistor and the high voltage MOS transistor. This may be because different ion implantation conditions may be necessary to form the LDD structures of the respective transistors.
Thus, referring to FIG. 1A, a photosensitive film may be applied to an entire surface of the wafer. Next, photosensitive film 118 corresponding to the low voltage MOS transistor may be removed by using an exposure process, while photosensitive film 106 corresponding to the high voltage MOS transistor may remain. Ion implantation process 107 may be performed, and may form LDD structure 108 of the low voltage MOS transistor. After the ion implantation process for the low voltage MOS transistor is completed, photosensitive film 106 corresponding to the high voltage MOS transistor may be removed.
To form an LDD structure in the high voltage MOS transistor using an ion implantation process, in the same manner as described above, a photosensitive film may be applied and an exposure process may be performed. Referring to FIG. 1B, photosensitive film 106 corresponding to the high voltage MOS transistor may be removed, while photosensitive film 118 corresponding to the low voltage MOS transistor may remain. Next, ion implantation process 109 may be performed, and may form LDD structure 110 for the high voltage MOS transistor.
Referring to FIG. 1C, step 104 between the gate oxide films may be removed. Spacers 111 may be formed on side surfaces of each gate. Ion implantation process 112 may then be performed, and may form source/drain regions 113 of the transistors.
Ion implantation processes to form each LDD structure may be performed separately for the high voltage MOS transistor and the low voltage MOS transistor. That is, when LDD ion implantation is performed for one transistor, a photosensitive film may be formed to block ion implantation into the other transistor. Hence, an additional masking step may be needed. The need of an additional masking step may increase a cost for a mask and may increase a number of steps in a manufacturing process. This could delay product development.