1. Field of the Invention
The present invention relates to a system for using bridges in a failover system and, in preferred embodiments, for allowing two or more processors to act as bus masters in a PCI to PCI bridge failover system.
2. Description of the Related Art
The Peripheral Component Interconnect (PCI) bus is a high-performance expansion bus architecture that was designed to replace the traditional ISA (Industry Standard Architecture) bus. A processor bus master communicates with the PCI local bus and devices connected thereto via a PCI Bridge. This bridge provides a low latency path through which the processor may directly access PCI devices mapped anywhere in the memory or I/O address space. The bridge may optionally include such functions as data buffering/posting and PCI central functions such as arbitration.
The PCI specification provides for totally software driven initialization and configuration via a separate configuration address space. During the configuration, the PCI bus master processor can read or write to the configuration space of each device connected to the local PCI bus in order to map the device to the memory address space and assign address spaces to the connected devices. The architecture and operation of the PCI local bus is described in "PCI Local Bus Specification," Revisions 2.0 (April, 1993) and Revision 2.1s, published by the PCI Special Interest Group, 5200 Elam Young Parkway, Hillsboro, Oregon, which specifications are incorporated herein by reference in their entirety.
A PCI to PCI bridge provides a connection path between two independent PCI local busses. The primary function of the bridge is to allow transactions between a master on one PCI bus and a target device on another PCI bus. The PCI Special Interest Group has published a specification on the architecture of a PCI to PCI bridge in "PCI to PCI Bridge Architecture Specification," Revision 1.0 (April 10, 1994), which specification is incorporated herein by reference in its entirety. This specification defines the following terms and definitions:
initiating bus--the master of a transaction that crosses a PCI to PCI bridge is said to reside on the initiating bus. PA1 target bus--the target of a transaction that crosses a PCI to PCI bridge is said to reside on the target bus. PA1 primary interface--the PCI interface of the PCI to PCI bridge that is connected to the PCI bus closest to the CPU is referred to as the primary PCI interface. PA1 secondary interface--the PCI interface of the PCI to PCI bridge that is connected to the PCI bus farthest from the CPU is referred to as the secondary PCI interface. PA1 downstream--transactions that are forwarded from the primary interface to the secondary interface of a PCI to PCI bridge are said to be flowing downstream. PA1 upstream--transactions forwarded from the secondary interface to the primary interface of a PCI to PCI bridge are said to be flowing upstream.
Thus, a PCI to PCI bridge has two PCI interfaces, the primary and secondary. Each interface is capable of either master or target operation. The bridge functions as a target on the initiating bus on behalf of the target that actually resides on the target bus. Likewise, the bridge functions as a master on the target bus on behalf of the master that actually resides on the initiating bus.
A master processor configures the PCI bridges, PCI local busses, and devices connected thereto and maps such devices to the memory address space using a combination of type 0 and type 1 configuration operation commands. Type 0 configuration commands are not forwarded across PCI to PCI bridges. Type 0 configuration commands are used to configure PCI to PCI bridges or other PCI devices that are connected to the PCI bus on which the type 0 configuration command is generated. Type 1 configuration commands can be forwarded by PCI to PCI bridges to any level within the PCI bus hierarchy, such as further busses and bridges. A PCI to PCI bridge that receives a type 1 configuration command converts the command to a type 0 command to configure devices connected to the bridge's secondary interface if the bus number in the type 1 command matches the bus number of the bus connected to the bridge's secondary interface, i.e., the secondary bus number. The bridge will forward a type 1 configuration command down its secondary interface to another PCI bridge if the address specified in the type 1 command is between the bus number of the bus attached to the secondary interface of the bridge and a subordinate bus number of the bridge. The subordinate bus number is the number of the highest numbered PCI bus that is behind or subordinate to a bridge.
During system initialization, the BIOS generates the secondary bus number, the primary bus number, which is the bus number of the bus that the primary interface of the bridge is connected to, and the subordinate bus number and records such information within PCI bridge registers. The BIOS that finds a PCI to PCI bridge further needs to map all devices that reside below the bridge on the primary interface to memory address space.
One limitation in the prior art is that a PCI subsystem, comprised of a hierarchical arrangement of local PCI busses, PCI to PCI bridges, and other devices, cannot be configured separately by two different processor bus masters as part of a failover system. For instance, primary and secondary processors may be connected to a PCI subsystem and each capable of functioning as a bus master. During initialization, the bridge for the primary processor will assign bus numbers to all the busses in the subsystem and assign address space to all devices and bridges within the subsystem. If the primary processor failed, then in a failback system, the secondary processor would attempt to assume control of the subsystem. However, limitations in the PCI prior art would prevent the secondary processor from successfully taking the place of the primary processor. In the current PCI prior art, the secondary processor would reconfigure the PCI bridges, busses and other devices connected to the system with bus numbers and addresses that conflict with the numbers and addresses assigned by the failed primary processor. The conflicting configurations assigned by the two bus masters prevent a dual master processor design in a PCI to PCI bridge failover subsystem.