The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device incorporating a test circuit, and a method of operation thereof.
A semiconductor memory device comprises of millions of memory cells tightly packed in an array on a semiconductor substrate. To ensure the quality of a memory device, various tests must be conducted on the memory cells in order to detect defective products prior to their shipments. Because the number of memory cells within a device is enormous, a preliminary test is typically performed on all memory cells to determine whether any cell is defective. If all of the memory cells pass the preliminary test, then no further tests need to be conducted. For example, a current leakage test is conducted on all cells, and if no usual leakage current is detected, then there is no need to test the memory cells individually for leakage current. But if a large leakage current is detected, it may indicate that the memory device has at least one defective cell. Further tests are required to determine which memory cell is defective and whether it can be cured.
A test circuit that implements such preliminary testing may include a first test pad connected to all word lines and a second test pad connected to all bit lines. By applying test signals to the first and second test pad, all of the memory cells can be tested at the same time. Typically, the test circuits are built in the scribe line of the wafer. Such test structure can measure the electrical characteristics of memory cells to determine if the device is defective, but because the same signal is applied to all the cells, interference between neighboring cells cannot be detected.
The present invention is directed to an improved testing structure so that different groups of memory cells can be tested, and defects related to interaction between neighboring memory cells can be detected, thus allowing improvement of manufacturing process in an efficient manner.