This invention relates generally to programmable logic circuitry, and more particularly the invention relates to circuitry which is flexible in application and efficient in circuit implementation.
Programmable logic circuits are important design tools and also provide a convenient replacement for small and medium scale integrated circuits. They allow the circuit designer to reduce package count with attendant lower cost and higher reliability. They also reduce inventory costs since a single programmable circuit can be used for many different applications.
A number of integrated circuits are known which offer programming flexibility. The electrically programmable logic array (PLA) and the field programmable logic array (FPLA) offer circuit flexibility but require complex circuitry which is not cost effective. The PLA comprises an array of logical AND gates and OR gates which can be programmed by mask during manufacture or by fusible links for a specific function in random logic networks, data routing, code converters, decoders, and the like.
The programmable array logic (PAL) was introduced to improve cost effectiveness but has substantially less flexibility in use. As described in U.S. Pat. No. 4,124,899, the PAL comprises a matrix of circuit inputs and the inputs to a plurality of AND gates. Outputs from subgroups of AND gates are non-programmably connected as inputs to individual, specific OR gates.
Copending application Ser. No. 754,653 filed July 15, 1985, now abandoned, discloses an electronically programmable gate array which has instant field programming features and includes universal (i.e. versatile configurable or programmable) logic cells. Moreover, the array is inexpensive and permits quick logic design and implementation. Since the array provides fast return time, circuits can be designed, fabricated, tested and installed more quickly than custom circuitry (e.g. gate array, standard cells, and full custom) and permit lower relative costs of producing a final product when non-recurring expenses are included.
Briefly, the electronically programmable gate array includes a plurality of cells with each cell including a plurality of gates which can provide at least one programmable logic function such as a gate, a flip-flop, and the like. A programmable interconnect structure is provided to selectively interconnect the gates of each cell and the plurality of cells. The selectively interconnected cells are interconnected by means of address and programming lines, with input/output pins, clock, and reset lines. Each of the cells is programmable to alter the specific functions thereof. Accordingly, a wide variety of programming options are provided. In accordance with one feature of the invention, electrically programmable elements determine the interconnect pattern and the specific function of the cells (e.g. gates and flip-flops).