The present invention relates to a semiconductor device and, more particularly, relates to a technique effectively applied to a semiconductor device using an SOI substrate and a method of manufacturing the same.
As an MISFET in which short-channel characteristics and element variations can be suppressed, an MISFET using an SOI substrate is used. The SOI substrate has a supporting board made of Si (silicon) or the like, an insulating layer (also called a BOX (Buried Oxide) layer) over the supporting board, and a thin semiconductor layer made of Si or the like over the insulating layer. An MISFET is formed by using the semiconductor layer. Such an MISFET can adjust the threshold voltage by applying voltage to the rear face side of the insulating layer.
In some cases, in such an SOI substrate, the MISFET and other elements are mixedly provided.
For example, patent literature 1 (Japanese Unexamined Patent Application Publication No. 2008-235310) discloses a semiconductor device having an ESD protection transistor. It also discloses that the total capacitance of a transistor for capacitance between a drain electrode of an ESD protection transistor and a bulk substrate is a function of the capacitance of a gate oxide film, the depletion layer capacitance of an SOI layer, and the capacitance of an insulating layer.
Patent literature 2 (Japanese Unexamined Patent Application Publication No. 2009-64860) discloses a semiconductor device having an MOS varactor formed in a main surface of an SOI substrate. The MOS varactor has a gate insulating film formed in a surface of an SOI layer, a gate electrode formed over the gate insulating film, and an n+type semiconductor region formed in the SOI layer on both sides of the gate electrode.