1. Field of the Invention
The present invention relates to semiconductor memory devices and methods of fabricating the semiconductor memory devices, in particular, semiconductor memory devices with a ferroelectric capacitor and methods of fabricating the same.
2. Description of the Related Art
A semiconductor memory device with a ferroelectric capacitor has the nature that even after a voltage is removed, it retains polarization in a direction of an applied voltage (the nature of spontaneous polarization) and, by making use of the nature of the spontaneous polarization, it is used as a nonvolatile memory that retains data. However, the spontaneous polarization of ferroelectrics has the temperature dependency and tends to decrease as a temperature becomes higher. Accordingly, when the data retention due to the ferroelectric capacitor is performed under a high temperature environment, an amount of spontaneous polarization of the ferroelectric capacitor decreases and the data is likely to be destroyed.
An existing semiconductor memory device that uses a ferroelectric capacitor is described in, for instance, patent literature 1. In the semiconductor memory device, a first transistor that has a ferroelectric capacitor in a gate portion and second and third transistors respectively connected to source and drain regions of the first transistor are formed through an insulating film on a supporting substrate. In such a configuration, in the case of a voltage to the ferroelectric capacitor being ceased to apply, when the second and third transistors are in a non-conduction state, since an active region of the first transistor is insulated with the insulating film from the supporting substrate, the active region of the first transistor becomes a floating state. Thereby, both ends of a series circuit of the ferroelectric capacitor and a gate insulating film, that is, a potential of an electrode of the ferroelectric capacitor and a potential at an interface between the gate insulating film and the active region are inhibited from becoming the same potential, and thereby the inverse bias retention where electric charges are cancelled out between the ferroelectric capacitor and the gate insulating film is inhibited from occurring.
Patent literature 1: JP-A No. 2000-269444 (pages 4 and 5, and FIG. 1).
The semiconductor memory device described in the patent literature 1 is a semiconductor memory device in which an electrode of a ferroelectric capacitor is connected to a gate portion of a first transistor, and owing to the spontaneous polarization of the ferroelectric capacitor the conduction or non-conduction of the first transistor is controlled. In such a configuration, the reverse bias retention between the ferroelectric capacitor and the gate insulating film is suppressed from occurring.
On the other hand, in a semiconductor memory in which a ferroelectric capacitor is connected to source and drain regions of a selection transistor and thereby a voltage is read out of the ferroelectric capacitor, from a reason different from the reverse bias retention, the data of the ferroelectric capacitor are likely to be destroyed. That is, since the ferroelectric capacitor is connected to the source and drain regions of the selection transistor, in the case of the data retention being carried out under a high temperature environment, charges are likely to move through a supporting substrate. Specifically, the source and drain regions of the selection transistor that are connected to one electrode of the ferroelectric capacitor are formed on the supporting substrate and a plate line driving portion that drives a plate line that is connected to the other electrode of the ferroelectric capacitor is also formed on the supporting substrate; accordingly, a path of charge transfer is likely to be formed through the supporting substrate between both electrodes of the ferroelectric capacitor. Accordingly, when the data retention is performed under a high temperature environment, a polarization amount of the ferroelectric capacitor decreases, charges at the electrodes of the ferroelectric capacitor transfer through the above-mentioned path and decrease. Thereafter, even when the ferroelectric capacitor is returned to under a low temperature environment, since charges at the electrodes of the ferroelectric capacitor are diminished, the spontaneous polarization amount does not turn back and the data is likely to be destroyed. In the patent literature 1, there is no mention of the problem of the data retention of the configuration where the ferroelectric capacitor is connected to source and drain regions of the selection transistor, that is, the problem of the data retention capability under a high temperature environment.
An object of the present invention is, in a semiconductor memory device in which a ferroelectric capacitor is connected to a main current path end of a selection transistor, to improve the data retention capability under a high temperature environment.