1. Field of the Invention
The present invention relates, in general, to layout and arrangement of components on a semiconductor chip, and, more particularly, to arrangement of capacitors for precision matching in an integrated circuit.
2. Relevant Background
Because capacitors are easily implemented in MOS fabrication technology, capacitors rather than resistors are used as the precision components in many analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). A plurality of capacitors are used as the precision elements in an array. A technique referred to as "charge redistribution" is used to operate ADCs and DACs using capacitors as the storage element. The accuracy of the ADC converter using the charge redistribution technique is primarily determined by the matching of the capacitors in the array.
In a charge redistribution converter, a sample is stored dynamically with minimum loss in an array of precision matched capacitors. The sample is stored as charge that is moved from one array capacitor to another by MOSFET switches. One of the more widely used charge redistribution converter techniques is based on successive approximation. This technique primarily uses capacitors having binary weighted values with a top plate of all the capacitors connected to one input of a comparator and the bottom plates switched between various voltages. The steering of the various switches is controlled by the comparator through auxiliary logic circuitry.
The charge redistribution conversion process is begins with a sampling step followed by a charge redistribution step in which the output digital word (or "byte") is determined. In the sampling step, the top plates of the capacitors are normally connected to ground or some suitable sample reference voltage, and the bottom plates are coupled to the input voltage. This results in a stored voltage on the bottom plate that is proportional to the input voltage.
The sample step may be followed by an optional hold step in which the top plate is electrically isolated and the bottom plates are normally connected to ground or some suitable hold reference voltage. During a hold step, the charge on the top plate is conserved and the top plate potential goes to the negative of the input voltage. Because the hold step can complicate the conversion process, it is often not used.
In the conversion or redistribution step, each individual bit of the output byte is determined by sequentially connecting the bottom plates of each of the capacitors to either a redistribution reference voltage or to ground until the voltage on the top plate reaches a predetermined voltage. This is usually the trip point of the comparator.
The array is a collection of capacitors having top plates that are all connected to a comparator input node. As used herein, the term "array capacitor" means any of the capacitors used for charge redistribution and is not intended to imply that the capacitors are arranged in a grid or geometric array. Most often, a binary array is used, meaning that the ratios of the capacitors within the array are powers of 2 (i.e., C.sub.N =2C.sub.N-1 =4C.sub.N-2 =2.sup.N-1 C1). The ADC linearity is determined by the errors in these ratios.
Error mechanisms in semiconductor fabrication processes that affect these ratios include patterning and etching variations when fabricating the capacitor plates and dielectric thickness variations when fabricating the insulator layer. Other error mechanisms are known and may dominate in a particular fabrication process including variations in dielectric constant or insulator composition. The present invention addresses ADC linearity limitations that are caused by the control of the fabrication process.
To reduce factory variations, each array capacitor is formed from a plurality of small, identical "unit capacitors". In this manner, process variations that affect the periphery of a unit capacitor have a proportionate affect on each of the array capacitors. The grouping of the unit capacitors in the array mimics the desired capacitor ratios. For example, if a ratio C.sub.2 =2C.sub.1 is desired, then C.sub.2 has two capacitors identical to C.sub.1 connected in parallel. This means that a binary array of N capacitors has of 2.sup.N -1 identical unit capacitors. The capacitance of each unit capacitor is typically that of the smallest capacitor in the array.
To minimize differences between unit capacitors they are typically placed on a regular two-dimensional grid. The grid is extended one extra unit in all four directions to surround the array by a perimeter of dummy unit capacitors. The dummy unit capacitors make the local environment of all interior unit capacitors as identical as possible. In spite of this great care in array layout, the complete elimination of fabrication errors is virtually impossible.
It has been recognized that many fabrication processes have spatial variations across a wafer and across a single integrated circuit chip. These variations make precision device matching difficult. Capacitor arrays for charge redistribution ADC devices have been formed from symmetrically arranged groups of the unit capacitors to compensate for spatial parameter variation across the chip. However, it has been discovered that such groupings only compensate for linear parametric variations. Hence, certain fabrication technologies that exhibit nonlinear parametric variations have produced poor device matching when simple symmetric arrangement is used.
Although capacitors can be formed using thin film materials such as polysilicon or polycide for the electrodes, such processes are relatively expensive to add to a conventional CMOS fabrication process. Also, in conventional CMOS processes, the dielectric placed between layers of thin films is typically quite thin. Although maximizing the capacitance per unit area is often desired, the thin film capacitors resulting from a conventional CMOS flow have such high capacitance per unit area that each of the array capacitors must be physically small to provide a suitable input impedance for the ADC. However, physically small capacitors exhibit greater process variability. Hence, it would be desirable to fabricate the unit capacitors using structures that allow physically large capacitors with low capacitance per unit area.
Metal-to-metal capacitors are formed during the interconnect metallization portion of conventional CMOS processing. The metal layers are typically separated by a thick dielectric that gives them relatively low capacitance per unit area. Unfortunately, prior efforts to arrange the metal-to-metal capacitors using the same symmetrical arrangements used for polysilicon capacitors have resulted in poor matching and greater ADC linearity errors. What is needed is a capacitor arrangement and method for arranging capacitors that compensate for process variations not handled by conventional symmetrical layouts.
A great deal of effort and expense has occurred in the industry recently to develop methods and structures that correct these errors. One method uses a second binary array of capacitors that adds to the regular charged redistribution capacitor array and error correcting signal to compensate for the mismatch. This error correcting signal is then stored and the other error correcting signals for the other capacitors in the regular capacitor array are determined and subsequently stored for later correction of other capacitance mismatch.
The present invention has particular application in charge redistribution ADCs that use an array of matched capacitors. However, it should be understood that the present invention is useful in any device requiring matched performance between devices on the chip. For example, matched capacitor arrays are used in digital to analog converters and switched capacitor filters also. Moreover, other types of matched devices, such as matched resisters or matched active devices including field effect transistor or bipolar transistors, can make use of the layout method and structure in accordance with the present invention. However, for purposes of discussion the present invention will be illustrated in terms of a charge redistribution ADC only.