In recent years, according to a popularization of portable devices, in stead of volatile memories such as a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), in which data stored in a memory are disappeared unless an electric power is continued to be supplied, a nonvolatile memory in which stored data can be kept without supplying an electric power attracts an attention. As the nonvolatile memory, an EPROM (Erasable and Programmable Read Only Memory), a flash memory, and so on, are already used widely, but they both are time-consuming in data writing, and therefore, the use and application thereof are limited to be used as memories capable for reading/writing of data.
On the other hand, a ferroelectric memory in which a ferroelectric is used for a memory cell, can read and write a data at a speed equivalent to a conventional SRAM, and has nonvolatilily of a stored data. The memory cell of the ferroelectric memory. has a similar configuration with the DRAM, and the ferroelectric (ferroelectric capacitor) is used for a capacitor portion to hold the data. Concretely speaking, one electrode of the ferroelectric capacitor is connected to a bit line via a MOS transistor of which gate is connected to a word line, and the other electrode is connected to a plate line.
FIG. 17 is a view showing a hysteresis characteristic of the ferroelectric capacitor. A horizontal axis represents a voltage applied to the ferroelectric capacitor (hereinafter, referred to just as an “applied voltage”), and when an electrode potential at a plate line side is higher than the electrode potential at a bit line side, it is regarded as positive (it is the same as in the following). Besides, a vertical axis represents a polarization charge amount, and a difference between a start point and an end point when it is shifted on a hysteresis curve in accordance with a change of the applied voltage, becomes to be an electric charge amount supplied from the ferroelectric capacitor.
In FIG. 17, when the applied voltage changes from 0 (zero) V to +VDD (power supply voltage) to 0 (zero) V to −VDD, and to 0 (zero) V, the polarization charge shifts from a point P1 to a point P2 to a point P3 to a point P4, and to a point P1. As shown in FIG. 17, on the hysteresis curve, there are two stable points P1 and P3, which have remanent polarizations and have different polarization directions, even when the applied voltage is 0 (zero) V. Data of “1” and “0 (zero)” are respectively corresponded to these points P1 and P3, and thereby, the ferroelectric memory can store the data, and a nonvolatile of the stored data becomes possible.
The ferroelectric memory applies a predetermined voltage to the ferroelectric capacitor based on a characteristic of the ferroelectric shown in FIG. 17, and performs a read/write of data from/to a memory cell.
As for the data write to the memory cell, when the “1” data is to be written, the voltage of −VDD is applied to the ferroelectric capacitor, for example, by turning the electric potential of the bit line to +VDD, and the electric potential of the plate line to 0 (zero) V. Besides, when the “0” (zero) data is to be written, the voltage of +VDD is applied to the ferroelectric capacitor, for example, by turning the electric potential of the bit line to 0 (zero) V, and the electric potential of the plate line to +VDD.
When a stored (written) data is read out of the memory cell, there are various methods to apply a voltage to the ferroelectric capacitor. At present, as for the read of a data out of the memory cell, a method is used in general, in which a voltage is applied to the ferroelectric capacitor toward a direction from the plate line side to the bit line side by, for example, turning the bit line to 0 (zero) V, and thereafter, turning it to a high impedance (floating) state, and turning the electric potential of the plate line to +VDD.
As described above, the data read out of the memory cell appears on the bit line as an electric potential at a certain level, and amplified by a sense amplifier, and so on, to be outputted. As for the electric potential appeared on the bit line in accordance with the read data, an explanation will be given by using FIG. 18. In FIG. 18, a horizontal axis represents a voltage applied to the ferroelectric capacitor, and a vertical axis represents a polarization charge amount.
When the bit line is turned to the high impedance state and the electric potential of the plate line is turned to +VDD, a potential difference between the electric potential of the plate line and the electric potential of the bit line is applied to the ferroelectric capacitor. Herewith, the respective data points shift toward the direction in which the applied voltage value is increasing (in the right direction in FIG. 18) on the hysteresis curve as shown by arrows in FIG. 18, and they stop at the positions corresponding to the voltage value finally applied to the ferroelectric capacitor. The difference between the polarization charge amount at the stopped position and the polarization charge amount before the voltage is applied, is the electric charge amount supplied (flow in) from the ferroelectric capacitor (memory cell) in the read operation.
The electric potential appeared on the bit line during the read operation can be obtained as a result of dividing the electric charge supplied from the ferroelectric capacitor in accordance with a ratio between a capacity of the bit line and the capacity of the ferroelectric capacitor. As it is obvious from FIG. 18, the electric charge amount supplied from the ferroelectric capacitor of the “1” data is larger and the electric potential change of the bit line becomes large.
Besides, in FIG. 18, the points P5 and P6 on the hysteresis curve are operating points when the “1” and “0” data are read respectively, and the difference of voltage values corresponding to the points P5 and P6 becomes to be a data margin (sense margin) DMC of the “1” data and the “0” data. The point P5 is an intersection point of a line (load curve) LC1 with the hysteresis curve, the line LC 1 of which a reference point is a point P7 corresponding to the polarization charge amount at the point P1 and the voltage +VDD applied to the plate line, and the load capacitance thereof is the capacity of the bit line. Similarly, the point P6 is the intersection point of a line LC2 with the hysteresis curve, the line LC2 of which the reference point is a point P8 corresponding to the polarization charge amount at the point P3 and the voltage +VDD applied to the plate line, and the load capacitance thereof is the capacity of the bit line.
As described above, in the conventional ferroelectric memory, the voltage applied to the ferroelectric capacitor and the electric potential appeared on the bit line, and so on, during the data read operation are determined in accordance with the ratio between the capacity of the bit line and the capacity of the ferroelectric capacitor, and the electric charge amount supplied from the ferroelectric capacitor.
Therefore, a memory cell configuration, and so on, in the ferroelectric capacitor has low flexibility, and therefore, there was a case when the capacity of the bit line and the capacity of the ferroelectric capacitor is not an adequate ratio relative to the number of the word lines determined by a design specification, namely, the number of the memory cells connected to one bit line. As a result, a state in which a sufficient voltage is not applied to the ferroelectric capacitor at the time of the data read occurs, and therefore, an error sensing of the read of data, and so on, may occur due to the small electric potential change of the bit line caused by the insufficient supply of the electric charge from the ferroelectric capacitor.
Further, the polarization charge amount of the ferroelectric memory decreases (deteriorate), and the data margin thereof becomes smaller in accordance with the increase of the number of rewrites. Consequently, there are trends that the data margin of the conventional ferroelectric memory becomes smaller, and an operating life of a device becomes shorter when the ratio between the capacity of the bit line and the capacity of the ferroelectric capacitor is not adequate.
There is disclosed a method to improve the electric potential appeared on the bit line by driving a circuit in the sense amplifier with controlling at the time of reading so as to suppress the above-described error sensing, and so on, to perform the data read accurately, in Japanese Patent Application Laid-open No. 2002-74939.
Besides, as it is obvious from the hysteresis curve of the ferroelectric capacitor shown in the above-stated FIG. 17 and FIG. 18, the electric charge amount supplied from the ferroelectric capacitor depends on the voltage applied to the ferroelectric capacitor. Therefore, when a data is read out of the memory cell, it is preferable to apply the voltage to the ferroelectric capacitor as large as possible.
For example, the bit line is connected relative to a ground to keep the electric potential of the bit line to be a ground level (0 (zero) V), and the electric potential of the word line is turned to +VDD, and thereby, it is possible to completely draw (make supply) the electric charge from the ferroelectric capacitor. However, all of the electric charge supplied from the ferroelectric capacitor flows into the ground, and therefore, it is impossible to output a data (information) stored in the ferroelectric capacitor.
Consequently, it is required to make the capacity of the bit line larger to apply a large voltage to the ferroelectric capacitor. However, for example, when a dummy capacitor is added to the bit line to increase the capacity of the bit line, it has almost no effect on rising the electric potential of the bit line (improve the data margin), because the capacity of the bit line also become large although an enough large voltage is applied to the ferroelectric capacitor at the time of reading, to increase the electric charge amount supplied from the ferroelectric capacitor.
Further, when the dummy capacitor is added to the bit line, a charge and discharge of the capacity of the dummy capacitor has to be performed at the time of amplification of the electric potential of the bit line by the sense amplifier, and at the time of a data write to the memory cell by a write amplifier, and thereby, a power consumption increases.
Patent Document 1
Japanese Patent Application Laid-open No. 2002-74939