During the manufacture and subsequent handling of printed circuit boards, defects such as unwanted open circuits or short circuits may develop in or between circuit pathways and electronic components. Manufacturers continually look for faster, more accurate and more economical ways to find defects. It is necessary and cost effective to perform automated testing of both populated and unpopulated printed circuit boards for manufacturing quality control.
Testing of printed circuit boards is becoming increasingly difficult and more expensive as the use of surface mount technology increases and as integrated circuits and printed circuit boards become more complex and operate at higher frequencies. Conventional techniques for automated printed circuit board testing involve applying signals through a set of test pins and measuring output signals on other test pins. "Functional testing" can be performed by energizing the printed circuit board, applying a predetermined set of input signals, and determining whether the proper output signals are generated by the circuitry on the board being tested. Alternatively, a printed circuit board may be tested on a "bed-of-nails" tester that comprises pins which directly contact the metallic traces on the printed circuit board being tested so that selected input signals may be applied at various nodes on the printed circuit board, and corresponding output signals can be measured to other nodes on the printed circuit board. Conventional bed-of-nails testing requires that the functionality of the circuits mounted on the board under test be known, so that test routines can be written to isolate the circuitry of interest, to apply input signals to the appropriate nodes, and to generate expected output signals to be received from other nodes.
Non-contact probes have been used for measurements on high frequency microwave circuits. However, at frequencies below 1 GHz, the test is difficult due to the high bandwidth of the probes. Most recent advances of the test equipment industry have resulted in devices for the evaluation of electromagnetic compatibility (EMC) of PCB assemblies. However, these devices, in their present forms, provide only information about electromagnetic interference caused by active populated boards, and can not be used for providing detailed information about the performance of the board. The present invention is targeted at testing for manufacturing faults of unpopulated boards and inactive populated boards.
One printed circuit board testing method is described in U.S. Pat. No. 5,218,294, issued Jun. 8, 1993 to Soiferman. The technique taught away from using a bed-of-nails tester. The patent disclosed stimulating a printed circuit board through the power and ground lines of the board with an AC signal and then contactlessly measuring the electromagnetic near field distribution proximate the board being tested. The electromagnetic "signature" of the board being tested was compared to the electromagnetic signature of a known good circuit board to determine whether the board under test was defective.
U.S. Pat. No. 4,829,238, issued May. 9, 1989 to Goulette, et al., discloses monitoring electromagnetic emissions from a printed circuit board by energizing the board while it is located adjacent an array of electromagnetic emission measuring probes. A division from that application, U.S. Pat. No. 5,006,788, issued to Goulette, et al. on Apr. 9, 1991. The Goulette patents are directed toward measuring radiating electromagnetic emissions from a circuit board, primarily for the purpose of eliminating or monitoring electromagnetic interference generated by a circuit board or the components thereon. Goulette's approach is not directed toward testing a printed circuit board for manufacturing defects which do not result in interfering levels of electromagnetic radiation. There are numerous other patents, as cited in the Goulette patents, which are directed toward testing printed circuit boards for undesirable radiating emissions.
One alternative printed circuit board testing method is described in U.S. Pat. No. 4,583,042, issued Apr. 15, 1986 to Riemer. That patent disclosed a circuit board test system for measuring the electrical continuity and integrity of line segments. The system consists of a capacitance meter with a pair of sensory terminals, one of which is coupled to a conductive elastomeric backside reference plane and the other is coupled to a test probe. The test probe is a single shielded one-point probe. The sensors measure voltage levels and from the voltage drop between the sensors, the line segment capacitance is determined. The test probe sensor moves relative to the test board for sequentially contacting all of the test points on the printed circuit board.
A deficiency with the Riemer system is the required electrical contact between the test probe and the printed circuit board under test. Another deficiency in the system is the dependence on the board layout, because the location of the test points must be determined prior to probing. Furthermore, it is critical for accurate measurements that the interface between the test board and reference plane be devoid of air gaps.
Another printed circuit board test system is disclosed in U.S. Pat. No. 5,124,660, issued Jun. 23, 1992 to Cilingiroglu. This patent discloses a system that determines whether input and output pins of semiconductor components are present and properly soldered to a printed circuit board. The system includes an oscillator which is connected to a metallic electrode placed on top of an integrated circuit package. A probe pin in a bed-of-nails tester is connected to a printed circuit board wiring trace that is soldered to the pin being tested. The oscillator signal is capacitively coupled through the integrated circuit package to the pin being tested, so if current is measured by the current measuring device, the pin is connected to the printed circuit board.
A deficiency with the Cilingiroglu system is the direct contact required between the bed-of-nails and the board under test. Another deficiency is the test is dependent on the board layout, because the location of the bed-of-nails test points must be determined. Furthermore, it only tests the connection between the pin of a component and the printed circuit board node.
Thus, there is a need in the art for a device and method that will detect manufacturing faults on unpopulated or inactive populated printed circuit boards. Inactive refers to the fact the printed circuit board is not powered up. Furthermore, there is a need for a device in the art that does not require functional test vectors, and that does not require isolating adjacent components on the printed circuit board for test purposes. There is a further requirement in the art that the printed circuit board being tested is not functioning or energized in an unique state during the test procedure. There is still a further need in the art for a "contactless test system", or a system with simple fixturing in which direct electrical contact between sensors or sources and the board under test is not required and the printed circuit board is tested independent of its structure and functionality.