1. Field of the Invention
The present invention relates to a structure of a semiconductor substrate producing an excellent gettering effect.
2. Description of the Background Art
In a manufacturing process of a semiconductor device, alkaline metal such as Na or heavy metal impurities such as Fe are brought into a semiconductor device from a contamination source such as a manufacturing apparatus, chemicals and atmosphere. These metal impurities have harmful influence, such as change of characteristics of the semiconductor device and an increase in junction leakage current. Therefore, a process to remove such metal impurities from inside a semiconductor device is carried out. The process is called gettering. Two such gettering processes are known, one being extrinsic gettering in which impurities are normally segregated through heat-treatment at high temperatures on a back surface of a semiconductor substrate which is not an active region of an element, and the other being intrinsic gettering in which a place for segregating harmful impurities is provided using supersaturated oxygen included in a silicon substrate. A conventional intrinsic gettering method will be described.
FIG. 11 is a sectional structural view of a silicon wafer which has undergone a gettering process. A denuded zone (hereinafter referred to as a DZ layer) having neither oxygen precipitates nor lattice defects is formed on a surface region of a silicon wafer 1 and an IG layer 4 producing a gettering effect is formed within a silicon wafer 1. Since lattice defects or the like do not exist in DZ layer 3, a variety of semiconductor elements are formed in this layer. IG layer 4 is a region where many oxygen precipitates 6 exist. Metal impurities brought into the surface of silicon wafer 1 are segregated around the oxygen precipitates 6 of the IG layer 4, so that DZ layer 3 in the surface of silicon wafer 1 is protected from contamination of impurities.
An intrinsic gettering method will be described. FIGS. 12 through 15 are diagrams showing steps of the gettering method for silicon wafer 1 shown in FIG. 11.
First, referring to FIG. 12, a silicon wafer la is prepared. Silicon wafer la manufactured by, for example, a Czochralski method (hereinafter referred to as a CZ method) has a concentration of oxygen of 14-18.times.10.sup.17 atoms/cm.sup.3.
Next, as shown in FIG. 13, silicon wafer 1a undergoes heat treatment at high temperatures of 1000.degree.-1250.degree. C., and oxygen 2 included in silicon wafer 1a is diffused outward. Through this step, DZ layer 3 of a low concentration of oxygen is formed in a surface of silicon wafer 1a. A region 4a of which concentration of oxygen is uniform remains inside silicon wafer 1a.
Thereafter, as shown in FIG. 14, heat treatment at low temperatures of 500.degree.-800.degree. C. is carried out and oxygen precipitation nuclei 5 grow in region 4a.
Referring to FIG. 15, in heat treatment at intermediate temperatures of 800.degree.-1100.degree. C., oxygen precipitating nuclei 5 are grown to be oxygen precipitates 6. The region where oxygen precipitates 6 are formed is IG layer 4 producing a gettering effect.
After three stages of heat treatment are carried out, silicon wafer 1a is placed into a manufacturing process of a device. Heat treatment to be carried out in the manufacturing process of a device may be replaced with the heat treatment step at intermediate temperature shown in FIG. 15. However, if the heat treatment in the manufacturing process of a device is short and insufficient, the above described heat treatment at intermediate temperature is carried out prior to the manufacturing process of a device.
Generally, DZ layer 3 where semiconductor elements are formed should have a thickness d of at least about 50.mu.m. As described above, a thickness of DZ layer 3 in a silicon wafer 1a manufactured by a conventional IG method is defined in heat treatment at high temperature shown in FIG. 13. In order to increase a thickness d of DZ layer 3, time for heat treatment at high temperature should be longer. If the time for heat treatment at high temperature is set longer, more oxygen 2 is diffused outward from silicon wafer 1a, and as a result, thickness d of DZ layer 3 having a low concentration of oxygen becomes larger. In the heat treatment step at high temperature, oxygen nuclei of IG layer 4 are restrained from growing and does not become larger, so that, in order to grow oxygen nuclei in the IG layer for providing more effective gettering, a time for heat treatment at low temperature shown in FIG. 14 should be set long. If the heat treatment at high temperature or low temperature for such a long time is carried out, non-uniform temperature distribution is caused, resulting in warping of wafer or slip dislocation within the wafer. The heat treatment step for such a long time lowers a throughput of wafer, which is a factor preventing mass production.
FIG. 16 is a diagram showing the distribution of oxygen concentration of the silicon wafer. Referring to the figure, the distribution of oxygen concentration is plotted as a gentle curve from DZ layer 3 to IG layer 4. In a horizontal direction with respect to the surface of wafer 1, oxygen precipitates 6 sparsely exists in a boundary of DZ layer 3 and IG layer 4, as shown in FIG. 11. As a result, necessary thickness d of DZ layer 3 is not uniform, oxygen precipitates 6 are formed in DZ layer 3, and therefore a problem arises that a yield of wafer is decreased.