1. Field of the Invention
The invention relates to the fabrication of integrated circuits and to a process for depositing dielectric layers on a substrate and the structures formed by the dielectric layers.
2. Description of the Related Art
One of the primary steps in the fabrication of modern semiconductor devices is the formation of metal and dielectric layers on a substrate by chemical reaction of gases. Such deposition processes are referred to as chemical vapor deposition or CVD. Conventional CVD processes supply reactive gases to the substrate surface where heat-induced or energy-enhanced chemical reactions take place to produce a desired layer.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 μm and even 0.18 μm feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries.
To further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and to use insulators having low dielectric constants (dielectric constants of less than 4.0) to reduce the capacitive coupling between adjacent metal lines. One such low k material comprises silicon, oxygen, and carbon, and may be deposited as a dielectric material in fabricating damascene features. One conductive material having a low resistivity is copper and its alloys, which have become the materials of choice for sub-quarter-micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 μΩ-cm compared to 3.1 μΩ-cm for aluminum), a higher current and higher carrying capacity. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
One difficulty in using copper in semiconductor devices is that copper is difficult to etch and achieve a precise pattern. Etching with copper using traditional deposition/etch processes for forming interconnects has been less than satisfactory. Therefore, new methods of manufacturing interconnects having copper containing materials and low k dielectric materials are being developed.
One method for forming vertical and horizontal interconnects is by a damascene or dual damascene method. In the damascene method, one or more dielectric materials, such as the low k dielectric materials, are deposited and pattern etched to form the vertical interconnects, i.e., vias, and horizontal interconnects, i.e., lines. Conductive materials, such as copper and barrier layer materials used to prevent diffusion of copper into the surrounding low k dielectric are then inlaid into the etched pattern. Any excess copper and barrier layer materials external to the etched pattern, such as on the field of the substrate, are then removed.
However, low k dielectric materials are often porous and susceptible to interlayer diffusion of conductive materials, such as copper, which can result in the formation of short-circuits and device failure. A dielectric barrier layer material is used in copper damascene structures to reduce or to prevent interlayer diffusion. However, traditional dielectric barrier layer materials, such as silicon nitride, often have high dielectric constants of 7 or greater. The combination of such a high k dielectric material with surrounding low k dielectric materials results in dielectric stacks having a higher than desired dielectric constant.
Additionally, low k materials are susceptible to surface defects or feature deformation during polishing and removal of conductive materials under conventional polishing processes. One solution to limiting or reducing surface defects and deformation is to deposit a hardmask over the exposed low k materials prior to patterning and etching feature definitions in the low k materials. The hardmask is resistive to damage and deformation and protects the underlying low k materials during subsequent material deposition and planarization or material removal processes, such as chemical mechanical polishing techniques or etching techniques, to reduce defect formation and feature deformation.
One difficulty when using hardmasks is that conventional hardmask materials do not have sufficient resistivity to polishing, which may result in premature removal of the hardmask and expose the underlying material to the process. The exposed underlying material, such as the low k dielectric material, may be damaged and result in surface defects and feature deformation. Additionally, conventional hardmask materials often have high dielectric constants of 7 or greater, which can produce dielectric stacks having a higher than desired dielectric constant. Current hardmask materials have not satisfactorily produced both low k material and sufficient polishing resistivity to be used in damascene fabrication.
Therefore, there remains a need for an improved process for depositing dielectric materials with reduced or low dielectric constants as barrier layers or hardmasks with a satisfactory polishing resistivity for damascene applications.