Upon a start-up of a multi-processor computer, or after a reset, first the primary CPU starts and checks whether there are additional processors. If so, it then enables those processors, thus enabling their respective local Advanced Programmable Interrupt Controllers (APICs). The input/output (I/O) APIC, to which the local APICs are connected, is also enabled. Collectively, the local APICs and the I/O APIC are responsible for delivering interrupts from sources to destinations within the multi-processor system. The I/O APIC specifically interfaces with the peripherals which issue hardware interrupts, and distributes the external interrupts according to a preprogrammed interrupt scheme to the local APICs.
When the operating system for such a multi-processor computer is upgraded, specifically when a version of an operating system for a multi-procesor computer based on the Advanced Configuration and Power Interface (ACPI) specification, as developed by Intel, Microsoft and Toshiba, replaces one based on the Intel MultiProcessor (MP) specification, various hardware specific configurations in the BIOS must be revised in order for the new system to function properly. Multi-processor system compliance with the ACPI specification requires that new tables be created to indicate how the system interrupts are wired. On the part of the deployment engineer, this requires knowledge of the specific hardware layout and how the I/O APIC and local APICs operate. Creation of such tables manually can be very time consuming for an engineer charged with deployment of the newer operating system on his customer's hardware and can be expensive for the customer. There is also a substantial likelihood of human-error and an increased necessity for providing customer support.