The present invention relates generally to a method for fabricating integrated circuits, and more particularly, to a fabricating method suitable to fabricate various types of integrated circuits, such as, an integrated circuit including various field effect transistors, an integrated circuit including field effect transistors and bi-polar transistors, and an integrated circuit having transistors which are different in structural parameters, such as, impurity density, conductivity type, thickness of epitaxial growth layer, or the like.
There is presently the need for integrated circuits which exhibit the capabilities of multi-function, high speed and less power; however, due to the insufficiency of the characteristics of the transistors incorporated therein, circuits having the combination of transistors possessing the desired characteristics have not yet been. For example, the field effect transistors can be roughly classified into an insulation gate type (MIS) and a junction type (BJT) depending on the gate structure, and moreover, classified into static induction transistor (SIT) and an FET having a similar characteristic to that of a pentode. The bi-polar transistor is one kind of these transistors. Although the SIT has advantages of higher speed operation and lower power consumption, a low impurity density layer of less than 10.sup.15 cm.sup.-3 is generally required. On the other hand, although the MIS.FET has advantages of lower speed operation with lower power consumption of direct current, an impurity density layer of more than 10.sup.14 cm.sup.-3 is generally required. In addition, it is said that the SIT and BJT have the feature of large capacity of current density, and that the SIT is good at a voltage regulating operation and the BJT is good at a constant current operation.
For example, in accordance with the foregoing facts, in integrated circuits for timepieces, it is desired to use a SIT for the crystal controlled oscillating portion and the higher speed frequency dividing portion, to use a MOS.FET for the lower speed frequency dividing portion and to use a BJT or SIT for the stepping motor driving portion. Moreover, it is easy to use the SIT and BJT for linear circuits, such as, a constant voltage source circuit, a circuit for constant current source or the like. Considering the SIT-IC as an example, for the channel portion alone, there are many structural to be considered factors, such as, the advantageous thickness and impurity density for obtaining the desired frequency characteristic, the advantageous thickness and impurity density for obtaining a large amplification factor or the like. It is preferable that SITs having various structural factors be incorporated into the same crystal in order to realize an integrated circuit having advantages of high efficiency, multi-function, precision and less consumption power.
The present invention provides a method for easily fabricating integrated circuit as described above, and more particularly, provides a method for forming semiconductor layers which are different from each other in impurity density, conductivity type and thickness in such a way that the surface levels of the layers are the same level.
To aid the understanding of the advantages of the present invention, fabricating, a conventional fabricating method will first be described in conjunction with FIGS. 1 and 2.
FIGS. 1(a) to 1(c) are sectional views illustrating steps for forming a vertical type of junction-type SIT and MOS.FET within the same chip. FIG. 1(a) is a sectional view in which an n.sup.+ region 11 is formed on one portion of an n-type Si substrate 10 with a density of approximately 10.sup.-15 cm.sup.-3 and, for example, n.sup.- epitaxial layer 13 with a density of approximately 10.sup.13 cm.sup.-3 is deposited. The n.sup.+ region 11 is a buried layer used for leading out a main electrode of the SIT in a later step, and the thickness of the n.sup.- epitaxial layer is between 5 to 20 [.mu.m] but is selectable at any value in accordance with the desired performance characteristics.
FIG. 1(b) is a sectional view illustrating a concave portion V.sub.3 used for forming an electrode in the n.sup.+ region 11 by selectively etching the Si using a mask of oxide film, and a concave portion V used for forming the MOS.FET in a later step. Since the portion V.sub.3 is different in depth from the portion V, at least two etching processes are required and the depth of each of the portions should be the same as the thickness of the n.sup.- epitaxial layer 13. After this, a p.sup.+ gate region 14 of the SIT, a p.sup.+ source region 112 of the MOS.FET and a p.sup.+ drain region 111 of the MOS.FET are formed by using a p.sup.+ selective diffusion process. Then, an n.sup.+ source region 12 of the SIT and an n.sup.+ drain lead-out region 21 are formed by using an n.sup.+ selective difffusion process, and moreover the n.sup.+ source.drain region is formed within a preformed p well if an n-channel MOS.FET is needed.
FIG. 1(c) is a sectional view showing a drain electrode 1, a source electrode 2 and a gate electrode 4 of the SIT, and electrodes 104, 102, 101 of the MOS-FET which are formed by selective etching process and evaporation for the windows and metal portions of each electrode. It is a difficult task to align the mask for each surface in order to form the SIT and MOS.FET. Although the exposing process is generally carried out under the condition of a tightly applied mask and resist coated over the wafer surface, in the above described step, the exposing process using the tightly applied mask is impossible due to the difficulty in masking the concave portions so that high accuracy patterns cannot be attained. Recently, a projection exposing process has been employed, however, due to the depth of the focus, the accuracy is not so improved when the top face and the bottom face of the concave portion V are exposed at the same time. Moreover, non uniformity of thickness of the photo-resist, cutting-off of the metal wiring persistent and so on are which still need problems to be solved in the future. Of course, without limitation of the example shown in FIG. 1, various values are selectable for the conductivity type of each region, impurity density, thickness or the like, however, the above described problems have not yet been solved. The fabrication steps are not so simple. Furthermore, there are examples employing a deep diffusion other than the method shown in FIG. 1(c), in which the n.sup.+ buried layer 11 is led out through the deep concave portion V.sub.3. However, this is not always preferable because a long duration heating step is required.
To remove the above described disadvantages and problems, a conventional method called a buried epitaxial growth method has been developed. Steps of the method are illustrated in FIGS. 2(a) and 2(b), in which epitaxial growth is carried out after an insulation film 7 is deposited on a substrate 10 and an opening is defined in the insulation film 7 to form concave portion V (FIG. 2(a)). At this time, as shown in FIG. 2(b), the concave portion V is completely filled with a single-crystal growth layer 13 and polycrystal growth layer 33 is deposited on the insulation film 7 at the same time. In this method, there is a likelihood that a projected region 23 is formed around the edge of the concave portion V by protruding the single-crystal growth layer 13 and growing in a vertical direction. To make the surface flat again, the polycrystal growth layer 33 and the projected region 23 should be removed by polishing them from the surface to the inner portion with relatively high speed. During polishing, however, the substrate will be scratched. To omit the step of polishing, it has been attempted to form the insulation film 7 in the form of an over-hang to the concave portion V or to process it by a chemical vapor deposition (CVD) method including HC1. However, it is impossible to fill up the concave portions, each of which has a different depth, at the same time and to obtain a flat surface. To overcome this drawback, various methods, for example, as disclosed in Japanese Patent Application Nos. 63031/79 and 63032/79, have been proposed. However, limitation of size is required since these methods require that the surface of the substrate be a low figure surface orientation, such as (111), (113), (112) or the like and the width of the concave portion be more than two times the interval of the produced growth nucleations to attain remarkable effect.
The present invention has been made in order to overcome the drawbacks of the conventional methods, and one object of the present invention is to provide a fabricating method which comprises forming more than two regions each of which is different in impurity density, conductivity type and/or thickness in such a way that the surface levels of these regions become the same surface level and fabricating semiconductor devices in each of the regions.
Another object of the present invention is to provide a fabricating method, in which a photo-lithography is easily and precisely carried out because the different regions have the same surface level. A further object of the present invention is to provide a method for easily fabricating integrated circuits, in which transistors having structural factors suitable for imparting the desired characteristics are incorporated into the same crystal. As a result, the semiconductor device which is composed of more than two chips by the prior art can be realized as one chip device, and higher performance can be obtained.
The different regions described above are formed by more than one time of selective epitaxial growth under the use of a mask made of an insulation film (SiO.sub.2) or nitricle film (Si.sub.3 N.sub.4). At this time, the mask covers at least the upper surface and the side face of the concave portion. Consequently, the projected region 23 shown in FIG. 2(b) is not formed, and moreover, since a selective epitaxial growth can be made by the CVD method using a mixture gas containing semiconductor chloride and hydrogen, the growth can be carried out without deposition of polycrystal on the insulating film. Other advantages are that the duration of the heating process can be shortened, it is suitable for fine working, and the occurrences of cutting-off of the metal wire and non-uniformity of the film thickness of the photo-resist can be effectively removed since the unevenness of the surface is small as compared with the conventional one and a leading-out region for the buried layer and a region providing isolation between the elements can be formed.
In addition, the crystal surface may be the lower figure surface or a surface deviated therefrom, and is freely selected without any limitation.