1. Field of the Invention
The present invention relates to a clock generator using PLL circuit, and its control method, and more particularly it relates to a clock generator for generating a clock signal of which oscillation frequency is spread in spectrum in order to decrease electromagnetic radiation due to high speed oscillation operation, and a control method thereof.
2. Description of the Related Art
As shown in FIG. 11, a PLL circuit disclosed in Japanese Laid-open Patent No. 2001-7700 comprises a PLL section 100 which is an ordinary PLL circuit for generating oscillation signal PO by operating so that the center frequency may be synchronized in phase with reference frequency signal R, and a dithering control section 200 for controlling dithering which is frequency modulation in specified frequency bandwidth by receiving supply of up signal UP or down signal DN and generating a changeover control signal CC for changing over the dividing ratio of DIV 150. The dithering control section 200 is composed of a latch circuit 210 for latching the state of up signal UP and down signal DN from PFD 11, and a charge pump circuit 220 for generating an additional charge pump signal PS.
In FIG. 12, supposing the center frequency of oscillation signal PO to be 100 MHz, the frequency of reference signal R to be 1 MHz, the basic dividing ratio of DIV 150 to be 100, and the frequency amplitude width to be +/−1 MHz, the operation is described below.
At a certain point T1, suppose the oscillation signal PO drops from the center frequency to 99 MHz. Dividing signal D (0.99 MHz) corresponding to dividing ratio 100 of DIV 150 is delayed in phase from reference signal R, and four pulses of up signal UP are outputted. In response to supply of up signal UP, CP 12 outputs positive charge pump signal PC. The dithering control section 200 outputs dividing ratio changeover control signal CC of L level, and one is added to the dividing ratio of DIV 150 to become 101. The frequency of the dividing signal D further declines from the frequency of reference signal R, and output of up signal UP continues from PFD 11. When the frequency of oscillation signal PO continues to rise until reaching 101 MHz, output of up signal UP from PFD 11 stops, and output of down signal DN starts. In response to supply of down signal DN, CP 12 outputs negative charge pump signal PC. The dithering control section 200 outputs dividing ratio changeover control signal CC of H level, and one is subtracted from the dividing ratio of DIV 150 to become 99. The frequency of the dividing signal D further exceeds the frequency of reference signal R, and output of down signal DN continues from PFD 11. When the frequency of oscillation signal PO continues to fall until reaching 99 MHz, output of down signal DN from PFD 11 stops. Thereafter, repeating the same operation, the oscillation signal PO is dithered within a desired frequency width 99 to 101 MHz.