The present invention relates generally to optimal use of delay circuits clocked by “double data rate” clock signals, and more particularly to systems including circuitry capable of generating double data rate clock signals that optimally clock data into and out of such delay circuits. The invention also relates to circuitry for automatically correcting duty cycles of clock signals to predetermined duty cycle values.
Double data rate clock signals are used to clock data into and out of a circuit, such as a register, on both the rising edges and the falling edges of the double data rate clock signals, allowing the use of a clock frequency that is one half of the data rate, and therefore allows doubling the effective bandwidth of the system. It usually is important that the duty cycle of high frequency (e.g., several gigahertz) double data rate clock signals be precisely 50%, because otherwise, the amounts of time available to accomplish the timing of the clocking or strobing of the data are asymmetrical for the rising and falling edges of the clock. That may cause various kinds of problems, including asymmetrical noise margins in the timing of various associated digital data signals, which is generally undesirable in very high speed (e.g. several gigahertz) applications wherein all aspects of the data signal timing accuracy may be critical.
For example, asymmetric double data rate clock signals cause higher data error rates in the digital signal being clocked and limit the maximum speed of the system clock signal. Because of the usual parameter variations in the inverters of a delay circuit, any variation from the optimum 50% duty cycle of a double data rate clock signal, wherein the data is latched on both the rising and falling edges of the double data rate clock signal, is likely to cause an even greater error rate of the data being clocked through the delay circuit. Therefore, “loose” control of the duty cycle of a “double data rate” clock usually is not acceptable at high frequencies.
“Prior Art” FIG. 1A shows a typical delay locked loop circuit 1 which includes a transmit register 3 that receives the input data signal DATA via multiconductor input bus 2. The signal DATA is clocked into transmit register 3 every data time frame by a transmit clock DLYCLK. That results in the signal DATA IN appearing on a multi-conductor bus 4 at the data input of a receive register 6 a fixed amount of delay time after the rising or falling edge of transmit clock DLYCLK. The fixed amount of delay time is equal to the sum of an intrinsic delay through transmit register 3 plus the signal propagation time along bus 4 from the data output of transmit register 3 to the data input of receive register 6, plus the set-up time of receive register 6. Data that has been clocked into receive register 6 by data clock DCLK appears as DATA OUT on multiconductor bus 5.
DATA IN bus 4 includes a synchronization conductor 4A having the same average total propagation delay as the other conductors of multi-conductor bus 4. Synchronization conductor 4A conducts a synchronization signal DATA SYNC.
Synchronization conductor 4A provides the synchronization signal DATA SYNC to one input of an exclusive OR gate 9, which functions as a phase detector. The other input of exclusive OR gate 9 receives the data clock signal DCLK which is also coupled by conductor 8 to the clock input 6A of receive register 6. Exclusive OR gate 9 produces an output signal DELAY CONTROL on conductor 10, which is connected to a control input of an adjustable delay circuit 11. Adjustable delay circuit 11 produces a delayed data clock signal DLYCLK on conductor 12. The delayed data clock signal DLYCLK produced by adjustable delay circuit 11 is coupled by conductor 12 to the clock input 3A of transmit register 3 to function as its transmit clock.
Data clock signal DCLK and delayed data clock signal DLYCLK serve as double data rate clock signals as shown in FIG. 1B and require a 50% duty cycle. The various “1”s and “0”s of the input data signal DATA on bus 2 are clocked into transmit register 3 by the rising edge A of DLYCLK as shown in the timing diagram of FIG. 1B and then appear on multiconductor bus 4 at the beginning of frame 17 of DATA SYNC on synchronization conductor 4A. During falling edge B of DLYCLK, the various “1”s and “0”s of DATA on bus 2 are clocked into transmit register 3 and then appear on multiconductor bus 4 at the beginning of frame 18 of DATA SYNC on synchronization conductor 4A. Similarly, the various “1”s and “0”s of DATA IN on multiconductor bus 4 are clocked into receive register 6 by the rising edge C of data clock DCLK and then appear as DATA OUT on output bus 5, and during falling edge D of DCLK the various “1”s and “0”s of DATA IN on multiconductor bus 4 are clocked into receive register 6 and then also appear as DATA OUT on output bus 5.
The feedback of the delay locked loop formed of exclusive OR gate 9, adjustable delay circuit 11, and transmit register 3 forces the edges of DLYCLK to be in quadrature phase locked relationship with the DATA SYNC signal. The rising and falling edges of clock signal DCLK on conductor 8 clock successive bits of DATA IN bus 4 into receive register 6. In order to compensate for various delays associated with transmit register 3 and multiconductor bus 4 and also the set-up time of receive register 6, the delay locked loop adjusts the delay between DCLK and DLYCLK until DCLK and synchronization signal DATA SYNC on conductor 4A are in “quadrature”, i.e. 90 degrees out of phase as shown in the timing diagram of FIG. 1B.
However, this operation does not ensure a 50% duty cycle of DLYCLK, which functions as the transmit clock of transmit register 3.
Although the data rates of the foregoing signals could be achieved by providing a clock that has twice the frequency of the signals DATA IN and DCLK and by latching DATA IN only on the rising edge of DCLK, that would double the bandwidth of the system, which in some cases would be impractical or disadvantageous.
Thus, there is an unmet need for a double data rate clock signal having a duty cycle that is not sensitive to changes in integrated circuit process parameters and temperature.
There also is an unmet need for a circuit and technique which can be used to automatically correct the duty cycle of high speed signals, including double data rate clock signals.
There also is an unmet need for a circuit and technique for providing the capability of generating a signal having an arbitrary fixed duty cycle.