1. Field of the Invention
The present invention relates to an electrically rewritable non-volatile semiconductor storage device and a method of manufacturing the same.
2. Description of the Related Art
Conventionally, LSIs are formed by integration of devices in a two-dimensional plane on the silicon substrate. Although it is common to reduce (refine) the dimension for each device in order to increase memory storage capacity, recent years are facing challenges in such refinement from the viewpoint of cost and technology. Such refinement requires further improvements in photolithography technology. However, the costs of lithography process are ever increasing. In addition, if such refinement is accomplished, it is assumed that physical improvement limit, such as in breakdown voltage between devices, would be reached unless driving voltage can be scaled. That is, it is likely that difficulties would be encountered in device operation itself.
Therefore, such semiconductor storage devices have been proposed recently where memory cells are arranged in a three-dimensional manner to achieve improved integration of memory devices (see Patent Document 1: Japanese Patent Laid-Open No. 2007-266143).
One of the conventional semiconductor storage devices where memory cells are arranged in a three-dimensional manner uses transistors with a cylinder-type structure (see Patent Document 1). Those semiconductor storage devices using transistors with the cylinder-type structure are provided with multiple conductive layers corresponding to gate electrodes and pillar-like columnar semiconductors. Each columnar semiconductor serves as a channel (body) part of a respective transistor. Memory gate insulation layers are provided around the columnar semiconductors. Such a configuration including these conductive layers, columnar semiconductor layers, and memory gate insulation layers is referred to as a “memory string”. In this memory string, the columnar semiconductor layers are formed in a matrix form in the row and column directions parallel to the substrate. The conductive layers are formed in a stripe pattern extending in the row direction, and at a certain pitch in the column direction.
In consideration of the lithography resolution limit (F) and the width of conductive layers, at least a distance of 3F in the column direction and 2F in the row direction is required for a distance between the centers of the columnar semiconductor layers. However, there is still a need for non-volatile semiconductor storage devices manufactured with even smaller occupation area than in the conventional technology as mentioned above.