1. Field of the Invention
The present invention relates to steering multiple macroinstructions to a decoder that decodes multiple macroinstructions in parallel.
2. Description of Related Art
Computers process information by executing a sequence of instructions, which may be supplied from a computer program written in a particular format and sequence designed to direct the computer to operate a particular sequence of operations. Most computer programs are written in high level languages such as FORTRAN or "C" which are not directly executable by the computer processor. In order to execute these high level instructions they must first be translated into macroinstructions with a format that can be decoded and executed within the processor.
Macroinstructions are conventionally stored in data blocks having a predefined length in a computer memory element, such as main memory or an instruction cache. Macroinstructions are fetched from the memory elements and then supplied sequentially to a decoder, in which each macroinstruction is decoded into one or more micro-operations having a form that is executable by an execution unit in the processor.
Pipelined processors define multiple stages for processing a macroinstruction. These stages are defined so that a typical instruction can complete processing in one cycle and then move on to the next stage in the next cycle. In order to obtain maximum efficiency from a pipelined processing path, the decoder and subsequent execution units must process instructions as frequently as possible. In other words, their idle time should be kept to a minimum. Accordingly, it is advantageous if at least one new macroinstruction can be steered to the decoder every cycle. In order to supply at least one instruction per clock, a block of instruction code at the most likely location is pre-fetched so that it can be supplied to an instruction buffer when requested.
Variable length instructions can be difficult to locate and align within a block of instruction code. Particularly, in the i486.TM. INTEL instruction set, implemented by processors such as the i486.TM. microprocessor instruction lengths vary between one and fifteen bytes. The existence of variable length instructions creates difficulties in locating instruction boundaries. An "instruction boundary" is defined as the location between adjoining macroinstructions in the instruction code. Furthermore, in the i486.TM. INTEL instruction set, the possibility that one or more prefix bytes precede the first opcode byte of an instruction creates additional difficulties. Due to the prefix bytes, the first opcode byte in a macroinstruction may not be equivalent to the first byte of the complete macroinstruction. Even if the first opcode byte were to be located, the first macroinstruction byte would still not be known, because the existence, and the number of prefix bytes can vary from instruction to instruction.
Because of the above difficulties, it can be difficult to supply even one variable length macroinstruction to a decoder. This problem is even more difficult if multiple variable length instructions are simultaneously required by multiple decoders such as those in the high performance superscalar systems.
It would be an advantage to provide a steering mechanism that can steer multiple macroinstructions aligned with a first opcode byte in every cycle to a multiple instruction decoder. Particularly, such a steering mechanism would be useful for a multiple instruction decoder that can issue multiple micro-operations to a high performance execution unit that executes more than one micro-operation per cycle.