With the rise of deep submicron CMOS technologies, integrated circuit designs are becoming more complex incorporating more and more of a system onto a single chip. System interconnects (i.e., signal lines), previously accessible to standard test and measurement equipment, such as oscilloscopes, spectrum analyzers, and the like, are no longer observable. Advanced BIST (Built-In Self-Test) and DFM (Design For Manufacturing)/DFT (Design For Test) approaches are required to verify that the silicon is designed and operating properly. Several companies, such as LogicVision (a part of Mentor Graphics Corporation in Wilsonville, Oreg., USA), are actively attempting to supply solutions to this problem by providing embedded test IP (Intellectual Property). However, this solution cannot solve a problem of not providing a signal to and from an inter-chip signal line to and from an outside test and measurement instrument.
At the same time, speed and signal densities are driving package manufacturers to use advanced technologies such as MCM (Multi-Chip Module) with ceramic and Silicon-Carrier substrates. The MCM can incorporate several dies or bare ICs (Integrated Circuits) as DUTs (Devices Under Test). FIG. 1 shows a magnified perspective view of a conventional MCM 10. It should be noted that the scales of the elements are not the same in FIG. 1. Two dies 12 and 14 as DUTs are mounted on an upper surface of a module substrate 16 made of ceramic and these dies are connected together via one or more conductive paths (shown by dotted lines) in the module substrate 16. The conductive paths may be on surface traces or buried traces, connected with through-holes so as to transmit signals for the DUTs 12 and 14. A lower surface of the ceramic substrate 16 is mounted on an upper surface of an ECB (etched circuit board) 18 having plural electrodes (or pads) 20 so that the conductive paths of the ceramic substrate 16 are electrically connected to the corresponding electrodes 20 of the circuit board 18 via bumps 22. These electrodes 20 are electrically connected to contacts or pins of a MCM package. A specific kind of cover 23 over the dies 12 and 14 would be a hardened liquid, sometimes called “glob”. Other standard kinds of covers can be a single IC cover, epoxied to the package, or a multichip module cover, epoxied, bolted or screwed to the module.
The above described configuration shown in FIG. 1 allows for significant portions of the system to be pulled together into a single package. This creates the same problem for signal assessability and observability as seen with advanced CMOS designs. To date, no one has offered a solution to observability for package integration.
JTAG architecture was standardized by IEEE std. 1149.1-1990 as Standard Test Access Port and Boundary-Scan Architecture. FIG. 2 shows a simplified block diagram of a conventional IC 30 using JTAG architecture. The IC 30 comprises an inherent IC function block 32, “PIN Test” blocks 34 each inserted between a terminal of the inherent IC function block 32 and a respective contact “I/O PIN”, test logic blocks 36 and 38 each connected between contacts “Test Data In” and “Test Data Out”, and a test access port controller 40 connected to contacts “Test Clock”, “Test Reset” and “Test Mode Select”. The contacts “Test Data In” and “Test Data Out” are connected to both of the lowest “PIN Test” blocks 34. In a normal operation of the IC 30, each “PIN Test” block 34 connects its respective contact “I/O PIN” to the inherent IC function block 32, so that the blocks 36-40 do not operate. In BST (Boundary Scan Test) mode, test data at the contact “Test Data In” is applied to a selected terminal of the inherent IC function block 32 via the “PIN Test” blocks 34 and an output from a selected terminal of the inherent IC function block 32 is applied to the contact “Test Data Out” via the “PIN Test” block 34 under control of the test access port controller 40 that is controlled by a signal from the contact “Test Mode Select”. However, this test mode is difficult to program and needs skilled test engineers. In addition, the test circuits, such as the test logic block and the test access port controller, should be contained in the IC 30 as the DUT. Recently, JTAG architecture has used not only the boundary scan test mode but also a communication method. Therefore, a signal at a desired terminal of the inherent IC function block 32 can be provided from the contact “Test Data Out” to circuitry external to the IC 30 under control of the “PIN Test” blocks 34. In this manner, the contact “Test Data Out” acts as a JTAG interface port.
Applying JTAG architecture to the MCM 10 shown in FIG. 1, a plurality of specified electrodes 42 of the circuit board 18 are connected via the signal paths to specified terminals of the die 14 and are further connected to a JTAG interface port. This is shown in the drawings as a simple, generic, interface and called out as “JTAG or other interface ports”. The JTAG implementation takes more than one physical path of connections. In the prior art shown in FIG. 2, five extra pins involved to implement JTAG would be more typical. In order to avoid this complexity, FIG. 1 is simplified. One skilled in the art will recognize that another appropriate interface port may be used instead of the JTAG interface port. Therefore, the desired signals of the dies 12 and 14 can be read from the JTAG interface port. Since the JTAG architecture is implemented, the dies 12 and 14 should include the test circuit. Moreover, integration of systems onto single die and multi-chip modules make observability and accessibility of system signals difficult.
What is needed is a method and device for measuring inter-chip signals by leading such signals to the outside of the module and measuring such signals with a conventional test and measurement instrument, recognizing that such methods and circuits will also lend themselves to applying stimulus signals to the DUT.