1. Field of the Invention
The present invention relates to circuit, system, and method for data transfer control for enhancing data bus utilization, and more particularly to a technique to enhance data bus utilization in an information processing system having a plurality of bus masters for carrying out data transfer through a data bus composed of a plurality of unit data buses by carrying out data transfer by split-controlling the data bus in unit data buses.
2. Description of the Background Art
A conventional information processing system for controlling data transfer by means of a plurality of data buses has an arrangement as shown in FIG. 1, for example. The system of FIG. 1 includes a central processing unit (CPU) 101 and a direct memory access controller (DMAC) 102 serving as bus masters, a memory 103, and a peripheral 104, which are interconnected to each other through a data bus 105 and an address bus 106. In FIG. 1, the CPU 101 and DMAC 102 serve as the bus masters and control a bus use (bus access).
In the foregoing system, as a first mechanism of bus arbitration of the data bus 105 using polling processing, the bus masters 101 and 102 control the bus use by using a req signal which is a bus use request signal from the DMAC 102 and a gnt signal which is a grant signal of bus use transfer. To be more specific, when the CPU 101 can release the data bus 105 in response to the bus use request signal (req signal) from the DMAC 102, the CPU 101 outputs the gnt signal to the DMAC 102, whereby the bus use is transferred to the DMAC 102 from the CPU 101. On the other hand, when the bus use is returned to the CPU 101, the gnt signal is inactivated, so that the CPU 101 acquires the bus use (bus access).
In the polling processing during the DMA data transfer in the system adopting the foregoing bus arbitration method, an I/O access from the CPU 101 frequently occurs during the DMA data transfer by the DMAC 102. In other words, an access (I/O access) to a register or the like retaining control information for the polling processing frequently occurs during the data transfer.
FIG. 2 is a timing chart showing timing of the polling processing during the DMA data transfer and an example of an occupancy state of one data bus composed of four unit data buses (the unit data buses have data widths of 8, 16, 32 bits, for example) in the foregoing system. In FIG. 2, the req signal and gnt signal are indicated as low-active signals (signals which are active in the low state).
With the I/O access necessary for the polling processing, the width of the register to be accessed is 16 bits or 32 bits, for example, which is far smaller than the width of the data bus. Further, in general, one byte or one word is sufficient for the control information of the polling processing retained in the register. On the other hand, a wider bus width is provided in the recent systems, and a bus having a width of 128 bits is not unusual.
However, in the conventional bus control system, the DMA data transfer is suspended while the I/O access is occurring for the polling processing. For example, when transfer data to be transferred by the I/O access is one byte, if the bus width is 128 bits, only 6% of the bus is utilized, and only 25% is utilized even when the transfer data is one word, thereby reducing the bus utilization and data transfer efficiency. Further, the larger the bandwidth of the data bus, the lower the data bus utilization becomes. In addition, when operating rates are different in the CPU and peripheral, the latency in the I/O access during the polling processing becomes larger. Thus, the I/O access for the polling processing occupies the data bus for a longer period, thereby reducing the data bus utilization further.
FIG. 3 is a second bus control mechanism of the information processing system. The system of FIG. 3 includes a central processing unit (CPU) 107 and a direct memory access controller (DMAC) 108 serving as bus masters, a memory 103 and a peripheral 104, which are interconnected to each other through a data bus 105 and an address bus 106. In this system, as a method of bus arbitration of the data bus 105, the bus arbitration is carried out by using a req signal which is a bus use request signal from the DMAC 108, a gnt signal which is a grant signal of bus use transfer, and a rel signal which is a bus release request signal from the CPU 107 for allowing the CPU 107 to temporarily acquire the bus use during the DMA data transfer.
In the system using the second bus arbitration mechanism, the data bus 105 cannot be released until the break of the DMA data transfer even when the bus release request signal (rel signal) from the CPU 107 is asserted, and therefore, the CPU 107 may stall.
FIG. 4 shows, as an example of such a stall, timing when the I/O access for the polling processing interrupts during the DMA data transfer and an example of an occupancy state of the data bus 105. In FIG. 4, the req signal, gnt signal, and rel signal are indicated as low-active signals. FIG. 4 shows that even when the CPU 107 asserts the release request signal (rel signal) of the data bus 105 to the DMAC 108 to allow the I/O access for the polling processing, the DMAC 108 does not release the data bus 105 until a break of the DMA transfer processing, thereby causing the CPU 107 to stall during that period.
As has been explained, in the conventional information processing system, wherein a plurality of bus masters carry out data transfer through the data bus, if the I/O access occurs for the polling processing or the like by the CPU during the DMA data transfer, the DMA data transfer and I/O access cannot be carried out simultaneously regardless of the fact that only a part of the data bus is necessary for the data transferred by the I/O access. For this reason, the data bus utilization is reduced.
In addition, when the I/O access for the polling processing or the like by the CPU occurs during the DMA data transfer, the data bus is not released until a break of the DMA data transfer, thereby posing a problem that the CPU stalls.