The present invention is directed, in general, to bipolar transistors and, more specifically, to a dual-bipolar-element transistor having a diminished voltage snap-back.
The electronic devices employed in paper media, automotive, digital audio, power management and many other applications include pinned components ranging from CMOS logic level up to 80 volts. However, output devices connected to high voltage pins are not always self-protecting. This presents the need for very high voltage, compact, ESD robust structures.
Typically, vertical npn-transistors play a key role in existing ESD solutions. Vertical npn-transistors better avoid current filamentation, and are generally more robust and smaller in size than alternative components. However, it is difficult to achieve the sustaining voltages required for many high voltage applications.
Those skilled in the art understand that most semiconductor bipolar devices, including bipolar transistors, experience a voltage snap-back. At low current the bipolar transistor exhibits a monotonically increasing I-V curve (voltage across the device increases as current through the device increase) until a xe2x80x9ctriggerxe2x80x9d voltage is reached, at which time the transistor collector-to-emitter voltage reverts or xe2x80x9csnaps-backxe2x80x9d to a sustaining voltage. For devices with high trigger voltage, the sustaining voltage can be as much as 50 volts less than the trigger voltage. While it is known that the trigger voltage may be successfully increased to a desired value, existing bipolar devices are not capable of achieving a sustaining voltage much higher than 20 volts, which is much lower than required for many of the applications discussed above. Moreover, while some proposed solutions may achieve higher sustaining voltages, these devices are significantly larger than desired, and many times impractical.
Other designs that achieve a higher sustaining voltage involve stacking two or more low voltage devices. However, these designs are larger than desired and normally exhibit more variation in sustaining voltage. Specifically, additional isolation structure is required among the stacked devices. The overall variation in sustaining voltage of the stacked devices increases variation in device performance.
Accordingly, what is needed in the art is an ESD robust device that exhibits a diminished voltage snap-back. What is further desired is an ESD robust device that is compact and otherwise overcomes the above-discussed disadvantages of the prior art.
To address the above-discussed deficiencies of the prior art, the present invention provides an ESD robust bipolar transistor having first and second bipolar elements, wherein a first trigger voltage of the first bipolar element is proximate a second sustaining voltage of the second bipolar element. The first and second bipolar elements interact to transfer current therebetween. More specifically, at low current, the first bipolar element conducts most of the current. However, as current increases and the corresponding voltage approaches the first trigger voltage of the first bipolar element, an increasing portion of the current is transferred to the second bipolar element. As current continues to increase, it is primarily conducted by the second bipolar element at the second sustaining voltage of the second bipolar element.
Thus, the present invention introduces the concept of allowing current in an ESD robust device to continually increase without a significant change in voltage across the device. Accordingly, the ESD robust bipolar transistor of the present invention may be employed in applications requiring a high sustaining voltage, but is not as susceptible (if at all) to latch-up or other problems inherent to devices that exhibit a non-monotonic curve.
In one embodiment of the present invention, the first bipolar element includes a first base, a first emitter and a first collector, and the second bipolar element includes a second base, a second emitter and a second collector. The first base is coupled to the second base, and the first collector is coupled to the second collector. The transistor also includes an emitter resistor coupling the first and second emitters and a base resistor coupling the second emitter to the first and second bases. The emitter resistor operates to transfer current from the first bipolar element to the second bipolar element at a predetermined current or voltage. The base resistor operates to initiate injection from the emitter which helps modulate transistor conductivity. This helps reduce the difference between breakdown and trigger voltage. The base resistor also aids in the regulation of current sharing among the first and second bipolar devices.
In one embodiment, the first trigger voltage is above about 40 volts, although the present invention is not limited to bipolar transistor devices or elements having any particular trigger voltage. For example, the first trigger voltage may range between 5 volts and 80 volts.
In one embodiment, the proximity of the first trigger voltage and the second sustaining voltage may be about 5 volts. Of course, the present invention is not limited to a specific separation between the first trigger voltage and the second sustaining voltage. For example, in some embodiments the first trigger voltage and the second sustaining voltage may be the same. In other embodiments, the first trigger voltage may be up to 20 volts different than the second sustaining voltage. The first trigger voltage may also be less than or greater than the second sustaining voltage.
In one embodiment, the ESD robust bipolar transistor may be coupled in parallel to a circuit cell. In this manner, any voltage greater than the first trigger voltage may cause the ESD cell to activate and conduct high current until the ESD event ceases and the circuit cell may again continue operation.
The present invention also provides a method of manufacturing an ESD robust bipolar transistor. The method includes configuring a first bipolar element to have a first trigger voltage and configuring a second bipolar element to have a second sustaining voltage proximate the first trigger voltage. Those skilled in the art will understand that the method of the present invention may include additional manufacturing steps.
The present invention also provides an ESD robust bipolar transistor that includes a first bipolar element region formed in a first substrate and a second bipolar element region formed in a second substrate, wherein the first and second substrates may comprises portions of a common substrate. The first bipolar element region includes a first collector region located in the first substrate, a first base region located adjacent the first collector region, and a first emitter region located in the first base region. The second bipolar element region includes a second collector region located in the second substrate, a second base region located adjacent the second collector region, and a second emitter region located in the second base region. The ESD robust bipolar transistor also includes an emitter resistor coupling the first and second emitter regions and a base resistor coupling the second emitter region to the first and second base regions.
The foregoing has outlined preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention.