1. Field of the Invention
The present invention relates to a technology for supporting verification of a large-scale integration (LSI).
2. Description of the Related Art
In LSI design, a verification work of verifying whether an LSI works normally is essential. While the verification work is important to maintain high quality especially for the LSI for which a larger scale, a high performance, a higher speed, and lower power consumption are required, enhanced work efficiency by shortening a design period has conventionally been demanded.
Especially in recent years, software and hardware are implemented on a single LSI and a system on chip (SoC) including not only conventional single-function hardware with an application specific integrated circuit (ASIC) but also software is now a mainstream of LSI. Moreover, since the functions conventionally realized by application software such as moving picture experts group (MPEG) and joint photographic experts group (JPEG) are now realized by hardware, functions of LSI are becoming complicated.
FIG. 38 is a flowchart of a conventional LSI development process. In FIG. 38, steps S3801 to S38805 are a design flow and steps S3806 to S3809 are a verification flow of verifying designed LSI.
In the design flow, a conceptual designing is made at step S3801. In the conceptual designing, a designer prepares a requirement specification 3810 in natural language based on a design request from a customer or receives the requirement specification 3810 described in natural language from the customer.
Functional designing is made at step S3802. In the functional designing, based on described contents of the requirement specification 3810, an LSI to be designed is divided into functional blocks and a functional specification 3820 describing contents of each functional black is prepared.
At step S3803, structural designing is conducted. In the structural designing, based on the functional specification 3820, hardware designing is carried out and a structural specification 3830 is prepared. Specifically, the structural designing is the designing to find out what kind of architecture should be introduced to realize the functions described in the functional specification 3820.
For example, out of functional blocks, architecture of a functional block is realized by software, architecture of a functional block is realized by purchasing intellectual property (IP), architecture of a functional block is prepared by the designer, and architecture of a functional block is realized by an underbus.
At step S3804, unit designing is conducted. In the unit designing, by dividing each hardware module described in the structural specification 3830 into a plurality of modules and by detail-designing of such modules, a unit specification 3840 is prepared.
At step S3805, implementation is conducted. Implementation is conducted using a timing chart of an interface and using a hardware description language (HDL) of a register transfer level (RTL) 3850 to be ultimately designed, considering internal logics.
At step S3806, unit verification is conducted. In the unit verification, the verification of the unit specification for each unit designed at the unit designing, namely, debugging, is conducted according to unit verification items 3860.
At step S3807, connection verification is conducted. In the connection verification, interfaces of respective units verified at the unit verification are connected and verification is made as to whether thus interconnected units work normally, according to connection verification At step S3808, function verification is conduced. In the function verification, verification is made as to whether functional requirements of the system to be designed are satisfied, according to function verification items 3880.
Finally, at step S3809, actual machine verification is conducted. In the actual machine verification, LSI is actually implemented on a chip using the RTL 3850 and it is verified whether the LSI actually works. Determination is made as to whether the requirement specification 3810 from the customer satisfies requirement verification items 3890.
In the above design processing, however, verification of LSI (steps S3806 to S3809) can not be made unless the implementation (step S3805) is made.
This leads to a problem that, when an error is made due to an error of the specification, ambiguity of description, or misinterpretation by a designer at any upstream step of the design flow, the error is accumulated at steps subsequent to such step.
In the structural designing, architecture was determined on the desk and there was no method to ascertain its appropriateness. Therefore, an increase in development risk could result in failure of a development project, to the loss of time and manpower spent in the development.
A special simulator (tools from electronic design automation (EDA) vendors such as VCS and NC-Sim) is required for applying simulation to HDL of the RTL 3850, and a slow simulation speed of the simulator leads to problems of decreased verification efficiency and a longer design period. Especially when an LSI to be designed is of a large scale, occasionally the verification work could not be completed within a predetermined period because of a bottleneck of the slow simulation speed.
On the other hand, it is conceivable to increase the simulation speed by introducing an emulator capable of working at a speed thousands times as fast as the simulator, but the emulator is very expensive and increases verification expenses, and it is difficult to build the environment and debugging is difficult at the time of occurrence of a problem, resulting in increased verification period and a longer design period.