Dynamic Random Access Memory devices in the present silicon based technology are volatile because periodic refresh of the stored information is necessary and the information is lost when the memory cells are no longer connected to a power supply.
Flash memory provides the complementary functions in modern electronic systems. Flash memory uses a floating gate which is charged or discharged through the surrounding insulating material to change the logic state. It is a read-only memory (ROM), because the information writing takes too long and is limited to a certain number of writing cycles, so it cannot be used for RAM applications. However, it provides a nonvolatile storage of the information, which is kept even when any power is disconnected from the memory cells. Flash memory is also dependent on processing and in practice there is a need to adjust for processing by having a micro processor on the same chip with built in corrections to compensate for these process fluctuations.
There have been attempts to form non volatile random access memory (NVRAM) devices—a memory cell with access characteristics of silicon RAMs and with retention times of silicon ROMs (flash memories)—and U.S. Pat. No. 6,373,095 is an example.
Another challenge in developing memory devices is to enable an increase in memory capacity, and one way of achieving this is to reduce the cell area (8F2 in current DRAMs). F is the minimum feature (the minimum line width that can be achieved by a certain technology), and 8F2 shows that the structure of state-of-the-art memory cells is such that every cell takes an area of 8F2. This challenge has been outlined by S. Okhonin, M. Nagoga, J. M. Sallese and P Fazan (IEEE Electron Device letters Vol 23 No 2 February 2002). A limiting factor in down scaling the feature size in the case of one transistor one capacitor (1T1C) cell used in DRAMs is that memory capacitance is dependent on F. Flash provides higher memory capacities because it uses a smaller one transistor (1T) cell with the possibility of more than 2 logic levels per cell. Still, there is a limit to the down scaling of the feature size, set by the need to accelerate electrons to energies that are sufficient for injection into the floating gate. A further factor is set by the minimum thickness of the insulator, which is subject to fatigue as the insulator thickness is reduced.
Silicon Carbide is not widely used to produce semiconductor devices which are mostly fabricated in silicon. Silicon carbide has been proposed for use in transistor applications but not for memory devices in U.S. Pat. Nos. 5,831,288, 6,218,254, and 6,281,521.
U.S. Pat. No. 6,365,919 discloses a Silicon carbide junction field effect transistor (JFET).
U.S. Pat. No. 5,465,249 discloses two possible implementations of the 1T1C cell in silicon carbide to achieve a nonvolatile RAM (NVRAM) with fast writing and virtually unlimited number of writing cycles (dynamic NVRAM). The difference between the two implementations is in the type of the transistor: SiC bipolar junction transistor (BJT) in one case and SiC metal-oxide-semiconductor field-effect transistor (MOSFET) in the other case. In both cases, the capacitor is implemented as metal-oxide-semiconductor (MOS) capacitor on SiC. Being 1T1C cell, the memory is read by sensing capacitance.
U.S. Pat. No. 5,510,630 discloses a SiC based 1T1C cell with a specific structure for the MOSFET (an accumulation-type MOSFET) and a stacked polysilicon-dielectric-metal capacitor.
U.S. Pat. Nos. 5,801,401, 5,989,958 and 6,166,401 disclose a ROM device using a silicon carbide floating gate.
It is an object of this invention to provide a dynamic NVRAM that is capable of having a small feature size and avoids the disadvantages of flash memory. A further object is to provide a cell that can enable more aggressive down scaling and significant reductions in power dissipation. This of course will also increase the density of memory storage.