1. Field of the Invention
The present invention relates to a multi-chip package on which a plurality of chips such as a memory device chip and a logic device chip are mounted, and, more particularly, to a novel structure which can implement fast transfer of data signals between both types of chips.
2. Description of the Related Art
A logic device, such as a microcontroller or a memory controller, and a memory device like a DRAM are connected together by a bus line, whereby a data signal like a stored data or an address is sent to the memory device from the logic device, and a data signal stored in the memory device is sent to the logic device.
FIG. 25 shows a conventional structure which has a logic device connected to a memory device. In FIG. 25, a logic device 10 and a memory device 20 are connected together by bus lines 5, so that a data signal is transferred at a high speed in synchronism with a clock. Recently, the speed of transfer of data signals between the logic device 10 and the memory device 20 is getting faster and faster. Increasing the data transfer rate requires an increase in the number of bus lines or an increase in the clock frequency for data transfer. The former scheme increases the bus-lines occupying area on the board on which both devices are mounted, thereby increasing the dissipation power for driving the bus lines. The latter scheme is inadequate because it suffers a limitation to the transfer performance of the bus lines themselves as well as the device speed itself.
FIG. 26 shows the structure of a system LSI which has a logic section 2 and a memory section 3 embedded in a single chip. This structure can permit an improvement on the speed of data transfer between the logic section 2 and the memory section 3. Optimization of the logic section 2 and the memory section 3 however requires that both sections should be formed by separate processes, which together with the one-chip structure would increase the manufacturing cost.
Although designing a logic device and a memory device on a single chip is advantageous in improving the transfer speed, however since it increases the manufacturing cost, it is not practical. A promising method therefore is to construct a logic device and a memory device on separate chips and then to design those chips into a multi-chip structure.
But, any adequate means for accomplishing fast transfer of data signals between such two chips of the multi-chip structure has not been proposed so far. In particular, no structure which outputs a data signal from one chip in synchronism with a predetermined clock and allows the other chip to receive the data signal and transfer it inside has been proposed yet.