The present application relates generally to an improved data processing apparatus and method and more specifically to an apparatus and method for improving the performance and efficiency of multi-core processor architecture by enabling effective collaboration of processor cores.
Three-dimensional integration provides performance improvement for microprocessor architectures through the increased interconnectivity and higher packaging density. Through silicon via technology allows low latency and high bandwidth communication between the layers in a 3D stack. As the TSV scaling continues, splitting the computation onto multiple strata becomes possible at a finer grain (such as processor core, functional unit or macro level).
However, splitting logic onto multiple silicon layers presents various challenges such as:                Thermal problems due to increased power density;        Timing and functionality problems—as a result of process variability among different dies;        Yield problems, since any faulty layer in the stack is likely to impact the functionality of the entire stack in fine-grain logic stacking.        