1. Technical Field
The present invention relates in general to the field of computers, and in particular to clustered shared-memory multiprocessor systems. More particularly, the present invention relates to an improved region coherence array having hint bits associated with processors in a clustered shared-memory multiprocessor system.
2. Description of the Related Art
To reduce global bandwidth requirements within a computer system, many modern shared-memory multiprocessor systems are clustered. The processors are divided into groups called symmetric multiprocessing nodes (SMP nodes), such that processors within the same SMP node may share a physical cabinet, a circuit board, a multi-chip module, or a chip, thereby enabling low-latency, high-bandwidth communication between processors in the same SMP node. Two-level cache coherence protocols exploit this clustering configuration to conserve global bandwidth by first broadcasting memory requests for a line of data from a processor to the local SMP node, and only sending memory requests to other SMP nodes if necessary (e.g., if it is determined from the responses to the first broadcast that the requested line is not cached on the local SMP node). While this type of two-level cache coherence protocol reduces the computer system global bandwidth requirements, memory requests that must eventually be broadcast to other SMP nodes are delayed by the checking of the local SMP node first for the requested line, causing the computer system to consume more SMP node bandwidth and power. It is important for performance, scalability, and power consumption to first send memory requests to the appropriate portion of the shared-memory computer system where the cached data is most likely to be found.
Several Coarse-Grain Coherence Tracking (CGCT) methods which include use of Region Coherence Arrays (RCAs) to avoid unnecessary broadcasts of memory requests in a broadcast-based, shared-memory multiprocessor system have been discussed. The RCAs are hardware structures that track the coherence status of data at a coarse granularity. The RCAs exploit spatial locality beyond the cache line and temporal locality beyond the capacity of the cache hierarchy. However, the known CGCT methods are solely targeted for multiprocessor systems that are flat (not clustered)—that is, there is a single, flat interconnect and no multiple levels of interconnect hierarchy. In this type of system, the problem is simply determining whether or not to broadcast a memory request, which memory request is broadcast to the entire flat system. The system does not allow an optional broadcast of memory requests to only a specified portion of a non-clustered system.
Further, some proposed region protocol methods for clustered shared-memory multiprocessor systems identify only where data might only possibly be found in the system, and do not answer the important question of where to first send memory requests in the event that multiple region coherence state bits of an RCA are set. Under these methods, when multiple region coherence state bits of an RCA are set which indicate that cached copies of lines from a region of memory are detected at multiple levels of the interconnect hierarchy, no optimal routing of requests occurs. Instead, a policy decision must be made to determine where to first send requests for a line of data (e.g., send requests first to the highest system interconnect level, to reduce latency, or to send requests first to the lowest system interconnect level to conserve bandwidth, etc.).
Thus, there is a need for a region protocol which utilizes RCAs having bits that predict which part of the system can most efficiently satisfy a request for a line in the region so that requests may be automatically routed and sent first sent to the part of the system indicated by the bits.