1. Field of the Invention
This invention pertains to improvements in memory cell array layouts and designs, and more particularly to improvements in memory cell bit line structures, and still more particularly to improvements in twisted bit line structures and methods for making same.
2. Relevant Background
An electrical schematic diagram of a portion 10 of a memory array in which the bit line structure and method for making it in which the invention may be practiced is shown in FIG. 1. As is well known, the memory array includes a number of word lines w1 . . . w6, and complementary bit line pairs b1, b2, b2, b3, and so on.
Sensing amplifiers 12, 12xe2x80x2, 12xe2x80x3, . . . are provided in association with each bit line pair. As is known, when noise, denoted by the arrows 14xe2x80x9414 appears across a pair of bit of lines, such as bit lines b2 and b2, the noise may be conducted to the sensing amplifier 12xe2x80x2, and may erroneously be interpreted as data, lack of data, or undesirably modified data.
It is well known that by twisting bit line structures in integrated circuits, such as memory cells, or the like, noise that may be induced into the bit line structure can be effectively canceled. Various bit line layouts are shown in FIG. 2. For example, in FIG. 2a, a bit line arrangement is shown in which no twist exists within the bit line pairs. This is similar to the bit line arrangement of the memory array of FIG. 1. In FIG. 2b, a bit line arrangement is shown in which the twist is provided in a bit line pair located between two untwisted bit line pairs. This twist arrangement results in significantly better noise cancellation than the untwisted layout of FIG. 2a, but does not provide perfect noise cancellation. In FIG. 2c, a bit line arrangement is shown in which the twist is provided in each bit line pair, with the twist arranged in a staggered relationship with respect to each other. This bit line arrangement provides the best noise cancellation of the three examples shown in FIG. 2.
More particularly, the physical layout of a typical bit line twist structure is shown in FIG. 3. As shown, bit line b1 and b3 are continuous, but complementary bit lines b2 and b2 are interconnected with a twist structure 18. In order to accomplish the twist, bit lines b2 and b2 are made discontinuous so that the respective ends of the bit line b2 and bit line b2 can be interconnected.
Thus, a diagonal conducting trace 20 is provided between bit line b2 on the right and bit line b2 on the left in a continuous pattern. All of the bit lines and the diagonal interconnect 20 are formed on a single level, for example, on a dielectric layer of an underlying substrate (not shown). In order to connect the left side of bit line b2 to the right side of bit line b2, an upper or lower level diagonal interconnect 22 is employed. The interconnect 22 is connected to the associated bit line segments of b2 and b2 through vias 24 and 26, and is formed in a vertical location separated from the bit line segments by a dielectric layer (not shown). Typically the interconnect 22 is formed above the level of the bit line traces, but, as mentioned, can be formed at a lower level.
Thus, conventionally, bit line structures are laid out on a semiconductor substrate by a number of parallel conductive traces. At pre-determined locations, the traces are formed in a discontinuous manner, with a diagonal interconnection made between the first set of the conductive traces and, on a different integrated circuit level, with a second diagonal interconnection between the second trace portions, with connections made to the traces by vias or other inter-level interconnections.
Thus, in the past, bit line construction has been accomplished by depositing a number of the conductive traces onto a semiconductor substrate, with spaced apart diagonal conductors formed between selected adjacent bit lines and with discontinuities in the respective lines that will subsequently be interconnected. After an insulating layer has been formed over the bit line structure, vias are formed through the insulating layer to the surfaces of the discontinuous bit lines. Thereafter, a diagonal conductor segment is formed to interconnect the discontinuous bit lines through the vias. Of course, the vertical order and placement of the diagonal interconnection may be varied, with the diagonal interconnection being first formed and the bit line structure being formed over an insulating layer in which are properly located vias may have been formed.
Thus, in order to construct twisted bit lines, a first bit line is typically constructed at an original level, and portions or segments of a second bitline are constructed parallel to the first bit line. However, in order for the second and bit line to be constructed without shorting to the first as it crosses thereover, an interconnection must be provided that is insulated from the first bit line. Such interconnection is generally constructed to be located either over or under the first and separated therefrom by a suitable insulation layer; typically, the interconnections of the second bit line are located at an upper level that is separated and insulated from the first bit line.
It should be noted that in the past, in the formation of the bitlines, a reticle has been used in which a number of opaque parallel line segments are formed on a glass substrate. The opaque parallel line segments may be formed, for example, of chromium or other material on the glass or other transparent substrate. The reticle is placed on or adjacent a surface of a substrate on which a photosensitive material has been deposited. Light is passed through the reticle, and is masked by the opaque line segments formed thereon but allowed to pass by the adjacent transparent line segments, to expose unmasked portions of the photosensitive material to the light. This causes a chemical change in the material that allows selected portions (for example, the light exposed portions) of the material to be removed.
However, since the typical scales patterned on wafers are comparable to the wave length of the light used in lithography equipment, the resulting pattern on the photosensitive material on the substrate therefore may have blurred or fuzzy edge definitions. When the photo sensitive material is removed during subsequent processing steps, the blurred or fuzzy edge definition may result in an inaccurate patterning, which, in turn, may result in unintended contact between adjacent memory array structures, such as the bit lines of concern herein.
To address this problem, a so-called xe2x80x9cLevensonxe2x80x9d reticle has been proposed in which selected portions of the glass substrate between masked elements are etched. The etched regions are, referred to as xe2x80x9cxcfx80xe2x80x9d regions, or xe2x80x9cphases,xe2x80x9d and the unetched regions are referred to as xe2x80x9c0xe2x80x9d regions, or xe2x80x9cphasesxe2x80x9d. By careful selection of the xe2x80x9cxcfx80xe2x80x9d and xe2x80x9c0xe2x80x9d regions, a pattern can be produced onto a semiconductor device having known semiconductor processing layers thereon which have sharply defined edges. Since the etched portions of the reticle are lower than the unetched portions, light passing through the reticle has a smaller light path, and therefore causing interference patterns, on the photo resist or substrate being patterned. This results in significantly better integrated circuit structure formation. In fact, it has been estimated that a Levenson reticle can produce line patterns with approximately twice the resolution of that of a conventional reticle.
The process by which the bit lines are formed includes the exposure of a photo sensitive layer (not shown) that has been deposited or formed onto the surface of the substrate on which the bit lines are to be constructed. In the past, a reticle mask 30 has been provided, as shown in FIG. 4a. The reticle mask includes a number of mask elements 32 formed on a surface 30 of a glass substrate 36. The mask elements 32 may be, for example, metal, such as chromium or the like. Typical scales on wafers are comparable to the wave length of the light used in lithography equipment. As a result, light that passes through the inter-spaces between the mask elements 32 produces interference patterns on the photo sensitive substrate when it is exposed. A typical pattern from a conventional reticle mask is shown in FIG. 4b. This results in imprecise line patterns, which can lead to shorting between adjacent bit line structures, especially as feature sizes in integrated circuit devices becomes smaller and smaller.
In light of the above, it is, therefore, an object of the invention to provide an improved method for making an improved twisted bit line.
It is another object of the invention to provide a method for constructing twisted bit lines using a xe2x80x9cLevensonxe2x80x9d mask, in which bit line diagonal connections can be made between bit line structures according to the Levenson phase shift layout rules.
It is yet another object of the invention to provide an improved bit line structure.
It is still another object of the invention to provide an improved bit line structure of the type described that may be more reliably constructed to avoid inadvertent shorts or contacts to adjoining integrated circuit structures.
These and other objects, features and advantages of the invention will be apparent to those skilled in the art from the following detailed description of the invention, when read in conjunction with the accompanying drawings and appended claims.
Thus, according tot present invention, a method is presented for making twisted bit line structures in an integrated circuit, such as an integrated circuit memory chip, or the like, using two Levenson phase shift rules: 1) structures with different phase must not touch; 2) and geometries, separated by the minimum design rule for the integrated circuit under consideration, should be constructed with different phases, Following these rules, thereover, and in accordance with a preferred embodiment of the present invention, a method is presented for interconnecting selected bit lines to accomplish a twisted bit line structure, by providing an interconnection between bit line segments that are untwisted in locations adjacent to locations at which the twist is provided in an adjacent bit line pair. Thus, if a series of bit line traces are formed with alternate xe2x80x9cxcfx80xe2x80x9d and xe2x80x9c0xe2x80x9d phases, interconnections can be made at upper or lower integrated circuit structural levels of both the twisted and untwisted bit line traces, to accomplish the twisted bit line structure.
In accordance with a broad aspect of the invention, therefore, a method for constructing a twisted bit line structure in an integrated memory circuit is presented. The method includes forming bit line traces on an integrated circuit substrate using phase shift lithography techniques. Using these techniques, the bit line traces are arranged with a plurality of substantially parallel bit line trace segments with discontinuous regions between segments of an interior pair of traces, with each xe2x80x9cphase xcfx80xe2x80x9d bit line trace being adjacent a xe2x80x9cphase 0xe2x80x9d bit line trace along two perpendicular axes. Twist connections are formed between first and second segments of a center pair of said bit line trace segments with each interconnection being formed at a different level from a level at which the bit line traces are formed.
According to another broad aspect of the invention, a twisted bit line structure for an integrated memory circuit is presented. The structure includes a plurality of bit line trace segments. At least a pair of the untwisted bit line trace segments are located adjacent and substantially parallel to an adjacent twisted bit line pair of bit line trace segments. Interconnections are established between discontinuous portions of the bit lines segments of the twisted bit line segments, the interconnection being contained on different levels from a level on which the bit line segments are contained.