The present invention relates to a mask data verification apparatus creating and verifying mask data from a design layout, a design layout verification apparatus verifying a design layout generated from a logic circuit, a method thereof, and a computer program thereof.
Recently, vertically integrated semiconductor manufacturers as well as fabless companies come to utilize foundries in the manufacturing field in order to suppress investment costs for development and manufacture of advanced processes. Exchanging useful information with each other is important to utilize foundries.
On the other hand, semiconductor devices are increasingly requested to be highly functional and versatile. Processes are refined accordingly. A process node finer than 180 nm must use the OPC (Optical Proximity Correction). The OPC deforms a photomask shape and thereby corrects the pattern shape formed on a wafer. The result directly affects manufacturing yield.
The OPC may be considered a function that uses a design layout as input and a photomask shape as output. While various types of design layouts are available, the function specification (hereinafter referred to as OPC specification) is optimized for a set of design layouts that may be input candidates. That is, a manufacturing party (such as foundry) awaits a design layout supplied from a designing party. The design layout contains an OPC specification previously optimized for a set of design layouts expected in the manufacturer.
There may be a case where a design layout unexpected in the manufacturing party is supplied from the designing party and is likely to affect manufacturing yield. In such a case, the manufacturing party reviews the OPC specification. During the verification, the manufacturing party searches for an optimal specification, examines an adverse effect on the other design layouts due to specification changes, and finally re-processes normal OPC and post-OPC verification.
The OPC process and the verification of its result are time-consuming. If a problem occurs, a general solution may be to postpone the manufacturing plan and refine the OPC specification or to tolerate a decrease in the manufacturing yield and keep the OPC specification unchanged.
A recent trend is to shorten the life cycle of final products using semiconductor devices. There is a demand to shorten a period from supply of a design layout from the designing party to completion of the semiconductor device manufacturing.
To manufacture semiconductor devices, the manufacturing party is supplied with a design layout from the designing party and performs OPC processes, photomask fabrication, wafer fabrication, inspection, and mounting. A considerable business loss might result from depending on the design layout and frequently revising the OPC specification. The related technologies are disclosed in patent documents 1 through 5 and non-patent document 1.
Patent document 1 aims at providing a semiconductor device, a basic cell library, a method of manufacturing the semiconductor device, a method of forming the basic cell library, and a mask in order to be able to decrease the amount of polydata corrected by the OPC, shorten the CAD processing time, perform the OPC on each cell, and shorten the turnaround time for products. A dummy wiring pattern is previously formed around a basic cell stored in the basic cell library. It is necessary to settle a distance between a polysilicon gate used for circuits in the basic cell and polysilicon wiring for the dummy wiring pattern adjacent to the polysilicon gate. The distance can be settled within the cell. As a result, this enables to estimate the magnitude of poly-width variation due to the optical proximity for all the polysilicon gates in the basic cell. The OPC is performed on a mask that corrects the gate width based on the poly-width variation. An OPC value can be settled only within the cell.
Patent document 2 aims at saving time needed for an optical proximity correction (OPC) process during the mask pattern design. OPC-preprocessed cells are laid out to form a mask pattern. The correction amount of the OPC is then fine-tuned. Calculation for the fine-tuning is performed only on an overlap region between an adjustable region of each cell and surrounding regions of the other adjacent cells. This enables to decrease a range of fine-tuning an OPC diagram, that is, an area of the region that needs the calculation. A mask pattern can be designed efficiently. This enables to greatly reduce the processing time and costs for the mask pattern design.
Patent document 3 aims at estimating distortion of a pattern formed during semiconductor manufacture and detecting a portion causing pattern distortion greater than or equal to a tolerance. The semiconductor manufacture process estimates a finish pattern that is formed based on a design layout pattern. An outline of the estimated finish pattern is shaped into a polygon. An inspection reference pattern is created based on the design layout pattern. The estimated polygonal finish pattern is compared with the inspection reference pattern to detect a distortion of the estimated finish pattern. The detected pattern distortion is identified in accordance with importance degrees. In addition, the pattern contrast is verified.
Patent document 4 aims at providing a pattern distortion correction apparatus that corrects a layout pattern distortion in consideration of a process margin as well as an edge shift amount. The pattern distortion correction apparatus includes a finish pattern estimation portion, an edge shift amount measurement portion, a process margin measurement portion, a measurement result determination portion, and a layout pattern temporary-correction portion. The finish pattern estimation portion estimates a finish pattern for the layout pattern. The edge shift amount measurement portion measures an edge shift amount equivalent to a difference between the estimated finish pattern and the reference pattern. The process margin measurement portion measures a process margin for the estimated finish pattern. The measurement result determination portion determines whether the measured edge shift amount and the measured process margin satisfy determination criteria. The layout pattern temporary-correction portion corrects the layout pattern so as to satisfy the determination criteria based on a determination result from the measurement result determination portion.
Patent document 5 aims at fast and efficiently verifying conformity to intended semiconductor device layout and surrounding situations in consideration of increasing manufacture variations due to fine design patterns or high-density circuits in semiconductor integrated circuit manufacturing processes. The condition input process supplies a layout pattern division condition containing multiple specific layout patterns whose circuit characteristics need to be identical. The data division process divides input mask layout design data into multiple layout pattern groups in accordance with the layout pattern division condition. The reference pattern selection process selects a reference pattern as the pattern matching reference for each of the divided layout pattern groups. The pattern matching process compares each layout pattern in each of the layout pattern groups with the reference pattern.
Non-patent document 1 concerns the method that uses pattern matching, for example, to detect in advance a design layout pattern likely to be problematic during a manufacturing stage and corrects the design layout pattern.
Patent document 1: Japanese Unexamined Patent Publication No. Hei 10(1998)-032253
Patent document 2: WO 2008/023660
Patent document 3: Japanese Unexamined Patent Publication No. 2000-032253
Patent document 4: Japanese Unexamined Patent Publication No. 2001-182921
Patent document 5: Japanese Unexamined Patent Publication No. 2010-020553
Non-patent document 1: J. H. Kang et al., “Combination of rule and pattern based lithography unfriendly pattern detection in OPC flow”, Proc. of SPIE Vol. 7122 (2008)