Significant technological innovation in methods of testing current digital LSIs has been made, and the capability to automatically generate test circuits for testing the chips thereof or test patterns, which are sequences of signals for performing testing, has been achieved. That is, digital LSIs are configured to handle processing of binary signals of “0”s and “1”s, and automation has been carried out using techniques such as scan path testing since digital LSIs are easier to test than analog LSIs and it is possible to simplify fault models by limiting the testing to single stuck-at faults.
Here, the term scan path testing is a technique including providing a path (scan path) in which flip-flops are serially connected and causing the flip-flops to hold arbitrary values through this scan path or reading values held in the flip-flops through the scan path to examine the state of the circuit. In this scan path testing, all the flip-flops that are usually used are connected in series in a test mode so that arbitrary data can be set in all the flip-flops from outside (improvement in controllability). Then, next, the mode is switched to a normal mode, in which the data of the flip-flops, which has been set from outside, is added to internal combinational gates of the LSI, and thereafter one clock is added, thus allowing the outputs of these gates to be captured by the same flip-flop. Finally, the scan-out operation is performed in the test mode again (improvement in observability), and a signal of an internal gate is output to outside the LSI so that it is determined whether the gate output is normal or not. This operation is repeated until the desired fault coverage is achieved. In this manner, examples in which scan path testing is used for the testing of digital LSIs are widely known (see, for example, Japanese Patent No. 2550521 (FIG. 5)).
In contrast to this, since analog LSIs handle consecutive analog values, the complexity of processing increases. Even at the present time, sufficient failure detection algorithms are not available, and automation is delayed. In analog signal processing, in general, no flip-flops are used, and an alternating current or direct current analog signal is added to an LSI. For example, amplifiers, filters, and the like can be comparatively easily controlled by directly adding signals of various levels or frequencies to the LSI. That is, in many of circuits in analog LSIs, the potentials of nodes etc., are unambiguously determined and, in many cases, controllability is high. On the other hand, for example, if it is envisaged that a filter exists inside the LSI, since a desired signal is comparatively easily added to the input of the filter in the manner described above, the output thereof is input to the subsequent signal processing circuit. In this case, it is necessary to provide a special built-in test circuit to observe the output of the filter. That is, it is general that analog LSIs have low observability.
Accordingly, it is useful in terms of improving observability to understand internal signals or potentials in analog LSIs. In addition, it is useful for test efficiency to further increase controllability.
The present invention has been made in view of such a situation, and an object thereof is to increase observability and controllability in a test of an analog LSI and further to achieve overall synchronization.