This invention relates to the field of memory readout circuitry and techniques, and more particularly to circuits and techniques for readback of data stored in multiphase memory arrays. Such arrays achieve higher speeds by storing sequential bytes or words of data in different memory portions on different phases of a system clock.
The effective writing speed of a memory system may be increased by the use of multiple memories. In such a memory system the high speed stream of input data is treated as if it were comprised of several sets of data multiplexed together. This stream of input data is demultiplexed by the memory write circuitry so that only every n-th bit of data is sent to the same memory portion, with successive bits being sent to other memories within a gang of multiple memories at a faster rate than any one of the individual memories could handle the data.
For example, if an input data stream consisted of four bits of data, ABCD, and two memories were being employed to double the maximum speed attainable, bit A would go to memory 1, bit B to memory 2, bit C to memory 1, and bit D to memory 2.
Such a multiple memory may operate off of different phases or edges of the same clock. Thus, in the preceding example, memory 1 could run off the rising edge of a system clock while memory 2 was running off the falling edge of the same clock. Alternatively, both memories could be clocked by a clock and its complement, using the same edge.
In such a system, both memories can be operated at or near their individual maximum speeds, permitting data which appears at the input to the system to be stored at a rate which is a multiple of the speed of the individual memories. In our example, with two memories alternating to receive one stream of input data, the speed of the memory system as a whole is twice that of the individual memories themselves.
Once data has been demultiplexed into these separate memories, it must be multiplexed back together in order to be meaningfully read out. In some environments it is necessary to maximize reading-out speed as well as writing-in speed. In other applications, such as that in which the instant invention is used, minimizing the number of readback lines, not the time to perform a readback is the most important design goal.
What is desired is a circuit that will require a minimum of total readback lines and a limited number of components, and which will allow the original stream of input data to be reconstructed as it is read out of the multiphase memory array.