FIG. 1 illustrates a conventional pixel 100 coupled via interconnect 125 to a conventional pixel reading circuit 150. The pixel 100 includes a photodiode 101, transistors 110-114, and nodes A, B, E, and P. Additionally, control signals AB, RESET, TX, and ROW can be respectively applied to the antiblooming transistor 113, reset transistor 110, transfer transistor 114, and row select transistor 112. Node A is connected to a voltage source for the pixel 100. Node E is a charge storage node. Node P is a charge accumulation node of the photodiode 101. The outputs produced by the pixel 100 are made available at node B. These outputs include a reset output voltage Vrst and a pixel image signal output voltage Vsig. The pixel reading circuit 150 includes a photo signal sample-and-hold (S/H) circuit SHS 151 for sampling and holding the Vsig output voltage, a reset signal S/H circuit SHR 152 for sampling and holding the Vrst output voltage, an amplifier 153, and nodes C and D. As illustrated, interconnect 125 couples the output of the pixel signal at node B to the input of the pixel reading signal at node C.
As is well known, the pixel 100 is operated by first asserting the RESET control signal while the photodiode 101 is not exposed to light to cause a reset voltage to be applied to charge stage node E and the pixel 100 to output a reset signal Vrst through transistors 111 and 112. The RESET controls signal is then deasserted and the photodiode 101 is exposed to light during a charge integration period, i.e., an exposure period. Upon completion of the integration, the accumulated charge is transferred to storage node E by transistor 114 causing the pixel to output a photo signal Vsig through transistors 111 and 112. Both the reset signal Vrst and the photo signal Vsig are output at node B, albeit at different times. During the exposure, the photodiode 101 accumulates charge at node P based on the amount of incident light and the exposure time, which is transferred by transistor 114 to storage node E.
The reset signal Vrst is sampled and held by the reset signal S/H circuit 152, while the photo signal Vsig is sampled and held by the photo signal S/H circuit 151. The sampled and held photo and reset signals are supplied as inputs to differential amplifier 153, and the resulting amplified output signal is available at node D. Transitor 113 is an antiblooming transistor which operates in response to control signal AB during the integration period to remove excess charge, which would otherwise saturate the pixel, from node P.
FIG. 2 illustrates a block diagram for an imager 200 having a pixel array 201. Each pixel 100 of array 200 may have the architecture as shown in FIG. 1 or other well-known pixel architectures. Pixel array 201 comprises a plurality of pixels 100 arranged in a predetermined number of columns and rows. The pixels 100 of each row in array 201 are all turned on at the same time by a row select line, e.g., a line that couples row select signal ROW to the gate of transistor 112 (FIG. 1), and the output signals Vrst, Vsig of the pixels 100 of each column are selectively output to node D by column select lines under control of column driver 260. After reaching node D, the output signals Vrst, Vsig are routed to an image processor 280, which performs additional signal processing. Once all the pixels of an image have been processed by the signal processor 280, they may be output to another device (e.g., a display device, a storage device, or a printing device) via output circuit 290. A plurality of row and column lines are provided for the entire array 201. The row lines are selectively activated by the row driver 210 in response to row address decoder 220 and the column select lines are selectively activated by the column driver 260 in response to column address decoder 270. Thus, a row and column address is provided for each pixel 100. The imager 200 may further include additional well known components, such as a lens assembly, which are not illustrated in order to avoid cluttering the figure.
The imager 200 is operated by the control circuit 250 which controls address decoders 220, 270 for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry 210, 260 which apply driving voltage to the drive transistors of the selected row and column lines. The control circuit 250 also controls when, and for how long, light is incident upon the pixel array 201. The control can be via a mechanical shutter which masks and unmasks the pixel array 201 from light focused by a lens assembly (not illustrated), or alternatively, for application in otherwise unlit environments, the control circuit 250 can pulse a light source 295.
It is often desirable to run the imager 200 in full frame mode, i.e., to expose every pixel 100 in the pixel array 201 simultaneously. In order to handle various lighting conditions, there must be an exposure controller to determine when to start (i.e., reset pixels and then open shutter or turn on the light source) and when to stop (i.e., close the shutter and/or turn off the light source, and read the pixel signal) the exposure. Typically, exposure time is calculated by metering the amount of light from a subject and setting the exposure time to permit an adequate exposure from that level of light. This method, however, is problematic in that the metered amount of light may not reflect the actual light level during exposure. For example, light levels may increase or decrease between the time of metering (and thus setting of the exposure time) and the time of the exposure. Ideally, the pixels should be non-destructively read during exposure and the exposure terminated before too many pixels oversaturate. However, some pixel architectures, such as that illustrated in FIG. 1, cannot be non-destructively read, and other pixel architectures which can be non-destructively read consume more power. In larger pixel arrays, non-destructive reads may take too long to perform and may consume too much operating current. Additionally, many pixels which support non-destructive reads do not support correlated double sampling, which is useful for reducing noise during read out.
There is therefore a need for a pixel architecture compatible with an exposure control circuit which can reliably control, even in large pixel arrays, the exposure process regardless of whether the pixels 100 of the imager 200 support non-destructive reads.