1. Field of the Invention
The present invention relates to semiconductor photodiodes, and in particular, to the structures of high performance, back-illuminated photodiode arrays and the methods of fabricating such structures.
2. Prior Art
Conventional photodiode array structures are based on either front illuminated or back illuminated technologies. FIG. 1a is a simplified cross section of an exemplary prior art front illuminated photodiode array and FIG. 1b is a simplified cross section of an exemplary prior art back illuminated photodiode array. The substrate may be either n-type or p-type material, with opposite conductivity type diffused regions 2 therein. This creates a p-on-n or n-on-p structure, respectively. The anode metal pads 3 for the p-on-n structure (the cathode contacts for the n-on-p structure) are always on the device front surface. The opposite polarity electrode is usually coated (plated) on the chip backside in the case of the front illuminated structure (see metal layer 4, FIG. 1a), or is made on the device front surface (see metal pads 4, FIG. 1b) using metallized through vias 6,7 in the case of the back illuminated structure. (See also U.S. Published Patent Application Ser. Nos. 2003/0209652 A1, 2004/0104351 A1 and 2004/0129992 A1.) The blanket-type implantation 5 of the back surface of the die of the same conductivity type as the substrate improves both the charge collection efficiency and DC/AC electrical performance of the devices.
Each of the two approaches—the front illuminated and back illuminated structures—has its own advantages and disadvantages. For example, traditional front illuminated structures like that shown in FIG. 1a allow building high performance photodiodes and photodiode arrays, but impose severe constraints on the metal run width. Those constraints limit a design of the front illuminating photodiode array to the use of either a smaller number of elements, or larger gaps between adjacent elements. Note that the metal runs should be accommodated in between adjacent diffusion areas 2 (see FIG. 1a).
Back illuminated structures reported recently by several companies take advantage of solder bump technology to electrically connect elements of the array to an external substrate or PC board using the contacts (bumps) on the front surface of the structure. By utilizing solder bump technology, the metal interconnects, which usually reside on top of the active surface between the adjacent elements openings, may be moved to the substrate or PC board upon which the chip is mounted. Such an approach allows minimizing the gaps between adjacent elements of the array, at the same time allowing a virtually unlimited total number of elements. However, several drawbacks of the previously reported back illuminated structures limit their application:                1) First, these structures are usually fabricated using relatively thick wafers (>50 μm) and the resistivity of the material has to be high enough (>1000 Ohm-cm) to deplete the entire volume at zero bias, which is required for many applications;        2) Second, the application of a high resistivity material usually diminishes the photodiode performance with respect to the leakage current and shunt resistance;        3) Third, if a high resistivity material is not used, then the time response will be very long (micro seconds or even longer) because the time response would be determined by the diffusion processes rather than drift processes of the totally depleted structures;        4) Fourth, there are little or no structural features that isolate adjacent cells from each other within the entire thickness of the device, which results in relatively high cross-talk, especially at zero bias.        
Summarizing, such parameters as the leakage current, shunt resistance, cross-talk, spectral sensitivity, and temporal response are of main concern for the prior art of back illuminated structures. Additionally, the handling of thin wafers (<70 μm thickness) in the wafer fabrication process is a matter of great concern by itself, and would become increasingly important with the further decrease of the wafer thickness.