The present invention relates to processors and computing devices and more particularly to compilers for optimized multiple function arithmetic execution units in a processor.
Many practical applications require processing of very large amounts of information in a short period of time. Examples include weather forecasting, the design and modeling of complex dynamic systems and others, which applications frequently involve repeated estimation of modeling functions over a set of input parameters.
One of the basic approaches to minimizing the time to perform such computations is to apply some sort of parallelism, so that tasks which are logically independent can be performed in parallel. This can be done, for example, by executing two or more instructions per machine cycle, i.e., by means of instruction-level parallelism. Thus, in a class of computers using superscalar processing, hardware is used to detect independent instructions and execute them in parallel, often using techniques developed in the early supercomputers.
Another more powerful approach to exploiting instruction level parallelism is used by the Very Long Instruction Word (VLIW) processor architectures in which the compiler performs most instruction scheduling and parallel dispatching at compile time, reducing the operating burden at run time. By moving the scheduling tasks to the compiler, a VLIW processor avoids both the operating latency problems and the large and complex circuitry associated with on-chip instruction scheduling logic.
As known, each VLIW instruction includes multiple independent operations for execution by the processor in a single cycle. A VLIW compiler processes these instructions according to precise conformance to the structure of the processor, including the number and type of the execution units, as well as execution unit timing and latencies. The compiler groups the operations into a wide instruction for execution in one cycle. At run time, the wide instruction is applied to the various execution units with little decoding. The execution units in a VLIW processor typically include arithmetic units such as floating point arithmetic units. An example of a VLIW processor that includes floating point execution units is described by R. K. Montoye, et al. in xe2x80x9cDesign of the IBM RISC System/6000 floating point execution unitxe2x80x9d, IBM J.Res. Develop., V. 43 No.1, pp. 61-62, January 1990. Additional examples are provided in U.S. Pat. No. 5,418,975, as well as pending patent application Ser. Nos. 08/733,480, 08/733,479, 08/733,833, 08/733,834, 08/733,831 and 08,733,832, the content of which is incorporated herein for all purposes.
While these processors are capable of performing a variety of tasks adequately, it is perceived that the performance of VLIW processors can be improved further by optimizing them with respect to certain specialized but highly repetitive and often used in practice tasks, such as function evaluation using decomposition into Taylor series.
A novel method and system is presented for use with a VLIW processor to optimize it for use in function evaluation. In accordance with a preferred embodiment of the present invention, a novel approach is presented to enhancing parallelism in the evaluation of functions by table approximation methods using decompositions into Taylor series.