The field of the invention is that of transferring and asynchronously switching cells. In particular, the invention is typically concerned with transferring synchronous channels (for example, 64 kbit/s channels of a digital multiplex) using asynchronous cell switches originally designed for switching broadband services.
In a situation of this kind, an essential condition to be complied with is the transfer delay across a switching node for each synchronous channel (ITU Recommendation Q-551 specifies an average transfer delay of 900 xcexcs, for example, with 95% of 1500 xcexcs or less). This is the case in particular when using standardized ATM cells, which would imply a cell assembly time of 6 xcexcs for clustering 48 samples (each on 8 bits) of a 64 kbit/s channel.
Various approaches to reducing cell assembly time have already been proposed, whereby each cell to be switched contains no more than one sample of the same channel.
Solutions of a first category are based on the use of standardized ATM cells in xe2x80x9ccompositexe2x80x9d mode (i.e. for more than one channel), to reduce the enormous increase in bandwidth when an ATM cell (consisting of 424 bits) is used to transfer a single channel sample on 8 bits, which leads to a bandwidth 53 times greater.
Solutions of the second category are based on the use of smaller cells each of which transfers an individual channel sample. However, even in this case, the required bandwidth is large and switching control is complex.
Documents WO 95 34977 and WO 97 33406 describe systems using composite cells and switching channel data between incoming and outgoing channels (on incoming and outgoing multiplex links, respectively) by transferring composite cells (between incoming and outgoing terminal modules connecting said links), each composite cell being able to contain a plurality of channel data blocks. Each xe2x80x98channel data blockxe2x80x99 contains not only channel data to be transmitted but also an xe2x80x98addressxe2x80x99 relating to that channel.
The system described in document WO 95 34977 uses an ATM xe2x80x98virtual channel identifierxe2x80x99.
The system described in document WO 97 33406 uses a xe2x80x98connection identityxe2x80x99 which is different from the identity of the incoming or outgoing synchronous channel.
The drawback of those prior art systems is that they require assignment, marking, management and release of configuration data for each individual connection between an incoming synchronous channel and an outgoing synchronous channel.
An object of the invention is to overcome the above drawbacks.
A first object of the invention is to provide a switching system and method providing a more effective and less complex solution.
Another object of the invention is to provide a system and a method of the above kind improving existing narrowband switching nodes using conventional (PCM) synchronous switches by replacing those switches with asynchronous cell switches.
A further object of the invention is to provide a system and a method of the above kind integrating broadband services and narrowband services in switching nodes using asynchronous cell switching techniques.
The above objects, together with others that become apparent below, are achieved according to the invention by means of a system for asynchronously switching cells each comprising a header field and a data field, of the type interconnecting incoming links and outgoing links, each of said links multiplexing data belonging to at least two channels, said system comprising input port modules and output port modules interconnected by at least one stage of intermediate switching elements, wherein:
at least some of said input modules comprise composite cell forming means comprising:
means for memorizing channel data received on incoming channels over incoming links of the input port module;
means for constructing channel data blocks each comprising a channel data to be transmitted, indication extracted from the channel data received, and at least one explicit channel identifier associated with said channel data to be transmitted indication, and
means for selectively multiplexing channel data blocks intended for a common destination corresponding to at least one same destination output port module, in the data field of at least one composite cell to be transmitted to said common destination,
and wherein at least some of said output modules comprise means for processing said composite cells, comprising:
means for extracting and recognizing said received channel data blocks in the data field of a composite cell by means of said associated explicit channel identifiers, and
means for transmitting to at least one outgoing link the channel data belonging to the various channels, as a function of said associated explicit channel identifiers,
characterized in that said explicit channel identifier designates:
either the address of an incoming synchronous channel in an input port module,
or the address of at least one outgoing synchronous channel in an output port module.
Both variants are discussed below.
Adding channel identifiers designating the address of the incoming synchronous channel in the input port module or the address of at least one outgoing synchronous channel in the output port module has many advantages, as will emerge below. In particular, it not only eliminates the need to reconfigure each channel but also eliminates the need to rearrange the channels. Also, a system of the above kind is more efficient than the prior art techniques. In particular, if the switching system is of the self-routing kind, it does not require any assignment, marking, management or release of configuration data for each individual connection between an incoming synchronous channel and an outgoing synchronous channel.
Depending on the embodiment, said channel data blocks can be of fixed and identical length or of variable length. In the latter case:
either the length of each of said channel data blocks is specified by a flag associated with each of said channel data blocks,
or the length of each of said channel data blocks is fixed for each connection to an outgoing channel and known to the destination output port module.
Said variable lengths are advantageously multiples of a base length.
Said selective multiplexing means can dynamically combine channel data blocks in various ways, and in particular:
in no predetermined order, depending on the order in which said channel data is received,
in a predefined order,
in a predefined order that is modified dynamically in each transmission cycle, or
in a random or quasi-random order which is modified in each transmission cycle.
Said selective multiplexing means preferably limit the number of channel data blocks to a maximum number of channel data blocks acceptable in the data field of a composite cell.
Said selective multiplexing means advantageously take account of a maximum time for assembling a composite cell and send a composite cell that is not completely full when said maximum time has elapsed.
In one embodiment of the invention, the length of the data field of said composite cells is variable.
In this case, said length of the data field is advantageously adapted dynamically as a function of the number and/or the length of the channel data blocks that said data field contains.
The invention also concerns input port modules and output port modules for use in an asynchronous switching system as defined above.
An input module of the above kind comprising composite cell forming means comprising:
means for memorizing channel data received on incoming channels over incoming links of the input port module;
means for constructing channel data blocks each comprising a channel data to be transmitted, indication extracted from the channel data received, and at least one explicit channel identifier associated with said channel data to be transmitted indication, and
means for selectively multiplexing channel data blocks intended for a common destination corresponding to at least one same destination output port module, in the data field of at least one composite cell to be transmitted to said common destination,
is characterized in that said explicit channel identifier designates:
either the address of an incoming synchronous channel in an input port module,
or the address of at least one outgoing synchronous channel in an output port module.
Likewise, an output module of the above kind comprising means for processing said composite cells, comprising:
means for extracting and recognizing said received channel data blocks in the data field of a composite cell by means of said associated explicit channel identifiers, and
means for transmitting to at least one outgoing link the channel data belonging to the various channels, as a function of said associated explicit channel identifiers,
is characterized in that said explicit channel identifier designates:
either the address of an incoming synchronous channel in an input port module,
or the address of at least one outgoing synchronous-channel in an output port module.