The following description relates to a memory device having an array portion as well as a peripheral portion. Moreover, the description refers to a method of forming such a memory device.
Among the memory devices non-volatile memory devices, such as for example, memory devices employing memory cells, which are based on the floating-gate technology, have gained increased importance during the last years.
As a general aim which is followed with regard to any type of memory device, it is intended to further reduce the size of the memory devices. As a result, a higher packaging density and, a reduced memory device size can be obtained. The efforts to further reduce the size of a memory device are, for example, focused on further reducing the size of the individual memory cells. Nevertheless, the reduction of size is limited amongst others by requirements of the space needed for wiring, for providing contacts to wiring layers and for providing an appropriate metallization layer. Accordingly, concepts are needed by which the space needed for wiring can be reduced without increasing the process complexity.