The quest to develop larger and larger semiconductors of the dynamic random access memory (DRAM) type is a well-known goal. The industry has steadily progressed from DRAMs of the 16 K type, shown in U.S. Pat. No. 4,081,701 issued to White, McAdams and Redwine, and the 64 K type, shown in U.S. Pat. No. 4,055,444 issued to Rao, to DRAMs of the 1 M type, as described in U.S. Pat. No. 4,658,377 issued to McElroy. DRAMs of the 4 M type are now being produced. Production plans for 16 M DRAMS of submicron technology now exist and U.S. Pat. No. 5,017,506 issued to Shen, Yashiro, McKee, and Chung, on May 21, 1991 describes a process suitable for manufacturing high density 16 M DRAMS. One factor furthering the development of larger DRAMs is the reduction in memory cell geometries as illustrated in U.S. Pat. No. 4,240,092 to Kuo (a planar capacitor cell), and as illustrated in U.S. Pat. No. 4,721,987 to Baglee et al, (a trench capacitor cell). The 16 M DRAM citor cell), and as illustrated in U.S. Pat. No. 4,721,987 described in U.S. Pat. No. 5,017,506 has submicron dimensions.
A problem encountered by designers in manufacturing high density devices is noise. Among undesirable items, noise may cause circuits to inadvertently switch, may cause data loss, and may disturb signal levels. As geometries continue to decrease and as devices become more tightly packed on a semiconductor die, the opportunity for noise to create problems increases.
It is an object of this invention to reduce noise in integrated semiconductor devices.
It is a further object of this invention to provide noise shielding in integrated semiconductor devices.
Other objects and advantages of this invention will be apparent to those of ordinary skill in the art having reference to the following specification and drawings.