1. Field of the Invention
The present invention relates to latch elements and flip-flops. More particularly, the invention relates to a design structure for flip-flops used in shift register operation that allows for accurate measurement of set-up and hold times at the flip-flop on-chip locations.
2. Description of the Related Art
The skilled artisan understands the importance of knowing flip-flop set-up and hold times when timing an integrated circuit or chip. Set-up time is particularly important for systems, e.g., system on chip (SOC), operating at a very high frequency (e.g., in a shallow pipelines). At very high switching speeds or operating frequencies, set-up time is or may be an appreciable part of the clock or latch cycle. Hold times are important at any frequency because clock skew often forces a large amount of delay padding on short paths to eliminate design-killing hold-time fails. Today, as IC manufacturers continue to increase the operating frequencies of their devices, IC test platforms and systems must improve speed. Conventional technologies provide systems that can test at upwards of 400 MHz base rates, generating test vectors and comparing device output data at such speeds. Such conventional techniques that include generating test vectors, or measuring outputs at extremely high device I/O switching speeds are critically dependent on fixturing. Known conventional techniques, however, cannot access outputs at on-chip IC locations, for example, measuring set-up and hold times directly at a flip-flop output pin.
The predominant conventional application for determining set-up and hold times to determine on-chip flip-flop delay for use by IC designers is Spice. The Spice platform provides various simulation techniques whereby flip-flops and their set-up and hold time delays are simulated. Functionally, Spice moves the clock and data inputs to a flip-flop (latch) progressively closer in time while observing or tracking delay increase. The clock-data separation that causes a tolerable delay increase is declared to be the set-up time (or hold time). This approach is suspect because the cause of the delay increase is that the flip-flop is spending extra time near the metastable point. At the metastable point, both nodes of a flip-flop are near 0.5*Vdd. With low-Vdd technologies, this value is near the transistor threshold, Simulation models emphasize accuracy at high overdrive conditions, but are far less accurate at such low overdrive.
As mentioned above, attempts to directly measure set-up and hold times with clock and data input pins to a chip are unlikely to be accurate. Signals directed to or emanating from an on-chip flip-flop cannot be observed with conventional hardware and software systems. Consequently, there are large and varying fixturing delays, and uncertain silicon latencies between the IC pins and the on-chip flip-flop. Often the signal edge resolution of test equipment operating at high frequencies is not insignificant compared to the set-up or hold time being measured. That is, when using conventional fixturing techniques and devices to detect or determine IC flip-flop set-up and hold times the entire test-signal path length and the signal's round trip delay (RTD) must be included in calculations.
Various technologies are known that provide processes and circuits for addressing IC design issues relating to delay broadly, and limitations imposed on high frequency operation in view of flip-flop set-up and hold time delay, particularly in shallow pipeline operation. For example, U.S. Pat. No. 5,404,311 discloses processes and apparatus for evaluating delay in an internal logical pathway by comparison of times a signals is required to traverse similar combinational logic paths. By comparison, the inventions determine the maximum operating frequency of a set of combinational logic paths. U.S. Pat. No. 5,403,311, however, does not “measure” set-up and hold times for latches within same set of paths to support the comparisons. Comparisons may not provide the most accurate delays at the latch of interest.
U.S. Pat. No. 6,090,150 discloses techniques for determining skew of the clock tree, and delay margin of combinational logic paths in an IC. The techniques utilize the clock tree skew, and logic path delay margin to selectively add delay to the clock tree to enable faster system operation. The techniques, however, did not investigate latches or flip-flops. U.S. Pat. No. 6,090,150 does not address the problems addresses herein the instant inventions by its circuitry that accurately measures latch element operation.
U.S. Pat. No. 6,311,148 uses simulations to measure clock and data delays. The techniques disclosed use the measured clock and data delay information gathered during simulation to extract or generate set-up and hold times. That is, the generated set-up and hold times are determined by subtraction of values from the simulation-derived values. While the patented processes or techniques may be implemented in code, any hardware implementation (for faster speed of operation) would be quite limited for at least the reason that the end points of the delay measurements are not observable directly, or accessible in hardware (a circuit). While concern for delay, and delay changes, is clearly evidenced, the techniques do not attempt characterize delay change by evaluation, or characterization of set-up and/or hold times. The techniques, whether implemented in code, or in hardware circuitry, or using simulation programs, do not investigate whether any limitations detected are related to latch or flip-flop set-up and hold times, or violations of such set-up and hold times.
U.S. Pat. No. 6,348,826 discloses a circuit referred to therein as a “phase interpolator” circuit. The phase interpolator circuit is understood to allow a phase of a clock signal to be changed in small, high-precision steps. The ability to make such clock adjustments enables timing optimization of strobe signals used in high-speed interconnect schemes. The patent's disclosure does not suggest or teach circuitry for analyzing set-up and hold times for on-chip latches (flip-flops).
U.S. Pat. No. 6,378,113 is directed to the use of simulations to measure clock and data delays within integrated circuits. As understood, the inventive processes disclosed extract or detect latch or flip-flop set-up times (but not hold times) from simulation data. As mentioned above, the set-up and hold times for latch elements operating on-chip in an IC are determined by software simulation, such as provided by Spice. The inventive processes are believed to be limited to software implementations because of inherent limitations for implementing such a technique in hardware. That is, by virtue of IC location, end points of delay measurements at internal latches are not observable (detectable) directly. The disclosed processes do not use or look to set-up or hold time violations to estimate delay changes.
U.S. Pat. No. 6,421,801 refers to “set-up and hold time” within IC designs as a concept. The phrase “set-up and hold times” as used in the referenced patent appear to be used to characterize and explain processes which may be applied to different levels of assemblies in an IC, with substantially different meaning. That is, “set-up and hold time” is not used in the referenced patent to refer to the narrow timing window near a flip-flop clock edge, the focus of the instant inventions. The present inventions' use of the phrase “set-up and hold time” herein refers to a narrow window of time in a latch cycle, wherein the flip-flop may not function properly. Set-up and hold time windows as used in the instant inventions, as distinguished from the disclosure found in U.S. Pat. No. 6,421,801, do not relate to solving design problems concerned with accurately measuring flip-flop or latch clock-cycle time per se, but on a single edge of the clock signal driving a latch or flip-flop.
U.S. Pat. No. 6,456,560 discloses a circuit that measures set-up and hold times, and includes a variable delay line for testing IC design circuitry. The variable delay line allows for evaluating set-up and hold times by changing the delay line setting and observing the behavior of the other circuitry under evaluation. The use of the phrase, or definition of “set-up and hold time” appears to relate to the set-up and hold times of a memory chip, not a flip-flop or latch. U.S. Pat. No. 6,456,560, does not appear to include circuitry capable of determining accurately set-up and hold times in latches or flip-flops comprising ICs, used for high-frequency pipelining.
U.S. Pat. No. 6,440,330 teaches a process which uses simulations to measure delays, to extract set-up and hold times from data realized from the simulations. The techniques disclosed appear to be implementable in software rather than hardware. The end points of the delay measurements are not observable in hardware, and therefore any software technique suffers from this hardware limitation.
U.S. Pat. No. 6,732,066 is similar, and commonly owned with U.S. Pat. No. 6,311,148. The patent references disclose the use of simulations to simulate or estimate clock and data delay information gathered during simulation. The generated set-up and hold times are determined by subtraction of simulation values from other the simulation-derived values. Simulation-generated or estimated set-up and hold time limitations may not be sufficiently accurate for all designs, particular those relying on high frequent shallow pipelining. Moreover, while the patented processes or techniques may be implementable by software, any hardware implementation, which would of course be much faster, would be quite limited for at least the reason that the end points of the delay measurements are not observable, or accessible in hardware (other than by use of simulation). While concern for delay, and delay changes, is clearly evidenced, the techniques do not attempt characterize delay change by physical evaluation, and whether detected limitations or simulations based on set-up and hold times in a flip-flop or latch are violated.
U.S. Pat. No. 6,904,579 discloses the use of simulations to measure delays, and to extract set-up and hold times from data derived during the simulations. The invention appears to be implementable in software, and not hardware, because the end points of the delay measurements are not observable in hardware. Attempts to measure delay using hardware circuitry would be much faster than software implementations of the same tasks, but limited for at least the reason that the end points of the delay measurements are not observable, or accessible in hardware (a circuit) directly. While concern for delay, and delay changes, is clearly evidenced, the techniques do not attempt characterize delay change by physical evaluation, and do not include a process or sub-process by which setup and hold times in a particular flip-flop or latch are violated, with respect to inherent delay.
U.S. Pat. No. 7,007,215 relates to a circuit that attempts to accurately measure set-up and hold times and through the use of a variable delay line. The circuitry relies on two edges generated with high precision test equipment. The disclosure appears to utilize the expression “set-up and hold time” as a time reference relating to the set-up and hold times of a memory chip, not the set-up and hold times of latches or flip-flops within an IC, or circuitry for determining the set-up and hold times for on-chip latches accurately, particularly for high speed shallow pipelining. That is, high-speed test equipment may influence the accuracy of estimated, simulated, set-up and hold time delays, or same determined using a text fixture (at pin measurements).
None of the above-mentioned conventional circuitry and processes suggest attempting to measure latch delay, accurately, at the on-chip latch location. That is, conventional processes are critically dependent on fixturing and simulations, which do not provide for direct set-up and hold measurement for flip-flops or latches used for pipelining, but merely estimate, or predict, which estimates and predictions cannot be relied upon in all cases, particularly during operation under environmental conditions that could influence, or modify the latch element metastability point (see details below), during high speed operation.