1. Field of the Invention
This invention relates to multi-bit-per-cell non-volatile memory and to methods for classifying and operating such memories for maximum data capacity.
2. Description of Related Art
A traditional semiconductor memory device such as an SRAM, DRAM, ROM, EPROM, Flash, EEPROM, or NVRAM has a data capacity (e.g., 1 Mbit or 1 Gbit) that is pre-determined by the memory device""s design. For a multi-bit-per-cell Flash memory, each design/mask-set fixes both the number N of bits stored per cell and the total storage capacity of the Flash memory. For example, a memory designed to store four bits per memory cell and include 64 Meg (1024xc3x971024) cells has a data capacity of 256 Mbits. This data capacity is fixed for the lifetime of the memory. If during manufacturing or operation the memory has fewer than 64 Meg cells that are capable of storing four bits per cell, the memory is defective and must be discarded during manufacture or replaced during operation. This reduces the yield and/or the usable life of multi-bit-per cell memories.
In the design of multi-bit-per-cell Flash memory, there is usually a trade-off between the number of bits N stored per cell and the error rate or data integrity/reliability that the memory provides. Generally, the number N of bits that can be stored per cell depends on the usable range of threshold voltages representing data values and the separation between consecutive threshold voltages that represent different data values. For current memory cell designs, the available threshold voltage range is less than about 5 volts. However, an infinite number of different threshold voltage levels are possible if read and write circuits are perfectly accurate and perfectly calibrated and the memory cells did not experience any threshold voltage drift. In an actual device, several factors limit the minimum separation between distinct threshold voltage levels. In particular, minimum separation must include a margin for charge-gain and charge-loss effects and data retention and endurance effects that change the threshold voltage of memory cells. Additionally, the write and read processes have limited accuracy, which can be affected by parasitic effects across the memory array, such as source line, word line, or bit line resistance, capacitance, and RC effects. Process variations can also lead to unequal performance and reactions for read and write circuits and memory cells. Sensitivities to power supply voltage and temperature provide transient effects that disturb the accuracy with which threshold voltages are read or written. A design for a multi-bit-per-cell memory must account for all of these factors and select a number N of bits that can be stored with a desired reliability.
Assuming a threshold voltage dynamic range of 3.2 V, conventional binary or 1-bit-per-cell Flash memory (N=1) has 2 levels with a threshold voltage window about 1.6 V wide for each level. A two-bit-per-cell memory (N=2) has four levels and an 800 mV wide window for each level. A four-bit-per-cell memory (N=4) has sixteen levels and a 200 mV wide window for each level. As the number of bits per cell increases, the threshold voltage window for each level narrows, and the capability of read and write circuits to distinguish between levels must correspondingly increase if reliability is to be maintained. In addition, the potential for data errors caused by small drifts in the threshold voltages increases as the window for each level narrows. Accordingly, threshold voltage drift must be more tightly controlled as the number N of bits stored per memory cell increases.
Generally, achieving the same reliability or error rate with a two-bit-per-cell memory as with a binary memory is difficult because a fraction of the memory cells in high density memories normally fail to meet all of the stringent requirements for reliably storing two bits of data. Achieving the same reliability with a three- or four-bit-per-cell memory is even more difficult. Further, non-volatile memories such as Flash memories have established quality expectations of minimum data retention time (about 10 years), minimum endurance ( greater than 100,000 write/erase cycles), and operability with supply voltage variations (xc2x110%), and temperature variation (0 to 70xc2x0 C.). The industry established expectations are based on the binary memory architecture and are more difficult to achieve in a multi-bit-per-cell memory.
Several crucial improvements of a proven 1-bit-per-cell memory design are generally required to achieve an N-bit-per-cell memory design with acceptable reliability. The read and write circuits must be modified to significantly improve the threshold voltage write and read accuracy. Assuming that data retention, charge-gain and charge-loss effects are intrinsic and cannot be totally eliminated, extensive tracking or reference circuitry must be added to reduce sensitivities to disturb and aging effects and to supply voltage, temperature, and process variations. Memory array architectures and memory cell and memory cell/array layouts must be tailored to minimize cell-to-cell, array-to-array, and die-to-die variations and disturb and endurance effects.
In accordance with the invention, a memory device includes multiple memory arrays. Each memory array is operable in multiple modes with each mode corresponding to a different number of bits stored per memory cell in the array. The number of bits stored per cell in each array can be selected based on results of a wafer-sort or a package level test and extrapolation based on a burn-in/life test. The memory device provides lower cost per bit of storage because the memory device can maximize the effective data storage of each array and can salvage memory devices that would otherwise be classified as defective when one or more of the arrays cannot provide a desired storage density. The memory device is particularly useful for mass data storage applications that store serial data because a serial data stream can be broken into data units of variable widths according to the number of bits Nj stored in each memory cell of the receiving array j.
The memory devices can be packaged with a minimum guaranteed memory density with a fixed N across all memory arrays, or with an option to select a highest possible memory density with a different number of bits stored in at least some of the memory arrays. The fixed N option may simplify random memory accesses, but the variable N provides higher data density. For the high-density option, one array may operate as multi-bit-per-cell storage (N greater than 1), while a second array operates a binary storage (N=1) and a third array is disabled (N=0). An on-chip electronic signature can indicate the combined or total (effective) memory density of the device. The package labeling also indicates the total capacity, and the selling price for each device can then be set individually depending on the capacity.
One embodiment of the invention is a manufacturing method that includes: fabricating an integrated circuit memory device that includes a plurality of memory units; testing each memory unit; and setting each memory unit j for storage of Nj bits per cell. Each memory unit has a design capacity to store a maximum of Nmax bits per memory cell, but for each memory unit j, the setting Nj depends on results of the extensive testing. A total storage capacity of the integrated circuit memory device depends on the settings of the memory units. The design of the memory units provides an expected capacity to store Nav bits per memory unit, which typically is less than Nmax. When testing indicates one of the memory units can accurately write, store, and read more than Nav bits per memory cell, the setting causes that memory unit to store more than Nav bits per cell. When testing indicates one of the memory units cannot accurately write, store, or read Nav bits per memory cell, the setting causes that memory unit to store fewer than Nav bits per cell. Accordingly, memory chips of the same design will end up with different memory capacities according to actual capabilities achieved in the manufacturing and testing processes. This allows production of more value memory chips having higher than expected memory capacity and higher yields of operable chips because memory chips having some memory arrays that do not meet expectations can still be salvaged as valuable devices.
Another embodiment of the invention is a memory including multiple memory arrays, a data input/output interface, and a data buffer. The memory arrays have the same design, but among the memory arrays are a first memory array and a second memory array capable of different levels of storage performance. The first memory array is configured to store N1 bits per memory cell, and the second memory array is configured to store N2 bits per memory cell, where N2 is less than N1 and greater than zero. The data buffer is between the input/output interface and the plurality of memory arrays and collects data read from or to be written to the plurality of memory cells. Accordingly, the data buffer converts between the variable data widths used in the memory, and standard data widths for external circuits.
An externally accessible register can store the settings of the numbers of bits store per cell in the arrays. External accessibility allows a user to examine or change the number of bits stored per cell, and thus allows a trade-off between data accuracy and data capacity. Such changes can, for example, maintain a desired level of data accuracy as the memory ages or decrease accuracy to increase memory capacity in error-tolerant applications, such as music or image storage. These techniques are also fully compatible with error correction schemes such as Reed-Solomon coding so that the decreased accuracy associated with the increased memory capacity does not generate any effective (i.e., uncorrectable) errors.
One implementation of the memory includes write and read circuits having a maximum capacity to write and read Nmax-bit digital values. Each digital value corresponds to a threshold voltage of a corresponding memory cell, but some of the bits of the Nmax-bit values may be inaccurate or vary from one memory access to the next. Converters convert data signals according to the accuracy of the memory arrays being accessed.
Yet another embodiment of the invention is a method for using an integrated circuit memory. The method includes: selecting a first memory array in the integrated circuit memory; identifying a number N1 of bits per cell for the first memory array; and accessing a first selected memory cell in the first memory array. The access of the first selected memory cell transfers N1 bits of data. The method further includes: selecting a second memory array in the integrated circuit memory; identifying a number N2 of bits per cell for the second memory array, wherein N2 differs from N1; and accessing a second selected memory cell in the second memory array. The access of the second selected memory cell transfers N2 bits of data. Accordingly, the memory uses internal accesses of different effective data widths per memory cell. Each access can be a write or read operation, and a register can store settings for identification of the numbers of bits per cell accessed in corresponding memory arrays.