Conventionally, source drivers (video signal line drive circuits) of liquid crystal display devices perform a process for converting digital image signals, which are externally transmitted in serial format, into parallel format in order to provide sufficient time for writing to (charging) each pixel capacitance. FIG. 9 is a block diagram illustrating the configuration of a source driver in a conventional liquid crystal display device having n video signal lines (hereinafter, referred to as the “first to n'th video signal lines SL1 to SLn”). The source driver includes a shift register 71, a No. 1 latch circuit group 72, a No. 2 latch circuit group 73, and an output circuit group 75. The shift register 71 includes n flip-flop circuits (hereinafter, referred to as the “first to n'th flip-flop circuits FF1 to FFn”) associated with the first to n'th video signal lines SL1 to SLn, respectively. That is, the shift register 71 is composed of n stages. The No. 1 latch circuit group 72 includes n latch circuits (hereinafter, referred to as the “first to n'th No. 1 latch circuits Lf1 to Lfn”) associated with the first to n'th video signal lines SL1 to SLn, respectively. The No. 2 latch circuit group 73 includes n latch circuits (hereinafter, referred to as the “first to n'th No. 2 latch circuits Ls1 to Lsn”) associated with the first to n'th video signal lines SL1 to SLn, respectively. The output circuit group 75 includes n output circuits (hereinafter, referred to as the “first to n'th output circuits B1 to Bn”) associated with the first to n'th video signal lines SL1 to SLn. In addition, each of the output circuits B1 to Bn includes a digital/analog conversion unit (not shown) and a buffer unit (not shown).
Inputted to the shift register 71 are a source start pulse signal SSP and a source clock signal SCK, and based on these signals SSP and SCK, the shift register 71 sequentially transfers each pulse included in the source start pulse signal SSP from the first flip-flop circuit FF1 to the n'th flip-flop circuit FFn. In response to the transfer, sampling pulses SO1 to SOn are sequentially outputted from their respective flip-flop circuits FF1 to FFn. The sampling pulses SO1 to SOn are respectively inputted to the first to n'th No. 1 latch circuits Lf1 to Lfn in the No. 1 latch circuit group 72. Also, a digital image signal Da outputted from a display control circuit 200 is inputted to each of the first to n'th No. 1 latch circuits Lf1 to Lfn. The digital image signals Da are sampled by the first to n'th No. 1 latch circuits Lf1 to Lfn, with the timings of the sampling pulses SO1 to SOn, respectively, and outputted as internal image signals (hereinafter, denoted by characters dLf1 to dLfn). The first to n'th No. 2 latch circuits Ls1 to Lsn respectively receive the internal image signals outputted from the first to n'th No. 1 latch circuits Lf1 to Lfn, and concurrently output the internal image signals in accordance with a transfer instruction signal TR outputted from the display control circuit 200 (hereinafter, the internal image signals outputted from the first to n'th No. 2 latch circuits Ls1 to Lsn are denoted by characters dLs1 to dLsn). The first to n'th output circuits B1 to Bn receive the internal image signals dLs1 to dLsn, respectively, and subject them to digital/analog conversion and impedance conversion before outputting them as drive video signals Out1 to Outn. The drive video signals Out1 to Outn are respectively outputted from output ends 39 to the first to n'th video signal lines SL1 to SLn.
FIG. 10 is a signal waveform diagram in relation to the above configuration. Character Ts denotes a cycle in which sampling pulses are outputted from the shift register 71 (a period corresponding to a pulse repetition cycle of the source clock signal SCK). Character Ta denotes a period corresponding to one horizontal scanning period. This corresponds to a pulse repetition cycle of the start pulse signal SSP. Character Tx denotes a period (hereinafter, also referred to as the “process period”) in which writing to the pixel capacitance is performed. Character dTm denotes a period related to the writing to the pixel capacitance and required for switching from one horizontal line to the next horizontal line. Characters t11 to t28 denote time points (timings) for each pulse repetition cycle of the source clock signal SCK. Characters d11 to d1n each denote pixel data for a pixel included in the first horizontal line, and characters d21 to d2n each denote pixel data for a pixel included in the second horizontal line.
When a pulse of the source start pulse signal SSP is inputted to the shift register 71, the flip-flop circuits FF1 to FFn sequentially and respectively output the sampling pulses SO1 to SOn in order from the first flip-flop circuit FF1 to the n'th flip-flop circuit FFn, in accordance with a pulse of the source clock signal SCK. The first to n'th No. 1 latch circuits Lf1 to Lfn sample the externally transmitted image signals Da, respectively, with the timings of the sampling pulses SO1 to SOn as described above, and output the sampled image signals Da as the internal image signals dLf1 to dLfn. For example, when the time point t11 is reached, the first No. 1 latch circuit Lf1 receives the sampling pulse SO1, and samples the image signal Da. At this time, the image signal Da represents the pixel data d11 as shown in FIG. 10. Accordingly, in a period from the time point t11 until the time point t21 at which the first No. 1 latch circuit Lf1 receives the next sampling pulse SO1, the internal image signal dLf1 representing the pixel data d11 is outputted from the first No. 1 latch circuit Lf1. As for the second to n'th No. 1 latch circuits Lf2 to Lfn, similarly, in their respective periods from reception of the sampling pulses SO2 to SOn until reception of the next sampling pulses SO2 to SOn, the internal image signals dLf2 to dLfn respectively representing the pixel data d12 to d1n are outputted. The internal image signals dLf1 to dLfn are inputted to the first to n'th No. 2 latch circuits Ls1 to Lsn, respectively.
Thereafter, when the transfer instruction signal TR changes from low to high level, the first to n'th No. 2 latch circuits Ls1 to Lsn respectively output, as the internal image signals dLs1 to dLsn, the internal image signals dLf1 to dLfn representing the pixel data d11 to d1n transmitted from the first to n'th No. 1 latch circuits Lf1 to Lfn. As such, the internal image signals representing pixel data for pixels included in each horizontal line are concurrently outputted from the No. 2 latch circuit group 73, thereby ensuring a sufficient charge time for writing to each pixel capacitance.
FIG. 11 is a block diagram illustrating the configuration of a source driver of a display device disclosed in Japanese Laid-Open Patent Publication No. 2002-140053, and FIG. 12 is a signal waveform diagram in relation to that configuration. As shown in FIG. 11, the No. 2 latch circuit group 73 of the source driver does not include a No. 2 latch circuit associated with the n'th video signal line SLn. In addition, the sampling pulse SOn outputted from the n'th flip-flop circuit FFn is inputted to the No. 2 latch circuit group 73 as the transfer instruction signal TR. As a result, while the No. 2 latch circuits are reduced in number, a sufficient charge time for writing to each pixel capacitance is ensured.    [Patent Document 1] Japanese Laid-Open Patent Publication No. 2002-140053