Modern computer systems comprise a memory and a memory controller. In memory, such as DRAMs (Dynamic Random Access Memory) or SRAMs (Static Random Access Memory) for examples, data stored in the memory may become corrupted, for example by one or more forms of radiation. Often this corruption presents itself as a “soft error”. For example, a single bit in a block of data read (such as a cache line that is read) may be read as a “0” whereas the single bit had been written as a “1”. Most modern computer systems use an error correcting code (ECC) circuitry to correct a single bit error (SBE) before passing the block of data to a processor. The SBE may be a permanent error (a physical error in the memory or interconnection to the memory) or the SBE may be a “soft error”.
Some modern computer systems are capable of correcting more than one error in the block of data read. For simplicity of explanation, ECC circuitry herein will be described in terms of correcting single bit errors, but the invention is not limited to computer systems having ECC circuitry that correct only single bit errors.
Soft errors in memory are often corrected by scrubbing. Scrubbing refers to periodically or otherwise reading data, correcting any correctable errors, and writing the corrected data back to memory. Scrubbing is important to prevent a single bit soft error from, over time, becoming a multi-bit error that the ECC circuitry is incapable of correcting.
For example, suppose the ECC circuitry is capable of correcting an SBE, and a first soft error occurs in a particular cache line. The ECC circuitry is capable of correcting the SBE and sending correct data to the processor. Further suppose that the first soft error is left uncorrected, and, after a period of time, a second error (hard or soft error) occurs in the particular cache line. A “hard” error is a permanent error, for example, a broken signal connector, or a failing driver or receiver. The ECC circuitry is not capable of correcting a cache line having two errors, and reports that an error has been detected but can not be corrected, resulting in likely termination of a task requesting the particular cache line, and possibly requiring a re-boot of the computer system.
To reduce the likelihood of uncorrectable multi-bit errors, therefore, memory is scrubbed over a specified scrub period. For example, an entire memory of a computer system may be scrubbed over a twenty four hour scrub period. Specified memory reliability rates rely on completion of scrubbing all memory in the specified period.
A memory controller determines how much memory is connected to the memory controller, determines how many scrub requests must be serviced to scrub the entire memory during the scrub period (e.g., a day), and breaks the scrub period into scrub intervals.
A memory controller sequences through the total number of scrubs required, one scrub command at a time, requiring that a scrub be serviced during each scrub interval.
With reference now to prior art FIGS. 3A and 3B, during a first scrub subinterval of a particular scrub interval, the scrub command will be serviced if doing so does not impact normal read commands issued by the processor, or, in some cases, write commands. If the scrub command has not been serviced during the first scrub subinterval of the particular scrub interval, the scrub request escalates to a scrub demand during a second scrub subinterval, at which point, normal command flow (servicing reads and writes issued by the processor) is delayed in favor of the scrub demand, the scrub demand is serviced, and then the normal command flow resumed. Demand scrubs reduce throughput of the computer system because they increase latency of read and write requests, causing a processor to wait for data. This is shown pictorially in FIG. 3B. In FIG. 3B, progress of scrubbing over the scrub period is shown as a straight line over the course of the scrub period (for exemplary purposes, the scrub period is one day). A memory demand workload is shown to increase at about 8 am, remain relatively high until about 5 pm, and then taper off. During Time A and Time C, memory demand workload is relatively light. During Time B, memory demand workload is relatively heavy, and it often occurs that scrub requests can not be serviced during a first scrub subinterval of a scrub interval. To keep on the straight-line “progress”, scrub demands, in a second scrub subinterval of the scrub interval, are then enforced, causing scrub requests to be serviced while read requests and write requests issued by the processor wait.
In an embodiment of the present invention, a scrub slack value is determined. The scrub slack value indicates whether, at a given time, scrub progress is ahead of, or behind, an expected progress of scrubbing. A memory workload is determined by dynamically measuring the workload or by using a predetermined estimate of memory workload by time of day. The memory workload may be dynamically determined by observation of fullness of a write queue or a read queue in a memory controller, wherein if the read queue and/or the write queue become relatively full, the memory workload is heavy. Responsive to scrub progress and memory workload, a scrub priority is adjusted. Advantageously, when memory workload is relatively light, the memory controller attempts to “get ahead” of the expected scrub progress by servicing more scrub requests in a given time interval. When memory workload is relatively heavy, the memory controller services relatively fewer scrub requests in order to reduce read and/or write request latency related to read requests and write requests issued by the processor. In addition, if the scrub progress lags the expected scrub progress as a scrub period nears completion, scrub priority is raised in order that the memory controller completes scrubbing of the entire memory during the scrub period.
In an embodiment, scrub priority is adjusted by lengthening or shortening a scrub interval. In an embodiment, scrub priority is adjusted by changing an apportionment of the scrub interval between a first scrub subinterval during which scrub requests have a first priority versus read and/or write requests, and a second scrub subinterval during which scrub requests have a second priority, higher than the first priority, versus read requests and/or write requests.