FIG. 1a shows the cross section of a conventional vertical DMOS (VDMOS) transistor 10. A conventional VDMOS transistor 10 has a N+ drain electrode 11 below a lightly doped N- region 12. Within the N- region 12 is a pair of P-type regions 13a and 13b. Each of the P type regions 13a and 13b respectively has a N type source region, 15a and 15b. A polysilicon gate electrode 17 is located above a portion of the N- region 12 overlapping both the P type regions 13a and 13b and the source electrodes 15a and 15b, with a dielectric layer 18 provided between the polysilicon gate electrode 17 and the aforementioned regions. When the drain electrode 11 is grounded and the voltage at the source electrodes 15a and 15b is higher than a threshold voltage, a current 19 is permitted to flow between the source electrodes and the drain electrode. The path of the current is shown by arrows 19 and is both horizontal and vertical.
FIG. 1b shows another type of conventional VDMOS transistor 20 which has a gate electrode 27 located in a trench. Current flows vertically from source electrodes 25a and 25b to a drain electrode 11 as shown by arrows 29.
Comparing the above-described conventional VDMOS transistors 10 and 20, transistor 10 consumes more electricity because the current 19 flows a longer distance in the lightly doped N- region 12, which results in a larger source/drain resistance. As may be readily appreciated, the transistor 20 is more efficient because it has a shorter current path. Although the trenched structure of transistor 20 reduces the source/drain resistance, both of the conventional VDMOS devices 10 and 20 have a deficiency in that their source/drain resistances and breakdown voltages decrease when the doping density of their respective N- regions are increased. As a result, high breakdown voltage and low source/drain resistance can not be achieved simultaneously.