1. Field of the Invention
The present invention relates to a screen display device for displaying characters and patterns such as the channel number and sound volume superimposed upon an image broadcast on a TV or VTR display screen.
2. Description of the Prior Art
FIG. 8 is a system block diagram of a prior art screen display device.
In the figure, reference numeral 1 represents a synchronous signal input circuit through which a horizontal synchronous signal HSYNC and a vertical synchronous signal VSYNC included in an image signal for TV and the like are input into an oscillator circuit 2 and a display position detection circuit 3. The display position detection circuit 3 detects the display position of a character or pattern based on these synchronous signals, and its output is input into a timing generator 4 and a display control circuit 5. The oscillator circuit 2 is reset for each horizontal synchronous signal HSYNC and oscillates at a predetermined frequency.
This oscillation output of this oscillator circuit 2 is input into the timing generator 4. The timing generator 4 generates a clock required for the operation of each part based on the oscillation output and provides the clock to an input control circuit 6, a display memory 7, a vertical-direction outlining control circuit 8A, a horizontal-direction outlining control circuit 9, a character ROM 10A and the display control circuit 5.
Meanwhile, code data CD (including commands such as display start, display stop and an outlining instruction, character codes and the like) from an unshown microcomputer for displaying a desired character or pattern are input into the display memory 7 through the input control circuit 6. The display memory 7 stores the input code data. The code data stored in the display memory 7 are read sequentially for display, and the read code data are input as addresses into the character ROM 10A which stores character font data for characters and patterns to be displayed. An outlining instruction signal Z is input into the vertical-direction outlining control circuit 8A for outputting a precharge signal X3 for outlining a display image in a vertical direction thereof and the horizontal-direction outlining control circuit 9 for outlining the display image in a horizontal direction thereof. FIG. 9 is a diagram showing the internal configuration of the vertical-direction outlining control circuit 8A. The vertical-direction outlining control circuit 8A consists of an X1 signal generator 81 for generating a precharge signal X1 only once at the beginning of a single-character display time-period and an X3 signal generator 82A for generating a precharge signal X3 three times within the single-character display time period when it receives the outlining instruction signal Z. The precharge signal X1 output from the vertical-direction outlining control circuit 8A once at the beginning of the single-character display time period is input into the character ROM 10A, and the precharge signal X3 output three times within the single-character display time period is input into the ROM data output control circuit 11. Character font data read from the character ROM 10A is input into the horizontal-direction outlining control circuit 9 through the ROM data output control circuit 11. The output SC (a character display signal SQ and an outline display signal SE to be described hereinafter) of the horizontal-direction outlining control circuit 9 is supplied to an unshown CRT through the display control circuit 5 to control display colors, for example.
One font is composed of l.times.x m dot pixels, for example, as shown in FIG. 10. The character ROM 10A has a storage capacity of l.times.m.times.n dots for storing n character fonts.
FIG. 11 is a structural diagram illustrating the character ROM 10A, the vertical-direction outlining control circuit 8A and the ROM data output control circuit 11, together with the horizontal-direction outlining control circuit 9.
The character ROM 10A comprises an address decoder circuit 12 to which code data from the display memory 7 are input, a ROM output control circuit 13 to which a clock signal CK from the timing generator 4 is input, and an m numbers of storage areas 14a through 14m. Address decode signals A1 through An output from the address-decoder circuit 12 and bit signals B1 through Bl output from the ROM output control signal 13 are input into the storage areas 14a through 14m. Data stored in the storage areas 14a through 14m are input into the horizontal-direction outlining control circuit 9 through data lines DL1 through DLm.
The outlining instruction signal Z and the clock signal CK are input from the display memory 7 and the timing generator 4 to the vertical-direction outlining control circuit 8A, respectively. The precharge signal X1 output from the vertical-direction outlining control circuit 8A is input into the storage areas 14a through 14m.
The ROM data output control circuit 11 consists of an m number of P channel MOS transistors E1 through Em, whose drains are connected to the respective data line DL1 through DLm, and whose sources are all connected to a precharge power supply VDD.
The precharge signal X3 output from the vertical-direction outlining control circuit 8A is input into the gates of the P channel MOS transistors E1 through Em.
FIG. 12 shows the details of the storage area 14c, for example, of the character ROM; other storage areas have the same structure, as shown in the figure.
The storage area 14c contains l.times.n memory cells M11 to Mln arranged in a matrix form. Each memory cell consists of an N-channel MOS transistor, and the gates of memory cells in each column (M11 through Ml1), and (M12 to Ml2) to and including (M1n through Mln) are connected to respective word lines WL1 through WLn, whereas the drains of memory cells in each row (M11 through M1n), and (M21 through M2n) to and including (M11 to Mln) are connected to respective bit lines BL1 through BLl. The drain of only a bit memory cell having character font data is connected to the respective bit line BL. For instance, in FIG. 12, the drain of the memory cell M31 is connected to the bit line BL3. This is equivalent to the writing of character font data onto the position of the checkered area (image display area) in FIG. 10. Each of the word lines WL1 to WLn to which the address decode signals A1 through An are input is connected to all storage areas. In other words, each storage area stores data on each column of all (n) character fonts (see FIG. 10), and a single font is constructed with all the memory cells connected to a single word line. The bit lines BL1 through BLl are connected to the power supply VDD through the respective P-channel MOS transistors C1 through Cl. The data lines DL1 through DLm of the storage areas are also connected to the power supply VDD through the respective P-channel MOS transistors E1 through Em. The precharge signals X1 and X3 are provided from the vertical-direction outlining control circuit 8A to the gates of the P-channel MOS transistors C1 to Cl, and E1 to Em, respectively, at the beginning of each access at a predetermined time, whereby the transistors C1 through Cl and E1 through Em become conductive, and the bit lines BL1 to BLl and the data lines DL1 to DLm are precharged.
After precharging, one of the address decode signals A1 through An is provided to the respective word line from the address decoder circuit 12 according to an address (code data) from the display memory 7.
For instance, when the address decode signal A1 is provided to the word line WL1, all the memory cells connected to this word line WL1 become conductive. In the storage area 14c shown in FIG. 12, the memory cells M11 through Ml1 become conductive, and the charge precharged onto the bit line BL3 is pulled out through the memory cell M31 connected to the bit line BL3.
The bit lines BL1 through BLl are all connected to the data line DL3 of the storage area 14c through the respective output gate transistors G1 through Gl, each of which consists of an N-channel MOS transistor. The gates of the output gate transistors G1 through Gl are connected to respective control lines CL1 through CLl. Moreover, each of the control lines CL1 to CLl is connected to all the storage areas 14a through 14m. The ROM output control circuit 13 provides the bit signals Bl through sequentially to the respective control lines CL1 to CLl upon each scanning in response to the clock of the timing generator 4. In accordance with this, in the storage area 14c of FIG. 12, the output gate transistors G1 to Gl become conductive sequentially so that data over the bit lines are read out sequentially to the data line DL3. The same operation is performed in other storage areas at the same time so that m-bit data is read out from each of the storage areas 14a through 14m to the respective data lines DL1 through DLm concurrently. For instance, when the bit signal B3 is input into the control line CL3, data over the third bit lines BL3 of the storage areas 14a through 14m are read out to the respective data lines DL1 through DLm concurrently. This is equivalent to the reading of m pieces of data over the third line shown by the arrow of FIG. 10. The read data are input into the horizontal-direction outlining control circuit 9.
The horizontal-direction outlining control circuit 9 comprises a parallel/serial conversion circuit 9a for an m-bit character pattern, and a parallel/serial conversion circuit 9b for an m-bit outline pattern as shown in FIG. 13. Character font data is input into these parallel/serial conversion circuits 9a and 9b from the character ROM 10A through the ROM data output control circuit 11. The output of the parallel/serial conversion circuits 9a (or 9b) is input into a flip-flop F1 (or F4) whose output is further supplied to a flip-flop F2 (or F5). Further, the output of the flip-flop F2 (or F5) is supplied to a flip-flop F3 (or F6). The output of each of these flip-flops is input into a three-input NOR circuit N1 (or N2), and the output of the flip-flop F2 is a character display signal SW. The clock CK of the timing generator 4 is input into the timing signal terminals T of the flip-flops F1 through F6. The outputs of the three-input NOR circuits N1 and N2 are input into a NOR circuit N3 which outputs an outline display signal SE through an AND circuit A controlled by the outlining instruction signal Z. The outline display signal SE and the character display signal SW are both input into the display control circuit 5.
A description is subsequently given of the basic operation of the horizontal-direction outlining control circuit. FIGS. 14(A) through (J) are timing charts of signals input into each part of the horizontal-direction outlining control circuit 9. These timing charts illustrate the status of data output by the bit signal B3 shown in FIG. 12 in the horizontal-direction outlining control circuit 9 so as to display an image at a position shown in FIG. 10. When a shift clock is input into the parallel/serial conversion circuit 9a for a character pattern, data received by the parallel/serial conversion circuit 9a for a character pattern is shifted in the order shown, in FIGS. 14(C) and (D) in response to first and second clocks and output from the parallel/serial conversion circuit 9a in response to a third clock. Then, the input side "a" of the flip-flop F1 rises to "H" and falls in synchronism with a fall in the first clock CK provided from the timing generator 4 and shown in FIG. 14(A). Thereafter, each time the subsequent second and third clocks. CK are provided, the flip-flops F2 and F3 operate reversely so that data is shifted in the order shown in FIGS. 14(E), (F) and (G) and the character display signal SW is output to the display control circuit 5. When the output of the flip-flop F2 becomes "L", the output side "d" of the flip-flop F3 becomes "H" as shown in FIG. 14(H). As shown in FIG. 14(I), the output side "e" of the NOR circuit N1 turns to "L" at the time when the output side "b" of the flip-flop F1 becomes "H", and to "H" at the time when the output side "d" of the flip-flop F3 becomes "L". Thereby, the output side "f" of the NOR circuit N3 is equal to the inverted output of the output side "e" of the NOR circuit N1 as shown in FIG. 14(J) and is output as the outline display signal SE through the AND circuit A. The character display signal SW and the outline display signal SE thus obtained are both supplied to the unshown CRT through the display control circuit 5 so that the horizontal direction of the image display area is outlined by the outline display area as shown in FIG. 10.
The parallel/serial conversion circuit 9b for outline pattern data is shown in FIG. 13. This parallel/serial circuit works in an identical manner as the parallel/serial conversion circuit 9a for the character data, discussed above.
A description is subsequently given of the operation of the screen display device.
FIGS. 15(A) through (I) are timing charts of the access operation of the character ROM 10A. In FIG. 8, when the horizontal synchronous signal HSYNC and the vertical synchronous signal VSYNC are input into the synchronous signal input circuit 1, signals related to these synchronous signals are output to the oscillator circuit 2 and the display position detection circuit 3. The oscillator circuit 2 generates a predetermined oscillation output to the timing generator 4 based on the input synchronous signals, and the display position detection circuit 3 detects the image display position of a preset screen based on the input synchronous signals in order to adjust timing of displaying an image.
Meanwhile, when code data for displaying characters and patterns are input into the input control circuit 6 from the unshown microcomputer, code data such as signals for displaying and not displaying an image, an outlining instruction signal and character codes are written continuously onto the display memory 7 in response to a clock from the timing generator 4. The contents of the display memory 7 are read sequentially, read code data are input into the character ROM 10A, and the outlining instruction signal Z is input into the vertical-direction outlining control circuit 8A and the horizontal-direction outlining control circuit 9. Thereby, the address decoder circuit 12 of the character ROM 10A generates address decode signals A1 through An shown in FIG. 15(C) corresponding to the input code data and the storage areas output character font data D1 through Dm shown in FIG. 15(D).
In other words, the vertical-direction outlining control circuit 8A outputs a precharge signal X1 shown in FIG. 15(B) which is set at an "L" level at the beginning of the single-character display time period. The bit lines BL1 through BLl of each storage area are precharged while the precharge signal X1 is at an "L" level. A character code from the display memory 7 is input into the character ROM 10A, whereby the address decoder circuit 12 of the character ROM 10A inputs into the storage areas 14a through 14m an address decode signal corresponding to the input character code from the address decode signals A1 to An shown in FIG. 15(C). Thereby, data corresponding to the address decode signal are output as character font data D1 through Dm shown in FIG. 15(D). In each storage area, the bit signals B1 to Bl are output sequentially upon each scanning in response to the display clock CK input from the timing generator 4 to the ROM output control circuit 13 of the character ROM 10A so that character font data D1 through Dl are sequentially read out upon each scanning.
Moreover, when the vertical-direction outlining control circuit 8A receives the outlining instruction signal Z, it outputs the precharge signal X3 shown in FIG. 15(E) which becomes "L" once at the beginning of the single-character display time period and twice near the end of the period, and precharges the data lines DL1 through DLm of the character ROM 10A while the precharge signal X3 is at "L". When the ROM output control circuit 13 outputs the bit signal B3 corresponding to the current scanning, for example, as shown in FIG. 15(G), data Q2 being scanned currently shown in FIG. 15(I) is output, and when it outputs the bit signal B2 shown in FIG. 15(F), data Q1 previously scanned (past) shown in FIG. 15(I) is output. Furthermore, as shown in FIG. 15(H), when the circuit 13 outputs the bit signal B4, data Q3 to be scanned next (future) shown in FIG. 15(I) is output. That is, data on dots above and below a display image area can be obtained along with data on the display image being scanned within the single-character display time period. The data Q1, Q2 and Q3 thus obtained are input into the horizontal-direction outlining control circuit 9.
At this time, the parallel/serial conversion circuit 9a for a character pattern receives only data Q2 upon input of data Q2 being scanned currently. The parallel/serial conversion circuit 9b for an outline pattern receives both data Q1 and Q3 upon input of data Q1 and Q3 scanned previously and to be scanned next, respectively.
As described in the foregoing, data of the parallel/serial conversion circuit 9a for a character pattern (or the parallel/serial conversion circuit 9b for an outline pattern) is supplied to the flip-flop F1 (or F4), the flip-flops F1, F2 and F3 (or F4, F5 and F6) operate reversely sequentially in response to the clock CK provided from the timing generator 4, and the flip-flop F2 outputs the character display signal SW. The output of the NOR circuit N1 to which the outputs of the flip-flops F1, F2 and F3 have been input and the output of the NOR circuit N2 to which the outputs of the flip-flops F4, F5 and F6 have been input are supplied to the NOR circuit N3, which outputs the outline display signal SE through the AND circuit A. Then, the character display signal SW and the outline display signal SE are supplied to the display control circuit 5 so as to control display such as display colors, and then to the unshown CRT.
In the case of scanning the position shown by the arrow in FIG. 10, data on the image display area, that is, data for obtaining an image, is supplied from the parallel/serial conversion circuit 9a for a character pattern to the flip-flop F1. Meanwhile, both data scanned previously and to be scanned next for obtaining the image, that is, data on dots above and below the image display area of FIG. 10, at rows 102 and 104, respectively, are supplied from the parallel/serial conversion circuit 9b for an outline pattern to the flip-flop F4. Thereafter, the time length of the outline display signal ST obtained as the output of the NOR circuit N3 and corresponding to data scanned previously, being scanned and to be scanned next is extended by the operation of the afore-mentioned horizontal-direction outlining control circuit 9 to enable the outline of an image in a horizontal direction thereof to be displayed. Therefore, the outline of an image in a vertical direction thereof can be displayed with both data scanned previously and to be scanned next, and the outline of the image in a horizontal direction thereof can also be displayed by extending the time length of these data.
In a case where a font for outline display is "1", the font is displayed as shown in FIGS. 16(A) through (C). When a position shown by an arrow is being scanned currently, the character display signal SW and the font are such as shown in FIG. 16(a). The outline display signal SE at this time and a pattern for outline display are such as shown in FIG. 16(b). An image displayed with the character display signal SW and the outline display signal SE is such as shown in FIG. 16(c) which illustrates the font "1" outlined in both vertical and horizontal directions thereof.
Since the conventional screen display device is structured as described above, it is necessary to read the character ROM three times within the single-character display time period for vertical-direction outline display, thus making it difficult to increase the speed of the device. Therefore, the device has the problem that it is inoperable at high display clock frequencies.