Integrated circuits (“ICs”) include many types of devices, some of which have programmable logic on board that can be configured to perform specified logic functions. One type of integrated circuit with programmable logic is a programmable logic device (“PLD”). One type of PLD is the field programmable gate array (“FPGA”), which typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. In CPLDs, configuration data is typically stored on-chip in nonvolatile memory. In some CPLDs, configuration data is stored on-chip in nonvolatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (“PLDs”), the functionality of the device is controlled by configuration data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in nonvolatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Semiconductor companies providing ICs such as PLDs have a responsibility of maintaining quality and reliability of their PLDs long after they leave the production test floor. End users may experience field failures or other malfunctions which may render the PLD inoperative. The cost of these failures is high both monetarily and also in terms of damaging the company's reputation for quality and reliability.
One way to mitigate the effects of PLD failures is to record PLD-specific data at various times during operation. However, since PLDs typically only contain static random access memory (“SRAM”), if the data is stored in the SRAM, then this data will be lost once the PLD is powered down. If the data is lost, then data, such as error data, cannot be used to mitigate the effects of the failure; for example, if the error data is lost, then the error data cannot be used to determine the reason for the PLD failure and resolve the bug or defect so that the failure does not reoccur.
For the foregoing reasons, it is desirable to record some types of data on an IC such that the data is not lost when the IC is powered down.