1. Field of the Invention
The present invention relates to a memory timing measurement circuit, a memory architecture, and a testing method thereof.
2. Description of Related Art
In memory test, how to correctly measure AC timing parameters is of great importance. Generally, AC timing parameters at least include a setup time parameter, a hold time parameter and an access time parameter.
In the past, tests of AC timing parameters are usually performed by an automatic testing machine (ATE). However, several disadvantages are caused.
(1) Due to high resolution, the ATE is not suitable for measuring the AC timing parameters of the memory. Generally, the resolution of the ATE can be up to 350 pico-seconds (ps); however, the AC timing parameters of memory may be merely several decades of ps. Thus, the accuracy of the measurement is easily reduced.
(2) Test signals sent by the ATE may have errors. When transmitted to a circuit board with a memory under test, the test signals pass routings and signal lines on the circuit, which causes greater errors (signal variations).
(3) It is difficult to know the true timing measurement value in the timing measurement. This is because the timing measurement value can merely be known from the ATE, and the signal timing inside the memory can merely be deduced from the measurement signal sent by the ATE.
(4) As the test signal, the control signal, and the clock signal are input from the outside of the memory, the number of the pins of the memory will be very large, which increases the chip area.
In order to overcome the above disadvantages, a memory timing measurement circuit, a memory architecture, and a testing method thereof are provided in the present invention.