The present application relates to non-planar semiconductor devices and methods of forming the same. More particularly, the present application relates to non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced and methods of forming the same.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, gate-all-around semiconductor nanowire field effect transistors (FETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor nanowire field effect transistors (FETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs. In its basic form, a semiconductor nanowire FET includes a source, a drain and one or more nanowire channels between the source and the drain. A gate electrode, which wraps around the one or more nanowire channels, regulates electron flow through the nanowire channel between the source and drain.
Despite being promising candidates for the end of the CMOS road map due to their excellent electrostatic control, semiconductor devices containing prior art gate-all-around semiconductor nanowires oftentimes sag and buckle due to gate stress or stress relaxation. Moreover, and for a gate last process, there are currently no good solutions to remove the sacrificial gate material under the semiconductor nanowires.