1. Field of the invention
The present invention relates to a method of reading a flash memory cell and a read voltage generating circuit which can perform a stable read operation regardless of a power supply voltage and can also perform a read operation rapidly when a program or an erase operation mode is shifted to a read mode.
2. Description of the Prior Art
FIG. 1 shows a structure of a conventional flash memory cell. A power supply voltage Vcc is applied to a gate VG. In this case, the threshold voltage Vt of a program cell becomes a program voltage Vcc+1V. That is, when a program operation is performed with a low voltage, the program threshold voltage can be reduced in proportion to the low voltage. However, if a read operation is performed for this cell with a high power supply voltage Vcc, there is a problem that a read speed is degraded or defect cells is caused, thereby lowering read margins.
Also, when a read operation of a split gate type flash memory cell is performed, since a power supply voltage Vcc is applied to a select gate and a control gate, read margins are varied in proportion to variation of a power supply voltage Vcc.