1. Field of the Invention
This invention relates generally to the shared usage of memory by a plurality of agents, i.e., processors. In particular, in one aspect it relates to the efficient use of shared synchronous memory by a plurality of agents, and in another aspect it relates to the flexible partitioning of shared memory between a plurality of agents.
2. Background of Related Art
With the ever-increasing speeds of today's processors, memory designs have attempted to meet the required speed requirements. For instance, synchronous memory such as synchronous static random access memory (SSRAM) and synchronous dynamic random access memory (SDRAM) are commonly available synchronous types of memory.
Synchronous memory technology is currently used in a wide variety of applications to close the gap between the needs of high-speed processors and the access time of asynchronous memory such as dynamic random access memory (DRAM). Synchronous memory, e.g., SDRAM technology, combines industry advances in fast dynamic random access memory (DRAM) with a high-speed interface.
Functionally, an SDRAM resembles a conventional DRAM, i.e., it is dynamic and must be refreshed. However, the SDRAM architecture has improvements over standard DRAMs. For instance, an SDRAM uses internal pipelining to improve throughput and on-chip interleaving between separate memory banks to eliminate gaps in output data.
The idea of using a SDRAM synchronously (as opposed to using a DRAM asynchronously) emerged in light of increasing data transfer demands of high-end processors. SDRAM circuit designs are based on state machine operation instead of being level/pulse width driven as in conventional asynchronous memory devices. Instead, the inputs are latched by the system clock. Since all timing is based on the same synchronous clock, designers can achieve better specification margins. Moreover, since the SDRAM access is programmable, designers can improve bus utilization because the processor can be synchronized to the SDRAM output.
The core of an SDRAM device is a standard DRAM with the important addition of synchronous control logic. By synchronizing all address, data and control signals with a single clock signal, SDRAM technology enhances performance, simplifies design and provides faster data transfer.
Similar advantage hold for other types of synchronous memory, e.g., SSRAM or even synchronous read only memory.
Synchronous memory requires a clock signal from the accessing agent to allow fully synchronous operation with respect to the accessing agent. If more than one agent is given access to a shared synchronous memory, each agent must conventionally supply its own clock signal to the synchronous memory. Unfortunately, the clock signals from separate agents are not conventionally synchronous or in phase with one another. Therefore, if a synchronous memory were to be shared among a plurality of agents, delays or wait states would be required to allow an error-free transition between access by the first agent having a first synchronous memory access clock signal and a subsequent access by another agent having a different synchronous memory access clock signal.
Some synchronous memory devices have the capability to provide burst input/output (I/O), particularly for the optimization of cache memory fills at the system frequency. Advanced features such as programmable burst mode and burst length improve memory system performance and flexibility in conventional synchronous memories, and eliminate the need to insert otherwise unnecessary wait states, e.g., dormant clock cycles, between individual accesses in the burst.
Conventional SDRAM devices include independent, fixed memory sections that can be accessed individually or in an interleaved fashion. For instance, two independent banks in an SDRAM device allow that device to have two different rows active at the same time. This means that data can be read from or written to one bank while the other bank is being precharged. The setup normally associated with precharging and activating a row can be hidden by interleaving the bank accesses.
There are limitations to conventional system designs using synchronous memory. For instance, wait states are inevitable and necessary when the shared synchronous memory adjusts for access by a different agent having a different clock signal.
For instance, FIG. 5 shows a conventional circuit for allowing, e.g., three agents 502–506 to access a shared synchronous memory block 508. Each agent 502–506 may be a suitable processor, e.g., a microprocessor, a microcontroller, or a digital signal processor (DSP). As shown in FIG. 5, the processors 502–506 provide read and/or write access to the shared synchronous memory block 508.
As may be appreciated, memory accesses by the separate agents 502–506 would clash unless they are arbitrated to allow only one agent to access the synchronous memory 508 at any one time. Thus, selection logic (i.e., an arbitrator 512) is conventionally provided to control a multiplexer 510, which selects the appropriate address for presentation to the synchronous memory 508, data and control (ADC) signals and clock signal from a current ‘owner’ of the busses. Typically, the agents 502–506 are assigned a hierarchy in which the highest priority agent will own the busses to the synchronous memory 508 and block out accesses by the other agents until finished.
Unfortunately, in such a system as is shown in FIG. 6, if the relative speeds of the agents 502–506 vary and/or the relative phase of the clock signals from each of the respective agents 502–506 varies with respect to one another, accesses to the synchronous memory 508 may necessarily include wait states. Wait states decrease the overall speed of accesses to the synchronous memory 508 and result in decreased performance.
Moreover, as background to another aspect of the invention, a plurality of separate memory systems 600 may be provided as shown in FIG. 6, using one or more arbitrators 612 to authorize access to the respective separate memory blocks 508a, 508b by the separate agents. However, the memory block 508a must be sized with respect to the maximum required amount of memory by the pre-defined groups of accessing agents 602–606, and the memory block 508b must be sized with respect to the maximum required amount of memory by the pre-defined groups of accessing agents 622–626. However, in practice, the synchronous memory blocks 508a, 508b are less than fully utilized, thus wasting memory. Moreover, if a particular use or application of the device uses one agent but not others, the memory pre-defined for use by the unused agent is wasted.
There is thus a need for synchronous memory systems which in one aspect allow efficient use of synchronous memory resources, e.g., by reducing the use of wait states. Moreover, there is also a need for memory systems which in another aspect allow efficient usage of shared memory with respect to adjusting for accesses by a plurality of accessing agents.