With the rapid development of semiconductor manufacturing technology, semiconductor devices have been developed in the direction of higher component density and higher integration level. As basic semiconductor devices, transistors are currently being widely used. With the increase of the component density and integration level, the gate size of transistors has become shorter than ever. However, decreasing the gate size could cause a short channel effect, and leakage current may be generated. Thus, the electrical properties of semiconductor devices are affected. Currently, the prior art methods to improve the performance of semiconductor devices mainly depends on increasing the carrier mobility. When the carrier mobility is increased, the drive current of a transistor increases; and the leakage current decreases. Increasing stress in the channel region of a transistor is a key to improve the carrier mobility. Therefore, increasing the stress in the channel region of a transistor may significantly improve the performance of the transistor.
Forming a stress layer in the source region and drain region is one of the several approaches to increase the carrier mobility of the channel region of a transistor because the stress layer may induce stress to the channel region of the transistor. The stress layer of the PMOS transistor may be made of silicon germanium (SiGe). Silicon germanium and silicon share a same lattice structure, i.e., a “diamond” configuration, and at room temperature, the lattice constant of silicon germanium is larger than that of silicon. Therefore, there is a crystal lattice mismatch between silicon and the embedded silicon germanium structures. Such a mismatch may provide a compressive stress to the channel region of the transistor; and thus improve the carrier mobility of the channel region. Similarly, the stress layer of the NMOS transistor may be made of silicon carbide (SiC). At room temperature, the smaller lattice constant of silicon carbide than silicon causes a crystal lattice mismatch between silicon carbide and silicon. Therefore, a tensile stress may be generated to the channel region of the transistor, the carrier mobility of the channel region may be increased; and the performance of the NMOS transistor may be enhanced.
However, the existing transistor having a stress layer in the source region and the drain region have certain issues, such as the quality of morphology, and the stability of performance, etc. The disclosed device structures and methods are directed to at least partially solve one or more problems set forth above and other problems.