1. Field of the Invention
The invention relates to mask programmable integrated circuits (ICs). More particularly, the invention relates to mask programmable ICs manufactured to emulate Field Programmable Gate Arrays (FPGAs).
2. Description of the Background Art
An FPGA is a user-programmable device that can be programmed in the field and then reprogrammed with the same or a different bitstream, to perform the same or a different function. An FPGA therefore must be capable of producing a large variety of logical behaviors. This flexibility has its price in terms of silicon area, i.e., an FPGA performing any of several functions typically has a higher monetary cost than a device that is capable of performing only a single function. Therefore, when a system including an FPGA reaches the point where it is considered unlikely to change, a manufacturer sometimes removes the FPGA from the system, and replaces the FPGA with a pin-, timing- and function-compatible replacement that can only perform the single function necessary in the system. Buch et al describe such a device in U.S. Pat. No. 5,550,839, xe2x80x9cMask-Programmed Integrated Circuits Having Timing and Logic Compatibility to User-Configured Logic Arraysxe2x80x9d, which is incorporated herein by reference and title to which is held by the assignee hereof. One such pin-, timing- and function-compatible replacement for an FPGA is the HardWire(trademark) device from Xilinx, Inc., described in the xe2x80x9cHardwire Data Bookxe2x80x9d (hereinafter referred to as xe2x80x9cthe Hardwire Data Bookxe2x80x9d), published 1994, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which is incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.) The term xe2x80x9cHardWire devicexe2x80x9d is used herein to describe a mask programmable IC capable of performing the same logical functions as a programmable IC that is not mask programmable, such as an FPGA or a PLD. The term xe2x80x9cmask programmable ICxe2x80x9d is used herein to describe an IC having many processing layers, the first several layers being common to all versions of the IC, and some or all of the remaining layers (typically including some or all of metal layers, via layers, and contact layers) being specific to a given IC manufactured for a specific purpose. Thus, the upper layers of the device are used to xe2x80x9cprogramxe2x80x9d the device to this specific purpose. A xe2x80x9cprogrammed HardWire devicexe2x80x9d is a HardWire device that has been processed to add the programmable mask layers.
Ideally, a HardWire device can emulate the FPGA it replaces in all system functionality, such that the replacement is transparent to the system. Therefore, the HardWire device should not only perform the same functions that were previously performed by the configured FPGA, but should also emulate the FPGA during the configuration process. An exception to this rule is when the FPGA configuration process did not involve other parts of the system (e.g., configuration was under the control of the FPGA), in which case configuration can sometimes be skipped without affecting system functionality. Another exception is when the system is altered at the time of the FPGA/Hardwire replacement so that configuration is no longer performed.
A method used by Xilinx, Inc. to produce one type of HardWire device comprises virtually duplicating the architecture of the FPGA to be replaced, but replacing the software programmable configuration memory cells with mask programmable connections. The removal of the configuration memory cells significantly reduces the required silicon area, and therefore reduces the cost of the devices. Making the devices mask programmable allows much of the design and processing to be done only once for each FPGA product, e.g., once for the XC4003 device, once for the XC4005 device, once for the XC5202 device, etc. Top-level processing layers specific to the user""s design are then added to customize the behavior of the HardWire device to match the functional behavior of the emulated FPGA as configured in the user""s system. (The term xe2x80x9cemulated FPGAxe2x80x9d is used herein to mean the FPGA being replaced by the HardWire device.) When this method is used, the configuration behavior of the FPGA is emulated, as well as the behavior after configuration.
Since the FPGA architecture is virtually duplicated in this type of HardWire device, both the FPGA configurable logic block (CLB) making up the core logic array and the FPGA input/output block (IOB) must be redesigned for the HardWire device. (The term xe2x80x9cIOBxe2x80x9d as used herein refers to the FPGA I/O block and does not apply to the I/O cell of the HardWire device. The I/O cell of the HardWire device may be an input cell, an output cell, or a bidirectional input/output cell.) Although this approach leads to a HardWire device that closely resembles the emulated FPGA in timing and input/output (I/O) characteristics, the redesign procedure must be individually performed for each FPGA product family, since the architecture differs in each family. (The term xe2x80x9cI/O characteristicsxe2x80x9d is used herein to mean AC and DC characteristics associated with the I/O. AC characteristics include rise and fall times and delays on both inputs and outputs. An example of DC characteristics is provided for the Xilinx XC4000E family of FPGAs on page 4-80 of the Xilinx 1996 Data Book entitled xe2x80x9cThe Programmable Logic Data Bookxe2x80x9d (hereinafter referred to as xe2x80x9cthe Xilinx 1996 Data Bookxe2x80x9d), published Sep. 1996, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which page is incorporated herein by reference.)
As a result of the extensive redesign required for both Configurable Logic Blocks (CLBs) and I/O Blocks (IOBs) of multiple FPGA product families, the redesign process (i.e., the design of HardWire replacements) incurs a high development cost. Additionally, a different HardWire product is required for each FPGA family as well as for devices of varying sizes, leading to a large number of products. These products must be separately manufactured, stored, sold, and supported by conversion software. (The term xe2x80x9cconversion softwarexe2x80x9d, is used herein to mean software that converts a user""s description of an FPGA design, such as a netlist, to a description that can be used to prepare masks for a mask programmed HardWire device.)
A second approach to manufacturing mask programmed replacement devices eliminates this undesirable overhead, but introduces other drawbacks. According to this method, a commercially available gate array is used to replace the FPGA, rather than designing a new mask programmable device. (The word xe2x80x9cgate arrayxe2x80x9d is used herein to mean a mask programmable IC comprising a core array of programmably interconnected transistors or gates and a set of input/output (I/O) cells. A gate array differs from an FPGA not only in being mask programmable, but also in the granularity of the core array, the basic repetitive element of the gate array core being a transistor, a gate, or a set of programmably interconnected transistors or gates rather than comprising larger blocks which may include lookup tables or flip-flops as in FPGAs. Some gate arrays also have RAM blocks or other specialized blocks in the core in addition to the basic repetitive element.)
This approach has the advantages of being low in cost, due to the elimination of the redesign process, and providing ready conversion, since the company that originally designs the gate array also typically provides software to implement a user""s design in the gate array. However, a disadvantage of this method is that the I/O characteristics of the gate array are usually different from those of the FPGA, often sufficiently different to cause problems when the FPGA is removed from the system and the gate array is substituted. Special features of the FPGA I/O (such as a low slew-rate option, optional delay on the input, etc.) are typically lost in the conversion as well. An additional problem is that the gate array is incapable of emulating the configuration behavior of the FPGA unless the configuration logic is duplicated in the logic gates of the core, which results in fewer core logic gates available for the converted design. A circuit and method for maintaining the configuration process in such a HardWire device are described by Glenn A. Baxter in U.S. Pat. No. 5,870,586, entitled xe2x80x9cConfiguration Emulation of a Programmable Logic Devicexe2x80x9d, which is incorporated herein by reference. Similarly, boundary scan is also unavailable in gate arrays unless implemented in core logic gates. Implementing boundary scan in core logic gates uses about 72 gates per boundary scan cell, a very high cost in silicon area.
Therefore, it is desirable to have a programmable IC capable of emulating an FPGA, while closely matching the I/O characteristics, special features, configuration behavior, and boundary scan capability of the emulated FPGA. It is further desirable to have a single programmable IC capable of emulating any of a multiplicity of FPGAs.
According to a first aspect of the invention, a hybrid HardWire device is provided that comprises a gate array core and a set of mask programmable I/O cells having I/O characteristics similar to those of the FPGA, i.e., sufficiently the same so the HardWire device can be used as a drop-in replacement for the FPGA with no redesign of the original system. A user""s design originally implemented in an FPGA can be emulated in the HardWire device, which then replaces the FPGA in the same board at a lower cost.
In another embodiment, the I/O cells are programmable such that they can emulate the I/O characteristics of FPGAs from any of two or more FPGA families. The I/O cells may be mask programmable or programmable by other means such as configurable memory cells or fuses. This ability reduces the number of separate devices that must be designed, manufactured, tested, stored, and sold, and also simplifies the software required to convert designs to the new device.
According to a second aspect of the invention, a mask programmable IC is provided that includes dedicated boundary scan logic in the I/O cells. Valuable core logic resources therefore need not be consumed to implement boundary scan logic. In one embodiment, one boundary scan cell is provided per I/O cell. In another embodiment, two boundary scan cells (blocks of logic) are provided for each I/O pad, each cell alone being capable of providing the boundary scan functions associated with one FPGA I/O pad. This embodiment provides great flexibility in emulating any of several FPGAs in any of several packages. By selectively choosing which of the boundary scan cells are included in the boundary scan data chain, the order of the boundary scan chain of the emulated FPGA in any of two or more packages can be reproduced. Boundary scan behavior is therefore emulated as well as the programmed logic behavior of the FPGA. In another embodiment, more than two boundary scan cells are provided per I/O cell.
In one embodiment, additional programmable interconnect lines accessing each boundary scan cell are provided. These interconnect lines can be used to programmably connect the data output of a first cell to the data input of second cell which need not be adjacent to the first. In another embodiment, programmable interconnect lines are provided from the data inputs and outputs of the boundary scan cells to the core logic to provide the possibility of connection through the core or to other logic in the core.