Circuitry in state-of-the-art semiconductor chips may be organized into selected regions, blocks or modules containing transistors and other circuit components, such as diodes, resistors, and capacitors, for example. The modules may be separated by channels through which electric wires pass between electric terminations or pins in the modules. The electric wires may be routed through the channels and over or under the modules themselves in separate layers, depending upon the design rules followed by the particular semiconductor chip. Intermediate levels of organization in the modules may include the use of standard cells, for example. In such standard cells, the design and its components are specifically predetermined, and, thus, the circuit characteristics, such as delay times for propagation of a signal through the particular standard cell are well known. Transistors and circuit components may also be organized into non-standard or custom cells which can be referred to as "leaf cells." This terminology is used in the semiconductor industry by analogy to how a tree grows from its trunk into branches and ultimately into leaves, at which photosynthesis takes place. Similarly, the basic circuit chip includes circuitry (the tree) which includes modules (the branches) which are organized into leaf cells (the leaves) which perform circuit activities. Simply stated, the leaf cells are at the lowest level of circuit organization above the transistors and other basic circuit elements. The standard cells themselves can be considered to be leaf cells as well.
The placement of leaf cells within electric circuit modules to be fabricated in semiconductor chips is dependent upon the capacitance between leaf cells connected by electric circuit wires and upon the actual worst case delay of signal propagation through particular leaf cells. The capacitance between particular pins on leaf cells to be connected is a function of the length of the connecting wire as well as its per-unit capacitance. Such capacitance can be determined in conventional manner, but there is wide variation between different kinds of leaf cells in terms of actual signal delays through the particular custom circuitry designed into the leaf cell.
The determination of leaf cell delays supports transistor level timing-driven place and route operations pursued in the course of developing a semiconductor chip to be fabricated. In standard cells and gate arrays, the delays between inputs and outputs of a particular group of transistors is pre-characterized and delay expressions are readily available, permitting completion of design operations leading to chip manufacture without extensive engineering efforts or without suffering considerable design errors.
Existing approaches for transistor level place and route operations depend upon representation of the electric circuitry for delay determination with a simple resistor and capacitor network, for example. Such an approach is not sensitive to input and state conditions and patterns occurring in the actual electric circuitry in particular leaf cells.