The present invention relates to a semiconductor memory having redundancy and, more particularly, to a semiconductor memory suited for high-level integration.
In the semiconductor memory having redundancy according to the prior art, an address compare method has been employed, as is discussed in ISSCC (1985) "Digest of Technical Papers", pp. 48 to 49, "64 Kb ECL RAM with Redundancy". This address compare method will be described in the following with reference to FIG. 1.
FIG. 1 shows a structure of a semiconductor memory having redundancy employing the address compare method. An X-address signal and a Y-address signal are decoded by an X-decoder 101 and a Y-decoder 102, respectively, so that one of memory cells is selected from a memory cell array 105. A read data from the memory cell selected is sensed by a sense circuit 107 so that output data D/O is outputted. In case a fault memory cell is found in the memory cell array 105, on the other hand, address data for selecting the fault memory cell is written in a PROM (which is the abbreviation of Programmable Read Only Memory) 104. Then, the address data inputted and the address data coming from the PROM 104 for selecting the fault memory cell are compared by an address comparator 103. In order that the memory cell array may not be selected when the two address data are coincident, a select prohibition signal SD is outputted to the decoder 101, and at the same time a spare word line 106 is selected to relieve the fault bit. Incidentally, FIG. 1 shows only the spare word line 106, but a spare bit line may also be provided in a column direction.
According to the address compare method, however, an (m.times.n) number of address comparators and PROMs have to be provided if the number of the address inputs in the row (or column) direction is designated at m whereas the number of the rows (or columns) of the spare rows (or columns) is designated at n. As a result, the address compare method obstructs the high-level integration due to its large power dissipation and chip size.
In Japanese Patent Laid-Open No. 57-198599, on the other hand, there is also disclosed a memory having redundancy. This technique has failed to give positive treatment to the fault bit word lines so that it has been unable to prevent other cells from being adversely affected. Since the redundant program has been executed by the signal lines leading to the word lines, moreover, the high-speed action has been obstructed by the accordingly high resistance.