Memory technology implies the need for accessing data within memory devices, such as DRAM or other memory devices. Therefore, different addressing strategies have already been proposed.
A possible feature of DRAMs is address multiplexing. This technique enables splitting the address in half and feeding each half in turn to the chip on the address bus pins.
The chip has a large array of memory capacitors that are arranged in rows and columns. To read one location in the array, the control circuit first calculates its row number, which it places on the DRAM's address pins. It then toggles the row address select (RAS) pin, causing the DRAM to read the row address. Internally, the DRAM connects the selected row to a bank of amplifiers called sense amplifiers, which read the contents of all the capacitors in the row. The control circuit then places the column number of the desired location on the same address pins, and toggles the column address select (CAS) pin, causing the DRAM to read the column address. The DRAM uses this to select the output of the sense amplifier corresponding to the selected column. After a delay called the CAS access time, this output is presented to the outside world on the DRAM's data I/O pin.
To write data to the DRAM, the control logic uses the same two-step addressing method, but instead of reading the data from the chip at the end of the operation, it provides data to the chip at the start of the operation.
After a read or write operation, the control circuit returns the RAS and CAS pins to their original states to ready the DRAM for its next operation. The DRAM requires a certain interval called the precharge interval between operations.
Once the control circuit has selected a particular row, it can select several columns in succession by placing different column addresses on the address pins, toggling CAS each time, while the DRAM keeps the same row activated. This is quicker than accessing each location using the full row-column procedure. This method is useful for retrieving microprocessor instructions, which tend to be stored at successive addresses in memory.
In addition, the provision of commands is typically provided through command strobes on the command bus. The number of different commands depends on the number of pins on the command bus with 2N commands being a possibility with N being the number of pins at the command bus. With the increasing demand for different commands, the command bus needed to be expanded. However, as die size is a crucial factor in application specific integrated circuit (ASIC) design, the number of pins on the command bus needs to be decreased.
Further, the size of the buses is also relevant for the overall size of the connection interface between the memory device and the central processing unit (CPU). The higher data rates that were required, the higher the number of connection pins on the data bus were selected. This increased the size of the interface. In addition, the number of pins on the address bus and the overall number of pins of the interface determined the type of memory to be used on the interface, besides protocol issues. However, the demand for flexibility of usage of different kinds of memory devices was not accounted for. There is a need for a flexible interface, which enables the use of different kinds of memory devices with different kinds of capabilities in terms of data throughput on the data bus.
With the rising need for flexible use of standard components, there is a need for providing a memory interface enabling to use both volatile memory and non-volatile memory on one same interface. However, as non-volatile memory and volatile memory have different prerequisites for the interfaces, there needs to be a possibility to adapt the interface for use with both types of memory.