In order to explain the prior art and the present invention, an equivalent logic circuit according to an example register comprised of latches will first be described with reference to FIG. 5. As shown, the register 1 comprises two latches 1a and 1b, a selector 1c for selecting an input, and OR gates 1d and 1e for respectively feeding two kinds of clocks to the latches 1a and 1b, and further has a data input terminal 1f, a scan input terminal 1g, a mode change input terminal 1h for changing the mode between normal mode and scan mode, clock input terminals 1i and 1j, scan clock input terminals 1k and 1l, a data output terminal 1m and a scan output terminal 1n which may also serve to output data. When the latch 1b is exclusively used for scanning purposes, the OR gate 1e and the clock input terminal 1j will be unnecessary.
FIG. 6 is a block diagram showing an arrangement of a scan path used in the conventional data processing unit. As shown, reference numeral 8 indicates an LSI, or printed circuit board, or a combination thereof which may constitute the data processing unit. The system 8 has a plurality of registers 1 as described above, reference numeral 2 denoting a scan input terminal, 3 a scan output terminal, 4 an input terminal for changing the mode between normal mode and scan mode, 5 a scan A clock input terminal, and 6 a scan B clock input terminal. Registers 1 are each connected to each of the input and output terminals as shown while the scan output terminal 1n of a preceding stage register 1 is sequentially connected to the scan input terminal 1g of the next stage register 1 to form a scan path.
The operation of the above-described system is described hereinafter by referring to FIGS. 5 and 6. The operation is split into normal and scan modes. These modes are switched in accordance with the value applied to the mode change input terminal 4 which may be controlled by a service processor.
In normal mode, each clock applied to the scan A clock input terminal 5 and the scan B clock input terminal 6 are set to be turned off. Data are set into the latch 1a from the data input terminal 1f of each register via the selector 1c by the clock from the clock input terminal 1i. If the OR gate 1e and the clock input terminal 1j are present and a clock has been fed to this clock input terminal 1j, the value in the latch 1a is transferred to the latch 1b.
In scan mode, A clock and B clock which alternately into a significant state are applied to the scan A clock input terminal 5 and the scan B clock input terminal 6 respectively, and accordingly the scan clock input terminals 1k and 1l of each register 1 are alternately switched into a significant state. As the same time, scan data is applied thereto from the scan input terminal 2 and is passed through the scan input terminal 1g, and the latches 1a and 1b of the first stage register 1 are sequentially set to the latches 1a and 1b through the scan input terminals 1g of the next stage register etc. At the same time, the value of each register 1 is transmitted through the scan output terminals 1n and 3 to be taken out to the exterior. During the scan, the clocks set to off-state.
Meanwhile, a reset operation is conducted as follows. The clocks applied to the clock input terminals 1i and 1j of each register 1 are previously set to off-state, the mode change input terminal 4 is set to the scan mode and the scan input terminal 2 is set to "0". Next, the clocks applied to the scan A clock input terminal 5 and the scan B clock input terminal 6 are both set to on-state. Since the data directly passes through the latch when the clocks are turned on, "0"input from the scan input terminal 2 will be sequentially transmitted through the registers 1. Since the propagation speed is only retarded by the gate delay, the reset operation can be processed at a speed 100 to 1000 times as high as in the above-described scan mode operation where the clocks are alternately applied. After the value of "0" has been propagated to all of the registers 1, the clocks applied to the scan A clock input terminal 5 and the scan B clock input terminal 6 are turned off, and all of the registers 1 are set to "0" and the reset action is completed.
Since the conventional reset system has the arrangement described above, resetting all registers to "0" can be done at high-speed, but it has been necessary when resetting to a pattern including "1" to resort to an operation of applying the clocks alternately, as described-above, which has made it difficult to achieve a fast reset action. In general, if odd parity is used as a parity bit, the need arises to reset to a pattern including "1".