1. Technical Field
Embodiments of the present disclosure may generally relate to a repair device and a semiconductor device including the repair device, and more particularly to post package repairs (PPRs).
2. Related Art
A semiconductor memory device includes a large number of memory cells integrated into one chip. However, if a defective or failed cell occurs in at least one memory cell from among a plurality of memory cells, it is impossible for a semiconductor memory device to operate normally. As a result, the semiconductor memory device having the defective cell is regarded as a defective product and abandoned. Semiconductor memory devices have been developed to have higher degrees of integration and operate at higher speeds, however higher degrees of integration and operating speeds increase the possibility of defective cells. Provided that the entirety of the semiconductor device is discarded due to a defect generated in only a few memory cells among all memory cells contained in the semiconductor memory device, the discarding of the entirety of the semiconductor memory device is cost ineffective and is far from productivity efficiency.
As a result, a production yield denoted by the ratio of a total number of chips to the number of normal chips, which is needed for deciding production costs of semiconductor memory devices, is gradually reduced. Therefore, in order to increase a production yield of semiconductor memory devices, many developers and companies are conducting intensive research into a method for fabricating highly-integrated semiconductor memory devices configured to operate at higher speeds and a method for efficiently repairing defective cells.
Generally, the semiconductor memory device includes a redundancy memory cell. When defective or failed memory cells occur after completion of such packaging, the defective memory cells are replaced with redundancy memory cells, such that the semiconductor memory device can be processed as a normal product. A method for replacing defective memory cells with redundancy memory cells after completion of a test in the packaged state is referred to as a post package repair (PPR).
The post package repair (PPR) technology can repair defective memory cells that are not discovered in a wafer state and generated after packaging completion, using an electrical fuse (e.g., array E-fuse: ARE), such that package productivity can increase through the post package repair (PPR) process.