The present invention is directed to a circuit compensation technique and more particularly, the present invention is directed to a stable predictable circuit compensation technique which is relatively insensitive to noise.
Due to their increased complexity and higher speed, high frequency processors and chipsets have become more sensitive to process, supply voltage, and temperature (PVT) variations. Accordingly, it has become necessary to compensate critical circuits for these variations. Thus, on-die terminations, I/O pre-drivers, and timing control circuits, etc., must be compensated since they affect signal reflections, transmission and reception timings, and edge rates. These circuits are often compensated by comparing the resistance of an external resistor to the resistance of an internal circuit. That is, for each kind of circuit, a separate external resistor may be used to compensate for each of the required attributes, such as, impedance, slew-rate, timing, etc.
Once the internal resistance has been matched to the external resistor, a certain digital code, commonly referred to as the reference code, is used to represent the matched internal resistance. A set of these reference codes is easily used either directly or indirectly to compensate the circuits noted above. The matching technique consists of providing a feedback loop for matching the external resistor to the internal resistance. The reference code is continually updated. External noise may result in an updated reference code which differs from the old reference code by a large amount. Since the circuit characteristics that are being compensated vary slowly over time, there should not be large changes between reference code updates.
As illustrated in FIGS. 1 and 2, the compensation of critical circuits with respect to PVT is performed utilizing an external resistor to match the on-chip compensation circuit resistance. The internal resistance consists of a parallel combination of transistor legs, often referred to as dummy legs. These dummy legs may be identical to the actual transistor legs used in each circuit to be compensated.
The matching of the on-chip resistance to the external resistor is performed by turning on the transistor legs of the dummy device (shown as a dummy buffer 110 in FIGS. 1 and 2) until the effective on-chip resistance of the circuit is approximately equal to that of the external resistor 120. At that point, the analog comparator 150 trips and the number of transistor legs that have been turned on it is recorded in the up/down counter 180. The same number of transistor legs are then turned on in the actual circuit to be compensated.
FIG. 1, noted above, illustrates a simplified block diagram of a closed loop compensation circuit and FIG. 2 illustrates the details of the dummy buffer 110 of FIG. 1 and FSMs (Finite State Machines) 1xe2x88x92n, where n is the number of circuits to be compensated. The dummy buffer 110 and external resistor 120 form a voltage divider whose output is then compared in the analog comparator 150 with the output of a voltage divider formed by resistors R1 and R2 after both outputs have passed through respective low pass filters 130 and 140. The output of the analog comparator 150 is inputted to the latch 160 which receives a latching signal fsample. The output of the latch 160 is inputted to the up/down counter 180 after passing through another low pass filter 170. The up/down counter 180 also receives a signal labeled fupdate. While the counter 180 has for exemplary purposes been shown as being incremented, it can also be decremented. Since the circuit of FIG. 1 is a closed loop feedback system, care must be taken to insure a stable system and feedback stability issues governed by control theory add to the complexity of the compensation circuit. Typically, the update frequency fupdate must be lower than the 1/RC frequency of the low pass filters which in turn must be lower than the sampling frequency fsample. While this criteria may appear at first to be easy to meet, the low pass filters 130 and 140 of the analog comparator 150 are highly PVT dependent and it is therefore sometimes difficult to simulate their behavior.
Several variations of the above-noted arrangement have been used in both open-loop and closed-loop forms. Close-loop systems have the classical stability problems while the open-loop systems unfortunately have large variations in the reference code. Stability problems can be reduced at the cost of increased to design/debug cycles since a significant amount of time is required to insure closed loop stability. On the other hand, open-loop systems avoid stability issues at the cost of large variations in the reference code updates.