1. Field of the Invention
This disclosure relates to semiconductor devices and, more particularly, to a semiconductor device having self-aligned contact holes on a semiconductor substrate and a method of fabricating the same.
2. Description of the Related Art
With the increase of an integration density of semiconductor memory devices, including a DRAM, new technologies for fabricating them have been studied. A contact technology among them has become more important in fabrication of highly-integrated semiconductor devices.
Recently, a self-aligned contact technology has been widely used, which is suitable for Fabricating highly-integrated semiconductor devices. A conventional process for fabricating the semiconductor devices using the self-aligned contact technology is as follows.
First, the conventional process includes providing a semiconductor substrate which has a cell array region and a peripheral circuit region. The cell array region and the peripheral circuit region have a plurality of word line patterns and at least one gate pattern, respectively. Each of word line patterns includes a word line and a capping insulating layer pattern stacked sequentially. The gate pattern also includes a gate electrode and a capping insulating layer pattern stacked sequentially.
The word line patterns and the gate pattern are used as ion implantation masks to implant impurity ions into the semiconductor substrate, and then to form low concentration source/drain regions in the semiconductor substrate. A spacer layer is formed on an upper surface of the semiconductor substrate having the low concentration source/drain regions. The spacer layer is anisotropically etched to form word line spacers and gate spacers on side walls of the word line patterns and on side walls of the gate pattern, respectively. The gate spacers are used in order to optimize a source/drain structure of a MOS transistor, that is, an LDD type source/drain structure formed in the peripheral circuit region. Accordingly, the width of the gate spacer maybe determined considering the MOS transistor characteristics.
The gate pattern and the gate spacers are used as ion implantation masks to implant impurity ions into the semiconductor substrate of the peripheral circuit region, and to form high concentration source/drain regions. As a result, the MOS transistors having the LDD type source/drain regions are formed in the peripheral circuit region.
An interlayer insulating layer is formed on an upper surface of the semiconductor substrate having the LDD type source/drain regions. The interlayer insulating layer is patterned to form a self-aligned contact hole penetrating a region between the word line patters. In this case, the capping insulating layer patterns and the word line spacers function as etching stop layers when the self-aligned contact hole is formed.
According to the conventional self-aligned contact technology, each of the gate spacers has the same width as that of each of the word line spacers. Also, the gate spacers maybe formed to have a desired width in order to optimize the MOS transistor characteristics formed in the peripheral circuit region. For example, in case of decreasing the width of each of gate spacers, the source/drain region of the MOS transistor has an abrupt impurity profile such that the reliability of the MOS transistor, including a hot carrier effect, is deteriorated. On the contrary, if the width of the gate spacers is increased, the width of the word line spacers is also increased such that a lower diameter of the self-aligned contact hole is reduced. Accordingly, the increase of the width of the gate spacers brings about a self-aligned contact fail. Therefore, it is not easy to optimize the characteristics of the MOS transistor and the self-aligned contact.
On the other hand, U.S. Pat. No. 6,159,806 to Horng-Nan Chern (the '806 patent) discloses a method of increasing the width of a spacer. According to the '806 patent, the method includes forming gate patterns of an interior circuit and a peripheral circuit on the semiconductor substrate. N− type regions are formed in the semiconductor substrate having the gate patterns. Next, gate spacers are formed on side walls of the gate patterns. A first dielectric layer is formed on the semiconductor substrate having the gate spacers. A photoresist layer is coated on the semiconductor substrate having the first dielectric layer. The photoresist is patterned by using a photolithographic process to open semiconductor substrate having the gate pattern on the peripheral circuit. Next, N+ type impurity ions are implanted into the semiconductor substrate to form N+ type regions overlapping with an edge portion of the gate spacer. The photoresist layer is removed after the N+ type impurity ions are implanted into the semiconductor substrate. A second dielectric layer is formed on the semiconductor substrate having the N+ type regions. The first and second dielectric layers are sequentially etched to form contact holes in the two layers, which are aligned with the gate patterns of the interior circuit and the peripheral circuit. At this time, the N+ type regions are formed to overlap with the edges of the gate patterns of the peripheral circuit, by using the gate spacers and the first dielectric layer. Accordingly, with the first dielectric layer, an effective channel length can be increased by a thickness of the first dielectric layer under the gate pattern of the peripheral circuit.
However, the method provides that the contact hole formed between the gate patterns under the given state that pitch of the gate patterns is fixed in the interior circuit. Moreover, the contact hole is formed after the gate spacers have been formed on the side walls of the gate pattern. Accordingly, the above-described method can deteriorate the resistance of the contact holes if the design rule of the gate patterns is further reduced.
Embodiments of the invention address these and other disadvantages of the conventional art.