FIG. 1 is a perspective diagram of a conventional multi-phase switching power system 10, and FIG. 2 is a typical waveform diagram of the switching power system 10. The switching power system 10 is operative to provide a regulated output voltage Vcore supplied to other electronic devices, for example a central processing unit (CPU). In the switching power system 10, an error amplifier 14 generates an error signal Vcomp, as shown by the waveform 32, according to the difference between the output voltage Vcore and a reference voltage Vref provided by a reference voltage generator 12, a ramp generator 16 provides ramp signals Vramp1 and Vramp2, as shown by the waveforms 28 and 30 respectively, a pulse width modulation (PWM) comparator 18 generates a PWM signal Vpwm1, as shown by the waveform 34, according to the error signal Vcomp and the ramp signal Vramp1, and a PWM comparator 20 generates a signal Vpwm2, as shown by the waveform 36, according to the error signal Vcomp and the ramp signal Vramp2. When the ramp signal Vramp1 is smaller than the error signal Vcomp, the PWM signal Vpwm1 is high and thus, a channel 22 is turned on to charge a capacitor C1 and thereby pump up the output voltage Vcore, as shown by the waveform 26. Likewise, when the ramp signal Vramp2 is smaller than the error signal Vcomp, the PWM signal Vpwm2 is high and in consequence, a channel 24 is turned on to charge a capacitor C2 and thereby pump up the output voltage Vcore.
However, the load current of CPU today is extremely dynamic, slewing very fast from low to high and vice versa. A CPU load current can occur within 1 μs, which is much less than the switching period of the switching power system 10. If a load transient takes place during a pulse of the PWM signal Vpwm1 or Vpwm2, for example in the interval t2 shown in FIG. 2, the falling speed of the output voltage Vcore is reduced due to the fact that the channel 22 or 24 is turned on. If a load transient occurs between pulses of the PWM signals Vpwm1 and Vpwm2, for example in the interval t1 shown in FIG. 2, the PWM controller can do nothing about it because neither Vpwm1 nor Vpwm2 is allowed to go high. So the output voltage Vcore is bound to drop out of control. Furthermore, if a load transient happens in the interval t2 while the PWM signal Vpwm1 or Vpwm2 is high, the drop of the output voltage Vcore will not be as severe as it is in the interval t1. But if the load transient is relatively large, the output voltage Vcore still significantly drops. Therefore, a quick response mechanism is needed to trigger a quick response event to turn on the channels 22 and 24 simultaneously.
To achieve optimal Vcore (no drop at all, or drop as predicted), an optimal quick response must exists. The trigger timing and the width of a quick response are both the most critical parameters of an optimal quick response. If a quick response starts too slow, the output voltage Vcore may drop out of the specification, which is known as an undershoot. On the contrary, a too fast quick response triggered before load transient occurs will induce a voltage spike. Besides, if the quick response duration is too short, the output voltage Vcore may still drop below the specification because there is no enough charge in the output capacitor pool. On the contrary, if the quick response duration is too long, the output voltage Vcore will rise high and causes a ringback. All of the above situations are desired to be prevented from.
FIG. 3 is a perspective diagram showing a conventional adaptive phase alignment (APA) for achieving quick response, in which an APA circuit 40 includes an error amplifier 42 to generate an error signal Vcomp according to the difference between the output voltage Vcore of a switching power system and a reference voltage Vref, a low-pass filter 44 to filter the error signal Vcomp to generate a signal V2, a current source 48 to provide a current Iapa flowing through a resistor Rapa to generate a voltage Vapa to offset the error signal Vcomp to generate a signal V1, and a comparator 46 to generate a quick response signal QR according to the signals V1 and V2. Thus, the APA circuit 40 works by monitoring the voltage at the APA pin and comparing it to the filtered Vcomp. The voltage at the APA pin is a copy of the error signal Vcomp with the negative offset Vapa. If the APA pin exceeds the filtered Vcomp, an APA event occurs and all channels are turned on. When a load transient occurs, the error signal Vcomp decreases, and the signal V2 falls accordingly. However, a capacitor Capa prevents the signal V1 from decreasing immediately. When the signal V2 becomes lower than the signal V1, the quick response signal QR is triggered to start a quick response. The trigger timing of the quick response signal QR is determined by the signalV1=Vcomp−Iapa×Rapa.  [EQ-1]A user can use a larger resistor Rapa to delay the trigger timing of the APA and vice versa. However, the APA duration depends on the low-pass filter 44. The lower corner it has, the wider APA is. It's difficult for a user to control the APA width because the low-pass filter 44 is built in the controller chip.
It is well known that the error signal Vcomp provided by the error amplifier 42 will be compensated by a compensator. In other words, there will be a compensation delay between the instant when the output voltage Vcore begins to fall and the instant when the error signal Vcomp begins to fall. The goal of a good quick response is to achieve a good output voltage Vcore. The APA technique triggers the quick response by Vcomp information instead of Vcore. When a load transient event occurs at Vcore, it has to go through the compensator and then boosts Vcomp. So the APA triggers after the compensator delay. This is no good if the load transient slew rate is very high. Vcore may drop out of the specification before the APA is triggered.
Therefore, it is desired a mechanism to accurately trigger a quick response and adjust the quick response width.