1. Field of the Invention
The present invention relates to a technology adapted for generating a test pattern for detecting faults in an electronic circuit such as an LSI (Large Scale Integration).
2. Description of the Related Art
Detection of manufacturing failure of electronic circuits, such as LSI (Large Scale Integration) and the like, due to its manufacturing is in general performed by applying an appropriate signal value, by means of tester, to an input pin of the LSI and a signal value appearing at an output pin is compared with an expected result. Here, the signal value applied to the input pin and the expected value that should appear at the output pin are collectively called a test pattern.
The defects occurring in the LSI during its manufacturing is called faults, and in order to verify all of the faults occurring in the LSI, many test patterns are required. And in order to decrease the number of these test patterns, a compaction method called as a dynamic compaction method is generally utilized (refer to patent literature 1 mentioning later).
As explained below, the dynamic compaction is said to be a compaction process for test data. For example, when a test for a primary fault on a target is successful with a test pattern generated by an ATPG (Automatic Test Pattern Generator), one secondary fault is selected in a set of remaining undetected faults under the net state conditions set in order to detect the primary fault. And a new value is set to a test point that is still an indeterminate value to execute the generation of a test pattern for the above secondary fault indeterminate. And a process similar to the above is repeated until another secondary fault is not selected from the set of undetected faults. Here, when another secondary fault is selected, the same fault is not again detected. The dynamic compaction is to decrease test data by increasing the number of faults detected in units of test as mentioned above.
In case of a current processor having high grade its specifications, in view of requirements for processor speed and chip size, in some case, an RF (register file) being composed of a RAM (Random Access Memory) being a non scan-able memory device and an NSL (no scan latch) array is built in the processor.
And before and behind this type memory device, there are often disposed a combinational circuit having a high repeating symmetric property (for example, a write/read address selector), a combinational circuit including XORs (exclusive Ors) (for example, an EEC (error correct circuit) such as a parity check circuit), and a match compare circuit in a TAG RAM.
In the conventional dynamic compaction method or at an ATG (automatic test generator) for individual faults, in connection with the decision for solving an unsolved gate (D frontier) of fault propagation or solving an unsolved gate (J frontier) of output, in many cases, there is introduced a heuristic approach such as a rotating back-trace for avoiding a decision bias by a static reference that is decided topologically, or a controllable/observable reference (for example, LEVEL, SCOAP, and FANOUT BASE).
Here, the J frontier (Justify frontier) is an unsolved gate in which a selection is required for setting an input value because a request value exists in the output and two or more Xs (indeterminate values) exist in the input. The D frontier (different frontier) is an unsolved gate in which D (different) propagation is unknown because the difference D between a normal value and a fault value exists in at least one of the inputs and one or more Xs (indeterminate values) exist at the other inputs. And the decision signifies that the ATG selects a state given to the input for solving the above-mentioned J frontier/D frontier.
[Patent Literature 1] Japanese Patent Laid-Open Publication HEI1-52030
FIG. 15 is a diagram showing a part of a circuit having a structure of a CAM (Content Address-able Memory)/TLB (Translation Look-aside Buffer) circuit. This circuit shown in FIG. 15 is provided with a key section 101 having scan_1, scan_2, and scan_3, a memory section 102 being an RF (as a broad sense, RAM) composed of an NSL array, and a match compare section 103 being a combinational circuit including XORs. The memory section 102 is provided with an entry #1 and an entry #2.
At the CAM/TLB circuit shown in FIG. 15, the memory section 102 and the match compare section 103 are studied separately. At the conventional dynamic compaction method, there is a possibility that sufficient pattern compaction cannot be expected, by control involved in the match compare section 103 being a combinational circuit including the XORs, or by control with respect to “write” of the memory section 102, which has high “write” exclusiveness in the entry direction.
Next, inefficiency to the pattern compaction is explained for each of the following two cases. (1) is a case of the control involved in the combinational circuit including the XORs, and (2) is a case of the control involved in the RAM (RF) having the high write exclusiveness in the entry direction.
For the case (1) being with the control involved in the combinational circuit including the XORs, for example, at the circuit shown in FIG. 15, it is assumed that “stack at 0 fault” being composed of faults f11, f12 and f13 is the fault to be detected.
As confirmed by observing, an ideal test for the faults f11 to f13 is realized by executing fault excitation and propagation on one time plane by allocating the following states.
nsl_11=nsl_12=nsl_13=1
scan_1=scan_2=scan_3=0
Here, as a preparation pattern for controlling the NSLs, one or more time planes are actually required. However, in order to make it simple, at the time planes of the preparation pattern, when it is assumed that the control for the NSLs relating to at least one entry is arbitrary, the test for the faults f11 to f13 becomes a minimum test (ideal test) by two time planes (refer to FIG. 16).
FIG. 16 is a diagram showing an example of an ideal test at the detection of the faults f11 to f13 at the entry #1 shown in FIG. 15. And FIG. 17 is a diagram showing an example of its worst test.
Here, a process, in which the dynamic compaction is executed at the time when the fault f11 is a primary fault from the initial state of the circuit being that all of the NSLs are the indeterminate value X, is studied. In the test generation for the fault f11, about the fault excitation and the fault propagation, the nsl_11=1, nsl_12=1, and nsl_13=1 can be decided uniquely as an indispensable state by a unique path check.
That is, at the decision of the ATG, the state of the scan_1 for solving the eor_11 being the D frontier, and the states of the scan_2 and the scan_3 and the states of the nsl_12 and the nsl_13 for solving the eor_12 and the eor_13 being the J frontiers are decided respectively.
However, the XOR being the D frontier is solved when the states of the input pins except the input pin in which the fault is propagated are not the indeterminate value X. And the XOR being the J frontier is immediately decided by the implication process of the state of the remaining 1 pin, when the input state of the pin (input pin_1) is decided.
In FIG. 15, the eor_11 being the D frontier is solved by deciding the state of the scan_1 as a value except the indeterminate value X. And at the two input XORs at the eor_12 and the eor_13 being the J frontiers, the solution by deciding the state of the scan_2 and the solution by deciding the state of the nsl_12 are equivalent. Such is also the same with the decision of the scan_3 and the nsl_13 regarding the solution of the eor_13. Therefore, the solution of the D frontier (eor_11) and the solution of the J frontiers (eor_12 and eor_13) result in the state decision of the scan_11 to scan_13.
At this time, the topological controllability of the scan_1 to scan_3 as viewed from the eor_11 to the ero_13 is the same because of the repeat of the circuit. Furthermore, the controllability for setting 0 and 1 is symmetric and the same because the scan_1 to the scan_3 are their own control points. Therefore, at the test generation for the fault f11, the controllable/observable reference using at the ATG of the conventional dynamic compaction method dose not show any selection reference involved in the control for the XOR gates in the match compare section.
Consequently, in connection with the fault f11, the selection reference regarding the nsl_12 and the nsl_13 except the nsl_11 for the fault excitation is not shown, therefore, there is a possibility that the test was successful by chance by allocating the nsl_12=nsl_13=0. Here, the possibility allocating the nsl_12=nsl_13=0 is the same at the rotating back trace being random number operation.
Further, in FIG. 15, a case of a situation, in which the faults f12 and f13 become the secondary fault after generating the test pattern of the fault f11 to which the state of the nsl_12=nsl_13=0 was allocated, is studied. In this case, on the time plane, in which the fault f11 was excited, the net state in which the faults f12 and f13 are already assumed, becomes equal to the fault value (0), therefore, the excitation becomes impossible.
Therefore, when the fault f12 was made to be a target as the secondary fault, the dynamic compaction generates a test pattern by executing the fault excitation of the fault f12 in expanding a different time plane from the time plane that executed the fault excitation of the fault f11.
And as is the case with the generation of the test pattern for the fault f11, at the conventional dynamic compaction method, there is a possibility that the nsl_13=0 is allocated at the test for the fault f12. Therefore, three different time planes are used at the fault excitation for the faults f11 to f13. That is, at the above-mentioned ideal test, it is possible that the fault excitation/propagation of the faults f11 to f13 is realized by one time plane. However, at the conventional dynamic compaction method, as shown in FIG. 17, the number of the time planes is increased to three in the worst case. And this increase of the number of the time planes signifies the increase of the number of test patterns, and the compaction efficiency is decreased.
Therefore, at the conventional dynamic compaction method, by the repeat and the symmetric property of the circuit at the controllable/observable reference using in the ATG, there is a fear that the reference involved in the state selection at the circuit including the XORs (refer to the match compare section 103 in FIG. 15) cannot be given.
Next, the case (2) of the control involved in the RAM (RF) having the high write exclusiveness in the entry direction is explained. FIG. 18 is a diagram showing an example of an ideal test at the detection of the faults f11 to f13 at the entry #1 and the faults f21 to f23 at the entry #2 shown in FIG. 15. And FIG. 19 is a diagram showing an example of its worst test.
The control related to the above-mentioned combinational circuit including the XORs is adapted for dealing with possibilities of increase in the number of possible patterns for the faults (refer to the faults f11 to f13 in FIG. 15) in the same entry. As shown in the worst case (the worst test; refer to FIG. 17), in case that a different time plane is used for each fault excitation, that is, three time planes are used for the fault excitation of the faults f11 to f13 in FIG. 15, there is a possibility that the increase of the patterns affects the other entry due to the exclusiveness with respect to “write” in the entry direction.
The reason is that not only at the RAM (RF) in the CAM/TLB circuit but also at a RAM (RF) in generally use, the number of entries which can write in one cycle is generally smaller than the number of holding entries. That is, as an extreme case, an RF of a CAM/TLB circuit, in which the number of entries that can write in one clock is one, is studied. In this case, at the time planes, which are executing the writing to the NSLs of the entry #1 (time (t) in FIG. 16, and time (t) to (t+2) in FIG. 17), it is impossible to write in the NSLs except the NSLs of the entry #1.
That is, in case that the exclusiveness with respect to “write” between the entries is high, at the time when the “write” is executed to the NSLs at one entry, it is impossible that the “write” is executed to the NSLs at the other entry. Therefore, executing “write” to the NSLs by using many time planes for the faults at a focused entry prevents the “write” to the NSLs of a non-focused entry. Consequently, as a whole, the number of test patterns is increased and the efficiency at the pattern compaction is decreased (refer to FIGS. 18 and 19).
Therefore, for example, when an NSL becomes a J frontier at time (t), in order to satisfy this request value, at the past time (t−n, n>1), it is necessary that the state of NSL is set to the request value by executing the following operation.
Write operation: Clock=ON and Din=request value.
Set operation: Set=ON (Here, Set value is request value).
Reset operation: Reset=ON (Here, Reset value is request value).
However, as mentioned above, in case that the write exclusiveness in the entry direction is high, at the time when the “write” is being executed to the NSLs of one entry, there is a fear that the “write” to the NSLs of the other entry becomes impossible. That is, using many time planes for one entry without any consideration causes the increase in the test patterns as a whole.