1. Field of the Invention
The present invention relates to a semiconductor memory device and in particular to a semiconductor memory device having a normal and redundant memory cells.
2. Description of the Related Art
As the storage capacity of semiconductor devices is enlarged, various measures have been proposed for remedying a memory having a deficient memory cell in order to improve the production yield of the devices. One proposal is to provide redundant memory cells in the devices beforehand to substitute for a possible deficient memory cell.
Ways of arranging redundant memory cells can be classified into two categories: one is to align one or more arrays of redundant memory cells parallel to the normal memory row (the normal memory refers to a memory in the usual sense), while the other is to align the arrays parallel to the normal memory column. In the former, the rows of the redundant memory cells are substituted for the same numbers of normal memory rows together with word lines in case the normal memory rows include a deficient memory cell, while in the latter, the redundant memory array columns are substituted for the same number of normal memory columns together with the column-selecting transistors and the sense amplifiers coupled to the columns.
Hereafter, the memory area to be substituted or by the redundant memory when it includes any deficiency will be referred to as the substitution area. Although not all the memory cells included in the substitution area are deficient, good memory cells contained in the substitution area are also substituted for by the redundant memory so far as the substitution area has at least one deficient memory cell. The good memory cells described above will be referred to as unused memory cells. Thus, in order to efficiently use the normal memory, it is necessary to minimize the number of unused memory cells. This can be attained by making the substitution area as small as possible, i.e., by dividing the entire normal memory into substitution areas of the smallest possible area. However, a large number /f substitution areas requires, if, for example, they are columnarly divided areas, a large number of sense amplifiers, which occupies a large area of the sense amplifiers on the semiconductor chip.
In order to solve this problem, a semiconductor memory device is proposed in U.S. Pat. No. 4,908,798. In this device, arrays of redundant memory cells are directed parallel to the normal memory column. The normal memory is divided into a plurality of columnar memory cell blocks, and each of the blocks is further divided into a plurality of subblocks, each of which is intended for the substitution area defined above. The redundant memory, however, is made of one block which has the same dimension as that of the subblock. The location of a column in a normal memory block is designated by a duplex address made up of a subblock address and an intrasubblock address (the internal address of the subblock), while the location of a column in the redundancy memory is designated by an intrablock address. The intrasubblock address of the normal memory column and the intrablock address of the redundant memory column are both decoded by a single decoder, the first Y-decoder. The subblock address is decoded by an additional decoder, the second Y-decoder. A sense amplifier is provided for every block. Accordingly, a datum read from the redundant memory is supplied directly to the sense amplifier belonging to the redundant memory block.
Addressing a column in a normal memory block is effected by the first and second decoder in accordance with an externally supplied duplex address. A datum read from the addressed column is fed to the relevant sense amplifier (the sense amplifier belonging to the block which includes the addressed column). If the relevant subblock (the subblock which includes the addressed column) does not include any deficient memory cell, then the second Y-decoder controls the switching on of the signal path between the relevant sense amplifier and the I/O terminal. If the addressed subblock includes any deficient memory cell, then the second Y-decoder controls the switching off of the signal path between the I/O terminal and the relevant sense amplifier and the switching on of the signal path between the I/O terminal and the sense amplifier belonging to the redundant memory block, whereby the datum is read from the redundant memory in lieu of the relevant subblock. In this way, since the substitution is carried out through the subblock unit, both fewer sense amplifiers and fewer unused memory cells result.
Many recent semiconductor memory devices are internally provided with circuits necessary for a test mode operation. Some of these devices are of the type in which specified internal data are provided to external circuits. Typical of the internal data is a product-identification code designating the maker and the model of, for example, an EPROM (an erasable programmable read-only memory). This code is accessed, by applying a high voltage to a given pin (for example, pin #A9), by first applying the lowest address (#AO) with the low level and then the high level. Corresponding to the low and high levels of the lowest address (#AO), the maker code and the model code respectively, are accessed. With these codes the programmer can prescribe the conditions to write to the EPROM.
This function of disclosing the maker code and the model code is a function conferred on almost all devices provided with EPROMs. In order to allow this function to be provided to such a device, typically, arrays of a mask ROM which stores the codes are formed next to the normal memory array, the drains of the mask ROM arrays and the normal memory being interconnected so that the mask ROM and the normal memory have common bit lines. The word lines of both memories are controlled so that, when pin #A9 is at the high voltage, all word lines of the mask ROM are activated and all word lines of the normal memory are inactivated, whereby the maker code and the model code are delivered through the bit lines to the exterior.
In the semiconductor memory device provided with redundant memory columns described above, however, when the normal memory columns are substituted with the redundant memory columns, the bit lines coupled to the substituted columns of the normal memory are also substituted, as described above. As a result, the part of the mask ROM coupled to the bit lines in common with the substituted columns of the normal memory becomes unable to be accessed.
This problem arises from the positional relation between the mask ROM and the normal.redundant selector circuit in the flow of data in the device, where the normal-redundant selector circuit is a circuit which switches over the connection between the relevant sense amplifier and the output data line to the connection between the sense amplifier belonging to the redundant memory and the output data line. If the mask ROM is arranged further upstream than the normal.redundant selector circuit, which is the case in the prior art device described above, the data path from the mask ROM to the output data line is switched over by the normal.redundant selector circuit, preventing data read from the mask ROM from being output.
In order to avoid this situation, it is necessary to arrange the mask ROM further downstream than the normal.redundant selector circuit. FIG. 1 shows a block diagram of a semiconductor memory device of the prior art provided with a redundant memory, in which the logic circuit for generating test codes (designated by reference number 12 as an intermediate buffer in the figure) is arranged further downstreams than normal-redundant selector circuit 9. This circuitry is adopted in the semiconductor memory devices with large storage capacities manufactured by NEC Corp. The arrays of normal memory 1 and redundant memory 2 are coupled to the common word lines, and each word line is designated by a row address signal decoded by common row decoder 3.
Columns in normal memory 1 and redundant memory 2 are selected by column selector circuits 5 and 6, respectively, operated in response to a column address signal decoded by column decoder 4. Data read from the accessed columns are amplified by sense amplifier circuits 7 and 8, and are delivered to data lines Dn and Dr. (While only one data line is shown as data line Dn in FIG. 1, data lines of the same number as that of the sense amplifiers arranged in sense amplifier circuit 7, i.e., the number of the blocks in the normal memory, are actually provided for data line Dn. The data serially read from each of the blocks are amplified by the corresponding sense amplifier and delivered to the data line connected to the sense amplifier.) Redundant address memory 10 stores the addresses of deficient memory cells by means well known in the art. Transfer control circuit 11 compares a supplied address with the address stored in redundant address memory 10 and provides transfer control signal S. Transfer control signal S controls normal.redundant selector circuit (hereinafter, referred to as an NR selector circuit) 9 to transfer the outputs of all sense amplifiers provided in sense amplifier circuit 7 to common data line Data in the case that normal memory 1 does not include any deficient memory cell, and to transfer the outputs of sense amplifier circuit 7 except for the output of the relevant sense amplifier in sense amplifier circuit 7 together with the output of sense amplifier circuit 8 in the case that normal memory 1 includes at least one deficient memory cell. The operation modes of the semiconductor memory device in the former and latter cases will be referred to below as the normal access mode and the substitution mode, respectively. Thus, in the normal access mode, the data read from the normal memory are delivered to data line Data as is, while, in the substitution mode, the data read from the normal memory with the substitution area substituted with the redundant memory are delivered to data line Data.
Code generating intermediate buffer 12 is directed to generating the product identification code and also to playing a role as a buffer register to transmit data from data line Data to data line D. Code generating intermediate buffer 12 includes a logic circuit capable of transmitting data in the normal mode operation and of generating the maker code and the model code in the test mode operation in response to code selection signal T. In order to have;the logic of the data on data line D accord with that of the data on data line Data, code generating intermediate buffer 12 has logic circuits connected in two stages. Code generating intermediate buffer 12 will be referred to as intermediate buffer 12 below.
Code selection control circuit 13 generates code selection signal T in response to voltage signals externally supplied through pins #A9 and #A0.
Code selection signal T controls intermediate buffer 12 so that,
if pin #A9 is at 0 V, then intermediate buffer 12 operates in the normal mode, PA1 if pin #A9 is applied with a high voltage (typically 12 V) and pin #A0 is supplied with the low level, then intermediate buffer 12 delivers the maker code, and PA1 if pin #A9 is applied with the high voltage and pin #A0 is supplied with the high level, then intermediate buffer 12 delivers the model code.
The output signal of intermediate buffer 12 is transmitted through output buffer 14 and output terminal 16 to an external circuit.
A problem encountered in the semiconductor memory device descibed above is that, since at least two stage logic circuits are necessary for the intermediate buffer in order to have the logic of data on the output data line accord with that on the input data line of the intermediate buffer, the transmission time of the data is delayed by the time required to pass the two stage logic circuits, which results in a decrease in the read velocity for the semiconductor memory device.