The present invention generally relates to integrated circuits and, in particular, to a flash memory structure and a method of flash memory fabrication wherein a new core cell structure eliminates a stacked gate structure for the select gate transistors while eliminating a core dual oxide manufacturing step. The elimination of the core dual oxide step substantially simplifies the process, eliminates associated tunnel oxide reliability concerns and shrinks the size of the select gate transistor by eliminating the need for a poly1 contact.
Semiconductor devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art FIG. 1a, a memory device such as a flash memory 10 comprises one or more high density core regions 11 and a low density peripheral portion 12 on a single substrate 13. The high density core regions 11 typically consist of at least one Mxc3x97N array of individually addressable, substantially identical floating-gate type memory cells and the low density peripheral portion 12 typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing).
The memory cells within the core portion 11 are coupled together in a NAND-type circuit configuration, such as, for example, the configuration illustrated in prior art FIG. 1b. Each memory cell 14 has a drain 14a, a source 14b and a stacked gate 14c. A plurality of memory cells 14 connected together in series with a drain select transistor at one end and a source select transistor at the other end to form a NAND string as illustrated in prior art FIG. 1b. Each stacked gate 14c is coupled to a word line (WL0, WL1, . . . , WLn) while each drain of the drain select transistors are coupled to a bit line (BL0, BL1, . . . , BLn). Lastly, each source of the source select transistors are coupled to a common source line Vss. Using peripheral decoder and control circuitry, each memory cell 14 can be addressed for programming, reading or erasing functions.
Prior art FIG. 1c represents a fragmentary cross section diagram of a typical memory cell 14 in the core region 11 of prior art FIGS. 1a and 1b. Such a cell 14 typically includes the source 14b, the drain 14a and a channel 15 in a substrate or P-well 16; and the stacked gate structure 14c overlying the channel 15. The stacked gate 14c further includes a thin gate dielectric layer 17a (commonly referred to as the tunnel oxide) formed on the surface of the P-well 16. The stacked gate 14c also includes a polysilicon floating gate 17b which overlies the tunnel oxide 17a and an interpoly dielectric layer 17c overlies the floating gate 17b. The interpoly dielectric layer 17c is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate 17d overlies the interpoly dielectric layer 17c. The control gates 17d of the respective cells 14 that are formed in a lateral row share a common word line (WL) associated with the row of cells (see, e.g., prior art FIG. 1b). In addition, as highlighted above, the drain regions 14a of the respective cells in a vertical column are connected together by a conductive bit line (BL). The channel 15 of the cell 14 conducts current between the source 14b and the drain 14a in accordance with an electric field developed in the channel 15 by the stacked gate structure 14c. 
According to conventional operation, the flash memory cell 14 operates in the following manner. The cell 14 is programmed by applying a relatively high voltage VG (e.g., approximately 18 volts) to the control gate 17d and connecting the drain, source and P-well to ground. A resulting high electric field across the tunnel oxide 17a leads to a phenomena called xe2x80x9cFowler-Nordheimxe2x80x9d tunneling. During this process, electrons in the core cell channel region tunnel through the gate oxide into the floating gate 17b and become trapped in the floating gate 17b since the floating gate 17b is surrounded by insulators (the interpoly dielectric 17c and the tunnel oxide 17a). As a result of the trapped electrons, the threshold voltage of the cell 14 increases by about 3 to 5 volts. This change in the threshold voltage (and thereby the channel conductance) of the cell 14 created by the trapped electrons is what causes the cell to be programmed.
To read the memory cell 14, a predetermined voltage VG that is greater than the threshold voltage of an erased cell, but less than the threshold voltage of a programmed cell, is applied to the control gate 17d with a voltage applied between the source 14b and the drain 14a. If the cell 14 conducts, then the cell 14 has not been programmed (the cell 14 is therefore at a first logic state, e.g., a zero xe2x80x9c0xe2x80x9d). Likewise, if the cell 14 does not conduct, then the cell 14 has been programmed (the cell 14 is therefore at a second logic state, e.g., a one xe2x80x9c1xe2x80x9d). Consequently, one can read each cell 14 to determine whether it has been programmed (and therefore identify its logic state).
In order to erase the flash memory cell 14, a relatively high voltage VS (e.g., approximately 20 volts) is applied to the P-well 16 and the control gate 17d is held at a ground potential (VG=0), while the drain 14a and the source 14b are allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide 17a between the floating gate 17b and the P-well 16. The electrons that are trapped in the floating gate 17b flow toward and cluster at the portion of the floating gate 17b overlying the source region 14b and are extracted from the floating gate 17b and into the source region 14b by way of Fowler-Nordheim tunneling through the tunnel oxide 17a. Consequently, as the electrons are removed from the floating gate 17b, the cell 14 is erased.
There is a strong need in the art for a flash memory device structure and process for manufacture that improves the performance and reliability of the device while simplifying its method of manufacture.
The present invention relates to flash memory device structure and a method for its manufacture. In a core portion of a NAND-type flash memory cell, a select gate transistor has a structure which includes a stacked ONO dielectric layer for a gate oxide. The select gate transistor structure allows the device to be easily fabricated by eliminating the dual core oxide formation process. Elimination of the dual core oxide process steps reduces the number of process steps and prevents a potential source of contamination prior to the formation of the core tunnel oxide, thereby improving the reliability of the device.
According to another aspect of the present invention, the formation of a select gate transistor structure utilizing the stacked ONO dielectric layer for a gate oxide eliminates the stacked gate structure for the select gate transistors and the need for a poly1 contact to short out the poly1 and poly2 layers, thereby advantageously reducing the die area. In addition, eliminating the stacked gate structure for the select gate transistor allows for a channel stop implant to be performed in the select gate transistor region, thereby improving the bit line isolation and decreasing the potential for bit line to bit line punch through.
According to yet another aspect of the present invention, the select gate transistor uses a stacked ONO dielectric layer which improves the resistance of the select gate transistor to high field stress induced dielectric damage. In addition, the ONO layer is substantially thinner than the other select gate transistor oxide, thereby improving the drive current and performance of the select gate transistor.