Time interleaved (or multi-channel) architecture is commonly used in semiconductor or other devices to provide parallelism in circuit design. As circuit speed, resolution and complexity are ever increasing, the demands on circuit design are immense. Time interleaved architecture assists in meeting these demands by providing a mechanism for relaxing the criteria without foregoing circuit performance. As shown in FIG. 8(a), for example, the time-interleaved architecture is typically composed of a plurality of parallel channel devices 82a, 82b, . . . 82m generating a plurality of channel output signals which are ultimately combined as a single output using a device such as multiplexer 84.
Many advantages arise from the use of such a time-interleaved architecture. For example, in a circuit design requiring a final speed of Fs, utilizing a time-interleaved architcture, a series of m channels (e.g., channels 1, 2, . . . m, as in FIG. 8 (a)) can be used. Where each channel is designed to perform the required functions in parallel, the individual channels need only be designed to perform at the less demanding speed of Fs/m. The circuit design on each individual channel therefore is relaxed and more manageable.
To successfully implement any time-interleaved architecture, a precise delay multi-phase clock generator is required. As shown in FIG. 8(a), a plurality of sample and hold devices 80a, 80b, . . . 80m must sample the input signals at precise intervals to provide the correct input signal samples to the plurality of channel devices 82a, 82b, . . . 82m. The multi-phase clock signals xcfx861, xcfx862, . . . xcfx86m must therefore be precise in the time intervals between clock phases. Ideally, the delay between any adjacent phases should be exactly the same, i.e., xcfx861, xcfx862, . . . uniformly distributed within one clock period m/Fs, xcex94td1=xcex94td2= . . . =xcex94tdm=1/Fs, as shown in FIG. 8(b).
In real-world applications, however, random variations of the sampling signals is unavoidable. The instability of every individual clock phase itself makes precise sampling difficult. The instability is often caused by noise sources (commonly known as xe2x80x9cjitterxe2x80x9d) on the device itself (e.g., integrated circuit or xe2x80x9cchipxe2x80x9d). Jitter raises the noise floor, thus, reducing signal-to-noise ratio (SNR). Variations in the sampling signals may also be attributed to mismatches in the device, the channel, or both. Such mismatches may introduce tones into the operation, thereby reducing spurious-free dynamic range (SFDR). Such random variations in the sampling signals is often critical to the effectiveness of the time-interleaved architecture.
In accordance with a preferred embodiment, a time-interleaved (or multi-phase) architecture is provided having individual control of a plurality of output signals or phases. The time-interleaved architecture may be implemented using a first set of delay cells such as those in a ring oscillator or a delay line device receiving overall control of its output signals by a global control signal. The global control signal may be issued by a phase-locked loop, delay-locked loop, or other like structure. A second set of delay cells is provided to further delay the output signals produced by the first set of delay cells. The second set of delay cells are controlled by individual control signals uniquely calibrated in accordance with a preferred embodiment of the invention to provide uniform (or substantially) uniform time spacing between output signals.