Data separators are used in various applications, and particularly in floppy disk controller designs. A floppy disk controller is a module that controls the data communication between a central processing unit (CPU) and a floppy disk drive (or a tape drive) in a personal computer (PC) system.
The communications between a floppy disk drive and a floppy disk controller flow through two wires referred to as "serial data out" (SDO) and "serial data in" (SDI). During the write operation, the data flow through the SDO line. As is known, the data consist of a series of pulses that are converted by the drive into magnetic flux reversals on the floppy disk. The pulses are later read by the drive and converted back to encoded pulses which can be decoded by the floppy disk controller into the original data.
The data read from the disk are subject to three irregularities, referred to as bit shift, motor speed variation (MSV), and instantaneous speed variation (ISV). Bit shift arises from the magnetic interaction of adjacent bits on the disk. When the flux transitions are recorded close to each other, the superposition of their magnetic fields causes them to move apart. Thus, when the bits are read, the disk drive's peak detector likewise moves the peaks of these flux transitions apart from each other. This is the major cause of bit shift, otherwise known as "jitter". While write precompensation circuitry can partially overcome this problem, a certain amount of bit shift remains.
MSV is caused by an error in the speed of the spindle motor in the disk drive, and it causes the data rate to vary typically 1-2% for each drive. ISV is an additional speed error that is caused by disk-jacket friction and mechanical resonances. ISV causes the data rate to vary an additional 1-2%.
A data separator must be able to synthesize the average frequency of the incoming serial data, which in turn minimizes the problems caused by bit shift. The incoming data on the SDI line represent both clock and data information. For successful, error-free communication, the data separator must regenerate the desired clock signal and synchronize it to the rate of the received pulse stream.
The difficulty of doing this is particularly great when the data are recorded in the format known as modified frequency modulation (MFM), which is currently the most widely used recording format for floppy disks. MFM defines a bit cell for each bit of data, with each cell containing a position for a clock pulse (clock window) and a position for a data pulse (data window). A data pulse is present if the data bit is one. A clock pulse is present only if the data bit is zero and the data bit in the previous bit cell was a zero. Thus, the pulses can be separated by one bit cell (data pulse followed by data pulse, or clock pulse followed by clock pulse), 1.5 bit cells (data pulse followed by clock pulse, or vice versa), or 2 bit cells (empty cell between two data pulses). The data separator must take this information and generate three outputs: a non-return-to-zero clock (NRZCK), which indicates the presence of a clock pulse in the bit cell, a non-return-to-zero data signal (NRZDA), which indicates the presence of a data pulse in the bit cell, and a bit-cell clock signal. The floppy disk controller can use this information to regenerate the data in the form in which it was originally received from the CPU.
Most conventional data separators use an analog phase locked loop (PLL) to generate the sampling clock. Analog PLLs have the potential of infinite resolution, but they require precise components such as resistors and capacitors, either external or internal. In the latter case, the components are susceptible to variations in the manufacturing process. Moreover, analog circuits are susceptible to signal noise, which limits their resolution in practice.