At present, DSL technologies have been widely applied, and requirements on the DSL subscriber board also rise continuously. Port density of a subscriber board is increasing from 8, 16, 32 to 64, or even higher, and DSL line bandwidth is increasing from 512 k, 2 M, 8 M, 24 M to as high as 100 M. To accord with the above developing trend, processing bandwidth of the DSL subscriber board must be increased quickly.
A structure of most DSL subscriber boards is shown in FIG. 1. There is only one interface (interface 1) between a DSL physical interface chip and a protocol processing chip. Generally, the interface 1 can be a Universal Test and Operations PHY Interface for ATM (UTOPIA) Level 1 (a first class of interface), or a UTOPIA Level 2 (a second class of interface), or a Packet over SONET/SDH (POS) Level 1 interface or a POS Level 2 interface. And there is only one uplink interface (interface 2) between the protocol processing chip and an uplink physical interface chip. The form of the interface 2 is not limited. Generally, it can be a Gigabyte Ethernet (GE) interface, a Fast Ethernet (FE) interface or a Low Voltage Difference Synchronization (LVDS) interface. Alternatively, the interface 2 can also be implemented by two interfaces which operate as work/backup interfaces, and only one of the two interfaces works at the same time.
Therefore, a method for increasing the bandwidth of a DSL subscriber board is required.