1. Field of the Invention
This invention relates to integrated circuit structures. More particularly, this invention relates to a process for treating dielectric films to prevent cracking after deposition on a semiconductor wafer.
2. Description of the Related Art
The steps of manufacturing an integrated circuit structure include the deposition of a plurality of layers onto the surface of a silicon wafer. Typically, these layers comprise either a conductive metallic material, such as tungsten or aluminum metals, or an insulating dielectric material, such as silicon oxide. The physical properties of these films play an important role in determining the quality of the film layers, and the interaction of the film layers with the silicon substrate. One important physical property which greatly effects the quality of a film layer and the interactions between the silicon substrate and the deposited film is residual stress, which can be either tensile or compressive with respect to the silicon wafer.
When a film exhibits tensile stress with respect to the silicon wafer, it tends toward forming a concave upper surface, which is caused by the film exerting a force directed away from the surface of the wafer. If the magnitude of the tensile stress is sufficient, the film may (1) crack and/or (2) pull away from the surface of the silicon wafer. These damaging effects may occur during the course of the integrated circuit manufacturing process, or at any time throughout the useful lifetime of the integrated circuit device.
In contrast, films exhibiting compressive stress, exert a force directed toward the surface of the wafer (and tend toward having a convex upper surface). Although compressive stress may not cause as much damage as tensile stress, if the compressive stress is of a great enough magnitude in a given film layer, the highly stressed film layer may exert damaging stress on an adjacent film layer. Therefore, ideally, a film layer which does not exhibit any residual stress is optimal for forming a high quality, stable film layer.
In practice, every film layer deposited on a silicon wafer exhibits some degree of residual stress. In an integrated circuit device having, for example, tungsten conductive metal layers and silicon oxide insulating dielectric layers, the metal layers exhibit tensile stress, while the silicon oxide layers exhibit compressive stress. The forces exerted in tensile stress and compressive stress are opposite in directionality. Therefore, the tensile and compressive stresses respectively exhibited by the tungsten metal and silicon oxide dielectric layers combine in such a way that the overall stress of the composite of metal and dielectric film layers is reduced. The lowering of accumulated stress by placement of layers with opposing stresses is effective when the magnitudes of the stresses are small, i.e., less than 10.sup.10 dynes/centimeter.sup.2 (dynes/cm.sup.2) in magnitude. However, use of a large amount of compressive stress to compensate for a large amount of tensile stress may also lead to a cracking of the films making up the various metal and dielectric layers. Therefore, an effective construction of an integrated circuit device comprises metal layers having low magnitudes of tensile stress, and dielectric layers having low magnitudes of compressive stress.
Although it may be preferable to have neither tensile nor compressive stress exerted by the various metal and dielectric layers on the silicon wafer, in practice, the quality of the integrated circuit devices may be more effectively maintained by having a small amount of compressive stress exerted by the composite of metal and dielectric layers rather than having a small amount of tensile stress exerted by the layers.
The conventional method of depositing a dielectric layer includes a continuous deposition of dielectric material onto an integrated circuit structure until the desired thickness has been attained. For the purposes of this invention, an integrated circuit structure may comprise a silicon wafer, with various components formed therein, including active devices, dielectric layers, underlying metal lines, oxide-filled dielectric trenches, etc. The prior art continuous deposition of a dielectric layer results in a structure as seen in prior art FIG. 1: a thick, single layer of a dielectric film 10, deposited onto an integrated circuit structure 2. When the dielectric layer made using the prior art process consists of silicon oxide, the layer, after heat treatment, exerts a compressive stress on the underlying integrated circuit structure.
While dielectric materials such as silicon oxide have been conventionally used in the construction of integrated circuit structures to electrically separate and isolate or insulate conductive elements of the integrated circuit structure from one another, as the spacing between such conductive elements in the integrated circuit structure have become smaller and smaller, the capacitance between such conductive elements through the silicon oxide dielectric material has become of increasing concern. Such capacitance has a negative influence on the overall performance of the integrated circuit structure in a number of ways, including its effect on speed of the circuitry and cross-coupling (crosstalk) between adjacent conductive elements.
Because of this ever increasing problem of capacitance between adjacent conductive elements separated by silicon oxide insulation, as the scale of integrated circuit structures continues to reduce, the use of other insulation materials having dielectric constants (k values) lower than conventional silicon oxide (which has a k value of about 4) has been proposed. One such class of material is a carbon doped silicon oxide material wherein at least a portion of the oxygen atoms, bonded to the silicon atoms in a traditional silicon oxide material, are replaced by one or more organic groups such as, for example, an alkyl group such as a methyl (CH.sub.3 --) group. These low k carbon doped silicon oxide dielectric materials have dielectric constants varying from about 2.5 to about 3.5 and are, therefore, of great interest as low dielectric constant substitutes for the conventional silicon oxide insulation material.
Certain low k dielectric layers, however, exhibit tensile stress when deposited as a thick single layer of dielectric film. In some low k films, such as porous ozone deposited films, a conventional post annealing step is sufficient to convert the residual stress of the film from tensile to compressive. However, other low k dielectric layers (such as, for example, low k carbon doped silicon oxide dielectric materials) exhibit tensile stress when deposited as a thick, single layer of dielectric film, and continue to exhibit tensile stress even after annealing. The presence of a dielectric layer with tensile stress, deposited as a thick, single layer of dielectric film onto one or more metal layers which also exhibit tensile stress, results in an integrated circuit device in which the deposited layers tend to crack and detach from the surface of the silicon wafer, resulting in damage to and even failure of the integrated circuit device.
It would, therefore, be desirable to provide a method for treating a film layer of a dielectric material located on an integrated circuit structure in such a manner that the film exhibits compressive stress following the post anneal step.