The present disclosure relates to methods for characterizing an electromigration (EM) parameter related to possible EM failures in signal nets of an integrated circuit (IC) chip design. More particularly, the present disclosure relates to using the EM parameter in an IC chip design flow.
As shown in FIG. 1, a suite of electronic design software tools 100 including tools for functional specification 110, circuit design 120, physical design 130, and verification/sign-off 140 are used in an IC chip design. The functional specification 110 of the IC chip is translated from a high level, logical language into a logic design. The logic design is then converted into a circuit design 120 that describes the exact behavior of digital circuits of the IC chip, as well as the interconnections to inputs and outputs of the digital circuits.
During physical design 130 all design components are instantiated with their geometric representations. The logic design is mapped to a netlist of logic gates of the target technology of the IC chip and the logic gates of the netlist are placed 132 at non-overlapping locations on the IC die. Iterative logical and placement transformations 134 of the logic gates in the semiconductor layers of the IC chip are used to close timing performance and power constraints for the IC chip. Interconnects, i.e., wires and vias, of the metal layers of the IC chip are next routed 136 to connect the logic gates of the netlist. A logic gate, and the wires and vias connected to the output of the logic gate form a signal gate-circuit or signal net. Post-routing optimization 138 of the signal interconnects, which seeks to mitigate possible failure mechanisms, enhances reliability of the IC chip design. Subsequent design for manufacturability can entail extensive error checking before final verification/sign-off 140 of the IC chip design.
One possible failure mechanism that can decrease the reliability of an IC chip design is electromigration (EM) in the wires and vias of the signal gate-circuits of the IC chip. Electromigration is due to momentum transfer from conducting electrons, flowing as a current in the wire, to the matrix of metal atoms of the wire, resulting in a gradual movement of the metal atoms over time. This gradual movement of metal atoms can result in two types of a circuit failure: a gap, i.e., an open circuit, developing in the wire as the metal atoms move away from a location of the wire; or a hillock, i.e., a short circuit, as the metal atoms pile up at a location and spread to touch nearby wires.
At the end of the 1960's, J. R. Black developed an empirical model to estimate the MTTF (mean time to failure) of a wire subject to electromigration, which is expressed by the following equation,
            M      ⁢                          ⁢      T      ⁢                          ⁢      T      ⁢                          ⁢      F        =                  A        ⁡                  (                      J                          -              n                                )                    ⁢              ⅇ                  Eg          kT                      ,where A is a constant based on the cross-sectional area of the wire, J is the current density, Ea is the activation energy, k is the Boltzmann's constant, T is the temperature and n is a scaling factor, usually set to 2.
Signal nets or signal gate-circuits, including wires and vias of the metal layers, interconnect inputs and outputs of the logic gates of the semiconductor layers of the IC chip. A signal gate-circuit includes a signal gate, having specified electrical parameters, and segments of wires and vias connected to an output pin of the signal gate. The signal gate can be characterized by a maximum output capacitance that will provide a maximum output current into the load of the signal gate-circuit under optimal conditions. The physical layout of the signal gate-circuit includes placement of the output pin of the signal gate on the IC die relative to a metal layer and placement of each of the segments of wires and vias forming the signal gate-circuit of the metal layer.
There remains a need to characterize an electromigration (EM) parameter related to possible EM failures in signal nets of an integrated circuit (IC) chip design and to use the EM parameter in an IC chip design flow.