1. Field of the Invention
The present invention relates to an inverter control device for controlling output waveform of an inverter used in a power converter or the like, and to an inverter control method.
2. Description of the Background Art
An inverter device shown in FIG. 1 has been known. The inverter device 50 controls an inverter main circuit 53 which outputs an AC current for driving a load 52 using a DC current from a DC power source 51 as an input. In inverter device 50, an inverter control device 54 formed of a DSP (Digital Signal Processor) instantaneously controls the value of the output current from inverter main circuit 53.
The method of control by inverter control device 54 will be described in the following. A current detector 55 detects an output current from inverter main circuit 53, and the output current value is subjected to A/D conversion at a prescribed sampling frequency by an A/D (Analog/Digital) converter 56. The output current signal I.sub.0 provided by the A/D conversion is input together with a reference current signal I.sub.c to inverter control device 54.
Inverter control device 54 includes an error amplifying portion 57 and a PWM (Pulse Width Modulation) operating portion 58 realized by software programming in the DSP. Error amplifying portion 57 calculates an error amplified signal E=K(I.sub.C -I.sub.0) based on the output current signal I.sub.0 and the reference current signal I.sub.C, where K represents proportional gain.
PWM operating portion 58 calculates a gate on time T.sub.on of switching elements (not shown) constituting inverter main circuit 53, based on the error amplified signal E. The gate on time T.sub.on calculated by inverter control device 54 is output to a timer counter circuit 59. Based on the input gate on time T.sub.on, timer counter circuit 59 generates a gate driving signal G for each switching element, and outputs it to a gate driving circuit 60. In gate driving circuit 60, based on the gate driving signal G input thereto, switching of inverter main circuit 53 is performed.
As for the input of output current signal I.sub.0 and reference current signal I.sub.c, calculation of error amplified signal E, and calculation and output of gate on time T.sub.on, these are continuously executed at prescribed sampling period.
Inverter control device 54 may be described as a proportional control system, as in the following. Referring to the control block diagram of FIG. 2, an output current signal I.sub.0 of an inverter 71 (including PWM operating portion 58, timer counter circuit 59, gate driving circuit 60, inverter main circuit 53 and so on) is detected by a current detector 70 (which corresponds to current detector 55 and A/D converter 56), and the current value is input to error amplifying portion 57. In error amplifying portion 57, a subtracting portion 57a subtracts output current signal I.sub.0 from separately input reference current signal I.sub.C (I.sub.c -I.sub.0). The result of subtraction is proportionally compensated (amplified) by using proportional gain K by a proportional control portion 57b, and its output (=error amplified signal) E is input to inverter 71. Inverter 71 forms, based on the output E from proportional control portion 57b, the output current signal I.sub.0.
On the thus formed output current signal I.sub.0, disturbance N which is inevitable because of the structure of inverter 71 is superposed. As an example, disturbance N is generated because of the following function. More specifically, disturbance N is caused by non-linearity derived from the fact that collector current at turn on of the switch element such as an IGBT (Insulated Gate Bipolar Transistor) is not proportional to the actual on time. If such disturbance N is generated, harmonic distortion of fundamental frequency is superposed on the output current.
It may be possible to remove the influence of such disturbance N by infinitely increasing proportional gain K of proportional control portion 57b. The larger the proportional gain K, the smaller the influence of disturbance N on output current signal I.sub.0. Therefore, ideally, when proportional gain K is made infinite, the error between reference current signal I.sub.C and output current signal I.sub.0 can be made zero.
However, in the actual inverter control device 50, inverter main circuit 53 and other peripheral circuitry have frequency characteristics including delay. Therefore, when proportional gain K is increased, the control system would be unstable, resulting in oscillation. Accordingly, inordinate increase in proportional gain K is not a practical solution.
In view of the foregoing, in the conventional inverter control device 50, a low pass filter 61 (see FIG. 1) is provided on the output side of error amplifying portion 57 to suppress high frequency oscillation of output current signal I.sub.0. It has been also proposed to filter the output (=error amplified signal) E of proportional control portion 57b by low pass filter 61 so as to decrease proportional gain K in high frequency range, and to have PWM operating portion 58 perform PWM operation using the filtered output F.
However, even when such measure is taken, the high frequency oscillation is not always well suppressed, since low pass filter 61 itself has delay which means that low pass filter 61 as a solution newly introduces delay.
Generally, in order to efficiently decrease proportional gain K in high frequency range by using low pass filter 61, cutoff frequency is made lower and the amount of attenuation is increased. However, these measures also result in larger delay of low pass filter 61. Therefore, proportional gain K could not readily be decreased.
The inventors of the present invention proposed, in Japanese Patent Laying-Open No. 7-267495, an inverter control device in which the above described influence of delay is eliminated. This proposal will be described in the following.
In the inverter control device, the inverter output is adjusted to have a desired output waveform by a periodic component control portion. More specifically, first, error between the inverter output waveform and the desired output waveform is calculated using one period of the fundamental wave of the inverter output as a unit period, so as to form an error waveform pattern of one period of the fundamental wave. The thus formed error waveform pattern is advanced relatively in phase by such amount that corresponds to the delay to be addressed, and the pattern thus advanced in phase is added to an inverter driving waveform pattern in accordance with which the inverter has been driven in the last period. In other words, the periodic component control portion integrates the error waveform pattern which has been subjected to the phase advancing process, and thus provides the inverter driving waveform pattern. The inverter output is controlled based on the inverter driving waveform pattern prepared in this manner.
Accordingly, it becomes possible for inverter control device to adjust the inverter output waveform gradually until it matches the desired output waveform, while the influence of delay is eliminated. Further, it becomes possible by the inverter control device to cancel harmonic distortion of the fundamental frequency caused by the fact that the collector current at the time of turn on of the IGBT is not proportional to the actual on time.
However, the conventional inverter control device which eliminates influence of delay and cancels harmonic distortion does not provide sufficient waveform control when the load varies abruptly. Accordingly, undesirable phenomena such as irregular current waveform and excessive current have been experienced, as described in the following.
In the conventional inverter control device in which the inverter driving waveform pattern is prepared by integrating the error waveform pattern which has been subjected to a prescribed phase advancing process, the error waveform pattern is advanced in phase to eliminate influence of delay. However, in actual waveform processing, it is not possible to have the error wave pattern advanced. Therefore, the phase advancing process is a relative one with respect to the inverter driving waveform pattern, realized by delaying the error waveform pattern actually. Therefore, the information of the error waveform pattern is reflected on the inverter output delayed by one period.
If a load 52 connected to inverter 71 is in a steady state, this method exhibits sufficient effect of control. However, if the load changes abruptly, control response to the abrupt change is delayed at least close to one period, and undesirable phenomenon such as irregular current waveform and excessive current have been experienced in this time lag.