1. Field of the Invention
The present invention relates to non-volatile memory technologies, and more specifically, to a method for fabricating electrically erasable programmable read only memories (EEPROM) having split gate memory cells.
2. Description of the Related Art
Flash memory, which is capable of retaining the stored data without continued supply of electrical power, has a stacked gate structure of a floating gate and a control gate. The floating gate, which is placed between the control gate and the semiconductor substrate, is isolated by an insulating oxide layer. When electrons are on the floating gate, they modify the electric field coming from the control gate, which modifies the threshold voltage of the cell. Thus, when the flash memory cell is “read” by applying a specific voltage to the control gate, electrical current will either flow or not flow, depending on the threshold voltage of the cell, which is controlled by the electrons on the floating gate. The presence or absence of current is sensed and translated into 1's and 0's, reproducing the stored data.
The flash EEPROM cells can be classified, according to their gate structure, into: stack gate cells and split gate cells.
FIG. 1A is a cross-sectional view of conventional stack gate flash EEPROM cell, and FIG. 1B is a cross-sectional view of the conventional split gate flash EEPROM cell.
Referring to FIGS. 1A and 1B, the flash memory cell of either stack gate or split gate comprises tunnel oxide 2, floating gate 3, interlayer dielectric 4, control gate 5, drain and source regions 6 and 7 formed in and on a P-type semiconductor substrate 1. The split gate flash memory cell has additional select gate oxide 8 as shown in FIG. 1B.
The stack gate cell of FIG. 1A occupies small area because of its three-dimensional stacked structure but has problems with over-erase when the cell is in an erase operation. The split gate cell of FIG. 1B can avoid the over-erase problem but occupies a larger area, which fails to meet the high integration trend of semiconductor microcircuit devices.
Moreover, the conventional horizonal control gate has a channel length that is formed by overlay control in photolithographic process, and hence variations in threshold voltage or current are observed when driving the control gate. Further, the control gate is formed in parallel to the surface of substrate or wafer, which requires consideration of the overlay margin mentioned above.