Integrated circuits contain many different layers of materials, including dielectric layers that insulate adjacent conducting layers from one another. With each decrease in the size of integrated circuits, the individual conducting layers and elements within the integrated circuits grow closer to adjacent conducting elements. This necessitates the use of dielectric layers made of materials with low dielectric constants to prevent problems with capacitance, cross talk, etc. between adjacent conducting layers and elements.
The use of copper as conductive lines in integrated circuits has allowed further size reductions to be achieved. Copper interconnects are typically formed via damascene processes. In the so-called dual damascene process, which is used to fabricate integrated circuits with, for example, 130 nm and smaller technology nodes, a copper interconnect is formed by etching a via completely through a dielectric layer, etching a trench that overlaps the via partially through the dielectric layer, filling the trench and via with an electrically conductive material via a plating process, and then removing excess conductive material from surfaces adjacent to the via and trench by a polishing process.
Where the dielectric layer is formed from a single low dielectric constant (“low k”) material, the process may be referred to as a “monolithic dual damascene” process. Monolithic dual damascene processes typically utilize a dielectric layer having an etch stop layer disposed between a first layer and a second layer of a low k material. The etch stop layer helps to stop the trench etch at a precise, reproducible depth in the dielectric layer.
The etch stop layer is typically made of a material with a different etching chemistry than the surrounding dielectric layer. For example, where an organic low k material is used for the dielectric layer, the etch stop may be formed from a silicon oxide-based material. In this case, an oxygen-containing plasma, for example, may be used to etch the organic material, as this etching process would substantially stop upon reaching the silicon oxide-based etch stop layer. Likewise, where a silicon dioxide-based dielectric layer is used, a silicon nitride etch stop layer may be used to stop a fluorine-based etching process.
However, the use of an etch stop layer within a dielectric layer creates a greater number of total layers in a device, and therefore a greater number of interfaces between layers within the device. It also requires separate deposition steps to be used for depositing the first layer of low k material, the etch stop layer, and the second layer of the low k material, thereby increasing the complexity of device fabrication.
Where the dielectric material is an inorganic material and the etch stop layer is silicon nitride, silicon carbide or other silicon based materials, it may be possible to deposit both the dielectric material and the etch stop layer via chemical vapor deposition (“CVD”) processes using a single CVD system (possibly with separate chambers for each process). However, the dielectric constants of current inorganic dielectric materials are generally limited to k≧3.0, and therefore may not be suitable for use in sub-65 nm circuits, which may require dielectric constants of k≦2.5.
Some organic dielectric materials may have suitably low dielectric constants. However, many conventional organic dielectric films are deposited via spin-on processes. The use of a spin-on deposition process may be less clean than a CVD process. Furthermore, this may require the use of separate tools to deposit the organic material and the etch stop layer, as many etch stop materials are deposited by CVD.