The present invention is generally related to power management techniques for computer chips. More particularly, the present invention is generally related to a power efficient flip-flop design.
Flip-Flops are the basic elements in any sequential machine, such as a finite state machine, counter, register file, storage buffer, and the like. Accordingly, the design of the flip-flop has always been a focus of VLSI designers.
Conventional flip-flop designs are mainly focused on performance or area optimization, especially with respect to flip-flops used in microprocessors. However, with the ever increasing demand for power in microprocessor chips, it is imperative that the power efficiency of every circuit, including flip-flops, in a microprocessor chip be maximized. Accordingly, techniques have been developed for reducing power consumption in microprocessor chips, such as placing circuits, including conventional flip-flops, in a sleep mode.
Even when using techniques for reducing power consumption, current semiconductor technology development indicates that transistor off current (i.e., leakage current in each individual device and standby current in the whole chip) is comparable to the transistor xe2x80x9conxe2x80x9d current, especially with respect to the 0.1 microns technology era. For example, even when circuits having flip-flops are functioning in an idle or sleep mode, a significant amount of power is dissipated through leakage paths.
In one respect, the present invention includes an exemplary method for minimizing power consumption by a circuit, such as a flip-flop. The method includes steps of providing power to a first latch in the circuit; capturing data in the first latch; transmitting data to a second latch in the circuit; and removing power from the first latch.
In another respect, the present invention includes an exemplary power efficient circuit having a first latch and a second latch connected to the first latch. The second latch is configured to receive data captured by the first latch. The circuit further includes a power switch connected to the first latch, and the power switch regulates power provided to the first latch. The first latch includes a high speed latch and the second latch includes a low leakage latch. The power switch minimizes power consumption by limiting the period of time power is provided to the high speed latch. Also, the power efficient circuit minimizes the leakage current generated by the high speed latch when power is not provided to the high speed latch by substantially eliminating a leakage path to ground using a virtual ground, the power switch and a decoupling device.
In comparison to known prior art, certain embodiments of the invention are capable of achieving certain aspects, such as providing an improved flip-flop design to minimize power consumption. Those skilled in the art will appreciate these and other aspects of various embodiments of the invention upon reading the following detailed description of a preferred embodiment with reference to the below-listed drawings.