Clock signals are often used in electronic circuits for timing internal operation of various circuits necessary to execute an operation. For example, in synchronous memories, external clock signals are provided to the memory and internally distributed to different circuits of the circuit to carry out memory operations. Typically, a clock distribution network is used to route internal clock signals generated from the external clock signal to the different circuits. In this manner, operation of the integrated circuit can be coordinated with the external clock signals.
When generating and routing the internal clock signals, however, maintaining the quality of the clock signals while being distributed to the various circuits can present challenges. An example of a challenge to maintaining the quality of the clock signals is generating internal clock signals while maintaining the duty-cycle of the external clock signals. The duty-cycle of a clock signal becomes distorted when the ratio of the high and low portions of a generated clock signal is different than that of the clock signal from which it is generated. Duty-cycle distortion may be process-induced, that is, the device characteristics of the clock generation circuits and clock distribution circuits can shift due to variation in the manufacturing process for the integrated circuit causing the resulting internal clock signal to be distorted. As a result of the duty-cycle distortion, when generating and distributing the internal clock signal, the various circuits receive a distorted version of the external clock signal. Due to the duty-cycle distortion, performance of the integrated circuit may be reduced, and in extreme cases, may cause the integrated circuit to function incorrectly.
Various approaches have been used to manage duty-cycle distortion in generating and distributing internal clock signals. For example, where external differential clock signals (i.e., both a clock signal and its complement) are used, the clock distribution network includes differential clock paths having separate clock paths for each of the differential clock signals. As known, using differential clock paths may reduce duty-cycle distortion in distributing internal differential clock signals to various circuits. This approach, however, consumes significant power to drive the circuitry of the differential clock path and requires considerable space to accommodate the parallel clock paths of the differential clock path.
Another example approach is to generate two internal single-ended clock signals (sometimes referenced as “pseudo-differential”) from an external differential clock signal and distribute the single-ended clock signals to be used to generate an internal differential clock signal for the various circuits. This approach also requires two separate clock paths to distribute the single-ended clock signals and suffers from the same issues as using a differential clock path, that is, significant power consumption and space for the two clock paths. Another example approach is to convert an external differential clock signal into a single-ended clock signal for distribution to the circuits. Although this approach has the benefits of using less power and requiring less space for the clock path in comparison to the previously discussed approaches, as known, distributing a single-ended clock signal and generating an internal differential clock signal from the single-ended clock signal is more susceptible to introducing duty-cycle distortion, such as that related to process-induced distortion.