Generally, the electrical resistance of a microelectronic structure such as a word line, bit line or conductive plug varies according to the materials from which the structure is formed, the cross-sectional area of the structure and the length thereof. As microelectronic devices become more highly integrated, structures such as conductive lines generally have a smaller cross-sectional area and contact other microelectronic structures at smaller contact areas, thereby increasing electrical resistance. Consequently, signal transmission may be delayed, which may in turn reduce the operating speed of the device. To prevent such delay, the cross-sectional area of the conductive line or the contact area may be increased, but increasing cross-sectional area of the conductor or increasing the contact area can limit the density of the layout of the device.
A conventional approach to decreasing electrical resistance of a conductor in a device is to utilize a conductive structure including a tungsten silicide layer with a resistance of approximately 400 .OMEGA./cm.sup.2 to 60 .OMEGA./cm.sup.2. As illustrated in FIG. 1, a contact area 12 is defined on a semiconductor substrate 10. Conductive impurities may be implanted into the substrate 10 at the contact area 12, in order to lower the potential barrier between the contact area 12 and a conductive layer formed on the contact area 12. An element, such as transistor, may be formed on or in the semiconductor substrate 10 at the contact area 12.
A first insulation layer 14 is then formed on the entire surface of the semiconductor substrate 10. A contact hole 16 is formed in the first insulation layer 14, exposing the contact area 12. Residues generated during formation of the contact hole 16 are then removed, and a conductive layer 18, typically an impurity-doped polycrystalline silicon (polysilicon) layer is formed, covering the first insulation layer 14 and the exposed area of the contact area 12. A tungsten silicide layer 20 is then formed on the conductive layer 18. As shown in FIG. 2, a second insulation film 22 is formed on the tungsten silicide layer 20. The resultant structure is then annealed to thermally stabilize the structure.
The thermal expansion coefficient of the tungsten silicide layer 20 generally is greater than that of the impurity-doped polysilicon used for the conductive layer 18. Consequently, during the annealing process the expansion force generated by the tungsten silicide layer 20 is typically greater than that generated by the conductive layer 18, causing stress in the tungsten silicide layer 20. The stress may cause lifting at portions 26 of the interface between the conductive layer 18 and the tungsten silicide layer 20.
Conventional techniques for preventing this lifting include drying wafers under a vacuum for an extended period after the silicide layer is formed. However, even with extensive drying and vacuum evacuation, monitoring may be required after annealing to determine whether lifting has occurred. Monitoring typically requires sampling of a large number of wafers, leading to the sacrifice of a significant number of wafers. Consequently, conventional techniques for formation of silicide structures may reduce productivity of fabrication processes for microelectronic devices incorporating the structures.