1. Field of the Invention
The present invention relates to a method for manufacturing thin film transistors.
2. Description of the Related Art
With respect to a thin film transistor, there has been known a technique where a contact resistance is lowered by interposing a silicon layer of high impurity concentration between a silicon layer and a source electrode or a drain electrode (see JP-A-11-87721).
In the conventional thin film transistor, a silicon layer which constitutes a channel and a silicon layer of high impurity concentration which constitutes a source electrode and a drain electrode are formed and hence, it is necessary to form them by etching respectively. Further, the silicon layer of high impurity concentration per se has the resistance and hence, it is desirable to form such a silicon layer with a small thickness. To prevent an erroneous operation due to absorption of light, it is preferable to form silicon layers in two layers such that these layers have a small thickness respectively. However, in forming the source electrode and the drain electrode, the silicon layer which constitutes the channel is also etched so that the reduction of thicknesses of these layers is limited.