1. Field of the Invention
The invention relates to a bar circuit for an integrated circuit, and more particularly to a bar circuit an on-chip inductor circuit.
2. Description of the Prior Art
As integrated circuit devices continue to shrink in dimension, the demand to integrate different functionality on the same integrated circuit die continues to grow. For example, portable wireless communication products have become high volume consumer devices. Some of these devices are now operating in the 1-2 GHz frequency range. There is, as a consequence, a demand to integrate RF front end circuits into high-yield silicon integrated circuit processes to allow a combination of analog, digital, and RF functions on the same integrated circuit die. Yet, some considerable difficulty has been experienced in attempts to fabricate inductors having high quality factors (Q) in silicon technology for RF circuits which are used in communications.
Attempts have been made to build high-Q inductors in silicon integrated circuit technology,. but have yielded Q factors of only three to eight. Problems associated with the use of silicon technology in these scenarios, in part, is a result of the conductivity of silicon substrate which tends to induce losses. As frequencies approach the self-resonant frequency, the inductance value decreases which is most undesirable. Losses in the conductive silicon substrates can be increased by the high dielectric constant of the insulators under the conductors and the relatively large values of stray capacitance coupling to the silicon substrate.
Some attempts have been made to provide oxide-encased, spiral-type inductors for silicon technology, with such encased inductors being disposed over a cavity which is etched into the silicon substrate. Others have attempted to provide higher-Q inductors in a five or six-level metal BiCMOS technology. The conductors in these instances are still encased in oxide but are far removed from the silicon substrate by virtue of a large number of insulator and metal levels. The number of these levels, however, is far in excess of the two to four levels commonly utilized in CMOS technology.
An exemplary lumped circuit element for an on-chip inductor is shown in FIG. 1. Ls represents an intrinsic inductor; Rs does a parasitic capacitance; Cp does a parasitic capacitance of an on-chip inductor; Cox does the capacitance between the on-chip inductor and the substrate; and Rb does a resistance to simulate the eddy current portion. Cox and Rb contribute to the substrate loss. When the on-chip inductor is in an operation mode, AC current may generate the change of the magnetic flux and thus induce eddy current in the substrate. Furthermore, the inductor itself can be considered as an energy tank. More eddy current generated in the substrate means more energy loss, equivalent to the degradation of Quality factor. In addition, cross talk of the inductor through the substrate happens because of the lower Rb contributing to the substrate.
In general, guard rings are used to prevent from the cross talk. However, the eddy current still exists and causes the degraded performance of the inductor. On the other hand, metal shield may be utilized to reduce the eddy current, but the inductor performance is sacrificed.
It is an object of the present invention to provide a bar circuit on an integrated circuit. The bar circuit can reduce cross talk and eddy current induced by the inductors of the integrated circuit with increasing the resistance of a semiconductor substrate.
It is another object of the present invention to provide a bar circuit in an on-chip inductor circuit. Strips of deep well below generally strips of well in a semiconductor substrate can reduce electromagnetic interference caused by the semiconductor substrate.
In the present invention provides a bar circuit for reducing cross talk and eddy current of an integrated circuit comprising a semiconductor substrate with a first conductivity type. A strip of first well with a second conductivity type is in the semiconductor substrate. A strip of second well with the second conductivity type is in the semiconductor substrate, below and adjacent to the strip of first well, whereby forms a junction barrier for, reducing the cross talk and the eddy current.