1. Technical Field
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device having an alignment mark used as an alignment key in a packaging operation for semiconductor chips and a method of fabricating the same.
2. Discussion of the Related Art
Semiconductor devices formed on a semiconductor substrate are typically assembled for connection to external devices and also packaged to protect these semiconductor devices from the external environment. In particular, a semiconductor device may have a pad electrode layer used as an input/output terminal for being connected to an external device, and an alignment mark used as an alignment key for assembling the semiconductor device. For example, a semiconductor device used as a driving device of a LCD (liquid crystal display) device may be assembled on a glass substrate. This is known as the COG (chip on glass) assembly method.
According to the COG assembly method, the semiconductor device is aligned on the glass substrate, using an align mark. For example, as for the COG assembly method, “Panel Structure for Chip on Glass” of Korean Patent No. 0258719 can be referred. However, a conventional alignment mark structure for a semiconductor device may cause alignment errors when the processes change during a fabricating operation.
FIG. 1 is a cross-sectional view illustrating a semiconductor device having a conventional alignment mark structure.
Referring to FIG. 1, an align mark layer 55 is formed on a semiconductor substrate 50 and enclosed by a passivation layer 60. A polyimide layer 70 to protect the semiconductor device is formed on the passivation layer 60. The polimide layer 70 is patterned so as to expose the passivation layer 60 formed on the align mark layer 55. Generally, the align mark layer 55 is formed in a field region (not shown) which is formed of an insulating layer for isolation.
An optical alignment apparatus perceives the contrast between the field region and a portion of the align mark layer 55 and aligns a semiconductor device by using this contrast between the field region and the align mark layer 55. However, a thickness (h) deviation of the passivation layer 60 formed on the align mark layer 55 may change the color of the portion of the align mark layer 55, and this color change may result in an alignment error for these semiconductor devices. As optical alignment apparatus processes the alignment of a semiconductor device based upon the contrast between the field region and the align mark layer 55 within a standard range, these alignment apparatuses may as a result not achieve proper alignment for a semiconductor device having a contrast outside of the standard range.
The contrast of the passiviation layer 60 changes significantly according to the thickness (h) deviation of the passiviation layer 60. Thus, it may be difficult to control the contrast by controlling the thickness (h) of the passivation layer 60. Accordingly, even though the passivation layer 60 may be within an allowable process margin range, an alignment error with respect to the semiconductor device may still occur.
Thus, there is a need for a semiconductor device having reduced alignment error. In addition, there is also a need for a method of fabricating a semiconductor device that reduces alignment error during the assembly of the semiconductor device and that is cost-effective.