1. Field of the Invention
The present invention relates to a scanning drive circuit and a display device including the same. More particularly, the invention relates to a scanning drive circuit in which a ratio between a display time period and a non-display time period in each of display elements composing a display device can be readily adjusted, and a display device including the same.
2. Description of the Related Art
In addition to a liquid crystal display device composed of voltage-driven liquid crystal cells, a display device including a light emitting portion (for example, an organic electro-luminescence light emitting portion) which emits a light by causing a current to flow through the light emitting portion, and a drive circuit for driving the same are known as a display device including display elements two-dimensionally disposed in a matrix.
A luminance of a display element including a light emitting portion which emits a light by causing a current to flow through the light emitting portion is controlled in accordance with a value of the current caused to flow through the light emitting portion. A simple matrix system and an active matrix system are well known as a drive system in the display device as well including such a display element (for example, the organic electro-luminescence display device) similarly to the case of the liquid crystal display device. Although the active matrix system has a disadvantage that a configuration is complicated as compared with the simple matrix system, the active matrix system has various advantages that a high luminance can be obtained for an image, and so forth.
Various drive circuits each including a transistor and a capacitor portion are well known as a circuit for driving a light emitting portion in accordance with the active matrix system. For example, Japanese Patent Laid-Open No. 2005-31630 discloses a display device using a display element including an organic electro-luminescence light emitting portion and a drive circuit for driving the same, and a method of driving the display device. The drive circuit is a drive circuit including six transistors and one capacitor portion (hereinafter referred to as a 6Tr/1C drive circuit). FIG. 19 shows an equivalent circuit diagram of a drive circuit (6Tr/1C drive circuit) composing a display element belonging to an m-th row and an n-th column in a display device having display elements two-dimensionally disposed in a matrix. It should be noted that a description will now be given on the assumption that the display elements are scanned in a line sequential manner every row.
The 6Tr/1C drive circuit includes a write transistor TRW, a drive transistor TRD, and a capacitor portion C1. Also, the 6Tr/1C drive circuit includes a first transistor TR1, a second transistor TR2, a third transistor TR3, and a fourth transistor TR4.
In the write transistor TRW, one source/drain region is connected to a data line DTLn, and a gate electrode is connected to a scanning line SCLm. In the drive transistor TRD, one source/drain region is connected to the other source/drain region of the write transistor TRW to compose a first node ND1. One terminal of the capacitor portion C1 is connected to a power supply line PS1. In the capacitor portion C1, a predetermined reference voltage (a voltage VCC, in the example of the related art shown in FIG. 19, which will be described later) is applied to one terminal, and the other terminal and a gate electrode of the drive transistor TRD are connected to each other to compose a second node ND2. The scanning line SCLm is connected to a scanning circuit (not shown), and a data line DTLn is connected to a signal outputting circuit 100.
In the first transistor TR1, one source/drain region is connected to the second node ND2, and the other source/drain region is connected to the other source/drain region of the drive transistor TRD. The first transistor TR1 composes a switch circuit portion connected between the second node ND2 and the other source/drain region of the drive transistor TRD.
In second transistor TR2, one source/drain region is connected to a power source line PS3 to which a predetermined initialization voltage VIni (for example, 4 V) in accordance with which a potential at the second node ND2 is initialized is applied, and the other source/drain region is connected to the second node ND2. The second transistor TR2 composes a switch circuit portion connected between the second node ND2 and the power supply line PS3 to which the predetermined initialization voltage VIni is applied.
In the third transistor TR3, one source/drain region is connected to the power supply line PS1 to which a predetermined drive voltage VCC (for example, 10 V) is applied, and the other source/drain region is connected to the first node ND1. The third transistor TR3 composes a switch circuit portion connected between the first node ND1 and the power supply line PS1 to which the predetermined drive voltage VCC is applied.
In the fourth transistor TR4, one source/drain region is connected to the other source/drain region of the drive transistor TRD, and the other source/drain region is connected to one terminal of a light emitting portion ELP (more specifically, an anode electrode of the light emitting portion ELP). The fourth transistor TR4 composes a switch circuit portion connected between the other source/drain region of the drive transistor TRD, and the one terminal of the light emitting portion ELP.
Each of the gate electrode of the write transistor TRW, and the gate electrode of the first transistor TR1 is connected to the scanning line SCLm. The gate electrode of the second transistor TR2 is connected to an initialization control line AZm. A scanning signal supplied to a scanning line SCLm−1 (not shown) which is scanned right before the scanning line SCLm is supplied to the initialization control line AZm as well. Each of the gate electrode of the third transistor TR3, and the gate electrode of the fourth transistor TR4 is connected to a display control line CLm through which a display state/non-display state of the display element is controlled.
For example, each of the write transistor TRW, the drive transistor TRD, the first transistor TR1, the second transistor TR2, the third transistor TR3, and the fourth transistor TR4 is composed of a p-channel Thin Film Transistor (TFT). Also, the light emitting portion ELP is provided on an interlayer insulating layer or the like which is formed so as to cover the drive circuit. In the light emitting portion ELP, the anode electrode is connected to the other source/drain region of the fourth transistor TR4, and a cathode electrode is connected to the power supply line PS2. A voltage Vcat (for example, 10 V) is applied to the cathode electrode of the light emitting portion ELP. In FIG. 19, reference symbol CEL designates a parasitic capacitance parasitized on the light emitting portion ELP.
When transistors are composed of TFTs, it may be impossible that threshold voltages thereof disperse to a certain extent. When amounts of currents caused to flow through the light emitting portions ELP, respectively, disperse along with a dispersion of the threshold voltages of the drive transistors TRD, uniformity of the luminances in the display device becomes worse. For this reason, it is necessary that even when the threshold voltages of the drive transistors TRD disperse, the amounts of currents caused to flow through the light emitting portions ELP, respectively, are prevented from being influenced by this dispersion. As will be described later, the light emitting portions ELP are driven so as not to be influenced by the dispersion of the threshold voltages of the drive transistors TRD.
A method of driving the display element belonging to the m-th row and the n-th column in the display device in which the display elements are two-dimensionally disposed in a matrix of N×M will be described hereinafter with reference to FIGS. 20A to 20D. FIG. 20A shows a schematic timing chart of the signals on the initialization control line AZm, the scanning line SCLm, and the display control line CLm, respectively. FIGS. 20B, 20C and 20D respectively schematically show an ON/OFF state and the like of each of the write transistor TRW, the drive transistor TRD, the first transistor TR1, the second transistor TR2, the third transistor TR3, and the fourth transistor TR4 in the 6TR/1C drive circuit. For the sake of convenience of the description, a time period for which the initialization control line AZm is scanned is called an (m−1)-th horizontal scanning time period, and a time period for which the scanning line SCLm is scanned is called an m-th horizontal scanning time period.
As shown in FIG. 20A, an initializing process is carried out for the (m−1)-th horizontal scanning time period. The initializing process will now be described in detail with reference to FIG. 20B. For the (m−1)-th horizontal scanning time period, a potential of the initialization control line AZm changes from a high level to a low level, and a potential of the display control line CLm changes from the low level to the high level. It is noted that a potential of the scanning line SCLm is held at the high level. Therefore, for the (m−1)-th horizontal scanning time period, the write transistor TRW, the first transistor TR1, the third transistor TR3, and the fourth transistor TR4 are each in an OFF state. On the other hand, the second transistor TR2 is held in an ON state.
The predetermined initialization voltage VIni in accordance with which the potential at the second node ND2 is initialized is applied to the second node ND2 through the second transistor TR2 held in the ON state. As a result, the potential at the second node ND2 is initialized.
Next, as shown in FIG. 20A, for the m-th horizontal scanning time period, a video signal Vsig is written to the display element concerned. At this time, processing for canceling the threshold voltage Vth of the drive transistor TRD is executed together with the write operation. Specifically, the second node ND2 and the other source/drain region of the drive transistor TRD are electrically connected to each other, so that the video signal Vsig is applied from the data line DTLn to the first node ND1 through the write transistor TRW which is held in the ON state in accordance with a signal from the scanning line SCLm. As a result, the potential at the second node ND2 changes toward a potential obtained by subtracting the threshold voltage Vth of the drive transistor TRD from the video signal Vsig.
A detailed description will be given with reference to FIGS. 20A and 20C. For the m-th horizontal scanning time period, the potential of the initialization control line AZm changes from the low level to the high level, and the potential of the scanning line SCLm changes from the high level to the low level. It is noted that the potential of the display control line CLm is held at the high level. Therefore, for the m-th horizontal scanning time period, the write transistor TRW and the first transistor TR1 are each held in the ON state. On the other hand, the second transistor TR2, the third transistor TR3, and the fourth transistor TR4 are each held in the OFF state.
The second node ND2, and the other source/drain region of the drive transistor TRD are electrically connected to each other through the first transistor TR1 held in the ON state. Thus, the video signal Vsig is applied from the data line DTLn to the first node ND1 through the write transistor TRW which is held in the ON state in accordance with the signal from the scanning line SCLm. As a result, the potential at the second node ND2 changes toward the potential obtained by subtracting the threshold voltage Vth of the drive transistor TRD from the video signal Vsig.
That is to say, if the potential at the second node ND2 is initialized in the initializing process described above so that the drive transistor TRD is turned ON at commencement of the m-th horizontal scanning time period, the potential at the second node ND2 changes toward the potential of the video signal Vsig applied to the first node ND1. However, when a difference in potential between the gate electrode and one source/drain region of the drive transistor TRD reaches the threshold voltage Vth of the drive transistor TRD, the drive transistor TRD is turned OFF. For the OFF state, the potential at the second node ND2 is approximately expressed by (Vsig−Vth).
Next, the current is caused to flow through the light emitting portion ELP via the drive transistor TRD, thereby driving the light emitting portion ELP.
A detailed description will now be given with reference to FIGS. 20A and 20D. The potential at the scanning line SCLm changes from the low level to the high level at the termination of the m-th horizontal scanning time period. In addition, the potential of the display control line CLm changes from the high level to the low level. It should be noted that the potential of the initialization control line AZm is held at the high level. The third transistor TR3 and the fourth transistor TR4 are each held in the ON state. On the other hand, the write transistor TRW, the first transistor TR1, and the second transistor TR2 are each held in the OFF state.
The drive voltage VCC is applied to one source/drain region of the drive transistor TRD through the third transistor TR3 held in the ON state. In addition, the other source/drain region of the drive transistor TRD and one terminal of the light emitting portion ELP are electrically connected to each other through the fourth transistor TR4 held in the ON state.
The current caused to flow through the light emitting portion ELP is a drain current Ids which is caused to flow from the source region to the drain region of the drive transistor TRD. Thus, when the drive transistor TRD ideally operates in a saturated region, the drain current Ids can be expressed by Expression (1):Ids=k·μ·(Vgs−Vth)2  (1)
where μ is an effective mobility, Vth is a threshold voltage, Vgs is a voltage developed across the source region and the gate electrode of the drive transistor TRD, and k is a constant.
Here, the constant k is given by Expression (2):k=(1/2)·(W/L)·Cox  (2)
where L is a channel length, W is a channel width, and Cox=(relative permeability of gate insulating layer)×(permittivity of vacuum)/(thickness of gate insulating layer).
Thus, as shown in FIG. 20D, the drain current Ids is caused to flow through the light emitting portion ELP, so that the light emitting portion ELP emits a light with a luminance corresponding to the drain current Ids.
Also, the voltage Vgs is given by Expression (3):Vgs≈VCC−(Vsig−Vth)  (3)
Therefore, Expression (1) can be transformed into Expression (4):
                                                                        I                ds                            =                              k                ·                μ                ·                                                      {                                                                  V                        CC                                            -                                              (                                                                              V                            sig                                                    -                                                      V                            th                                                                          )                                            -                                              V                        th                                                              }                                    2                                                                                                        =                              k                ·                μ                ·                                                      (                                                                  V                        CC                                            -                                              V                        sig                                                              )                                    2                                                                                        (        4        )            
As apparent from Expression (4), the threshold voltage Vth of the drive transistor TRD has no relation to the value of the drain current Ids. In other words, the drain current Ids corresponding to the video signal Vsig can be caused to flow through the light emitting portion ELP without being influenced by the value of the threshold voltage Vth of the drive transistor TRD. According to the driving method described above, the dispersion of the threshold voltages Vth of the drive transistors TRD is prevented from exerting an influence on any of the luminances of the display elements.