Traditional caches in multi-processor system operate independently. Data coherency between the caches is managed by coherency protocols, such as e.g. MESI, MOSI, MOESI, and others.
In those cache systems, the data of the same memory addresses may be duplicated and reside in multiple of the caches, wasting memory space and power and creating the need for coherency management.
A more advanced cache system for multi-core processors is disclosed in WO 2006/072061 A2 (PCT/US2005/047592), Hughes et al. in which each processor has a nearest cache, but yet has access to the caches of all other processors via a ring bus. A set of data related to a specific memory address is usually stored in solely one of the caches, but may be transferred from a cache to the cache nearest to the processor currently accessing the data.
However this method has various issues. The ring bus limits the scalability of the number of processor respective caches as it becomes inefficient. Furthermore moving data from one cache to another consumes significant time and energy.
Within the patent terms such as “processor”, “processors” (plural) or “a plurality of processors” are used. They are related to multi processor computer systems, which are typically multi-core single-chip processors or multi-core multi chip-processors, with the plurality of chips being mounted within one single package.
Multi-chip processors are preferably being built of a stack of processor chips, the stack may comprise other chip structures, such as static and/or dynamic memories. For further details reference is made to PCT/EP 2009/007415, Vorbach, which will be used for further explanation of the implementation details and is incorporated by reference into this patent application for full disclosure.
Furthermore the described concepts are scalable, even up to system level. The inventive tree structure may be extended beyond a single processor (which may comprise a plurality of processors/processor cores) and used for multi processor systems, e.g. massive parallel computers (high performance computing) and/or multi processor mainboards, as they are used e.g. in server systems.
The present invention describes a new memory hierarchy for multicore processor architectures, such as e.g. the ZZYX processor, or other multicore processors such as the Intel Xeon, Pentium, Core2 and/or Larrabee, AMD processors, Tilera, or graphics processors such as ATI and nVidia (e.g. CUDA).
While the invention is already advantageous for multi-processor arrangements, it becomes even more efficient if at least some of the processors comprise a plurality of Load/Store-units and/or Address-Generators. Having the ability of accessing multiple memories or memory sections through a plurality of rather independent Load/Store-units and/or Address-Generators increases bandwidth and coherence problems significantly for state of the art implementations of the memory hierarchy.
It shall be noted that whereas hereinafter, frequently terms such as “each” or “every” and the like are used when certain preferred properties of elements of the architecture and so forth. are described. This is done so in view of the fact that generally it may be highly preferred to have certain advantageous properties for each and every element of a group of similar elements. It will be obvious to the average skilled person however, that some if not all of the advantages of the present invention disclosed hereinafter might be obtainable, even if only to a lesser degree, if only some but not all similar elements of a group do have a particular property. Thus, the use of certain words such as “each”, “any”, “every” and so forth. is intended to disclose the preferred mode of invention and whereas it is considered feasible to limit any claim to only such preferred embodiments, it will be obvious that such limitations are not meant to restrict the scope of the disclosure to only the embodiments preferred.
It shall also be noted that notwithstanding the fact that a completely new architecture is disclosed hereinafter, several aspects of the disclosure are considered inventive per se, even in cases where other advantageous aspects described hereinafter are not realized.
The technology described in this patent is especially applicable on ZYXX processors as described in PCT/EP 2009/007415, Vorbach, which is fully incorporated by reference into this patent application by reference for detailed disclosure.
The ZZYX processor comprises multiple ALU-Blocks in an array with pipeline stages between each row of ALU-Blocks. Each ALU-BLOCK may comprise further internal pipeline stages. In contrast to reconfigurable processors data flows preferably in one direction only, in the following exemplary embodiments from top to bottom. Each ALU may execute a different instruction on a different set of data, whereas the structure may be understood as a MIMD (Multiple Instruction, Multiple Data) machine.
The ZZYX processor is optimized for loop execution. In contrast to traditional processors, instructions once issued to the ALUs may stay the same for a plurality of clock cycles, while multiple data words are streamed through the ALUs. Each of the multiple data words is processed based on the same temporarily fixed instructions. After a plurality of clock cycles, e.g. when the loop has terminated, the operation continues with one or a set of newly fetched, decoded and issued instruction(s).
The ZZYX processor provides sequential VLIW-like processing combined with superior dataflow and data stream processing capabilities. The ZZYX processor cores are scaleable in at least 3 ways:    1. The number of ALUs can be scaled at least two dimensionally according to the required processing performance; the term multi-dimensional is to refer to “more than one dimension”. It should be noted that stacking several planes may lead to a three dimensional arrangement;    2. the amount of Load/Store units and/or Local Memory Blocks is scalable according to the data bandwidth required by the application;    3. the number of ZZYX cores per chip is scalable at least one dimensionally, preferably two or more dimensionally (in particular as definable by interconnection topology), according to the product and market. Low cost and low power mobile products (such as mobile phones, PDAs, cameras, camcorders and mobile games) may comprise only one or a very small amount of ZZYX cores, while high end consumer products (such as Home PCs, HD Settop Boxes, Home Servers, and gaming consoles) may have tens of ZZYX cores or more.            High end applications, such as HPC (high performance computing) systems, accelerators, servers, network infrastructure and high and graphics may comprise a very large number of interconnected ZZYX cores.        
ZZYX processors may therefore represent one kind of multicore processor and/or chip multiprocessors (CMPs) architecture.
The major benefit of the ZZYX processor concept is the implicit software scalability. Software written for a specific ZZYX processor may run on single processor as well as on a multi processor or multicore processor arrangement without modification as will be obvious from the text following hereinafter. Thus, the software scales automatically according to the processor platform it is executed on.
The concepts of the ZZYX processor and the inventions described in this patent are applicable on traditional processors, multithreaded processors and/or multi-core processors. A traditional processor is understood as any kind of processor, which may be a microprocessor, such as an AMD Phenom, Intel Pentium, Core2 or Xeon, IBM's and Sony's CELL processor, ARM, Tensilica or ARC; but also DSPs such as the C64 family from TI, 3DSP, Starcore, or the Blackfin from Analog Devices.
The concepts disclosed are also applicable on reconfigurable processors, such as SiliconHive, IMEC's ADRES, the DRP from NEC, Stretch, or IPFlex; or multi-processors systems such as Picochip or Tilera. Most of the concepts, especially the memory hierarchy, local memories elements, and Instruction Fetch units as well as the basic processor model can be used in FPGAs, either by configuring the according mechanisms into the FPGAs or by implementing according hardwired elements fixedly into the silicon chip. FPGAs are known as Field Programmable Gate Arrays, well known from various suppliers such as XILINX (e.g. the Virtex or Spartan families), Altera, or Lattice.
The concepts disclosed are particularly well applicable on stream processors, graphics processors (GPU) as for example known from NVidia (e.g. GeForce, and especially the CUDA technology), ATI/AMD and Intel (e.g. Larrabee), and especially General Purpose Graphics Processors (GPGPU) also know from NVidia, ATI/AMD and Intel.
ZZYX processors may operate stand alone, or integrated partially, or as a core into traditional processors or FPGAs; it is noted that any such FPGA integrating a ZZYX processor as disclosed hereinafter will be or have coarse granular elements. While ZZYX may operate as a co-processor or thread resource connected to a processor (which may be a microprocessor or DSP), it may be integrated into FPGAs as processing device. FPGAs may integrate just one ZZYX core or multiple ZZYX cores arranged in a horizontal or vertical stripe or as a multi-dimensional matrix.
All described embodiments are exemplary and solely for the purpose of outlining the inventive apparatuses and/or methods. Different aspects of the invention can be implemented or combined in various ways and/or within or together with a variety of other apparatuses and/or methods.
Various patent and literature documents which are incorporated by reference into this patent application for full disclosure and it is expressively stated, that using that methods within the scope of and in conjunction with this invention is regarded inventive per se and might be claimed.