1. Field of the Invention
The present invention relates to the problem of resonance due to plating stubs on circuit boards.
2. Background of the Related Art
An integrated circuit (IC), also commonly referred to as a “microchip” or “chip,” is an electronic circuit comprising miniaturized semiconductor devices formed in a semiconductor substrate. Many copies of an integrated circuit may be formed on a large semiconductor wafer, which is then cut into individual pieces referred to as a “die chips” or “dies,” each containing a copy of the integrated circuit. Semiconductor materials such as silicon are typically brittle, so a fragile die chip is commonly packaged on a carrier, referred to as a “chip package” or simply “package.” The substrate of the chip package functions as an interposer for interfacing the chip with a printed circuit board (PCB). For example the processor for a computer may be carried on a chip package that is mounted to a motherboard.
The die chip may be electrically connected to a package substrate by wirebonding. Wirebonding is a process known in the art by which a very fine wire is connected from a bond pad on the chip to corresponding signal pathways (“traces”) on the package substrate. Bond wires are typically formed of a highly conductive material, such as platinum or other precious metal. A package in which a die chip is connected to the substrate by wirebonding may be referred to as a “wirebond package.” The traces on the substrate extend from the location of bonding with the wirebond to signal interconnects elsewhere on the substrate. The signal interconnects on one layer of the substrate may be electrically connected to signal interconnects on another layer of the substrate using through-connections known as “vias.” Thus, for example, the signal connects on the face to which the chip is mounted may be connected to corresponding pins of a pin grid array (PGA) or to corresponding balls of a ball grid array (BGA) on the opposing face of the substrate. The PGA or BGA may then be placed in contact with a corresponding pattern of electrical contacts on the PCB to which the chip package is subsequently secured.
Signal traces are typically formed of commonly available materials, such as copper, that are relatively affordable and have sufficient electrical conductivity. Materials having improved electrical conductivity, including precious metals such as platinum and gold, are then selectively applied to the substrate at locations where the expense of such materials is warranted. For example, to facilitate wire bonding, platinum may be applied at locations along the signal traces where wire bonds are formed. Gold is often applied to signal interconnects. These materials are usually applied by electroplating. However, most electroplating processes result in open plating stubs extending from the signal interconnects. The electroplating voltage is applied at or near the periphery of the package substrate, which results in the plating stubs extending to or near the periphery of the substrate.
Plating stubs may hinder signal performance of the package if left intact. An open-ended plating stub can cause signal reflections. Signal performance is greatly impacted by reflections from these open stubs, particularly at higher frequencies wherein the wavelength of the signal is comparable to or less than the length of the plating stub. A quarter-wave length resonance is particularly detrimental in high speed data transmissions. One solution to avoid signal degradation caused by plating stubs is to remove the plating stubs by additional etching. However, such measures increase manufacturing costs and decrease product yield.