1. Field of the Invention
This invention relates to thin film semiconductor DRAM memories and more particularly to buried bit line DRAM memories.
2. Description of Related Art
Conventional manufacturing process provide DRAMs with poor bit line step coverage. Moreover, bit line contact is difficult to process because of poor step coverage or because of processing requirements such as required for using the buried N+ bit lines as described in (UMC2-93-010) M. T. Yang and G. Hong Ser. No. 08/100,707 filed Aug. 2, 1993 for an "MOSFET Device with Buried Bit Line", wherein a high energy implant or epitaxial process is required. For example, some ROMs use a buried bit line.
See U.S. Pat. No. 5,188,975 of Kojima et al for "method of Producing a Connection Hole for a DRAM Having at Least Three Conductor Layers in a Self Alignment Manner" which describes a stacked capacitor layout and process.