This application claims the priority benefit under 35 U.S.C. §119 of Japanese Patent Application No. 2003-322437, filed on Sep. 16, 2003, and Japanese Patent Application No. 2004-210876, filed on Jul. 20, 2004, which are hereby incorporated by reference.
1. Filed of the Invention
The present invention relates to a device made of gallium nitride compound semiconductors. In particular, the invention relates to a device having electrodes best suited to gallium nitride compound semiconductors, and a method (device process) of manufacturing the device.
2. Description of the Related Art
FIG. 1 shows a conventional gallium nitride compound semiconductor light-emitting device. This light-emitting device is shown with its electrode side downward since it is mounted on feeding electrodes (not-shown) in a flip chip fashion. This light-emitting device has an n-type gallium nitride compound semiconductor layer 92 (hereinafter, referred to as n-type GaN layer), an active layer 93, and a p-type gallium nitride compound semiconductor layer 94 (hereinafter, referred to as p-type GaN layer) which are formed on a sapphire substrate 91 in this order. The light-emitting device can emit a predetermined wavelength of light when an electric current is supplied to these layers through an electrode 95 for an n-type gallium nitride compound semiconductor (hereinafter, referred to as an n-type GaN electrode) and an electrode 96 for a p-type gallium nitride compound semiconductor (hereinafter, referred to as an p-type GaN electrode). While the substrate illustrated here is a sapphire substrate, it is not limited thereto. It is conventionally known that the substrate may be replaced with an SiC substrate or Si substrate. Thin films of gallium nitride compound semiconductors (AlxInyGa(1-x-y)N, 0≦x, y≦1) can be formed on this substrate by using conventionally-known techniques such as MOCVD (metal organic chemical vapor deposition).
In general, the n-type GaN electrode 95 is made of metal thin films such as Ti/Al and V/Al. The p-type GaN electrode 96 is often made of Pt, or metal thin films such as Ni/Au. As employed in this specification, the expression “A/B layer” shall hereinafter mean that the material A on the left lies closer to a semiconductor layer and the material B on the right lies farther from the semiconductor layer. To improve light output efficiency in the case of flip-chip mounting, there have been known techniques of making the n-type GaN electrode 95 out of an Rh/Al layer having high reflectivity so that the light emitted from the device is reflected at the sapphire-substrate side, and making the p-type GaN electrode 96 out of Rh/Al, Ag, and the like similarly. Incidentally, the reference numerals 97 and 97′ in the diagram represent eutectic electrodes.
Examples of these conventional gallium nitride compound semiconductor light-emitting devices and the methods of manufacturing the same include Japanese Unexamined Patent Application Publications Nos. Hei 5-211347, Hei 11-220168, 2003-110140, 2003-110138, Hei 5-291621, 2000-36619, and 2000-183400.
Japanese Unexamined Patent Application Publication No. Hei 5-211347 discloses an electrode having an Ni layer at the junction with an i layer of the gallium nitride compound semiconductor. Japanese Unexamined Patent Application Publication No. Hei 11-220168 discloses a gallium nitride compound semiconductor device of flip chip type in which a thin-film metal layer is interposed between a p-type layer and a thick-film reflective electrode layer. Japanese Unexamined Patent Application Publication No. 2003-110140 discloses a nitride semiconductor light-emitting device in which a predetermined area of an electrode is given high reflectivity for the sake of enhanced light output efficiency. Japanese Unexamined Patent Application Publication No. 2003-110138 discloses a nitride semiconductor light-emitting diode in which the sheet resistance and light transmittance of a transparent p electrode are balanced for improved external quantum efficiency. Japanese Unexamined Patent Application Publication No. Hei 5-291621 discloses the use of Au, Pt, Ag, and Ni as the material for making ohmic contact with a gallium nitride compound semiconductor doped with p-type impurities, and the use of Al, Cr, Ti and In as the material for making ohmic contact with a gallium nitride compound semiconductor doped with n-type impurities. Japanese Unexamined Patent Application Publication No. 2000-36619 discloses a gallium nitride compound semiconductor device of flip chip type in which Ag, Rh, Ru, Pt, or Pd is used to give a high reflectivity to a thick-film electrode layer to be connected with a p-type layer. Japanese Unexamined Patent Application Publication No. 2000-183400 also discloses a gallium nitride compound semiconductor device of flip chip type in which a thick-film electrode layer to be connected with a p-type layer is given a high reflectivity.
The conventional GaN electrodes mentioned above, however, have included no disclosure on the finding that annealing is not actively performed for the sake of ohmic contact with the semiconductor layer(s). In any of the above cases, establishing ohmic contact with a gallium nitride compound semiconductor requires annealing at or above 400° C. This causes several problems as follows:
(1) A first problem is evident in that surface contamination and oxidation are inevitable in the annealing furnace.
In typical GaN device processes, a wafer is annealed by either: the successive steps i) of forming n-type GaN electrodes->annealing->forming p-type GaN electrodes->annealing (alternatively, the p-type GaN electrodes and the n-type GaN electrodes are formed by steps of inverted order); or the successive steps ii) of forming n-type GaN electrodes->forming p-type GaN electrodes->annealing (alternatively, the p-type GaN electrodes and the n-type GaN electrodes are formed by steps of inverted order).
With the steps i), the n-type GaN electrodes are formed before annealing for establishing ohmic contact. At the time of annealing, the areas of the wafer surface for forming the p-type GaN electrodes are thus exposed directly to the furnace atmosphere. This inevitably contaminates the surface with impurities in the furnace and causes surface oxidation, so that the p-type GaN electrodes formed thereon become poor in electric characteristic. Even if the electrode-forming surface is cleaned to alleviate contamination and surface oxidation, the n-type GaN electrodes that are formed already preclude cleaning processes that can affect the material of the electrodes. This results in imperfect cleaning. In addition, the presence of the annealing even after the formation of the p-type GaN electrodes can give the n-type GaN electrodes an excessive heat history. The two annealing processes thus result in poorer electric characteristics. The same problems can also occur when the p-type GaN electrodes are formed first.
The steps ii) will not cause the same problems as those of steps i) since the annealing is conducted only once unlike in the steps i). It is required, however, that more severe temperature, atmosphere, time, and other annealing conditions for the n-type GaN electrodes or the p-type GaN electrodes be applied as the conditions of the annealing process after the electrode formation. Consequently, the other electrodes which would exhibit optimum ohmic characteristics at milder conditions are inevitably deteriorated in characteristic.
The n-type GaN electrodes and p-type GaN electrodes both can be evaporated and annealed at the same time if they were of the same material and the same conditions. Such a material, however, has not been adequately found so far.
For example, when the n-type GaN electrode 95 requires annealing at around 400° C. and the p-type GaN electrode 96 requires annealing at around 700° C., the p-type GaN electrode 96 must be formed first. The reason is that if the n-type GaN electrode 95 is formed first, it must undergo the 700° C. annealing in order for the p-type GaN electrode 96 formed later on the same wafer to acquire ohmic characteristics. This applies excessive heat to the n-type GaN electrode 95 resulting in deterioration in electric characteristics.
(2) A Second Problem lies in that the device process is limited.
The eutectic electrodes 97 and 97′ shown in FIG. 1 have a metal laminate structure such as a Ti/Au/(Pt/Au)n layer and an Ni/Au/(Pt/Au)n layer. The outermost surface layer of the eutectic electrodes 97, 97′ is an eutectic material layer of Au, under which an eutectic limitation layer of Pt is formed. For flip chip connection, these layers are put downward and connected with Au/Sn eutectic parts which are laminated on the side of a submount or wiring. At the time of connection, the Au layers at the outermost surface of the eutectic electrodes 97, 97′ and the Au layer at the outermost surface of the eutectic parts of the submount are put together, to which a heat of around 300° C. is applied to create an Au/Sn eutectic state for junction. Thus, if the n-type GaN electrode 95 described above is formed and then the film forming step is continued to form the eutectic electrodes 97 and 97′ before annealing is conducted at or above 400° C. for the sake of ohmic connection of the electrode metal, the eutectic metal can melt during the annealing to preclude the function of the electrodes 97 and 97′. Hence, both the electrodes 95 and 96 for n-type GaN and p-type GaN must be formed and annealed before the eutectic electrodes 97 and 97′, which are formed in a separate step. Incidentally, as employed in this specification, the expression “(A/B)n layer” shall mean that the material A and the material B are laminated n times repeatedly.
In general, when annealed at excessive temperatures, each of the n-type GaN electrodes and p-type GaN electrodes is coarsened at the surface of its metal layer on the semiconductor-layer side, with an unfavorable deterioration in reflectivity and ohmic characteristic. When Pt, Rh, Pd, and the like are used as a p-type GaN electrode for LED in particular, the heat treatment can increase the startup voltage (Vf) by 0.05 to 0.2 V. Needless annealing is thus better omitted.
As described above, the sequence of the device process depends on order of temperatures of the annealing processes on the wafer. In addition, the annealing temperature cannot be optimized. This inevitably causes the problems that the device process cannot be designed freely, and device characteristics cannot be optimized.