The present invention relates generally to semiconductor devices and more particularly to die seal structures and methods for protecting semiconductor devices from moisture.
Semiconductor devices, such as integrated circuits (ICs), are typically manufactured by forming multiple devices and interconnections (e.g., circuits) on a semiconductor wafer, which are then separated into individual parts or dies. Individual devices are located within corresponding die areas on the wafer with sufficient spacing provided between adjacent devices for subsequent separation operations and the manufacturing tolerances associated therewith. Typically, the devices are oriented in grid style on the wafer, with rows and columns of devices located on the top or front side of the wafer. The devices are formed using multi-step processing involving selective deposition, removal, and/or doping of active regions on the wafer surface to build electrical components (e.g., memory cells, transistors, diodes, resistors, capacitors, etc.) and connections therebetween. Within a particular die area, many electrical components are thus formed, and are interconnected with one another using one or more overlying metal layers, by which an integrated circuit device is produced. Thereafter, the individual dies or devices are separated from the wafer.
Following die separation, individual dies may then be assembled into integrated circuit chips. In constructing an integrated circuit chip, a semiconductor die is mounted onto a lead frame and wires are connected between lead frame leads and corresponding bonding pads on the die using a technique known as wire bonding. Wire bonding involves attachment of fine aluminum or gold wires to the die bonding pads through various bonding techniques, such as thermocompression bonding or ultrasonic bonding. Once the pads on the die are appropriately connected to the lead frame leads, the lead frame is encapsulated in a ceramic or plastic package, which may then be assembled onto a printer circuit board (PCB) by soldering the exposed portions of the leads onto corresponding conductive pads on the board. Alternatively, the dies may be mounted directly onto PCBs, where electrical connections are made between conductive circuit board pads and electrically conductive bonding pads on the dies. In this regard, Flip-Chip technology has recently become popular, wherein an individual semiconductor die is mounted directly to a circuit board. Bumps (e.g., solder bumps, plated bumps, gold stud bumps, adhesive bumps, or the like) are added to the bonding pads of the die using a process known as bumping. With stud bumps attached, the die or chip is then xe2x80x9cflippedxe2x80x9d over, with the bonding pads facing downward, and the bumps are attached to corresponding pads on the PCB using, for example, ultrasonic or other bonding techniques.
Moisture is known to cause adverse effects in the operational reliability and/or longevity of semiconductor devices. For example, where the electrical components within an active region of a semiconductor die are exposed to moisture, the characteristics of the transistors, memory cells, or the like may be affected. Thus, in a flash memory device, for instance, internal exposure to such moisture may change the programmed and/or erased threshold voltages associated with one or more memory cell structures therein, resulting in reduced reliability for storing or providing access to user data. During semiconductor device fabrication, as well as during subsequent bonding, packaging, and eventual operation of the device die (e.g., mounted in an integrated circuit package or directly on a circuit board), the exterior of the die may be exposed to a moist ambient operating environment. Where such moisture invades the electrical component areas of the device, operational degradation may result. It is therefore desirable to prevent or reduce the likelihood of such moisture entering the interior active regions of the device die, both during manufacturing and thereafter.
Various attempts have previously been made to seal the interior of the semiconductor device dies from such ambient moisture. The bottom substrate in most semiconductor devices (e.g., silicon) effectively blocks moisture from entering the interior of the die from the bottom, but materials commonly employed in fabricating further layers above the substrate provide a path for moisture to enter from the top and/or sides of the die following die separation. For example, certain commonly employed insulator materials such as silicon oxide (SiO) are relatively easily penetrated by moisture. Accordingly, lateral or side seal structures are often provided between the die edges and the active region. Such side seal structures are formed in one or more layers in the processed semiconductor device using vertically oriented contacts (e.g., such as tungsten) and metal die seal structures, wherein the contacts and die seal metal structures extend around the periphery of the active region of each individual die.
Each layer formed between the bottom substrate and the upper most metal layer typically includes such a structure, by which a vertical moisture barrier extends laterally around the periphery of the device active region from the bottom substrate to the upper most metal layer. Thus, where multiple metal connection layers are employed in a device fabrication process, the lower most die seal contacts extend from the substrate to a metal die seal structure in the first metal layer. Additional contacts are formed in an overlying insulator material, which extend upward from the metal die seal structure in the first metal layer to a similar seal structure in the second metal layer. This structure is then repeated for each successive metal layer until the final metal layer is formed.
In the past, moisture has been prevented from entering the die active region by an upper seal or liner layer directly overlying the upper most metal layer. A final insulator layer, such as SiO is then formed over the liner. Openings are made (e.g., etched) in the liner and final insulator layers so as to expose die bonding pads in the upper most metal layer for wire bonding after die separation. Thus, in the interior of the active region, the liner layer and the exposed metal bonding pads provide a seal against moisture entering from the top of the die. Furthermore, because the liner layer is formed directly over the final metal layer, a moisture seal is provided at the peripheral edges of the active region, where the liner layer is formed directly over the metal die seal structure in the top metal layer. Thus, although moisture may pass from the top ambient through the upper most SiO insulator layer, the liner layer prevents further downward moisture transfer to the electrical components below.
However, the use of such a liner overlying the upper metal layer may cause problems in the operation of the circuitry in the semiconductor device. For instance, in order to satisfy the demand for more and more functionality in modern semiconductor products, there is a continuing trend toward higher device densities. Such higher device densities, in turn, are facilitated by reduction in the device dimensions achieved through smaller and smaller features sizes. These feature sizes include the width and spacing of interconnecting lines in the various metal layers, which have recently become smaller to the point where electrical characteristics of the liner layer overlying the upper most metal layer features may have an adverse effect on the device performance. Thus, there is a need for improved moisture sealing structures and methodologies by which the semiconductor device and the components therein can be protected from moisture, without adversely affecting the circuit operation.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention, and is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, the primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The invention provides moisture seal apparatus and methodologies for protecting semiconductor devices from moisture, by which the above mentioned and other shortcomings associated with prior techniques may be mitigated or overcome.
One aspect of the invention provides semiconductor devices and moisture seal structures therefor in which an upper seal layer, such as silicon nitride (SiN) or an equivalent sealing material, is formed over an upper insulator layer and an exposed portion of a die seal metal structure so as to form a vertical moisture seal between electrical components in the semiconductor device and the ambient environment. A lateral moisture seal may be formed from the die seal metal structure in an upper metal layer in the device and one or more contacts extending downward from the die seal metal to the substrate or to a lower die seal metal structure. Together with the underlying bottom substrate, a moisture seal is thus provided to protect the internal active die region and the electrical components therein from the adverse effects of moisture.
In addition to providing a moisture seal, the invention may advantageously mitigate adverse effects of the electrical properties of the upper seal layer on the device operation. For example, the inventors have found that as line spacings in the upper metal layer are decreased to provide interconnection in high feature density devices, the dielectric properties of a liner layer directly formed on the upper metal layer may cause capacitive problems in circuit operation, where the liner material formed between adjacent signal line connection features creates a capacitor therebetween. In this regard, the inventors have found that the present invention advantageously allows silicon oxide (SiO) or other insulator layers to be formed directly above the upper most metal layer features, by which a reduction in such undesirable capacitive effects of the seal layer may be achieved.
Another aspect of the invention provides techniques for protecting a semiconductor device against moisture, comprising forming a seal structure in a final metal layer in the semiconductor device and forming an upper insulator layer overlying the final metal layer. The upper insulator layer may be formed, for example, using SiO, which has limited adverse capacitive effects on adjacent signal lines in the upper metal layer. A portion of the seal structure is exposed through the upper insulator layer, and an upper seal layer is then formed, which overlies the upper insulator layer and an exposed portion of the seal structure. By this technique, the effects of the electrical characteristics (e.g., such as dielectric properties) of the seal layer on the circuitry in the device may be mitigated.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.