1. Field of the Invention
The present invention generally relates to a digital phase-locked loop ("PLL") circuit, and more particularly, is directed to a digital PLL circuit for use in a carrier recovery system such as an M-ary phase shift keyed ("PSK") or quadrature amplitude modulated ("QAM") data communication system.
2. Description of the Prior Art
Much research on huge capacity digital data communication systems, e.g. video information transmission systems, has been recently developed and some systems have been marketed. In such digital data communication systems, M-ary PSK and QAM are used. These modulated systems use a digital PLL for obtaining a stable carrier recovered from the modulated data.
A conventional digital PLL circuit for processing complex number signals for such a purpose has been proposed, as shown in FIGS. 4 and 5.
FIG. 4A shows a block diagram of a conventional digital PLL circuit. Input terminals 20, 21 of a complex multiplier 22 accept a pair of complex in-phase (I) and quadrature (Q) data respectively which are converted into digital form.
The multiplier 22 also receives a sinusoidal signal ("Sin") and a cosinusoidal signal ("Cos"), both of which are provided from a data converter 26, and produces corresponding multiplication result signals: Icos.omega.-Qsin.omega. and Icos.omega.+Qsin.omega..
The phase comparator 23 receives the multiplication result signals and calculates the tangent characteristic based on the real and imaginary parts of the supplied multiplication inputs, and detects the phase .theta..sub.D in using the arctangent characteristic, which is derived from the aforementioned tangent characteristic, according to the following formula: EQU .theta..sub.D =arctan(Q/I)=tan.sup.-1 (Q/I) (i)
The phase comparator 23 determines the phase deviation .DELTA..theta. of the detected phase .theta..sub.D from a preselected phase .theta..sub.R, and outputs a phase deviation signal in proportion to the phase deviation. The phase deviation signal is fed to a PLL loop filter 24.
This phase deviation signal is also fed to a demodulation circuit (not shown in FIG. 4A) for use in data demodulation.
The phase deviation signal becomes a control variable for a numerical controlled oscillator 25 after passing through the PLL loop filter 24.
The output of the numerical controlled oscillator 25, a phase signal whose frequency is controlled by the control variable, is fed to a data converter 26.
The data converter 26 bifurcates the phase signal by converting it into the sinusoidal and cosinusoidal signals which are fed to the multiplier 22.
The above-mentioned completely digitalized loop circuit, which is comprised of the complex multiplier 22, phase comparator 23, PLL loop filter 24, numerical controlled oscillator 25 and data converter 26, can accomplish frequency acquisition and phase synchronizing.
FIG. 4B shows the phase comparison characteristic of the phase comparator 23. It is a sawtooth characteristic, i.e. a triangle wave detected by an arctangent characteristic (see formula (i)). In the process of frequency acquisition, according to the above phase comparison characteristic, the phase deviation signal from the phase comparator 23 should be a sampling signal, as shown in FIG. 5A, which can be acquired by sampling a sawtooth wave. Put another way, the phase deviation signal is a sampling sawtooth signal whose sampling frequency and frequency offset are f.sub.S and .DELTA.f, respectively. A sawtooth signal inherently possesses higher harmonics components. Therefore, the phase deviation signal has aliases caused by the higher harmonics, as shown in broken lines in FIG. 5B. Frequency acquisition can be accomplished by using the DC component, which represents the phase deviation .DELTA..theta., of the output of the loop filter 24. However, aliases caused by the higher harmonics cancel the useful DC component. As a result, the digital PLL circuit is not able to accomplish frequency acquisition and locks onto an incorrect frequency. This phenomenon is called "false lock."
Therefore, if the conventional PLL circuit shown in FIG. 4A has a sawtooth phase comparison characteristic, it cannot accomplish phase synchronization via frequency acquisition because of the occurrence of false lock in the course of frequency acquisition.
Conventional digital PLL circuits, such as that described above having the sawtooth phase comparison characteristic of the phase comparator, have been restricted in their range of frequency acquisition because of the presence of the aliases caused by the higher harmonics.