1. Field of the invention
The present invention relates to a semiconductor memory device, and particularly to a memory cell structure and the method of making the same which increases the electric capacity of a capacitor in a dynamic type semiconductor memory device performing storage of information by storing charges in the capacitor.
2. Description of the Prior Art
FIG. 1 illustrates a cross sectional structure of a conventional memory cell composed of one transistor/one capacitor. In FIG. 1, the memory cell comprises a memory capacitor 7 for storing charges and a transfer gate 8 for electrically connecting the capacitor 7 to a bit line.
The memory capacitor 7 comprises a semiconductor substrate 1, an extremely thin gate dielectric film 3a formed on the substrate 1, and a memory cell plate 4 formed on the dielectric film 3a. A voltage from a power supply V.sub.CP is applied to the memory cell plate 4 which becomes one electrode of the capacitor 7. The other electrode of the capacitor 7 is composed of the semiconductor substrate 1 (more specifically, an inversion layer formed by the cell plate 4).
The transfer gate 8 is formed of n.sup.+ diffused regions 6a formed on the surface of the semiconductor substrate 1 and a gate electrode (word line) 5 formed on a charge transfer region between the n.sup.+ diffused regions 6a with an extremely thin oxide film 3b interposed therebetween. One of the n.sup.+ diffused regions 6a is connected to a bit line BL for reading/writing of signals. A cell isolation region 2 of thick dielectric film composed of, e.g. SiO.sub.2, is formed on one end of the memory cell thereby electrically insulating the memory cell from an adjacent memory cell. The operation of the aforementioned memory cell will be hereinafter described with reference to FIG. 1.
The electric capacity C of the capacitor 7 is given by the following equation EQU C=.epsilon. S/t
where .epsilon. denotes the dielectric constant of the gate dielectric film 3a, t denotes the film thickness thereof and S denotes the area of the memory capacitor 7. When the voltage V from the power supply V.sub.CP is applied to the capacitor 7 having the capacitance value of C, the quantity of electricity Q stored in the memory capacitor 7 becomes EQU Q=C.multidot.V
The information is stored responsive to the presence or absence of the quantity of electric charge.
Reading of the information out of the memory cell is performed by applying a "H" signal to the word line WL to turn the transfer gate 8 on-state. On this occasion, the quantity of electricity Q of the capacitor 7 is transferred to the bit line BL through the transfer gate 8. When the quantity of electricity Q is transferred on the bit line BL, the presence or absence of the quantity of electricity Q is detected by a sense amplifier (not shown) connected to the bit line BL. Accordingly, the reading of the stored information is performed.
Since a conventional one transistor/one capacitor type memory cell is formed as described above, the electric capacity C of the capacitor portion must be increased in order to increase the quantity of electricity Q which can be stored in the capacitor portion. Thinning the film thickness of the gate dielectric film 3a is proposed as a method for increasing the electric capacity C, and a silicon oxide film of about 100 .ANG. has become utilized. However a gate dielectric film with thinner film thickness lacts reliability because the number of defects such as pinholes increases, the yield thereof decreases and, in addition, the electric field strength applied to the gate dielectric film 3a extremely increases to cause a dielectric breakdown.
The electric capacity C can be increased by enlarging the area S of the capacitor. However, if the area S of the capacitor is enlarged, the occupation area of a memory cell will be increased, resulting in a big obstacle in implementation of a highly integrated memory device with a large memory capacity.
FIGS. 2A and 2B illustrate a memory cell structure (a Trench Capacitor Cell) for eliminating the above described problems in which not the occupation area of a memory cell is increased but the area of the capacitor only is increased; FIGS. 2A and 2B show the cross sectional structure and the planar layout thereof, respectively. As may be seen from FIGS. 2A and 2B, the trench capacitor cell comprises a narrow and deep trench 9 formed at the central portion of the capacitor, a thin dielectric film 3a and a memory cell plate 4 being formed in the trench 9 to form a capacitor at the inner side wall of the trench 9, whereby the effective area of the capacitor is enlarged to increase the electric capacity C.
However, in a recent semiconductor memory device with large memory capacity, since a memory cell size is minimized and the planar area occupied by the capacitor is limited, the area of the opening of the trench capacitor 9 is only about 1 to 2 .mu.m.sup.2. Therefore, the depth of the trench capacitor 9 need be more than 4 .mu.m in order to obtain the required electric capacity for the storing operation. To form such a deep trench by etching, then to form an extremely thin gate dielectric film 3a of about 100 .ANG. and a memory cell plate 4 of polycrystalline silicon in the deep trench, and in addition, to level the surface of the capacitor portion by filling insulators in the trench is extremely difficult in the manufacturing technique resulting in a serious problem with regard to the yield.
In addition, as may be seen from the cross sectional structure shown in FIG. 2A, since trenches 9 deeper than the cell isolating region 2 are formed adjacently, the effect of isolation of the cell isolation region 2 does not work, causing a leak current flowing through the adjacent trench capacitors to erase the stored information, which is a fatal defect in a memory device.
The above described planar type capacitor and a DRAM memory cell structures having trench type capacitors are disclosed in "Cell Structure for Future DRAM'S", H. Sunami, Technical Digest of IEDM 1985, pp. 694 to 697.