1. Cross-Reference to Related Patent Applications
This patent application is related to U.S. patent application entitled "Asymmetrical Resist Sidewall", and U.S. patent application entitled "Selective Reduction of Sidewall Slope on Isolation Edge", both filed on the same day as the instant patent application and presently assigned to the assignee of the instant application and the disclosure of which is incorporated herein by reference.
2. Field of the Invention
This invention relates to asymmetric field effect transistors (FETs) having a lightly doped drain.
3. Description of Related Art
In electronic component manufacture and in particular integrated circuit silicon wafer manufacturing, the key factor in delineating small patterns in the wafer is the shape of the resist pattern. The following description will be directed to integrated circuit silicon wafer manufacture and silicon devices but it will be appreciated by those skilled in the art that the invention may be applied to the manufacture of other electronic components such as gallium arsenide circuits, component packages and printed circuit boards.
In the manufacture of integrated circuit components such as semiconductors, electronic circuit pattern control, e.g., linewidth control is becoming increasingly important because of even higher integration of the circuits and the linewidth and other circuit patterns are required to be increasingly fine and precise. Pattern control in photolithographic processes, however, is negatively impacted by numerous effects ranging from resist thickness variations, bake non-uniformities, non-flat wafers, etc.
Photolithography techniques are preferably used to form the fine resist pattern to define the circuit and, in general, a wafer, on which a resist having a predetermined thickness is applied, is positioned on a wafer stage and light from a light source passes through a photo mask having a predetermined mask (circuit) pattern thereon. The light passing through the photo mask is projected onto the resist on the wafer forming the mask pattern on the resist. The resists are typically negative resists or positive resists. The exposed resist is then processed using a number of cleaning, developing and etching steps to form a pattern on the wafer either in the form of openings in the resist which are to be metallized to form the desired circuit pattern (negative resist) or in the form of a positive resist pattern delineating the desired pattern on the wafer surface to be metallized. The above photolithographic process is shown in U.S. Pat. No. 5,300,786 which is assigned to the assignee of the present invention.
In either of the negative or positive resist methods or combination resist methods (e.g., image reversal resists), it is necessary that a photo mask be used to form the pattern on the resist and, traditionally, the imaging process using optical lithography creates a plurality of resist patterns which are each, in cross-section, of substantially constant width, height and symmetry. Under some exposure conditions, the width of the resist pattern may vary somewhat with the height of the resist with the width at the base being slightly wider than the width at the top of the resist. In any event, the resist pattern is still symmetrical and a metallized circuit line would be of essentially constant cross-section measured about a vertical axis extending upward from the midpoint of the base of the resist pattern.
There are many different integrated circuit manufacturing processes that require an asymmetric resist pattern as part of the process to provide desired circuit designs, and one application, for example, is to produce a pattern for lift off processes. These methods are well known in the art.
A number of attempts have been made to create an asymmetrical resist (photoresist) profile or pattern. In U.S. Pat. No. 5,547,789 to Nakatani et al. an asymmetrical light intensity profile is used to pattern a positive resist, which resist is then converted by flood illumination into a negative resist (image reversal resist) in order to affect the placement of subsequently formed gate electrodes. The purpose of the asymmetry of the resist pattern is to create an asymmetrical placement of the gate electrode. The asymmetrical intensity profile is achieved by a pattern transfer mask comprised of a transfer substrate, a linear light shielding film pattern disposed on the transparent substrate, and a means for reducing the intensity of light transmitted through a part of the mask on either side of the light shielding film pattern. The pattern transfer mask comprises a transparent substrate having different kinds of light attenuating films placed on the transparent substrate next to the light shielding pattern such as an opaque material, a light shielding film with different thicknesses or a semi-transparent film. The resist profiles shown are strongly re-entrant on both sides of the pattern which is not acceptable for many manufacturing methods.
Another patent which shows an asymmetrical light intensity profile is U.S. Pat. No. 5,370,975 to Nakatani wherein the mask designed to create the asymmetrical light profile employs a phase shifter with an edge angle ranging from 70.degree.-85.degree. or 95.degree.-110.degree. or the phase shifter is shaped to be smoothly curved. In U.S. Pat. No. 5,300,786, supra, there is a description of a phase shift mask which can shift the intensity profile of the light for the purpose of determining and controlling the focus settings of an optical lithography exposure system. When there is a change in focus, the minimum point of the intensity profile is shifted to create an asymmetrical displacement of the photoresist pattern to the left or right direction. The intensity profile is asymmetric about the minimum intensity peak point and it is the asymmetric peak shift which creates a pattern placement error which is used in conjunction with other reference patterns to measure the focus as an overlay by an automated overlay error measurement tool.
In U.S. Pat. No. 5,368,962 to Hanyu et al. a photo mask is shown comprising a light shielding layer formed on a mask substrate and light transmission areas defined on the mask substrate by the light shielding areas. The light transmitting areas are divided with phase shifters. The above patents are hereby incorporated by reference.
An example of a symmetric FET with lightly doped drain and source regions, and a method for making such an FET is described in U.S. Pat. No. 5,518,945.
In the IBM Technical Disclosure Bulletin article "Method for making a self-aligned, reverse-T gate LDD MOSFET", Vol. 32, No. 3B, August 1989, another example of a symmetric FET is given. The FET described therein has a reverse-T type structure.
Other examples of LDD structures or methods for making the same are addressed in IBM Technical Disclosure Bulletin article "Process for fabricating lightly doped drain MOS devices with punch-through stoppers", Vol. 27, No. 11, April 1985, IBM Technical Disclosure Bulletin article "Integrated Schottky diode in CMOS", Vol. 28, No. 12, May 1986, IBM Technical Disclosure Bulletin article "LDD Sidewall Spacers without reactive ion etch", Vol. 27, No. 7B, December 1984.
It is an object of the present invention to provide a new FET structure with improved reliability and performance.
It is another object to provide a new FET structure which can be easily made.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.