The synthesis of register transfer level (RTL) based design is a process of translating hardware descriptive language (HDL) coded design to logic gates based on library technology provided and given timing constraints. In order for a design to be synthesized to the logic gates, timing constraints may be imposed onto the input and output pins. Based on the timing constraints of the input and output pins, the logic gates may be established based on the HDL-coded design to meet these timing constraints. This achieves the required speed of operation and logic functionality using the logic gate library technology provided.
An RTL based design may be register retimed during synthesis in order to meet timing constraints, and as a result, additional circuitry like flip flops may be added to a design that are unnecessary for certain functional modes of the design. Meanwhile, current designs are increasingly complex with demands to incorporate more functionality with smaller areas and lower power consumption. However, conventional approaches of synthesizing designs are limited when attempting to achieve a required speed of operation and logic functionality while lowering power consumption of integrated circuit innovations.