Read only memories (ROMs) typically serve as a nonvolatile source of data storage. Volatile memory devices, such as dynamic random access memories (DRAMs) and static random access memories (SRAMs) can store data, but once power is removed from such devices, the data is lost. In contrast, nonvolatile memory devices, such as ROMs, electrically programmable ROMs (EPROMs), and electrically erasable and programmable ROMs (EEPROMs) retain data in the absence of power. Many volatile memory devices sense the logic stored within a memory cell by detecting a change in voltage. For example, in the case of DRAMs, a charge is placed on a bit line to create a difference in voltage between the bit line and a reference voltage. In the case of SRAMs, an SRAM cell often includes circuitry for pulling a bit line to a higher or lower potential. In contrast, many nonvolatile memory devices sense memory cell stored logic by detecting current values. In the case of many EPROMs and EEPROMs, a programmed memory cell (typically logic "0") will draw negligible current, while an erased memory cell (typically logic "1") will draw a relatively large amount of current.
Nonvolatile memory devices commonly include an architecture in which memory addresses are applied to access a particular set of data. As in the case of most every other memory device, an important aspect to consider in the selection of such devices is the speed at which data can be read. Data is typically stored within thousands or millions of memory cells packed within a single device. Because of this, the data signal provided by an individual memory cell is typically a very small voltage or current signal. Because of this, a nonvolatile memory device includes sense amplifier circuits, for sensing the logic value of the memory cell signal, and amplifying the signal.
As noted above, in the case of EPROMs and EEPROMs, the memory cell signal is often a current signal. This arises out of the fact that many EPROMs and EEPROMs employ memory cells having floating gates that are used to alter the threshold voltage of an insulated gate field effect transistor structure. If the memory cell is programmed, the floating gate is charged, and when its respective transistor is accessed, the threshold voltage of the cell will be higher than the applied control gate voltage, that the cell will draw no (or negligible) current, establishing a logic "0." If the memory cell is not programmed (or in the case of an EEPROM, erased), the cell will draw current when accessed, thereby establishing a logic "1".
In addition to speed, another important concern in the design and manufacture of nonvolatile memory devices is that of yield and reliability. Yield refers to the number of functional devices that are produced at a given point in a manufacturing process. Because semiconductor memory devices are fabricated on silicon wafers as a number of individual die, yield is often referred to as the number of "good" die per wafer. It is noted however, the yield can also refer to "back-end" portions of the manufacturing process in which individual dies are placed in packages and subjected to other process steps, such as "burn-in." Reliability refers to the ability of the memory device to operate without failing over time. Therefore, although a device may appear fully functional, over time the device may fail.
Yield is important in the fabrication of semiconductor devices, as the process used in manufacturing nonvolatile devices, such as EPROMs and EEPROMs, can include manufacturing steps (for example those steps required to fabricate the memory cell) above and beyond those of conventional logic devices. Thus, there may be a greater chance that defects will be introduced during these process steps.
Reliability of EPROMs and EEPROMs is important, because nonvolatile memory devices are typically used to store important system information. In the event the EPROM or EEPROM is defective, incorrect data will be output by the nonvolatile memory device, resulting in erroneous performance of a system. As one example, EPROMs, and increasingly, EEPROMs are used to store the basic input-output system (BIOS) in personal computer systems. In the event this information is corrupted, the personal computer can malfunction. As another example, EEPROMs are also being employed as elements in mass storage elements devices, such as "solid state" disks. In the event an EEPROM within such a device fails, data errors will occur. There are reliability issues particular to EEPROMs, as well. The performance of EEPROM memory cells may degrade each time the memory cell is cycled through a program and erase operation. The reliability of an EPROM or EEPROM is thus often referred to in terms of "cycles."
Because many EPROMs and EEPROMs include sense amplifiers which sense current signals, defects resulting in the excess drawing of current can be a particularly problematic yield and/or reliability issue. Referring now to FIG. 1a, a schematic diagrams is set forth illustrating the sense operation of a defect free EPROM or EEPROM. FIG. 1b illustrates the sense operation of an EPROM or EEPROM that includes a current drawing defect.
Referring now to FIG. 1a, a portion of an EEPROM memory array 100 is set forth in a schematic diagram. Two memory cells of the array 100 are shown as Q100 and Q102. The memory cells (Q100 and Q102) each include a source, drain, floating gate, and control gate. The sources of the memory cells (Q100 and Q102) are commonly coupled to a low power supply, VSS, and the drains are commonly coupled to a bit line 102. The gates of the memory cells (Q100 and Q102) are coupled to different word lines, 104 and 106. The bit line 102 is coupled as one input to a current sense amplifier 108 by column select transistor N100. Transistor N100 is activated by a COLDEC signal applied to its gate. The other input to the sense amplifier 108 is a reference current, shown as Iref.
In the particular example of FIG. 1a, it is assumed that word line 104 is activated, and the word line 106 is de-activated. In addition, the column decode signal COLDEC is high, turning on transistor N100. As a result, data is read from memory cell Q100, and a current Isense, will be drawn through memory cell Q100. In the event memory cell Q100 is programmed (i.e., its floating gate is charged with negative charge), its threshold voltage will be high, and the Isense current will be negligible. Because word line 106 is de-activated, memory cell Q102 will be off, and also draw only a negligible current. The reference current Iref is designed to be greater than the sum of all such negligible currents, but less than the magnitude of the current drawn by an erase cell. Thus, because the Isense current is less than the Iref current, the output (SAOUT) of the current sense amplifier 108 will be low. In contrast, in the event memory cell Q100 is erased, when word line 104 is activated, Isense will be substantially higher than the Iref current, and SAOUT will be high.
FIG. 1b illustrates the same general EEPROM configuration as FIG. 1a, but differs from the previously described case, in that memory cell Q102 includes a defect. The defect results in current being drawn through the memory cell Q102, despite the fact that the memory cell is turned off. Thus, when word line 104 is activated, and transistor N100 is turned on, in addition to the current Isense being drawn by memory cell Q100, a defect induced leakage current (Ileak) will be drawn through memory cell Q102. Thus, the total current drawn on the bit line 102 will be Isense+Ileak.
In the event memory cell Q100 is programmed, Isense will be negligible, as in the case of FIG. 1a. However, the Ileak current will continue to be drawn. This can result in a slower sensing speed, as the current sense amplifier 108 may take longer to sense the smaller differential current produced by the difference between Iref and Ileak. Further, in the event the Ileak is greater than Iref, the sense amplifier 108 will output an erroneous high SAOUT signal.
Referring now to FIGS. 2a-2d, a series of side cross sectional views of memory cells is set forth to further illustrate current induced defects in an EEPROM. Each of the side cross sectional views of FIGS. 2a-2d sets forth a stacked gate "one-transistor" EEPROM cell, and so includes the same general structures. The memory cells are formed on a substrate 200, which includes a source 202, a drain 204, and a channel 206. A floating gate 208 is disposed above the channel 206, and a control gate 210 is disposed above the floating gate 208. A bit line 212 is shown coupled to the drain 204.
FIG. 2a illustrates a programmed memory cell that is accessed during a read operation. Negative charge is stored within the floating gate 208, resulting in a higher threshold voltage in the memory cell. Thus, when a positive potential is applied to the control gate 210, the potential will not be sufficient to invert the channel 206, and thereby create a conductive channel between the source 202 and drain 204. Consequently, only a negligible source-drain current (Isense) will be drawn through the bit line 212.
FIG. 2b illustrates an erased memory cell that is accessed during a read operation. The charge on the floating gate 208 results in the memory cell having a threshold voltage that is less than the positive potential applied to the control gate 210. The channel 206 inverts, and a conductive channel is formed between the source 202 and drain 204. Consequently, a relatively high source-drain current (Isense) will be drawn through the bit line 212.
FIG. 2c illustrates a defective memory cell that is not accessed during a read operation, but nevertheless draws current through the bit line 212. In the case of FIG. 2c, the floating gate 208 has accumulated a positive charge that results in the memory device functioning as a depletion mode device (i.e., a "depleted" bit). Despite the fact that the control gate 210 is maintained at a de-select voltage (zero volts as one example), the positive charge in the floating gate induces a conductive channel between the source 202 and drain 204. Consequently, a defect induced leakage current (Ileak) is drawn through bit line 212. Depleted bits can be cycling induced defects. That is, the positive charge may slowly accumulated over repeated cycling of the memory cell. In addition, depleted bits can be created by "over-erase." Over-erase occurs when an erase cycle removes too much negative charge from a floating gate, and the resulting floating gate has a relatively positive charge.
FIG. 2d illustrates a second example of a defective memory cell that is not accessed during a read operation. In the case of FIG. 2d, a process-induced defect has resulted in drain-substrate short condition. Thus, as in the case of FIG. 2c, a defect induced leakage current Ileak is drawn through bit line 212. In addition to drain-substrate shorts, other possible leakage paths include drain to source shorts (pipeline defects) and isolation leakage.
Depleted bits can be restored by a variety of processes that are referred to as "compaction," "healing," or "convergence." Such processes can inject additional electrons into the floating gate to reduce the positive charge thereon. A drawback to such approaches is that they can consume considerable time and/or require additional circuitry. Of course, compaction procedures, and variations thereof, are not effective in addressing bits having short-circuit like conditions, such as that set forth in FIG. 2d.
It would be desirable to provide an EPROM or EEPROM that can address the adverse effects of resulting from memory cells that introduce leakage current when data is being sensed in the memory cells.