The invention relates to producing smoothed clock and data signals from gapped clock and data signals.
In many modern communication systems, timing information, in the form of clock signals, plays a critical role in system performance. In these applications, the clock signals are used to drive circuitry such as mixers and sampling circuits for which consistency in the sampling instant is an important performance parameter. Minimizing timing errors requires minimizing the noise introduced during the distribution and buffering of clock signals in the system.
Some communication devices, such as cable modems, derive clock signals from timestamps embedded in data streams. In addition to timestamps, these data streams usually include error correction and synchronization information to ensure integrity and synchronization. In processing the data stream, the cable modem removes the error correction and synchronization bits, leaving a reference clock that is gapped or jittered where the error correction and other information were located. In general, these communication systems must smooth the reference clock for accurate data recovery.
Many systems use phase-locked loops (PLLs), or other similar circuits, to smooth the reference clock and the incoming data signal. A PLL uses a voltage-controlled oscillator (VCO) to produce an output frequency that is proportional to the voltage at the PLL output. As a result, PLLs require signal feedback and filtering. A PLL also requires careful attention to all sources of noise in the system and overall interaction of system components to minimize timing errors. Therefore, attaining high performance levels with PLLs may contribute considerable expense and complexity to the systems in which PLLs are used.
Direct digital synthesizers (DDSs) also are used to produce clock signals by accumulating phase changes at one clock frequency to generate highly accurate waveforms at a lower frequency. The DDS allows high resolution frequency and phase control, producing frequency steps on the order of mHz and phase increments on the order of nHz. To produce a particular frequency, an associated phase increment value is loaded into an input frequency register. The generated frequency and the DDS reference frequency are related to the phase increment value by the following equation:
Fgen=N/2kxc2x7Fref
k=number of bits in phase accumulator
N=phase increment value
A desired frequency is generated by programming the phase change within the bit resolution of the phase accumulator. However, a conventional k-bit DDS has a resolution limited by the number of bits, k. Furthermore, sampling theory limits the generated frequency to no more than one-half the frequency of the incoming reference clock (the Nyquist rate).
The inventors have developed a clock and data smoothing technique that allows generation of a clock of virtually any frequency up to the frequency of a reference clock. This technique is capable of generating exact frequencies and thus does not require approximations that normally involve the monitoring of feedback. Elimination of feedback obviates the need for a PLL circuit in many cases. This, in turn, allows the use of lower cost materials and fewer gate elements than are required for standard DDS clocks. This clock and data smoothing technique provides fully deterministic and pre-calculated phase errors of a given ratio N/M.
In addition, this technique produces a smooth clock up to the reference frequency, with a timing jitter less than the period of the reference clock. This technique also eliminates the need to maintain jitter statistics, acquisition times, and bandwidth for statistical performance analysis.
In one aspect, the invention involves the generation of a smoothed clock signal from a gapped clock signal having unevenly spaced pulses separated by gaps that result from the removal of data bits and from a reference clock signal having evenly spaced pulses that create a predetermined reference frequency. The smoothed clock signal includes one pulse for each of the pulses in the gapped clock signal and has a frequency that is greater than one-half of the predetermined reference frequency. Each pulse in the smoothed clock signal is synchronized with a pulse in the reference clock signal.
In some embodiments, the smoothed clock signal has a frequency equal to (Mxe2x88x92N)/M of the predetermined reference frequency, where M represents the total number of pulses of the reference clock signal during a period of predetermined length, and where N equals the total number of these pulses that coincide with the gaps in the gapped clock signal. In other embodiments, an accumulator counts the pulses of the reference clock signal, and a modulo element resets the accumulator to a particular reset value when a predetermined number of pulses is reached. An output element produces one pulse of the smoothed clock signal for each pulse of the reference clock signal on which the modulo element does not reset the accumulator.
In another aspect of the invention, the smoothed clock signal is generated from the gapped clock signal and the reference clock signal by using an accumulator to count the pulses of the reference clock signal and by resetting the accumulator to a particular reset value when a predetermined number of pulses M is reached. One pulse of the smoothed clock signal is produced for each pulse of the reference clock signal on which the accumulator is not reset.
In some embodiments, the particular reset value equals a number of counted pulses minus the predetermined number. In other embodiments, resetting the accumulator involves comparing a number of counted pulses to the predetermined number N and asserting a modulo signal when the number of counted pulses reaches the predetermined number M. An output element produces a pulse of the smoothed clock signal at each pulse of the reference clock signal when enabled. The output element is disabled when the modulo signal is asserted. In other embodiments, the accumulator increments by a predetermined number N at each pulse of the reference clock signal, such that N/M equals a proportion of the gapped clock signal that is consumed by the gaps.
In another aspect, the invention features a system for use in removing jitter from a signal having gaps that result from the removal of error correction and synchronization information. The system includes a reference signal having a plurality of periodic pulses and a counting mechanism configured to count the periodic pulses in the reference signal by incrementing a count value by a first predetermined number. A reset mechanism resets the count value to a particular reset value when the count reaches a second predetermined number such that the ratio of the second predetermined number to the first predetermined number represents the ratio of the total amount of information in the input signal before removal of the error correction and synchronization information to the amount of error correction and synchronization information removed from the input signal. A pulse generating mechanism generates an output signal pulse on each pulse of the reference signal for which the count value has not reached the second predetermined number and leaves a gap in the output signal on pulses for which the reset mechanism resets the count value, where each pulse of the output signal is synchronized with one of the pulses of the reference signal.