1. Field
The invention relates to an integrated power module for multi-device parallel operation. More particularly, the invention relates to systems and methods for providing a low parasitic inductance design and a more symmetrical layout design for an integrated power module for multi-device parallel operation.
2. Description of the Related Art
FIG. 1 is a conventional top view power module 100 layout that shows as an example four transistor chips 120 and FIG. 2 is a circuit schematic 200 of the conventional power module 100 shown in FIG. 1. The circuit shown in FIG. 2 is a switch position of any power electronics circuit topology, e.g., half-bridge, full-bridge, etc. Referring to FIGS. 1 and 2, the power module 100 includes a dielectric substrate 105, conductor traces (or pads) 110, four transistor chips 120, and wire bonds 115. The dielectric substrate 105 may be formed of a material such as Alumina, Aluminium Nitride (AlN), Silicon Nitride (Si3N4), and so on. The conductor traces (or pads) 110 are copper (or aluminum) traces or pads integrated into the dielectric substrate 105. The dielectric substrate 105 is sometimes referred to as Direct Bond Copper (DBC), Direct Bond Aluminum (DBA), or Active Metal Brazing (AMB).
The conductor traces (or pads) 110 are etched to form a source (S) conductor trace (or pad) 125, a drain (D) conductor trace (or pad) 130, and a gate (G) conductor trace (or pad) 135 (from top to bottom). As an example, the transistor chips 120 are shown as MOSFETs. However, other types of transistor chips 120 can be used such as IGBTs, JFETs, BJTs, and so on. Each transistor chip 120 includes at least three electrical conductor traces 110, for example, the source (S) conductor trace 125, the drain (D) conductor trace 130, and the gate (G) conductor trace 135. Each transistor chip 120 is positioned on or mounted onto the drain (D) conductor trace 130. The source (S) conductor trace 125, the drain (D) conductor trace 130, and the gate (G) conductor trace 135 are formed or integrated as conductors 110 on the dielectric substrate 105. Hence, each similar electrical element (e.g., source, drain or gate) shares the same conductor or pad. The conductor traces 110 can be any kind of conducting material attached to or formed on the dielectric substrate 105. As shown in FIGS. 1 and 2, the source (S) conductor trace 125, the drain (D) conductor trace 130, and the gate (G) conductor trace 135 are connected by wire bonds 115 and transistor chips 120. Other types of connectors can be used such as lead frames.
The transistor chips 120 are arranged in a parallel circuit configuration. One drawback of arranging the transistor chips 120 in a parallel configuration is that gate loops are formed between the paralleled transistor chips 120.
FIG. 3 is a circuit schematic 300 of the conventional power module 100 of FIGS. 1 and 2 with gate and source inductances (Lg and Ls) shown. The gate voltage to the source voltage of each device 320 is built up at a different speed because of the inherent unbalanced characteristics of the devices 320 and the asymmetric layout. As a result, the conventional power module 100 is prone to suffer gate oscillation as illustrated in FIG. 3. The arrows 325 illustrate an example of the oscillation loops, i.e., the common gate to common source loops. In some configurations, common gate to common drain loops may also be formed. The oscillation occurring at the gate (G) conductor trace 135 may turn on or turn off the transistors 320 accidentally, which may cause the transistors 320 to short-circuit or malfunction.
FIG. 4 is another conventional top view power module 400 layout with separate gate conductor pads 405 and FIG. 5 is a circuit schematic 500 of the conventional power module 400 but the individual gate resistors (Rg) are located on a printed circuit board (PCB) and are added in order to complete the loops 525. Referring to FIGS. 4 and 5, the conventional power module 400 divides the gate conductor into separate gate conductor pads 405 and connects each gate pad 405 to a PCB (not shown) by terminal pins or a case (not shown) by wire bonds. At the output terminal of the gate drive board or circuit (usually on top of the power module 400), a gate resistor (Rg) is connected to each individual gate terminal to dampen the oscillation, as shown in FIG. 5. Connecting each gate conductor pad 405 to the gate resistor (Rg) on the gate drive board or circuit essentially increases the length of the gate loop, and thus increases the total loop inductance (Lg and Ls), which are undesirable characteristics for designers.
The above drawbacks provide challenges to designers of integrated power modules. Thus, there is a need for an integrated power module that overcomes the above drawbacks.