1. Field of the Invention
The invention relates to a semiconductor memory and a driving method of a semiconductor memory. More particularly, the invention relates to a semiconductor memory having a ferroelectric capacitor and a driving method of such a memory.
2. Related Background Art
In recent years, an interest in a memory using a ferroelectric substance as a capacitor dielectric film (hereinafter, such a memory is referred to as a “ferroelectric memory”) is increasing more and more. The ferroelectric memory stores information by using a spontaneous polarization of a ferroelectric substance. When a polarizing direction is oriented to one direction by once applying a voltage to the ferroelectric capacitor, the polarization remains (referred to as a “residual polarization”) even if no electric power is supplied after that, and the stored information is held. The ferroelectric memory having such a feature can be used as a non-volatile memory.
Further, in case of a general volatile memory such as a DRAM or the like, a voltage of 10V or more is necessary for writing data. According to the ferroelectric memory, a polarizing direction of the ferroelectric capacitor is reversed by a voltage of a few volts and data can be written. A data writing time of the general non-volatile memory is on the order of microseconds. A polarization reversing time of the ferroelectric memory is on the order of nanoseconds. As mentioned above, the ferroelectric memory is largely expected as a non-volatile memory of the next generation in which the operation of a low voltage and a high speed can be executed.
At present, a ferroelectric memory having a plurality of memory cells comprising MOS transistors (selective transistors) each of which functions as a switching device and ferroelectric capacitors mainly becomes a target of study and development. A construction and the operation of the memory cells of the ferroelectric memory will now be described with reference to FIG. 5.
In case of writing data into a memory cell MC, a word line WL is asserted and a selective transistor Tr is turned on. 0 v is applied to a bit line BL and a positive voltage is applied to a plate line PL. Thus, a polarization of a ferroelectric capacitor C is directed to one direction (↑ direction) shown in FIG. 5 and it is stored as information of, for example, “1” into the memory cell MC. On the contrary, when a positive voltage is applied to the bit line BL and 0V is applied to the plate line PL, the polarization of the ferroelectric capacitor C is directed to the direction (↓ direction) opposite to the above one direction and it is stored as information of, for example, “0” into the memory cell MC.
In case of reading out the information from the memory cell MC, the bit line BL is precharged to 0V and a positive voltage is applied to the plate line PL. If the ferroelectric capacitor C has already been polarized in the opposite direction (↓ direction) (the information “0” has been held), the polarizing direction is reversed. On the other hand, if the ferroelectric capacitor C has already been polarized in one direction (↑ direction) (the information “1” has been held), the polarizing direction is not reversed. An electric potential of the bit line BL changes in accordance with the polarizing state of the ferroelectric capacitor C. Therefore, by detecting and amplifying a change amount of the electric potential of the bit line BL by a sense amplifier SA connected to the bit line BL, the information stored in the memory cell MC is read out.
The sense amplifier SA amplifies the electric potential of the bit line BL to either the L (low) level (for example, 0V) or the H (high) level (for example, a power potential Vcc) by using a reference potential Vref as a reference.
Generally, a dummy memory cell (not shown) in which information opposite to that in the memory cell MC is stored is provided for the ferroelectric memory. The reference potential Vref is inputted from the dummy memory cell to the sense amplifier SA. In this case, one information is stored by two memory cells in which complementary data is stored, respectively. Such a memory configuration is called a 2-transistor/2-capacitor (2T/2C) type.
As a memory configuration of the DRAM, a 1-transistor/1-capacitor (1T/1C) type in which one information is stored by one memory cell is used. According to the memory of the 1T/1C type, as compared with the 2T/2C type, since a layout area of a memory cell array is reduced, a large capacity of the memory can be easily realized.
The conventional ferroelectric memory having the memory array of the 1T/1C type has been disclosed in, for example, JP-A-7-93978. FIGS. 18(a) and 21 of this Official Gazette show circuit constructions of the conventional ferroelectric memory, and FIGS. 18(b) and 22 show the data reading operations thereof.
Although the 1T/1C type has a structural advantage as mentioned above, the use of it to the ferroelectric memory is not progressed due to the following reasons.
In case of the memory of the 1T/1C type, a circuit for generating the reference potential Vref is additionally necessary. In the ferroelectric memory, its circuit construction is more complicated than that of the DRAM.
In case of the DRAM, the bit line is set to ½ of the power voltage Vcc, the plate line is set to the power voltage Vcc or 0V, and data is written into the memory cell. After that, in order to read out the data, it is sufficient to precharge the bit line to ½ Vcc and activate the word line. An electric potential which is induced to the bit line is set to a voltage which is either higher or lower than ½ Vcc in accordance with the data stored in the memory cell. That is, in case of the DRAM, if ½ Vcc is used as a reference potential Vref, the stored data can be accurately read out.
Also in case of the ferroelectric memory as a target of the present invention, in a manner similar to the DRAM, an electric potential of the bit line during the data reading operation differs in dependence on contents of the data which is read out. Since an absolute value of the bit line potential differs in dependence on a variation of characteristics of the ferroelectric capacitor, it is not easy to decide such a value at the stage of design. Therefore, it is extremely difficult to generate the reference potential Vref adjusted to an intermediate value of two electric potentials which show a binary value and are induced on the bit line during the data reading operation, that is, an average value of the bit line potential in case of reading out the information “0” and the bit line potential in case of reading out the information “1”. Unless the reference potential Vref is accurately adjusted to the intermediate value of the two electric potentials induced on the bit line, there is also a possibility that the stored information is erroneously read out.
As mentioned above, hitherto, in case of using the memory array construction of the 1T/1C type for the ferroelectric memory, since the reliability of the data which is read out deteriorates, the memory construction of the 2T/2C type which is disadvantageous to realize a large capacity has to be used.