1. Field of the Invention
This invention relates in general to the field of microelectronics, and more particularly to an apparatus and method for synchronizing and clocks and data related to the transmission and reception of source synchronous signals.
2. Description of the Related Art
A present day computer system employs a source synchronous system bus to provide for exchange of data between bus agents, such as between a microprocessor and a memory hub. A “source synchronous” bus protocol allows for the transfer of data at very high bus speeds. Source synchronous protocols operate on the principle that a transmitting bus agent places data out on the bus for a fixed time period and asserts or switches a “strobe” signal corresponding to the data to indicate to a receiving bus agent that the data is valid. Both data signals and their corresponding strobe are routed over the bus along equal propagation paths, thus enabling a receiver to be relatively certain that when switching of the corresponding strobe is detected, data is valid on the data signals.
But data strobes and data signals are subject to error for a number of reasons. One source of error is inaccuracies of associated clock generation circuits, typically phase locked loops, that are employed to gate the data signals onto the bus and to switch the strobes to indicate that the data is valid. These inaccuracies may be the result of design margins, fabrication tolerances, or environmental factors. In an optimum case, it is desired that a strobe signal switch precisely halfway through a data validity period so that there is equal set up and hold time for the data as seen at the receiver. And inaccuracies in the associated clock generation circuits may result in skewing of the data signals and/or their strobes such that reception conditions are not optimum.
Another source of error caused by distribution of a strobe signal within a receiving device. While system designers go to great lengths to ensure that a strobe and its associated data signals are routed along the same propagation path on a system board (i.e., motherboard), it is well known that once the strobe enters the receiving device, it must be distributed to all of the internal synchronous receivers that are associated with that strobe. In some devices, the additional propagation lengths that are required to route the strobe to various receivers may add delay over that of the data signals, thereby skewing the phase of the synchronous transmission.
Therefore, what is needed are apparatus and methods that compensate for misalignment of signals on a synchronous data bus.
What is also needed is a technique that allows the signals on a synchronous bus to be optimized for reception by modifying the phase alignment of a data strobe and its corresponding data signals.
What is furthermore needed is a mechanism that allows the phase alignment of a data strobe and its associated data signals to be modified at the motherboard level.
What is moreover needed is an apparatus that is programmable at the motherboard level to align synchronous bus signals for optimum reception conditions.