This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-026086, filed on Feb. 3, 2003; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly relates to a vertical trench MOSFET.
2. Related Background Art
Power MOSFETs have been increasingly used in not the only high current, high withstand voltage switching power supply market but also the energy saving switching market for mobile communications equipment including notebook personal computers and the like. For such purposes, the power MOSFET is often used in a power management circuit, the safety circuit of a lithium ion battery, or the like. Therefore, in view of realizing low driving voltage, low ON resistance and low switching loss by which directly driving of the power MOSFET with a battery voltage is enabled, it is required to further decrease the capacitance between the gate and drain of the power MOSFET.
As an index which represents element characteristics for evaluating the decrease of the driving voltage, that of the ON resistance, and that of the switching loss of the element, the product Ronxc2x7Qgd of the ON resistance Ron and the gate-drain electric charges Qgd during switching is employed. The element characteristic index Ronxc2x7Qgd is the product of the ON resistance and the gate-drain electric charges Qgd during switching. Due to this, the lower the index is, the larger the decrease of the driving voltage, that of the ON resistance, and that of the switching loss of the element become.
FIG. 1 is a cross-sectional view showing a first example of conventional trench gate type power MOSFETs. FIG. 2 is a plan view of the surface of the semiconductor substrate of the first example of the conventional trench gate type power MOSFETs. It is noted that FIG. 1 is a cross-sectional view taken along line DDxe2x80x2 of FIG. 2 and that FIG. 2 is a plan view of the semiconductor substrate surface in a state in which source electrodes on the semiconductor substrate surface are eliminated so as to facilitate understanding.
The conventional trench gate type power MOSFETs include an n+ type semiconductor substrate 1, an nxe2x88x92 type semiconductor layer 2 formed on the n+ type semiconductor substrate 1, a p type base layer 3 formed on the nxe2x88x92 type semiconductor layer 2, a plurality of columns of stripe trenches 4 formed at predetermined intervals from the surface of the p type base layer 3 by a predetermined depth, insulating films 5 formed on the side surfaces and bottoms of the respective trenches 4, n+ type source layers 6 formed in the surface layer portions of the p type base layer 3 between the respective trenches 4, stripe p+ contact layers 7 formed at the center of the surface layer portions of the p type base layer 3 between the respective trenches 4, gate electrodes 8 formed in the respective trenches 4, source electrodes 9 formed on the respective n+ type source layers 6 and the p+ type contact layers 7, and a drain electrode 10 formed on the rear surface of the n+ type semiconductor substrate 1.
The nxe2x88x92 type semiconductor layer 2 consists of, for example, an epitaxial layer formed by epitaxial growth. As shown in FIG. 1, for example, each stripe trench 4 has a depth from the surface of the p type base layer 3 to the surface layer portion of the nxe2x88x92 type semiconductor layer 2. The insulating film 5 consists of, for example, a silicon oxide film.
A parameter al shown in FIG. 2 represents the element interval of the first example of the conventional trench gate type power MOSFET.
FIG. 3 is a cross-sectional view of a second example of the conventional trench gate type power MOSFETs. FIG. 4 is a plan view of the semiconductor substrate surface of the second example of the conventional trench gate type power MOSFETs. It is noted that FIG. 3 is a cross-sectional view taken along line EExe2x80x2 of FIG. 4 and that FIG. 4 is a plan view of the semiconductor substrate surface in a state in which source electrodes on the semiconductor substrate surface are eliminated so as to facilitate understanding.
A parameter a2 shown in FIG. 4 represents the element interval of the second example of the conventional trench gate type power MOSFET.
The second example of the conventional trench gate type power MOSFET is equal in configuration to the first example except that the element interval a2 is twice as high as the element interval a1 of the first example.
The element characteristic index Ronxc2x7Qgd stated above will now be considered. The gate-drain electric charges Qgd during switching increase proportionally to the density of the gate. Therefore, if the element interval is, for example, doubled as in the case of the element interval of the second example of the conventional trench gate type power MOSFET relative to that of the first example, the gate-drain electric charges Qgd during switching are halved.
On the other hand, the components of the ON resistance Ron are divided to a channel resistance and an epitaxial layer resistance. The ratio of the channel resistance to the epitaxial layer resistance of the first example of the conventional trench gate type power MOSFET is 1:1. If the element interval is doubled, the channel resistance is doubled but the epitaxial layer resistance remains the same. As a result, the overall ON resistance Ron of the element is increased to 4/3 times.
Accordingly, as in the case of the second example relative to the first example of the conventional trench gate type power MOSFET, the element characteristic index Ronxc2x7Qgd can be decreased to 2/3 times by doubling the element interval.
However, the trench gate type power MOSFET having the high element interval has a disadvantage of low unclumped inductive switching capability during switching if an inductor is a load.
A semiconductor device according to the first embodiment of the present invention comprises:
a semiconductor substrate of a first conductive type;
a semiconductor layer of the first conductive type formed on the semiconductor substrate;
a base layer of a second conductive type formed on the semiconductor layer;
a plurality of columns of stripe trenches formed at predetermined intervals from a surface of the base layer by a predetermined depth;
insulating films formed on side surfaces and bottoms of the trenches, respectively;
source layers of the first conductive type formed on surface layer portions of the base layer between the trenches, respectively;
stripe contact layers of the second conductive type formed each at centers of the surface layer portions of the base layer between the trenches, respectively;
a gate electrode formed in every other trench among the plurality of columns of trenches;
source electrodes formed in the trenches other than the trenches in which the gate electrodes are formed and on the source layers and the contact layers, respectively; and
a drain electrode formed on a rear surface of the semiconductor substrate.
A semiconductor device according to the second embodiment of the present invention comprises:
a semiconductor substrate of a first conductive type;
a semiconductor layer of the first conductive type formed on the semiconductor substrate;
a base layer of a second conductive type formed on the semiconductor layer;
a plurality of columns of stripe trenches formed at predetermined intervals from a surface of the base layer by a predetermined depth;
insulating films formed on side surfaces and bottoms of the trenches, respectively;
gate electrodes formed in every two columns of the respective trenches among the plurality of columns of trenches;
source layers of the first conductive type formed on surface layer portions of the base layer adjacent to the trenches in which the gate electrodes are formed, respectively;
contact layers of the second conductive type formed to be stripe at centers of the surface layer portions of the base layer on which the source layers are formed, and formed on the surface layer portions of the base layer other than the surface layer portions of the base layer on which the source layers are formed, respectively;
source electrodes formed in the trenches other than the trenches in which the gate electrodes are formed and on the source layers and/or the contact layers, respectively; and
a drain electrode formed on a rear surface of the semiconductor substrate.
A semiconductor device according to the third embodiment of the present invention comprises:
a semiconductor substrate of a first conductive type;
a semiconductor layer of the first conductive type formed on the semiconductor substrate;
a base layer of a second conductive type formed on the semiconductor layer;
a plurality of columns of stripe trenches formed at predetermined intervals and at wider intervals for every three columns from a surface of the base layer by a predetermined depth;
insulating films formed on side surfaces and bottoms of the trenches, respectively;
gate electrodes formed in the central trenches of the respective three consecutive columns of trenches formed at the predetermined intervals among the plurality of columns of trenches;
source layers of the first conductive type formed on surface layer portions of the base layer adjacent to the trenches in which the gate electrodes are formed, respectively;
contact layers of the second conductive type formed to be stripe at centers of the surface layer portions of the base layer on which each of the source layers is formed, and formed on the surface layer portions of the base layer other than the surface layer portions of the base layer on which the source layers are formed, respectively;
source electrodes formed in the trenches other than the trenches in which the gate electrodes are formed and on the source layers and/or the contact layers, respectively; and
a drain electrode formed on a rear surface of the semiconductor substrate.