Charge-coupled device (CCD) image sensors and complementary metal-oxide semiconductor (CMOS) image sensors are the two major types of electronic image sensors currently in use. CCD image sensors can provide excellent light sensitivity and high image quality, but manufacturing of CCD image sensors generally requires specialized fabrication processes that make CCD sensors more expensive to make and more difficult to integrate with associated circuitry. CMOS image sensors, on the other hand, can be inexpensively fabricated using standard CMOS manufacturing technology and can be easily integrated on the same die with circuit blocks serving other imaging and non-imaging functions. However, high light sensitivity and high image quality are more difficult to achieve with CMOS image sensors.
FIG. 1 illustrates a conventional CMOS image sensor 100, which includes an array 110 of pixel sensors 120. Control lines (e.g., row lines 112 and column lines 114) in array 110 connect pixel sensors 120 to control circuits such as row control block 130 and column control block 140 that are outside array 110. Generally, a selection signal can be asserted on one of row line 112 to select a row of pixel sensors 110 for reading via column lines 114. FIG. 1 shows only row lines 112 and column lines 114 connected to pixel sensors 120, but more generally, the circuitry in each pixel sensor 120 also connects to additional control lines (not shown).
Capturing an image with CMOS image sensor 100 generally includes a reset operation, an integration operation, and a readout operation. The reset operation resets voltages on the nodes of photodiodes in pixel sensors 120. After the voltages are reset, the integration operation partially discharges (or charges) the nodes via currents that flow through the photodiodes. The current through each photodiode depends on the intensity of the incident light on the photodiode, so that the voltage on the photodiode node in a pixel sensor 120 at the end of the integration operation indicates an integral of the intensity of the incident light on that pixel sensor 120 during the integration operation. The readout operation samples or measures the photodiode voltages, and those voltages can be converted to digital pixel values.
Signal noise can be a significant problem in CMOS image sensor 100, particularly during the reset operations. Ideally, each reset operation sets the photodiode node of a pixel sensor to the same reference voltage level. If a particular pixel sensor 120 is charged to different levels during different reset operations, the pixel values read out from the pixel sensor will be inconsistent from one image to the next, leading to poor image quality.
FIG. 2 is a circuit diagram of a conventional pixel sensor 200 that is designed to provide low noise levels during reset operations. Pixel sensor 200 includes a photodiode 210, a PMOS transistor 220, and five NMOS transistors 230, 240, 250, 260, and 270. Transistors 220, 230, 240, and 250 form a reset circuit 280, and transistors 260 and 270 form a readout circuit 290. Reset circuit 280 serves to reset a voltage Vpd on a node of photodiode 210 before an integration operation. During the integration operation, incident light on photodiode 210 causes a current that pulls voltage Vpd down to a level that depends on the intensity of the incident light. Readout circuit 290 reads out voltage Vpd, which indicates an integrated light intensity for the pixel.
For an active reset operation, a control signal Vpr is high (i.e., at supply voltage level Vdd), control signal Vg is high, and control signal Vr starts low (i.e., at ground level) and begins ramping up. Bias voltage Vbias controls a current through transistor 220, which raises voltages V1 and V2. When voltage V2 nears the threshold voltage of transistor 250, transistor 250 charges up photodiode voltage Vpd, which turns on transistor 230. Voltages V1 and V2 then begin following the rise in control voltage Vr. When control voltage Vr reaches supply voltage Vdd, photodiode voltage Vpd reaches its maximum value, which is less than supply voltage Vdd because of the threshold voltages of NMOS transistors 240 and 250. For example, if supply voltage Vdd is a nominal 2.8 volts, the maximum voltage for signal Vr is about 1.2 volts, which is less than supply voltage Vdd by the threshold voltages of transistors 240, 250, and 130, and the maximum for photodiode voltage Vpd is about 1.8 volts, less than supply voltage Vdd by the threshold voltages of transistors 240 and 250.
To prepare for the integration operation, control voltage Vr is decreased, and then about 1 or 2 μS later, bias voltage Vbias is raised at the end of the reset operation. During the reset operation, the devices in reset circuit 280 operate as an amplifier where photodiode voltage Vpd is greater in voltage than control signal Vr by the threshold voltage of transistor 230. When control signal Vr drops, for example, by about 50 mV, photodiode voltage Vpd must fall to maintain stable closed loop behavior. The only way for photodiode voltage Vpd to fall is for voltages V1 and V2 to fall and pull charge from the photodiode node via the parasitic gate to source capacitance of transistor 250. The small change in signal Vr induces a large change in voltages V1 and V2, shutting off transistor 250 and trapping photodiode voltage Vpd near its maximum level. Control signal Vg can then go low, shutting off transistor 240 to disable the feedback loop allowing the current through photodiode 210 to control photodiode voltage Vpd.
After integration, the readout operation asserts a signal WORD on the word line 112 that is coupled to pixel sensor 200, thereby turning on transistor 270. The bit line 114 connected to pixel sensor 200 is then pulled up via a current through transistor 260, which has a gate at photodiode voltage Vpd, permitting measurement of photodiode voltage Vpd through the effect on bit line 114. U.S. Pat. No. 6,424,375, entitled “Low Noise Active Reset Readout for Image Sensors” further describes operation of pixel sensors similar to pixel sensor 200.
Pixel sensor 200 has some significant drawbacks. In particular, pixel sensor 200 includes five NMOS transistors 230, 240, 250, 260, and 270 and one PMOS transistor 220, which are difficult to fit within the available area of a fine pitch pixel sensor array, especially since PMOS transistor 220 generally requires additional space for isolation. Even for larger pixels, the circuit area required for the transistors 220, 230, 240, 250, 260, and 270 significantly reduces the circuit area available for light-sensing photodiode 210, causing a low fill factor and low light sensitivity. Additionally, pixel noise is sensitive to the impedance ramp generator driving control signal Vr. In a two-dimensional array of pixel sensors, control lines for signal Vr will add resistance to the impedance of the circuit drive control signal Vr, resulting in higher noise levels when pixel sensor 200 is in an image sensing array such as illustrated in FIG. 1.
In view of the drawbacks of existing CMOS image sensors, pixel sensors are sought that contain fewer transistors and control lines while still implementing low-noise reset operations.