The desire to realize smaller and thinner modules mounted with semiconductor ICs has prompted numerous proposals regarding how to mount a bare semiconductor IC chip on a printed circuit board. A semiconductor IC in the bare-chip state has a very much narrower electrode pitch than a packaged semiconductor IC. When it is mounted on a printed circuit board, therefore, a need arises to address the important issue of how to bond the electrode pads of the semiconductor IC (sometimes called the “land electrodes” in the following description) with the wiring of the printed circuit board (sometimes called the “board wiring pattern”).
One known method of bonding the land electrodes and board wiring pattern is wire bonding. Although this method enables relatively easy mounting of a bare-chip semiconductor IC, a problem arises in that the mounting area becomes large owing to the need to establish the region for mounting the semiconductor IC and the region for connecting the bonding wires on different surfaces of the printed circuit board.
Another method of connecting the land electrodes and board wiring pattern is that of mounting the bare-chip semiconductor IC by the flip-chip method. While this method reduces the mounting area, it involves complicated processing, such as applying multiple layers of under barrier metal (UBM) on the land electrodes in order to ensure adequate mechanical bonding strength between the land electrodes and board wiring pattern.
Moreover, both of these methods result in the semiconductor IC being mounted on the surface of the printed circuit board. The methods therefore have the common disadvantage of making it difficult to reduce the overall thickness of the module. Japanese Patent Application Laid Open No. 9-321408 ('408) teaches a method of fabricating a module with embedded semiconductor IC by forming a cavity in the printed circuit board and embedding a bare-chip semiconductor IC in the cavity.
When the method of '408 is adopted, however, the thickness of the printed circuit board needs to be increased to some degree so as to reinforce the strength of the region where the cavity is formed. This runs counter to the desire to make the module thinner. In addition, the size of the cavity in the planar direction has to be made somewhat larger than the size of the semiconductor IC in the planar direction. The resulting shift in the positional relationship between the land electrodes and board wiring pattern makes it very difficult to use a semiconductor IC having an electrode pitch of 100 μm or smaller.
Thus with the conventional module with embedded semiconductor IC, it is difficult to achieve sufficient thickness reduction and, further, very difficult to use a semiconductor IC having a narrow electrode pitch.
In the method taught by '408, most of the semiconductor IC is covered by the resin layer for filling the cavity. When a material excellent in physical properties is selected for the resin layer, the electrical properties are inadequate, and when a material excellent in electrical properties is selected, the physical properties are inadequate. In the conventional module with embedded semiconductor IC, it has therefore been hard to achieve both good semiconductor IC physical protection and excellent electrical properties at the same time.