1. Field of the Invention
The present invention relates to a device equipped with series connected thyristors and adapted for use as a reactive power compensator or the like.
FIG. 1 shows a conventional reactive power compensator as an example of this type, wherein there are included an AC power source 1 for supplying a voltage V, a power source impedance 2, an inductive load 3, a reactive power compensator 4, a phase advance capacitor 5, a current controller 6 consisting of a diode 7 and a thyristor 8 which are so connected as to constitute an antiparallel circuit, a voltage transformer 9, a current transformer 10, a reactive power detector 11, and a gate signal generator 12. The reactive power detector 11 serves to detect a reactive power Q out of a circuit voltage V.sub.R obtained from the voltage transformer 9 and a circuit current I.sub.R obtained from the current transformer 10 and, upon increase of the detected reactive power Q to a preset value, feeds a capacitor output command signal q to the gate signal generator 12. As shown in FIG. 3, the gate signal generator 12 comprises a timing pulse generator 121, an inverter 122, AND elements 123a and 123b, and a signal generator 124. The timing pulse generator 121 receives the output V.sub.R of the voltage transformer 9 shown in FIG. 1 and, as illustrated in FIG. 5, produces a gate-on command pulse P.sub.ON synchronously with the negative maximum value of the output V.sub.R and also a gate-off command pulse P.sub.OFF after delay of a predetermined time To therefrom. And both the pulse P.sub.ON and the capacitor output command signal q are fed to the AND circuit 123a, while the pulse P.sub.OFF and the inverted capacitor output command signal q obtained from the inverter 122 are fed to the AND circuit 123b. The gate signal generator 124 consists of a self-excited oscillator which, in response to an input signal received at its terminal A from the AND circuit 123a, feeds a wide-duration gate signal GP to the gate of the thyristor 8 and maintains such an action continuously until arrival of a signal at its terminal B from the AND circuit 123b.
FIG. 2 shows a current controller 6 employed when the main circuit of the device is of high-voltage type. This controller consists of a plurality of series connected diodes 7a, 7b and 7c and a plurality of series connected thyristors 8a, 8b and 8c. Also shown are pulse transformer 13 and demodulators 14a, 14b and 14c.
Hereinafter the operation of this device will be described with reference to the waveform charts of FIGS. 4 and 5.
Since the thyristor 8 remains in its off-state until arrival of the capacitor output command signal q, the phase advance capacitor 5 is charged at a potential equivalent to the negative maximum value V.sub.max of the voltage V, so that a voltage V.sub.A-K having a waveform of FIG. 4 (c) including both the supply voltage V and the output voltage V.sub.C of the capacitor 5 superposed thereon is applied between the anode and the cathode of the thyristor 8.
Supposing now that the capacitor output command signal q is produced at time t.sub.0, the gate-on command signal P.sub.ON is not outputted despite application of the signal q to the gate signal generator 12 until time t.sub.1 at which the supply voltage V reaches its negative maximum value, so that the gate signal GP is not generated either until arrival of time t.sub.1. This circuit configuration is designed in such a manner as to prevent flow of a rush current from the phase advance capacitor 5 by placing the thyristor 8 in a conducting state when the voltage V.sub.A-K applied thereto is in the vicinity of its zero level. Upon generation of the gate signal GP, the thyristor 8 is turned on to permit flow of a capacitor current Ic of FIG. 4 via the phase advance capacitor 5, thereby compensating for the reactive power in the main circuit to improve the power factor thereof.
When the power factor is thus improved to reduce the reactive power below a predetermined value, the capacitor output command signal q comes to be extinct. But even after extinction of the signal q at time t.sub.2 as shown, the capacitor current Ic still keeps flowing via the diode 7 until time t.sub.4 at which the supply voltage V reaches its negative maximum value. For this reason, the gate-off command pulse P.sub.OFF is preset to have a duration shorter than one cycle of the supply voltage V by the turn-off time T.sub.OFF of the thyristor 8.
The above conventional device performs its operation as mentioned when the load 3 is an inductive one. However, in case the load 3 is a thyristor unit or the like, the waveform of the supply voltage V is distorted as shown in FIG. 6 due to higher harmonics included in the circuit current I, so that a distorted current comes to flow in the phase advance capacitor 5. An example of such distorted current is shown in FIG. 6 (d). If the time point, at which the current Icd flowing in the diode 7 (hereinafter referred to as diode current) becomes zero like the capacitor current Ic, deviates toward time t.sub.3 of extinction of the gate signal GP in the case where the current controller 6 is equipped with series connected thyristors 8a, 8b and 8c as shown in FIG. 2, there may occur an undesired phenomenon that, for example, the thyristors 8a and 8b are turned off while the thyristor 8c fails to be turned off because of some variation in the turn-off characteristics of the individual thyristors. And with subsequent increase of the supply voltage V posterior to time t.sub.4, the entire voltage comes to be applied to the thyristor 8c alone to eventually cause its withstand voltage breakdown. (Hereinafter this will be referred to as first case of withstand voltage breakdown.)
Furthermore, when the waveform of the capacitor current Ic is distorted as shown in FIG. 7 (d), i.e. in case the current flowing in the circuit of thyristors 8a, 8b and 8c at the time of extinction of the gate signal GP is commutated to the circuit of diodes 7a, 7b and 7c at time t.sub.42 and then is blocked by the thyristors 8a, 8b and 8c at time t.sub.43 : the period from time t.sub.42 to time t.sub.43 is excessively short to fail in securing a sufficient turn-off time as a result, and due to the variation in the characteristics of the individual thyristors, there occurs a phenomenon that, e.g. the thyristor 8c alone is left in its on-state and is finally led to withstand voltage breakdown. (Hereinafter this will be referred to as second case of withstand voltage breakdown.)