Scaling the physical size of CMOS devices has been a principal focus of the microelectronics industry over the last two decades. A more recent scaling technique utilizes a deep-submicron CMOS type process. Deep-submicron CMOS is a primary technology for ultra-large scale integrated-circuit (ULSI) systems.
A MOSFET, by its own geometric nature, is a symmetrical device in the sense that the source and drain are interchangeable. In other words, they are identified by the operating bias rather than the structure. However, as the gate length becomes increasingly small, the device operation is asymmetrical, even at a very low drain bias. This asymmetrical operation results in short-channel effects (SCE), such as threshold voltage roll-off and drain induced barrier loading (DIBL), as well as hot-carrier effects that limit the transistor scaling. As the conventional scaling limit is approached, new structures employing asymmetric architectures must be developed. However, building asymmetrical structures requires that new techniques be developed in order to manufacture these reduced scale designs.
The problems associated with short channel effects, such as threshold voltage roll-off and DIBL that degrade the performance of scaled MOS devices, have been addressed by the recently proposed dual-material gate field-effect transistor (DMGFET). The proposed DMGFET is described in the publication by W. Long and K. K Chin, of a "Dual Material Gate Field Effect Transistor (DMGFET)," IEEE IEDM Tech. Dig., 1997, pp. 549-552 (hereinafter referred to as "Long"), and is based upon the ideas of dual-gate and split-gate transistors.
Dual-gate transistors are discussed in a publication by P. Dollfus and P. Hesto, entitled "Monte Carlo Study of a 50 nm-Dual-Gate HEMT Providing Against Short-Channel Effects," Solid-State Electron., vol. 36, no. 5, pp. 711-715, 1993, (hereinafter referred to as "Dollfus"). Also, split-gate transistors are discussed in a publication by M. Shur, entitled "Split-gate field-effect transistor," Appl. Phys. Lett., vol. 54, no. 2, pp. 162-164, 1989, (hereinafter referred to as "Shur").
The DMGFET has a gate comprising two laterally contacting materials with different work functions. For both an N-channel FET and a P-channel FET, this gate structure takes advantage of a material work function difference.
For an N-channel FET, the threshold voltage near the source is more positive than that near the drain. Utilization of this material work function difference results in a more rapid acceleration of the charge carriers in the channel and a screening effect to suppress the short channel effects.
The DMGFET has shown a significant suppression of short-channel effects, as well as an enhancement of transconductance. These "DMG effects" have been demonstrated with a 1 .mu.m HFET, and it has been predicted that more benefits could be obtained for devices with ultra-small dimensions. Simulation has shown that, for an N-channel FET, by adding a layer of material with a larger work-function to the source side of the gate, short channel effects of an N-channel FET can be greatly suppressed without degrading the driving ability. These "DMG effects" are discussed in more detail in the publication by Xing Zhou and Wei Long, entitled "A Novel Hetero-Material Gate (HMG) MOSFET for Deep-Submicron ULSI Technology", IEEE Trans., Electron. Dev., vol. 45, no. 12, 1998, (hereinafter referred to as "Zhou").
Each of the four above referenced publications, Long, Dollfus, Shur, and Zhou, are each incorporated by reference as though fully set forth herein.
Accordingly, for a P-channel FET, by adding a layer of material with a smaller work-function to the source side of the gate, the short channel effects of a P-channel FET can be greatly suppressed. It is of vital importance, however, that such novel devices can be integrated into the current ULSI technology.
Both the Long and Zhou references discuss the manufacture of dual material gates. However, some problems exist with the conventional techniques of forming dual material gate devices.
The Long reference describes the conventional technique for fabricating a dual material gate device, but for a metal gate. For example, to form a dual material gate of 1 .mu.m in length, a first gate material is evaporated with a carefully controlled tilt angle, and then a second material is formed using conventional evaporation. Unfortunately, this tilt evaporation technique is not easily transferable to polysilicon gates. Further, this tilt technique is not easily integrated with other process steps currently utilized in the fabrication of high density CMOS type devices.
In the Zhou reference, Zhou concludes that "a technology breakthrough in realizing the proposed device would have tremendous impact on the ULSI technology." The present invention provides one such breakthrough.