This invention relates generally to methods for determining the frequency or period of a signal, and more specifically to methods for determining a timestamp for a timing edge of a signal.
The frequency (f) of a repetitive (or periodic) signal can be defined by the number of cycles (M) of that signal that occur during a particular time interval (t). There are several known methods for determining the frequency of a signal, which is also referred to as frequency counting. Two basic types of frequency counting are direct counting and reciprocal counting.
A direct counter counts the number of signal cycles (M) for a known time interval (e.g., 1 second). If the time interval is equal to one second (t=1 s), the frequency is expressed as the number of cycles per second or the number of cycles Hertz (Hz).
On the other hand, rather than count the number of signal cycles to determine frequency (f), a reciprocal counter determines the period (T) of the signal, which can be determined by measuring the time interval (t) for completion of a single signal cycle (T=t). Once the period of a signal has been determined, the frequency of that signal can be determined by the reciprocating the period (f=1/T) to calculate the number of signal cycles per second or the number of signal cycles Hz. Alternatively, rather than measuring the time interval for completion of a single signal cycle, the period can be determined by measuring the time interval (tM) for completion of a known number of signal cycles (M) and dividing that time interval by the number of signal cycles (T=tM/M). Once again, the frequency of that signal can be determined by calculating the reciprocal of the period (f=1/T=M/tM). Accordingly, in order to determine the time interval, reciprocal counting requires the determination of the start of a signal cycle and the start of the next signal cycle (or some other known signal cycle (e.g., every ten signal cycles) and associating a timestamp with each of those events.
The timestamps for these signal cycle start times can be provided in terms of a count of the number of clock cycles of a timer clock signal (e.g., timer clock cycle 100) or a time equivalent to the timer clock cycle count (i.e., timer clock cycle 100 for a timer clock signal having a timer clock period of 100 ns is equivalent to a time of 10 ms (100 timer clock cycles multiplied by 100 ns/timer clock cycle)). If the timestamps a provided in terms of the number of timer clock cycles, the number of timer clock cycles that occurred during the signal cycle can be multiplied by the timer clock period to determine the time interval. If the timestamps are provided as times equivalent to the timer clock cycle count, the time interval can be determined by subtracting the first timestamp from the second timestamp. Given this dependence on the timer clock cycle count, the accuracy of a conventional reciprocal counter is dependent on the speed of a timer clock. For example, if a timer clock is operating at 10 MHz (i.e., timer clock cycle occurs every 100 ns), the resolution of the reciprocal counter is 100 ns. This correlation between timer clock speed and resulting resolution is explained by way of the following illustrative example starting at t=0.
Assume that the first signal timing edge (e.g., a particular rising edge or falling edge that starts a signal cycle) for a signal cycle is detected at t=95 ns when the timer clock cycle count is equal to 001. Since the timer clock cycle count is equal to 001 from t=0 ns to 100 ns during the first timer clock period (i.e., until the second timer clock cycle occurs at 100 ns), regardless of when the first signal timing edge is detected during this first timer clock period, the timer clock cycle count will be equal to 001. Assume now that the second signal timing edge is detected at time=405 ns when the timer clock cycle count is equal to 005. Once again, since the timer clock cycle count is equal to 005 from t=400 ns to 500 ns during the fifth timer clock period, regardless of when the second signal timing edge of the signal is detected during this fifth timer clock period, the timer counter will be equal to 005. Accordingly in this example, the reciprocal counter has timestamped the first and second signal timing edges with the timer counts or times equivalent to the timer counts (i.e., a timer count of 001 is equivalent to a time of 100 ns and a timer count of 005 is equivalent to a time of 500 ns)
In order to determine the time interval (or period (T)) for this single cycle of the signal, the first timestamp (100 ns or timer clock cycle 001) is subtracted from the second timestamp (500 ns or timer clock cycle 005) to provide a time interval of 400 ns. This time interval for a single signal cycle is equivalent to a frequency of 2.5 MHz. As shown in this example, however, the actual time interval for the signal cycle (from 95 ns to 405 ns) was only 310 ns rather than 400 ns, representing an error of 90 ns between the determined time interval (400 ns=2.50 MHz) and the actual time interval (310 ns=3.23 MHZ).
This error can be reduced by the use of a faster timer clock, which would reduce the timer clock period and improve resolution. For example, if a timer clock was operating at 20 MHz instead of 10 MHz (i.e., each timer clock cycle has a period of 50 ns instead of 100 ns), the first signal timing edge is detected at t=95 ns when the timer clock cycle count is equal to 002 (second timer clock cycle) equivalent to a time of 100 ns, while the second signal timing edge is detected at time=405 ns when the timer clock cycle count is equal to 009 equivalent to a time of 450 ns. This would provide a determined time interval of 350 ns (seven timer clock cycles multiplied by the timer clock period (i.e., 50 ns)), which would reduce the error between the determined time interval (350 ns=2.86 MHz) and the actual time interval (310 ns=3.23 MHZ).
While increasing the speed of a timer clock improves the resolution of the reciprocal counter, this also increases the power consumption and resulting heat generation of the system. In systems that require battery power or cannot effectively dissipate the additional heat, such an increase in timer clock speed may not be an option. Furthermore, significant increases in timer clock speed require that the complementary electronics have the capacity to operate at these higher speeds, which can increase the cost of a system.
Given the disadvantages of increasing the speed of a timer clock to improve the resolution of a reciprocal counter, other systems have sought to improve system resolution without necessarily increasing the speed of a timer clock through the use of delay lines. However, in these systems, the delay lines are attached to a timer clock, which typically operates at significantly greater speeds than the signal that is being measured. Accordingly, while these delay line systems somewhat diminish the increase in power consumption that would be required by increasing timer clock speed, the required increase in the number of devices operating at a timer clock speed still results in an increase in power consumption, heat generation, and cost.
It would be advantageous to significantly improve the resolution of a reciprocal counter without having to significantly increase timer clock speed or power consumption.