There are several circumstances in which a circuit or electronic device may experience may experience voltages higher than the connected supply voltage. For example, a hot-swap is an operation to add or remove a circuit or electronic device from an already powered system, normally without disturbing the rest of the system. This may cause some I/O to connect to powered signals in the system before the device is connected to a power supply. In some applications, such as inter-integrated circuit (I2C) communication, coupling of integrated circuits (ICs) that run at different supply voltages can cause input/output (I/O) pads of the IC or device to connect to a higher voltage than a supply voltage of the IC or device, potentially damaging the device or causing excessive loading or leakage currents in some I/O. Such excessive current leakage through the I/O pad can adversely impact signals on the I2C bus. In addition, when a device is connected to a system and power to the system is turned on or turned off, there may be voltages on I/O pins of the device that are higher than the supply during either a turning-on transition, a turning-off transition, or when the power is stably off. Thus, a hot-swap or over-voltage tolerant circuit is desirable to enable the IC or device to be connected to a system, or to other ICs and devices, while the system is powered, without risk of damage to the IC or the system, without excessive leakage, and without interruption of communication.
One such circuit is illustrated in FIG. 1A. Referring to FIG. 1A, the hot-swap circuit 100 typically includes a pull-up p-channel metal-oxide-semiconductor field effect transistor (PMOS 102) formed in an n-well and coupled to the I/O pad 104, an n-well selection circuit 106, a sensing circuit 108, and a latch 110 configured to retain a state of the sensing circuit, the latch coupled to the sensing circuit and the n-well selection circuit through a PMOS drive circuit 112. The n-well node, labeled vpb_drvr in FIG. 1A, of the pull-up PMOS 102 is driven by PMOS transistors P1 and P2 in the n-well selection circuit 106 such that vpb_drvr is connected to either a supply voltage (Vcc) or a voltage applied to the pad (Vpad), depending on Vpad. Typically, vpb_drvr is also indirectly connected to a gate of the pull-up PMOS 102 through a gate drive 114. In certain non-I2C applications the gate drive 114 may be further connected to a control circuit to turn the pull-up PMOS on or off when it is not used.
FIG. 1B, illustrates the I/O pad voltage, n-well resistance and the latch state during example operation of the circuit of FIG. 1A. Referring to FIG. 1B, the I/O pad voltage may rise from a ground voltage (Vgnd) to Vcc−Vtp, where Vtp is a threshold voltage of the PMOS transistors P1 and P2. During this time sense transistor P3 is ON and sense transistor P4 is OFF, and the latch 110 is in a normal state, which forces the gate of transistor P1 to Vgnd, turning it ON. Transistor P2 is OFF because Vpad is lower than Vcc, and hence the n-well node, vpb_drvr, of the pull-up PMOS is connected to Vcc. During a second time period the I/O pad voltage is rising from Vcc−Vtp to Vcc+Vtp. Both sense transistors P3 and P4 are OFF while the latch 110 retains the normal state and drives gate of transistor P1 to Vgnd. Transistor P2 is OFF and hence vpb_drvr is connected to Vcc. During a third time period the I/O pad voltage is rising from Vcc+Vtp to an external voltage (Vext) coupled to the I/O pad 104 and then falling back to Vcc+Vtp. The sense transistor P4 turns ON while sense transistor P3 is OFF, which forces the latch 110 into a hot-swap state. The flipped latch 110 drives the gate of transistor P1 high turning it OFF, transistor P2 is automatically turned ON as the I/O pad 104 rises above transistor P2's gate voltage and hence vpb_drvr is connected to the I/O pad external voltage (Vext). Finally, in a fourth time period the pad voltage is falling first from Vcc+Vtp to Vcc−Vtp. Both sense transistors P3 and P4 are OFF. Latch 110 remains in the hot-swap state and drives gate of transistor P1 high turning it OFF, while transistor P2 is also automatically turned OFF, and hence vpb_drvr is neither connected to Vcc nor to the pad voltage (Vext). Thus, the n-well of the pull-up PMOS 102 floats when the I/O pad 104 is within a Vtp of Vcc as the pad voltage falls from a voltage above Vcc+Vtp. During this period in which the n-well of the pull-up PMOS 102 is floating, commonly called a dead-zone, the risk of latch-up and associated device malfunction and interruption in communication is high. As shown in the N-well drive resistance plot at the bottom of FIG. 1B, the resistance of the N-well connection varies with the pad voltage. When the resistance is high, the risk of latch-up is increased. Although the turn-on and turn-off of P1 and P2 has been described as changing abruptly at Vcc−Vtp and Vcc+Vtp, but in actual operation these changes will have a gradual transition and the effective on resistance of P1 and P2 will vary as the voltage varies.