With the increasing maturity of silicon-germanium (SiGe) process, radio-frequency (RF) circuit integration is becoming increasingly commonplace. Such modules as RF receiver, RF transmitter, switch and so on have a tendency towards integration. Therefore, both a low noise amplifier (LNA) for amplifying received signals and a power amplifier (PA) for amplifying the signals to be transmitted should be fabricated on an identical chip, which requires that, on the same SiGe process platform, high-voltage SiGe HBTs with different high breakdown voltages can be designed by merely changing the layout, so as to meet the requirements of various amplifiers. In the manufacturing process of an existing high-voltage SiGe HBT, buried layers, which are called pseudo buried layers, are formed at the bottom of field oxide regions on both sides of an active area; the pseudo buried layers are heavily N-doped; deep hole contacts formed by etching the field oxide regions are directly connected to the pseudo buried layers to pick up the collector region. In the case that a CMOS process is not used, a high-voltage resistant device can be easily manufactured, as few thermal processes are involved. However, once the SiGe HBT is integrated with a CMOS device, thermal processes of the CMOS process will cause the diffusion of the pseudo buried layers, which will lead to a great drop in the breakdown voltage of the device.
There are some methods capable of increasing the breakdown voltage of the device shown as follows: 1) controlling the thermal processes of CMOS; 2) controlling the doping concentration of the collector region of a transistor; 3) performing implantation at positions far from the collector region to form pseudo buried layers far from the collector region, in this way, the diffusion of the pseudo buried layers into the collector region during thermal processes will be reduced with the increase of the distance between the pseudo buried layers and the collector region. However, the above method 3) has a negative effect that the saturation voltage drop of the device will be significantly large, because although the amount of impurities that diffuse into the collector region decreases after the pseudo buried layers are arranged at farther positions, at the same time, the length of the current paths is increased and moreover, as the doping concentration of the lengthened paths are not very high, a large increase in device resistance is resulted.