The invention relates to semiconductor devices and methods of manufacturing the semiconductor devices, and in particular relates to a semiconductor device having a thin film transistor and the method of manufacturing the semiconductor device.
As further integration of a semiconductor device and a reduction in size of a semiconductor device proceed, a soft error may be caused due to storing information into a memory node portion in a volatile memory referred to as an SRAM (Static Random Access Memory). To deal with this problem, Japanese Patent Laid-Open No. 2004-79696 (Patent Document 1) and Japanese Patent Laid-Open No. 2004-200598 (Patent Document 2) disclose a semiconductor device in which a capacitor as a DRAM (Dynamic Random Access Memory) is added to an SRAM circuit that uses a thin film transistor called a TFT (Thin Film Transistor) as a load transistor. In each of Patent Document 1 and Patent Document 2, a charge is retained in the capacitor in place of a memory node portion, and the potential of the capacitor is held by the flip-flop circuit constituting the SRAM circuit. For this reason, the occurrence of a soft error due to alpha rays can be restrained as compared with an SRAM in which a charge is stored in the memory node portion. Furthermore, because at least a part of the flip-flop circuit is provided above a bit line, the semiconductor device can be miniaturized.
Japanese Patent Laid-Open No. 2001-68548 (Patent Document 3) discloses a semiconductor device in which a power wiring and a signal wiring constituted by copper are formed from the same layer. The semiconductor device can reduce the signal delay in the signal wiring without reducing the wiring capacitance of the power wiring. According to Patent Document 3, the lower portion of the power wiring is embedded into an insulating film having a dielectric constant higher than an insulating film in which the power wiring is formed, so that the wiring capacitance of the power wiring is increased.