Modern high frequency communication systems such as transceivers or equipments for testing such systems often include frequency converter or synthesizer circuits which can perform a variety of functions. For instance, such circuitry is utilized in transceivers or test equipment to provide a selected local oscillator signal when such equipment is operated in a “receive mode” or to provide an output signal having a selected stable reference frequency for converting the frequencies of a modulated signal when such equipment is operated in a “transmit mode” or as a signal generator. Further, frequency synthesizer systems are required in signal generators in order to adequately test high performance RF systems and components.
A frequency synthesizer is an apparatus which generates an output signal having a frequency which is a multiple of a reference frequency. The accuracy of the output signal frequency is typically determined by the accuracy and stability of the reference frequency source. A common type of frequency synthesizer uses a phase-locked loop (PLL) to provide an output signal having a selectable, precise and stable frequency. A PLL typically includes a phase detector, a voltage-controlled oscillator (VCO) and, a feedback path arranged so that the phase of the VCO output is forced to be synchronous with the phase of the input reference frequency.
The complexity of PLLs can give rise to more complex phase noise profiles, can compromise frequency settling time, or generate spurious signals. Phase noise may be defined as is rapid, short-term, random fluctuations in the phase of a wave, caused by time domain instabilities. Spurious signals are any outputs in the spectrum of a source that are neither part of the carrier, nor its harmonic and they may be discreet or bands of frequencies. Such noise and spurious signals are problematic for synthesizers. In the frequency domain, an ideal carrier would appear as an infinitesimally thin line, the typical carrier however, will have phase noise or skirts whose amplitudes generally follow 1/f distribution with increasing frequencies. These skirts are the envelope of side bands due to modulations of the carrier, are random in both frequency and amplitude, and are caused by various phenomena relating to the physics of the particular oscillator. Spurious signals are equally problematic for frequency synthesizers. For instance, spurious signals with amplitude 10% of true phase calibration signal may introduce errors in determination of group delays up to 50 psec. Unfortunately, cases of such strong spurious signals are quite prevalent in frequency synthesizers.
Frequently, performance compromises must be made in the design of synthesizers, resulting in less than optimum performance of one or more frequency synthesizer characteristics. For instance, current frequency synthesizer noise reduction techniques are directed toward single frequency noise reduction, lack coherent spurious signals, or do not exploit the coherent spurious nature of the frequency synthesizer architecture if present. Disadvantageously, this creates a shortcoming in frequency synthesizers. For instance, in order to provide a frequency synthesizer having a small step size between adjacent output frequencies, a very low reference frequency is required. Using a very low reference frequency, however, limits the frequency range and extends the time required for the PLL to settle (or lock) once a new frequency has been selected.
Referring to FIG. 1, a prior art synthesizer 100 is shown. Synthesizer includes at least one phase locked loop which includes an input reference frequency 102, a modulated fractional divider (MFD) 104, a phase detector 106, a voltage controlled oscillator (VCO) 108, a mixer 110 and a divider 112. The phase detector 106 typically has an output coupled through a loop filter to control the frequency of the VCO 108. The output of the VCO 108 is fed back through a circuit, such as a divide by N circuit 112, to a first input of the phase detector 106. The frequency of the VCO 108 output signal is changed in steps by changing “N” of the divide-by-N circuit 112 in a known manner. At phase-lock, a synthesized output frequency 114 is proportional to the input frequency 102. A constant reference frequency signal is applied to a second input of the phase detector 106 by a crystal oscillator, for instance. A modulated fractional divider is utilized to provide fine frequency steps. However, this prior art circuitry is capable of providing non-coherent spurious signals on the modulated fractional divider.
Referring to FIG. 2, an additional prior art synthesizer is shown. Synthesizer 200 includes a single frequency source as an input reference frequency, a first divider 204, a phase detector 206, a VCO 208, a mixer 210 and a second divider 212. By utilizing a divider circuit 212 in the VCO feedback path and selectably controlling the division ratio, a variable frequency can be provided at the output of the frequency synthesizer. In this manner, the VCO output frequency 214 is divided by the selectable divisor, and the VCO output frequency is an exact multiple of the reference frequency. If the divisor N is an integer, the smallest increment in the VCO output frequency value is necessarily equal to the magnitude of the reference frequency itself. This technique provides coherent spurious content, however, it is only useful for single frequency applications.
Consequently, it would be advantageous if a method and system existed which provided an improved frequency synthesizer that reduces phase noise and spurious signals for multiple frequencies.