The present invention relates to input buffers, and more particularly to an input buffer for a digital integrated circuit of FETs which can receive ECL level signals.
As the input buffer of a digital integrated circuit constructed of FETs (field effect transistors), a circuit as shown in FIG. 1 has heretofore been employed by way of example.
This circuit consists of an inverter which is composed of normally "on" type FETs Q.sub.3 and Q.sub.4, and a level shifting circuit which is composed of diodes D and a resistor R. The level shifting circuit shifts an input level V.sub.in thereby to convert it into a voltage level capable of switching the inverter of the succeeding stage, that is, a transition logic level.
FIG. 2 is a graph of transfer characteristics in FIG. 1 in which a, b and c indicate the curves in the cases where the ratio W.sub.4 /W.sub.3 between the gate widths of the FETs Q.sub.3 and Q.sub.4 is set at 5, 13 and 50, respectively. In this figure, a case is illustrated where a supply voltage V.sub.SS is set at -2 V, the threshold voltage V.sub.T of the FET at -1 V and the level shift magnitude V.sub.S of of the diodes D at 1.55 V.
As illustrated in FIG. 2, with the input buffer of FIG. 1, an input logic swing required for completely switching the output becomes smaller as the ratio between the gate width W.sub.4 of the FET Q.sub.4 and that W.sub.3 of the FET Q.sub.3 becomes greater. Here, assuming that the input signal is of an ECL (Emitter Coupled Logic) level, the output of the inverter needs to be completely switched in a range of signal levels from -1.45 V to -1.15 V. It is seen from FIG. 2 that W.sub.4 /W.sub.3 needs to be at least 13 (i.e. curve b) in order to satisfy the above specification.
In this regard, the input buffer of FIG. 1 has the following two disadvantages:
(1) In a case where the threshold voltage V.sub.T of the FETs has fluctuated from the desired design level due to dispersions in manufacturing conditions etc., the input logic swing necessary for reliably switching the output increases.
(2) Also in a case where the supply voltage V.sub.SS has fluctuated, the input logic swing necessary for reliably switching the output increases.
FIG. 3 is a graph of transfer characteristics in the case where the threshold voltage V.sub.T has fluctuated in the circuit of FIG. 1, while FIG. 4 is a graph of transfer characteristics in the case where the supply voltage V.sub.SS has fluctuated in the same. In FIGS. 3 and 4, a curve d indicates the transfer characteristic obtained for design values of a threshold voltage V.sub.T =-1 V and a supply voltage V.sub.SS =-2 V in the case of W.sub.4 /W.sub.3 =13, and it is the same curve as that b in FIG. 2. Curves e and f in FIG. 3 indicate the transfer characteristics obtained when the supply voltage V.sub.SS is at a design value (V.sub.SS =-2 V) and the threshold voltage V.sub.T has become -1.3 V and -0.7 V, respectively. Curves g and h in FIG. 4 indicate the transfer characteristics obtained when the threshold voltage V.sub.T is at a design value (V.sub.T =-1 V) and the supply voltage V.sub.SS has become -2.2 V and -1.8 V, respectively. In any case, the input necessary for reliably switching the output is about -1.6 V as a low level and about -0.9 V as a high level, that is, the logic swing becomes about 0.7 V.
This value is approximately double the input logic swing 0.3 V requirement which the FIG. 1 circuit was originally designed to meet in the absence of any fluctuation, and this becomes a serious problem in practical circuit operation. The value of 0.7 V corresponds to the addition of about 0.4 V to the required 0.3 V logic swing range. This 0.4 V addition is the width of the change of the input logic threshold value of the inverter, the change being attributed to the fluctuation of the threshold voltage V.sub.T or the supply voltage V.sub.SS. In a case where the fluctuations of the threshold voltage V.sub.T and the supply voltage V.sub.SS have simultaneously occurred, an additional 0.4 V is added to the logic swing required for complete switching. Therefore, the input logic swing becomes 1.1 V. When the gate width ratio W.sub.4 /W.sub.3 is set to be smaller, the influence of the fluctuation of the threshold voltage V.sub.T can be somewhat mitigated. However, even in this case, the input logic swing originally required increases as stated before. It can accordingly be said that, in the presence of manufacturing dispersions or supply voltage fluctuation, a signal of the ECL level cannot satisfactorily be received and operated on by the circuit of FIG. 1.
Although the case of using the normally "on" type FETs has thus far been described, a similar problem arises in a circuit employing normally "off" type FETs.