New generations of CMOS IC processes provide faster transistors with greater circuit density; however, many traditional analog characteristics are sacrificed. Consequently, circuit designers have pursued new mixed-signal circuit architectures that take advantage of digital circuits to augment analog processing of signals. In particular, digital phase locked loops (PLLs) have benefited from the use of time, rather than voltage or current, as a signal domain.
A time-to-digital converter (TDC) is used to quantify time information of a signal event with respect to a reference event. Traditionally, TDCs have been used in applications in experimental physics and laser range finding. More recently, fully integrated TDCs have been investigated as a core building block for a variety of clocking and phase-locked loop systems and applications.
A typical TDC operates as shown in FIG. 1. The time difference tin to be measured is defined by the difference between a reference signal edge occurring at a time tref and an event signal edge occurring at a time tevent. To obtain a quantitative measurement of tin, time is segmented into discrete steps according to the timing resolution tres of the TDC. A measured time difference tout is provided by the TDC to approximate tin with some quantization error tq, where tq=tout−tin.
A TDC 10 is commonly implemented with standard digital circuit elements as shown in FIG. 2. The reference signal is propagated through a serial configuration of delay stages 14A to 14J (generally 14, only three shown for clarity). In time, the reference signal edge moves from left to right in the figure, from the first delay stage 14A to the last delay stage 14J. At a rising event signal edge, the states of all the delay elements 14 are clocked into respective serial registers 18A to 18 K (generally 18). The output time tout of the TDC 10 is determined according to the product of a positive integer output Nout and the delay tres of a single delay stage 14. Thus the minimum resolution of the TDC 10 is limited by process technology. The quantization error of the TDC has a substantially white spectrum although practical applications can exhibit quantization noise with significant tone content for certain input signals.
A vernier delay TDC is based on a variation of the conventional TDC structure and achieves an improvement in the resolution of the TDC. An example of a vernier delay TDC 20 is shown in FIG. 3. The reference signal edge propagates through the serial configuration of delay elements 14. The event signal edge propagates through a separate serial configuration of delay elements 22A to 22J (generally 22). The delay tdelay caused by each delay element 14 in the propagation path for the reference signal edge is slightly greater by a time toffset than the delay of each delay element 22 in the propagation path for the event signal edge. Thus, if the reference signal edge occurs first and the two edges propagate through their respective delay elements 14 and 22, the event signal edge slowly catches up to the reference signal edge. Ideally, the vernier delay TDC 20 improves the time resolution by tdelay/toffset. Mismatches within the propagation paths and thermal noise contributed by the registers 18 limits the minimum TDC resolution. In addition, the number of delay elements 14 and 22 required for a maximum acceptable input time difference increases compared to a standard TDC, thereby reducing throughput and making the vernier delay TDC 20 unsuitable for applications requiring a large dynamic range.
The noise performance of a TDC can be an obstacle for meeting the noise requirements of many applications, including applications based on current wireless communications standards. To reduce the effect of a high TDC resolution, the bandwidth of a PLL can be reduced. The reduced bandwidth sacrifices utility such as the option to modulate a data stream within the PLL that is not otherwise possible without a significant reduction in the TDC resolution. Improved TDC resolution is not likely to be realized soon through processing technology advances and the vernier delay TDC 20 is not a practical option for many applications due to its inherent circuit complexity.
What is needed is a TDC that overcomes the problems and limitations described above. The present invention satisfies this need and provides additional advantages.