With the development in the semiconductor manufacturing industry, integrated circuits with better performance and more powerful functions require greater element density, and sizes of and spaces between components have to be further scaled down (which has already reached the nanometer level nowadays). Accordingly, various micro effects come up along with scaling down of sizes of semiconductor devices. In order to meet the demands in developing semiconductor devices, persons skilled in the art are dedicated to exploring new manufacturing processes.
Silicon-On-Insulator (SOI) devices exhibit good feature of dielectric isolation, thus integrated circuits made of SOI exhibits merits such as small parasitic capacitance, high integration, fast operation speed, simple manufacturing process and alleviated short-channel effect. An SOI substrate usually consists of three layers of main structures, which are respectively a body silicon layer, a Buried Oxide layer (BOX layer) on the body silicon layer, and an SOI layer lying on the BOX layer, the material of which usually is mono-crystalline silicon.
In the prior art, processes of recessed source/drain regions are employed in manufacturing a semiconductor device with aforesaid SOI substrate, such as the semiconductor structure shown in FIG. 1. A specific method for forming the structure shown in FIG. 1 is as follow: etching an SOI substrate first, specifically, etching an SOI layer 10 and a BOX layer 11 between a gate structure 15 and isolation regions of the SOI substrate, so as to form a trench extending to the BOX layer; then, filling a semiconductor material into the trench to form a semiconductor layer 14; and finally forming source/drain regions within the semiconductor layer 14.
However, aforesaid semiconductor structure has following defects; as shown in FIG. 1, when a dielectric layer 17 is etched to form contact vias to the source/drain regions in subsequent processes, high controlling capability for etching is required, because the source/drain regions on the semiconductor layer 14 have to be aligned in one aspect, and the gate structure 15 should be protected from damage in another aspect. For a semiconductor structure with a metal gate, capacitances exist between the metal gate and the contact vias, which accordingly affects the performance of the semiconductor device. At formation of the contact vias to the source/drain regions, scaled down device size and limited contact area between bottoms of the contact vias and the source/drain regions cause relatively large contact resistance, which shall also affect the performance of the semiconductor device.