1. Field of the Invention
The invention relates in general to a memory, and more particularly to a memory cell of a memory using array cells to form bit line transistors (BLTs).
2. Description of the Related Art
FIG. 1 (Prior Art) is an equivalent circuit diagram showing a portion of a memory cell array 10. Referring to FIG. 1, the memory cell array 10 includes a memory cell 150, bit line transistors (BLTs) 131 to 138, BLT control lines 141 to 148, word lines 161 and 162, a global word line 112, a global word line 114, a global word line 116, a global word line 118 and local bit lines 121 to 128. The bit line transistors 131 to 138 control to select which local bit line for the programming operation, and the bit line transistors 131 to 138 are respectively controlled by the BLT control lines 141 to 148.
However, the conventional bit line transistor is a metal-oxide semiconductor (MOS) transistor, so the circuit layout area of the of the bit line transistor cannot be reduced due to the limitations of the contact holes and the manufacturing processes of the MOS transistor.