Delay-locked loops (DLLs) are often employed in integrated circuit devices to change the phase of a reference clock signal. In operation, a delay-locked loop generates an output clock signal based on an input clock signal to the delay-locked loop. The delay-locked loop generates an error signal by comparing the phase of the input clock signal to the phase of an output clock signal. Additionally, the delay-locked loop integrates the error signal and controls the delay of the input clock signal through a chain of delay elements based on the integrated error signal.
Phase-locked loops (PLLs) are also employed in integrated circuit devices to change the phase of a reference clock signal. Unlike a delay-locked loop, a phase-locked loop includes a voltage-controller oscillator. In operation, the phase-locked loop generates an error signal by comparing the phase of an oscillating clock signal generated by the voltage controlled oscillator with the phase of an input clock signal to the phase-locked loop. Additionally, the phase-lock loop generates a control signal for the voltage controlled oscillator by integrating the error signal. Because the control signal controls the frequency of the oscillating signal generated by the voltage controlled oscillator, the voltage controlled oscillator performs an integration in the phase-locked loop. Generally, a phase-locked loop performs two integrations but a delay-locked loop performs only a single integration. Thus the phase-locked loop is a second order feedback system while the delay locked loop is a first order feedback system.
In integrated circuit implementations, a delay-locked loop adjusts the error signal generated in a feedback loop of the delay-locked loop to compensate for voltage, temperature, and process variations across the integrated circuit. Because voltage, temperature, and process variations are generally independent of each other in an integrated circuit, the error signal generated by the delay-locked loop may not adjust to all these variations quickly enough to achieve phase-lock of the output clock signal to the input clock signal or have enough range to cover the variation.