Many integrated circuits contain multi-layer electrical interconnect structures to provide electrical signals to logical elements such as transistors located on a semiconductor substrate. The interconnect structures often contain interconnect lines which are spaced apart in a nearly coplanar arrangement within a dielectric material that insulates the lines from one another. Selected connections between interconnect lines on different levels are made by vias formed through the insulating material.
The interconnect lines are often made of highly conductive metals or alloys. Copper has become a widely used material due, in part, to its low electrical resistance compared to other metals. Typically, the copper is electroplated in the damascene process. A barrier layer is used to prevent diffusion of the copper into dielectric layers. Chemical mechanical polishing (CMP) removes the copper and barrier layers from the upper surface of the dielectric, leaving the barrier layer and copper inlaid within the trenches and vias. A cladding metal, in some cases, is selectively deposited over the copper to seal it and to provide an etchant stop for additional interconnect layers.
Problems associated with forming the cladding are discussed conjunction with FIG. 1.