Dielectric layers with low dielectric constant, or so-called low-k and extremely low-k dielectric layers are becoming an increasingly popular material in the manufacture of semiconductor devices. Low-k dielectric materials are particularly valuable as device geometries shrink well below the micron range, with gate lengths approaching 90 nm, 65 nm, 45 nm, and below. This is because dielectric layers are becoming commensurately thinner, as device critical dimensions become smaller. Power is consumed unnecessarily and device switching speed is degraded by stray capacitance between conductors and interconnects. Low-k and extremely low-k dielectrics reduce capacitance between conductors and, hence, alleviate some of these concerns.
While low-k dielectric materials provide improved electrical characteristics, they generally suffer from poor mechanical strength and adhesion. This is due, at least in significant part, to the fact that low-k dielectric materials are typically quite porous, i.e., composed in significant part of air trapped within the matrix of the dielectric material. Air, having a dielectric constant of 1 is an excellent dielectric material, but obviously provides quite poor mechanical strength. The more porous a material is, i.e., the more pores contained within its matrix, the lower its dielectric constant, but also the lower its mechanical strength.
Low-k dielectrics are particularly well suited as inter-metal dielectrics (IMDs), which are typically employed as an insulator layer in which conductive interconnects are formed. Numerous process steps in the formation of the conductive interconnects, however, place the low-k dielectric material under substantial mechanical stress. The result can be significant degradation to not only the mechanical properties of the dielectric layer, but also the electrical properties. Back-end-of-line processes such as etching, ashing, wet cleaning, and the like, can degrade the low-k dielectric. Processes related to conventional damascene and dual damascene, particularly chemical mechanical polishing (CMP) can also significantly degrade the low-k dielectrics.
FIGS. 1a through 1c illustrate one manner in which semiconductor processes can degrade a low-k dielectric material in a deleterious manner. In FIG. 1a, a porous low-k dielectric material 4 has been formed atop a substrate 2. A mask 6 has been formed atop low-k dielectric material 4 and patterned in a conventional manner, leaving a portion of low-k dielectric material 4 exposed. As shown in FIG. 1a, a fluorine-containing etchant is used to etch an opening 8 in low-k dielectric layer 4. Because of the presence of pores in low-k dielectric material 4 (which, as explained above, give the material its low dielectric constant property) some fluorine species, illustrated schematically as 10, is adsorbed by low-k dielectric material 4 during the etch process and remains within the pores after the etch process has been completed. This process is also schematically illustrated via arrows 12, which represent fluorine species adsorbing into dielectric material 4.
In a subsequent process step, such as a rinse with distilled water as illustrated in FIG. 1b, hydrogen containing species and hydrogen ions 14 come in contact with low-k dielectric material 4 and with the fluorine species trapped within the pores of the material. Other process steps, such as a hydrogen containing plasma step can also deliver hydrogen to the fluorine trapped within low-k dielectric material 4. The hydrogen reacts with the fluorine, forming hydrofluoric acid, HF. The resulting hydrofluoric acid is an etchant and etches large voids 16 within the low-k dielectric material 4.
As illustrated in FIG. 1c, opening 8 in low-k dielectric material 4 is subsequently filled with a conductor 18 such as copper, typically in a conventional damascene process. The large voids 16 in low-k dielectric material 4 cause significant stress, which stress can lead to degraded circuit performance, increased electromigration in the conduct, and possibly an open circuit leading to device failure.
Another adverse consequence of the formation of large voids 16 in low-k dielectric layer 4 is the formation of grains of conductor 18 (typically copper, but alternatively titanium, tantalum, titanium nitride, tantalum nitride, aluminum, or the like) in the low-k dielectric material, such as illustrated in FIG. 1d. These grains of conductor 18 reduce the insulative properties of the material and could, in some circumstances, result in a short circuit between adjacent conductors, again resulting in device failure.
What is needed then is a method for forming a low-k dielectric material that is less sensitive to subsequent processing steps, while still maintaining its desirable electrical properties.