1. Field of the Invention
Embodiments relate to a semiconductor device and, more particularly, to a semiconductor device capable of improving an overlay margin of a contact structure.
2. Description of the Related Art
A semiconductor device includes multi-layer patterns formed on a semiconductor substrate and an insulating layer formed to provide insulation between the multi-layer patterns. A first pattern over the insulating layer and a second pattern under the insulating layer are electrically coupled through a contact structure formed to penetrate the insulating layer. In order to electrically couple the first pattern and the second pattern through the contact structure, an overlay margin of the contact structure must be secured. With an increase of a degree of integration of semiconductor devices, however, it is difficult to secure the overlay margin of the contact structure because an interval between the patterns is narrowed.
The cell array of a NAND flash memory device, for example, includes isolation regions in which trenches or isolation layers are formed, and active regions isolated from each other with the isolation region interposed therebetween. The isolation regions and the active regions are alternately disposed in parallel. Furthermore, drain select lines and source select lines are formed to cross the active regions, and a plurality of word lines is formed between the drain select line and the source select line. A junction is formed within the active region between the drain select lines, between the source select lines, between the word lines, between the drain select line and the word line, and between the source select line and the word line.
The junction formed between the drain select lines becomes a drain region, and the junction formed between the source select lines becomes a source region. Drain contact plugs are formed over the respective drain regions, and source contact lines are formed over the source regions. Furthermore, bit lines are formed over the respective drain contact plugs disposed in a same direction as the active regions.
The bit lines have to overlay on the respective drain contact plugs, and the drain contact plugs have to overlay on the respective drain regions. Thus, the bit lines can be electrically coupled to drains through the drain contact plugs. However, there is a problem in that it is difficult to secure the overlay margin of a contact structure, such as the drain contact plug, because an interval between the drain regions is narrowed according to an increase of the degree of integration of the semiconductor devices.