1. Field of Invention
The present invention relates to preparing FBEOL (FAR-BACK-END-OF-LINE) copper metallizations for use in semiconductors without relying on additional Al-wirebond pads by: a process of probing, bonding, and fusing with only one patterning step for the final passivation opening; or a process of probing, bonding, fusing and flip chip bumping with two patterning stepsxe2x80x94wherein both processes eliminate the Al-via+Al-pad patterning.
2. Description of the Related Art
It is known in semi-conductor manufacturing that a fabricated integrated circuit (IC) device is assembled into a package for use on a printed circuit board as part of a larger circuit. For leads of the package to make electrical contact with the bonding pads of the fabricated IC device, a metal bond is formed to make a connection between the bonding pad of the IC device and a lead extending to the package lead frame, or a solder ball connection to a ceramic or polymeric chip carrier.
Historically, Al and Al alloys are used as conventional chip wiring materials. However, it is desirous to replace Al wiring material with Cu and Cu alloys since Cu wiring would provide improved chip performance and superior reliability compared to Al and alloys of Al. Nevertheless, the packaging of IC devices utilizing copper wiring presents a considerable number of technical issues and challenges related to the reaction of copper with material used in the solder-ball process and/or the susceptibility of copper to attack and corrosion.
Current FEOL or BEOL practices for Cu metallization continue to rely on additional Al-wirebond pads. This reliance means that when currently preparing FEOL or BEOL processes for Cu metallization, additional patterning steps for Al-via to Cu Al-pad patterning is required, in addition to the opening of the final passivation.
U.S. Pat. No. 6,187,680 disclose a method for creating aluminum wirebond pad on a copper BEOL. The process comprises:
(a) forming a passivating layer on an integrated circuit (IC) semiconductor wafer containing Cu wiring embedded therein;
(b) forming terminal via openings through the passivation layer to expose the Cu wiring;
(c) forming a barrier layer at least over the exposed Cu wiring, on the side walls of the terminal via openings and on regions of the barrier layer near the terminal via openings;
(d) forming an Al stack on the barrier layer at least in the terminal via openings and on regions of the barrier layer near the terminal via openings;
(e) patterning and etching the Al stack and the barrier layer;
(f) forming a second passivating layer over the patterned Al stack; and
(g) providing second openings in the second passivating layer so as to expose regions of the patterned Al stack located on top of the Cu wiring whereby the Cu wiring is protected from environmental exposure or attack by etching chemistries and from the problem of Cu-Al intermixing.
An integrated pad and fuse structure for planar copper metallurgy is disclosed in U.S. Pat. No. 5,795,819. The method of making the interconnection structure for the semiconductor circuit comprises:
providing a substrate having coplanar damascene non-self passivating conductors embedded in a first insulator defining a first electrical interconnect layer;
forming a second electrical interconnect layer comprising coplanar self-passivating conductors in a second insulator, the second electrical interconnect layer over-lying the first electrical interconnect layer and the second interconnect self-passivating conductors contacting the non-self passivating conductors; and
depositing a final passivation layer over the second electrical interconnect layer.
One of the non-self passivating conductors forms part of a Controlled, Collapse Chip Connection (C4) barrier structure, the method further comprising the steps of:
etching the final passivation layer above the C4 barrier structure; and
depositing pad limiting and C4 metallurgies.
U.S. Pat. No. 6,054,380 disclose a method an apparatus for integrating low dielectric constant materials into a multilevel metallization and interconnect structure. The method comprises:
forming a metal line upon a surface of a substrate, where the metal line has a top surface and sidewalls;
depositing a barrier layer over the metal line and the surface of said substrate;
removing a portion of the barrier layer where the barrier layer remains deposited on at least the sidewalls of the metal line;
depositing a first insulative layer over said metal line, the surface of the substrate and the barrier layer, where the insulative layer is a material that, but for the barrier layer protecting the sidewalls of the metal line, would react with a material of the same metal line;
depositing a second insulative layer over the first insulative layer; and
forming a via that contacts a top surface of the metal line.
There is a need in the art of preparing FEOL and BEOL processes in which Cu metallizations still rely on additional Al-wire bond pads to prepare an improvement of FBEOL structures that eliminate the additional patterning steps normally required for Al-via to Cu and Al-wire bond pads, in addition to the opening step required for final passivation.
One object of the present invention is to provide a process for fabricating a semiconductor device of a Cu far-back-end-of-the-line (FBEOL) structure comprising Cu metallizations wherein probing, bonding and fusing is accomplished with only one patterning step for the final passivation opening.
Another object of the present invention is to provide a process for fabricating a semiconductor device of a Cu far-back-end-of-the-line (FBEOL) structure comprising Cu metallization wherein probing, bonding, and fusing is accomplished together with flip chip bumping with two patterning steps.
A further object of the present invention is to provide a process for preparing Cu far-back-end-of-the-line (FBEOL) structures of Cu metallizations that eliminate the Al-via+Al-pad patterning.