With developments of the semiconductor structure manufacturing technology, integrated circuits with better performance and more powerful functions require greater element density, and sizes of elements and spacing among elements need to be further downscaled; accordingly, lithography process faces greater demand and challenges at formation of semiconductor structures. In traditional processes, steps for forming metal interconnect liners include: firstly, forming a lithographical pattern for wires on an insulating material via once-for-all lithography process; next, etching the insulating layer to expose interconnect wires on the base layer, such that deep trenches are engraved; finally, filling metal into the deep trenches through depositing or electroplating process, and then forming metal interconnect liners, which are individually isolated and insulated, by means of chemical mechanical polish (CMP). However, it is noteworthy that in each layer of the metal interconnect liners, there are many collinear interconnect wires that have the same critical size and spacing. Along with further downscaling of feature sizes, chip area also shrinks significantly; consequently, the traditional process for manufacturing interconnect wires needs to be further modified so as to satisfy requirements in development of technologies, for example, reducing distance between ends of collinear interconnect wires at the meantime of suppressing short-circuit problems that may happen to interconnect wires due to small spacing among metal interconnect liners.