1. Field of the Invention
The present invention relates to the field of integrated circuits. More particularly, the present invention relates to interfacing integrated circuits to busses and circuits having higher voltage ranges.
2. Art Background
To achieve greater transistor densities and speeds for integrated circuits, circuits designers are reducing the physical dimensions of the transistors fabricated on the integrated circuits. Greater transistor densities enable implementation of greater functionality in an integrated circuit. However, as the physical dimensions of the transistors of an integrated circuit decreases, the supply voltage for the integrated circuit correspondingly decreases.
For example, metal oxide semi-conductor (MOS) transistors contained on newer generation high density integrated circuits are fabricated with smaller channel lengths than MOS transistors on older lower density integrated circuits. The gate oxides layers of the MOS transistors are reduced in width in accordance with the reduced channel length. However, the thinner gate oxide layers of the newer generation integrated circuits cannot withstand the high voltage levels of prior generations having thicker gate oxide layers.
As a consequence, the newer generation MOS integrated circuits operate with lower supply voltages than previous generations. For example, many newer generation MOS integrated circuits operate with a 3.3 V supply voltage rather than a 5 V supply voltage common in prior generations.
Nevertheless, in many applications an integrated circuit operating with a low supply voltage must interface with devices and buses operating at higher voltages. If a low voltage integrated circuit is coupled to a high voltage environment, the thin gate oxide layers of the low voltage MOS transistors gradually deteriorate. The gradual deterioration of the gate oxide layers leads to unreliability and ultimate failure of the integrated circuit.
Referring briefly to FIG. 1, a typical prior art tri-state input/output circuit for a pad of an integrated circuit is illustrated. An output data signal 101 is coupled to the gates of a transistor Q10 and a transistor Q12. An output enabled bar signal (OEB) 104 is coupled to control the gates of transistors Q11 and Q15. An output enable (OE) 105 is coupled to control the gates of transistors Q13 and Q14. The output circuit has a pull-up transistor Q16 and a pull-down transistor Q17. The n-well 106 of the transistor Q16 is coupled to the supply voltage VCC. The input circuit is comprised of a pull-up transistor Q18 and a pull-down transistor Q19.
For the prior art circuit to function properly, the supply voltage VCC must be greater than or equal to the voltage at an output pad 102, and the voltage at the output pad 102 must be greater than or equal to the voltage at a common node 107. Transistors contained in the prior art circuit are vulnerable to gate oxide layer breakdown if the output pad 102 is coupled to a bus or other circuit having higher voltage swings than the VCC supply voltage. The pull-up transistor Q18 and the pull-down transistor Q19 are vulnerable. Also, a conducting path exists from the drain of the transistor Q16, into the n-well 106 of the transistor Q16, and onto the VCC supply voltage node 100.
One prior technique of interfacing a low voltage integrated circuit to a high voltage environment is to employ an interface chip as a buffer between high and low voltage environments. However, such interface chips adds significant delays in signal transfer to and from the low voltage integrated circuit. Moreover, such an interface chip requires extra system board space and increases the cost of the system.
Another prior technique for interfacing low voltage devices to a high voltage environment is to fabricate high voltage transistors directly on the low voltage integrated circuit. The high voltage transistors interface directly to the high voltage environment, while protecting the low voltage transistors contained on the integrated circuit. However, such a solution requires extra process steps during integrated circuit fabrication in order to form the larger high voltage transistors. The extra steps increases the cost of fabrication and reduces the yield of the fabrication process. Also, such a solution requires that the integrated circuit chip be supplied with a higher voltage VCC for the outputs.
As will be described, the present invention is a voltage interfacing circuit for interfacing a low voltage integrated circuit to a high voltage environment, while implementing only low voltage transistors on the integrated circuit.