The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. An MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain electrodes. Complementary MOS (CMOS) devices include a plurality of N-channel MOS (NMOS) transistors and a plurality of P-channel (PMOS) transistors.
The fabrication of integrated circuits requires a large number of circuit elements, such as MOS transistors and the like, to be formed on a given chip area according to a specified circuit layout. CMOS technology is a commonly used technology for manufacturing complex circuitry due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed in and on a substrate including a crystalline semiconductor layer. An MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, includes so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the distance between the source and drain regions, which is also referred to as channel length. Therefore, reducing the feature sizes, and in particular the gate length, of field effect transistors has been an important design criterion.
In view of further enhancing performance of transistors, in addition to other advantages, the SOI (semiconductor- or silicon-on-insulator) architecture has continuously been gaining in importance for manufacturing MOS transistors due to their characteristic of a reduced parasitic capacitance of the PN junctions, thereby allowing higher switching speeds compared to bulk transistors. In SOI transistors, the semiconductor region, in which the drain and source regions as well as the channel region are located, also referred to as the body, is dielectrically encapsulated. Depending on the level of charge carriers in the channel region, which in turn is dependent upon the doping of the channel region, SOI transistors are either “partially-depleted” or “fully-depleted.”
In partially-depleted SOI transistors, during operation, charges can accumulate in the channel region by virtue of the remaining charge carriers therein and the fact that the channel is dielectrically encapsulated. This is referred to in the art as the “floating body” effect. The accumulated charges affect the current in the drain region of the transistor, resulting in drain current “kink” effect, i.e., an abnormal threshold voltage slope, low drain breakdown voltage, and drain current transient charges. For example, when an SOI MOSFET is operated at a large drain-to-source voltage, channel electrons cause substrate ionization near the drain end of the channel. Holes build up in the body of the device, raising the body potential and thereby raising the threshold voltage. This increases the MOSFET current causing a “kink” in the current vs. voltage (I-V) curves.
Utilization of this kink effect is beneficial in certain CMOS integrated circuit designs. For example, in low-power memory device applications, partially-depleted SOI transistors are often used to read and write from memory arrays. Heretofore, as noted above, the kink effect has only been observed in integrated circuits manufactured over a SOI substrate. However, due to processing restrictions and the increased expense of SOI substrates, it is often desirable to employ bulk silicon substrates. Thus, in the prior art, the selection of a bulk silicon substrate required the integrated circuit designer to forego the use of the “kink” effect, and the low-power benefits attendant therewith.
Accordingly, it is desirable to provide improved bulk silicon substrate integrated circuits and methods for fabricating the same that include partially-depleted transistors, which, in operation, exhibit the above-noted kink effect. Furthermore, it is desirable to provide bulk silicon substrate integrated circuits suitable for use in low-power memory device applications. Still further, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description of the disclosure and the appended claims, taken in conjunction with the accompanying drawings and this background of the disclosure.