The present invention relates to bubble memories, and more particularly to methods and apparatus for dealing with defective data storage loops in such memories.
Presently, the most popular architecture for a bubble memory includes a plurality of minor loops for storing bubbles representative of data therein. The bubbles are written into these minor loops and read therefrom in response to control signals applied to the memory. However, due to a variety of reasons a small number of the loops, such as five or ten percent, typically are defective. These defects may be due to flaws in the garnet film in which the bubbles are formed. They may also be due to permalloy defects arising from dust which enters the memory during the photolithographic stage of its fabrication. Defective data storage loops may also result from shorts between adjacent permalloy propagation elements which define the loops. A permalloy short creates a barrier to bubble propagation and renders a loop containing the short inoperable. Permalloy shorts occur randomly and are more of a problem when fabrication tolerances approach the resolution limit of the photolithography.
Thus, in order to construct high yield bubble memory chips, it is necessary to provide extra data storage loops on the chip. Then, during final chip testing, the defective loops are determined, and this information is subsequently used to control which loops are actually used to store bubbles.
In one prior art solution to the problem, defective loops have been identified to the user by stamping a defective loop map on each of the packages. The user has then encoded this information into a read only memory (ROM). The ROM was then used in conjunction with other control logic to mask out the defective loops during write or read operations.
U.S. Pat. No. 4,073,012 discloses a data relocation technique for overcoming the problem of defective minor loops in a bubble memory chip. It provides for coding the information to be stored in the memory by inserting zeros in the data stream so as to avoid the storage of meaningful bits into defective minor loops. A ROM on the chip is used to store positions of the defective minor loops.
U.S. Pat. No. 3,909,810 discloses a redundancy bubble memory system designed to operate with a plurality of data chips having a major-minor loop configuration where in some of the minor loops are defective. A plurality of data chips are interconnected to form a shift register and the data chips communicate with a flag chip of similar organization. Data is detected from the flag chip concurrently with the data chips to prevent any faulty loops on the data chips from being read and used for data storage.
U.S. Pat. No. 4,090,251 discloses another scheme for dealing with defective minor loops in a bubble memory chip. The first page written into the minor loops, where a page is defined as a common bit position in each of the plurality of minor loops, presents a series of magnetic domains and voids. The domains represent the operable minor loops and the voids represent the defective minor loops. The second page in the minor loops is a series of magnetic domains and voids separated into bytes of information which are representative of the loop numbers of defective minor loops on the chip. The third page in the minor loops is a repetition of the first page of data. Collectively, the three pages comprise the on-chip firmware which provides redundancy information. A microprocessor accesses and compares the redundancy patterns stored in the first three pages of the minor loops before it will read or write from the magnetic memory device.
More recently, some bubble memories have included a single extra loop on the chip for storing error map information therein. The user is thus able to read the error map from the memory during system initialization and to store the map in a random access memory (RAM). The RAM is then used in conjunction with control logic to mask out the defective loops during a write or read operation. Published German application No. 2804695 filed by Texas Instruments, Inc. is believed to be representative of this last mentioned approach. For a further discussion of the ROM and RAM approaches to error map storage see pages 35-36 of the book entitled Magnetic-Bubble Memory Technology by Hsu Chang, copyright 1978 and published by Marcel Dekker Inc.
All of the foregoing approaches have certain deficiencies. For example, with the ROM approach, each memory system requires unique parts. That is, the ROM in one memory system cannot be used as the ROM in another memory system because the bubble memory chips en each memory system have different defective minor loops. Furthermore, when a bubble memory chip in a memory system goes completely bad, due to aging for example, the replacement of the bubble memory chip also neccessitates the replacement of the ROM. Some of the foregoing approaches require too much redundancy information programming or too much additional circuitry.
One problem with the prior art bubble memory chips that provide an on chip error map storage loop is that they include no redundant error map loops. That is, they include only a single error map loop. Therefore, if that loop is defective, due to any of the above described processing problems, the entire chip must be discarded. Thus, the production yield of those bubble memory chips is undesirably low. This last mentioned problem has been overcome by my co-pending U.S. Patent application Ser. No. 3,651 filed Jan. 15, 1979 and now U.S. Pat. No. 4,228,522 and owned by the assignee of the present application. That application discloses a bubble memory including a plurality of minor loops for storing bubbles representative of information data therein, and a pair of minor loops for storing bubbles representative of an error map therein. The error map is selectively written into and read from only one loop of the pair. The other error map loop is redundant. Thus, if one of the error map loops is defective the entire chip need not be discarded since the other non-defective error map loop can then be utilized.
Heretofore the best approach for dealing with defective minor loops in a bubble memory chip has been to store the error map in an on chip error map loop. However, such an approach is not without its own shortcomings. One of its main disadvantages is that because the stream of bubbles representing the error map are moving in the on chip error map storage loop during rotations of the drive field there is a potential for data scrambling or data loss. To explain more fully, the error map is typically a stream of bubbles with interspersed no-bubble positions therebetween. The presence or absence of a buble in a given position is thus indicative of whether a particular loop is good or bad. This stream is stored in the error map storage loop and is frequently shorter than the length of that loop.
During rotations of the magnetic drive field the error map stream rotates about the error map loop. If the starting and stopping of the rotation of the drive field is not done in precise alignment with reference to the 360.degree. field of rotation, it is possible for magnetic bubbles in the error map to jump between adjacent permalloy propagation elements or collapse after the drive field has stopped rotating. When this happens the logic circuit associated with the bubble memory no longer knows where the error map starts and stops and therefore it cannot read the same. Therefore the logic circuit can no longer distinguish between good and defective minor loops and as a result the information stored in such minor loops is permanently lost.
Another problem with the on-chip error map loop approach is that a significannt amount of time is required to read the error map loop. Generally a leader in the form of a predetermined stream of bubble and no-bubble bit positions must be formed at the beginning of the error map. The leader is a code which tells the logic circuit that the error map follows. In order to read the leader and the error map from the storage loop a control conductor must be pulsed once for each bit position in the leader and the error map, one pulse for every revolution of the drive field. Thereafter the leader and the error map must be propagated to the detector and the logic circuit must search for and read the leader before the error map can be read. Thus, storage of the error map in a loop necessitates both serial access and a relatively large number of control conductor pulses. Parallel access to the error map would be preferable from a systems standpoint since it would take less time to access the error map and a single control conductor pulse could be utilized, resulting in less power consumption.