In the field of radio receivers, portable or mobile receivers for low-cost, high-speed data links ideally should be compact, fully-integrated and consume minimal DC power. Simple modulation schemes, such as wideband FSK, are currently of interest for wireless local and personal area communication, where low-complexity receivers capable of robust data transfers at rates up to 1 Gbit/s are required. Down-conversion and demodulation of data streams on the order of Gbit/s at baseband frequencies has proven difficult with conventional circuit techniques within a reasonable power constraint. Demodulation at IF, using a heterodyne approach, simplifies the implementation of a wideband receiver, thereby saving power and chip area. Low-complexity prior art FM receivers are efficient and compact when processing data rates on the order of 100 kbps. Their wideband performance for data rates approaching 1 Gbit/s, however, is limited, as the power consumption increases in proportion to the increase in data rate.
There is thus a need for a low power FM demodulator that is able to operate across a relatively wide frequency band, and more particularly, operate over a wide fractional bandwidth fc/Δf. The FM demodulator is preferably low cost, able to be constructed using commonly available semiconductor manufacturing processes and able to be integrated into a wide variety of system designs. In addition, the circuit should be able to accept a wideband input signal on the order of 2 to 10 GHz, have a fractional bandwidth greater than one and generate a demodulated output signal while minimizing power dissipation.