This invention relates generally to an apparatus and technique for testing of multi-level cells (MLC) in a memory storage device, and more particularly to a system that tests multi-level memory cells using a high bandwidth data path architecture.
A typical memory storage device may include a number of memory cells, each capable of storing a zero or one bit. Memory cells may be grouped together in a memory cell array containing a pattern of zeros and ones. Data bits can be loaded into memory cell arrays by identifying a word made up of memory cells in the array and storing the expected data bits into the memory cells of the word.
A memory cell may be tested by using an iterative test technique in which the memory cell is loaded with a reference zero or one bit pattern, the pattern read from the memory cell and compared against the reference value. Memory cell arrays similarly may be tested by loading reference sequences of ones and zeros into the array, reading the values stored in the memory cell array, and comparing them against the reference sequence. Exhaustive testing of a memory cell array including n memory cells requires testing all combinations of ones and zeros that may be stored in the memory cell array. Thus, up to 2n load/store tests described above may have to be performed to adequately test the memory cell array. Such exhaustive testing may be time consuming and costly, adding significantly to the final cost of the memory storage device.
Another type of memory storage device may include multilevel cells (MLCs). Each MLC may have more than two logic levels. Due to its ability to indicate more than two logical states, multiple bits may be stored in each MLC. These multiple bits per cell create additional challenges for testing a memory storage device having MLCs.
Thus, there is a continuing need for better ways to test an MLC memory that reduces test time and does not require increased hardware and die area.