Glossary of microelectronics manufacturing terms
Glossary of microelectronics manufacturing terms
This is a list of terms used in the manufacture of electronic micro-components. Many of the terms are already defined and explained in Wikipedia; this glossary is for looking up, comparing, and reviewing the terms. You can help enhance this page by adding new terms or clarifying definitions of existing ones. 2.5D integration – an advanced integrated circuit packaging technology that bonds dies and/or chiplets onto an interposer for enclosure within a single package3D integration – an advanced semiconductor technology that incorporates multiple layers of circuitry into a single chip, integrated both vertically and horizontally3D-IC (also 3DIC or 3D IC) – Three-dimensional integrated circuit; an integrated circuit built with 3D integrationadvanced packaging – the aggregation and interconnection of components before traditional packagingALD – see atomic layer depositionatomic layer deposition (ALD) – chemical vapor deposition process by which very thin films of a controlled composition are grownback end of line (BEoL) – wafer processing steps from the creation of metal interconnect layers through the final etching step that creates pad openings (see also front end of line, far back end of line, post-fab)BEoL – see back end of linebonding – any of several technologies that attach one electronic circuit or component to another; see wire bonding, thermocompression bonding, flip chip, hybrid bonding, etc.breadboard – a construction base for prototyping of electronicsbumping – the formation of microbumps on the surface of an electronic circuit in preparation for flip chip assemblycarrier wafer – a wafer that is attached to dies, chiplets, or another wafer during intermediate steps, but is not a part of the finished devicechip – an integrated circuit; may refer to either a bare die or a packaged devicechip carrier – a package built to contain an integrated circuitchiplet – a small die designed to be integrated with other components within a single packagechemical-mechanical polishing (CMP) – smoothing a surface with the combination of chemical and mechanical forces, using an abrasive/corrosive chemical slurry and a polishing padcircuit board – see printed circuit boardclass 10, class 100, etc. – a measure of the air quality in a cleanroom; class 10 means fewer than 10 airborne particles of size 0.5 μm or larger are permitted per cubic foot of aircleanroom (clean room) – a specialized manufacturing environment that maintains extremely low levels of particulatesCMP – see chemical-mechanical polishingcopper pillar – a type of microbump with embedded thin-film thermoelectric materialdeep reactive-ion etching (DRIE) – process that creates deep, steep-sided holes and trenches in a wafer or other substrate, typically with high aspect ratiosdicing – cutting a processed semiconductor wafer into separate diesdie – an unpackaged integrated circuit; a rectangular piece cut (diced) from a processed waferdie-to-die (also die-on-die) stacking – bonding and integrating individual bare dies atop one anotherdie-to-wafer (also die-on-wafer) stacking – bonding and integrating dies onto a wafer before dicing the waferdoping – intentional introduction of impurities into a semiconductor material for the purpose of modulating its propertiesDRIE – see deep reactive-ion etchinge-beam – see electron-beam processingEDA – see electronic design automationelectron-beam processing (e-beam) – irradiation with high energy electrons for lithography, inspection, etc.electronic design automation (EDA) – software tools for designing electronic systemsetching (etch, etch processing) – chemically removing layers from the surface of a wafer during semiconductor device fabricationfab – a semiconductor fabrication plantfan-out wafer-level packaging – an extension of wafer-level packaging in which the wafer is diced, dies are positioned on a carrier wafer and molded, and then a redistribution layer is addedfar back end of line (FBEoL) – after normal back end of line, additional in-fab processes to create RDL, copper pillars, microbumps, and other packaging-related structures (see also front end of line, back end of line, post-fab)FBEoL – see far back end of lineFEoL – see front end of lineflip chip – interconnecting electronic components by means of microbumps that have been deposited onto the contact padsfront end of line (FEoL) – initial wafer processing steps up to (but not including) metal interconnect (see also back end of line, far back end of line, post-fab)heterogeneous integration – combining different types of integrated circuitry into a single device; differences may be in fabrication process, technology node, substrate, or functionHIC - see hybrid integrated circuithybrid bonding – a permanent bond that combines a dielectric bond with embedded metal to form interconnectionshybrid integrated circuit (HIC) – a miniaturized circuit constructed of both semiconductor devices and passive components bonded to a substrateIC – see integrated circuitintegrated circuit (IC) – a miniature electronic circuit formed by microfabrication on semiconducting material, performing the same function as a larger circuit made from discrete componentsinterconnect (n.) – wires or signal traces that carry electrical signals between the elements in an electronic deviceinterposer – a small piece of semiconductor material (glass, silicon, or organic) built to host and interconnect two or more dies and/or chiplets in a single packagelead – a metal structure connecting the circuitry inside a package with components outside the packagelead frame (or leadframe) – a metal structure inside a package that connects the chip to its leadsmask – see photomaskMCM – see multi-chip modulemicrobump – a very small solder ball that provides contact between two stacked physical layers of electronicsmicroelectronics – the study and manufacture (or microfabrication) of very small electronic designs and componentsmicrofabrication – the process of fabricating miniature structures of sub-micron scaleMoore’s Law – an observation by Gordon Moore that the transistor count per square inch on ICs doubled every year, and the prediction that it would continue to do somore than Moore – a catch-all phrase for technologies that attempt to bypass Moore’s Law, creating smaller, faster, or more powerful ICs without shrinking the size of the transistormulti-chip module (MCM) – an electronic assembly integrating multiple ICs, dies, chiplets, etc.