# Path: luz_asm_sim/lib/simlib/peripheral/peripheral.py
# class Peripheral(object):
#     """ An abstract memory-mapped perhipheral interface.
#         Memory-mapped peripherals are accessed through memory
#         reads and writes.
# 
#         The address given to reads and writes is relative to the
#         peripheral's memory map.
#         Width is 1, 2, 4 for byte, halfword and word accesses.
#     """
#     def read_mem(self, addr, width):
#         raise NotImplementedError()
# 
#     def write_mem(self, addr, width, data):
#         raise NotImplementedError()
# 
# Path: luz_asm_sim/lib/commonlib/luz_defs.py
# ADDR_EXCEPTION_VECTOR       = 0x004
# 
# ADDR_CONTROL_1              = 0x100
# 
# ADDR_EXCEPTION_CAUSE        = 0x108
# 
# ADDR_EXCEPTION_RETURN_ADDR  = 0x10C
# 
# ADDR_INTERRUPT_ENABLE       = 0x120
# 
# ADDR_INTERRUPT_PENDING      = 0x124


from .peripheral import Peripheral
from .errors import (PeripheralMemoryAccessError,
    PeripheralMemoryAlignError)
from ...commonlib.utils import MASK_WORD
from ...commonlib.luz_defs import (
    ADDR_EXCEPTION_VECTOR, ADDR_CONTROL_1, ADDR_EXCEPTION_CAUSE,
    ADDR_EXCEPTION_RETURN_ADDR, ADDR_INTERRUPT_ENABLE,
    ADDR_INTERRUPT_PENDING)
# Simulates the CPU control registers
#
# Luz micro-controller simulator
# Eli Bendersky (C) 2008-2010


# Maps memory addresses of registers to names
#
cregs_memory_map = {
    ADDR_EXCEPTION_VECTOR:      'exception_vector',
    ADDR_CONTROL_1:             'control_1',
    ADDR_EXCEPTION_CAUSE:       'exception_cause',
    ADDR_EXCEPTION_RETURN_ADDR: 'exception_return_addr',

# Path: luz_asm_sim/lib/simlib/peripheral/peripheral.py
# class Peripheral(object):
#     """ An abstract memory-mapped perhipheral interface.
#         Memory-mapped peripherals are accessed through memory
#         reads and writes.
# 
#         The address given to reads and writes is relative to the
#         peripheral's memory map.
#         Width is 1, 2, 4 for byte, halfword and word accesses.
#     """
#     def read_mem(self, addr, width):
#         raise NotImplementedError()
# 
#     def write_mem(self, addr, width, data):
#         raise NotImplementedError()
# 
# Path: luz_asm_sim/lib/commonlib/luz_defs.py
# ADDR_EXCEPTION_VECTOR       = 0x004
# 
# ADDR_CONTROL_1              = 0x100
# 
# ADDR_EXCEPTION_CAUSE        = 0x108
# 
# ADDR_EXCEPTION_RETURN_ADDR  = 0x10C
# 
# ADDR_INTERRUPT_ENABLE       = 0x120
# 
# ADDR_INTERRUPT_PENDING      = 0x124


# Path: luz_asm_sim/lib/simlib/peripheral/coreregisters.py
from .peripheral import Peripheral
from .errors import (PeripheralMemoryAccessError,
    PeripheralMemoryAlignError)
from ...commonlib.utils import MASK_WORD
from ...commonlib.luz_defs import (
    ADDR_EXCEPTION_VECTOR, ADDR_CONTROL_1, ADDR_EXCEPTION_CAUSE,
    ADDR_EXCEPTION_RETURN_ADDR, ADDR_INTERRUPT_ENABLE,
    ADDR_INTERRUPT_PENDING)

# Simulates the CPU control registers
#
# Luz micro-controller simulator
# Eli Bendersky (C) 2008-2010


# Maps memory addresses of registers to names
#
cregs_memory_map = {
    ADDR_EXCEPTION_VECTOR:      'exception_vector',
    ADDR_CONTROL_1:             'control_1',
    ADDR_EXCEPTION_CAUSE:       'exception_cause',
    ADDR_EXCEPTION_RETURN_ADDR: 'exception_return_addr',

    ADDR_INTERRUPT_ENABLE:      'interrupt_enable',