# Path: luz_asm_sim/lib/asmlib/asm_common_types.py

# 
# Path: luz_asm_sim/lib/commonlib/portability.py
# def is_int_type(obj):
#     if sys.hexversion > 0x03000000:
#         return isinstance(obj, int)
#     else:
#         return isinstance(obj, int) or isinstance(obj, long)
# 
# Path: luz_asm_sim/lib/asmlib/asmparser.py
# class ParseError(Exception): pass
# class AsmParser(object):
#     def __init__(self, yacctab='parsetab'):
#     def parse(self, text):
#     def _lex_error_func(self, msg):
#     def p_asm_file(self, p):
#     def p_asm_line_1(self, p):
#     def p_asm_line_2(self, p):
#     def p_empty_line(self, p):
#     def p_directive_1(self, p):
#     def p_directive_2(self, p):
#     def p_instruction_1(self, p):
#     def p_instruction_2(self, p):
#     def p_label_def(self, p):
#     def p_arguments_opt(self, p):
#     def p_arguments_1(self, p):
#     def p_arguments_2(self, p):
#     def p_argument_1(self, p):
#     def p_argument_2(self, p):
#     def p_argument_3(self, p):
#     def p_argument_4(self, p):
#     def p_argument_5(self, p):
#     def p_number(self, p):
#     def p_error(self, p):


import re
from .asm_common_types import ImportType, RelocType
from ..commonlib.utils import (
    extract_bitfield, num_fits_in_nbits, build_bitfield)
from ..commonlib.luz_opcodes import *
from ..commonlib.portability import is_int_type
from .asmparser import (
    AsmParser, Id, Number, String, MemRef)
def _instr_mul(args, instr_addr, symtab, defines):
    return _instr_3reg(_opcode_of('mul'), args)

def _instr_divu(args, instr_addr, symtab, defines):
    return _instr_3reg(_opcode_of('divu'), args)

def _instr_div(args, instr_addr, symtab, defines):
    return _instr_3reg(_opcode_of('div'), args)

def _instr_sll(args, instr_addr, symtab, defines):
    return _instr_3reg(_opcode_of('sll'), args)

def _instr_srl(args, instr_addr, symtab, defines):
    return _instr_3reg(_opcode_of('srl'), args)

def _instr_and(args, instr_addr, symtab, defines):
    return _instr_3reg(_opcode_of('and'), args)

def _instr_or(args, instr_addr, symtab, defines):
    return _instr_3reg(_opcode_of('or'), args)

def _instr_nor(args, instr_addr, symtab, defines):
    return _instr_3reg(_opcode_of('nor'), args)

def _instr_xor(args, instr_addr, symtab, defines):
    return _instr_3reg(_opcode_of('xor'), args)

def _instr_nop(args, instr_addr, symtab, defines):
    # Pseudo-instruction: ADD r0, r0, r0
    return _instr_3reg( _opcode_of('add'),

# Path: luz_asm_sim/lib/asmlib/asm_common_types.py

# 
# Path: luz_asm_sim/lib/commonlib/portability.py
# def is_int_type(obj):
#     if sys.hexversion > 0x03000000:
#         return isinstance(obj, int)
#     else:
#         return isinstance(obj, int) or isinstance(obj, long)
# 
# Path: luz_asm_sim/lib/asmlib/asmparser.py
# class ParseError(Exception): pass
# class AsmParser(object):
#     def __init__(self, yacctab='parsetab'):
#     def parse(self, text):
#     def _lex_error_func(self, msg):
#     def p_asm_file(self, p):
#     def p_asm_line_1(self, p):
#     def p_asm_line_2(self, p):
#     def p_empty_line(self, p):
#     def p_directive_1(self, p):
#     def p_directive_2(self, p):
#     def p_instruction_1(self, p):
#     def p_instruction_2(self, p):
#     def p_label_def(self, p):
#     def p_arguments_opt(self, p):
#     def p_arguments_1(self, p):
#     def p_arguments_2(self, p):
#     def p_argument_1(self, p):
#     def p_argument_2(self, p):
#     def p_argument_3(self, p):
#     def p_argument_4(self, p):
#     def p_argument_5(self, p):
#     def p_number(self, p):
#     def p_error(self, p):


# Path: luz_asm_sim/lib/asmlib/asm_instructions.py
import re
from .asm_common_types import ImportType, RelocType
from ..commonlib.utils import (
    extract_bitfield, num_fits_in_nbits, build_bitfield)
from ..commonlib.luz_opcodes import *
from ..commonlib.portability import is_int_type
from .asmparser import (
    AsmParser, Id, Number, String, MemRef)

def _instr_mul(args, instr_addr, symtab, defines):
    return _instr_3reg(_opcode_of('mul'), args)

def _instr_divu(args, instr_addr, symtab, defines):
    return _instr_3reg(_opcode_of('divu'), args)

def _instr_div(args, instr_addr, symtab, defines):
    return _instr_3reg(_opcode_of('div'), args)

def _instr_sll(args, instr_addr, symtab, defines):
    return _instr_3reg(_opcode_of('sll'), args)

def _instr_srl(args, instr_addr, symtab, defines):
    return _instr_3reg(_opcode_of('srl'), args)

def _instr_and(args, instr_addr, symtab, defines):
    return _instr_3reg(_opcode_of('and'), args)

def _instr_or(args, instr_addr, symtab, defines):
    return _instr_3reg(_opcode_of('or'), args)

def _instr_nor(args, instr_addr, symtab, defines):
    return _instr_3reg(_opcode_of('nor'), args)

def _instr_xor(args, instr_addr, symtab, defines):
    return _instr_3reg(_opcode_of('xor'), args)

def _instr_nop(args, instr_addr, symtab, defines):
    # Pseudo-instruction: ADD r0, r0, r0
    return _instr_3reg( _opcode_of('add'),

                        [Id('$r0'), Id('$r0'), Id('$r0')])