# Path: myhdl/_Signal.py
# def _isListOfSigs(obj):
#     def purge(self):
#     def __init__(self, sig):
#     def _toVerilog(self):
#     def _toVHDL(self):
#     def __init__(self, sig):
#     def _toVerilog(self):
#     def _toVHDL(self):
# def posedge(sig):
# def negedge(sig):
# def Signal(val=None, delay=None):
#     def __init__(self, val=None):
#     def _clear(self):
#     def _update(self):
#     def val(self):
#     def next(self):
#     def next(self, val):
#     def posedge(self):
#     def negedge(self):
#     def max(self):
#     def min(self):
#     def driven(self):
#     def driven(self, val):
#     def read(self):
#     def read(self, val):
#     def _markRead(self):
#     def _markUsed(self):
#     def _setNextBool(self, val):
#     def _setNextInt(self, val):
#     def _setNextIntbv(self, val):
#     def _setNextNonmutable(self, val):
#     def _setNextMutable(self, val):
#     def _printVcdStr(self):
#     def _printVcdHex(self):
#     def _printVcdBit(self):
#     def _printVcdVec(self):
#     def __call__(self, left, right=None):
#     def __hash__(self):
#     def __bool__(self):
#     def __len__(self):
#     def __getitem__(self, key):
#     def __add__(self, other):
#     def __radd__(self, other):
#     def __sub__(self, other):
#     def __rsub__(self, other):
#     def __mul__(self, other):
#     def __rmul__(self, other):
#     def __truediv__(self, other):
#     def __rtruediv__(self, other):
#     def __floordiv__(self, other):
#     def __rfloordiv__(self, other):
#     def __mod__(self, other):
#     def __rmod__(self, other):
#     def __pow__(self, other):
#     def __rpow__(self, other):
#     def __lshift__(self, other):
#     def __rlshift__(self, other):
#     def __rshift__(self, other):
#     def __rrshift__(self, other):
#     def __and__(self, other):
#     def __rand__(self, other):
#     def __or__(self, other):
#     def __ror__(self, other):
#     def __xor__(self, other):
#     def __rxor__(self, other):
#     def __neg__(self):
#     def __pos__(self):
#     def __abs__(self):
#     def __invert__(self):
#     def __int__(self):
#     def __long__(self):
#     def __float__(self):
#     def __oct__(self):
#     def __hex__(self):
#     def __index__(self):
#     def __eq__(self, other):
#     def __ne__(self, other):
#     def __lt__(self, other):
#     def __le__(self, other):
#     def __gt__(self, other):
#     def __ge__(self, other):
#     def __getattr__(self, attr):
#     def __str__(self):
#     def __repr__(self):
#     def _toVerilog(self):
#     def _augm(self):
#     def __setitem__(self, key, val):
#     def assign(self, sig):
#         def genFunc():
#         def toVHDL():
#         def toVerilog():
#     def __init__(self, val=None, delay=1):
#     def _update(self):
#     def _apply(self, next, timeStamp):
#     def delay(self):
#     def delay(self, delay):
#     def __init__(self, sig, next, timeStamp):
#     def apply(self):
# class _WaiterList(list):
# class _PosedgeWaiterList(_WaiterList):
# class _NegedgeWaiterList(_WaiterList):
# class _Signal(object):
# class _DelayedSignal(_Signal):
# class _SignalWrap(object):


import ast
import itertools
from types import FunctionType
from myhdl._util import _flatten
from myhdl._enum import EnumType
from myhdl._Signal import SignalType


class Data():
    pass


def _resolveRefs(symdict, arg):
    gens = _flatten(arg)
    data = Data()
    data.symdict = symdict
    v = _AttrRefTransformer(data)
    for gen in gens:
        v.visit(gen.ast)
    return data.objlist

# TODO: Refactor this into two separate nodetransformers, since _resolveRefs
# needs only the names, not the objects


def _suffixer(name, used_names):
    suffixed_names = (name + '_renamed{0}'.format(i) for i in itertools.count())
    new_names = itertools.chain([name], suffixed_names)
    return next(s for s in new_names if s not in used_names)


class _AttrRefTransformer(ast.NodeTransformer):

    def __init__(self, data):
        self.data = data
        self.data.objlist = []

# Path: myhdl/_Signal.py
# def _isListOfSigs(obj):
#     def purge(self):
#     def __init__(self, sig):
#     def _toVerilog(self):
#     def _toVHDL(self):
#     def __init__(self, sig):
#     def _toVerilog(self):
#     def _toVHDL(self):
# def posedge(sig):
# def negedge(sig):
# def Signal(val=None, delay=None):
#     def __init__(self, val=None):
#     def _clear(self):
#     def _update(self):
#     def val(self):
#     def next(self):
#     def next(self, val):
#     def posedge(self):
#     def negedge(self):
#     def max(self):
#     def min(self):
#     def driven(self):
#     def driven(self, val):
#     def read(self):
#     def read(self, val):
#     def _markRead(self):
#     def _markUsed(self):
#     def _setNextBool(self, val):
#     def _setNextInt(self, val):
#     def _setNextIntbv(self, val):
#     def _setNextNonmutable(self, val):
#     def _setNextMutable(self, val):
#     def _printVcdStr(self):
#     def _printVcdHex(self):
#     def _printVcdBit(self):
#     def _printVcdVec(self):
#     def __call__(self, left, right=None):
#     def __hash__(self):
#     def __bool__(self):
#     def __len__(self):
#     def __getitem__(self, key):
#     def __add__(self, other):
#     def __radd__(self, other):
#     def __sub__(self, other):
#     def __rsub__(self, other):
#     def __mul__(self, other):
#     def __rmul__(self, other):
#     def __truediv__(self, other):
#     def __rtruediv__(self, other):
#     def __floordiv__(self, other):
#     def __rfloordiv__(self, other):
#     def __mod__(self, other):
#     def __rmod__(self, other):
#     def __pow__(self, other):
#     def __rpow__(self, other):
#     def __lshift__(self, other):
#     def __rlshift__(self, other):
#     def __rshift__(self, other):
#     def __rrshift__(self, other):
#     def __and__(self, other):
#     def __rand__(self, other):
#     def __or__(self, other):
#     def __ror__(self, other):
#     def __xor__(self, other):
#     def __rxor__(self, other):
#     def __neg__(self):
#     def __pos__(self):
#     def __abs__(self):
#     def __invert__(self):
#     def __int__(self):
#     def __long__(self):
#     def __float__(self):
#     def __oct__(self):
#     def __hex__(self):
#     def __index__(self):
#     def __eq__(self, other):
#     def __ne__(self, other):
#     def __lt__(self, other):
#     def __le__(self, other):
#     def __gt__(self, other):
#     def __ge__(self, other):
#     def __getattr__(self, attr):
#     def __str__(self):
#     def __repr__(self):
#     def _toVerilog(self):
#     def _augm(self):
#     def __setitem__(self, key, val):
#     def assign(self, sig):
#         def genFunc():
#         def toVHDL():
#         def toVerilog():
#     def __init__(self, val=None, delay=1):
#     def _update(self):
#     def _apply(self, next, timeStamp):
#     def delay(self):
#     def delay(self, delay):
#     def __init__(self, sig, next, timeStamp):
#     def apply(self):
# class _WaiterList(list):
# class _PosedgeWaiterList(_WaiterList):
# class _NegedgeWaiterList(_WaiterList):
# class _Signal(object):
# class _DelayedSignal(_Signal):
# class _SignalWrap(object):


# Path: myhdl/_resolverefs.py
import ast
import itertools
from types import FunctionType
from myhdl._util import _flatten
from myhdl._enum import EnumType
from myhdl._Signal import SignalType



class Data():
    pass


def _resolveRefs(symdict, arg):
    gens = _flatten(arg)
    data = Data()
    data.symdict = symdict
    v = _AttrRefTransformer(data)
    for gen in gens:
        v.visit(gen.ast)
    return data.objlist

# TODO: Refactor this into two separate nodetransformers, since _resolveRefs
# needs only the names, not the objects


def _suffixer(name, used_names):
    suffixed_names = (name + '_renamed{0}'.format(i) for i in itertools.count())
    new_names = itertools.chain([name], suffixed_names)
    return next(s for s in new_names if s not in used_names)


class _AttrRefTransformer(ast.NodeTransformer):

    def __init__(self, data):
        self.data = data
        self.data.objlist = []

        self.myhdl_types = (EnumType, SignalType)