# Path: basil/utils/sim/utils.py
# def cocotb_compile_and_run(*args, **kw):
#     # run simulator in background
#     with open('Makefile', 'w') as f:
#         f.write(cocotb_makefile(*args, **kw))
#     subprocess.Popen(['make'])
# 
# def cocotb_compile_clean():
#     subprocess.call('make clean', shell=True)
#     subprocess.call('rm -f Makefile', shell=True)
# 
# def get_basil_dir():
#     return str(os.path.dirname(basil.__file__))


import sys
import unittest
import os
import yaml
import numpy as np
import pixel # noqa E402
from bitarray import bitarray
from basil.utils.sim.utils import cocotb_compile_and_run, cocotb_compile_clean, get_basil_dir
            os.path.join(fw_path, 'sram_fifo/sram_fifo_core.v'),
            os.path.join(fw_path, 'sram_fifo/sram_fifo.v'),
            os.path.join(os.path.dirname(__file__), '../firmware/src/clk_gen.v'),
            os.path.join(os.path.dirname(__file__), '../firmware/src/pixel.v'),
            os.path.join(os.path.dirname(__file__), '../tests/tb.v')],
            top_level='tb',
            sim_bus='basil.utils.sim.SiLibUsbBusDriver'
        )

        with open(os.path.join(os.path.dirname(__file__), '../pixel.yaml'), 'r') as f:
            cnfg = yaml.safe_load(f)

        # change to simulation interface
        cnfg['transfer_layer'][0]['type'] = 'SiSim'

        self.chip = pixel.Pixel(cnfg)
        self.chip.init()

    def test_simple(self):
        input_arr = bitarray('10' * 64)

        self.chip['PIXEL_REG'][:] = input_arr
        self.chip['PIXEL_REG'][0] = 0
        self.chip.program_pixel_reg()

        ret = self.chip['DATA'].get_data()

        data0 = ret.astype(np.uint8)
        data1 = np.right_shift(ret, 8).astype(np.uint8)
        data = np.reshape(np.vstack((data1, data0)), -1, order='F')

# Path: basil/utils/sim/utils.py
# def cocotb_compile_and_run(*args, **kw):
#     # run simulator in background
#     with open('Makefile', 'w') as f:
#         f.write(cocotb_makefile(*args, **kw))
#     subprocess.Popen(['make'])
# 
# def cocotb_compile_clean():
#     subprocess.call('make clean', shell=True)
#     subprocess.call('rm -f Makefile', shell=True)
# 
# def get_basil_dir():
#     return str(os.path.dirname(basil.__file__))


# Path: examples/mio_pixel/tests/test_Sim_mio_pixel.py
import sys
import unittest
import os
import yaml
import numpy as np
import pixel # noqa E402
from bitarray import bitarray
from basil.utils.sim.utils import cocotb_compile_and_run, cocotb_compile_clean, get_basil_dir

            os.path.join(fw_path, 'sram_fifo/sram_fifo_core.v'),
            os.path.join(fw_path, 'sram_fifo/sram_fifo.v'),
            os.path.join(os.path.dirname(__file__), '../firmware/src/clk_gen.v'),
            os.path.join(os.path.dirname(__file__), '../firmware/src/pixel.v'),
            os.path.join(os.path.dirname(__file__), '../tests/tb.v')],
            top_level='tb',
            sim_bus='basil.utils.sim.SiLibUsbBusDriver'
        )

        with open(os.path.join(os.path.dirname(__file__), '../pixel.yaml'), 'r') as f:
            cnfg = yaml.safe_load(f)

        # change to simulation interface
        cnfg['transfer_layer'][0]['type'] = 'SiSim'

        self.chip = pixel.Pixel(cnfg)
        self.chip.init()

    def test_simple(self):
        input_arr = bitarray('10' * 64)

        self.chip['PIXEL_REG'][:] = input_arr
        self.chip['PIXEL_REG'][0] = 0
        self.chip.program_pixel_reg()

        ret = self.chip['DATA'].get_data()

        data0 = ret.astype(np.uint8)
        data1 = np.right_shift(ret, 8).astype(np.uint8)
        data = np.reshape(np.vstack((data1, data0)), -1, order='F')

        bdata = np.unpackbits(data)