# Path: tests/packer_algo_tl.py
# class PackerTlAlgo(sydpy.Component, JesdPackerAlgo):
#     @sydpy.compinit
#     def __init__(self, name, parent, ch_samples, tSample = None, N=8, S=1, CS=0, CF=0, L=1, F=1, HD=0, **kwargs):
#         sydpy.Component.__init__(self, name, parent)
#         JesdPackerAlgo.__init__(self, dtype = sydpy.Bit, M=len(ch_samples), N=N, S=S, CS=CS, CF=CF, L=L, F=F, HD=HD)
#         self.csin = []
#         self.din = []
#         for i, d in enumerate(ch_samples):
#             self.din.append(sydpy.isig('din{}'.format(i), self, dtype=tSample, dflt={'d': 0, 'cs':0}))
#             d >>= self.din[-1]
#         
#         sydpy.Process('pack', self, self.pack)
#     
#     def pack(self):
#         while(1):
#             sydpy.ddic['sim'].wait(sydpy.Delay(10))
#             samples = []
#             for _ in range(self.S):
#                 for d in self.din:
#                     samples.append(d.bpop())
#             
#             JesdPackerAlgo.pack(self, samples)
# 
# Path: tests/packer_tl_matrix.py
# class PackerTlMatrix(sydpy.Component, JesdPackerAlgo):
#     @sydpy.compinit
#     def __init__(self, name, parent, ch_samples, tSample = None, N=8, S=1, CS=0, CF=0, L=1, F=1, HD=0, **kwargs):
#         sydpy.Component.__init__(self, name, parent)
#         dtype = SymbolicBit
#         M = len(ch_samples)
#         JesdPackerAlgo.__init__(self, dtype=dtype, M=M, N=N, S=S, CS=CS, CF=CF, L=L, F=F, HD=HD)
#     
#         sym_samples = []
#         for i in range(M):
#             sym_samples.append((dtype(N)([(i, 0, j) for j in range(N)]), 
#                             dtype(CS)([(i, 1, j) for j in range(CS)])))    
#     
#         print('Samples: ', sym_samples)
#         self.pack_m = JesdPackerAlgo.pack(self, sym_samples)
#         
#         self.csin = []
#         self.din = []
#         for i, d in enumerate(ch_samples):
#             self.din.append(sydpy.isig('din{}'.format(i), self, dtype=tSample, dflt={'d': 0, 'cs':0}))
#             d >>= self.din[-1]
#         
#         sydpy.Process('pack', self, self.pack)
#     
#     def pack(self):
#         while(1):
#             sydpy.ddic['sim'].wait(sydpy.Delay(10))
#             samples = []
#             for _ in range(self.S):
#                 for d in self.din:
#                     samples.append(d.bpop())
#             
#             frame = []
#             for m_lane in self.pack_m:
#                 f_lane = []
#                 for m_byte in m_lane:
#                     f_byte = sydpy.Bit(8)(0)
#                     for i, m_bit in enumerate(m_byte.val):
#                         if m_bit:
#                             f_byte[i] = samples[m_bit[0]][m_bit[1]][m_bit[2]]
#                         else:
#                             f_byte[i] = 0
#                     f_lane.append(f_byte)
#                     
#                 frame.append(f_lane)
#                 
#             print(f_lane)


import sydpy
from tests.packer_algo_tl import PackerTlAlgo
from tests.packer_tl_matrix import PackerTlMatrix
#             self.inst(ch, Channel)
        
        ch_gen = []
        for i in range(M):
            ch_gen.append(sydpy.Channel('ch_gen{}'.format(i), self))
            Converter('conv{}'.format(i), self, ch_sample=ch_gen[-1])
            
        PackerTlAlgo('pack_algo', self, ch_samples=ch_gen)
        PackerTlMatrix('pack_matrix', self, ch_samples=ch_gen)

N = 11
CS = 2

conf = [
        ('top.M'       , 16),
        ('top/*.CF'    , 1),
        ('top/*.CS'    , CS),
        ('top/*.F'     , 4),
        ('top/*.HD'    , 1),
        ('top/*.L'     , 7),
        ('top/*.S'     , 1),
        ('top/*.N'     , N),
        ('sim.duration', 10)
        ]

sydpy.ddic.configure('top/*.tSample', sydpy.Struct(('d', sydpy.Bit(N)), 
                                             ('cs', sydpy.Bit(CS))))


for c, v in conf:

# Path: tests/packer_algo_tl.py
# class PackerTlAlgo(sydpy.Component, JesdPackerAlgo):
#     @sydpy.compinit
#     def __init__(self, name, parent, ch_samples, tSample = None, N=8, S=1, CS=0, CF=0, L=1, F=1, HD=0, **kwargs):
#         sydpy.Component.__init__(self, name, parent)
#         JesdPackerAlgo.__init__(self, dtype = sydpy.Bit, M=len(ch_samples), N=N, S=S, CS=CS, CF=CF, L=L, F=F, HD=HD)
#         self.csin = []
#         self.din = []
#         for i, d in enumerate(ch_samples):
#             self.din.append(sydpy.isig('din{}'.format(i), self, dtype=tSample, dflt={'d': 0, 'cs':0}))
#             d >>= self.din[-1]
#         
#         sydpy.Process('pack', self, self.pack)
#     
#     def pack(self):
#         while(1):
#             sydpy.ddic['sim'].wait(sydpy.Delay(10))
#             samples = []
#             for _ in range(self.S):
#                 for d in self.din:
#                     samples.append(d.bpop())
#             
#             JesdPackerAlgo.pack(self, samples)
# 
# Path: tests/packer_tl_matrix.py
# class PackerTlMatrix(sydpy.Component, JesdPackerAlgo):
#     @sydpy.compinit
#     def __init__(self, name, parent, ch_samples, tSample = None, N=8, S=1, CS=0, CF=0, L=1, F=1, HD=0, **kwargs):
#         sydpy.Component.__init__(self, name, parent)
#         dtype = SymbolicBit
#         M = len(ch_samples)
#         JesdPackerAlgo.__init__(self, dtype=dtype, M=M, N=N, S=S, CS=CS, CF=CF, L=L, F=F, HD=HD)
#     
#         sym_samples = []
#         for i in range(M):
#             sym_samples.append((dtype(N)([(i, 0, j) for j in range(N)]), 
#                             dtype(CS)([(i, 1, j) for j in range(CS)])))    
#     
#         print('Samples: ', sym_samples)
#         self.pack_m = JesdPackerAlgo.pack(self, sym_samples)
#         
#         self.csin = []
#         self.din = []
#         for i, d in enumerate(ch_samples):
#             self.din.append(sydpy.isig('din{}'.format(i), self, dtype=tSample, dflt={'d': 0, 'cs':0}))
#             d >>= self.din[-1]
#         
#         sydpy.Process('pack', self, self.pack)
#     
#     def pack(self):
#         while(1):
#             sydpy.ddic['sim'].wait(sydpy.Delay(10))
#             samples = []
#             for _ in range(self.S):
#                 for d in self.din:
#                     samples.append(d.bpop())
#             
#             frame = []
#             for m_lane in self.pack_m:
#                 f_lane = []
#                 for m_byte in m_lane:
#                     f_byte = sydpy.Bit(8)(0)
#                     for i, m_bit in enumerate(m_byte.val):
#                         if m_bit:
#                             f_byte[i] = samples[m_bit[0]][m_bit[1]][m_bit[2]]
#                         else:
#                             f_byte[i] = 0
#                     f_lane.append(f_byte)
#                     
#                 frame.append(f_lane)
#                 
#             print(f_lane)


# Path: tests/packing.py
import sydpy
from tests.packer_algo_tl import PackerTlAlgo
from tests.packer_tl_matrix import PackerTlMatrix

#             self.inst(ch, Channel)
        
        ch_gen = []
        for i in range(M):
            ch_gen.append(sydpy.Channel('ch_gen{}'.format(i), self))
            Converter('conv{}'.format(i), self, ch_sample=ch_gen[-1])
            
        PackerTlAlgo('pack_algo', self, ch_samples=ch_gen)
        PackerTlMatrix('pack_matrix', self, ch_samples=ch_gen)

N = 11
CS = 2

conf = [
        ('top.M'       , 16),
        ('top/*.CF'    , 1),
        ('top/*.CS'    , CS),
        ('top/*.F'     , 4),
        ('top/*.HD'    , 1),
        ('top/*.L'     , 7),
        ('top/*.S'     , 1),
        ('top/*.N'     , N),
        ('sim.duration', 10)
        ]

sydpy.ddic.configure('top/*.tSample', sydpy.Struct(('d', sydpy.Bit(N)), 
                                             ('cs', sydpy.Bit(CS))))


for c, v in conf:

    sydpy.ddic.configure(c, v)