# Path: src/uio/ti/eirq.py
# class EIrq( ctypes.Structure ):
#     _fields_ = [
#             ("enabled", ushort),    #rw
#             ("pending", ushort),    #r-
#             ("_clear",  ushort),    #-c
#             ("_set",    ushort),    #-s
#         ]
# 
#     def clear( self, bits, *, eoi=False ):
#         if eoi:
#             bits |= 1
#         self._clear = bits
#         self._clear  # ocp barrier
#         if bits & 1 and hasattr( self, 'uio' ):
#             self.uio.irq_enable()
# 
#     def set( self, bits ):
#         self._set = bits
# 
#     def enable( self, bits ):
#         self.enabled |= bits
#         if hasattr( self, 'uio' ):
#             self.uio.irq_enable()
# 
#     def disable( self, bits ):
#         self.enabled &= ~bits
# 
#     @property
#     def active( self ):
#         return self.enabled & self.pending
# 
#     def recv( self ):
#         if hasattr( self, 'uio' ):
#             self.uio.irq_recv()
#         events = self.active
#         self.clear( events, eoi=True )
#         return events
# 
#     def reset( self ):
#         self.enabled = 0
#         self.clear( 0xffff )


from uio.utils import fix_ctypes_struct, cached_getter, add_field
from ctypes import c_uint8 as u8, c_uint16 as u16, c_uint32 as u32
from .eirq import EIrq
import ctypes
            # bits  7- 9   rw  fine divider / 2 (0 = disabled, i.e. /1)
            # bits 10-12   rw  coarse divider, log2
            # bit  13      rw  updown counter direction on sync-in counter load
            # bits 14-15   rw  debug suspend:  0 hard  1 soft  2 disabled

            ("status",      u16),
            # bit   0      r-  counter direction
            # bit   1      rc  sync-in event
            # bit   2      rc  max event

            ("",            u16),       #rw
            ("ld_counter",  ctr_t),     #rw
            ("counter",     ctr_t),     #rw

            ("ld_maximum",  ctr_t),     #rw

            ("",            u16),


            #-------- comparators ----------------------------------------------
            #
            # Four events generated:
            #   up-a    if counter == cmp-a while counting up
            #   up-b    if counter == cmp-b while counting up
            #   down-a  if counter == min( cmp-a, maximum ) while counting down
            #   down-b  if counter == min( cmp-b, maximum ) while counting down
            #
            # In updown mode, at an endpoint (where the direction is reversed),
            # the new direction applies.


# Path: src/uio/ti/eirq.py
# class EIrq( ctypes.Structure ):
#     _fields_ = [
#             ("enabled", ushort),    #rw
#             ("pending", ushort),    #r-
#             ("_clear",  ushort),    #-c
#             ("_set",    ushort),    #-s
#         ]
# 
#     def clear( self, bits, *, eoi=False ):
#         if eoi:
#             bits |= 1
#         self._clear = bits
#         self._clear  # ocp barrier
#         if bits & 1 and hasattr( self, 'uio' ):
#             self.uio.irq_enable()
# 
#     def set( self, bits ):
#         self._set = bits
# 
#     def enable( self, bits ):
#         self.enabled |= bits
#         if hasattr( self, 'uio' ):
#             self.uio.irq_enable()
# 
#     def disable( self, bits ):
#         self.enabled &= ~bits
# 
#     @property
#     def active( self ):
#         return self.enabled & self.pending
# 
#     def recv( self ):
#         if hasattr( self, 'uio' ):
#             self.uio.irq_recv()
#         events = self.active
#         self.clear( events, eoi=True )
#         return events
# 
#     def reset( self ):
#         self.enabled = 0
#         self.clear( 0xffff )


# Path: src/uio/ti/epwm.py
from uio.utils import fix_ctypes_struct, cached_getter, add_field
from ctypes import c_uint8 as u8, c_uint16 as u16, c_uint32 as u32
from .eirq import EIrq
import ctypes

            # bits  7- 9   rw  fine divider / 2 (0 = disabled, i.e. /1)
            # bits 10-12   rw  coarse divider, log2
            # bit  13      rw  updown counter direction on sync-in counter load
            # bits 14-15   rw  debug suspend:  0 hard  1 soft  2 disabled

            ("status",      u16),
            # bit   0      r-  counter direction
            # bit   1      rc  sync-in event
            # bit   2      rc  max event

            ("",            u16),       #rw
            ("ld_counter",  ctr_t),     #rw
            ("counter",     ctr_t),     #rw

            ("ld_maximum",  ctr_t),     #rw

            ("",            u16),


            #-------- comparators ----------------------------------------------
            #
            # Four events generated:
            #   up-a    if counter == cmp-a while counting up
            #   up-b    if counter == cmp-b while counting up
            #   down-a  if counter == min( cmp-a, maximum ) while counting down
            #   down-b  if counter == min( cmp-b, maximum ) while counting down
            #
            # In updown mode, at an endpoint (where the direction is reversed),
            # the new direction applies.


            ("cmp_load",    u16),