# Path: sibyl/abi/abi.py
# class ABI(object):
# class ABIRegsStack(ABI):
#     def __init__(self, jitter, ira):
#     def reset(self):
#     def add_arg(self, number, element):
#     def prepare_call(self, ret_addr):
#     def get_result(self):
#     def __init__(self, *args, **kwargs):
#     def add_arg(self, number, element):
#     def vm_push(self, element):
#     def set_ret(self, element):
#     def prepare_call(self, ret_addr):
#     def reset(self):
#     def get_result(self):


from sibyl.abi import abi
class ABIRegsStack_x86(abi.ABIRegsStack):

    def set_ret(self, ret_addr):
        self.vm_push(ret_addr)


class ABIStdCall_x86_32(ABIRegsStack_x86):

    regs_mapping = [] # Stack only
    arch = ["x86_32"]

    def vm_push(self, element):
        self.jitter.push_uint32_t(element)


class ABIFastCall_x86_32(ABIRegsStack_x86):

    regs_mapping = ["ECX", "EDX"]
    arch = ["x86_32"]

    def vm_push(self, element):
        self.jitter.push_uint32_t(element)


class ABI_AMD64_SYSTEMV(ABIRegsStack_x86):

    regs_mapping = ["RDI", "RSI", "RDX", "RCX", "R8", "R9"]
    arch = ["x86_64"]

    def vm_push(self, element):

# Path: sibyl/abi/abi.py
# class ABI(object):
# class ABIRegsStack(ABI):
#     def __init__(self, jitter, ira):
#     def reset(self):
#     def add_arg(self, number, element):
#     def prepare_call(self, ret_addr):
#     def get_result(self):
#     def __init__(self, *args, **kwargs):
#     def add_arg(self, number, element):
#     def vm_push(self, element):
#     def set_ret(self, element):
#     def prepare_call(self, ret_addr):
#     def reset(self):
#     def get_result(self):


# Path: sibyl/abi/x86.py
from sibyl.abi import abi

class ABIRegsStack_x86(abi.ABIRegsStack):

    def set_ret(self, ret_addr):
        self.vm_push(ret_addr)


class ABIStdCall_x86_32(ABIRegsStack_x86):

    regs_mapping = [] # Stack only
    arch = ["x86_32"]

    def vm_push(self, element):
        self.jitter.push_uint32_t(element)


class ABIFastCall_x86_32(ABIRegsStack_x86):

    regs_mapping = ["ECX", "EDX"]
    arch = ["x86_32"]

    def vm_push(self, element):
        self.jitter.push_uint32_t(element)


class ABI_AMD64_SYSTEMV(ABIRegsStack_x86):

    regs_mapping = ["RDI", "RSI", "RDX", "RCX", "R8", "R9"]
    arch = ["x86_64"]

    def vm_push(self, element):

        self.jitter.push_uint64_t(element)