+incdir+../testbench
+incdir+../simulation
+incdir+../rtl      
+incdir+../cores/orpsoc-cores/cores/wb_bfm/wb_bfm-0/
+incdir+../cores/orpsoc-cores/cores/verilog_utils/
+incdir+../cores/orpsoc-cores/cores/wb_common/      
+define+VERBOSE
+define+SIM
      

../rtl/syscon.v
../rtl/adc_clk_gen.v
../rtl/wb_dsp_algorithm_sm.v
../rtl/wb_dsp_equations_top.v
../rtl/equation_sum.v
../rtl/wb_dsp_slave_registers.v
../rtl/wb_dsp_top.v
../rtl/wb_daq_bus_master.v
../rtl/wb_daq_slave_registers.v
../rtl/wb_daq_top.v
../rtl/wb_master_interface.v
../rtl/wb_daq_data_aggregation.v
../rtl/wb_daq_channel.v
../rtl/fifo.v
../rtl/fifo_to_sram.v
../behavioral/adc/adc.v
../testbench/testbench.v
../testbench/test_tasks.v
../testbench/arbiter.v
../testbench/wb_dsp_testbench_intercon.v
../testbench/wb_dump.v
../cores/orpsoc-cores/cores/wb_intercon/wb_mux.v
../cores/orpsoc-cores/cores/wb_intercon/wb_arbiter.v
../cores/orpsoc-cores/cores/wb_intercon/wb_data_resize.v      
../cores/orpsoc-cores/cores/wb_bfm/wb_bfm-0/wb_bfm_master.v
../cores/orpsoc-cores/cores/wb_ram/rtl/verilog/wb_ram.v
../cores/orpsoc-cores/cores/wb_ram/rtl/verilog/wb_ram_generic.v      
