
+incdir+${MOR1KX_SOC}/ve/mor1kx_soc_alt_uvm/tb
+incdir+${MOR1KX_SOC}/ve/mor1kx_soc_alt_uvm/tests

${QUARTUS_ROOTDIR}/../modelsim_ase/altera/verilog/src/altera_mf.v

-f ${MOR1KX_SOC}/rtl/rtl.f
-f ${MEMORY_PRIMITIVES}/rtl/fpga/altsyncram/rtl.f

${MOR1KX_SOC}/ve/mor1kx_soc_alt_uvm/tb/mor1kx_soc_alt_uvm_env_pkg.sv

${MOR1KX_SOC}/ve/mor1kx_soc_alt_uvm/tests/mor1kx_soc_alt_uvm_tests_pkg.sv

${MOR1KX_SOC}/ve/mor1kx_soc_alt_uvm/tb/mor1kx_soc_alt_uvm_tb.sv


