+incdir+../testbench
+incdir+../cores/orpsoc-cores/cores/wb_bfm/wb_bfm-0/
+incdir+../cores/orpsoc-cores/cores/verilog_utils/
+define+VERBOSE
+define+SIM
      
../rtl/syscon.v
../rtl/testing_wb_slave.v
../testbench/testbench_testing_wb_slave.v
../testbench/arbiter.v
../testbench/wb_switch1.v
../testbench/dump.v
../cores/orpsoc-cores/cores/wb_bfm/wb_bfm-0/wb_bfm_master.v
../cores/orpsoc-cores/cores/wb_intercon/wb_mux.v
../cores/orpsoc-cores/cores/wb_intercon/wb_arbiter.v
../cores/orpsoc-cores/cores/wb_intercon/wb_data_resize.v      
