${PRJ_DIR}/hw/top_earlgrey/rtl/top_pkg.sv
${PRJ_DIR}/hw/ip/tlul/rtl/tlul_pkg.sv
${PRJ_DIR}/hw/ip/prim/rtl/prim_pkg.sv

${PRJ_DIR}/hw/ip/prim/rtl/prim_assert.sv
${PRJ_DIR}/hw/ip/prim/rtl/prim_flop_2sync.sv
${PRJ_DIR}/hw/ip/prim/rtl/prim_fifo_async.sv
${PRJ_DIR}/hw/ip/prim/rtl/prim_fifo_sync.sv
${PRJ_DIR}/hw/ip/prim/rtl/prim_clock_inverter.sv
${PRJ_DIR}/hw/ip/prim/abstract/prim_clock_mux2.sv
${PRJ_DIR}/hw/ip/prim_generic/rtl/prim_generic_clock_mux2.sv

${PRJ_DIR}/hw/vendor/pulp_riscv_dbg/src/dm_pkg.sv
${PRJ_DIR}/hw/vendor/pulp_riscv_dbg/debug_rom/debug_rom.sv
${PRJ_DIR}/hw/vendor/pulp_riscv_dbg/src/dm_sba.sv
${PRJ_DIR}/hw/vendor/pulp_riscv_dbg/src/dm_csrs.sv
${PRJ_DIR}/hw/vendor/pulp_riscv_dbg/src/dm_mem.sv
${PRJ_DIR}/hw/vendor/pulp_riscv_dbg/src/dmi_cdc.sv
${PRJ_DIR}/hw/vendor/pulp_riscv_dbg/src/dmi_jtag.sv
${PRJ_DIR}/hw/vendor/pulp_riscv_dbg/src/dmi_jtag_tap.sv
${PRJ_DIR}/hw/ip/tlul/rtl/tlul_adapter_sram.sv
${PRJ_DIR}/hw/ip/tlul/rtl/tlul_err.sv
