Bit-serial architecture
In computer architecture, bit-serial architectures send data one bit at a time, along a single wire, in contrast to bit-parallel word architectures, in which data values are sent all bits or a word at once along a group of wires. All digital computers built before 1951, and most of the early massive parallel processing machines used a bit-serial architecture—they were serial computers. Bit-serial architectures were developed for digital signal processing in the 1960s through 1980s, including efficient structures for bit-serial multiplication and accumulation. The HP Nut processor used in many Hewlett-Packard calculators operated bit-serially. Often, N serial processors will take less FPGA area and have a higher total performance than a single N-bit parallel processor. See also 1-bit computing Bit banging Bit slicing Serial computer BKM algorithm CORDIC References External links Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method BIT-Serial FIR filters with CSD Coefficients for FPGAs Data transmission