What I am trying to do is as follows:  

I am taking few elements of an array, comparing them with a fixed value and trying to create a vector out of it.

Here is a piece of code:

```
architecture behav of main_ent is
... 
type f_array is array(0 to 8) of std_logic_vector(7 downto 0);
signal ins_f_array: f_array;
signal sel_sig_cmd : std_logic_vector(3 downto 0); 
...
process begin
sel_sig_cmd <= ((ins_f_array(4) = x"3A")&(ins_f_array(3)= x"3A")&(ins_f_array(2)= x"3A")&(ins_f_array(1)= x"3A"));

....
end process;
...

```

This should give something like **sel\_sig\_cmd = 1000** or may be **1011 etc**. But this is not working. Is there any alternative to this code?  

 cheers   

 Tahir
['https://Stackoverflow.com/questions/52837952', 'https://Stackoverflow.com', 'https://Stackoverflow.com/users/9547499/']
The answer from Tricky is a good one to follow. However, if you want to implement it in a process, then the process can be rewritten as follows :

```
architecture behav of main_ent is
... 
type f_array is array(0 to 8) of std_logic_vector(7 downto 0);
signal ins_f_array: f_array;
signal sel_sig_cmd : std_logic_vector(3 downto 0); 
...
process(ins_f_array(4 downto 1)) begin
if ((ins_f_array(4) = x"3A")&(ins_f_array(3)= x"3A")&
              (ins_f_array(2)= x"3A")&(ins_f_array(1)= x"3A")) then
sel_sig_cmd <= "XXXX" -- Enter your desired value
....
end process;
...

```

This process would be tedious though as it has to cover all the 16 possibilities of the "if condition".

Another implementation is to use an if condition for each bit as follows :

```
architecture behav of main_ent is
... 
type f_array is array(0 to 8) of std_logic_vector(7 downto 0);
signal ins_f_array: f_array;
signal sel_sig_cmd : std_logic_vector(3 downto 0); 
...
process(ins_f_array(4 downto 1)) begin
if (ins_f_array(4) = x"3A") then
sel_sig_cmd(3) <= "X" -- Enter your desired value
else
sel_sig_cmd(3) <= "X" -- Enter your desired value
end if;
-- Repeat for other bits
....
end process;
...

```
You can overload the "=" operator :

```
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb is
end entity;

architecture behav of tb is

  function "=" (Left, Right: std_logic_vector) return std_logic is
  begin
    if (Left = Right) then
      return '1';
    else
      return '0';
    end if;
  end function "=";

  type f_array is array(0 to 8) of std_logic_vector(7 downto 0);
  signal ins_f_array: f_array := (x"00",x"01",x"02",x"03",x"04",x"05",x"06",x"07",x"08");
  signal sel_sig_cmd : std_logic_vector(3 downto 0); 

  begin

    process (ins_f_array(1 to 4)) begin
      sel_sig_cmd <= ((ins_f_array(4) = x"3A")&(ins_f_array(3) = x"3A")&(ins_f_array(2) = x"3A")&(ins_f_array(1) = x"3A"));
    end process;

    process
    begin
      wait for 10 us;
      for i in 0 to 8 loop  
        ins_f_array(i) <= std_logic_vector(unsigned(ins_f_array(i)) + 1);
      end loop;
    end process;

end architecture;

```