I'm learning VHDL and I've come to a halt. I'd like to create a simple gate out of smaller gates (a NAND gate here). Here's the code:

```
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity ANDGATE2 is
     port(
         x,y  : in STD_LOGIC;
         z    : out STD_LOGIC
         );
end ANDGATE2;

architecture ANDGATE2 of ANDGATE2 is
begin

    z <= x AND y;

end ANDGATE2;

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity NOTGATE1 is
     port(
         x : in STD_LOGIC;
         z : out STD_LOGIC
         );
end NOTGATE1;

architecture NOTGATE1 of NOTGATE1 is
begin

    z <= NOT x;

end NOTGATE1;       

library  ieee;
use  ieee.std_logic_1164.all;

entity NANDGATE2 is
     port(
         x : in STD_LOGIC;
         y : in STD_LOGIC;
         z : out STD_LOGIC
         );
end NANDGATE2;

architecture NANDGATE2 of NANDGATE2 is   
signal c, d: std_logic;
    component NOTGATE1
         port(
             n_in : in STD_LOGIC;
             n_out : out STD_LOGIC
             );
    end component;  
    component ANDGATE2
        port(
             a_in1, a_in2 : in STD_LOGIC;
             a_out        : out STD_LOGIC
             );
    end component;
begin     
    N0: ANDGATE2
    port map(x, y, c);
    N1: NOTGATE1
    port map(c, d); 

    z <= d;

end NANDGATE2;

```

Here's the code from some tutorial I've been using as a template; it compiles with no problems.

```
library  ieee;
use  ieee.std_logic_1164.all;

-- definition of a full adder

entity FULLADDER is
    port 
    (
        a, b, c: in std_logic;
        sum, carry: out std_logic
    );
end FULLADDER;     

architecture fulladder_behav of FULLADDER is
begin
sum <= (a xor b) xor c ;
carry <= (a and b) or (c and (a xor b));
     end fulladder_behav;

     -- 4-bit adder

library  ieee;
use  ieee.std_logic_1164.all;

entity FOURBITADD is
    port 
    (
        a, b: in std_logic_vector(3 downto 0);
        Cin : in std_logic;
        sum: out std_logic_vector (3 downto 0);
        Cout, V: out std_logic
    );
end FOURBITADD;

architecture fouradder_structure of FOURBITADD is
     signal c: std_logic_vector (4 downto 0);
component FULLADDER
    port
    (
        a, b, c: in std_logic;
        sum, carry: out std_logic
    );
end component;

begin
           FA0: FULLADDER
                port map (a(0), b(0), Cin, sum(0), c(1));
           FA1: FULLADDER
                port map (a(1), b(1), C(1), sum(1), c(2));
           FA2: FULLADDER
                port map (a(2), b(2), C(2), sum(2), c(3));
           FA3: FULLADDER
                port map (a(3), b(3), C(3), sum(3), c(4));
           V <= c(3) xor c(4);
           Cout <= c(4);
end fouradder_structure;

```

My code compiles with no errors, but with two warnings:

```
# Warning: ELAB1_0026: p2.vhd : (85, 0): There is no default binding for component "andgate2".(Port "a_in1" is not on the entity).
# Warning: ELAB1_0026: p2.vhd : (87, 0): There is no default binding for component "notgate1".(Port "n_in" is not on the entity).

```

What gives?
['https://Stackoverflow.com/questions/5336413', 'https://Stackoverflow.com', 'https://Stackoverflow.com/users/663907/']
You need to use the same port names on your component and entity declarations.

Right now, for example in your `NOTGATE1` entity declaration, you have input port `x` and output port `z`, but in the `NANDGATE2` architecture, you declare the `NOTGATE1` component to have ports `n_in` and `n_out`.

This won't cause problems during compilation, since compilation looks at a single unit at a time, and won't see the actual entities. In the elaboration phase, your tools will try to match up the entities to components, but this will fail since the ports don't match.
Not 100% sure, but I think the pins in your `component` declarations need to match up to the ones in your `entity` blocks:

```
component NOTGATE1
     port(
         x : in STD_LOGIC;
         z : out STD_LOGIC
         );
end component;  
component ANDGATE2
    port(
         x,y : in STD_LOGIC;
         z   : out STD_LOGIC
         );

```