<jupyter_start><jupyter_text>DFF and TFF (Toggle Flip-Flop)In this example we create a toggle flip-flop (TFF) from a d-flip-flop (DFF). In `Magma`, finite state machines can be constructed by composing combinational logic with flop-flops register primitives.<jupyter_code>import magma as m
from mantle import DFF
class TFF(m.Circuit):
    io = m.IO(O=m.Out(m.Bit)) + m.ClockIO()
    # instance a dff to hold the state of the toggle flip-flop - this needs to be done first
    dff = DFF()
    # compute the next state as the not of the old state ff.O
    io.O <= dff(~dff.O)
        
def tff():
    return TFF()()<jupyter_output><empty_output><jupyter_text>Test using the python simulator.<jupyter_code>from fault import PythonTester
tester = PythonTester(TFF, TFF.CLK)

tester.eval()
val = tester.peek(TFF.O)
assert val == False

for i in range(10):
    val = not val
    
    tester.step() # toggle clock - now High
    assert val == tester.peek(TFF.O)

    tester.step() # toggle clock - now Low
    assert val == tester.peek(TFF.O)

print("Success!")<jupyter_output>Success!<jupyter_text>Generate Verilog Generate verilog with `coreir`.<jupyter_code>m.compile("build/TFF", TFF, inline=True)
%cat build/TFF.v
%cat build/TFF.json
!coreir -i build/TFF.json -p instancecount<jupyter_output>An instance count of all the primitives
=======================================
DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse | instances in current | instances in children | 
  coreir_reg__width1 | 1 | 0

TFF | instances in current | instances in children | 
  corebit_not | 1 | 0
  coreir_reg__width1 | 0 | 1

=======================================
{"top":"global.TFF",
"namespaces":{
  "global":{
    "modules":{
      "DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse":{
        "type":["Record",[
          ["I","BitIn"],
          ["O","Bit"],
          ["CLK",["Named","coreir.clkIn"]]
        ]],
        "instances":{
          "reg_P_inst0":{
            "genref":"coreir.reg",
            "genargs":{"width":["Int",1]},
            "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",1],"1'h0"]}
          }
        },
        "connections":[
          ["self.CLK","reg_P_inst0.clk"],
          ["self.I","reg_P_inst0.in.0"],
  [...]<jupyter_text>Here's an example of testing using fault's *staged* `Tester` class and the `verilator ` simulator.<jupyter_code>import fault
tester = fault.Tester(TFF, TFF.CLK)
for i in range(5):
    tester.step(2)
    tester.print("TFF.O=%d\n", TFF.O)
tester.compile_and_run("verilator", disp_type='realtime')<jupyter_output>[36m[1mRunning command: [0mverilator -Wall -Wno-INCABSPATH -Wno-DECLFILENAME --cc TFF.v --exe TFF_driver.cpp --top-module TFF
[36m[1mRunning command: [0mverilator --version
[35m[1m<STDOUT>[0m
Verilator 4.013 devel rev UNKNOWN_REV
[35m[1m</STDOUT>[0m
[36m[1mRunning command: [0mmake -C obj_dir -j -f VTFF.mk VTFF
[35m[1m<STDOUT>[0m
clang++  -I.  -MMD -I/usr/local/Cellar/verilator/HEAD-efa6f4c/share/verilator/include -I/usr/local/Cellar/verilator/HEAD-efa6f4c/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -faligned-new -fbracket-depth=4096 -Qunused-arguments -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-parameter -Wno-unused-variable -Wno-shadow       -c -o TFF_driver.o ../TFF_driver.cpp
/usr/bin/perl /usr/local/Cellar/verilator/HEAD-efa6f4c/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VTFF.cpp > VTFF__ALLcls.cpp
/usr/bin/perl /usr/local/Cellar/verilator/HEAD-efa6f4c/share/verilator/[...]
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