<commit_before>#!/usr/bin/env python3

#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>,
# Copyright (c) 2021 <NAME> <<EMAIL>>,
# SPDX-License-Identifier: BSD-2-Clause

import os
import argparse

from migen import *

from litex_boards.platforms import snickerdoodle
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict

from litex.soc.interconnect import axi
from litex.soc.interconnect import wishbone

from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *

from litex.build.generic_platform import Pins, IOStandard, Subsignal

# UTILS ---------------------------------------------------------------------------------------------

def load_ps7(soc, xci_file):
    odir = os.path.join("build", "snickerdoodle", "gateware", "xci")
    os.makedirs(odir, exist_ok=True)
    file = "snickerdoodle_ps7.xci"
    dst = os.path.join(odir, file)
    if xci_file is None:
        src = "https://technicaltoys-support.s3.amazonaws.com/xci/" + file
        os.system("wget " + src + " -O " + dst)
    else:
        os.system("cp -p  " + xci_file + " " + dst)
    soc.cpu.set_ps7_xci(dst)

class Blinky(Module):
    def __init__(self, led, sys_clk_freq, period=1e0):
        counter = Signal(max=int(period * sys_clk_freq))
        self.comb += led.eq(counter[counter.nbits-1])
        self.sync += counter.eq(counter + 1)

# CRG ----------------------------------------------------------------------------------------------

class _CRG(Module):
    def __init__(self, platform, sys_clk_freq, use_ps7_clk=False, ext_freq=10e6):
        self.rst = Signal()
        self.clock_domains.cd_sys = ClockDomain()

        # # #

        if use_ps7_clk:
            assert sys_clk_freq == 100e6
            self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
            self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
        else:
            self.submodules.pll = pll = S7MMCM(speedgrade=-1)
            self.comb += pll.reset.eq(self.rst)
            pll.register_clkin(platform.request(platform.default_clk_name),
                               platform.default_clk_freq)
            pll.create_clkout(self.cd_sys, sys_clk_freq)
            # Ignore sys_clk to pll.clkin path created by SoC's rst.
            platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)

# BaseSoC ------------------------------------------------------------------------------------------

class BaseSoC(SoCCore):

    def __init__(self,
                 sys_clk_freq = int(100e6),<commit_msg>Removed unused ext_freq parameter.<commit_after>#!/usr/bin/env python3

#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>,
# Copyright (c) 2021 <NAME> <<EMAIL>>,
# SPDX-License-Identifier: BSD-2-Clause

import os
import argparse

from migen import *

from litex_boards.platforms import snickerdoodle
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict

from litex.soc.interconnect import axi
from litex.soc.interconnect import wishbone

from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *

from litex.build.generic_platform import Pins, IOStandard, Subsignal

# UTILS ---------------------------------------------------------------------------------------------

def load_ps7(soc, xci_file):
    odir = os.path.join("build", "snickerdoodle", "gateware", "xci")
    os.makedirs(odir, exist_ok=True)
    file = "snickerdoodle_ps7.xci"
    dst = os.path.join(odir, file)
    if xci_file is None:
        src = "https://technicaltoys-support.s3.amazonaws.com/xci/" + file
        os.system("wget " + src + " -O " + dst)
    else:
        os.system("cp -p  " + xci_file + " " + dst)
    soc.cpu.set_ps7_xci(dst)

class Blinky(Module):
    def __init__(self, led, sys_clk_freq, period=1e0):
        counter = Signal(max=int(period * sys_clk_freq))
        self.comb += led.eq(counter[counter.nbits-1])
        self.sync += counter.eq(counter + 1)

# CRG ----------------------------------------------------------------------------------------------

class _CRG(Module):
    def __init__(self, platform, sys_clk_freq, use_ps7_clk=False):
        self.rst = Signal()
        self.clock_domains.cd_sys = ClockDomain()

        # # #

        if use_ps7_clk:
            assert sys_clk_freq == 100e6
            self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
            self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
        else:
            self.submodules.pll = pll = S7MMCM(speedgrade=-1)
            self.comb += pll.reset.eq(self.rst)
            pll.register_clkin(platform.request(platform.default_clk_name),
                               platform.default_clk_freq)
            pll.create_clkout(self.cd_sys, sys_clk_freq)
            # Ignore sys_clk to pll.clkin path created by SoC's rst.
            platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)

# BaseSoC ------------------------------------------------------------------------------------------

class BaseSoC(SoCCore):

    def __init__(self,
                 sys_clk_freq = int(100e6),
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