<commit_before>/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C $  */
/*                                                                        */
/* OpenPOWER HostBoot Project                                             */
/*                                                                        */
/* Contributors Listed Below - COPYRIGHT 2015,2019                        */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* Licensed under the Apache License, Version 2.0 (the "License");        */
/* you may not use this file except in compliance with the License.       */
/* You may obtain a copy of the License at                                */
/*                                                                        */
/*     http://www.apache.org/licenses/LICENSE-2.0                         */
/*                                                                        */
/* Unless required by applicable law or agreed to in writing, software    */
/* distributed under the License is distributed on an "AS IS" BASIS,      */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
/* implied. See the License for the specific language governing           */
/* permissions and limitations under the License.                         */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */
//-----------------------------------------------------------------------------------
///
/// @file p9_pcie_scominit.C
/// @brief Perform PCIE Phase1 init sequence (FAPI2)
///
// *HWP HWP Owner: <NAME> <EMAIL>
// *HWP FW Owner: <NAME> <EMAIL>
// *HWP Team: Nest
// *HWP Level: 2
// *HWP Consumed by: HB

//-----------------------------------------------------------------------------------
// Includes
//-----------------------------------------------------------------------------------
#include <p9_pcie_scominit.H>

#include <p9_misc_scom_addresses.H>
#include <p9_misc_scom_addresses_fixes.H>
#include <p9_misc_scom_addresses_fld.H>

/// @brief This function configures a buffer with respect to different pec id
///
/// @param[in]         in_target The target
/// @param[in/out]     io_buf  The buffer
/// @param[in]         in_pec_id The PEC id
/// @param[in]         in_attr The attribute value to be set
/// @param[in]         in_pec_id The PEC id
/// @param[in]         in_pec[0-2]_s The start bit for pec[0-2]
/// @param[in]         in_pec[0-2]_c The bit count for pec[0-2]
//
/// @return  FAPI2_RC_SUCCESS if success, else error code.

fapi2::ReturnCode set_buf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& in_target,
                          fapi2::buffer<uint64_t>& io_buf,
                          const int in_pec_id, const uint8_t in_attr,
                          const uint32_t in_pec0_s, const uint32_t in_pec0_c,
                          const uint32_t in_pec1_s, const uint32_t in_pec1_c,
                          const uint32_t in_pec2_s, const uint32_t in_pec2_c)
{
    switch(in_pec_id)
    {
        case 0:
            FAPI_TRY(io_buf.insertFromRight(in_attr, in_pec0_s, in_pec0_c));
            break;

        case 1:
            FAPI_TRY(io_buf.insertFromRight(in_attr, in_pec1_s, in_pec1_c));
            break;

        case 2:
            FAPI_TRY(io_buf.insertFromRight(in_attr, in_pec2_s, in_pec2_c));
            break;

        default:
            FAPI_ASSERT(false,
                        fapi2::P9_PCIE_SCOMINIT_PECID_ERROR().set_TARGET(in_target),
                        "Unknown PEC ID: %i!", in_pec_id);
            break;
    }

fapi_try_exit:
    return fapi2::current_err;
}

//-----------------------------------------------------------------------------------
// Function definitions
//-----------------------------------------------------------------------------------
fapi2::ReturnCode p9_pcie_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
    FAPI_INF("Start");
    uint8_t l_attr_proc_pcie_iop_config = 0;
    uint8_t l_attr_proc_pcie_iop_swap = 0;
    uint8_t l_attr_proc_pcie_iovalid_enable = 0;
    fapi2::buffer<uint64_t> l_buf = 0;
    unsigned char l_pec_id = 0;
    auto l_pec_chiplets_vec = i_target.getChildren<fapi2::TARGET_TYPE_PEC>();
    uint32_t l_pcs_config_mode[NUM_PCS_CONFIG] = {PCS_CONFIG_MODE0, PCS_CONFIG_MODE1, PCS_CONFIG_MODE2, PCS_CONFIG_MODE3};
    uint8_t l_pcs_cdr_gain[NUM_PCS_CONFIG] = {0};
    uint16_t l_pcs_loff_control[NUM_PCS_CONFIG] = {0};
    uint16_t l_pcs_vga_control_register3[NUM_PCS_CONFIG] = {0};
    uint16_t l_pcs_m_cntl[NUM_M_CONFIG] = {0};
    uint8_t l_pcs_rot_cntl_cdr_lookahead = 0;
    uint8_t l_pcs_rot_cntl_cdr_ssc = 0;
    uint8_t l_attr_8 = 0;
    uint16_t l_attr_16 = 0;

    FAPI_DBG("target vec size: %#x", l_pec_chiplets_vec.size());
    FAPI_DBG("l_buf: %#x", l_buf());

    for (auto l_pec_chiplets : l_pec_chiplets_vec)
    {
        // Get the pec id
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_pec_chiplets,
                               l_pec_id));

        // Phase1 init step 1 (get VPD, no operation here)

        // Phase1 init step 2a
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_IOP_CONFIG, l_pec_chiplets,
                               l_attr_proc_pcie_iop_config));
        FAPI_DBG("attr_proc_pcie_iop_config: %#x", l_attr_proc_pcie_iop_config);
        l_buf = 0;
        FAPI_TRY(set_buf(i_target, l_buf, l_pec_id, l_attr_proc_pcie_iop_config,
                         PEC0_IOP_CONFIG_START_BIT, PEC0_IOP_BIT_COUNT * 2,
                         PEC1_IOP_CONFIG_START_BIT, PEC1_IOP_BIT_COUNT * 2,
                         PEC2_IOP_CONFIG_START_BIT, PEC2_IOP_BIT_COUNT * 2));
        FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
        FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_CPLT_CONF1_OR, l_buf));

        // Phase1 init step 2b
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_IOP_SWAP, l_pec_chiplets,
                               l_attr_proc_pcie_iop_swap));
        FAPI_DBG("attr_proc_pcie_iop_swap: %#x", l_attr_proc_pcie_iop_swap);
        l_buf = 0;
        FAPI_TRY(set_buf(i_target, l_buf, l_pec_id, l_attr_proc_pcie_iop_swap,
                         PEC0_IOP_SWAP_START_BIT, PEC0_IOP_BIT_COUNT,
                         PEC1_IOP_SWAP_START_BIT, PEC1_IOP_BIT_COUNT,
                         PEC2_IOP_SWAP_START_BIT, PEC2_IOP_BIT_COUNT));
        FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
        FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_CPLT_CONF1_OR, l_buf));

        // Phase1 init step 3a
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_IOVALID_ENABLE, l_pec_chiplets,
                               l_attr_proc_pcie_iovalid_enable));
        FAPI_DBG("l_attr_proc_pcie_iovalid_enable: %#x", l_attr_proc_pcie_iovalid_enable);
        l_buf = 0;
        FAPI_TRY(set_buf(i_target, l_buf, l_pec_id, l_attr_proc_pcie_iovalid_enable,
                         PEC0_IOP_IOVALID_ENABLE_START_BIT, PEC0_IOP_BIT_COUNT,
                         PEC1_IOP_IOVALID_ENABLE_START_BIT, PEC1_IOP_BIT_COUNT,
                         PEC2_IOP_IOVALID_ENABLE_START_BIT, PEC2_IOP_BIT_COUNT));
        FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
        FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_CPLT_CONF1_OR, l_buf));

        // Phase1 init step 3b (enable clock)
        l_buf = 0;
        FAPI_TRY(l_buf.insertFromRight(1, PEC_CPLT_CTRL0_TC_REFCLK_DRVR_EN_DC, 1));
        FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
        FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_CPLT_CTRL0_OR, l_buf));<commit_msg>p9_pcie_scominit, support added for attribute refclock_enable<commit_after>/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C $  */
/*                                                                        */
/* OpenPOWER HostBoot Project                                             */
/*                                                                        */
/* Contributors Listed Below - COPYRIGHT 2015,2019                        */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* Licensed under the Apache License, Version 2.0 (the "License");        */
/* you may not use this file except in compliance with the License.       */
/* You may obtain a copy of the License at                                */
/*                                                                        */
/*     http://www.apache.org/licenses/LICENSE-2.0                         */
/*                                                                        */
/* Unless required by applicable law or agreed to in writing, software    */
/* distributed under the License is distributed on an "AS IS" BASIS,      */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
/* implied. See the License for the specific language governing           */
/* permissions and limitations under the License.                         */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */
//-----------------------------------------------------------------------------------
///
/// @file p9_pcie_scominit.C
/// @brief Perform PCIE Phase1 init sequence (FAPI2)
///
// *HWP HWP Owner: <NAME> <EMAIL>
// *HWP FW Owner: <NAME> <EMAIL>
// *HWP Team: Nest
// *HWP Level: 2
// *HWP Consumed by: HB

//-----------------------------------------------------------------------------------
// Includes
//-----------------------------------------------------------------------------------
#include <p9_pcie_scominit.H>

#include <p9_misc_scom_addresses.H>
#include <p9_misc_scom_addresses_fixes.H>
#include <p9_misc_scom_addresses_fld.H>

/// @brief This function configures a buffer with respect to different pec id
///
/// @param[in]         in_target The target
/// @param[in/out]     io_buf  The buffer
/// @param[in]         in_pec_id The PEC id
/// @param[in]         in_attr The attribute value to be set
/// @param[in]         in_pec_id The PEC id
/// @param[in]         in_pec[0-2]_s The start bit for pec[0-2]
/// @param[in]         in_pec[0-2]_c The bit count for pec[0-2]
//
/// @return  FAPI2_RC_SUCCESS if success, else error code.

fapi2::ReturnCode set_buf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& in_target,
                          fapi2::buffer<uint64_t>& io_buf,
                          const int in_pec_id, const uint8_t in_attr,
                          const uint32_t in_pec0_s, const uint32_t in_pec0_c,
                          const uint32_t in_pec1_s, const uint32_t in_pec1_c,
                          const uint32_t in_pec2_s, const uint32_t in_pec2_c)
{
    switch(in_pec_id)
    {
        case 0:
            FAPI_TRY(io_buf.insertFromRight(in_attr, in_pec0_s, in_pec0_c));
            break;

        case 1:
            FAPI_TRY(io_buf.insertFromRight(in_attr, in_pec1_s, in_pec1_c));
            break;

        case 2:
            FAPI_TRY(io_buf.insertFromRight(in_attr, in_pec2_s, in_pec2_c));
            break;

        default:
            FAPI_ASSERT(false,
                        fapi2::P9_PCIE_SCOMINIT_PECID_ERROR().set_TARGET(in_target),
                        "Unknown PEC ID: %i!", in_pec_id);
            break;
    }

fapi_try_exit:
    return fapi2::current_err;
}

//-----------------------------------------------------------------------------------
// Function definitions
//-----------------------------------------------------------------------------------
fapi2::ReturnCode p9_pcie_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
    FAPI_INF("Start");
    uint8_t l_attr_proc_pcie_iop_config = 0;
    uint8_t l_attr_proc_pcie_iop_swap = 0;
    uint8_t l_attr_proc_pcie_iovalid_enable = 0;
    uint8_t l_attr_proc_pcie_refclock_enable = 0;
    fapi2::buffer<uint64_t> l_buf = 0;
    unsigned char l_pec_id = 0;
    auto l_pec_chiplets_vec = i_target.getChildren<fapi2::TARGET_TYPE_PEC>();
    uint32_t l_pcs_config_mode[NUM_PCS_CONFIG] = {PCS_CONFIG_MODE0, PCS_CONFIG_MODE1, PCS_CONFIG_MODE2, PCS_CONFIG_MODE3};
    uint8_t l_pcs_cdr_gain[NUM_PCS_CONFIG] = {0};
    uint16_t l_pcs_loff_control[NUM_PCS_CONFIG] = {0};
    uint16_t l_pcs_vga_control_register3[NUM_PCS_CONFIG] = {0};
    uint16_t l_pcs_m_cntl[NUM_M_CONFIG] = {0};
    uint8_t l_pcs_rot_cntl_cdr_lookahead = 0;
    uint8_t l_pcs_rot_cntl_cdr_ssc = 0;
    uint8_t l_attr_8 = 0;
    uint16_t l_attr_16 = 0;

    FAPI_DBG("target vec size: %#x", l_pec_chiplets_vec.size());
    FAPI_DBG("l_buf: %#x", l_buf());

    for (auto l_pec_chiplets : l_pec_chiplets_vec)
    {
        // Get the pec id
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_pec_chiplets,
                               l_pec_id));

        // Phase1 init step 1 (get VPD, no operation here)

        // Phase1 init step 2a
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_IOP_CONFIG, l_pec_chiplets,
                               l_attr_proc_pcie_iop_config));
        FAPI_DBG("attr_proc_pcie_iop_config: %#x", l_attr_proc_pcie_iop_config);
        l_buf = 0;
        FAPI_TRY(set_buf(i_target, l_buf, l_pec_id, l_attr_proc_pcie_iop_config,
                         PEC0_IOP_CONFIG_START_BIT, PEC0_IOP_BIT_COUNT * 2,
                         PEC1_IOP_CONFIG_START_BIT, PEC1_IOP_BIT_COUNT * 2,
                         PEC2_IOP_CONFIG_START_BIT, PEC2_IOP_BIT_COUNT * 2));
        FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
        FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_CPLT_CONF1_OR, l_buf));

        // Phase1 init step 2b
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_IOP_SWAP, l_pec_chiplets,
                               l_attr_proc_pcie_iop_swap));
        FAPI_DBG("attr_proc_pcie_iop_swap: %#x", l_attr_proc_pcie_iop_swap);
        l_buf = 0;
        FAPI_TRY(set_buf(i_target, l_buf, l_pec_id, l_attr_proc_pcie_iop_swap,
                         PEC0_IOP_SWAP_START_BIT, PEC0_IOP_BIT_COUNT,
                         PEC1_IOP_SWAP_START_BIT, PEC1_IOP_BIT_COUNT,
                         PEC2_IOP_SWAP_START_BIT, PEC2_IOP_BIT_COUNT));
        FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
        FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_CPLT_CONF1_OR, l_buf));

        // Phase1 init step 3a
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_IOVALID_ENABLE, l_pec_chiplets,
                               l_attr_proc_pcie_iovalid_enable));
        FAPI_DBG("l_attr_proc_pcie_iovalid_enable: %#x", l_attr_proc_pcie_iovalid_enable);
        l_buf = 0;
        FAPI_TRY(set_buf(i_target, l_buf, l_pec_id, l_attr_proc_pcie_iovalid_enable,
                         PEC0_IOP_IOVALID_ENABLE_START_BIT, PEC0_IOP_BIT_COUNT,
                         PEC1_IOP_IOVALID_ENABLE_START_BIT, PEC1_IOP_BIT_COUNT,
                         PEC2_IOP_IOVALID_ENABLE_START_BIT, PEC2_IOP_BIT_COUNT));
        FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
        FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_CPLT_CONF1_OR, l_buf));

        // Phase1 init step 3b (enable clock)
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_PCIE_REFCLOCK_ENABLE, l_pec_chiplets, l_attr_proc_pcie_refclock_enable));
        FAPI_DBG("l_attr_proc_pcie_refclock_enable: %#x", l_attr_proc_pcie_refclock_enable);
        l_buf = 0;
        FAPI_TRY(l_buf.insertFromRight(l_attr_proc_pcie_refclock_enable, PEC_IOP_REFCLOCK_ENABLE_START_BIT, 1));
        FAPI_DBG("pec%i: %#lx", l_pec_id, l_buf());
        FAPI_TRY(fapi2::putScom(l_pec_chiplets, PEC_CPLT_CTRL0_OR, l_buf));
{'fraction_non_alphanumeric': 0.13907975460122698, 'fraction_numerical': 0.020245398773006136, 'mean_word_length': 1.601500159591446, 'pattern_counts': {'":': 0, '<': 29, '<?xml version=': 0, '>': 29, 'https://': 0, 'lorem ipsum': 0, 'www.': 2, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 62, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '5829160', 'n_tokens_mistral': 5528, 'n_tokens_neox': 5352, 'n_words': 915}