<commit_before>---
layout: home
title: SKiDL
description: Use Python to create circuits.
headline: SKiDL
tags: [Python, SKiDL, home]
---

# TL;DR

**Never use a lousy schematic editor again!**
SKiDL is a simple module that lets you describe electronic circuits using Python.
The resulting Python program outputs a netlist that a PCB layout tool uses to
create a finished circuit board.

### Contents

- [TL;DR](#tldr)
    - [Contents](#contents)
- [Introduction](#introduction)
- [Installation](#installation)
- [Basic Usage](#basic-usage)
  - [Accessing SKiDL](#accessing-skidl)
  - [Finding Parts](#finding-parts)
    - [Command-line Searching](#command-line-searching)
    - [Zyc: A GUI Search Tool](#zyc-a-gui-search-tool)
  - [Instantiating Parts](#instantiating-parts)
  - [Connecting Pins](#connecting-pins)
  - [Checking for Errors](#checking-for-errors)
  - [Generating a Netlist](#generating-a-netlist)
- [Going Deeper](#going-deeper)
  - [Basic SKiDL Objects: Parts, Pins, Nets, Buses](#basic-skidl-objects-parts-pins-nets-buses)
  - [Creating SKiDL Objects](#creating-skidl-objects)
  - [Finding SKiDL Objects](#finding-skidl-objects)
  - [Copying SKiDL Objects](#copying-skidl-objects)
  - [Accessing Part Pins and Bus Lines](#accessing-part-pins-and-bus-lines)
    - [Accessing Part Pins](#accessing-part-pins)
    - [Accessing Bus Lines](#accessing-bus-lines)
  - [Making Connections](#making-connections)
  - [Making Serial, Parallel, and Tee Networks](#making-serial-parallel-and-tee-networks)
  - [Aliases](#aliases)
  - [Units Within Parts](#units-within-parts)
  - [Part Fields](#part-fields)
  - [Hierarchy](#hierarchy)
    - [Subcircuits](#subcircuits)
    - [Packages](#packages)
  - [Interfaces](#interfaces)
  - [Libraries](#libraries)
  - [Doodads](#doodads)
    - [No Connects](#no-connects)
    - [Net and Pin Drive Levels](#net-and-pin-drive-levels)
    - [Pin, Net, Bus Equivalencies](#pin-net-bus-equivalencies)
    - [Selectively Supressing ERC Messages](#selectively-supressing-erc-messages)
    - [Customizable ERC Using `erc_assert()`](#customizable-erc-using-ercassert)
- [Going Really Deep](#going-really-deep)
  - [Circuit Objects](#circuit-objects)
- [Converting Existing Designs to SKiDL](#converting-existing-designs-to-skidl)
- [SPICE Simulations](#spice-simulations)



# Introduction

SKiDL is a module that allows you to compactly describe the interconnection of <commit_msg>Fix anchor link in index.md<commit_after>---
layout: home
title: SKiDL
description: Use Python to create circuits.
headline: SKiDL
tags: [Python, SKiDL, home]
---

# TL;DR

**Never use a lousy schematic editor again!**
SKiDL is a simple module that lets you describe electronic circuits using Python.
The resulting Python program outputs a netlist that a PCB layout tool uses to
create a finished circuit board.

### Contents

- [TL;DR](#tldr)
    - [Contents](#contents)
- [Introduction](#introduction)
- [Installation](#installation)
- [Basic Usage](#basic-usage)
  - [Accessing SKiDL](#accessing-skidl)
  - [Finding Parts](#finding-parts)
    - [Command-line Searching](#command-line-searching)
    - [Zyc: A GUI Search Tool](#zyc-a-gui-search-tool)
  - [Instantiating Parts](#instantiating-parts)
  - [Connecting Pins](#connecting-pins)
  - [Checking for Errors](#checking-for-errors)
  - [Generating a Netlist](#generating-a-netlist)
- [Going Deeper](#going-deeper)
  - [Basic SKiDL Objects: Parts, Pins, Nets, Buses](#basic-skidl-objects-parts-pins-nets-buses)
  - [Creating SKiDL Objects](#creating-skidl-objects)
  - [Finding SKiDL Objects](#finding-skidl-objects)
  - [Copying SKiDL Objects](#copying-skidl-objects)
  - [Accessing Part Pins and Bus Lines](#accessing-part-pins-and-bus-lines)
    - [Accessing Part Pins](#accessing-part-pins)
    - [Accessing Bus Lines](#accessing-bus-lines)
  - [Making Connections](#making-connections)
  - [Making Serial, Parallel, and Tee Networks](#making-serial-parallel-and-tee-networks)
  - [Aliases](#aliases)
  - [Units Within Parts](#units-within-parts)
  - [Part Fields](#part-fields)
  - [Hierarchy](#hierarchy)
    - [Subcircuits](#subcircuits)
    - [Packages](#packages)
  - [Interfaces](#interfaces)
  - [Libraries](#libraries)
  - [Doodads](#doodads)
    - [No Connects](#no-connects)
    - [Net and Pin Drive Levels](#net-and-pin-drive-levels)
    - [Pin, Net, Bus Equivalencies](#pin-net-bus-equivalencies)
    - [Selectively Supressing ERC Messages](#selectively-supressing-erc-messages)
    - [Customizable ERC Using `erc_assert()`](#customizable-erc-using-erc_assert)
- [Going Really Deep](#going-really-deep)
  - [Circuit Objects](#circuit-objects)
- [Converting Existing Designs to SKiDL](#converting-existing-designs-to-skidl)
- [SPICE Simulations](#spice-simulations)



# Introduction

SKiDL is a module that allows you to compactly describe the interconnection of 
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