<commit_before>// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

// Macro bodies included by prim_assert.sv for tools that support full SystemVerilog and SVA syntax.
// See prim_assert.sv for documentation for each of the macros.

`define ASSERT_I(__name, __prop) \
  __name: assert (__prop)        \
    else begin                   \
      `ASSERT_ERROR(__name)      \
    end

// Formal tools will ignore the initial construct, so use static assertion as a workaround.
// This workaround terminates design elaboration if the __prop predict is false.
// It calls $fatal() with the first argument equal to 2, it outputs the statistics about the memory
// and CPU time.
`define ASSERT_INIT(__name, __prop)                                                  \
`ifdef FPV_ON                                                                        \
  if (!(__prop)) $fatal(2, "Fatal static assertion [%s]: (%s) is not true.",         \
                        (__name), (__prop));                                         \
`else                                                                                \
  initial begin                                                                      \
    // #9017: Avoid race condition between the evaluation of assertion and `__prop`. \
    //                                                                               \
    // According to IEEE 1800-2017 SystemVerilog LRM, immediate assertions, unlike   \
    // concurrent assertions are evaluated in the active region set, as opposed to   \
    // the observed region. They are hence, susceptible to race conditions           \
    // (described in section 4.8). The #0 is an acceptable workaround for this.      \
    #0;                                                                              \
    __name: assert (__prop)                                                          \
      else begin                                                                     \
        `ASSERT_ERROR(__name)                                                        \
      end                                                                            \
  end                                                                                \
`endif

`define ASSERT_FINAL(__name, __prop)                                         \
  final begin                                                                \
    __name: assert (__prop || $test$plusargs("disable_assert_final_checks")) \
      else begin                                                             \
        `ASSERT_ERROR(__name)                                                \
      end                                                                    \
  end
<commit_msg>[prim_assert,dv] Use if condition in assert_init<commit_after>// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

// Macro bodies included by prim_assert.sv for tools that support full SystemVerilog and SVA syntax.
// See prim_assert.sv for documentation for each of the macros.

`define ASSERT_I(__name, __prop) \
  __name: assert (__prop)        \
    else begin                   \
      `ASSERT_ERROR(__name)      \
    end

// Formal tools will ignore the initial construct, so use static assertion as a workaround.
// This workaround terminates the design elaboration if __prop evaluates to false.
`define ASSERT_INIT(__name, __prop)                                                  \
`ifdef FPV_ON                                                                        \
  // The first argument to $fatal() call below, '2' enables the dumping of CPU time  \
  // and memory usage statistics.                                                    \
  if (!(__prop)) $fatal(2, "Fatal static assertion [%s]: (%s) is not true.",         \
                        (__name), (__prop));                                         \
`else                                                                                \
  initial begin                                                                      \
    // #9017: Avoid race condition between the evaluation of assertion and `__prop`. \
    //                                                                               \
    // According to IEEE 1800-2017 SystemVerilog LRM, immediate assertions, unlike   \
    // concurrent assertions are evaluated in the active region set, as opposed to   \
    // the observed region. They are hence, susceptible to race conditions           \
    // (described in section 4.8). The #0 is an acceptable workaround for this.      \
    //                                                                               \
    // In this context, the assert and if condition exhibit the same behavior, so we \
    // replace it with if statement instead.                                         \
    #0;                                                                              \
    if (!(__prop)) begin: __name                                                     \
      `ASSERT_ERROR(__name)                                                          \
    end                                                                              \
  end                                                                                \
`endif

`define ASSERT_FINAL(__name, __prop)                                               \
  final begin                                                                      \
    if (!(__prop) && !$test$plusargs("disable_assert_final_checks")) begin: __name \
      `ASSERT_ERROR(__name)                                                        \
    end                                                                            \
  end

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