<commit_before>/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2010-2017 Intel Corporation
 */

#include "test.h"

#include <unistd.h>
#include <string.h>
#include <rte_mempool.h>
#include <rte_cycles.h>
#include <rte_common.h>
#include <rte_mbuf.h>
#include <rte_distributor.h>
#include <rte_pause.h>

#define ITER_POWER_CL 25 /* log 2 of how many iterations  for Cache Line test */
#define ITER_POWER 21 /* log 2 of how many iterations we do when timing. */
#define BURST 64
#define BIG_BATCH 1024

/* static vars - zero initialized by default */
static volatile int quit;
static volatile unsigned worker_idx;

struct worker_stats {
	volatile unsigned handled_packets;
} __rte_cache_aligned;
struct worker_stats worker_stats[RTE_MAX_LCORE];

/*
 * worker thread used for testing the time to do a round-trip of a cache
 * line between two cores and back again
 */
static void
flip_bit(volatile uint64_t *arg)
{
	uint64_t old_val = 0;
	while (old_val != 2) {
		while (!*arg)
			rte_pause();
		old_val = *arg;
		*arg = 0;
	}
}

/*
 * test case to time the number of cycles to round-trip a cache line between
 * two cores and back again.
 */
static void
time_cache_line_switch(void)
{
	/* allocate a full cache line for data, we use only first byte of it */
	uint64_t data[RTE_CACHE_LINE_SIZE*3 / sizeof(uint64_t)];

	unsigned i, slaveid = rte_get_next_lcore(rte_lcore_id(), 0, 0);
	volatile uint64_t *pdata = &data[0];
	*pdata = 1;
	rte_eal_remote_launch((lcore_function_t *)flip_bit, &data[0], slaveid);
	while (*pdata)
		rte_pause();

	const uint64_t start_time = rte_rdtsc();
	for (i = 0; i < (1 << ITER_POWER_CL); i++) {
		while (*pdata)<commit_msg>test/distributor: fix return type of thread function<commit_after>/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2010-2017 Intel Corporation
 */

#include "test.h"

#include <unistd.h>
#include <string.h>
#include <rte_mempool.h>
#include <rte_cycles.h>
#include <rte_common.h>
#include <rte_mbuf.h>
#include <rte_distributor.h>
#include <rte_pause.h>

#define ITER_POWER_CL 25 /* log 2 of how many iterations  for Cache Line test */
#define ITER_POWER 21 /* log 2 of how many iterations we do when timing. */
#define BURST 64
#define BIG_BATCH 1024

/* static vars - zero initialized by default */
static volatile int quit;
static volatile unsigned worker_idx;

struct worker_stats {
	volatile unsigned handled_packets;
} __rte_cache_aligned;
struct worker_stats worker_stats[RTE_MAX_LCORE];

/*
 * worker thread used for testing the time to do a round-trip of a cache
 * line between two cores and back again
 */
static int
flip_bit(volatile uint64_t *arg)
{
	uint64_t old_val = 0;
	while (old_val != 2) {
		while (!*arg)
			rte_pause();
		old_val = *arg;
		*arg = 0;
	}
	return 0;
}

/*
 * test case to time the number of cycles to round-trip a cache line between
 * two cores and back again.
 */
static void
time_cache_line_switch(void)
{
	/* allocate a full cache line for data, we use only first byte of it */
	uint64_t data[RTE_CACHE_LINE_SIZE*3 / sizeof(uint64_t)];

	unsigned i, slaveid = rte_get_next_lcore(rte_lcore_id(), 0, 0);
	volatile uint64_t *pdata = &data[0];
	*pdata = 1;
	rte_eal_remote_launch((lcore_function_t *)flip_bit, &data[0], slaveid);
	while (*pdata)
		rte_pause();

	const uint64_t start_time = rte_rdtsc();
	for (i = 0; i < (1 << ITER_POWER_CL); i++) {
		while (*pdata)
{'fraction_non_alphanumeric': 0.11361613764461584, 'fraction_numerical': 0.02640166122812222, 'mean_word_length': 4.412520064205458, 'pattern_counts': {'":': 0, '<': 25, '<?xml version=': 0, '>': 19, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '6254822', 'n_tokens_mistral': 1336, 'n_tokens_neox': 1234, 'n_words': 387}