<commit_before><!--* freshness: {
  owner: 'azalia'
  owner: 'tobyboyd'
  owner: 'sguada'
  owner: 'morpheus-oss-team'
  reviewed: '2022-01-11'
  review_interval: '12 months'
} *-->


# Circuit Training: An open-source framework for generating chip floor plans with distributed deep reinforcement learning.

*Circuit Training* is an open-source framework for generating chip floor plans
with distributed deep reinforcement learning. This framework reproduces the
methodology published in the Nature 2021 paper:

*[A graph placement methodology for fast chip design.](https://www.nature.com/articles/s41586-021-03544-w) <NAME>., <NAME>.,
<NAME>., <NAME>., <NAME>., <NAME>., <NAME>., <NAME>., <NAME>., <NAME>. and <NAME>., 2021. Nature, 594(7862), pp.207-212. [[PDF]](https://www.nature.com/articles/s41586-021-03544-w.epdf?sharing_token=<PASSWORD>VSBxWSp<PASSWORD>YnEXoBE4esRDSWqubhDFWUPyI5wK_5B_YIO-D_kS8%3D)*


Our hope is that *Circuit Training* will foster further collaborations between
academia and industry, and enable advances in deep reinforcement learning for
Electronic Design Automation, as well as, general combinatorial and decision
making optimization problems. Capable of optimizing chip blocks with hundreds of
macros, *Circuit Training* automatically generates floor plans in hours, whereas
baseline methods often require human experts in the loop and can take months.

Circuit training is built on top of [TF-Agents](https://github.com/tensorflow/agents)
and [TensorFlow 2.x](https://www.tensorflow.org/) with support for<commit_msg>Increase list of authors.<commit_after><!--* freshness: {
  owner: 'azalia'
  owner: 'tobyboyd'
  owner: 'sguada'
  owner: 'morpheus-oss-team'
  reviewed: '2022-01-11'
  review_interval: '12 months'
} *-->


# Circuit Training: An open-source framework for generating chip floor plans with distributed deep reinforcement learning.

*Circuit Training* is an open-source framework for generating chip floor plans
with distributed deep reinforcement learning. This framework reproduces the
methodology published in the Nature 2021 paper:

*[A graph placement methodology for fast chip design.](https://www.nature.com/articles/s41586-021-03544-w) <NAME>, <NAME>, <NAME>, <NAME>, <NAME>, <NAME>, <NAME>, <NAME>, <NAME>, <NAME>, <NAME>, <NAME>, <NAME>, <NAME>, <NAME>, <NAME>, <NAME>, <NAME>, <NAME> & <NAME>, 2021. Nature, 594(7862), pp.207-212. [[PDF]](https://www.nature.com/articles/s41586-021-03544-w.epdf?sharing_token=<KEY>A-E1yNUWVMMVSBxWSp7ZFFIWawYQYnEXoBE4esRDSWqubhDFWUPyI5wK_5B_YIO-D_kS8%3D)*

Our hope is that *Circuit Training* will foster further collaborations between
academia and industry, and enable advances in deep reinforcement learning for
Electronic Design Automation, as well as, general combinatorial and decision
making optimization problems. Capable of optimizing chip blocks with hundreds of
macros, *Circuit Training* automatically generates floor plans in hours, whereas
baseline methods often require human experts in the loop and can take months.

Circuit training is built on top of [TF-Agents](https://github.com/tensorflow/agents)
and [TensorFlow 2.x](https://www.tensorflow.org/) with support for
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