<commit_before>/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: src/usr/isteps/istep06/thread_activate/thread_activate.C $    */
/*                                                                        */
/* OpenPOWER HostBoot Project                                             */
/*                                                                        */
/* Contributors Listed Below - COPYRIGHT 2012,2016                        */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* Licensed under the Apache License, Version 2.0 (the "License");        */
/* you may not use this file except in compliance with the License.       */
/* You may obtain a copy of the License at                                */
/*                                                                        */
/*     http://www.apache.org/licenses/LICENSE-2.0                         */
/*                                                                        */
/* Unless required by applicable law or agreed to in writing, software    */
/* distributed under the License is distributed on an "AS IS" BASIS,      */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
/* implied. See the License for the specific language governing           */
/* permissions and limitations under the License.                         */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */
/**
 *  @file thread_activate.C
 *
 *  Support file to start non-primary threads
 *
 *  HWP_IGNORE_VERSION_CHECK
 *
 */

/******************************************************************************/
// Includes
/******************************************************************************/
#include    <stdint.h>

#include    <initservice/taskargs.H>
#include    <errl/errlentry.H>

#include    <devicefw/userif.H>
#include    <sys/misc.h>
#include    <sys/mm.h>
#include    <p9_thread_control.H>
#include    <arch/pirformat.H>

//  targeting support
#include    <targeting/common/target.H>
#include    <targeting/common/commontargeting.H>
#include    <targeting/common/utilFilter.H>

//  fapi support
#include    <fapi2.H>
#include    <fapi2_target.H>
#include    <fapi2_hw_access.H>
#include    <plat_hwp_invoker.H>
#include    <istep_reasoncodes.H>
#include    <p9_cpu_special_wakeup.H>

#include    <pnor/pnorif.H>
#include    <vpd/mvpdenums.H>
#include    <vfs/vfs.H>

namespace   THREAD_ACTIVATE
{

/**
 * @brief This function will query MVPD and figure out if the master
 *        core has a fully configured cache or not..
 *
 * @param[in] i_masterCoreId - Core number of the core we're running on.
 *
 *
 * @return bool - Indicates if half of cache is deconfigured or not.
 *                true - half cache deconfigured, only 4MB available
 *                false -> No Cache deconfigured, 8MB available.
*/
bool getCacheDeconfig(uint64_t i_masterCoreId)
{
    TRACFCOMP( g_fapiImpTd,
               "Entering getCacheDeconfig, i_masterCoreId=0x%.8X",
               i_masterCoreId);

    //CH Keyword in LPRx Record of MVPD contains the Cache Deconfig State
    //the x in LPRx is the core number.
    errlHndl_t  l_errl  =   NULL;
    bool cacheDeconfig = true;
    uint64_t theRecord = 0x0;
    uint64_t theKeyword = MVPD::CH;
    uint8_t * theData = NULL;
    size_t theSize = 0;
    TARGETING::Target* l_procTarget = NULL;

    do {
        // Target: Find the Master processor
        TARGETING::targetService().masterProcChipTargetHandle(l_procTarget);
        assert(l_procTarget != NULL);

        //Convert core number to LPRx Record ID.
        //TODO: use a common utility function for conversion. RTC: 60552
        switch (i_masterCoreId)
        {
        case 0x0:
            theRecord = MVPD::LRP0;
            break;
        case 0x1:
            theRecord = MVPD::LRP1;
            break;
        case 0x2:
            theRecord = MVPD::LRP2;
            break;
        case 0x3:
            theRecord = MVPD::LRP3;
            break;
        case 0x4:
            theRecord = MVPD::LRP4;
            break;
        case 0x5:
            theRecord = MVPD::LRP5;
            break;
        default:
            TRACFCOMP( g_fapiImpTd,
                       "getCacheDeconfig: No MVPD Record for core 0x%.8X",
                       i_masterCoreId);
            /*@
             * @errortype
             * @moduleid     ISTEP::MOD_GET_CACHE_DECONFIG
             * @reasoncode   ISTEP::RC_INVALID_RECORD
             * @userdata1    Master Core Number
             * @userdata2    Master processor chip huid
             * @devdesc      getCacheDeconfig> Master core is not mapped
             *               to a LRPx Module VPD Record.
             * @custdesc     A problem occurred during the IPL
             *               of the system.
             */<commit_msg>RC_INCORRECT_KEWORD_SIZE on zzfp018<commit_after>/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: src/usr/isteps/istep06/thread_activate/thread_activate.C $    */
/*                                                                        */
/* OpenPOWER HostBoot Project                                             */
/*                                                                        */
/* Contributors Listed Below - COPYRIGHT 2012,2016                        */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* Licensed under the Apache License, Version 2.0 (the "License");        */
/* you may not use this file except in compliance with the License.       */
/* You may obtain a copy of the License at                                */
/*                                                                        */
/*     http://www.apache.org/licenses/LICENSE-2.0                         */
/*                                                                        */
/* Unless required by applicable law or agreed to in writing, software    */
/* distributed under the License is distributed on an "AS IS" BASIS,      */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
/* implied. See the License for the specific language governing           */
/* permissions and limitations under the License.                         */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */
/**
 *  @file thread_activate.C
 *
 *  Support file to start non-primary threads
 *
 *  HWP_IGNORE_VERSION_CHECK
 *
 */

/******************************************************************************/
// Includes
/******************************************************************************/
#include    <stdint.h>

#include    <initservice/taskargs.H>
#include    <errl/errlentry.H>

#include    <devicefw/userif.H>
#include    <sys/misc.h>
#include    <sys/mm.h>
#include    <p9_thread_control.H>
#include    <arch/pirformat.H>

//  targeting support
#include    <targeting/common/target.H>
#include    <targeting/common/commontargeting.H>
#include    <targeting/common/utilFilter.H>

//  fapi support
#include    <fapi2.H>
#include    <fapi2_target.H>
#include    <fapi2_hw_access.H>
#include    <plat_hwp_invoker.H>
#include    <istep_reasoncodes.H>
#include    <p9_cpu_special_wakeup.H>

#include    <pnor/pnorif.H>
#include    <vpd/mvpdenums.H>
#include    <vfs/vfs.H>

namespace   THREAD_ACTIVATE
{

/**
 * @brief This function will query MVPD and figure out if the master
 *        core has a fully configured cache or not..
 *
 * @param[in] i_masterCoreId - Core number of the core we're running on.
 *
 *
 * @return bool - Indicates if half of cache is deconfigured or not.
 *                true - half cache deconfigured, only 4MB available
 *                false -> No Cache deconfigured, 8MB available.
*/
bool getCacheDeconfig(uint64_t i_masterCoreId)
{
    TRACFCOMP( g_fapiImpTd,
               "Entering getCacheDeconfig, i_masterCoreId=0x%.8X",
               i_masterCoreId);

    //CH Keyword in LPRx Record of MVPD contains the Cache Deconfig State
    //the x in LPRx is the EQ number.
    errlHndl_t  l_errl  =   NULL;
    bool cacheDeconfig = true;
    uint64_t theRecord = 0x0;
    uint64_t theKeyword = MVPD::CH;
    uint8_t * theData = NULL;
    size_t theSize = 0;
    TARGETING::Target* l_procTarget = NULL;

    do {
        // Target: Find the Master processor
        TARGETING::targetService().masterProcChipTargetHandle(l_procTarget);
        assert(l_procTarget != NULL);

        //Convert core number to LPRx Record ID.
        //TODO: use a common utility function for conversion. RTC: 60552
        switch (i_masterCoreId)
        {
        case 0x00:
        case 0x01:
        case 0x02:
        case 0x03:
            theRecord = MVPD::LRP0;
            break;
        case 0x04:
        case 0x05:
        case 0x06:
        case 0x07:
            theRecord = MVPD::LRP1;
            break;
        case 0x08:
        case 0x09:
        case 0x0A:
        case 0x0B:
            theRecord = MVPD::LRP2;
            break;
        case 0x0C:
        case 0x0D:
        case 0x0E:
        case 0x0F:
            theRecord = MVPD::LRP3;
            break;
        case 0x10:
        case 0x11:
        case 0x12:
        case 0x13:
            theRecord = MVPD::LRP4;
            break;
        case 0x14:
        case 0x15:
        case 0x16:
        case 0x17:
            theRecord = MVPD::LRP5;
            break;
        default:
            TRACFCOMP( g_fapiImpTd,
                       "getCacheDeconfig: No MVPD Record for core 0x%.8X",
                       i_masterCoreId);
            /*@
             * @errortype
             * @moduleid     ISTEP::MOD_GET_CACHE_DECONFIG
             * @reasoncode   ISTEP::RC_INVALID_RECORD
             * @userdata1    Master Core Number
             * @userdata2    Master processor chip huid
             * @devdesc      getCacheDeconfig> Master core is not mapped
             *               to a LRPx Module VPD Record.
             * @custdesc     A problem occurred during the IPL
             *               of the system.
             */
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