<commit_before>#include "memory_manager.h"
#include "cache_base.h"
#include "simulator.h"
#include "network.h"
#include "network_model_emesh_hop_by_hop_generic.h"
#include "log.h"

namespace PrL1PrL2DramDirectoryMOSI
{

MemoryManager::MemoryManager(Core* core, 
      Network* network, ShmemPerfModel* shmem_perf_model):
   MemoryManagerBase(core, network, shmem_perf_model),
   m_dram_directory_cntlr(NULL),
   m_dram_cntlr(NULL),
   m_dram_cntlr_present(false),
   m_enabled(false)
{
   // Read Parameters from the Config file
   volatile float core_frequency = 0.0;

   UInt32 l1_icache_size = 0;
   UInt32 l1_icache_associativity = 0;
   std::string l1_icache_replacement_policy;
   UInt32 l1_icache_data_access_time = 0;
   UInt32 l1_icache_tags_access_time = 0;
   std::string l1_icache_perf_model_type;

   UInt32 l1_dcache_size = 0;
   UInt32 l1_dcache_associativity = 0;
   std::string l1_dcache_replacement_policy;
   UInt32 l1_dcache_data_access_time = 0;
   UInt32 l1_dcache_tags_access_time = 0;
   std::string l1_dcache_perf_model_type;

   UInt32 l2_cache_size = 0;
   UInt32 l2_cache_associativity = 0;
   std::string l2_cache_replacement_policy;
   UInt32 l2_cache_data_access_time = 0;
   UInt32 l2_cache_tags_access_time = 0;
   std::string l2_cache_perf_model_type;

   UInt32 dram_directory_total_entries = 0;
   UInt32 dram_directory_associativity = 0;
   UInt32 dram_directory_max_num_sharers = 0;
   UInt32 dram_directory_max_hw_sharers = 0;
   std::string dram_directory_type_str;
   UInt32 dram_directory_home_lookup_param = 0;
   UInt32 dram_directory_cache_access_time = 0;

   volatile float dram_latency = 0.0;
   volatile float per_dram_controller_bandwidth = 0.0;
   bool dram_queue_model_enabled = false;
   std::string dram_queue_model_type;

   std::string unicast_network_type_lt_threshold;
   std::string unicast_network_type_ge_threshold;
   std::string broadcast_network_type;

   try
   {
      core_frequency = Sim()->getCfg()->getFloat("perf_model/core/frequency");

      m_cache_block_size = Sim()->getCfg()->getInt("perf_model/l1_icache/cache_block_size");

      // L1 ICache
      l1_icache_size = Sim()->getCfg()->getInt("perf_model/l1_icache/cache_size");
      l1_icache_associativity = Sim()->getCfg()->getInt("perf_model/l1_icache/associativity");
      l1_icache_replacement_policy = Sim()->getCfg()->getString("perf_model/l1_icache/replacement_policy");
      l1_icache_data_access_time = Sim()->getCfg()->getInt("perf_model/l1_icache/data_access_time");
      l1_icache_tags_access_time = Sim()->getCfg()->getInt("perf_model/l1_icache/tags_access_time");
      l1_icache_perf_model_type = Sim()->getCfg()->getString("perf_model/l1_icache/perf_model_type");

      // L1 DCache
      l1_dcache_size = Sim()->getCfg()->getInt("perf_model/l1_dcache/cache_size");
      l1_dcache_associativity = Sim()->getCfg()->getInt("perf_model/l1_dcache/associativity");
      l1_dcache_replacement_policy = Sim()->getCfg()->getString("perf_model/l1_dcache/replacement_policy");
      l1_dcache_data_access_time = Sim()->getCfg()->getInt("perf_model/l1_dcache/data_access_time");
      l1_dcache_tags_access_time = Sim()->getCfg()->getInt("perf_model/l1_dcache/tags_access_time");
      l1_dcache_perf_model_type = Sim()->getCfg()->getString("perf_model/l1_dcache/perf_model_type");

      // L2 Cache
      l2_cache_size = Sim()->getCfg()->getInt("perf_model/l2_cache/cache_size");
      l2_cache_associativity = Sim()->getCfg()->getInt("perf_model/l2_cache/associativity");
      l2_cache_replacement_policy = Sim()->getCfg()->getString("perf_model/l2_cache/replacement_policy");
      l2_cache_data_access_time = Sim()->getCfg()->getInt("perf_model/l2_cache/data_access_time");
      l2_cache_tags_access_time = Sim()->getCfg()->getInt("perf_model/l2_cache/tags_access_time");
      l2_cache_perf_model_type = Sim()->getCfg()->getString("perf_model/l2_cache/perf_model_type");

      // Dram Directory Cache
      dram_directory_total_entries = Sim()->getCfg()->getInt("perf_model/dram_directory/total_entries");
      dram_directory_associativity = Sim()->getCfg()->getInt("perf_model/dram_directory/associativity");
      dram_directory_max_num_sharers = Sim()->getConfig()->getTotalCores();
      dram_directory_max_hw_sharers = Sim()->getCfg()->getInt("perf_model/dram_directory/max_hw_sharers");
      dram_directory_type_str = Sim()->getCfg()->getString("perf_model/dram_directory/directory_type");
      dram_directory_home_lookup_param = Sim()->getCfg()->getInt("perf_model/dram_directory/home_lookup_param");
      dram_directory_cache_access_time = Sim()->getCfg()->getInt("perf_model/dram_directory/directory_cache_access_time");

      // Dram Cntlr
      dram_latency = Sim()->getCfg()->getFloat("perf_model/dram/latency");
      per_dram_controller_bandwidth = Sim()->getCfg()->getFloat("perf_model/dram/per_controller_bandwidth");
      dram_queue_model_enabled = Sim()->getCfg()->getBool("perf_model/dram/queue_model/enabled");
      dram_queue_model_type = Sim()->getCfg()->getString("perf_model/dram/queue_model/type");

      // Packet Types
      m_unicast_threshold = Sim()->getCfg()->getInt("caching_protocol/pr_l1_pr_l2_dram_directory_mosi/unicast_threshold");
      unicast_network_type_lt_threshold = Sim()->getCfg()->getString("caching_protocol/pr_l1_pr_l2_dram_directory_mosi/unicast_network_type_lt_threshold");
      unicast_network_type_ge_threshold = Sim()->getCfg()->getString("caching_protocol/pr_l1_pr_l2_dram_directory_mosi/unicast_network_type_ge_threshold");
      broadcast_network_type = Sim()->getCfg()->getString("caching_protocol/pr_l1_pr_l2_dram_directory_mosi/broadcast_network_type");
   }
   catch(...)
   {
      LOG_PRINT_ERROR("Error reading memory system parameters from the config file");
   }

   m_user_thread_sem = new Semaphore(0);
   m_network_thread_sem = new Semaphore(0);

   std::vector<core_id_t> core_list_with_dram_controllers = getCoreListWithMemoryControllers();
   
   if (getCore()->getId() == 0)
      printCoreListWithMemoryControllers(core_list_with_dram_controllers);
   
   if (find(core_list_with_dram_controllers.begin(), core_list_with_dram_controllers.end(), getCore()->getId()) != core_list_with_dram_controllers.end())
   {
      m_dram_cntlr_present = true;<commit_msg>[shared mem] Removed the WARNING statement from memory manager<commit_after>#include "memory_manager.h"
#include "cache_base.h"
#include "simulator.h"
#include "network.h"
#include "network_model_emesh_hop_by_hop_generic.h"
#include "log.h"

namespace PrL1PrL2DramDirectoryMOSI
{

MemoryManager::MemoryManager(Core* core, 
      Network* network, ShmemPerfModel* shmem_perf_model):
   MemoryManagerBase(core, network, shmem_perf_model),
   m_dram_directory_cntlr(NULL),
   m_dram_cntlr(NULL),
   m_dram_cntlr_present(false),
   m_enabled(false)
{
   // Read Parameters from the Config file
   volatile float core_frequency = 0.0;

   UInt32 l1_icache_size = 0;
   UInt32 l1_icache_associativity = 0;
   std::string l1_icache_replacement_policy;
   UInt32 l1_icache_data_access_time = 0;
   UInt32 l1_icache_tags_access_time = 0;
   std::string l1_icache_perf_model_type;

   UInt32 l1_dcache_size = 0;
   UInt32 l1_dcache_associativity = 0;
   std::string l1_dcache_replacement_policy;
   UInt32 l1_dcache_data_access_time = 0;
   UInt32 l1_dcache_tags_access_time = 0;
   std::string l1_dcache_perf_model_type;

   UInt32 l2_cache_size = 0;
   UInt32 l2_cache_associativity = 0;
   std::string l2_cache_replacement_policy;
   UInt32 l2_cache_data_access_time = 0;
   UInt32 l2_cache_tags_access_time = 0;
   std::string l2_cache_perf_model_type;

   UInt32 dram_directory_total_entries = 0;
   UInt32 dram_directory_associativity = 0;
   UInt32 dram_directory_max_num_sharers = 0;
   UInt32 dram_directory_max_hw_sharers = 0;
   std::string dram_directory_type_str;
   UInt32 dram_directory_home_lookup_param = 0;
   UInt32 dram_directory_cache_access_time = 0;

   volatile float dram_latency = 0.0;
   volatile float per_dram_controller_bandwidth = 0.0;
   bool dram_queue_model_enabled = false;
   std::string dram_queue_model_type;

   std::string unicast_network_type_lt_threshold;
   std::string unicast_network_type_ge_threshold;
   std::string broadcast_network_type;

   try
   {
      core_frequency = Sim()->getCfg()->getFloat("perf_model/core/frequency");

      m_cache_block_size = Sim()->getCfg()->getInt("perf_model/l1_icache/cache_block_size");

      // L1 ICache
      l1_icache_size = Sim()->getCfg()->getInt("perf_model/l1_icache/cache_size");
      l1_icache_associativity = Sim()->getCfg()->getInt("perf_model/l1_icache/associativity");
      l1_icache_replacement_policy = Sim()->getCfg()->getString("perf_model/l1_icache/replacement_policy");
      l1_icache_data_access_time = Sim()->getCfg()->getInt("perf_model/l1_icache/data_access_time");
      l1_icache_tags_access_time = Sim()->getCfg()->getInt("perf_model/l1_icache/tags_access_time");
      l1_icache_perf_model_type = Sim()->getCfg()->getString("perf_model/l1_icache/perf_model_type");

      // L1 DCache
      l1_dcache_size = Sim()->getCfg()->getInt("perf_model/l1_dcache/cache_size");
      l1_dcache_associativity = Sim()->getCfg()->getInt("perf_model/l1_dcache/associativity");
      l1_dcache_replacement_policy = Sim()->getCfg()->getString("perf_model/l1_dcache/replacement_policy");
      l1_dcache_data_access_time = Sim()->getCfg()->getInt("perf_model/l1_dcache/data_access_time");
      l1_dcache_tags_access_time = Sim()->getCfg()->getInt("perf_model/l1_dcache/tags_access_time");
      l1_dcache_perf_model_type = Sim()->getCfg()->getString("perf_model/l1_dcache/perf_model_type");

      // L2 Cache
      l2_cache_size = Sim()->getCfg()->getInt("perf_model/l2_cache/cache_size");
      l2_cache_associativity = Sim()->getCfg()->getInt("perf_model/l2_cache/associativity");
      l2_cache_replacement_policy = Sim()->getCfg()->getString("perf_model/l2_cache/replacement_policy");
      l2_cache_data_access_time = Sim()->getCfg()->getInt("perf_model/l2_cache/data_access_time");
      l2_cache_tags_access_time = Sim()->getCfg()->getInt("perf_model/l2_cache/tags_access_time");
      l2_cache_perf_model_type = Sim()->getCfg()->getString("perf_model/l2_cache/perf_model_type");

      // Dram Directory Cache
      dram_directory_total_entries = Sim()->getCfg()->getInt("perf_model/dram_directory/total_entries");
      dram_directory_associativity = Sim()->getCfg()->getInt("perf_model/dram_directory/associativity");
      dram_directory_max_num_sharers = Sim()->getConfig()->getTotalCores();
      dram_directory_max_hw_sharers = Sim()->getCfg()->getInt("perf_model/dram_directory/max_hw_sharers");
      dram_directory_type_str = Sim()->getCfg()->getString("perf_model/dram_directory/directory_type");
      dram_directory_home_lookup_param = Sim()->getCfg()->getInt("perf_model/dram_directory/home_lookup_param");
      dram_directory_cache_access_time = Sim()->getCfg()->getInt("perf_model/dram_directory/directory_cache_access_time");

      // Dram Cntlr
      dram_latency = Sim()->getCfg()->getFloat("perf_model/dram/latency");
      per_dram_controller_bandwidth = Sim()->getCfg()->getFloat("perf_model/dram/per_controller_bandwidth");
      dram_queue_model_enabled = Sim()->getCfg()->getBool("perf_model/dram/queue_model/enabled");
      dram_queue_model_type = Sim()->getCfg()->getString("perf_model/dram/queue_model/type");

      // Packet Types
      m_unicast_threshold = Sim()->getCfg()->getInt("caching_protocol/pr_l1_pr_l2_dram_directory_mosi/unicast_threshold");
      unicast_network_type_lt_threshold = Sim()->getCfg()->getString("caching_protocol/pr_l1_pr_l2_dram_directory_mosi/unicast_network_type_lt_threshold");
      unicast_network_type_ge_threshold = Sim()->getCfg()->getString("caching_protocol/pr_l1_pr_l2_dram_directory_mosi/unicast_network_type_ge_threshold");
      broadcast_network_type = Sim()->getCfg()->getString("caching_protocol/pr_l1_pr_l2_dram_directory_mosi/broadcast_network_type");
   }
   catch(...)
   {
      LOG_PRINT_ERROR("Error reading memory system parameters from the config file");
   }

   m_user_thread_sem = new Semaphore(0);
   m_network_thread_sem = new Semaphore(0);

   std::vector<core_id_t> core_list_with_dram_controllers = getCoreListWithMemoryControllers();
   if (getCore()->getId() == 0)
      printCoreListWithMemoryControllers(core_list_with_dram_controllers);
   
   if (find(core_list_with_dram_controllers.begin(), core_list_with_dram_controllers.end(), getCore()->getId()) != core_list_with_dram_controllers.end())
   {
      m_dram_cntlr_present = true;
{'fraction_non_alphanumeric': 0.12308910891089109, 'fraction_numerical': 0.020752475247524754, 'mean_word_length': 5.733866666666667, 'pattern_counts': {'":': 0, '<': 5, '<?xml version=': 0, '>': 149, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '3023536', 'n_tokens_mistral': 4495, 'n_tokens_neox': 4406, 'n_words': 483}