<commit_before>#!/usr/bin/env python

import fileinput
import sys
import re
import os
import math

if( __name__ == '__main__' ):

  if( len(sys.argv) < 3 ):
    print 'Usage: v2pymtl.py [model name] [verilog file]'
    sys.exit()

  model_name = sys.argv[1]
  filename_v = sys.argv[2]

  filename_pyx = model_name + '.pyx'
  filename_w = 'W' + model_name + '.py'
  vobj_name = 'V' + model_name

  # Verilate the translated module (warnings suppressed)
  os.system( 'verilator -cc {0} -top-module {1} -Wno-lint -Wno-UNOPTFLAT'.format( filename_v, model_name ) )

  # Import the specified module and get its input and output ports
  __import__( model_name )

  imported_module = sys.modules[ model_name ]

  model_class = imported_module.__dict__[ model_name ]
  model_inst = model_class()
  model_inst.elaborate()

  in_ports = model_inst.get_inports()
  out_ports = model_inst.get_outports()

  in_ports = [ ( p.verilog_name(), str( p.width ) ) for p in in_ports if not p.verilog_name() in [ 'clk', 'reset' ] ] 
  out_ports = [ ( p.verilog_name(), str( p.width ) ) for p in out_ports ] 

  # Generate the Cython source code
  f = open(filename_pyx, 'w')

  pyx = 'from pymtl import *\n\n\
cdef extern from \"obj_dir/{0}.h\":\n\
  cdef cppclass {0}:\n'.format( vobj_name )

  for i in ( [ ('clk', '1') ] + in_ports + out_ports ):
    s = int( i[1] )

    if s <= 8:
      pyx += '    char '
    elif s <= 16:
      pyx += '    unsigned short '
    elif s <= 32:
      pyx += '    unsigned long '
    elif s <= 64:
      pyx += '    long long '
    else:
      pyx += '    unsigned long '

    pyx += i[0]

    if s <= 64:
      pyx += '\n'
    else:
      pyx += '[{0}]\n'.format( int ( math.ceil( s / 32.0 ) ) )

  pyx += '\n\
    void eval()\n\
\n\
cdef {0} *{1} = new {0}()\n\n'.format(vobj_name, model_name)

  pyx += 'def set_clk(clk):\n  global {0}\n  {0}.clk = clk\n\n'.format( model_name )

  for i in in_ports:
    pyx += 'def set_{0}({0}):\n  global {1}\n'.format( i[0], model_name )
    s = int( i[1] )

    if s <= 64:
      pyx += '  {0}.{1} = {1}.value.int\n\n'.format( model_name, i[0] )
    else:
      for j in range( s / 32 ):
        pyx += '  {0}.{1}[{2}] = {1}.value[{3}:{4}].int\n'.format( model_name, i[0], j, 32*j, 32*(j+1)-1 )
      if s % 32 != 0:
        pyx += '  {0}.{1}[{2}] = {1}.value[{3}:{4}].int\n'.format( model_name, i[0], int( math.ceil( s  / 32.0 ) ), s / 32, s-1  )

      pyx += '\n'
<commit_msg>[v2pymtl] fixed slice indexing and uint bug in pyx gen<commit_after>#!/usr/bin/env python

import fileinput
import sys
import re
import os
import math

if( __name__ == '__main__' ):

  if( len(sys.argv) < 3 ):
    print 'Usage: v2pymtl.py [model name] [verilog file]'
    sys.exit()

  model_name = sys.argv[1]
  filename_v = sys.argv[2]

  filename_pyx = model_name + '.pyx'
  filename_w = 'W' + model_name + '.py'
  vobj_name = 'V' + model_name

  # Verilate the translated module (warnings suppressed)
  os.system( 'verilator -cc {0} -top-module {1} -Wno-lint -Wno-UNOPTFLAT'.format( filename_v, model_name ) )

  # Import the specified module and get its input and output ports
  __import__( model_name )

  imported_module = sys.modules[ model_name ]

  model_class = imported_module.__dict__[ model_name ]
  model_inst = model_class()
  model_inst.elaborate()

  in_ports = model_inst.get_inports()
  out_ports = model_inst.get_outports()

  in_ports = [ ( p.verilog_name(), str( p.width ) ) for p in in_ports if not p.verilog_name() in [ 'clk', 'reset' ] ] 
  out_ports = [ ( p.verilog_name(), str( p.width ) ) for p in out_ports ] 

  # Generate the Cython source code
  f = open(filename_pyx, 'w')

  pyx = 'from pymtl import *\n\n\
cdef extern from \"obj_dir/{0}.h\":\n\
  cdef cppclass {0}:\n'.format( vobj_name )

  for i in ( [ ('clk', '1') ] + in_ports + out_ports ):
    s = int( i[1] )

    if s <= 8:
      pyx += '    char '
    elif s <= 16:
      pyx += '    unsigned short '
    elif s <= 32:
      pyx += '    unsigned long '
    elif s <= 64:
      pyx += '    long long '
    else:
      pyx += '    unsigned long '

    pyx += i[0]

    if s <= 64:
      pyx += '\n'
    else:
      pyx += '[{0}]\n'.format( int ( math.ceil( s / 32.0 ) ) )

  pyx += '\n\
    void eval()\n\
\n\
cdef {0} *{1} = new {0}()\n\n'.format(vobj_name, model_name)

  pyx += 'def set_clk(clk):\n  global {0}\n  {0}.clk = clk\n\n'.format( model_name )

  for i in in_ports:
    pyx += 'def set_{0}({0}):\n  global {1}\n'.format( i[0], model_name )
    s = int( i[1] )

    if s <= 64:
      pyx += '  {0}.{1} = {1}.value.uint\n\n'.format( model_name, i[0] )
    else:
      word_aligned = s/32
      for j in range( word_aligned ):
        pyx += '  {0}.{1}[{2}] = {1}.value[{3}:{4}].uint\n'.format( model_name, i[0], j, 32*j, 32*(j+1) )
      if s % 32 != 0:
        idx = word_aligned
        start = word_aligned*32
        end = s
        pyx += '  {0}.{1}[{2}] = {1}.value[{3}:{4}].uint\n'.format( model_name, i[0], idx, start, end )

      pyx += '\n'

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