<commit_before>/**
 * @file
 * LM3S6965 ethernet driver.
 *
 * @section LICENSE
 * Copyright (c) 2009, <NAME>, <NAME>. All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without 
 * modification, are permitted provided that the following conditions are met:
 * 
 *    * Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright 
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AS IS'' AND ANY EXPRESS 
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 
 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY DIRECT, INDIRECT, 
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
 * LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR  
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS  SOFTWARE, 
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <FreeRTOS.h>
#include <task.h>
#include <semphr.h>
#include "ethernet.h"
#include "mmap.h"
#include "uart.h"
#include <esix.h>

// Mutexes
static xSemaphoreHandle ether_receive_sem;
static xSemaphoreHandle ether_send_sem;

// Prototypes
void ether_receive_task(void *param);
void ether_send_task(void *param);

/**
 * ether_init : configures the ethernet hardware found in lm3s6965 
 */
void ether_init(u16_t lla[3])
{
	SYSCTR->RCGC2	|= (1 << 30); //enable PHY clock 
	SYSCTR->RCGC2	|= (1 << 28); //enable MAC clock

	//give them a little time to wake up
	asm("nop");

	//set the MAC Management frequency (must be <2.5MHz,
	//Fmfq = Fcpu/(2*(MACDVR+1)) )
	//still dunno at what speed we're running. 50MHz now?
	ETH0->MACMDV	= 0x0000000a;

	//program a MAC address (we should be reading this from somewhere...)
	ETH0->MACIA0	= (lla[0] << 16) | lla[1];	//4 first MAC address bytes
	ETH0->MACIA1	= lla[2];  //the first 2 bytes are marked as reserved

	//generate FCS in hardware, do autoneg, FD.
	ETH0->MACTCTL	|= 0x00000016;

	//flush rx fifo, reject frames with bad CRC in hardware
	ETH0->MACRCTL	|= 0x00000018;

	//tell the hardware to hand over multicast frames. We're going to need 
	//them for IPv6 and this ether chip doesn't have any mcast filter list.
	ETH0->MACRCTL	|= 0x00000002;

	//set leds to be controlled by hardware
	GPIOF->AFSEL |= 0x0000000c;
	GPIOF->ODR   |= 0x0000000c;
	
	ETH0->MACIM	&= ~0x0000007f;

	//Unmask ethernet interrupt at the processor level and set
	//a priority of configMAX_SYSCALL_INTERRUPT_PRIORITY+2
	NVIC->IPR[10] &= ~(0xff << 16); // Set interrupt priority
	NVIC->IPR[10] |= ((configMAX_SYSCALL_INTERRUPT_PRIORITY+2) << 16);
	NVIC->ISER[1] |= (1 << 10); // Unmask ethernet interrupt

	vSemaphoreCreateBinary(ether_receive_sem);
	xSemaphoreTake(ether_receive_sem, portMAX_DELAY);
	xTaskCreate(ether_receive_task, (signed char *) "eth reeive", 200, NULL, tskIDLE_PRIORITY + 1, NULL);
	vSemaphoreCreateBinary(ether_send_sem);
	xSemaphoreTake(ether_send_sem, portMAX_DELAY);
	xTaskCreate(ether_send_task, (signed char *) "eth send", 200, NULL, tskIDLE_PRIORITY + 1, NULL);
}

/**
 * ether_enable : activates the ethernet interface
 */
void ether_enable()
{

	//TX and RX are started independantly
	//RX
	ETH0->MACRCTL	|= 0x00000001;
	//TX
	ETH0->MACTCTL	|= 0x00000001;
	//Unmask all ethernet interupts
	//at the controller level
	ETH0->MACIM	|= 0x0000001;

	//Unmask interrupts at the MII level

/*
	u32_t mii_val = 0xffff;
	ether_mii_request(0x11, &mii_val, MII_WRITE);
        ETH0->MACMTXD |= 0xff00;
	
	u16_t addr = 0x11;
        u16_t tmp     = (addr << 3 ) + 0x03; //0x3 = write + start
        ETH0->MACMCTL = tmp;
*/
}

/**
 * ether_disable : disables the ethernet interface
 */
void ether_disable()
{
	//TX and RX are started independantly
	//RX
	ETH0->MACRCTL	&= ~0x00000001;
	//TX
	ETH0->MACTCTL	&= ~0x00000001;

	//mask interrupts
	ETH0->MACIM	&= ~0x0000007f;
}

/**
 * ether_handler : Ethernet interrupt handler
 */
void ether_handler()
{
	u16_t int_val	= ETH0->MACRIS;
	static portBASE_TYPE resched_needed; 
	resched_needed = pdFALSE;

	if(int_val&RXINT)
	{
		xSemaphoreGiveFromISR(ether_receive_sem, &resched_needed);
		ETH0->MACRIS |= 0x1;
		ETH0->MACIM	&= ~0x1;<commit_msg>small updates...<commit_after>/**
 * @file
 * LM3S6965 ethernet driver.
 *
 * @section LICENSE
 * Copyright (c) 2009, <NAME>, <NAME>. All rights reserved.
 * 
 * Redistribution and use in source and binary forms, with or without 
 * modification, are permitted provided that the following conditions are met:
 * 
 *    * Redistributions of source code must retain the above copyright notice,
 *      this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright 
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AS IS'' AND ANY EXPRESS 
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 
 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY DIRECT, INDIRECT, 
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
 * LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR  
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS  SOFTWARE, 
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <FreeRTOS.h>
#include <task.h>
#include <semphr.h>
#include "ethernet.h"
#include "mmap.h"
#include "uart.h"
#include <esix.h>

// Mutexes
static xSemaphoreHandle ether_receive_sem;
static xSemaphoreHandle ether_send_sem;

// Prototypes
void ether_receive_task(void *param);
void ether_send_task(void *param);

/**
 * ether_init : configures the ethernet hardware found in lm3s6965 
 */
void ether_init(u16_t lla[3])
{
	SYSCTR->RCGC2	|= (1 << 30); //enable PHY clock 
	SYSCTR->RCGC2	|= (1 << 28); //enable MAC clock

	//give them a little time to wake up
	asm("nop");

	//set the MAC Management frequency (must be <2.5MHz,
	//Fmfq = Fcpu/(2*(MACDVR+1)) )
	//still dunno at what speed we're running. 50MHz now?
	ETH0->MACMDV	= 0x0000000a;

	//program a MAC address (we should be reading this from somewhere...)
	ETH0->MACIA0	= (lla[0] << 16) | lla[1];	//4 first MAC address bytes
	ETH0->MACIA1	= lla[2];  //the first 2 bytes are marked as reserved

	//generate FCS in hardware, do autoneg, FD.
	ETH0->MACTCTL	|= 0x00000016;

	//flush rx fifo, reject frames with bad CRC in hardware
	ETH0->MACRCTL	|= 0x00000018;

	//tell the hardware to hand over multicast frames. We're going to need 
	//them for IPv6 and this ether chip doesn't have any mcast filter list.
	ETH0->MACRCTL	|= 0x00000002;

	//set leds to be controlled by hardware
	GPIOF->AFSEL |= 0x0000000c;
	GPIOF->ODR   |= 0x0000000c;
	
	ETH0->MACIM	&= ~0x0000007f;

	//Unmask ethernet interrupt at the processor level and set
	//a priority of configMAX_SYSCALL_INTERRUPT_PRIORITY+2
	NVIC->IPR[10] &= ~(0xff << 16); // Set interrupt priority
	NVIC->IPR[10] |= ((configMAX_SYSCALL_INTERRUPT_PRIORITY+2) << 16);
	NVIC->ISER[1] |= (1 << 10); // Unmask ethernet interrupt

	vSemaphoreCreateBinary(ether_receive_sem);
	xSemaphoreTake(ether_receive_sem, portMAX_DELAY);
	xTaskCreate(ether_receive_task, (signed char *) "eth reeive", 200, NULL, tskIDLE_PRIORITY + 1, NULL);
	vSemaphoreCreateBinary(ether_send_sem);
	xSemaphoreTake(ether_send_sem, portMAX_DELAY);
	xTaskCreate(ether_send_task, (signed char *) "eth send", 200, NULL, tskIDLE_PRIORITY + 1, NULL);
}

/**
 * ether_enable : activates the ethernet interface
 */
void ether_enable()
{

	//TX and RX are started independantly
	//RX
	ETH0->MACRCTL	|= 0x00000001;
	//TX
	ETH0->MACTCTL	|= 0x00000001;
	//Unmask all ethernet interupts
	//at the controller level
	ETH0->MACIM	|= 0x0000001;

	//Unmask interrupts at the MII level

/*
	u32_t mii_val = 0xffff;
	ether_mii_request(0x11, &mii_val, MII_WRITE);
        ETH0->MACMTXD |= 0xff00;
	
	u16_t addr = 0x11;
        u16_t tmp     = (addr << 3 ) + 0x03; //0x3 = write + start
        ETH0->MACMCTL = tmp;
*/
}

/**
 * ether_disable : disables the ethernet interface
 */
void ether_disable()
{
	//TX and RX are started independantly
	//RX
	ETH0->MACRCTL	&= ~0x00000001;
	//TX
	ETH0->MACTCTL	&= ~0x00000001;

	//mask interrupts
	ETH0->MACIM	&= ~0x0000007f;
}

/**
 * ether_handler : Ethernet interrupt handler
 */
void ether_handler()
{
	u16_t int_val	= ETH0->MACRIS;
	static portBASE_TYPE resched_needed; 
	resched_needed = pdFALSE;

	if(int_val&RXINT)
	{
		xSemaphoreGiveFromISR(ether_receive_sem, &resched_needed);
		//ETH0->MACRIS |= 0x1;
		ETH0->MACIM	&= ~0x1;
{'fraction_non_alphanumeric': 0.10863748260729958, 'fraction_numerical': 0.04730814513539548, 'mean_word_length': 3.972857903139968, 'pattern_counts': {'":': 0, '<': 45, '<?xml version=': 0, '>': 65, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 16, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '3573018', 'n_tokens_mistral': 3700, 'n_tokens_neox': 3130, 'n_words': 1038}