<commit_before>// Copyright (C) 2015 <NAME>, <NAME>
// License: BSD 2-Clause (see LICENSE for details)

package TurboRav

import Chisel._
import Constants._

/*
 * The memory stage handles memory request related logic.
 *
 * The main pipeline delay of this stage comes from the synchronous
 * ram module. To not double-pipeline this stage we send memory
 * request signals asynchrounously through io.rr_io.request.
 *
 * The response comes back 1 clock cycle later through
 * io.rr_io.response.
 * */

class Memory extends Module {
  val io = new MemoryIO()

  // Pipeline registers
  val exe_mem = Reg(init = new ExecuteMemory())

  val request  = io.rr_io.request
  val response = io.rr_io.response
  val mem_ctrl = io.exe_mem.mem_ctrl

  val stall_mem = Wire(Bool())

  // 1 bit of state for keeping track of if we are doing a multi-cycle
  // memory transfer like a MMIO access.
  val is_multi_cycle_transfer_next = Bool()
  val is_multi_cycle_transfer = Reg(init = Bool(false), next = is_multi_cycle_transfer_next)

  // Usually we comb. use control signals from execute to do memory
  // requests to Roam, but there is an exception. During a multi-cycle
  // memory transfer we must first use control signals from exe as
  // usual, but on the next clock cycle exe will be giving us
  // different control signals. To hold the same memory request over
  // several cycles we we switch to using signals from the pipeline
  // register on the second cycle.
  val ctrl = Mux(
    is_multi_cycle_transfer,
    exe_mem,
    io.exe_mem
  )

  val is_mem_transfer = ctrl.mem_ctrl.write || ctrl.mem_ctrl.read
  request.valid        := is_mem_transfer
  request.bits.addr    := ctrl.alu_result
  request.bits.wdata   := ClearIfDisabled(ctrl.rs2, ctrl.mem_ctrl.write)
  request.bits.write   := ctrl.mem_ctrl.write
  request.bits.byte_en := Cat(ctrl.mem_ctrl.is_halfword, ctrl.mem_ctrl.is_byte)

  when(is_multi_cycle_transfer) {
    // During a mulit-cycle transfer, we stay in this state until we
    // get a valid response.
    is_multi_cycle_transfer_next := ! response.valid
  }.elsewhen(is_mem_transfer && isApbAddress(request.bits.addr)) {
    is_multi_cycle_transfer_next := Bool(true)
  }.otherwise {
    is_multi_cycle_transfer_next := Bool(false)
  }

  io.mem_wrb := exe_mem

  io.mem_wrb.mem_read_data := response.bits.word<commit_msg>Optimization: Don't clear data signals<commit_after>// Copyright (C) 2015 <NAME>, <NAME>
// License: BSD 2-Clause (see LICENSE for details)

package TurboRav

import Chisel._
import Constants._

/*
 * The memory stage handles memory request related logic.
 *
 * The main pipeline delay of this stage comes from the synchronous
 * ram module. To not double-pipeline this stage we send memory
 * request signals asynchrounously through io.rr_io.request.
 *
 * The response comes back 1 clock cycle later through
 * io.rr_io.response.
 * */

class Memory extends Module {
  val io = new MemoryIO()

  // Pipeline registers
  val exe_mem = Reg(init = new ExecuteMemory())

  val request  = io.rr_io.request
  val response = io.rr_io.response
  val mem_ctrl = io.exe_mem.mem_ctrl

  val stall_mem = Wire(Bool())

  // 1 bit of state for keeping track of if we are doing a multi-cycle
  // memory transfer like a MMIO access.
  val is_multi_cycle_transfer_next = Bool()
  val is_multi_cycle_transfer = Reg(init = Bool(false), next = is_multi_cycle_transfer_next)

  // Usually we comb. use control signals from execute to do memory
  // requests to Roam, but there is an exception. During a multi-cycle
  // memory transfer we must first use control signals from exe as
  // usual, but on the next clock cycle exe will be giving us
  // different control signals. To hold the same memory request over
  // several cycles we we switch to using signals from the pipeline
  // register on the second cycle.
  val ctrl = Mux(
    is_multi_cycle_transfer,
    exe_mem,
    io.exe_mem
  )

  val is_mem_transfer = ctrl.mem_ctrl.write || ctrl.mem_ctrl.read
  request.valid        := is_mem_transfer
  request.bits.addr    := ctrl.alu_result
  request.bits.wdata   := ctrl.rs2
  request.bits.write   := ctrl.mem_ctrl.write
  request.bits.byte_en := Cat(ctrl.mem_ctrl.is_halfword, ctrl.mem_ctrl.is_byte)

  when(is_multi_cycle_transfer) {
    // During a mulit-cycle transfer, we stay in this state until we
    // get a valid response.
    is_multi_cycle_transfer_next := ! response.valid
  }.elsewhen(is_mem_transfer && isApbAddress(request.bits.addr)) {
    is_multi_cycle_transfer_next := Bool(true)
  }.otherwise {
    is_multi_cycle_transfer_next := Bool(false)
  }

  io.mem_wrb := exe_mem

  io.mem_wrb.mem_read_data := response.bits.word
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