<commit_before>/*
 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.

 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public
 * License as published by the Free Software Foundation;
 * either version 2, or (at your option) any later version.

 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
 * the implied warranty of MERCHANTABILITY or FITNESS FOR
 * A PARTICULAR PURPOSE.See the GNU General Public License
 * for more details.

 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc.,
 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

#include "global.h"
struct res_map_refresh res_map_refresh_tbl[] = {
/*hres, vres, vclock, vmode_refresh*/
	{480, 640, RES_480X640_60HZ_PIXCLOCK, 60},
	{640, 480, RES_640X480_60HZ_PIXCLOCK, 60},
	{640, 480, RES_640X480_75HZ_PIXCLOCK, 75},
	{640, 480, RES_640X480_85HZ_PIXCLOCK, 85},
	{640, 480, RES_640X480_100HZ_PIXCLOCK, 100},
	{640, 480, RES_640X480_120HZ_PIXCLOCK, 120},
	{720, 480, RES_720X480_60HZ_PIXCLOCK, 60},
	{720, 576, RES_720X576_60HZ_PIXCLOCK, 60},
	{800, 480, RES_800X480_60HZ_PIXCLOCK, 60},
	{800, 600, RES_800X600_60HZ_PIXCLOCK, 60},
	{800, 600, RES_800X600_75HZ_PIXCLOCK, 75},
	{800, 600, RES_800X600_85HZ_PIXCLOCK, 85},
	{800, 600, RES_800X600_100HZ_PIXCLOCK, 100},
	{800, 600, RES_800X600_120HZ_PIXCLOCK, 120},
	{848, 480, RES_848X480_60HZ_PIXCLOCK, 60},
	{856, 480, RES_856X480_60HZ_PIXCLOCK, 60},
	{1024, 512, RES_1024X512_60HZ_PIXCLOCK, 60},
	{1024, 600, RES_1024X600_60HZ_PIXCLOCK, 60},
	{1024, 768, RES_1024X768_60HZ_PIXCLOCK, 60},
	{1024, 768, RES_1024X768_75HZ_PIXCLOCK, 75},
	{1024, 768, RES_1024X768_85HZ_PIXCLOCK, 85},
	{1024, 768, RES_1024X768_100HZ_PIXCLOCK, 100},
/*  {1152,864, RES_1152X864_70HZ_PIXCLOCK,  70},*/
	{1152, 864, RES_1152X864_75HZ_PIXCLOCK, 75},
	{1280, 768, RES_1280X768_60HZ_PIXCLOCK, 60},
	{1280, 800, RES_1280X800_60HZ_PIXCLOCK, 60},
	{1280, 960, RES_1280X960_60HZ_PIXCLOCK, 60},
	{1280, 1024, RES_1280X1024_60HZ_PIXCLOCK, 60},
	{1280, 1024, RES_1280X1024_75HZ_PIXCLOCK, 75},
	{1280, 1024, RES_1280X768_85HZ_PIXCLOCK, 85},
	{1440, 1050, RES_1440X1050_60HZ_PIXCLOCK, 60},
	{1600, 1200, RES_1600X1200_60HZ_PIXCLOCK, 60},
	{1600, 1200, RES_1600X1200_75HZ_PIXCLOCK, 75},
	{1280, 720, RES_1280X720_60HZ_PIXCLOCK, 60},
	{1920, 1080, RES_1920X1080_60HZ_PIXCLOCK, 60},
	{1400, 1050, RES_1400X1050_60HZ_PIXCLOCK, 60},
	{1400, 1050, RES_1400X1050_75HZ_PIXCLOCK, 75},
	{1368, 768, RES_1368X768_60HZ_PIXCLOCK, 60},
	{960, 600, RES_960X600_60HZ_PIXCLOCK, 60},
	{1000, 600, RES_1000X600_60HZ_PIXCLOCK, 60},
	{1024, 576, RES_1024X576_60HZ_PIXCLOCK, 60},
	{1088, 612, RES_1088X612_60HZ_PIXCLOCK, 60},
	{1152, 720, RES_1152X720_60HZ_PIXCLOCK, 60},
	{1200, 720, RES_1200X720_60HZ_PIXCLOCK, 60},
	{1280, 600, RES_1280X600_60HZ_PIXCLOCK, 60},
	{1280, 720, RES_1280X720_50HZ_PIXCLOCK, 50},
	{1280, 768, RES_1280X768_50HZ_PIXCLOCK, 50},
	{1360, 768, RES_1360X768_60HZ_PIXCLOCK, 60},
	{1366, 768, RES_1366X768_50HZ_PIXCLOCK, 50},
	{1366, 768, RES_1366X768_60HZ_PIXCLOCK, 60},
	{1440, 900, RES_1440X900_60HZ_PIXCLOCK, 60},
	{1440, 900, RES_1440X900_75HZ_PIXCLOCK, 75},
	{1600, 900, RES_1600X900_60HZ_PIXCLOCK, 60},
	{1600, 1024, RES_1600X1024_60HZ_PIXCLOCK, 60},
	{1680, 1050, RES_1680X1050_60HZ_PIXCLOCK, 60},
	{1680, 1050, RES_1680X1050_75HZ_PIXCLOCK, 75},
	{1792, 1344, RES_1792X1344_60HZ_PIXCLOCK, 60},
	{1856, 1392, RES_1856X1392_60HZ_PIXCLOCK, 60},
	{1920, 1200, RES_1920X1200_60HZ_PIXCLOCK, 60},
	{1920, 1440, RES_1920X1440_60HZ_PIXCLOCK, 60},
	{1920, 1440, RES_1920X1440_75HZ_PIXCLOCK, 75},
	{2048, 1536, RES_2048X1536_60HZ_PIXCLOCK, 60}
};

struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
{VIASR, SR15, 0x02, 0x02},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR17, 0xFF, 0x1F},
{VIASR, SR18, 0xFF, 0x4E},
{VIASR, SR1A, 0xFB, 0x08},
{VIASR, SR1E, 0x0F, 0x01},
{VIASR, SR2A, 0xFF, 0x00},
{VIACR, CR0A, 0xFF, 0x1E},	/* Cursor Start                        */
{VIACR, CR0B, 0xFF, 0x00},	/* Cursor End                          */
{VIACR, CR0E, 0xFF, 0x00},	/* Cursor Location High                */
{VIACR, CR0F, 0xFF, 0x00},	/* Cursor Localtion Low                */
{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR33, 0xFF, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0x08, 0x00},
{VIACR, CR69, 0xFF, 0x00},
{VIACR, CR6A, 0xFF, 0x40},
{VIACR, CR6B, 0xFF, 0x00},
{VIACR, CR6C, 0xFF, 0x00},
{VIACR, CR7A, 0xFF, 0x01},	/* LCD Scaling Parameter 1             */
{VIACR, CR7B, 0xFF, 0x02},	/* LCD Scaling Parameter 2             */
{VIACR, CR7C, 0xFF, 0x03},	/* LCD Scaling Parameter 3             */
{VIACR, CR7D, 0xFF, 0x04},	/* LCD Scaling Parameter 4             */
{VIACR, CR7E, 0xFF, 0x07},	/* LCD Scaling Parameter 5             */
{VIACR, CR7F, 0xFF, 0x0A},	/* LCD Scaling Parameter 6             */
{VIACR, CR80, 0xFF, 0x0D},	/* LCD Scaling Parameter 7             */
{VIACR, CR81, 0xFF, 0x13},	/* LCD Scaling Parameter 8             */
{VIACR, CR82, 0xFF, 0x16},	/* LCD Scaling Parameter 9             */
{VIACR, CR83, 0xFF, 0x19},	/* LCD Scaling Parameter 10            */
{VIACR, CR84, 0xFF, 0x1C},	/* LCD Scaling Parameter 11            */
{VIACR, CR85, 0xFF, 0x1D},	/* LCD Scaling Parameter 12            */
{VIACR, CR86, 0xFF, 0x1E},	/* LCD Scaling Parameter 13            */
{VIACR, CR87, 0xFF, 0x1F},	/* LCD Scaling Parameter 14            */
{VIACR, CR88, 0xFF, 0x40},	/* LCD Panel Type                      */
{VIACR, CR89, 0xFF, 0x00},	/* LCD Timing Control 0                */
{VIACR, CR8A, 0xFF, 0x88},	/* LCD Timing Control 1                */
{VIACR, CR8B, 0xFF, 0x69},	/* LCD Power Sequence Control 0        */
{VIACR, CR8C, 0xFF, 0x57},	/* LCD Power Sequence Control 1        */
{VIACR, CR8D, 0xFF, 0x00},	/* LCD Power Sequence Control 2        */
{VIACR, CR8E, 0xFF, 0x7B},	/* LCD Power Sequence Control 3        */
{VIACR, CR8F, 0xFF, 0x03},	/* LCD Power Sequence Control 4        */
{VIACR, CR90, 0xFF, 0x30},	/* LCD Power Sequence Control 5        */
{VIACR, CR91, 0xFF, 0xA0},	/* 24/12 bit LVDS Data off             */
{VIACR, CR96, 0xFF, 0x00},
{VIACR, CR97, 0xFF, 0x00},
{VIACR, CR99, 0xFF, 0x00},
{VIACR, CR9B, 0xFF, 0x00}
};

/* Video Mode Table for VT3314 chipset*/
/* Common Setting for Video Mode */
struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
{VIASR, SR15, 0x02, 0x02},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR17, 0xFF, 0x1F},
{VIASR, SR18, 0xFF, 0x4E},
{VIASR, SR1A, 0xFB, 0x82},
{VIASR, SR1B, 0xFF, 0xF0},
{VIASR, SR1F, 0xFF, 0x00},
{VIASR, SR1E, 0xFF, 0x01},
{VIASR, SR22, 0xFF, 0x1F},
{VIASR, SR2A, 0x0F, 0x00},
{VIASR, SR2E, 0xFF, 0xFF},
{VIASR, SR3F, 0xFF, 0xFF},
{VIASR, SR40, 0xF7, 0x00},
{VIASR, CR30, 0xFF, 0x04},
{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR33, 0x7F, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0xFF, 0x31},
{VIACR, CR41, 0xFF, 0x80},
{VIACR, CR42, 0xFF, 0x00},
{VIACR, CR55, 0x80, 0x00},
{VIACR, CR5D, 0x80, 0x00},	/*Horizontal Retrace Start bit[11] should be 0*/
{VIACR, CR68, 0xFF, 0x67},	/* Default FIFO For IGA2 */
{VIACR, CR69, 0xFF, 0x00},
{VIACR, CR6A, 0xFD, 0x40},
{VIACR, CR6B, 0xFF, 0x00},
{VIACR, CR6C, 0xFF, 0x00},
{VIACR, CR77, 0xFF, 0x00},	/* LCD scaling Factor */
{VIACR, CR78, 0xFF, 0x00},	/* LCD scaling Factor */
{VIACR, CR79, 0xFF, 0x00},	/* LCD scaling Factor */
{VIACR, CR9F, 0x03, 0x00},	/* LCD scaling Factor */
{VIACR, CR7A, 0xFF, 0x01},	/* LCD Scaling Parameter 1 */
{VIACR, CR7B, 0xFF, 0x02},	/* LCD Scaling Parameter 2 */
{VIACR, CR7C, 0xFF, 0x03},	/* LCD Scaling Parameter 3 */
{VIACR, CR7D, 0xFF, 0x04},	/* LCD Scaling Parameter 4 */
{VIACR, CR7E, 0xFF, 0x07},	/* LCD Scaling Parameter 5 */
{VIACR, CR7F, 0xFF, 0x0A},	/* LCD Scaling Parameter 6 */
{VIACR, CR80, 0xFF, 0x0D},	/* LCD Scaling Parameter 7 */
{VIACR, CR81, 0xFF, 0x13},	/* LCD Scaling Parameter 8 */
{VIACR, CR82, 0xFF, 0x16},	/* LCD Scaling Parameter 9 */
{VIACR, CR83, 0xFF, 0x19},	/* LCD Scaling Parameter 10 */
{VIACR, CR84, 0xFF, 0x1C},	/* LCD Scaling Parameter 11 */
{VIACR, CR85, 0xFF, 0x1D},	/* LCD Scaling Parameter 12 */
{VIACR, CR86, 0xFF, 0x1E},	/* LCD Scaling Parameter 13 */
{VIACR, CR87, 0xFF, 0x1F},	/* LCD Scaling Parameter 14 */
{VIACR, CR88, 0xFF, 0x40},	/* LCD Panel Type */
{VIACR, CR89, 0xFF, 0x00},	/* LCD Timing Control 0 */
{VIACR, CR8A, 0xFF, 0x88},	/* LCD Timing Control 1 */
{VIACR, CR8B, 0xFF, 0x5D},	/* LCD Power Sequence Control 0 */
{VIACR, CR8C, 0xFF, 0x2B},	/* LCD Power Sequence Control 1 */
{VIACR, CR8D, 0xFF, 0x6F},	/* LCD Power Sequence Control 2 */
{VIACR, CR8E, 0xFF, 0x2B},	/* LCD Power Sequence Control 3 */
{VIACR, CR8F, 0xFF, 0x01},	/* LCD Power Sequence Control 4 */
{VIACR, CR90, 0xFF, 0x01},	/* LCD Power Sequence Control 5 */
{VIACR, CR91, 0xFF, 0xA0},	/* 24/12 bit LVDS Data off */
{VIACR, CR96, 0xFF, 0x00},
{VIACR, CR97, 0xFF, 0x00},
{VIACR, CR99, 0xFF, 0x00},
{VIACR, CR9B, 0xFF, 0x00},
{VIACR, CR9D, 0xFF, 0x80},
{VIACR, CR9E, 0xFF, 0x80}
};

struct io_reg KM400_ModeXregs[] = {
	{VIASR, SR10, 0xFF, 0x01},	/* Unlock Register                 */
	{VIASR, SR16, 0xFF, 0x08},	/* Display FIFO threshold Control  */
	{VIASR, SR17, 0xFF, 0x1F},	/* Display FIFO Control            */
	{VIASR, SR18, 0xFF, 0x4E},	/* GFX PREQ threshold              */
	{VIASR, SR1A, 0xFF, 0x0a},	/* GFX PREQ threshold              */
	{VIASR, SR1F, 0xFF, 0x00},	/* Memory Control 0                */
	{VIASR, SR1B, 0xFF, 0xF0},	/* Power Management Control 0      */
	{VIASR, SR1E, 0xFF, 0x01},	/* Power Management Control        */
	{VIASR, SR20, 0xFF, 0x00},	/* Sequencer Arbiter Control 0     */
	{VIASR, SR21, 0xFF, 0x00},	/* Sequencer Arbiter Control 1     */
	{VIASR, SR22, 0xFF, 0x1F},	/* Display Arbiter Control 1       */
	{VIASR, SR2A, 0xFF, 0x00},	/* Power Management Control 5      */
	{VIASR, SR2D, 0xFF, 0xFF},	/* Power Management Control 1      */
	{VIASR, SR2E, 0xFF, 0xFF},	/* Power Management Control 2      */
	{VIACR, CR0A, 0xFF, 0x1E},	/* Cursor Start                    */
	{VIACR, CR0B, 0xFF, 0x00},	/* Cursor End                      */
	{VIACR, CR0E, 0xFF, 0x00},	/* Cursor Location High            */
	{VIACR, CR0F, 0xFF, 0x00},	/* Cursor Localtion Low            */
	{VIACR, CR33, 0xFF, 0x00},
	{VIACR, CR55, 0x80, 0x00},
	{VIACR, CR5D, 0x80, 0x00},
	{VIACR, CR36, 0xFF, 0x01},	/* Power Mangement 3                  */
	{VIACR, CR68, 0xFF, 0x67},	/* Default FIFO For IGA2              */
	{VIACR, CR6A, 0x20, 0x20},	/* Extended FIFO On                   */
	{VIACR, CR7A, 0xFF, 0x01},	/* LCD Scaling Parameter 1            */
	{VIACR, CR7B, 0xFF, 0x02},	/* LCD Scaling Parameter 2            */
	{VIACR, CR7C, 0xFF, 0x03},	/* LCD Scaling Parameter 3            */
	{VIACR, CR7D, 0xFF, 0x04},	/* LCD Scaling Parameter 4            */
	{VIACR, CR7E, 0xFF, 0x07},	/* LCD Scaling Parameter 5            */
	{VIACR, CR7F, 0xFF, 0x0A},	/* LCD Scaling Parameter 6            */
	{VIACR, CR80, 0xFF, 0x0D},	/* LCD Scaling Parameter 7            */
	{VIACR, CR81, 0xFF, 0x13},	/* LCD Scaling Parameter 8            */
	{VIACR, CR82, 0xFF, 0x16},	/* LCD Scaling Parameter 9            */
	{VIACR, CR83, 0xFF, 0x19},	/* LCD Scaling Parameter 10           */
	{VIACR, CR84, 0xFF, 0x1C},	/* LCD Scaling Parameter 11           */
	{VIACR, CR85, 0xFF, 0x1D},	/* LCD Scaling Parameter 12           */
	{VIACR, CR86, 0xFF, 0x1E},	/* LCD Scaling Parameter 13           */
	{VIACR, CR87, 0xFF, 0x1F},	/* LCD Scaling Parameter 14           */
	{VIACR, CR88, 0xFF, 0x40},	/* LCD Panel Type                     */
	{VIACR, CR89, 0xFF, 0x00},	/* LCD Timing Control 0               */
	{VIACR, CR8A, 0xFF, 0x88},	/* LCD Timing Control 1               */
	{VIACR, CR8B, 0xFF, 0x2D},	/* LCD Power Sequence Control 0       */
	{VIACR, CR8C, 0xFF, 0x2D},	/* LCD Power Sequence Control 1       */
	{VIACR, CR8D, 0xFF, 0xC8},	/* LCD Power Sequence Control 2       */
	{VIACR, CR8E, 0xFF, 0x36},	/* LCD Power Sequence Control 3       */
	{VIACR, CR8F, 0xFF, 0x00},	/* LCD Power Sequence Control 4       */
	{VIACR, CR90, 0xFF, 0x10},	/* LCD Power Sequence Control 5       */
	{VIACR, CR91, 0xFF, 0xA0},	/* 24/12 bit LVDS Data off            */
	{VIACR, CR96, 0xFF, 0x03},	/* DVP0        ; DVP0 Clock Skew */
	{VIACR, CR97, 0xFF, 0x03},	/* DFP high    ; DFPH Clock Skew */
	{VIACR, CR99, 0xFF, 0x03},	/* DFP low           ; DFPL Clock Skew*/
	{VIACR, CR9B, 0xFF, 0x07}	/* DVI on DVP1       ; DVP1 Clock Skew*/
};

/* For VT3324: Common Setting for Video Mode */
struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
{VIASR, SR15, 0x02, 0x02},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR17, 0xFF, 0x1F},
{VIASR, SR18, 0xFF, 0x4E},
{VIASR, SR1A, 0xFB, 0x08},
{VIASR, SR1B, 0xFF, 0xF0},
{VIASR, SR1E, 0xFF, 0x01},
{VIASR, SR2A, 0xFF, 0x00},
{VIASR, SR2D, 0xFF, 0xFF},	/* VCK and LCK PLL power on.           */
{VIACR, CR0A, 0xFF, 0x1E},	/* Cursor Start                        */
{VIACR, CR0B, 0xFF, 0x00},	/* Cursor End                          */
{VIACR, CR0E, 0xFF, 0x00},	/* Cursor Location High                */
{VIACR, CR0F, 0xFF, 0x00},	/* Cursor Localtion Low                */
{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR33, 0xFF, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0x08, 0x00},
{VIACR, CR47, 0xC8, 0x00},	/* Clear VCK Plus. */
{VIACR, CR69, 0xFF, 0x00},
{VIACR, CR6A, 0xFF, 0x40},
{VIACR, CR6B, 0xFF, 0x00},
{VIACR, CR6C, 0xFF, 0x00},
{VIACR, CR7A, 0xFF, 0x01},	/* LCD Scaling Parameter 1             */
{VIACR, CR7B, 0xFF, 0x02},	/* LCD Scaling Parameter 2             */
{VIACR, CR7C, 0xFF, 0x03},	/* LCD Scaling Parameter 3             */
{VIACR, CR7D, 0xFF, 0x04},	/* LCD Scaling Parameter 4             */
{VIACR, CR7E, 0xFF, 0x07},	/* LCD Scaling Parameter 5             */
{VIACR, CR7F, 0xFF, 0x0A},	/* LCD Scaling Parameter 6             */
{VIACR, CR80, 0xFF, 0x0D},	/* LCD Scaling Parameter 7             */
{VIACR, CR81, 0xFF, 0x13},	/* LCD Scaling Parameter 8             */
{VIACR, CR82, 0xFF, 0x16},	/* LCD Scaling Parameter 9             */
{VIACR, CR83, 0xFF, 0x19},	/* LCD Scaling Parameter 10            */
{VIACR, CR84, 0xFF, 0x1C},	/* LCD Scaling Parameter 11            */
{VIACR, CR85, 0xFF, 0x1D},	/* LCD Scaling Parameter 12            */
{VIACR, CR86, 0xFF, 0x1E},	/* LCD Scaling Parameter 13            */
{VIACR, CR87, 0xFF, 0x1F},	/* LCD Scaling Parameter 14            */
{VIACR, CR88, 0xFF, 0x40},	/* LCD Panel Type                      */
{VIACR, CR89, 0xFF, 0x00},	/* LCD Timing Control 0                */
{VIACR, CR8A, 0xFF, 0x88},	/* LCD Timing Control 1                */
{VIACR, CRD4, 0xFF, 0x81},	/* Second power sequence control       */
{VIACR, CR8B, 0xFF, 0x5D},	/* LCD Power Sequence Control 0        */
{VIACR, CR8C, 0xFF, 0x2B},	/* LCD Power Sequence Control 1        */
{VIACR, CR8D, 0xFF, 0x6F},	/* LCD Power Sequence Control 2        */
{VIACR, CR8E, 0xFF, 0x2B},	/* LCD Power Sequence Control 3        */
{VIACR, CR8F, 0xFF, 0x01},	/* LCD Power Sequence Control 4        */
{VIACR, CR90, 0xFF, 0x01},	/* LCD Power Sequence Control 5        */
{VIACR, CR91, 0xFF, 0x80},	/* 24/12 bit LVDS Data off             */
{VIACR, CR96, 0xFF, 0x00},
{VIACR, CR97, 0xFF, 0x00},
{VIACR, CR99, 0xFF, 0x00},
{VIACR, CR9B, 0xFF, 0x00},
{VIACR, CRD2, 0xFF, 0xFF}	/* TMDS/LVDS control register.         */
};

/* Video Mode Table */
/* Common Setting for Video Mode */
struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00},
{VIASR, SR2A, 0x0F, 0x00},
{VIASR, SR15, 0x02, 0x02},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR17, 0xFF, 0x1F},
{VIASR, SR18, 0xFF, 0x4E},
{VIASR, SR1A, 0xFB, 0x08},

{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0x08, 0x00},
{VIACR, CR6A, 0xFF, 0x80},
{VIACR, CR6A, 0xFF, 0xC0},<commit_msg>viafb: remove LVDS initialization<commit_after>/*
 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.

 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public
 * License as published by the Free Software Foundation;
 * either version 2, or (at your option) any later version.

 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
 * the implied warranty of MERCHANTABILITY or FITNESS FOR
 * A PARTICULAR PURPOSE.See the GNU General Public License
 * for more details.

 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc.,
 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

#include "global.h"
struct res_map_refresh res_map_refresh_tbl[] = {
/*hres, vres, vclock, vmode_refresh*/
	{480, 640, RES_480X640_60HZ_PIXCLOCK, 60},
	{640, 480, RES_640X480_60HZ_PIXCLOCK, 60},
	{640, 480, RES_640X480_75HZ_PIXCLOCK, 75},
	{640, 480, RES_640X480_85HZ_PIXCLOCK, 85},
	{640, 480, RES_640X480_100HZ_PIXCLOCK, 100},
	{640, 480, RES_640X480_120HZ_PIXCLOCK, 120},
	{720, 480, RES_720X480_60HZ_PIXCLOCK, 60},
	{720, 576, RES_720X576_60HZ_PIXCLOCK, 60},
	{800, 480, RES_800X480_60HZ_PIXCLOCK, 60},
	{800, 600, RES_800X600_60HZ_PIXCLOCK, 60},
	{800, 600, RES_800X600_75HZ_PIXCLOCK, 75},
	{800, 600, RES_800X600_85HZ_PIXCLOCK, 85},
	{800, 600, RES_800X600_100HZ_PIXCLOCK, 100},
	{800, 600, RES_800X600_120HZ_PIXCLOCK, 120},
	{848, 480, RES_848X480_60HZ_PIXCLOCK, 60},
	{856, 480, RES_856X480_60HZ_PIXCLOCK, 60},
	{1024, 512, RES_1024X512_60HZ_PIXCLOCK, 60},
	{1024, 600, RES_1024X600_60HZ_PIXCLOCK, 60},
	{1024, 768, RES_1024X768_60HZ_PIXCLOCK, 60},
	{1024, 768, RES_1024X768_75HZ_PIXCLOCK, 75},
	{1024, 768, RES_1024X768_85HZ_PIXCLOCK, 85},
	{1024, 768, RES_1024X768_100HZ_PIXCLOCK, 100},
/*  {1152,864, RES_1152X864_70HZ_PIXCLOCK,  70},*/
	{1152, 864, RES_1152X864_75HZ_PIXCLOCK, 75},
	{1280, 768, RES_1280X768_60HZ_PIXCLOCK, 60},
	{1280, 800, RES_1280X800_60HZ_PIXCLOCK, 60},
	{1280, 960, RES_1280X960_60HZ_PIXCLOCK, 60},
	{1280, 1024, RES_1280X1024_60HZ_PIXCLOCK, 60},
	{1280, 1024, RES_1280X1024_75HZ_PIXCLOCK, 75},
	{1280, 1024, RES_1280X768_85HZ_PIXCLOCK, 85},
	{1440, 1050, RES_1440X1050_60HZ_PIXCLOCK, 60},
	{1600, 1200, RES_1600X1200_60HZ_PIXCLOCK, 60},
	{1600, 1200, RES_1600X1200_75HZ_PIXCLOCK, 75},
	{1280, 720, RES_1280X720_60HZ_PIXCLOCK, 60},
	{1920, 1080, RES_1920X1080_60HZ_PIXCLOCK, 60},
	{1400, 1050, RES_1400X1050_60HZ_PIXCLOCK, 60},
	{1400, 1050, RES_1400X1050_75HZ_PIXCLOCK, 75},
	{1368, 768, RES_1368X768_60HZ_PIXCLOCK, 60},
	{960, 600, RES_960X600_60HZ_PIXCLOCK, 60},
	{1000, 600, RES_1000X600_60HZ_PIXCLOCK, 60},
	{1024, 576, RES_1024X576_60HZ_PIXCLOCK, 60},
	{1088, 612, RES_1088X612_60HZ_PIXCLOCK, 60},
	{1152, 720, RES_1152X720_60HZ_PIXCLOCK, 60},
	{1200, 720, RES_1200X720_60HZ_PIXCLOCK, 60},
	{1280, 600, RES_1280X600_60HZ_PIXCLOCK, 60},
	{1280, 720, RES_1280X720_50HZ_PIXCLOCK, 50},
	{1280, 768, RES_1280X768_50HZ_PIXCLOCK, 50},
	{1360, 768, RES_1360X768_60HZ_PIXCLOCK, 60},
	{1366, 768, RES_1366X768_50HZ_PIXCLOCK, 50},
	{1366, 768, RES_1366X768_60HZ_PIXCLOCK, 60},
	{1440, 900, RES_1440X900_60HZ_PIXCLOCK, 60},
	{1440, 900, RES_1440X900_75HZ_PIXCLOCK, 75},
	{1600, 900, RES_1600X900_60HZ_PIXCLOCK, 60},
	{1600, 1024, RES_1600X1024_60HZ_PIXCLOCK, 60},
	{1680, 1050, RES_1680X1050_60HZ_PIXCLOCK, 60},
	{1680, 1050, RES_1680X1050_75HZ_PIXCLOCK, 75},
	{1792, 1344, RES_1792X1344_60HZ_PIXCLOCK, 60},
	{1856, 1392, RES_1856X1392_60HZ_PIXCLOCK, 60},
	{1920, 1200, RES_1920X1200_60HZ_PIXCLOCK, 60},
	{1920, 1440, RES_1920X1440_60HZ_PIXCLOCK, 60},
	{1920, 1440, RES_1920X1440_75HZ_PIXCLOCK, 75},
	{2048, 1536, RES_2048X1536_60HZ_PIXCLOCK, 60}
};

struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
{VIASR, SR15, 0x02, 0x02},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR17, 0xFF, 0x1F},
{VIASR, SR18, 0xFF, 0x4E},
{VIASR, SR1A, 0xFB, 0x08},
{VIASR, SR1E, 0x0F, 0x01},
{VIASR, SR2A, 0xFF, 0x00},
{VIACR, CR0A, 0xFF, 0x1E},	/* Cursor Start                        */
{VIACR, CR0B, 0xFF, 0x00},	/* Cursor End                          */
{VIACR, CR0E, 0xFF, 0x00},	/* Cursor Location High                */
{VIACR, CR0F, 0xFF, 0x00},	/* Cursor Localtion Low                */
{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR33, 0xFF, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0x08, 0x00},
{VIACR, CR69, 0xFF, 0x00},
{VIACR, CR6A, 0xFF, 0x40},
{VIACR, CR6B, 0xFF, 0x00},
{VIACR, CR6C, 0xFF, 0x00},
{VIACR, CR7A, 0xFF, 0x01},	/* LCD Scaling Parameter 1             */
{VIACR, CR7B, 0xFF, 0x02},	/* LCD Scaling Parameter 2             */
{VIACR, CR7C, 0xFF, 0x03},	/* LCD Scaling Parameter 3             */
{VIACR, CR7D, 0xFF, 0x04},	/* LCD Scaling Parameter 4             */
{VIACR, CR7E, 0xFF, 0x07},	/* LCD Scaling Parameter 5             */
{VIACR, CR7F, 0xFF, 0x0A},	/* LCD Scaling Parameter 6             */
{VIACR, CR80, 0xFF, 0x0D},	/* LCD Scaling Parameter 7             */
{VIACR, CR81, 0xFF, 0x13},	/* LCD Scaling Parameter 8             */
{VIACR, CR82, 0xFF, 0x16},	/* LCD Scaling Parameter 9             */
{VIACR, CR83, 0xFF, 0x19},	/* LCD Scaling Parameter 10            */
{VIACR, CR84, 0xFF, 0x1C},	/* LCD Scaling Parameter 11            */
{VIACR, CR85, 0xFF, 0x1D},	/* LCD Scaling Parameter 12            */
{VIACR, CR86, 0xFF, 0x1E},	/* LCD Scaling Parameter 13            */
{VIACR, CR87, 0xFF, 0x1F},	/* LCD Scaling Parameter 14            */
{VIACR, CR88, 0xFF, 0x40},	/* LCD Panel Type                      */
{VIACR, CR89, 0xFF, 0x00},	/* LCD Timing Control 0                */
{VIACR, CR8A, 0xFF, 0x88},	/* LCD Timing Control 1                */
{VIACR, CR8B, 0xFF, 0x69},	/* LCD Power Sequence Control 0        */
{VIACR, CR8C, 0xFF, 0x57},	/* LCD Power Sequence Control 1        */
{VIACR, CR8D, 0xFF, 0x00},	/* LCD Power Sequence Control 2        */
{VIACR, CR8E, 0xFF, 0x7B},	/* LCD Power Sequence Control 3        */
{VIACR, CR8F, 0xFF, 0x03},	/* LCD Power Sequence Control 4        */
{VIACR, CR90, 0xFF, 0x30},	/* LCD Power Sequence Control 5        */
{VIACR, CR91, 0xFF, 0xA0},	/* 24/12 bit LVDS Data off             */
{VIACR, CR96, 0xFF, 0x00},
{VIACR, CR97, 0xFF, 0x00},
{VIACR, CR99, 0xFF, 0x00},
{VIACR, CR9B, 0xFF, 0x00}
};

/* Video Mode Table for VT3314 chipset*/
/* Common Setting for Video Mode */
struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
{VIASR, SR15, 0x02, 0x02},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR17, 0xFF, 0x1F},
{VIASR, SR18, 0xFF, 0x4E},
{VIASR, SR1A, 0xFB, 0x82},
{VIASR, SR1B, 0xFF, 0xF0},
{VIASR, SR1F, 0xFF, 0x00},
{VIASR, SR1E, 0xFF, 0x01},
{VIASR, SR22, 0xFF, 0x1F},
{VIASR, SR2A, 0x0F, 0x00},
{VIASR, SR2E, 0xFF, 0xFF},
{VIASR, SR3F, 0xFF, 0xFF},
{VIASR, SR40, 0xF7, 0x00},
{VIASR, CR30, 0xFF, 0x04},
{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR33, 0x7F, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0xFF, 0x31},
{VIACR, CR41, 0xFF, 0x80},
{VIACR, CR42, 0xFF, 0x00},
{VIACR, CR55, 0x80, 0x00},
{VIACR, CR5D, 0x80, 0x00},	/*Horizontal Retrace Start bit[11] should be 0*/
{VIACR, CR68, 0xFF, 0x67},	/* Default FIFO For IGA2 */
{VIACR, CR69, 0xFF, 0x00},
{VIACR, CR6A, 0xFD, 0x40},
{VIACR, CR6B, 0xFF, 0x00},
{VIACR, CR6C, 0xFF, 0x00},
{VIACR, CR77, 0xFF, 0x00},	/* LCD scaling Factor */
{VIACR, CR78, 0xFF, 0x00},	/* LCD scaling Factor */
{VIACR, CR79, 0xFF, 0x00},	/* LCD scaling Factor */
{VIACR, CR9F, 0x03, 0x00},	/* LCD scaling Factor */
{VIACR, CR7A, 0xFF, 0x01},	/* LCD Scaling Parameter 1 */
{VIACR, CR7B, 0xFF, 0x02},	/* LCD Scaling Parameter 2 */
{VIACR, CR7C, 0xFF, 0x03},	/* LCD Scaling Parameter 3 */
{VIACR, CR7D, 0xFF, 0x04},	/* LCD Scaling Parameter 4 */
{VIACR, CR7E, 0xFF, 0x07},	/* LCD Scaling Parameter 5 */
{VIACR, CR7F, 0xFF, 0x0A},	/* LCD Scaling Parameter 6 */
{VIACR, CR80, 0xFF, 0x0D},	/* LCD Scaling Parameter 7 */
{VIACR, CR81, 0xFF, 0x13},	/* LCD Scaling Parameter 8 */
{VIACR, CR82, 0xFF, 0x16},	/* LCD Scaling Parameter 9 */
{VIACR, CR83, 0xFF, 0x19},	/* LCD Scaling Parameter 10 */
{VIACR, CR84, 0xFF, 0x1C},	/* LCD Scaling Parameter 11 */
{VIACR, CR85, 0xFF, 0x1D},	/* LCD Scaling Parameter 12 */
{VIACR, CR86, 0xFF, 0x1E},	/* LCD Scaling Parameter 13 */
{VIACR, CR87, 0xFF, 0x1F},	/* LCD Scaling Parameter 14 */
{VIACR, CR88, 0xFF, 0x40},	/* LCD Panel Type */
{VIACR, CR89, 0xFF, 0x00},	/* LCD Timing Control 0 */
{VIACR, CR8A, 0xFF, 0x88},	/* LCD Timing Control 1 */
{VIACR, CR8B, 0xFF, 0x5D},	/* LCD Power Sequence Control 0 */
{VIACR, CR8C, 0xFF, 0x2B},	/* LCD Power Sequence Control 1 */
{VIACR, CR8D, 0xFF, 0x6F},	/* LCD Power Sequence Control 2 */
{VIACR, CR8E, 0xFF, 0x2B},	/* LCD Power Sequence Control 3 */
{VIACR, CR8F, 0xFF, 0x01},	/* LCD Power Sequence Control 4 */
{VIACR, CR90, 0xFF, 0x01},	/* LCD Power Sequence Control 5 */
{VIACR, CR91, 0xFF, 0xA0},	/* 24/12 bit LVDS Data off */
{VIACR, CR96, 0xFF, 0x00},
{VIACR, CR97, 0xFF, 0x00},
{VIACR, CR99, 0xFF, 0x00},
{VIACR, CR9B, 0xFF, 0x00},
{VIACR, CR9D, 0xFF, 0x80},
{VIACR, CR9E, 0xFF, 0x80}
};

struct io_reg KM400_ModeXregs[] = {
	{VIASR, SR10, 0xFF, 0x01},	/* Unlock Register                 */
	{VIASR, SR16, 0xFF, 0x08},	/* Display FIFO threshold Control  */
	{VIASR, SR17, 0xFF, 0x1F},	/* Display FIFO Control            */
	{VIASR, SR18, 0xFF, 0x4E},	/* GFX PREQ threshold              */
	{VIASR, SR1A, 0xFF, 0x0a},	/* GFX PREQ threshold              */
	{VIASR, SR1F, 0xFF, 0x00},	/* Memory Control 0                */
	{VIASR, SR1B, 0xFF, 0xF0},	/* Power Management Control 0      */
	{VIASR, SR1E, 0xFF, 0x01},	/* Power Management Control        */
	{VIASR, SR20, 0xFF, 0x00},	/* Sequencer Arbiter Control 0     */
	{VIASR, SR21, 0xFF, 0x00},	/* Sequencer Arbiter Control 1     */
	{VIASR, SR22, 0xFF, 0x1F},	/* Display Arbiter Control 1       */
	{VIASR, SR2A, 0xFF, 0x00},	/* Power Management Control 5      */
	{VIASR, SR2D, 0xFF, 0xFF},	/* Power Management Control 1      */
	{VIASR, SR2E, 0xFF, 0xFF},	/* Power Management Control 2      */
	{VIACR, CR0A, 0xFF, 0x1E},	/* Cursor Start                    */
	{VIACR, CR0B, 0xFF, 0x00},	/* Cursor End                      */
	{VIACR, CR0E, 0xFF, 0x00},	/* Cursor Location High            */
	{VIACR, CR0F, 0xFF, 0x00},	/* Cursor Localtion Low            */
	{VIACR, CR33, 0xFF, 0x00},
	{VIACR, CR55, 0x80, 0x00},
	{VIACR, CR5D, 0x80, 0x00},
	{VIACR, CR36, 0xFF, 0x01},	/* Power Mangement 3                  */
	{VIACR, CR68, 0xFF, 0x67},	/* Default FIFO For IGA2              */
	{VIACR, CR6A, 0x20, 0x20},	/* Extended FIFO On                   */
	{VIACR, CR7A, 0xFF, 0x01},	/* LCD Scaling Parameter 1            */
	{VIACR, CR7B, 0xFF, 0x02},	/* LCD Scaling Parameter 2            */
	{VIACR, CR7C, 0xFF, 0x03},	/* LCD Scaling Parameter 3            */
	{VIACR, CR7D, 0xFF, 0x04},	/* LCD Scaling Parameter 4            */
	{VIACR, CR7E, 0xFF, 0x07},	/* LCD Scaling Parameter 5            */
	{VIACR, CR7F, 0xFF, 0x0A},	/* LCD Scaling Parameter 6            */
	{VIACR, CR80, 0xFF, 0x0D},	/* LCD Scaling Parameter 7            */
	{VIACR, CR81, 0xFF, 0x13},	/* LCD Scaling Parameter 8            */
	{VIACR, CR82, 0xFF, 0x16},	/* LCD Scaling Parameter 9            */
	{VIACR, CR83, 0xFF, 0x19},	/* LCD Scaling Parameter 10           */
	{VIACR, CR84, 0xFF, 0x1C},	/* LCD Scaling Parameter 11           */
	{VIACR, CR85, 0xFF, 0x1D},	/* LCD Scaling Parameter 12           */
	{VIACR, CR86, 0xFF, 0x1E},	/* LCD Scaling Parameter 13           */
	{VIACR, CR87, 0xFF, 0x1F},	/* LCD Scaling Parameter 14           */
	{VIACR, CR88, 0xFF, 0x40},	/* LCD Panel Type                     */
	{VIACR, CR89, 0xFF, 0x00},	/* LCD Timing Control 0               */
	{VIACR, CR8A, 0xFF, 0x88},	/* LCD Timing Control 1               */
	{VIACR, CR8B, 0xFF, 0x2D},	/* LCD Power Sequence Control 0       */
	{VIACR, CR8C, 0xFF, 0x2D},	/* LCD Power Sequence Control 1       */
	{VIACR, CR8D, 0xFF, 0xC8},	/* LCD Power Sequence Control 2       */
	{VIACR, CR8E, 0xFF, 0x36},	/* LCD Power Sequence Control 3       */
	{VIACR, CR8F, 0xFF, 0x00},	/* LCD Power Sequence Control 4       */
	{VIACR, CR90, 0xFF, 0x10},	/* LCD Power Sequence Control 5       */
	{VIACR, CR91, 0xFF, 0xA0},	/* 24/12 bit LVDS Data off            */
	{VIACR, CR96, 0xFF, 0x03},	/* DVP0        ; DVP0 Clock Skew */
	{VIACR, CR97, 0xFF, 0x03},	/* DFP high    ; DFPH Clock Skew */
	{VIACR, CR99, 0xFF, 0x03},	/* DFP low           ; DFPL Clock Skew*/
	{VIACR, CR9B, 0xFF, 0x07}	/* DVI on DVP1       ; DVP1 Clock Skew*/
};

/* For VT3324: Common Setting for Video Mode */
struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
{VIASR, SR15, 0x02, 0x02},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR17, 0xFF, 0x1F},
{VIASR, SR18, 0xFF, 0x4E},
{VIASR, SR1A, 0xFB, 0x08},
{VIASR, SR1B, 0xFF, 0xF0},
{VIASR, SR1E, 0xFF, 0x01},
{VIASR, SR2A, 0xFF, 0x00},
{VIASR, SR2D, 0xFF, 0xFF},	/* VCK and LCK PLL power on.           */
{VIACR, CR0A, 0xFF, 0x1E},	/* Cursor Start                        */
{VIACR, CR0B, 0xFF, 0x00},	/* Cursor End                          */
{VIACR, CR0E, 0xFF, 0x00},	/* Cursor Location High                */
{VIACR, CR0F, 0xFF, 0x00},	/* Cursor Localtion Low                */
{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR33, 0xFF, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0x08, 0x00},
{VIACR, CR47, 0xC8, 0x00},	/* Clear VCK Plus. */
{VIACR, CR69, 0xFF, 0x00},
{VIACR, CR6A, 0xFF, 0x40},
{VIACR, CR6B, 0xFF, 0x00},
{VIACR, CR6C, 0xFF, 0x00},
{VIACR, CR7A, 0xFF, 0x01},	/* LCD Scaling Parameter 1             */
{VIACR, CR7B, 0xFF, 0x02},	/* LCD Scaling Parameter 2             */
{VIACR, CR7C, 0xFF, 0x03},	/* LCD Scaling Parameter 3             */
{VIACR, CR7D, 0xFF, 0x04},	/* LCD Scaling Parameter 4             */
{VIACR, CR7E, 0xFF, 0x07},	/* LCD Scaling Parameter 5             */
{VIACR, CR7F, 0xFF, 0x0A},	/* LCD Scaling Parameter 6             */
{VIACR, CR80, 0xFF, 0x0D},	/* LCD Scaling Parameter 7             */
{VIACR, CR81, 0xFF, 0x13},	/* LCD Scaling Parameter 8             */
{VIACR, CR82, 0xFF, 0x16},	/* LCD Scaling Parameter 9             */
{VIACR, CR83, 0xFF, 0x19},	/* LCD Scaling Parameter 10            */
{VIACR, CR84, 0xFF, 0x1C},	/* LCD Scaling Parameter 11            */
{VIACR, CR85, 0xFF, 0x1D},	/* LCD Scaling Parameter 12            */
{VIACR, CR86, 0xFF, 0x1E},	/* LCD Scaling Parameter 13            */
{VIACR, CR87, 0xFF, 0x1F},	/* LCD Scaling Parameter 14            */
{VIACR, CR88, 0xFF, 0x40},	/* LCD Panel Type                      */
{VIACR, CR89, 0xFF, 0x00},	/* LCD Timing Control 0                */
{VIACR, CR8A, 0xFF, 0x88},	/* LCD Timing Control 1                */
{VIACR, CRD4, 0xFF, 0x81},	/* Second power sequence control       */
{VIACR, CR8B, 0xFF, 0x5D},	/* LCD Power Sequence Control 0        */
{VIACR, CR8C, 0xFF, 0x2B},	/* LCD Power Sequence Control 1        */
{VIACR, CR8D, 0xFF, 0x6F},	/* LCD Power Sequence Control 2        */
{VIACR, CR8E, 0xFF, 0x2B},	/* LCD Power Sequence Control 3        */
{VIACR, CR8F, 0xFF, 0x01},	/* LCD Power Sequence Control 4        */
{VIACR, CR90, 0xFF, 0x01},	/* LCD Power Sequence Control 5        */
{VIACR, CR91, 0xFF, 0x80},	/* 24/12 bit LVDS Data off             */
{VIACR, CR96, 0xFF, 0x00},
{VIACR, CR97, 0xFF, 0x00},
{VIACR, CR99, 0xFF, 0x00},
{VIACR, CR9B, 0xFF, 0x00}
};

/* Video Mode Table */
/* Common Setting for Video Mode */
struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00},
{VIASR, SR2A, 0x0F, 0x00},
{VIASR, SR15, 0x02, 0x02},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR17, 0xFF, 0x1F},
{VIASR, SR18, 0xFF, 0x4E},
{VIASR, SR1A, 0xFB, 0x08},

{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0x08, 0x00},
{VIACR, CR6A, 0xFF, 0x80},
{VIACR, CR6A, 0xFF, 0xC0},
{'fraction_non_alphanumeric': 0.15328235555414538, 'fraction_numerical': 0.16108766697337945, 'mean_word_length': 3.076833527357392, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 3, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '7219353', 'n_tokens_mistral': 17878, 'n_tokens_neox': 13968, 'n_words': 3773}