<commit_before># FEI4A
fei4a = {
    'flavor': 'fei4a',
    'calibration_parameters': {
        'C_Inj_Low': 2.0,  # fF
        'C_Inj_Med': 4.1,  # fF
        'C_Inj_High': 6.1,  # fF
        'Vcal_Coeff_0': None,  # mV
        'Vcal_Coeff_1': 1.5,  # mV/PlsrDAC
        'Pulser_Corr_C_Inj_Low': None,
        'Pulser_Corr_C_Inj_Med': None,
        'Pulser_Corr_C_Inj_High': None
    },
    'commands': {
        # fast
        'LV1': {'bitstream': '11101', 'bitlength': 5, 'description': 'Level 1 Trigger: a single bit flip in the LV1 command will still result in a LV1 being decoded'},
        'BCR': {'bitstream': '101100001', 'bitlength': 9, 'description': 'Bunch Counter Reset: the bunch crossing counter is set to zero'},
        'ECR': {'bitstream': '101100010', 'bitlength': 9, 'description': 'Event Counter Reset: clears all memory pointers and data structures without touching configuration memory'},
        'CAL': {'bitstream': '101100100', 'bitlength': 9, 'description': 'Calibration Pulse: digital or analog calibration pulse is distributed to the pixel array'},
        'Slow': {'bitstream': '101101000', 'bitlength': 9, 'description': 'Slow command header'},
        # slow
        'RdRegister': {'bitstream': 'Slow+0001+ChipID+Address', 'bitlength': 23, 'description': 'Read Register: read global memory register'},
        'WrRegister': {'bitstream': 'Slow+0010+ChipID+Address+GlobalData', 'bitlength': 39, 'description': 'Write Register: write global memory register'},
        'WrFrontEnd': {'bitstream': 'Slow+0100+ChipID+000000+PixelData', 'bitlength': 695, 'description': 'Write Pixel: write conf data to selected shift register'},
        'GlobalReset': {'bitstream': 'Slow+1000+ChipID', 'bitlength': 17, 'description': 'Reset Command: puts chip in initial state'},
        'GlobalPulse': {'bitstream': 'Slow+1001+ChipID+Width', 'bitlength': 23, 'description': 'Global Pulse: e.g. functionality determined by the Control Pulser register'},
        'RunMode': {'bitstream': 'Slow+1010+ChipID+111000', 'bitlength': 23, 'description': 'Run Mode'},
        'ConfMode': {'bitstream': 'Slow+1010+ChipID+000111', 'bitlength': 23, 'description': 'Configuration Mode (default for power-up or reset)'},
        # parts
        'ChipID': {'value': 0, 'bitlength': 4, 'description': 'Read Register: read global memory register'},
        'Address': {'value': 0, 'bitlength': 6, 'description': 'Write Register: write global memory register'},
        'GlobalData': {'value': 0, 'bitlength': 16, 'description': 'Gloabal Register data: payload of WrRegister'},
        'PixelData': {'value': 0, 'bitlength': 672, 'description': 'Pixel Register data: payload of WrFrontEnd'},
        'Width': {'value': 0, 'bitlength': 6, 'description': 'Width of of Global Pulse'},
    },<commit_msg>ENH: comments, update default values<commit_after># FEI4A
fei4a = {
    'flavor': 'fei4a',
    'calibration_parameters': {
        'C_Inj_Low': 2.0,  # fF, C_Low
        'C_Inj_Med': 4.1,  # fF, C_High
        'C_Inj_High': 6.1,  # fF, C_Low + C_High
        'Vcal_Coeff_0': 0.0,  # mV, offset
        'Vcal_Coeff_1': 1.5,  # mV/PlsrDAC, slope
        'Pulser_Corr_C_Inj_Low': None,
        'Pulser_Corr_C_Inj_Med': None,
        'Pulser_Corr_C_Inj_High': None
    },
    'commands': {
        # fast
        'LV1': {'bitstream': '11101', 'bitlength': 5, 'description': 'Level 1 Trigger: a single bit flip in the LV1 command will still result in a LV1 being decoded'},
        'BCR': {'bitstream': '101100001', 'bitlength': 9, 'description': 'Bunch Counter Reset: the bunch crossing counter is set to zero'},
        'ECR': {'bitstream': '101100010', 'bitlength': 9, 'description': 'Event Counter Reset: clears all memory pointers and data structures without touching configuration memory'},
        'CAL': {'bitstream': '101100100', 'bitlength': 9, 'description': 'Calibration Pulse: digital or analog calibration pulse is distributed to the pixel array'},
        'Slow': {'bitstream': '101101000', 'bitlength': 9, 'description': 'Slow command header'},
        # slow
        'RdRegister': {'bitstream': 'Slow+0001+ChipID+Address', 'bitlength': 23, 'description': 'Read Register: read global memory register'},
        'WrRegister': {'bitstream': 'Slow+0010+ChipID+Address+GlobalData', 'bitlength': 39, 'description': 'Write Register: write global memory register'},
        'WrFrontEnd': {'bitstream': 'Slow+0100+ChipID+000000+PixelData', 'bitlength': 695, 'description': 'Write Pixel: write conf data to selected shift register'},
        'GlobalReset': {'bitstream': 'Slow+1000+ChipID', 'bitlength': 17, 'description': 'Reset Command: puts chip in initial state'},
        'GlobalPulse': {'bitstream': 'Slow+1001+ChipID+Width', 'bitlength': 23, 'description': 'Global Pulse: e.g. functionality determined by the Control Pulser register'},
        'RunMode': {'bitstream': 'Slow+1010+ChipID+111000', 'bitlength': 23, 'description': 'Run Mode'},
        'ConfMode': {'bitstream': 'Slow+1010+ChipID+000111', 'bitlength': 23, 'description': 'Configuration Mode (default for power-up or reset)'},
        # parts
        'ChipID': {'bitlength': 4, 'description': 'Read Register: read global memory register'},
        'Address': {'bitlength': 6, 'description': 'Write Register: write global memory register'},
        'GlobalData': {'bitlength': 16, 'description': 'Gloabal Register data: payload of WrRegister'},
        'PixelData': {'bitlength': 672, 'description': 'Pixel Register data: payload of WrFrontEnd'},
        'Width': {'bitlength': 6, 'description': 'Width of of Global Pulse'},
    },
{'fraction_non_alphanumeric': 0.1607079013228459, 'fraction_numerical': 0.048444762245262785, 'mean_word_length': 4.175763182238668, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 3, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '2862917', 'n_tokens_mistral': 1953, 'n_tokens_neox': 1716, 'n_words': 538}