<commit_before>/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: src/import/chips/p10/procedures/hwp/nest/p10_smp_link_firs.C $ */
/*                                                                        */
/* OpenPOWER HostBoot Project                                             */
/*                                                                        */
/* Contributors Listed Below - COPYRIGHT 2019,2020                        */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* Licensed under the Apache License, Version 2.0 (the "License");        */
/* you may not use this file except in compliance with the License.       */
/* You may obtain a copy of the License at                                */
/*                                                                        */
/*     http://www.apache.org/licenses/LICENSE-2.0                         */
/*                                                                        */
/* Unless required by applicable law or agreed to in writing, software    */
/* distributed under the License is distributed on an "AS IS" BASIS,      */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
/* implied. See the License for the specific language governing           */
/* permissions and limitations under the License.                         */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */
///
/// @file p10_smp_link_firs.H
/// @brief Setup the FIR mask and action registers for a given SMP link
///
/// *HWP HW Maintainer: <NAME> <<EMAIL>>
/// *HWP FW Maintainer: <NAME> <<EMAIL>>
/// *HWP Consumed by: SBE
///

//------------------------------------------------------------------------------
// Includes
//------------------------------------------------------------------------------
#include <p10_smp_link_firs.H>
#include <p10_fbc_utils.H>
#include <target_filters.H>

#include <p10_scom_proc.H>
#include <p10_scom_pauc.H>
#include <p10_scom_iohs.H>

//------------------------------------------------------------------------------
// Constant definitions
//------------------------------------------------------------------------------

// Struct that contains the bits to modify (btm) in a fir
// register for a given IOHS link (and sublink if applicable)
struct fir_registers_btm
{
    uint64_t EXT_FIR[FABRIC_NUM_IOHS_LINKS];
    uint64_t PTL_FIR[NUM_SUBLINK_OPTS][FABRIC_NUM_IOHS_LINKS];
    uint64_t DLP_FIR[NUM_SUBLINK_OPTS];
    uint64_t PHY_FIR[FABRIC_NUM_IOHS_LINKS];
};

const struct fir_registers_btm firs_btm =
{
    .EXT_FIR =
    {
        0x8000000000000000, // iohs0
        0x4000000000000000, // iohs1
        0x2000000000000000, // iohs2
        0x1000000000000000, // iohs3
        0x0800000000000000, // iohs4
        0x0400000000000000, // iohs5
        0x0200000000000000, // iohs6
        0x0100000000000000, // iohs7
    },
    .PTL_FIR =
    {
        {
            // both even/odd
            0xCF0E332F0C000000, // iohs0
            0x30F1CCD0F3000000, // iohs1
            0xCF0E332F0C000000, // iohs2
            0x30F1CCD0F3000000, // iohs3
            0xCF0E332F0C000000, // iohs4
            0x30F1CCD0F3000000, // iohs5
            0xCF0E332F0C000000, // iohs6
            0x30F1CCD0F3000000, // iohs7
        },
        {
            // even only
            0x8F08222C08000000, // iohs0
            0x20F18890C2000000, // iohs1
            0x8F08222C08000000, // iohs2
            0x20F18890C2000000, // iohs3
            0x8F08222C08000000, // iohs4
            0x20F18890C2000000, // iohs5
            0x8F08222C08000000, // iohs6
            0x20F18890C2000000, // iohs7
        },
        {
            // odd only
            0x4F06112304000000, // iohs0
            0x10F0C45031000000, // iohs1
            0x4F06112304000000, // iohs2
            0x10F0C45031000000, // iohs3
            0x4F06112304000000, // iohs4
            0x10F0C45031000000, // iohs5
            0x4F06112304000000, // iohs6
            0x10F0C45031000000, // iohs7
        },
    },
    .DLP_FIR =
    {
        0xFFFFFFFFFFFFFFFF, // both halves
        0xAAAAAAAAAAAAAAAA, // even only
        0x5555555555555555, // odd only
    },
    .PHY_FIR =
    {
        0x88FFFFC000000000, // iohs0
        0x44FFFFC000000000, // iohs1
        0x88FFFFC000000000, // iohs2
        0x44FFFFC000000000, // iohs3
        0x88FFFFC000000000, // iohs4
        0x44FFFFC000000000, // iohs5
        0x88FFFFC000000000, // iohs6
        0x44FFFFC000000000, // iohs7
    },
};

// Struct that contains the values to program in a fir register
// and the formed values (clr/set) to apply to mask registers
// based on a given IOHS (and sublink if applicable)
struct fir_registers
{
    uint64_t EXT_FIR_ACTION0;
    uint64_t EXT_FIR_ACTION1;
    uint64_t EXT_FIR_MASK;

    uint64_t PTL_FIR_ACTION0;
    uint64_t PTL_FIR_ACTION1;
    uint64_t PTL_FIR_MASK;

    uint64_t DLP_FIR_ACTION0;
    uint64_t DLP_FIR_ACTION1;
    uint64_t DLP_FIR_MASK;

    uint64_t PHY_FIR_ACTION0;
    uint64_t PHY_FIR_ACTION1;
    uint64_t PHY_FIR_MASK;

    uint64_t EXT_FIR_MASK_CLR;
    uint64_t EXT_FIR_MASK_SET;
    uint64_t PTL_FIR_MASK_CLR;
    uint64_t PTL_FIR_MASK_SET;
    uint64_t DLP_FIR_MASK_CLR;
    uint64_t DLP_FIR_MASK_SET;
    uint64_t PHY_FIR_MASK_CLR;
    uint64_t PHY_FIR_MASK_SET;
};

const struct fir_registers firs_inactive =
{
    .EXT_FIR_ACTION0 = 0x0000000000000000,
    .EXT_FIR_ACTION1 = 0x0000000000000000,
    .EXT_FIR_MASK    = 0xFFFFFFFFFFFFFFFF,

    .PTL_FIR_ACTION0 = 0xF22003CFFFFFFFFF,
    .PTL_FIR_ACTION1 = 0xF66003CFFFFFFFFF,
    .PTL_FIR_MASK    = 0xFFFFFFFFFFFFFFFF,

    .DLP_FIR_ACTION0 = 0xFCFC3FFFFCC00003,
    .DLP_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFF,
    .DLP_FIR_MASK    = 0xFFFFFFFFFFFFFFFF,

    .PHY_FIR_ACTION0 = 0x8000000000000000,
    .PHY_FIR_ACTION1 = 0xF47FDB0000000000,
    .PHY_FIR_MASK    = 0xFFFFFFFFFFFFFFFF,
};

const struct fir_registers firs_runtime =
{
    .EXT_FIR_ACTION0 = 0x0000000000000000,
    .EXT_FIR_ACTION1 = 0x0000000000000000,
    .EXT_FIR_MASK    = 0x00FFFFFFFFFFFFFF,

    .PTL_FIR_ACTION0 = 0xF22003CFFFFFFFFF,
    .PTL_FIR_ACTION1 = 0xF66003CFFFFFFFFF,
    .PTL_FIR_MASK    = 0xF22003CFFFFFFFFF,

    .DLP_FIR_ACTION0 = 0xFCFC3FFFFCC00003,
    .DLP_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFF,
    .DLP_FIR_MASK    = 0xFCFC3FFFFCC00003,

    .PHY_FIR_ACTION0 = 0x8000000000000000,
    .PHY_FIR_ACTION1 = 0xF47FDB0000000000,
    .PHY_FIR_MASK    = 0x0B8024C000000000,
};

// DL Config Register Enums
const uint8_t DLP_PHY_CONFIG_DL_SELECT_DLP  = 0x01;

//------------------------------------------------------------------------------
// Function definitions
//------------------------------------------------------------------------------

/// @brief Display values to be programmed into FIR registers
/// @param[in] i_target  Reference to IOHS target
/// @param[in] i_data    Data to display for given target
/// @return void.
void p10_smp_link_firs_display(
    const fapi2::Target<fapi2::TARGET_TYPE_IOHS>& i_iohs_target,
    const struct fir_registers& i_data)
{
    char l_target_str[fapi2::MAX_ECMD_STRING_LEN];
    fapi2::toString(i_iohs_target, l_target_str, sizeof(l_target_str));<commit_msg>unmasked bits 22:25<commit_after>/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: src/import/chips/p10/procedures/hwp/nest/p10_smp_link_firs.C $ */
/*                                                                        */
/* OpenPOWER HostBoot Project                                             */
/*                                                                        */
/* Contributors Listed Below - COPYRIGHT 2019,2020                        */
/* [+] International Business Machines Corp.                              */
/*                                                                        */
/*                                                                        */
/* Licensed under the Apache License, Version 2.0 (the "License");        */
/* you may not use this file except in compliance with the License.       */
/* You may obtain a copy of the License at                                */
/*                                                                        */
/*     http://www.apache.org/licenses/LICENSE-2.0                         */
/*                                                                        */
/* Unless required by applicable law or agreed to in writing, software    */
/* distributed under the License is distributed on an "AS IS" BASIS,      */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
/* implied. See the License for the specific language governing           */
/* permissions and limitations under the License.                         */
/*                                                                        */
/* IBM_PROLOG_END_TAG                                                     */
///
/// @file p10_smp_link_firs.H
/// @brief Setup the FIR mask and action registers for a given SMP link
///
/// *HWP HW Maintainer: <NAME> <<EMAIL>>
/// *HWP FW Maintainer: <NAME> <<EMAIL>>
/// *HWP Consumed by: SBE
///

//------------------------------------------------------------------------------
// Includes
//------------------------------------------------------------------------------
#include <p10_smp_link_firs.H>
#include <p10_fbc_utils.H>
#include <target_filters.H>

#include <p10_scom_proc.H>
#include <p10_scom_pauc.H>
#include <p10_scom_iohs.H>

//------------------------------------------------------------------------------
// Constant definitions
//------------------------------------------------------------------------------

// Struct that contains the bits to modify (btm) in a fir
// register for a given IOHS link (and sublink if applicable)
struct fir_registers_btm
{
    uint64_t EXT_FIR[FABRIC_NUM_IOHS_LINKS];
    uint64_t PTL_FIR[NUM_SUBLINK_OPTS][FABRIC_NUM_IOHS_LINKS];
    uint64_t DLP_FIR[NUM_SUBLINK_OPTS];
    uint64_t PHY_FIR[FABRIC_NUM_IOHS_LINKS];
};

const struct fir_registers_btm firs_btm =
{
    .EXT_FIR =
    {
        0x8000000000000000, // iohs0
        0x4000000000000000, // iohs1
        0x2000000000000000, // iohs2
        0x1000000000000000, // iohs3
        0x0800000000000000, // iohs4
        0x0400000000000000, // iohs5
        0x0200000000000000, // iohs6
        0x0100000000000000, // iohs7
    },
    .PTL_FIR =
    {
        {
            // both even/odd
            0xCF0E332F0C000000, // iohs0
            0x30F1CCD0F3000000, // iohs1
            0xCF0E332F0C000000, // iohs2
            0x30F1CCD0F3000000, // iohs3
            0xCF0E332F0C000000, // iohs4
            0x30F1CCD0F3000000, // iohs5
            0xCF0E332F0C000000, // iohs6
            0x30F1CCD0F3000000, // iohs7
        },
        {
            // even only
            0x8F08222C08000000, // iohs0
            0x20F18890C2000000, // iohs1
            0x8F08222C08000000, // iohs2
            0x20F18890C2000000, // iohs3
            0x8F08222C08000000, // iohs4
            0x20F18890C2000000, // iohs5
            0x8F08222C08000000, // iohs6
            0x20F18890C2000000, // iohs7
        },
        {
            // odd only
            0x4F06112304000000, // iohs0
            0x10F0C45031000000, // iohs1
            0x4F06112304000000, // iohs2
            0x10F0C45031000000, // iohs3
            0x4F06112304000000, // iohs4
            0x10F0C45031000000, // iohs5
            0x4F06112304000000, // iohs6
            0x10F0C45031000000, // iohs7
        },
    },
    .DLP_FIR =
    {
        0xFFFFFFFFFFFFFFFF, // both halves
        0xAAAAAAAAAAAAAAAA, // even only
        0x5555555555555555, // odd only
    },
    .PHY_FIR =
    {
        0x88FFFFC000000000, // iohs0
        0x44FFFFC000000000, // iohs1
        0x88FFFFC000000000, // iohs2
        0x44FFFFC000000000, // iohs3
        0x88FFFFC000000000, // iohs4
        0x44FFFFC000000000, // iohs5
        0x88FFFFC000000000, // iohs6
        0x44FFFFC000000000, // iohs7
    },
};

// Struct that contains the values to program in a fir register
// and the formed values (clr/set) to apply to mask registers
// based on a given IOHS (and sublink if applicable)
struct fir_registers
{
    uint64_t EXT_FIR_ACTION0;
    uint64_t EXT_FIR_ACTION1;
    uint64_t EXT_FIR_MASK;

    uint64_t PTL_FIR_ACTION0;
    uint64_t PTL_FIR_ACTION1;
    uint64_t PTL_FIR_MASK;

    uint64_t DLP_FIR_ACTION0;
    uint64_t DLP_FIR_ACTION1;
    uint64_t DLP_FIR_MASK;

    uint64_t PHY_FIR_ACTION0;
    uint64_t PHY_FIR_ACTION1;
    uint64_t PHY_FIR_MASK;

    uint64_t EXT_FIR_MASK_CLR;
    uint64_t EXT_FIR_MASK_SET;
    uint64_t PTL_FIR_MASK_CLR;
    uint64_t PTL_FIR_MASK_SET;
    uint64_t DLP_FIR_MASK_CLR;
    uint64_t DLP_FIR_MASK_SET;
    uint64_t PHY_FIR_MASK_CLR;
    uint64_t PHY_FIR_MASK_SET;
};

const struct fir_registers firs_inactive =
{
    .EXT_FIR_ACTION0 = 0x0000000000000000,
    .EXT_FIR_ACTION1 = 0x0000000000000000,
    .EXT_FIR_MASK    = 0xFFFFFFFFFFFFFFFF,

    .PTL_FIR_ACTION0 = 0xF220000FFFFFFFFF,
    .PTL_FIR_ACTION1 = 0xF660000FFFFFFFFF,
    .PTL_FIR_MASK    = 0xFFFFFFFFFFFFFFFF,

    .DLP_FIR_ACTION0 = 0xFCFC3FFFFCC00003,
    .DLP_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFF,
    .DLP_FIR_MASK    = 0xFFFFFFFFFFFFFFFF,

    .PHY_FIR_ACTION0 = 0x8000000000000000,
    .PHY_FIR_ACTION1 = 0xF47FDB0000000000,
    .PHY_FIR_MASK    = 0xFFFFFFFFFFFFFFFF,
};

const struct fir_registers firs_runtime =
{
    .EXT_FIR_ACTION0 = 0x0000000000000000,
    .EXT_FIR_ACTION1 = 0x0000000000000000,
    .EXT_FIR_MASK    = 0x00FFFFFFFFFFFFFF,

    .PTL_FIR_ACTION0 = 0xF220000FFFFFFFFF,
    .PTL_FIR_ACTION1 = 0xF660000FFFFFFFFF,
    .PTL_FIR_MASK    = 0xF220000FFFFFFFFF,

    .DLP_FIR_ACTION0 = 0xFCFC3FFFFCC00003,
    .DLP_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFF,
    .DLP_FIR_MASK    = 0xFCFC3FFFFCC00003,

    .PHY_FIR_ACTION0 = 0x8000000000000000,
    .PHY_FIR_ACTION1 = 0xF47FDB0000000000,
    .PHY_FIR_MASK    = 0x0B8024C000000000,
};

// DL Config Register Enums
const uint8_t DLP_PHY_CONFIG_DL_SELECT_DLP  = 0x01;

//------------------------------------------------------------------------------
// Function definitions
//------------------------------------------------------------------------------

/// @brief Display values to be programmed into FIR registers
/// @param[in] i_target  Reference to IOHS target
/// @param[in] i_data    Data to display for given target
/// @return void.
void p10_smp_link_firs_display(
    const fapi2::Target<fapi2::TARGET_TYPE_IOHS>& i_iohs_target,
    const struct fir_registers& i_data)
{
    char l_target_str[fapi2::MAX_ECMD_STRING_LEN];
    fapi2::toString(i_iohs_target, l_target_str, sizeof(l_target_str));
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