<commit_before>/* Copyright 2020 The Chromium OS Authors. All rights reserved.
 * Use of this source code is governed by a BSD-style license that can be
 * found in the LICENSE file.
 */

/* TCPM on ITE chip it8xxx2 with embedded TCPC */

#include "common.h"
#include "config.h"
#include "console.h"
#include "it83xx_pd.h"
#include "registers.h"
#include "system.h"
#include "task.h"
#include "timer.h"
#include "util.h"
#include "usb_common.h"
#include "usb_pd.h"
#include "usb_pd_tcpm.h"
#include "hooks.h"

#ifdef CONFIG_USB_PD_TCPMV1
#if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) || \
	defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) || \
	defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \
	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
#error "Unsupported config options of IT8xxx2 PD driver"
#endif
#endif

#ifdef CONFIG_USB_PD_TCPMV2
#if defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) || \
	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
#error "Unsupported config options of IT8xxx2 PD driver"
#endif
#endif

#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)

bool rx_en[IT83XX_USBPD_PHY_PORT_COUNT];
STATIC_IF(CONFIG_USB_PD_DECODE_SOP)
	bool sop_prime_en[IT83XX_USBPD_PHY_PORT_COUNT];
static uint8_t tx_error_status[IT83XX_USBPD_PHY_PORT_COUNT] = {0};

const struct usbpd_ctrl_t usbpd_ctrl_regs[] = {
	{&IT83XX_GPIO_GPCRF4, &IT83XX_GPIO_GPCRF5, IT83XX_IRQ_USBPD0},
	{&IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, IT83XX_IRQ_USBPD1},
	{&IT83XX_GPIO_GPCRP0, &IT83XX_GPIO_GPCRP1, IT83XX_IRQ_USBPD2},
};
BUILD_ASSERT(ARRAY_SIZE(usbpd_ctrl_regs) >= IT83XX_USBPD_PHY_PORT_COUNT);

/*
 * Disable cc analog and pd digital module, but only left Rd_5.1K (Not
 * Rd_DB) analog module alive to assert Rd on CCs. EC reset or calling
 * _init() are able to re-active cc and pd.
 */
void it83xx_Rd_5_1K_only_for_hibernate(int port)
{
	uint8_t cc_config = (port == USBPD_PORT_C ?
			     IT83XX_USBPD_CC_PIN_CONFIG2 :
			     IT83XX_USBPD_CC_PIN_CONFIG);

	/* This only apply to active PD port */
	if (*usbpd_ctrl_regs[port].cc1 == cc_config &&<commit_msg>zephyr: tcpm: Update ITE driver to support zephyr names<commit_after>/* Copyright 2020 The Chromium OS Authors. All rights reserved.
 * Use of this source code is governed by a BSD-style license that can be
 * found in the LICENSE file.
 */

/* TCPM on ITE chip it8xxx2 with embedded TCPC */

#include "common.h"
#include "config.h"
#include "console.h"
#include "it83xx_pd.h"
#include "registers.h"
#include "system.h"
#include "task.h"
#include "timer.h"
#include "util.h"
#include "usb_common.h"
#include "usb_pd.h"
#include "usb_pd_tcpm.h"
#include "hooks.h"

#ifdef CONFIG_USB_PD_TCPMV1
#if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) || \
	defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) || \
	defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \
	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
#error "Unsupported config options of IT8xxx2 PD driver"
#endif
#endif

#ifdef CONFIG_USB_PD_TCPMV2
#if defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) || \
	defined(CONFIG_USB_PD_DISCHARGE_TCPC)
#error "Unsupported config options of IT8xxx2 PD driver"
#endif
#endif

#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)

#ifdef CONFIG_ZEPHYR
/* Use the Zephyr names here. When upstreaming we can update this */
#include <dt-bindings/interrupt-controller/ite-intc.h>

#define IT83XX_GPIO_GPCRF4	GPCRF4
#define IT83XX_GPIO_GPCRF5	GPCRF5
#define IT83XX_GPIO_GPCRH1	GPCRH1
#define IT83XX_GPIO_GPCRH2	GPCRH2
#define IT83XX_GPIO_GPCRP0	IT8XXX2_GPIO_GPCRP0
#define IT83XX_GPIO_GPCRP1	IT8XXX2_GPIO_GPCRP1
#define IT83XX_IRQ_USBPD0	IT8XXX2_IRQ_USBPD0
#define IT83XX_IRQ_USBPD1	IT8XXX2_IRQ_USBPD1
#define IT83XX_IRQ_USBPD2	IT8XXX2_IRQ_USBPD2
#define USB_VID_ITE		0x048d
#endif

bool rx_en[IT83XX_USBPD_PHY_PORT_COUNT];
STATIC_IF(CONFIG_USB_PD_DECODE_SOP)
	bool sop_prime_en[IT83XX_USBPD_PHY_PORT_COUNT];
static uint8_t tx_error_status[IT83XX_USBPD_PHY_PORT_COUNT] = {0};

const struct usbpd_ctrl_t usbpd_ctrl_regs[] = {
	{&IT83XX_GPIO_GPCRF4, &IT83XX_GPIO_GPCRF5, IT83XX_IRQ_USBPD0},
	{&IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, IT83XX_IRQ_USBPD1},
	{&IT83XX_GPIO_GPCRP0, &IT83XX_GPIO_GPCRP1, IT83XX_IRQ_USBPD2},
};
BUILD_ASSERT(ARRAY_SIZE(usbpd_ctrl_regs) >= IT83XX_USBPD_PHY_PORT_COUNT);

/*
 * Disable cc analog and pd digital module, but only left Rd_5.1K (Not
 * Rd_DB) analog module alive to assert Rd on CCs. EC reset or calling
 * _init() are able to re-active cc and pd.
 */
void it83xx_Rd_5_1K_only_for_hibernate(int port)
{
	uint8_t cc_config = (port == USBPD_PORT_C ?
			     IT83XX_USBPD_CC_PIN_CONFIG2 :
			     IT83XX_USBPD_CC_PIN_CONFIG);

	/* This only apply to active PD port */
	if (*usbpd_ctrl_regs[port].cc1 == cc_config &&
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