<commit_before>#ifdef PERFCTR20
#define PERFCTR18
#endif
/* This substrate should never malloc anything. All allocation should be
   done by the high level API. */

/* The values defined in this file may be X86-specific (2 general 
   purpose counters, 1 special purpose counter, etc.*/

/* PAPI stuff */

#include SUBSTRATE

/* First entry is mask, counter code 1, counter code 2, and TSC. 
A high bit in the mask entry means it is an OR mask, not an
and mask. This means that the same even is available on either
counter. */

static hwd_preset_t *preset_map;

static hwd_preset_t p6_preset_map[PAPI_MAX_PRESET_EVENTS] = { 
  {CNTR2|CNTR1,0,0,{{0x45,0x45,0x0,0x0}},""},	// L1 Cache Dmisses 
  {CNTR2|CNTR1,0,0,{{0x81,0x81,0x0,0x0}},""},	// L1 Cache Imisses 
  {0,0,0,{{0,0,0x0,0x0}},""}, 			// L2 Cache Dmisses
  {0,0,0,{{0,0,0x0,0x0}},""}, 			// L2 Cache Imisses
  {0,0,0,{{0,0,0x0,0x0}},""}, 			// L3 Cache Dmisses
  {0,0,0,{{0,0,0x0,0x0}},""}, 			// L3 Cache Imisses
  {CNTR2|CNTR1,0,0,{{0xf2e,0xf2e,0x0,0x0}},""},	// L1 Total Cache misses 
  {CNTR2|CNTR1,0,0,{{0x24,0x24,0x0,0x0}},""}, 	// L2 Total Cache misses
  {0,0,0,{{0,0,0x0,0x0}},""}, 			// L3 Total Cache misses
  {0,0,0,{{0,0,0x0,0x0}},""},			// Snoops
  {CNTR2|CNTR1,0,0,{{0x222e,0x222e,0x0,0x0}},""},	// Req. access to shared cache line
  {CNTR2|CNTR1,0,0,{{0x212e,0x212e,0x0,0x0}},""},	// Req. access to clean cache line
  {CNTR2|CNTR1,0,0,{{0x2069,0x2069,0x0,0x0}},""},	// Req. Cache Line Invalidation
  {CNTR2|CNTR1,0,0,{{0x2e2e,0x2e2e,0x0,0x0}},""},	// Req. Cache Line Intervention
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3 LDM
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3 STM
  {0,0,0,{{0,0,0x0,0x0}},""},			// cycles branch idle
  {0,0,0,{{0,0,0x0,0x0}},""},			// cycles int idle
  {0,0,0,{{0,0,0x0,0x0}},""},			// cycles fpu idle
  {0,0,0,{{0,0,0x0,0x0}},""},			// cycles load/store idle
  {0,0,0,{{0,0,0x0,0x0}},""},		 	// D-TLB misses
  {CNTR2|CNTR1,0,0,{{0x85,0x85,0x0,0x0}},""},	// I-TLB misses
  {0,0,0,{{0,0,0x0,0x0}},""},			// Total TLB misses
  {CNTR2|CNTR1,0,0,{{0xf29,0xf29,0x0,0x0}},""},	// L1 load M
  {CNTR2|CNTR1,0,0,{{0xf2A,0xf2A,0x0,0x0}},""},	// L1 store M
  {0,0,0,{{0,0,0x0,0x0}},""},			// L2 load M
  {0,0,0,{{0,0,0x0,0x0}},""},			// L2 store M
  {CNTR2|CNTR1,0,0,{{0xe2,0xe2,0x0,0x0}},""},	// BTAC misses
  {0,0,0,{{0,0,0x0,0x0}},""},	                // Prefmiss
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3DCH
  {0,0,0,{{0,0,0x0,0x0}},""},			// TLB shootdowns
  {0,0,0,{{0,0,0x0,0x0}},""},			// Failed Store cond.
  {0,0,0,{{0,0,0x0,0x0}},""},			// Suc. store cond.
  {0,0,0,{{0,0,0x0,0x0}},""},			// total. store cond.
  {0,0,0,{{0,0,0x0,0x0}},""},	                // Cycles stalled waiting for memory /
  {0,0,0,{{0,0,0x0,0x0}},""},		   	// Cycles stalled waiting for memory read /
  {0,0,0,{{0,0,0x0,0x0}},""},		   	// Cycles stalled waiting for memory write /
  {0,0,0,{{0,0,0x0,0x0}},""},			// Cycles no instructions issued /
  {0,0,0,{{0,0,0x0,0x0}},""},			// Cycles max instructions issued /
  {0,0,0,{{0,0,0x0,0x0}},""},			// Cycles no instructions comleted /
  {0,0,0,{{0,0,0x0,0x0}},""},			// Cycles max instructions completed /
  {CNTR2|CNTR1,0,0,{{0xC8,0xC8,0x0,0x0}},""},	// hardware interrupts
  {0,0,0,{{0,0,0x0,0x0}},""},	                // Uncond. branches executed
  {CNTR2|CNTR1,0,0,{{0xC4,0xC4,0x0,0x0}},""},	// Cond. Branch inst. executed
  {CNTR2|CNTR1,0,0,{{0xC9,0xC9,0x0,0x0}},""},	// Cond. Branch inst. taken
  {CNTR2|CNTR1,DERIVED_SUB,0,{{0xC4,0xC9,0x0,0x0}},""}, // Cond. Branch inst. not taken
  {CNTR2|CNTR1,0,0,{{0xC5,0xC5,0x0,0x0}},""},	// Cond. branch inst. mispred.
  {CNTR2|CNTR1,DERIVED_SUB,0,{{0xC4,0xC5,0x0,0x0}},""}, // Cond. branch inst. corr. pred.
  {0,0,0,{{0,0,0x0,0x0}},""},			// FMA
  {CNTR2|CNTR1,0,0,{{0xD0,0xD0,0x0,0x0}},""},	// Total inst. issued
  {CNTR2|CNTR1,0,0,{{0xC0,0xC0,0x0,0x0}},""},	// Total inst. executed
  {0,0,0,{{0,0,0x0,0x0}},""},			// Integer inst. executed
  {CNTR1,0,0,{{0xC1,0,0x0,0x0}},""},		// Floating Pt. inst. executed
  {0,0,0,{{0,0,0x0,0x0}},""},			// Loads executed
  {0,0,0,{{0,0,0x0,0x0}},""},			// Stores executed
  {CNTR2|CNTR1,0,0,{{0xC4,0xC4,0x0,0x0}},""},	// Branch inst. executed
  {CNTR2|CNTR1,0,0,{{0xB0,0xB0,0x0,0x0}},""},	// Vector/SIMD inst. executed 
  {CNTR2|CNTR1,DERIVED_PS,1,{{0xC1,0x79,0x0,0x0}},""}, // FLOPS
  {CNTR2|CNTR1,0,0,{{0xA2,0xA2,0x0,0x0}},""},	// Cycles any resource stalls
  {0,0,0,{{0,0,0x0,0x0}},""},			// Cycles FPU stalled
  {CNTR2|CNTR1,0,0,{{0x79,0x79,0x0,0x0}},""},	// Total cycles
  {CNTR2|CNTR1,DERIVED_PS,1,{{0xC0,0x79,0x0,0x0}},""}, // IPS
  {0,0,0,{{0,0,0,0}},""},			// Total load/store inst. exec
  {0,0,0,{{0,0,0x0,0x0}},""},			// SYnc exec.
  {CNTR2|CNTR1,DERIVED_SUB,0,{{0x43,0x45,0x0,0x0}},""}, // L1_DCH
  {CNTR2|CNTR1,DERIVED_SUB,0,{{0xf2e,0xf24,0x0,0x0}},""}, // L2_DCH
  {CNTR2|CNTR1,0,0,{{0x43,0x43,0x0,0x0}},""},	// L1_DCA
  {CNTR2|CNTR1,DERIVED_ADD,0,{{0xf29,0xf2a,0x0,0x0}},""}, // L2_DCA
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3_DCA
  {0,0,0,{{0,0,0x0,0x0}},""},			// L1_DCR
  {CNTR2|CNTR1,0,0,{{0xf29,0xf29,0x0,0x0}},""},	// L2_DCR
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3_DCR
  {0,0,0,{{0,0,0x0,0x0}},""},			// L1_DCW
  {CNTR2|CNTR1,0,0,{{0xf2a,0xf2a,0x0,0x0}},""},	// L2_DCW
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3_DCW
  {CNTR2|CNTR1,DERIVED_SUB,0,{{0x80,0x81,0x0,0x0}},""}, // L1_ICH
  {0,0,0,{{0,0,0x0,0x0}},""},			// L2_ICH
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3_ICH
  {CNTR2|CNTR1,0,0,{{0x80,0x80,0x0,0x0}},""},	// L1_ICA
  {CNTR2|CNTR1,0,0,{{0xf28,0xf28,0x0,0x0}},""},	// L2_ICA
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3_ICA
  {CNTR2|CNTR1,0,0,{{0x80,0x80,0x0,0x0}},""},	// L1_ICR
  {CNTR2|CNTR1,0,0,{{0xf28,0xf28,0x0,0x0}},""},	// L2_ICR
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3_ICR
  {CNTR2|CNTR1,0,0,{{0x81,0x81,0x0,0x0}},""},	// L1_ICW
  {0,0,0,{{0,0,0x0,0x0}},""},			// L2_ICW
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3_ICW
  {0,0,0,{{0,0,0x0,0x0}},""},			// L1_TCH
  {0,0,0,{{0,0,0x0,0x0}},""},			// L2_TCH
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3_TCH
  {CNTR2|CNTR1,DERIVED_ADD,0,{{0x43,0x80,0x0,0x0}},""},	// L1_TCA
  {CNTR2|CNTR1,0,0,{{0xf2e,0xf2e,0x0,0x0}},""},	// L2_TCA
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3_TCA<commit_msg>Modification of instruction cache related events on the linux-perfctr Pentium Pro/II/III platform. These were mixed up slightly in that you got more L2 instruction fetches than L1 instruction misses. linux-perf and Windows substrates not checked for the same (possible) mix-up.<commit_after>#ifdef PERFCTR20
#define PERFCTR18
#endif
/* This substrate should never malloc anything. All allocation should be
   done by the high level API. */

/* The values defined in this file may be X86-specific (2 general 
   purpose counters, 1 special purpose counter, etc.*/

/* PAPI stuff */

#include SUBSTRATE

/* First entry is mask, counter code 1, counter code 2, and TSC. 
A high bit in the mask entry means it is an OR mask, not an
and mask. This means that the same even is available on either
counter. */

static hwd_preset_t *preset_map;
static hwd_preset_t p6_preset_map[PAPI_MAX_PRESET_EVENTS] = { 
  {CNTR2|CNTR1,0,0,{{0x45,0x45,0x0,0x0}},""},	// L1 Cache Dmisses 
  {CNTR2|CNTR1,0,0,{{0xf28,0xf28,0x0,0x0}},""},	// L1 Cache Imisses 
  {0,0,0,{{0,0,0x0,0x0}},""}, 			// L2 Cache Dmisses
  {CNTR2|CNTR1,0,0,{{0x81,0x81,0x0,0x0}},""},	// L2 Cache Imisses 
  {0,0,0,{{0,0,0x0,0x0}},""}, 			// L3 Cache Dmisses
  {0,0,0,{{0,0,0x0,0x0}},""}, 			// L3 Cache Imisses
  {CNTR2|CNTR1,0,0,{{0xf2e,0xf2e,0x0,0x0}},""},	// L1 Total Cache misses 
  {CNTR2|CNTR1,0,0,{{0x24,0x24,0x0,0x0}},""}, 	// L2 Total Cache misses
  {0,0,0,{{0,0,0x0,0x0}},""}, 			// L3 Total Cache misses
  {0,0,0,{{0,0,0x0,0x0}},""},			// Snoops
  {CNTR2|CNTR1,0,0,{{0x222e,0x222e,0x0,0x0}},""},	// Req. access to shared cache line
  {CNTR2|CNTR1,0,0,{{0x212e,0x212e,0x0,0x0}},""},	// Req. access to clean cache line
  {CNTR2|CNTR1,0,0,{{0x2069,0x2069,0x0,0x0}},""},	// Req. Cache Line Invalidation
  {CNTR2|CNTR1,0,0,{{0x2e2e,0x2e2e,0x0,0x0}},""},	// Req. Cache Line Intervention
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3 LDM
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3 STM
  {0,0,0,{{0,0,0x0,0x0}},""},			// cycles branch idle
  {0,0,0,{{0,0,0x0,0x0}},""},			// cycles int idle
  {0,0,0,{{0,0,0x0,0x0}},""},			// cycles fpu idle
  {0,0,0,{{0,0,0x0,0x0}},""},			// cycles load/store idle
  {0,0,0,{{0,0,0x0,0x0}},""},		 	// D-TLB misses
  {CNTR2|CNTR1,0,0,{{0x85,0x85,0x0,0x0}},""},	// I-TLB misses
  {0,0,0,{{0,0,0x0,0x0}},""},			// Total TLB misses
  {CNTR2|CNTR1,0,0,{{0xf29,0xf29,0x0,0x0}},""},	// L1 load M
  {CNTR2|CNTR1,0,0,{{0xf2A,0xf2A,0x0,0x0}},""},	// L1 store M
  {0,0,0,{{0,0,0x0,0x0}},""},			// L2 load M
  {0,0,0,{{0,0,0x0,0x0}},""},			// L2 store M
  {CNTR2|CNTR1,0,0,{{0xe2,0xe2,0x0,0x0}},""},	// BTAC misses
  {0,0,0,{{0,0,0x0,0x0}},""},	                // Prefmiss
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3DCH
  {0,0,0,{{0,0,0x0,0x0}},""},			// TLB shootdowns
  {0,0,0,{{0,0,0x0,0x0}},""},			// Failed Store cond.
  {0,0,0,{{0,0,0x0,0x0}},""},			// Suc. store cond.
  {0,0,0,{{0,0,0x0,0x0}},""},			// total. store cond.
  {0,0,0,{{0,0,0x0,0x0}},""},	                // Cycles stalled waiting for memory /
  {0,0,0,{{0,0,0x0,0x0}},""},		   	// Cycles stalled waiting for memory read /
  {0,0,0,{{0,0,0x0,0x0}},""},		   	// Cycles stalled waiting for memory write /
  {0,0,0,{{0,0,0x0,0x0}},""},			// Cycles no instructions issued /
  {0,0,0,{{0,0,0x0,0x0}},""},			// Cycles max instructions issued /
  {0,0,0,{{0,0,0x0,0x0}},""},			// Cycles no instructions comleted /
  {0,0,0,{{0,0,0x0,0x0}},""},			// Cycles max instructions completed /
  {CNTR2|CNTR1,0,0,{{0xC8,0xC8,0x0,0x0}},""},	// hardware interrupts
  {0,0,0,{{0,0,0x0,0x0}},""},	                // Uncond. branches executed
  {CNTR2|CNTR1,0,0,{{0xC4,0xC4,0x0,0x0}},""},	// Cond. Branch inst. executed
  {CNTR2|CNTR1,0,0,{{0xC9,0xC9,0x0,0x0}},""},	// Cond. Branch inst. taken
  {CNTR2|CNTR1,DERIVED_SUB,0,{{0xC4,0xC9,0x0,0x0}},""}, // Cond. Branch inst. not taken
  {CNTR2|CNTR1,0,0,{{0xC5,0xC5,0x0,0x0}},""},	// Cond. branch inst. mispred.
  {CNTR2|CNTR1,DERIVED_SUB,0,{{0xC4,0xC5,0x0,0x0}},""}, // Cond. branch inst. corr. pred.
  {0,0,0,{{0,0,0x0,0x0}},""},			// FMA
  {CNTR2|CNTR1,0,0,{{0xD0,0xD0,0x0,0x0}},""},	// Total inst. issued
  {CNTR2|CNTR1,0,0,{{0xC0,0xC0,0x0,0x0}},""},	// Total inst. executed
  {0,0,0,{{0,0,0x0,0x0}},""},			// Integer inst. executed
  {CNTR1,0,0,{{0xC1,0,0x0,0x0}},""},		// Floating Pt. inst. executed
  {0,0,0,{{0,0,0x0,0x0}},""},			// Loads executed
  {0,0,0,{{0,0,0x0,0x0}},""},			// Stores executed
  {CNTR2|CNTR1,0,0,{{0xC4,0xC4,0x0,0x0}},""},	// Branch inst. executed
  {CNTR2|CNTR1,0,0,{{0xB0,0xB0,0x0,0x0}},""},	// Vector/SIMD inst. executed 
  {CNTR2|CNTR1,DERIVED_PS,1,{{0xC1,0x79,0x0,0x0}},""}, // FLOPS
  {CNTR2|CNTR1,0,0,{{0xA2,0xA2,0x0,0x0}},""},	// Cycles any resource stalls
  {0,0,0,{{0,0,0x0,0x0}},""},			// Cycles FPU stalled
  {CNTR2|CNTR1,0,0,{{0x79,0x79,0x0,0x0}},""},	// Total cycles
  {CNTR2|CNTR1,DERIVED_PS,1,{{0xC0,0x79,0x0,0x0}},""}, // IPS
  {0,0,0,{{0,0,0,0}},""},			// Total load/store inst. exec
  {0,0,0,{{0,0,0x0,0x0}},""},			// SYnc exec.
  {CNTR2|CNTR1,DERIVED_SUB,0,{{0x43,0x45,0x0,0x0}},""}, // L1_DCH
  {0,0,0,{{0,0,0x0,0x0}},""},			// L2_DCH
  {CNTR2|CNTR1,0,0,{{0x43,0x43,0x0,0x0}},""},	// L1_DCA
  {CNTR2|CNTR1,DERIVED_ADD,0,{{0xf29,0xf2a,0x0,0x0}},""}, // L2_DCA
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3_DCA
  {0,0,0,{{0,0,0x0,0x0}},""},			// L1_DCR
  {CNTR2|CNTR1,0,0,{{0xf29,0xf29,0x0,0x0}},""},	// L2_DCR
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3_DCR
  {0,0,0,{{0,0,0x0,0x0}},""},			// L1_DCW
  {CNTR2|CNTR1,0,0,{{0xf2a,0xf2a,0x0,0x0}},""},	// L2_DCW
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3_DCW
  {CNTR2|CNTR1,DERIVED_SUB,0,{{0x80,0xf28,0x0,0x0}},""}, // L1_ICH
  {CNTR2|CNTR1,DERIVED_SUB,0,{{0xf28,0x81,0x0,0x0}},""}, // L2_ICH
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3_ICH
  {CNTR2|CNTR1,0,0,{{0x80,0x80,0x0,0x0}},""},	// L1_ICA
  {CNTR2|CNTR1,0,0,{{0xf28,0xf28,0x0,0x0}},""},	// L2_ICA
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3_ICA
  {CNTR2|CNTR1,0,0,{{0x80,0x80,0x0,0x0}},""},	// L1_ICR
  {CNTR2|CNTR1,0,0,{{0xf28,0xf28,0x0,0x0}},""},	// L2_ICR
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3_ICR
  {0,0,0,{{0,0,0x0,0x0}},""},			// L1_ICW
  {0,0,0,{{0,0,0x0,0x0}},""},			// L2_ICW
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3_ICW
  {0,0,0,{{0,0,0x0,0x0}},""},			// L1_TCH
  {CNTR2|CNTR1,DERIVED_SUB,0,{{0xf2e,0x24,0x0,0x0}},""}, // L2_TCH
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3_TCH
  {CNTR2|CNTR1,DERIVED_ADD,0,{{0x43,0x80,0x0,0x0}},""},	// L1_TCA
  {CNTR2|CNTR1,0,0,{{0xf2e,0xf2e,0x0,0x0}},""},	// L2_TCA
  {0,0,0,{{0,0,0x0,0x0}},""},			// L3_TCA
{'fraction_non_alphanumeric': 0.287842574888464, 'fraction_numerical': 0.168578712555768, 'mean_word_length': 4.4412657130472475, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 3, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '4968998', 'n_tokens_mistral': 7530, 'n_tokens_neox': 7246, 'n_words': 864}