<commit_before>


function! asmhelp#load()
    if !exists("g:asm_mini_docu")
        let g:asm_mini_docu = {
                    \ 'mov'	: 'Copies the value of the second operand into the first operand (destination register)',
                    \ 'movt'	: 'Writes a 16 bit immediate value (second operand) to the top halfword of its desitation register',
                    \ 'bfc'     : 'Bit Field Clear | BFC Rd, #<lsb>, #<width>  | Rd[(width+lsb–1):lsb] := 0, other bits of Rd unaffected',
		    \ 'bfi'	: 'Bit Field Insert | BFI Rd, Rn, #<lsb>, #<width> Rd[(width+lsb–1):lsb] := Rn[(width-1):0], other bits of Rd unaffected',
		    \ 'sbfx'	: 'Signed Bit Field Extract | SBFX Rd, Rn, #<lsb>, #<width> Rd[(width–1):0] = Rn[(width+lsb–1):lsb], Rd[31:width] = Replicate( Rn[width+lsb–1] )',
		    \ 'ubfx'	: 'Unsigned Bit Field Extract | UBFX Rd, Rn, #<lsb>, #<width> Rd[(width–1):0] = Rn[(width+lsb–1):lsb], Rd[31:width] = Replicate( 0 )',
		    \ 'cmp'	: 'Compare CMP{cond} Rn, <Operand2> | N Z C V Update CPSR flags on Rn – Operand2',
		    \ 'cmn'	: 'Compare negative CMN{cond} | Rn, <Operand2> N Z C V Update CPSR flags on Rn + Operand2',
		    \ 'tst'	: 'Test TST{cond} Rn, <Operand2> N Z C Update CPSR flags on Rn AND Operand2',
		    \ 'teq'	: 'Test equivalence TEQ{cond} Rn, <Operand2> N Z C Update CPSR flags on Rn EOR Operand2',
		    \ 'and'	: 'AND AND{cond}{S} Rd, Rn, <Operand2> N Z C Rd := Rn AND Operand2',
		    \ 'eor'	: 'EOR EOR{cond}{S} Rd, Rn, <Operand2> N Z C Rd := Rn EOR Operand2',
		    \ 'orr'	: 'ORR ORR{cond}{S} Rd, Rn, <Operand2> N Z C Rd := Rn OR Operand2',
		    \ 'bic'	: 'Bit Clear BIC{cond}{S} Rd, Rn, <Operand2> N Z C Rd := Rn AND NOT Operand2'
                    \ }
    endif
endfunction
<commit_msg>Modified the mini help<commit_after>


function! asmhelp#load()
    if !exists("g:asm_mini_docu")
        let g:asm_mini_docu = {
                    \ 'adc'	: 'Add with carry',
                    \ 'add'     : 'Add',
                    \ 'b'       : 'Branch',
                    \ 'bic'     : 'Bit clear',
                    \ 'bl'      : 'Branch with link'
                    \ 'bx'      : 'Branch and exchange'
                    \ 'cdp'     ; 'Coprocessor data processing'
                    \ 'cmn'     : 'Compare negative'
                    \ 'cmp'     : 'Compare'
                    \ 'eor'     : 'Exclusive OR'
                    \ 'ldc'     : 'Load coprocessor from memory'
                    \ 'ldm'     : 'Load multiple registers'
                    \ 'ldr'     : 'Load register from memory'
                    \ 'mcr'     : 'Move CPU register to coprocessor register'
                    \ 'mla'     : 'Multiply accumlate'
                    \ 'mov'     : 'Move register or constant'
                    \ 'mrc'     : 'Move from coprocessor register to cpu register'
                    \ 'mrs'     : 'Move PSR status/flags to register'
                    \ 'msr'     : 'Move register to PSR status/flags'
                    \ 'mul'     : 'Multiply'
                    \ 'mvn'     : 'Move negative number'
                    \ 'orr'     : 'OR'
                    \ 'rsb'     : 'Reverse subtract'
                    \ 'rsc'     : 'Reverse subtract with carry'
                    \ 'sbc'     : 'Subtract with carry'
                    \ 'stc'     : 'Store coprocessor register to memory'
                    \ 'stm'     : 'Store multiple'
                    \ 'str'     : 'Store register to memory'
                    \ 'sub'     : 'Subtract'
                    \ 'swi'     : 'Software interrup'
                    \ 'swp'     : 'Swap register with memory'
                    \ 'teq'     : 'Test bitwise equality'
                    \ 'tst'     : 'Test bits'
                    \ }
    endif
endfunction

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