<commit_before>#=======================================================================
# vcd.py
#=======================================================================
# VCD generation support for SimulationTool. VCD file format standard
# can be found here:
#
# - http://support.ema-eda.com/search/eslfiles/default/main/sl_legacy_releaseinfo/staging/sl3/release_info/psd142/vlogref/chap20.html#1031979
# - http://staff.ustc.edu.cn/~songch/download/IEEE.1364-2005.pdf
#
# TODO:
#
# - distinguish reg signals from wire signals (maybe)

from __future__ import print_function

import time
import sys

#-----------------------------------------------------------------------
# get_vcd_timescale
#-----------------------------------------------------------------------
DEFAULT_TIMESCALE = '10ps'
def get_vcd_timescale( model ):
  try:
    return model.vcd_timescale
  except AttributeError:
    return DEFAULT_TIMESCALE

#-----------------------------------------------------------------------
# write_vcd_header
#-----------------------------------------------------------------------
def write_vcd_header( o, model ):

  def dedent( lines, trim=4 ):
    return ''.join( [x[trim:]+'\n' for x in lines.split('\n')] ).lstrip()

  print( dedent("""
    $date
        {time}
    $end
    $version
        PyMTL ?.??
    $end
    $timescale
        {vcd_timescale}
    $end"""
    ).format(
      time          = time.asctime(),
      vcd_timescale = get_vcd_timescale( model ),
    ),
  file=o )

#-----------------------------------------------------------------------
# mangle_name
#-----------------------------------------------------------------------
# Mangle signal names so that lists of signals/models show up correctly.
def mangle_name( name ):
  return name.replace('[','(').replace(']',')')

#-----------------------------------------------------------------------
# write_vcd_signal_defs
#-----------------------------------------------------------------------
def write_vcd_signal_defs( o, model ):

  vcd_symbol = _gen_vcd_symbol()
  all_nets   = set()

  # Inner utility function to perform recursive descent of the model.
  def recurse_models( model, level ):

    # Create a new scope for this module
    print( "$scope module {name} $end".format( name=model.name ), file=o )

    # Define all signals for this model.
    for i in model.get_ports() + model.get_wires():

      # Multiple signals may be collapsed into a single net in the
      # simulator if they are connected. Generate new vcd symbols per
      # net, not per signal as an optimization.
      net = i._signalvalue
      if not hasattr( net, '_vcd_symbol' ):
        net._vcd_symbol = vcd_symbol.next()
        net._vcd_is_clk = i.name == 'clk'
      symbol = net._vcd_symbol

      print( "$var {type} {nbits} {symbol} {name} $end".format(
          type='reg', nbits=i.nbits, symbol=symbol, name=mangle_name(i.name),
      ), file=o )

      all_nets.add( net )

    # Recursively visit all submodels.
    for submodel in model.get_submodules():
      recurse_models( submodel, level+1 )

    print( "$upscope $end", file=o )<commit_msg>fix broken VCD generator<commit_after>#=======================================================================
# vcd.py
#=======================================================================
# VCD generation support for SimulationTool. VCD file format standard
# can be found here:
#
# - http://support.ema-eda.com/search/eslfiles/default/main/sl_legacy_releaseinfo/staging/sl3/release_info/psd142/vlogref/chap20.html#1031979
# - http://staff.ustc.edu.cn/~songch/download/IEEE.1364-2005.pdf
#
# TODO:
#
# - distinguish reg signals from wire signals (maybe)

from __future__ import print_function

import time
import sys

#-----------------------------------------------------------------------
# get_vcd_timescale
#-----------------------------------------------------------------------
DEFAULT_TIMESCALE = '10ps'
def get_vcd_timescale( model ):
  try:
    return model.vcd_timescale
  except AttributeError:
    return DEFAULT_TIMESCALE

#-----------------------------------------------------------------------
# write_vcd_header
#-----------------------------------------------------------------------
def write_vcd_header( o, model ):

  def dedent( lines, trim=4 ):
    return ''.join( [x[trim:]+'\n' for x in lines.split('\n')] ).lstrip()

  print( dedent("""
    $date
        {time}
    $end
    $version
        PyMTL ?.??
    $end
    $timescale
        {vcd_timescale}
    $end"""
    ).format(
      time          = time.asctime(),
      vcd_timescale = get_vcd_timescale( model ),
    ),
  file=o )

#-----------------------------------------------------------------------
# mangle_name
#-----------------------------------------------------------------------
# Mangle signal names so that lists of signals/models show up correctly.
def mangle_name( name ):
  return name.replace('[','(').replace(']',')')

#-----------------------------------------------------------------------
# write_vcd_signal_defs
#-----------------------------------------------------------------------
def write_vcd_signal_defs( o, model ):

  vcd_symbol = _gen_vcd_symbol()
  all_nets   = []

  # Inner utility function to perform recursive descent of the model.
  def recurse_models( model, level ):

    # Create a new scope for this module
    print( "$scope module {name} $end".format( name=model.name ), file=o )

    # Define all signals for this model.
    for i in model.get_ports() + model.get_wires():

      # Multiple signals may be collapsed into a single net in the
      # simulator if they are connected. Generate new vcd symbols per
      # net, not per signal as an optimization.
      net = i._signalvalue
      if not hasattr( net, '_vcd_symbol' ):
        net._vcd_symbol = vcd_symbol.next()
        net._vcd_is_clk = i.name == 'clk'
        all_nets.append( net )
      symbol = net._vcd_symbol

      print( "$var {type} {nbits} {symbol} {name} $end".format(
          type='reg', nbits=i.nbits, symbol=symbol, name=mangle_name(i.name),
      ), file=o )

    # Recursively visit all submodels.
    for submodel in model.get_submodules():
      recurse_models( submodel, level+1 )

    print( "$upscope $end", file=o )
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