<commit_before>/**
 * \file
 * \brief Intel e1000 driver: Initialize the hardware
 *
 *
 */

/*
 * Copyright (c) 2007, 2008, 2009, 2010, ETH Zurich.
 * All rights reserved.
 *
 * This file is distributed under the terms in the attached LICENSE file.
 * If you do not find this file, copies can be found by writing to:
 * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
 */



#include <barrelfish/barrelfish.h>
#include <string.h>
// Following two are needed for call "sys_debug_feign_frame_cap"
#define  ENABLE_FEIGN_FRAME_CAP
#include <barrelfish/sys_debug.h>
#include <barrelfish/inthandler.h>
#include <ethersrv/ethersrv.h>
#include <trace/trace.h>


#include "eMAC_dev.h"
#include "eMAC_driver.h"

#include "eMAC_debug.h"

/* Enable tracing based on the global settings. */
#if CONFIG_TRACE && NETWORK_STACK_TRACE
#define TRACE_ETHERSRV_MODE 1
#endif // CONFIG_TRACE && NETWORK_STACK_TRACE


#define MIN(a, b) (((a) < (b)) ? (a) : (b))

static eMAC_t emac;

#define EMAC_CFG_REGS_BASE         (0xF9000000)
#define EMAC_CFG_REGS_SIZE         (0x10000)

#define EMAC_IRQ_CONFIG 1       /// Pin on core to use (1 == LINT1)
/*
#define EMAC0_IRQ       0x1     /// IRQ of eMAC #2
#define EMAC1_IRQ       0x2     /// IRQ of eMAC #2
#define EMAC2_IRQ       0x4     /// IRQ of eMAC #2
#define EMAC3_IRQ       0x8     /// IRQ of eMAC #2
*/

#define CSIZE           (32)
#define SLOTS           (1 << 16)
#define BUFF_SIZE       (SLOTS * CSIZE)
#define TX_MAX_PKT_SIZE 1536


static struct capref RX_capframe;
static void *RX_internal_memory_pa = NULL;
static void *RX_internal_memory_va = NULL;
static uint32_t volatile RX_read_index = 0;
static uint32_t RX_max_slots = SLOTS - 1;

static struct capref TX_capframe;
static void *TX_internal_memory_pa = NULL;
static void *TX_internal_memory_va = NULL;
static uint32_t volatile TX_write_index = 0;
static uint32_t TX_max_slots = SLOTS - 1;


// For measurement of interrupts
extern uint64_t interrupt_counter;
extern uint64_t interrupt_loop_counter;

/* MAC address */
extern uint64_t eMAC_mac;

/* set at hwinit */
static uint8_t eMAC_PHY_id = 0; /* Which emac PHY you are using? */
//static interrupt_handler_fn high_level_handler = NULL;


/* FIXME: allocate following buffer with malloc (or get it from user apps) */

#define MAX_FRAME_SIZE  1600
static uint8_t dummy_pkt[MAX_FRAME_SIZE];

/* FIXME: remove these */
static volatile uint8_t *rb_RX = NULL;
static volatile uint8_t *rb_TX = NULL;
static volatile uint16_t *rb_TX_header = NULL;
static volatile uint16_t *rb_RX_header = NULL;


static unsigned long long rx_tile_offset = 0;
static int rx_pos = 0;
static int rx_mode = 0;

static uint8_t core_id = 0;
//static uint8_t core_id = 0;
static uint64_t call_counter = 0;
static uint64_t pkt_counter = 0;

static size_t get_cachelines(uint64_t data_size)
{
    size_t cachelines = (data_size)/ CSIZE;
    if (((data_size)%CSIZE) > 0) {
        ++cachelines;
    }
    return cachelines;
}

/*
static void print_cline(uint8_t *cline)
{
    EMAC_DEBUG("Cacheline [");
    for(int j = 0; j < 32; ++j) {
        printf("%x,", cline[j]);
    }
    printf("]\n");
}
*/
/*
static void increment_TX_write_index(void)
{
    ++TX_write_index;
    if (TX_write_index > TX_max_slots ) {
        TX_write_index = 1;
    }
} // end function: increment_TX_write_index
*/

static void increment_RX_read_index(void)
{
    ++RX_read_index;
    if (RX_read_index > RX_max_slots || RX_read_index == 0) {
        RX_read_index = 1;
    }
} /* end function: increment_read_index */

/*
static void my_memcpy(uint8_t *dst, uint8_t *src, size_t len)
{
    for(int i = 0; i < len; ++i){
        dst[i] = src[i];
    }
}
*/

static void show_packet(uint8_t *pkt, size_t len)
{
/*
    printf("\n[");
    for(int i = 0; i < len; ++i) {
        if(i % 16 == 0){
            printf("\n%04x", i);
        }
        printf(" %02x", pkt[i]);
    }
    printf("\n] = %u\n", len);
*/
} /* end function: show_packet */

static void receive_frame_data(void)
{
    /* 9.6.5.4 Receiving Frame Data */
    /*
        1. Check for updated write index in head of buffer
                (or FPGA register) (RX buffer+0x00)
            a. Read 4 bytes from RX buffer at address 0 and compare
                the write index value to the internal read index value stored
                in the driver
    */

    eMAC_RX_Buffer_read_index_t idx_r;
    eMAC_RX_Buffer_write_index_t idx_w;
    /*
    uint16_t rid;
    uint16_t wid;
*/

    cl1flushmb();
    uint16_t volatile wid = 0;
    uint8_t volatile *buf = (uint8_t *) RX_internal_memory_va;
    void *pkt_to_upload = NULL;
    ++call_counter;

    uint16_t volatile wid1 = 0;
    uint16_t volatile rid1 = 0;
    idx_r = eMAC_eMAC2_RX_Buffer_read_index_rd(&emac, core_id);
    idx_w = eMAC_eMAC2_RX_Buffer_write_index_rd(&emac, core_id);
    rid1 = idx_r.rid;
    wid1 = idx_w.wid;

    if (rid1 != wid1 ){
        EMAC_DEBUG("######## we have a packet! rid [%"PRIx16"] wid[%"PRIx16"]\n",
                rid1, wid1);
        EMAC_DEBUG("old values %"PRIx32", %"PRIx16", %"PRIx16"\n",
                RX_read_index, rb_RX_header[0], rb_RX_header[1]);
//        abort();
    }

    wid = rb_RX_header[0];
    wid = wid1;
    RX_read_index = rid1;
    if (RX_read_index == wid) {
        return;
    }


    assert( wid <= RX_max_slots);

/*    EMAC_DEBUG("%" PRIx64 ": new pkt [rid1 (%u) (%u) == wid1(%u) (%u)]\n",
            call_counter, rid1, rb_RX_header[1],  wid1, rb_RX_header[0]);
*/
    EMAC_DEBUG("MOVEMENT: %" PRIx64 " [rid (%x) != wid (%x)]\n",
            call_counter, RX_read_index,  wid);

    do {
        ++interrupt_loop_counter;
        increment_RX_read_index();

        uint16_t frame_len = 0;
        uint16_t *frame_len_ptr;
        uint32_t copied = 0;

        uint8_t *pkt_ptr = (uint8_t *)(buf + (RX_read_index * 32));
//        show_packet(pkt_ptr, 90);<commit_msg>Minor fix: non-existent variable was linked in eMAC driver<commit_after>/**
 * \file
 * \brief Intel e1000 driver: Initialize the hardware
 *
 *
 */

/*
 * Copyright (c) 2007, 2008, 2009, 2010, ETH Zurich.
 * All rights reserved.
 *
 * This file is distributed under the terms in the attached LICENSE file.
 * If you do not find this file, copies can be found by writing to:
 * ETH Zurich D-INFK, Haldeneggsteig 4, CH-8092 Zurich. Attn: Systems Group.
 */



#include <barrelfish/barrelfish.h>
#include <string.h>
// Following two are needed for call "sys_debug_feign_frame_cap"
#define  ENABLE_FEIGN_FRAME_CAP
#include <barrelfish/sys_debug.h>
#include <barrelfish/inthandler.h>
#include <ethersrv/ethersrv.h>
#include <trace/trace.h>


#include "eMAC_dev.h"
#include "eMAC_driver.h"

#include "eMAC_debug.h"

/* Enable tracing based on the global settings. */
#if CONFIG_TRACE && NETWORK_STACK_TRACE
#define TRACE_ETHERSRV_MODE 1
#endif // CONFIG_TRACE && NETWORK_STACK_TRACE


#define MIN(a, b) (((a) < (b)) ? (a) : (b))

static eMAC_t emac;

#define EMAC_CFG_REGS_BASE         (0xF9000000)
#define EMAC_CFG_REGS_SIZE         (0x10000)

#define EMAC_IRQ_CONFIG 1       /// Pin on core to use (1 == LINT1)
/*
#define EMAC0_IRQ       0x1     /// IRQ of eMAC #2
#define EMAC1_IRQ       0x2     /// IRQ of eMAC #2
#define EMAC2_IRQ       0x4     /// IRQ of eMAC #2
#define EMAC3_IRQ       0x8     /// IRQ of eMAC #2
*/

#define CSIZE           (32)
#define SLOTS           (1 << 16)
#define BUFF_SIZE       (SLOTS * CSIZE)
#define TX_MAX_PKT_SIZE 1536


static struct capref RX_capframe;
static void *RX_internal_memory_pa = NULL;
static void *RX_internal_memory_va = NULL;
static uint32_t volatile RX_read_index = 0;
static uint32_t RX_max_slots = SLOTS - 1;

static struct capref TX_capframe;
static void *TX_internal_memory_pa = NULL;
static void *TX_internal_memory_va = NULL;
static uint32_t volatile TX_write_index = 0;
static uint32_t TX_max_slots = SLOTS - 1;


// For measurement of interrupts
extern uint64_t interrupt_counter;

/* MAC address */
extern uint64_t eMAC_mac;

/* set at hwinit */
static uint8_t eMAC_PHY_id = 0; /* Which emac PHY you are using? */
//static interrupt_handler_fn high_level_handler = NULL;


/* FIXME: allocate following buffer with malloc (or get it from user apps) */

#define MAX_FRAME_SIZE  1600
static uint8_t dummy_pkt[MAX_FRAME_SIZE];

/* FIXME: remove these */
static volatile uint8_t *rb_RX = NULL;
static volatile uint8_t *rb_TX = NULL;
static volatile uint16_t *rb_TX_header = NULL;
static volatile uint16_t *rb_RX_header = NULL;


static unsigned long long rx_tile_offset = 0;
static int rx_pos = 0;
static int rx_mode = 0;

static uint8_t core_id = 0;
//static uint8_t core_id = 0;
static uint64_t call_counter = 0;
static uint64_t pkt_counter = 0;

static size_t get_cachelines(uint64_t data_size)
{
    size_t cachelines = (data_size)/ CSIZE;
    if (((data_size)%CSIZE) > 0) {
        ++cachelines;
    }
    return cachelines;
}

/*
static void print_cline(uint8_t *cline)
{
    EMAC_DEBUG("Cacheline [");
    for(int j = 0; j < 32; ++j) {
        printf("%x,", cline[j]);
    }
    printf("]\n");
}
*/
/*
static void increment_TX_write_index(void)
{
    ++TX_write_index;
    if (TX_write_index > TX_max_slots ) {
        TX_write_index = 1;
    }
} // end function: increment_TX_write_index
*/

static void increment_RX_read_index(void)
{
    ++RX_read_index;
    if (RX_read_index > RX_max_slots || RX_read_index == 0) {
        RX_read_index = 1;
    }
} /* end function: increment_read_index */

/*
static void my_memcpy(uint8_t *dst, uint8_t *src, size_t len)
{
    for(int i = 0; i < len; ++i){
        dst[i] = src[i];
    }
}
*/

static void show_packet(uint8_t *pkt, size_t len)
{
/*
    printf("\n[");
    for(int i = 0; i < len; ++i) {
        if(i % 16 == 0){
            printf("\n%04x", i);
        }
        printf(" %02x", pkt[i]);
    }
    printf("\n] = %u\n", len);
*/
} /* end function: show_packet */

static void receive_frame_data(void)
{
    /* 9.6.5.4 Receiving Frame Data */
    /*
        1. Check for updated write index in head of buffer
                (or FPGA register) (RX buffer+0x00)
            a. Read 4 bytes from RX buffer at address 0 and compare
                the write index value to the internal read index value stored
                in the driver
    */

    eMAC_RX_Buffer_read_index_t idx_r;
    eMAC_RX_Buffer_write_index_t idx_w;
    /*
    uint16_t rid;
    uint16_t wid;
*/

    cl1flushmb();
    uint16_t volatile wid = 0;
    uint8_t volatile *buf = (uint8_t *) RX_internal_memory_va;
    void *pkt_to_upload = NULL;
    ++call_counter;

    uint16_t volatile wid1 = 0;
    uint16_t volatile rid1 = 0;
    idx_r = eMAC_eMAC2_RX_Buffer_read_index_rd(&emac, core_id);
    idx_w = eMAC_eMAC2_RX_Buffer_write_index_rd(&emac, core_id);
    rid1 = idx_r.rid;
    wid1 = idx_w.wid;

    if (rid1 != wid1 ){
        EMAC_DEBUG("######## we have a packet! rid [%"PRIx16"] wid[%"PRIx16"]\n",
                rid1, wid1);
        EMAC_DEBUG("old values %"PRIx32", %"PRIx16", %"PRIx16"\n",
                RX_read_index, rb_RX_header[0], rb_RX_header[1]);
//        abort();
    }

    wid = rb_RX_header[0];
    wid = wid1;
    RX_read_index = rid1;
    if (RX_read_index == wid) {
        return;
    }


    assert( wid <= RX_max_slots);

/*    EMAC_DEBUG("%" PRIx64 ": new pkt [rid1 (%u) (%u) == wid1(%u) (%u)]\n",
            call_counter, rid1, rb_RX_header[1],  wid1, rb_RX_header[0]);
*/
    EMAC_DEBUG("MOVEMENT: %" PRIx64 " [rid (%x) != wid (%x)]\n",
            call_counter, RX_read_index,  wid);

    do {
        increment_RX_read_index();

        uint16_t frame_len = 0;
        uint16_t *frame_len_ptr;
        uint32_t copied = 0;

        uint8_t *pkt_ptr = (uint8_t *)(buf + (RX_read_index * 32));
//        show_packet(pkt_ptr, 90);
{'fraction_non_alphanumeric': 0.12134639965913932, 'fraction_numerical': 0.03544951001278227, 'mean_word_length': 2.9515151515151516, 'pattern_counts': {'":': 2, '<': 29, '<?xml version=': 0, '>': 21, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 2, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '4914712', 'n_tokens_mistral': 4654, 'n_tokens_neox': 4370, 'n_words': 1155}