<commit_before>add_file_target(FILE plle2_test.v SCANNER_TYPE verilog)
add_file_target(FILE pll_int_basys3_x1y0.v SCANNER_TYPE verilog)
add_file_target(FILE pll_buf_basys3_x1y0.v SCANNER_TYPE verilog)
add_file_target(FILE pll_ext_basys3_x1y0.v SCANNER_TYPE verilog)

add_file_target(FILE basys3_x1y0.pcf)

add_fpga_target(
  NAME pll_int_basys3_full
  BOARD basys3-full
  SOURCES pll_int_basys3_x1y0.v
  INPUT_IO_FILE basys3_x1y0.pcf
  EXPLICIT_ADD_FILE_TARGET
  )

add_fpga_target(
  NAME pll_buf_basys3_full
  BOARD basys3-full
  SOURCES pll_buf_basys3_x1y0.v
  INPUT_IO_FILE basys3_x1y0.pcf
  EXPLICIT_ADD_FILE_TARGET
  )

add_fpga_target(
  NAME pll_ext_basys3_full
  BOARD basys3-full
  SOURCES pll_ext_basys3_x1y0.v
  INPUT_IO_FILE basys3_x1y0.pcf
  EXPLICIT_ADD_FILE_TARGET
  )


add_vivado_target(
  NAME pll_int_basys3_full_vivado
  PARENT_NAME pll_int_basys3_full
  CLOCK_PINS clk
  CLOCK_PERIODS 10.0
  # TODO: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/1018
  DISABLE_DIFF_TEST
  )

add_vivado_target(
  NAME pll_buf_basys3_full_vivado
  PARENT_NAME pll_buf_basys3_full
  CLOCK_PINS clk
  CLOCK_PERIODS 10.0
  # TODO: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/1018<commit_msg>Use bottom graph to avoid input routing problems.<commit_after>add_file_target(FILE plle2_test.v SCANNER_TYPE verilog)
add_file_target(FILE pll_int_basys3_x1y0.v SCANNER_TYPE verilog)
add_file_target(FILE pll_buf_basys3_x1y0.v SCANNER_TYPE verilog)
add_file_target(FILE pll_ext_basys3_x1y0.v SCANNER_TYPE verilog)

add_file_target(FILE basys3_x1y0.pcf)

add_fpga_target(
  NAME pll_int_basys3_full
  BOARD basys3-bottom
  SOURCES pll_int_basys3_x1y0.v
  INPUT_IO_FILE basys3_x1y0.pcf
  EXPLICIT_ADD_FILE_TARGET
  )

add_fpga_target(
  NAME pll_buf_basys3_full
  BOARD basys3-bottom
  SOURCES pll_buf_basys3_x1y0.v
  INPUT_IO_FILE basys3_x1y0.pcf
  EXPLICIT_ADD_FILE_TARGET
  )

add_fpga_target(
  NAME pll_ext_basys3_full
  BOARD basys3-bottom
  SOURCES pll_ext_basys3_x1y0.v
  INPUT_IO_FILE basys3_x1y0.pcf
  EXPLICIT_ADD_FILE_TARGET
  )


add_vivado_target(
  NAME pll_int_basys3_full_vivado
  PARENT_NAME pll_int_basys3_full
  CLOCK_PINS clk
  CLOCK_PERIODS 10.0
  # TODO: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/1018
  DISABLE_DIFF_TEST
  )

add_vivado_target(
  NAME pll_buf_basys3_full_vivado
  PARENT_NAME pll_buf_basys3_full
  CLOCK_PINS clk
  CLOCK_PERIODS 10.0
  # TODO: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/1018
{'fraction_non_alphanumeric': 0.0505663430420712, 'fraction_numerical': 0.04449838187702265, 'mean_word_length': 5.81267217630854, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 3, 'https://': 4, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '5297823', 'n_tokens_mistral': 1237, 'n_tokens_neox': 1181, 'n_words': 148}