<commit_before>/*
 * Copyright (c) 2021 Andes Technology Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @brief Macros for the Andes ATCSMU
 */

#ifndef SOC_RISCV_ANDES_V5_SMU_H_
#define SOC_RISCV_ANDES_V5_SMU_H_

/*
 * SMU Register Base Address
 */

#if DT_NODE_EXISTS(DT_INST(0, andestech_atcsmu100))
#define SMU_BASE			DT_REG_ADDR(DT_INST(0, andestech_atcsmu100))
#endif /* DT_NODE_EXISTS(DT_INST(0, andestech_atcsmu100)) */

/*
 * SMU register offset
 */

/* Basic */
#define SMU_SYSTEMVER			0x00
#define SMU_BOARDVER			0x04
#define SMU_SYSTEMCFG			0x08
#define SMU_SMUVER			0x0C
<commit_msg>soc: riscv: riscv-privilege: andes_v5: make smu.h self contained<commit_after>/*
 * Copyright (c) 2021 Andes Technology Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @brief Macros for the Andes ATCSMU
 */

#ifndef SOC_RISCV_ANDES_V5_SMU_H_
#define SOC_RISCV_ANDES_V5_SMU_H_

#include <devicetree.h>
#include <sys/util_macro.h>

/*
 * SMU Register Base Address
 */

#if DT_NODE_EXISTS(DT_INST(0, andestech_atcsmu100))
#define SMU_BASE			DT_REG_ADDR(DT_INST(0, andestech_atcsmu100))
#endif /* DT_NODE_EXISTS(DT_INST(0, andestech_atcsmu100)) */

/*
 * SMU register offset
 */

/* Basic */
#define SMU_SYSTEMVER			0x00
#define SMU_BOARDVER			0x04
#define SMU_SYSTEMCFG			0x08
#define SMU_SMUVER			0x0C

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