<commit_before>#!/usr/bin/env python3
# -*- coding: utf-8 -*-

from hwt.code import If, Concat, FsmBuilder, In, log2ceil
from hwt.hdlObjects.constants import DIRECTION
from hwt.hdlObjects.typeShortcuts import vecT
from hwt.hdlObjects.types.enum import Enum
from hwt.interfaces.agents.rdSynced import RdSyncedAgent
from hwt.interfaces.std import Signal, RdSynced, VectSignal
from hwt.interfaces.utils import addClkRstn
from hwt.synthesizer.interfaceLevel.unit import Unit
from hwt.synthesizer.param import Param
from hwtLib.i2c.intf import I2c


NOP, START, STOP, READ, WRITE = range(5)


def hasRisen(last, actual):
    return ~last & actual


def hasFallen(last, actual):
    return last & ~actual


class I2cBitCntrlCmd(RdSynced):
    def _config(self):
        pass

    def _declr(self):
        self.din = Signal()
        self.cmd = VectSignal(log2ceil(5))
        self.rd = Signal(masterDir=DIRECTION.IN)

    def _getSimAgent(self):
        return I2cBitCntrlCmdAgent


class I2cBitCntrlCmdAgent(RdSyncedAgent):
    def doRead(self, s):
        """extract data from interface"""
        return (s.read(self.intf.cmd), s.read(self.intf.din))

    def doWrite(self, s, data):
        """write data to interface"""
        w = s.write
        if data is None:
            cmd, d = None, None
        else:
            cmd, d = data
        w(d, self.intf.din)
        w(cmd, self.intf.cmd)


class I2cMasterBitCtrl(Unit):
    """
    -----------------------------------
     Bit controller section
    ----------------------------------

     Translate simple commands into SCL/SDA transitions
     Each command has 5 states, 0/1/2/3/idle

     start:    SCL  ~~~~~~~~~~~~~~\____
               SDA  XX/~~~~~~~\______
                    x | 0 | 1 | 2 | 3 | i

     repstart  SCL  ______/~~~~~~~\___
               SDA  __/~~~~~~~\______
                    x | 0 | 1 | 2 | 3 | i

     stop      SCL  _______/~~~~~~~~~~~
               SDA  ==\___________/~~~~~
                    x | 0 | 1 | 2 | 3 | i

     - write    SCL  ______/~~~~~~~\____
               SDA  XXX===============XX
                    x | 0 | 1 | 2 | 3 | i

     - read     SCL  ______/~~~~~~~\____
               SDA  XXXXXXX=XXXXXXXXXXX
                    x | 0 | 1 | 2 | 3 | i

     Timing:      Normal mode     Fast mode
    ---------------------------------------------------------------
     Fscl         100KHz          400KHz
     Th_scl       4.0us           0.6us   High period of SCL
     Tl_scl       4.7us           1.3us   Low period of SCL
     Tsu:sta      4.7us           0.6us   setup time for a repeated start condition
     Tsu:sto      4.0us           0.6us   setup time for a stop condition
     Tbuf         4.7us           1.3us   Bus free time between a stop and start condition
    """
    def _config(self):
        self.CLK_CNTR_WIDTH = Param(16)

    def _declr(self):
        addClkRstn(self)
        self.clk_cnt_initVal = Signal(dtype=vecT(16))
        self.i2c = I2c()

        self.cntrl = I2cBitCntrlCmd()
        self.arbitrationLost = Signal()  # arbitration lost
        self.dout = Signal()

    def stateClkGen(self, scl_sync, scl_t, scl):
        # whenever the slave is not ready it can delay the cycle by pulling SCL low
        # delay scl_oen
        delayedScl_t = self._reg("delayedScl_t", defVal=1)
        delayedScl_t ** scl_t

        # slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
        # slave_wait remains asserted until the slave releases SCL
        slave_wait = self._reg("slave_wait", defVal=0)
        slave_wait ** ((~scl_t & delayedScl_t & ~scl) | (slave_wait & ~scl))

        clkCntr = self._reg("clkCntr",
                            vecT(self.CLK_CNTR_WIDTH, False),
                            defVal=self.clk_cnt_initVal)
        stateClkEn = self._reg("stateClkEn", defVal=1)

        If(clkCntr._eq(0) | scl_sync,<commit_msg>i2c fix docstrings to be compatible with sphinx<commit_after>#!/usr/bin/env python3
# -*- coding: utf-8 -*-

from hwt.code import If, Concat, FsmBuilder, In, log2ceil
from hwt.hdlObjects.constants import DIRECTION
from hwt.hdlObjects.typeShortcuts import vecT
from hwt.hdlObjects.types.enum import Enum
from hwt.interfaces.agents.rdSynced import RdSyncedAgent
from hwt.interfaces.std import Signal, RdSynced, VectSignal
from hwt.interfaces.utils import addClkRstn
from hwt.synthesizer.interfaceLevel.unit import Unit
from hwt.synthesizer.param import Param
from hwtLib.i2c.intf import I2c


NOP, START, STOP, READ, WRITE = range(5)


def hasRisen(last, actual):
    return ~last & actual


def hasFallen(last, actual):
    return last & ~actual


class I2cBitCntrlCmd(RdSynced):
    def _config(self):
        pass

    def _declr(self):
        self.din = Signal()
        self.cmd = VectSignal(log2ceil(5))
        self.rd = Signal(masterDir=DIRECTION.IN)

    def _getSimAgent(self):
        return I2cBitCntrlCmdAgent


class I2cBitCntrlCmdAgent(RdSyncedAgent):
    def doRead(self, s):
        """extract data from interface"""
        return (s.read(self.intf.cmd), s.read(self.intf.din))

    def doWrite(self, s, data):
        """write data to interface"""
        w = s.write
        if data is None:
            cmd, d = None, None
        else:
            cmd, d = data
        w(d, self.intf.din)
        w(cmd, self.intf.cmd)


class I2cMasterBitCtrl(Unit):
    """
    Translate simple commands into SCL/SDA transitions
    Each command has 5 states, 0/1/2/3/idle
    .. aafig::
        start:    SCL  ~~~~~~~~~~~~~~\____
                  SDA  XX/~~~~~~~\______
                       x | 0 | 1 | 2 | 3 | i
        
        repstart  SCL  ______/~~~~~~~\___
                  SDA  __/~~~~~~~\______
                       x | 0 | 1 | 2 | 3 | i
        
        stop      SCL  _______/~~~~~~~~~~~
                  SDA  ==\___________/~~~~~
                       x | 0 | 1 | 2 | 3 | i
        
        write    SCL  ______/~~~~~~~\____
                 SDA  XXX===============XX
                      x | 0 | 1 | 2 | 3 | i
        
        read     SCL  ______/~~~~~~~\____
                 SDA  XXXXXXX=XXXXXXXXXXX
                      x | 0 | 1 | 2 | 3 | i

    ============ ============== ============================================================= 
     Timing:      Normal mode    Fast mode
    ============ ============== =============================================================
     Fscl         100KHz         400KHz
     Th_scl       4.0us          0.6us   High period of SCL
     Tl_scl       4.7us          1.3us   Low period of SCL
     Tsu:sta      4.7us          0.6us   setup time for a repeated start condition
     Tsu:sto      4.0us          0.6us   setup time for a stop condition
     Tbuf         4.7us          1.3us   Bus free time between a stop and start condition
    ============ ============== =============================================================
    """
    def _config(self):
        self.CLK_CNTR_WIDTH = Param(16)

    def _declr(self):
        addClkRstn(self)
        self.clk_cnt_initVal = Signal(dtype=vecT(16))
        self.i2c = I2c()

        self.cntrl = I2cBitCntrlCmd()
        self.arbitrationLost = Signal()  # arbitration lost
        self.dout = Signal()

    def stateClkGen(self, scl_sync, scl_t, scl):
        # whenever the slave is not ready it can delay the cycle by pulling SCL low
        # delay scl_oen
        delayedScl_t = self._reg("delayedScl_t", defVal=1)
        delayedScl_t ** scl_t

        # slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
        # slave_wait remains asserted until the slave releases SCL
        slave_wait = self._reg("slave_wait", defVal=0)
        slave_wait ** ((~scl_t & delayedScl_t & ~scl) | (slave_wait & ~scl))

        clkCntr = self._reg("clkCntr",
                            vecT(self.CLK_CNTR_WIDTH, False),
                            defVal=self.clk_cnt_initVal)
        stateClkEn = self._reg("stateClkEn", defVal=1)

        If(clkCntr._eq(0) | scl_sync,
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