<commit_before>!# issue 1323
!#CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
0x0: 0x70,0x47,0x00 == bx lr ; op_count: 1 ; operands[0].type: REG = lr ; operands[0].access: READ ; Registers read: lr ; Registers modified: pc ; Groups: thumb jump 

!# issue 1317
!#CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
0x0: 0xd0,0xe8,0x11,0xf0 == tbh [r0, r1, lsl #1] ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = r0 ; operands[0].mem.index: REG = r1 ; operands[0].mem.lshift: 0x1 ; operands[0].access: READ ; Shift: 2 = 1 ; Registers read: r0 r1 ; Groups: thumb2 jump 

!# issue 1308
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
0x0: 0x83,0x3d,0xa1,0x75,0x21,0x00,0x04 == cmp dword ptr [rip + 0x2175a1], 4 ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0x83 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0x3d ; disp: 0x2175a1 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0x4 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.base: REG = rip ; operands[0].mem.disp: 0x2175a1 ; operands[0].size: 4 ; operands[0].access: READ ; operands[1].type: IMM = 0x4 ; operands[1].size: 4 ; Registers read: rip ; Registers modified: rflags ; EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF

!# issue 1262
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
0x0: 0x0f,0x95,0x44,0x24,0x5e == setne byte ptr [rsp + 0x5e] ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0x0f 0x95 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0x44 ; disp: 0x5e ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x5e ; operands[0].size: 1 ; operands[0].access: WRITE ; Registers read: rflags rsp ; EFLAGS: TEST_ZF

!# issue 1262
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
0x0: 0x0f,0x94,0x44,0x24,0x1f == sete byte ptr [rsp + 0x1f] ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0x0f 0x94 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0x44 ; disp: 0x1f ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x1f ; operands[0].size: 1 ; operands[0].access: WRITE ; Registers read: rflags rsp ; EFLAGS: TEST_ZF

!# issue 1255
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
0x0: 0xdb,0x7c,0x24,0x40 == fstp xword ptr [rsp + 0x40] ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0xdb 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0x7c ; disp: 0x40 ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x40 ; operands[0].size: 10 ; operands[0].access: WRITE ; Registers read: rsp ; Registers modified: fpsw ; FPU_FLAGS: MOD_C1 UNDEF_C0 UNDEF_C2 UNDEF_C3 ; Groups: fpu 

!# issue 1255
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
0x0: 0xdd,0xd9 == fstp st(1) ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0xdd 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0xd9 ; disp: 0x0 ; sib: 0x0 ; op_count: 1 ; operands[0].type: REG = st(1) ; operands[0].size: 10 ; operands[0].access: WRITE ; Registers modified: fpsw st(1) ; EFLAGS: MOD_CF PRIOR_SF PRIOR_AF PRIOR_PF

!# issue 1255
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
0x0: 0xdf,0x7c,0x24,0x68 == fistp qword ptr [rsp + 0x68] ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0xdf 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0x7c ; disp: 0x68 ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x68 ; operands[0].size: 8 ; operands[0].access: WRITE ; Registers read: rsp ; Registers modified: fpsw ; FPU_FLAGS: RESET_C1 UNDEF_C0 UNDEF_C2 UNDEF_C3 ; Groups: fpu 

!# issue 1221
!#CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None
0x0: 0x55,0x48,0x89,0xe5 == call 0x55222794

!# issue 1144
!#CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None
0x0: 0x00,0x00,0x02,0xb6 == tbz x0, #0x20, #0x4000

!# issue 1144
!#CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None
0x0: 0x00,0x00,0x04,0xb6 == tbz x0, #0x20, #0xffffffffffff8000

!# issue 1144
!#CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None
0x0: 0x00,0x00,0x02,0xb7 == tbnz x0, #0x20, #0x4000

!# issue 1144
!#CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None
0x0: 0x00,0x00,0x04,0xb7 == tbnz x0, #0x20, #0xffffffffffff8000

!# issue 826
!#CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
0x0: 0x0b,0x00,0x00,0x0a == beq #0x34 ; op_count: 1 ; operands[0].type: IMM = 0x34 ; Code condition: 1 ; Registers read: pc ; Registers modified: pc ; Groups: branch_relative arm jump 

!# issue 1047
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
0x0: 0x48,0x83,0xe4,0xf0 == andq $0xfffffffffffffff0, %rsp

!# issue 959
!#CS_ARCH_X86, CS_MODE_32, None
0x0: 0xa0,0x28,0x57,0x88,0x7c == mov al, byte ptr [0x7c885728]

!# issue 950
!#CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
0x0: 0x66,0xa3,0x94,0x90,0x04,0x08 == mov word ptr [0x8049094], ax ; Prefix:0x00 0x00 0x66 0x00  ; Opcode:0xa3 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x8049094 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.disp: 0x8049094 ; operands[0].size: 2 ; operands[0].access: WRITE ; operands[1].type: REG = ax ; operands[1].size: 2 ; operands[1].access: READ ; Registers read: ax

!# issue 938
!#CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN, None
0x0: 0x70,0x00,0xb2,0xff == sd $s2, 0x70($sp)

!# issue 915
!#CS_ARCH_X86, CS_MODE_64, None
0x0: 0xf0,0x0f,0x1f,0x00 == lock nop dword ptr [rax]

!# issue 913
!#CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
0x0: 0x04,0x10,0x9d,0xe4 == pop {r1} ; op_count: 1 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; Write-back: True ; Registers read: sp ; Registers modified: sp r1 ; Groups: arm 

!# issue 884
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
0x0: 0x64,0x48,0x03,0x04,0x25,0x00,0x00,0x00,0x00 == addq %fs:0, %rax

!# issue 872
!#CS_ARCH_X86, CS_MODE_32, None
0x0: 0xf2,0xeb,0x3e == bnd jmp 0x41

!# issue 861
!#CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
0x0: 0x01,0x81,0xa0,0xfc == stc2 p1, c8, [r0], #4 ; op_count: 4 ; operands[0].type: P-IMM = 1 ; operands[1].type: C-IMM = 8 ; operands[2].type: MEM ; operands[2].mem.base: REG = r0 ; operands[2].access: READ ; operands[3].type: IMM = 0x4 ; Write-back: True ; Registers read: r0 ; Registers modified: r0 ; Groups: prev8 

!# issue 852
!#CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
0x0: 0x64,0xa3,0x00,0x00,0x00,0x00 == mov dword ptr fs:[0], eax ; Prefix:0x00 0x64 0x00 0x00  ; Opcode:0xa3 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.segment: REG = fs ; operands[0].size: 4 ; operands[0].access: WRITE ; operands[1].type: REG = eax ; operands[1].size: 4 ; operands[1].access: READ ; Registers read: fs eax

!# issue 825
!#CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
0x0: 0x0e,0xf0,0xa0,0xe1 == mov pc, lr ; op_count: 2 ; operands[0].type: REG = pc ; operands[0].access: WRITE ; operands[1].type: REG = lr ; operands[1].access: READ ; Registers read: lr ; Registers modified: pc ; Groups: arm 

!# issue 813
!#CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN, None
0x0: 0xF6,0xC0,0x04,0x01 == movt r4, #0x801

!# issue 809
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
0x0: 0x0f,0x29,0x8d,0xf0,0xfd,0xff,0xff == movaps xmmword ptr [rbp - 0x210], xmm1 ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0x0f 0x29 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0x8d ; disp: 0xfffffffffffffdf0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.base: REG = rbp ; operands[0].mem.disp: 0xfffffffffffffdf0 ; operands[0].size: 16 ; operands[0].access: WRITE ; operands[1].type: REG = xmm1 ; operands[1].size: 16 ; operands[1].access: READ ; Registers read: rbp xmm1 ; Groups: sse1 

!# issue 807
!#CS_ARCH_X86, CS_MODE_64, None
0x0: 0x4c,0x0f,0x00,0x80,0x16,0x76,0x8a,0xfe == sldt word ptr [rax - 0x17589ea]

!# issue 806
!#CS_ARCH_X86, CS_MODE_64, None
0x0: 0x0f,0x35 == sysexit 

!# issue 805
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
0x0: 0x48,0x4c,0x0f,0xb5,0x80,0x16,0x76,0x8a,0xfe == lgs -0x17589ea(%rax), %r8

!# issue 804
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
0x0: 0x66,0x48,0xf3,0xd1,0xc0 == rol $1, %ax

!# issue 789
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
0x0: 0x8e,0x1e == movw 0(%rsi), %ds

!# issue 767
!#CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL<commit_msg>cstest: correct 0(mem) case in issues.cs<commit_after>!# issue 1323
!#CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
0x0: 0x70,0x47,0x00 == bx lr ; op_count: 1 ; operands[0].type: REG = lr ; operands[0].access: READ ; Registers read: lr ; Registers modified: pc ; Groups: thumb jump 

!# issue 1317
!#CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
0x0: 0xd0,0xe8,0x11,0xf0 == tbh [r0, r1, lsl #1] ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = r0 ; operands[0].mem.index: REG = r1 ; operands[0].mem.lshift: 0x1 ; operands[0].access: READ ; Shift: 2 = 1 ; Registers read: r0 r1 ; Groups: thumb2 jump 

!# issue 1308
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
0x0: 0x83,0x3d,0xa1,0x75,0x21,0x00,0x04 == cmp dword ptr [rip + 0x2175a1], 4 ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0x83 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0x3d ; disp: 0x2175a1 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0x4 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.base: REG = rip ; operands[0].mem.disp: 0x2175a1 ; operands[0].size: 4 ; operands[0].access: READ ; operands[1].type: IMM = 0x4 ; operands[1].size: 4 ; Registers read: rip ; Registers modified: rflags ; EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF

!# issue 1262
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
0x0: 0x0f,0x95,0x44,0x24,0x5e == setne byte ptr [rsp + 0x5e] ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0x0f 0x95 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0x44 ; disp: 0x5e ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x5e ; operands[0].size: 1 ; operands[0].access: WRITE ; Registers read: rflags rsp ; EFLAGS: TEST_ZF

!# issue 1262
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
0x0: 0x0f,0x94,0x44,0x24,0x1f == sete byte ptr [rsp + 0x1f] ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0x0f 0x94 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0x44 ; disp: 0x1f ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x1f ; operands[0].size: 1 ; operands[0].access: WRITE ; Registers read: rflags rsp ; EFLAGS: TEST_ZF

!# issue 1255
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
0x0: 0xdb,0x7c,0x24,0x40 == fstp xword ptr [rsp + 0x40] ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0xdb 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0x7c ; disp: 0x40 ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x40 ; operands[0].size: 10 ; operands[0].access: WRITE ; Registers read: rsp ; Registers modified: fpsw ; FPU_FLAGS: MOD_C1 UNDEF_C0 UNDEF_C2 UNDEF_C3 ; Groups: fpu 

!# issue 1255
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
0x0: 0xdd,0xd9 == fstp st(1) ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0xdd 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0xd9 ; disp: 0x0 ; sib: 0x0 ; op_count: 1 ; operands[0].type: REG = st(1) ; operands[0].size: 10 ; operands[0].access: WRITE ; Registers modified: fpsw st(1) ; EFLAGS: MOD_CF PRIOR_SF PRIOR_AF PRIOR_PF

!# issue 1255
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
0x0: 0xdf,0x7c,0x24,0x68 == fistp qword ptr [rsp + 0x68] ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0xdf 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0x7c ; disp: 0x68 ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x68 ; operands[0].size: 8 ; operands[0].access: WRITE ; Registers read: rsp ; Registers modified: fpsw ; FPU_FLAGS: RESET_C1 UNDEF_C0 UNDEF_C2 UNDEF_C3 ; Groups: fpu 

!# issue 1221
!#CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None
0x0: 0x55,0x48,0x89,0xe5 == call 0x55222794

!# issue 1144
!#CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None
0x0: 0x00,0x00,0x02,0xb6 == tbz x0, #0x20, #0x4000

!# issue 1144
!#CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None
0x0: 0x00,0x00,0x04,0xb6 == tbz x0, #0x20, #0xffffffffffff8000

!# issue 1144
!#CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None
0x0: 0x00,0x00,0x02,0xb7 == tbnz x0, #0x20, #0x4000

!# issue 1144
!#CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, None
0x0: 0x00,0x00,0x04,0xb7 == tbnz x0, #0x20, #0xffffffffffff8000

!# issue 826
!#CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
0x0: 0x0b,0x00,0x00,0x0a == beq #0x34 ; op_count: 1 ; operands[0].type: IMM = 0x34 ; Code condition: 1 ; Registers read: pc ; Registers modified: pc ; Groups: branch_relative arm jump 

!# issue 1047
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
0x0: 0x48,0x83,0xe4,0xf0 == andq $0xfffffffffffffff0, %rsp

!# issue 959
!#CS_ARCH_X86, CS_MODE_32, None
0x0: 0xa0,0x28,0x57,0x88,0x7c == mov al, byte ptr [0x7c885728]

!# issue 950
!#CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
0x0: 0x66,0xa3,0x94,0x90,0x04,0x08 == mov word ptr [0x8049094], ax ; Prefix:0x00 0x00 0x66 0x00  ; Opcode:0xa3 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x8049094 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.disp: 0x8049094 ; operands[0].size: 2 ; operands[0].access: WRITE ; operands[1].type: REG = ax ; operands[1].size: 2 ; operands[1].access: READ ; Registers read: ax

!# issue 938
!#CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN, None
0x0: 0x70,0x00,0xb2,0xff == sd $s2, 0x70($sp)

!# issue 915
!#CS_ARCH_X86, CS_MODE_64, None
0x0: 0xf0,0x0f,0x1f,0x00 == lock nop dword ptr [rax]

!# issue 913
!#CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
0x0: 0x04,0x10,0x9d,0xe4 == pop {r1} ; op_count: 1 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; Write-back: True ; Registers read: sp ; Registers modified: sp r1 ; Groups: arm 

!# issue 884
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
0x0: 0x64,0x48,0x03,0x04,0x25,0x00,0x00,0x00,0x00 == addq %fs:0, %rax

!# issue 872
!#CS_ARCH_X86, CS_MODE_32, None
0x0: 0xf2,0xeb,0x3e == bnd jmp 0x41

!# issue 861
!#CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
0x0: 0x01,0x81,0xa0,0xfc == stc2 p1, c8, [r0], #4 ; op_count: 4 ; operands[0].type: P-IMM = 1 ; operands[1].type: C-IMM = 8 ; operands[2].type: MEM ; operands[2].mem.base: REG = r0 ; operands[2].access: READ ; operands[3].type: IMM = 0x4 ; Write-back: True ; Registers read: r0 ; Registers modified: r0 ; Groups: prev8 

!# issue 852
!#CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
0x0: 0x64,0xa3,0x00,0x00,0x00,0x00 == mov dword ptr fs:[0], eax ; Prefix:0x00 0x64 0x00 0x00  ; Opcode:0xa3 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.segment: REG = fs ; operands[0].size: 4 ; operands[0].access: WRITE ; operands[1].type: REG = eax ; operands[1].size: 4 ; operands[1].access: READ ; Registers read: fs eax

!# issue 825
!#CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
0x0: 0x0e,0xf0,0xa0,0xe1 == mov pc, lr ; op_count: 2 ; operands[0].type: REG = pc ; operands[0].access: WRITE ; operands[1].type: REG = lr ; operands[1].access: READ ; Registers read: lr ; Registers modified: pc ; Groups: arm 

!# issue 813
!#CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN, None
0x0: 0xF6,0xC0,0x04,0x01 == movt r4, #0x801

!# issue 809
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
0x0: 0x0f,0x29,0x8d,0xf0,0xfd,0xff,0xff == movaps xmmword ptr [rbp - 0x210], xmm1 ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0x0f 0x29 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0x8d ; disp: 0xfffffffffffffdf0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.base: REG = rbp ; operands[0].mem.disp: 0xfffffffffffffdf0 ; operands[0].size: 16 ; operands[0].access: WRITE ; operands[1].type: REG = xmm1 ; operands[1].size: 16 ; operands[1].access: READ ; Registers read: rbp xmm1 ; Groups: sse1 

!# issue 807
!#CS_ARCH_X86, CS_MODE_64, None
0x0: 0x4c,0x0f,0x00,0x80,0x16,0x76,0x8a,0xfe == sldt word ptr [rax - 0x17589ea]

!# issue 806
!#CS_ARCH_X86, CS_MODE_64, None
0x0: 0x0f,0x35 == sysexit 

!# issue 805
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
0x0: 0x48,0x4c,0x0f,0xb5,0x80,0x16,0x76,0x8a,0xfe == lgs -0x17589ea(%rax), %r8

!# issue 804
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
0x0: 0x66,0x48,0xf3,0xd1,0xc0 == rol $1, %ax

!# issue 789
!#CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
0x0: 0x8e,0x1e == movw (%rsi), %ds

!# issue 767
!#CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
{'fraction_non_alphanumeric': 0.14489920586438607, 'fraction_numerical': 0.1510079413561393, 'mean_word_length': 5.180067950169875, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 3, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 10, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '5794944', 'n_tokens_mistral': 9249, 'n_tokens_neox': 8036, 'n_words': 1736}