<commit_before># ArgInOut
In class, we went through a "HelloWorld" example. In Part II, we will first go through the process of deploying this example on the DE1SoC board. 

Before you start, make sure that you are in the directory where you have your spatial set up.
First, initialize the environment variables by running:
```bash
source init-env.sh
```
## Completing ArgInOut
Take a look at $SPATIAL_HOME/apps/src/ArgInOut.scala, and complete it by following the comments in the file. 
Before running apps, we need to first make them by running:
```bash
make apps
```

## Simulating Apps
### Functional Simulation
First, we want to make sure that the app is functionally correct. To do so, run: 
```bash
bin/spatial ArgInOut --scala
```
This will generate the app files under ./gen/ArgInOut. Navigate into ./gen/ArgInOut and run the functional simulation with argument set to 3:
```bash
cd ./gen/ArgInOut
chmod +x run.sh
./run.sh 3
```
You will see the following messages in your terminal: 
```bash
[info] Running Main 3
expected: 7
result: 7
```

### Cycle-accurate Simulation
After verifying the basic functions, we want to start generating circuit designs. To do so, you need to first go back to the home directory of spatial and then generate the chisel project files for ArgInOut:
```bash
cd $SPATIAL_HOME
bin/spatial ArgInOut --chisel
```

This will generate the hardware description files under ./gen/ArgInOut. Navigate into ./gen/ArgInOut, and you will see the following folders: 
```bash
chisel
cpp
```

The chisel folder contains descriptions for running designs on FPGA, and the cpp file contains C++ code that runs on the CPU side. To generate cycle-accurate simulation, we need to first scp the generated project folder onto a server that has VCS installed. In this class, we will use the tucson server to run our simulation. Run: 
```bash
cd $SPATIAL_HOME
scp -r gen/ArgInOut <EMAIL>.stanford.edu:~/YOUR_TARGET_DIR
```
YOUR_TARGET_DIR is a placeholder. You should replace it with your working directory on the server.
On the server side, first navigate into the project folder, then run: 
```bash
make vcs
./Top YOUR_ARG_IN
```
This will initiate VCS simulation on tucson. You will observe something similar to the following outputs on your terminal:
```bash
tianzhao@tucson:~/synthTest/ArgInOut$ ./run.sh 3
[WARNING]: DELITE_NUM_THREADS undefined, defaulting to 1
Executing with 1 thread(s)
Chronologic VCS simulator copyright 1991-2015
Contains Synopsys proprietary information.
Compiler version K-2015.09-SP2-7_Full64; Runtime version K-2015.09-SP2-7_Full64;  Apr 11 23:37 2017
[SIM] Sim process started!
idealDRAM = 0
Connection successful!
== Loading device model file '/home/tianzhao/synthTest/ArgInOut/verilog/DRAMSim2/ini/DDR2_micron_16M_8b_x8_sg3E.ini' == 
== Loading system model file '/home/tianzhao/synthTest/ArgInOut/verilog/DRAMSim2/spatial.dram.ini' == 
===== MemorySystem 0 =====
CH. 0 TOTAL_STORAGE : 16384MB | 16 Ranks | 8 Devices per rank
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
writing vis file to /home/tianzhao/synthTest/ArgInOut/verilog/DRAMSim2/results/dramSimVCS/DDR2_micron_16M_8b_x8_sg3E/16GB.1Ch.16R.scheme2.open_page.32TQ.32CQ.RtB.pRank.vis
DRAMSim2 Clock Frequency =333333333Hz, CPU Clock Frequency=150000000Hz
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
Design ran for 8 cycles, status = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
Kernel done, test run time = 0 ms
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
expected: 7
result: 7
Received SIGHUP (signal 1), exiting.
			V C S   S i m u l a t i o n   R e p o r t 
			Time: 59000 ps
			CPU Time:      0.500 seconds;       Data structure size:   0.0Mb
			Tue Apr 11 23:37:01 2017
			Realistic DRAM Simulation

```

## Synthesizing and Running Spatial Apps on DE1-SoC
On tucson, under the project folder, run:
```bash
make de1soc
```
The synthesis process will start, and will take roughly 15 min to finish. After the synthesis finishes, you will see two generated files under ./prog in the project directory:<commit_msg>added part2 readme<commit_after># ArgInOut
In class, we went through a "HelloWorld" example. In Part II, we will first go through the process of deploying this example on the DE1SoC board. 

Before you start, make sure that you are in the directory where you have your spatial set up.
First, initialize the environment variables by running:
```bash
source init-env.sh
```
## Completing ArgInOut
Take a look at $SPATIAL_HOME/apps/src/ArgInOut.scala, and complete it by following the comments in the file. 
Before running apps, we need to first make them by running:
```bash
make apps
```

## Simulating Apps
### Functional Simulation
First, we want to make sure that the app is functionally correct. To do so, run: 
```bash
bin/spatial ArgInOut --scala
```
This will generate the app files under ./gen/ArgInOut. Navigate into ./gen/ArgInOut and run the functional simulation with argument set to 3:
```bash
cd ./gen/ArgInOut
chmod +x run.sh
./run.sh 3
```
You will see the following messages in your terminal: 
```bash
[info] Running Main 3
expected: 7
result: 7
```

### Cycle-accurate Simulation
After verifying the basic functions, we want to start generating circuit designs. To do so, you need to first go back to the home directory of spatial and then generate the chisel project files for ArgInOut:
```bash
cd $SPATIAL_HOME
bin/spatial ArgInOut --chisel
```

This will generate the hardware description files under ./gen/ArgInOut. Navigate into ./gen/ArgInOut, and you will see the following folders: 
```bash
chisel
cpp
```

The chisel folder contains descriptions for running designs on FPGA, and the cpp folder contains C++ code that runs on the CPU side. To generate cycle-accurate simulation, we need to first scp the generated project folder onto a server that has VCS installed. In this class, we will use the tucson server to run our simulation. Run: 
```bash
cd $SPATIAL_HOME
scp -r gen/ArgInOut <EMAIL>:~/
```
After the scp is finished, you will need to complete the rest of the work on tucson. To log onto tucson, run:
```bash
ssh -Y <EMAIL>
```

On the server side, first you need to set up the environment by running:
```bash
source env.sh
```
Then navigate into the project folder and compile VCS binary by running: 
```bash
cd ~/ArgInOut
make vcs
```
To run VCS simulation, let's use 3 as the input argument. The following command will initiate the simulation:
```bash
chmod +x run.sh
./run.sh 3
```
You will observe something similar to the following outputs on your terminal:
```bash
tianzhao@tucson:~/synthTest/ArgInOut$ ./run.sh 3
[WARNING]: DELITE_NUM_THREADS undefined, defaulting to 1
Executing with 1 thread(s)
Chronologic VCS simulator copyright 1991-2015
Contains Synopsys proprietary information.
Compiler version K-2015.09-SP2-7_Full64; Runtime version K-2015.09-SP2-7_Full64;  Apr 11 23:37 2017
[SIM] Sim process started!
idealDRAM = 0
Connection successful!
== Loading device model file '/home/tianzhao/synthTest/ArgInOut/verilog/DRAMSim2/ini/DDR2_micron_16M_8b_x8_sg3E.ini' == 
== Loading system model file '/home/tianzhao/synthTest/ArgInOut/verilog/DRAMSim2/spatial.dram.ini' == 
===== MemorySystem 0 =====
CH. 0 TOTAL_STORAGE : 16384MB | 16 Ranks | 8 Devices per rank
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
writing vis file to /home/tianzhao/synthTest/ArgInOut/verilog/DRAMSim2/results/dramSimVCS/DDR2_micron_16M_8b_x8_sg3E/16GB.1Ch.16R.scheme2.open_page.32TQ.32CQ.RtB.pRank.vis
DRAMSim2 Clock Frequency =333333333Hz, CPU Clock Frequency=150000000Hz
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
Design ran for 8 cycles, status = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
Kernel done, test run time = 0 ms
[readOutputStream] data = 374a656e, tag = 8b3dfe16, last = 1
expected: 7
result: 7
Received SIGHUP (signal 1), exiting.
			V C S   S i m u l a t i o n   R e p o r t 
			Time: 59000 ps
			CPU Time:      0.500 seconds;       Data structure size:   0.0Mb
			Tue Apr 11 23:37:01 2017
			Realistic DRAM Simulation

```
As you can see, the simulation result tells us that the expected result is the same as the one generated by VCS.

## Synthesizing and Running Spatial Apps on DE1-SoC
On tucson, under the same project folder, run:
```bash
make vcs-clean
make de1soc
```
The synthesis process will start, and will take roughly 15 min to finish. After the synthesis finishes, you will see two generated files under ./prog in the project directory:
{'fraction_non_alphanumeric': 0.0892189920714481, 'fraction_numerical': 0.07299735714936663, 'mean_word_length': 4.528463476070529, 'pattern_counts': {'":': 0, '<': 6, '<?xml version=': 0, '>': 6, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 4, 'word_list_counts': {'cursed_substrings.json': 4, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '4851929', 'n_tokens_mistral': 4372, 'n_tokens_neox': 3612, 'n_words': 1449}