<commit_before># Pipelined MIPS CPU

## Instructions

1. Data processing
2. PSR (Program Status Register) transfer
3. Multiply
4. Single data swap
5. Single data transfer
6. Branch Predictor
7. Block data transfer
8. Coprocessor register transfer
9. Coprocessor data transfer
10. Coprocessor data operation
11. Undefined Instruction
12. Software interrupt 

## Frameworks

### Controller

*   Instruction decoding
*   Pipeline Registers
*   FSM(branch predictor)
*   Interrupt handler

## Installation

```sh
$ sudo apt install logisim # install logisim platform
$ sudo apt install verilog # install icarus verilog simulatr
$ sudo apt install gtkwave # install waveform viewer comes with icarus verilog
$ sudo apt install yosys   # synthesize
$ sudo apt install geda    # graphic eda toolchains
```

## Development

```sh
$ iverilog -o demo demo_tb.v demo.v # compiler
$ iverilog -o demo -c src.list      # src.list => demo.v demo_tb.v
$ iverilog -s main -o hello hello.v # set root module to `main`
$ vvp demo                          # simulation runtime engine
$ vvp -n demo -lxt2
$ gtkwave demo.lxt
$ gtkwave trace.vcd
```

### GTKWave

In your .v file, specify:

```verilog
$dumpfile(“file.vcd”)
$dumpvars(level, vars_or_modules)
```

where level means 0 all or 1 listed only:

*   file.vcd is created when vvp is run
*   Visualize using: gtkwave file.vcd

```verilog
module trace;
    reg clk=0; reg[3:0]a=4'd0; reg b=0;
    always #1 clk=~clk;
    always @(posedge clk) begin
        a=a+1; b=a[2]; end
    initial begin<commit_msg>update(arch-pipeline-test bench): advanced tb with iverilog flags<commit_after># Pipelined MIPS CPU

## Instructions

1. Data processing
2. PSR (Program Status Register) transfer
3. Multiply
4. Single data swap
5. Single data transfer
6. Branch Predictor
7. Block data transfer
8. Coprocessor register transfer
9. Coprocessor data transfer
10. Coprocessor data operation
11. Undefined Instruction
12. Software interrupt 

## Frameworks

### Controller

*   Instruction decoding
*   Pipeline Registers
*   FSM(branch predictor)
*   Interrupt handler

## Installation

```sh
$ sudo apt install logisim # install logisim platform
$ sudo apt install verilog # install icarus verilog simulatr
$ sudo apt install gtkwave # install waveform viewer comes with icarus verilog
$ sudo apt install yosys   # synthesize
$ sudo apt install geda    # graphic eda toolchains
```

## Tools

```sh
$ iverilog -o demo demo_tb.v demo.v # compiler
$ iverilog -o demo -c src.list      # src.list => demo.v demo_tb.v
$ iverilog -s main -o hello hello.v # set root module to `main`
$ iverilog -E -o preprocessed.v unpreprocessed.v # pre-process signal stage
$ iverilog -I/include               # for `include directive
$ iverilog -y/lib                   # add lib search path
$ vvp demo                          # simulation runtime engine
$ vvp -n demo -lxt2
$ gtkwave demo.lxt
$ gtkwave trace.vcd
```

### test bench

*   `$time/$finish/$display/$monitor`

*   `$value$plusargs`

```verilog
module main;

  reg clk, reset;
  reg [31:0] x;
  wire [15:0] y;
  wire        rdy;

  sqrt32 dut (clk, rdy, reset, x, y);

  always #10 clk = ~clk;

  initial begin
     clk = 0;
     reset = 1;

     if (! $value$plusargs("x=%d", x)) begin
        $display("ERROR: please specify +x=<value> to start.");
        $finish;
     end

     #35 reset = 0;

     wait (rdy) $display("y=%d", y);
     $finish;
  end // initial begin

endmodule // main
```

```sh
$ iverilog -osqrt_plusargs.vvp sqrt_plusargs.v sqrt.v
$ vvp sqrt_plusargs.vvp +x=81
  # => y = 9
```

*   $readmemh

```verilog
module main;

  reg clk, reset;
  reg [31:0] data[4:0];
  reg [31:0] x;
  wire [15:0] y;
  wire        rdy;

  sqrt32 dut (clk, rdy, reset, x, y);

  always #10 clk = ~clk;

  integer i;
  initial begin
     /* Load the data set from the hex file. */
     $readmemh("sqrt.hex", data);
     for (i = 0 ;  i <= 4 ;  i = i + 1) begin
       clk = 0;
       reset = 1;

       x = data[i];

       #35 reset = 0;

       wait (rdy) $display("y=%d", y);
     end
     $finish;
  end // initial begin

endmodule // main
```

```sh
  # sqrt.hex =>
  # 51
  # 19
  # 1a
  # 18
  # 1
$ iverilog -osqrt_readmem.vvp sqrt_readmem.vl sqrt.vl
$ vvp sqrt_readmem.vvp
  # y = 9
  # y = 5
  # y = 5
  # y = 4
  # y = 1
```

### GTKWave

In your .v file, specify:

```verilog
$dumpfile(“file.vcd”)
$dumpvars(level, vars_or_modules)
```

where level means 0 all or 1 listed only:

*   file.vcd is created when vvp is run
*   Visualize using: gtkwave file.vcd

```verilog
module trace;
    reg clk=0; reg[3:0]a=4'd0; reg b=0;
    always #1 clk=~clk;
    always @(posedge clk) begin
        a=a+1; b=a[2]; end
    initial begin
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