<commit_before>#!/usr/bin/env python
import argparse
import ConfigParser
import getpass
import math
import os
import sys

from sweep_config import *

GEM5_CFG = "gem5.cfg"
ALADDIN_CFG = "aladdin.cfg"
CACTI_CACHE_CFG = "cacti_cache.cfg"
CACTI_TLB_CFG = "cacti_tlb.cfg"
CACTI_LQ_CFG = "cacti_lq.cfg"
CACTI_SQ_CFG = "cacti_sq.cfg"

# Taken from the template cfg file in <gem5_home>/configs/aladdin.
GEM5_DEFAULTS = {
  "cycle_time": 1,
  "memory_type": "cache",
  "spad_ports": 1,
  "tlb_hit_latency": 0,
  "tlb_miss_latency": 100,
  "tlb_page_size": 4096,
  "tlb_entries": 0,
  "tlb_max_outstanding_walks": 0,
  "tlb_assoc": 0,
  "tlb_bandwidth": 1,
  "is_perfect_tlb": False,
  "load_bandwidth": 1,
  "load_queue_size": 16,
  "store_bandwidth": 1,
  "store_queue_size": 16,
  "cache_assoc": 8,
  "cache_hit_latency": 1,
  "cache_line_sz" : 64,
  "dma_setup_latency" : 1,
  "max_dma_requests" : 16,
}

def generate_aladdin_config(benchmark, config_name, params):
  """ Write an Aladdin configuration file for the specified parameters.

  Args:
    benchmark: A benchmark description object.
    config_name: Name of the configuration.
    params: Configuration parameters. Must include the keys partition,
        unrolling, and pipelining.
  """
  os.chdir(config_name)
  config_file = open(ALADDIN_CFG, "wb")
  if "pipelining" in params:
    config_file.write("pipelining,%d\n" % params["pipelining"])

  if "partition" in params:
    for array in benchmark.arrays:
      if array.partition_type == PARTITION_CYCLIC:
        config_file.write("partition,cyclic,%s,%d,%d,%d\n" %
                          (array.name,
                           array.size*array.word_size,
                           array.word_size,
                           params["partition"]))
      elif array.partition_type == PARTITION_BLOCK:
        config_file.write("partition,block,%s,%d,%d,%d\n" %
                          (array.name,
                           array.size*array.word_size,
                           array.word_size,
                           params["partition"]))
      elif array.partition_type == PARTITION_COMPLETE:
        config_file.write("partition,complete,%s,%d\n" %
                          (array.name, array.size*array.word_size))
      else:
        print("Invalid array partitioning configuration for array %s." %
              array.name)
        exit(1)

  for loop in benchmark.loops:
    if (loop.trip_count == UNROLL_FLATTEN):
      config_file.write("flatten,%s,%d\n" % (loop.name, loop.line_num))
    elif (params["unrolling"] >= loop.trip_count):
      config_file.write("flatten,%s,%d\n" % (loop.name, loop.line_num))
    elif (loop.trip_count == UNROLL_ONE):
      config_file.write("unrolling,%s,%d,%d\n" %
                        (loop.name, loop.line_num, loop.trip_count))
    elif (loop.trip_count == ALWAYS_UNROLL or
          params["unrolling"] < loop.trip_count):
      # We only unroll if it was specified to always unroll or if the loop's
      # trip count is greater than the current unrolling factor.
      config_file.write("unrolling,%s,%d,%d\n" %
                        (loop.name, loop.line_num, params["unrolling"]))

  config_file.close()
  os.chdir("..")

def write_cacti_config(config_file, config_name, params):
  """ Writes CACTI 6.5+ config files to the provided file handle. """
  config_file.write("// Config: %s\n" % config_name)  # File comment
  config_file.write("-size (bytes) %d\n" % params["cache_size"])
  config_file.write("-associativity %d\n" % params["cache_assoc"])
  config_file.write("-read-write port %d\n" % params["rw_ports"])
  config_file.write("-cache type \"%s\"\n" % params["cache_type"])
  config_file.write("-block size (bytes) %d\n" % params["line_size"])
  config_file.write("-search port %d\n" % params["search_ports"])
  config_file.write("-output/input bus width %d\n" % params["io_bus_width"])
  config_file.write("-exclusive write port %d\n" % params["exw_ports"])

  # Default parameters
  config_file.write(
      "-Power Gating - \"false\"\n"
      "-Power Gating Performance Loss 0.01\n"
      "-exclusive read port 0\n"
      "-single ended read ports 0\n"
      "-UCA bank count 1\n"
      "-technology (u) 0.045\n"
      "-page size (bits) 8192 \n"
      "-burst length 8\n"
      "-internal prefetch width 8\n"
      "-Data array cell type - \"itrs-hp\"\n"
      "-Tag array cell type - \"itrs-hp\"\n"
      "-Tag array peripheral type - \"itrs-hp\"\n"
      "-hp Vdd (V) \"default\"\n"
      "-lstp Vdd (V) \"default\"\n"
      "-lop Vdd (V) \"default\"\n"
      "-DVS(V): 0.8 1.1 1.3 1.4 1.5\n"
      "-Long channel devices - \"true\"\n"
      "-operating temperature (K) 300\n"
      "-tag size (b) \"default\"\n"
      "-access mode (normal, sequential, fast) - \"normal\"\n"
      "-design objective (weight delay, dynamic power, leakage power, "
          "cycle time, area) 0:0:0:100:0\n"
      "-deviate (delay, dynamic power, leakage power, cycle time, area) "
          "20:100000:100000:100000:100000\n"
      "-NUCAdesign objective (weight delay, dynamic power, leakage power, "
          "cycle time, area) 100:100:0:0:100\n"
      "-NUCAdeviate (delay, dynamic power, leakage power, cycle time, area) "
          "10:10000:10000:10000:10000\n"
      "-Optimize ED or ED^2 (ED, ED^2, NONE): \"NONE\"\n"
      "-Cache model (NUCA, UCA)  - \"UCA\"\n"
      "-NUCA bank count 0\n"
      "-Wire signalling (fullswing, lowswing, default) - \"Global_30\"\n"
      "-Wire inside mat - \"semi-global\"\n"
      "-Wire outside mat - \"semi-global\"\n"
      "-Interconnect projection - \"conservative\"\n"
      "-Core count 1\n"
      "-Cache level (L2/L3) - \"L2\"\n"
      "-Add ECC - \"true\"\n"
      "-Print level (DETAILED, CONCISE) - \"DETAILED\"\n"<commit_msg>Remove the DVS configuration file from CACTI cfg files.<commit_after>#!/usr/bin/env python
import argparse
import ConfigParser
import getpass
import math
import os
import sys

from sweep_config import *

GEM5_CFG = "gem5.cfg"
ALADDIN_CFG = "aladdin.cfg"
CACTI_CACHE_CFG = "cacti_cache.cfg"
CACTI_TLB_CFG = "cacti_tlb.cfg"
CACTI_LQ_CFG = "cacti_lq.cfg"
CACTI_SQ_CFG = "cacti_sq.cfg"

# Taken from the template cfg file in <gem5_home>/configs/aladdin.
GEM5_DEFAULTS = {
  "cycle_time": 1,
  "memory_type": "cache",
  "spad_ports": 1,
  "tlb_hit_latency": 0,
  "tlb_miss_latency": 100,
  "tlb_page_size": 4096,
  "tlb_entries": 0,
  "tlb_max_outstanding_walks": 0,
  "tlb_assoc": 0,
  "tlb_bandwidth": 1,
  "is_perfect_tlb": False,
  "load_bandwidth": 1,
  "load_queue_size": 16,
  "store_bandwidth": 1,
  "store_queue_size": 16,
  "cache_assoc": 8,
  "cache_hit_latency": 1,
  "cache_line_sz" : 64,
  "dma_setup_latency" : 1,
  "max_dma_requests" : 16,
}

def generate_aladdin_config(benchmark, config_name, params):
  """ Write an Aladdin configuration file for the specified parameters.

  Args:
    benchmark: A benchmark description object.
    config_name: Name of the configuration.
    params: Configuration parameters. Must include the keys partition,
        unrolling, and pipelining.
  """
  os.chdir(config_name)
  config_file = open(ALADDIN_CFG, "wb")
  if "pipelining" in params:
    config_file.write("pipelining,%d\n" % params["pipelining"])

  if "partition" in params:
    for array in benchmark.arrays:
      if array.partition_type == PARTITION_CYCLIC:
        config_file.write("partition,cyclic,%s,%d,%d,%d\n" %
                          (array.name,
                           array.size*array.word_size,
                           array.word_size,
                           params["partition"]))
      elif array.partition_type == PARTITION_BLOCK:
        config_file.write("partition,block,%s,%d,%d,%d\n" %
                          (array.name,
                           array.size*array.word_size,
                           array.word_size,
                           params["partition"]))
      elif array.partition_type == PARTITION_COMPLETE:
        config_file.write("partition,complete,%s,%d\n" %
                          (array.name, array.size*array.word_size))
      else:
        print("Invalid array partitioning configuration for array %s." %
              array.name)
        exit(1)

  for loop in benchmark.loops:
    if (loop.trip_count == UNROLL_FLATTEN):
      config_file.write("flatten,%s,%d\n" % (loop.name, loop.line_num))
    elif (params["unrolling"] >= loop.trip_count):
      config_file.write("flatten,%s,%d\n" % (loop.name, loop.line_num))
    elif (loop.trip_count == UNROLL_ONE):
      config_file.write("unrolling,%s,%d,%d\n" %
                        (loop.name, loop.line_num, loop.trip_count))
    elif (loop.trip_count == ALWAYS_UNROLL or
          params["unrolling"] < loop.trip_count):
      # We only unroll if it was specified to always unroll or if the loop's
      # trip count is greater than the current unrolling factor.
      config_file.write("unrolling,%s,%d,%d\n" %
                        (loop.name, loop.line_num, params["unrolling"]))

  config_file.close()
  os.chdir("..")

def write_cacti_config(config_file, config_name, params):
  """ Writes CACTI 6.5+ config files to the provided file handle. """
  config_file.write("// Config: %s\n" % config_name)  # File comment
  config_file.write("-size (bytes) %d\n" % params["cache_size"])
  config_file.write("-associativity %d\n" % params["cache_assoc"])
  config_file.write("-read-write port %d\n" % params["rw_ports"])
  config_file.write("-cache type \"%s\"\n" % params["cache_type"])
  config_file.write("-block size (bytes) %d\n" % params["line_size"])
  config_file.write("-search port %d\n" % params["search_ports"])
  config_file.write("-output/input bus width %d\n" % params["io_bus_width"])
  config_file.write("-exclusive write port %d\n" % params["exw_ports"])

  # Default parameters
  config_file.write(
      "-Power Gating - \"false\"\n"
      "-Power Gating Performance Loss 0.01\n"
      "-exclusive read port 0\n"
      "-single ended read ports 0\n"
      "-UCA bank count 1\n"
      "-technology (u) 0.045\n"
      "-page size (bits) 8192 \n"
      "-burst length 8\n"
      "-internal prefetch width 8\n"
      "-Data array cell type - \"itrs-hp\"\n"
      "-Tag array cell type - \"itrs-hp\"\n"
      "-Tag array peripheral type - \"itrs-hp\"\n"
      "-hp Vdd (V) \"default\"\n"
      "-lstp Vdd (V) \"default\"\n"
      "-lop Vdd (V) \"default\"\n"
      "-Long channel devices - \"true\"\n"
      "-operating temperature (K) 300\n"
      "-tag size (b) \"default\"\n"
      "-access mode (normal, sequential, fast) - \"normal\"\n"
      "-design objective (weight delay, dynamic power, leakage power, "
          "cycle time, area) 0:0:0:100:0\n"
      "-deviate (delay, dynamic power, leakage power, cycle time, area) "
          "20:100000:100000:100000:100000\n"
      "-NUCAdesign objective (weight delay, dynamic power, leakage power, "
          "cycle time, area) 100:100:0:0:100\n"
      "-NUCAdeviate (delay, dynamic power, leakage power, cycle time, area) "
          "10:10000:10000:10000:10000\n"
      "-Optimize ED or ED^2 (ED, ED^2, NONE): \"NONE\"\n"
      "-Cache model (NUCA, UCA)  - \"UCA\"\n"
      "-NUCA bank count 0\n"
      "-Wire signalling (fullswing, lowswing, default) - \"Global_30\"\n"
      "-Wire inside mat - \"semi-global\"\n"
      "-Wire outside mat - \"semi-global\"\n"
      "-Interconnect projection - \"conservative\"\n"
      "-Core count 1\n"
      "-Cache level (L2/L3) - \"L2\"\n"
      "-Add ECC - \"true\"\n"
      "-Print level (DETAILED, CONCISE) - \"DETAILED\"\n"
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