<commit_before>/**
 *
 */

interface dfi_if #(
        C_ROW_WIDTH   = 16, // width of row address
        C_BANK_WIDTH  = 16, // width of bank address
        C_CKE_WIDTH   = 4 , // width of
        C_CK_WIDTH    = 1 ,
        C_CS_WIDTH    = 1 ,
        C_DQ_WIDTH    = 64,
        C_DQS_WIDTH   = 8 ,
        C_CS_PER_RANK = 8 ,
        C_DM_WIDTH    = 4 ,
        C_ODT_WIDTH   = 4
    );

    // DFI control interface
    logic [ C_ROW_WIDTH-1:0] dfi_address;
    logic [C_BANK_WIDTH-1:0] dfi_bank   ;
    logic [   C_CKE_WIDTH-1] dfi_ras_n  ;<commit_msg>Fixed single value range error in packed dimension<commit_after>/**
 * This file defines the DDR PHY interface signals for convenience.
 */

interface dfi_if #(
        C_ROW_WIDTH   = 16, // width of row address
        C_BANK_WIDTH  = 16, // width of bank address
        C_CKE_WIDTH   = 4 , // width of
        C_CK_WIDTH    = 1 ,
        C_CS_WIDTH    = 1 ,
        C_DQ_WIDTH    = 64,
        C_DQS_WIDTH   = 8 ,
        C_CS_PER_RANK = 8 ,
        C_DM_WIDTH    = 4 ,
        C_ODT_WIDTH   = 4
    );

    // DFI control interface
    logic [ C_ROW_WIDTH-1:0] dfi_address;
    logic [C_BANK_WIDTH-1:0] dfi_bank   ;
    logic [ C_CKE_WIDTH-1:0] dfi_ras_n  ;
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