<commit_before># FIXME
# FIXME 16B/cy bidirectional transfers between L2 and L3 are not (yet) supported by kerncraft
# FIXME performance counters might be wrong. This will only affect the Benchmark model
# FIXME bandwidth measurements need validataion
# FIXME
kerncraft version: 0.7.1  # which version of kerncraft was this file created for

model name: Intel(R) Xeon(R) Gold 6148 CPU @ 2.40GHz
model type: Intel Skylake SP processor
sockets: 2
cores per socket: 20
threads per core: 2
NUMA domains per socket: 1
cores per NUMA domain: 20
clock: 2.4 GHz
FLOPs per cycle:
  SP:
    total: 64
    FMA: 64
    ADD: 32
    MUL: 32
  DP:
    total: 32
    FMA: 32
    ADD: 16
    MUL: 16
micro-architecture: SKX
compiler:
  !!omap
  - icc: -O3 -fno-alias -xCORE-AVX512 -qopenmp
  - clang: -O3 -march=skylake-avx512 -D_POSIX_C_SOURCE=200112L -fopenmp
  - gcc: -O3 -march=skylake-avx512 -fopenmp
cacheline size: 64 B
overlapping model:
  ports: ["0", "0DV", "1", "2", "3", "4", "5", "6", "7"]
  performance counter metric:
          Max(UOPS_DISPATCHED_PORT_PORT_0:PMC[0-3],
          UOPS_DISPATCHED_PORT_PORT_1:PMC[0-3],
          UOPS_DISPATCHED_PORT_PORT_4:PMC[0-3],
          UOPS_DISPATCHED_PORT_PORT_5:PMC[0-3],
          UOPS_DISPATCHED_PORT_PORT_6:PMC[0-3],
          UOPS_DISPATCHED_PORT_PORT_7:PMC[0-3])
non-overlapping model:
  ports: ["2D", "3D"]
  performance counter metric:
    T_OL + T_L2 + T_L3 + T_MEM
memory hierarchy:
- level: L1
  # non-overlap upstream throughput is gathered from port assignment (non-overlapping model -> ports)
  performance counter metrics:
    accesses:  MEM_INST_RETIRED_ALL_LOADS:PMC[0-3]
    misses: L1D_REPLACEMENT:PMC[0-3]
    evicts: L2_TRANS_L1D_WB:PMC[0-3]
  cache per group:
    sets: 64
    ways: 8
    cl_size: 64
    replacement_policy: 'LRU'
    write_allocate: True
    write_back: True
    load_from: L2
    store_to: L2
  size per group: 32.00 kB
  groups: 20
  cores per group: 1
  threads per group: 2
- level: L2
  non-overlap upstream throughput: [64 B/cy, 'half-duplex']
  performance counter metrics:
    accesses: L1D_REPLACEMENT:PMC[0-3]
    misses: L2_LINES_IN_ALL:PMC[0-3]
    evicts: L2_TRANS_L2_WB:PMC[0-3]
  cache per group:
    sets: 1024
    ways: 16
    cl_size: 64
    replacement_policy: 'LRU'
    write_allocate: True
    write_back: True
    load_from: null  # L3 is a victim cache, thus unless a hit in L3, misses get forwarded to MEM
    victims_to: L3  # all victims, modified or not are passed onto L3
    store_to: L3
  size per group: 1.00 MB
  groups: 20
  cores per group: 1
  threads per group: 2
- level: L3
  non-overlap upstream throughput: [16 B/cy, 'full-duplex']
  performance counter metrics:
    accesses: L2_LINES_IN_ALL:PMC[0-3]
    # FIXME not all misses in L2 lead to loads from L3, only the hits do
    misses: (CAS_COUNT_RD:MBOX0C[01] + CAS_COUNT_RD:MBOX1C[01] +
             CAS_COUNT_RD:MBOX2C[01] + CAS_COUNT_RD:MBOX3C[01] +
             CAS_COUNT_RD:MBOX4C[01] + CAS_COUNT_RD:MBOX5C[01])
    evicts: (CAS_COUNT_WR:MBOX0C[01] + CAS_COUNT_WR:MBOX1C[01] +
             CAS_COUNT_WR:MBOX2C[01] + CAS_COUNT_WR:MBOX3C[01] +
             CAS_COUNT_WR:MBOX4C[01] + CAS_COUNT_WR:MBOX5C[01])
  cache per group:
    sets: 28672
    # TODO is actuall something else, but necessary to get to 16.5 MB
    ways: 16
    # TODO is actually 11, but pycachesim only supports powers of two
    cl_size: 64
    replacement_policy: 'LRU'
    write_allocate: False
    write_back: True
  size per group: 28 MB
  groups: 20
  cores per group: 20
  threads per group: 40
- level: MEM
  non-overlap upstream throughput: ['full socket memory bandwidth', 'half-duplex']<commit_msg>fxied Skylake L3 group count<commit_after># FIXME
# FIXME 16B/cy bidirectional transfers between L2 and L3 are not (yet) supported by kerncraft
# FIXME performance counters might be wrong. This will only affect the Benchmark model
# FIXME bandwidth measurements need validataion
# FIXME
kerncraft version: 0.7.1  # which version of kerncraft was this file created for

model name: Intel(R) Xeon(R) Gold 6148 CPU @ 2.40GHz
model type: Intel Skylake SP processor
sockets: 2
cores per socket: 20
threads per core: 2
NUMA domains per socket: 1
cores per NUMA domain: 20
clock: 2.4 GHz
FLOPs per cycle:
  SP:
    total: 64
    FMA: 64
    ADD: 32
    MUL: 32
  DP:
    total: 32
    FMA: 32
    ADD: 16
    MUL: 16
micro-architecture: SKX
compiler:
  !!omap
  - icc: -O3 -fno-alias -xCORE-AVX512 -qopenmp
  - clang: -O3 -march=skylake-avx512 -D_POSIX_C_SOURCE=200112L -fopenmp
  - gcc: -O3 -march=skylake-avx512 -fopenmp
cacheline size: 64 B
overlapping model:
  ports: ["0", "0DV", "1", "2", "3", "4", "5", "6", "7"]
  performance counter metric:
          Max(UOPS_DISPATCHED_PORT_PORT_0:PMC[0-3],
          UOPS_DISPATCHED_PORT_PORT_1:PMC[0-3],
          UOPS_DISPATCHED_PORT_PORT_4:PMC[0-3],
          UOPS_DISPATCHED_PORT_PORT_5:PMC[0-3],
          UOPS_DISPATCHED_PORT_PORT_6:PMC[0-3],
          UOPS_DISPATCHED_PORT_PORT_7:PMC[0-3])
non-overlapping model:
  ports: ["2D", "3D"]
  performance counter metric:
    T_OL + T_L2 + T_L3 + T_MEM
memory hierarchy:
- level: L1
  # non-overlap upstream throughput is gathered from port assignment (non-overlapping model -> ports)
  performance counter metrics:
    accesses:  MEM_INST_RETIRED_ALL_LOADS:PMC[0-3]
    misses: L1D_REPLACEMENT:PMC[0-3]
    evicts: L2_TRANS_L1D_WB:PMC[0-3]
  cache per group:
    sets: 64
    ways: 8
    cl_size: 64
    replacement_policy: 'LRU'
    write_allocate: True
    write_back: True
    load_from: L2
    store_to: L2
  size per group: 32.00 kB
  groups: 20
  cores per group: 1
  threads per group: 2
- level: L2
  non-overlap upstream throughput: [64 B/cy, 'half-duplex']
  performance counter metrics:
    accesses: L1D_REPLACEMENT:PMC[0-3]
    misses: L2_LINES_IN_ALL:PMC[0-3]
    evicts: L2_TRANS_L2_WB:PMC[0-3]
  cache per group:
    sets: 1024
    ways: 16
    cl_size: 64
    replacement_policy: 'LRU'
    write_allocate: True
    write_back: True
    load_from: null  # L3 is a victim cache, thus unless a hit in L3, misses get forwarded to MEM
    victims_to: L3  # all victims, modified or not are passed onto L3
    store_to: L3
  size per group: 1.00 MB
  groups: 20
  cores per group: 1
  threads per group: 2
- level: L3
  non-overlap upstream throughput: [16 B/cy, 'full-duplex']
  performance counter metrics:
    accesses: L2_LINES_IN_ALL:PMC[0-3]
    # FIXME not all misses in L2 lead to loads from L3, only the hits do
    misses: (CAS_COUNT_RD:MBOX0C[01] + CAS_COUNT_RD:MBOX1C[01] +
             CAS_COUNT_RD:MBOX2C[01] + CAS_COUNT_RD:MBOX3C[01] +
             CAS_COUNT_RD:MBOX4C[01] + CAS_COUNT_RD:MBOX5C[01])
    evicts: (CAS_COUNT_WR:MBOX0C[01] + CAS_COUNT_WR:MBOX1C[01] +
             CAS_COUNT_WR:MBOX2C[01] + CAS_COUNT_WR:MBOX3C[01] +
             CAS_COUNT_WR:MBOX4C[01] + CAS_COUNT_WR:MBOX5C[01])
  cache per group:
    sets: 28672
    # TODO is actuall something else, but necessary to get to 16.5 MB
    ways: 16
    # TODO is actually 11, but pycachesim only supports powers of two
    cl_size: 64
    replacement_policy: 'LRU'
    write_allocate: False
    write_back: True
  size per group: 28 MB
  groups: 1
  cores per group: 20
  threads per group: 40
- level: MEM
  non-overlap upstream throughput: ['full socket memory bandwidth', 'half-duplex']
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