<commit_before>Chip Design Glossary
===============================

## Chip Architecture

* [ADC](https://en.wikipedia.org/wiki/Analog-to-digital_converter): Analog to Digital Converter
* [AES](https://en.wikipedia.org/wiki/Advanced_Encryption_Standard): Advanced encryption standard
* [Adder](https://en.wikipedia.org/wiki/Adder_%28electronics%29): Circuit to add two numbers
* [ALU](https://en.wikipedia.org/wiki/Arithmetic_logic_unit): Arithmetic logic unit
* [Amdahl's Law](https://en.wikipedia.org/wiki/Amdahl%27s_law): Amdahl's law of diminishing returns for speeding up fixed workloads
* [Arbiter](https://en.wikipedia.org/wiki/Arbiter_%28electronics%29): Arbitrates between competing requesters
* [ASIC](https://en.wikipedia.org/wiki/Application-specific_integrated_circuit): Application specific integrated circuit.
* [Audio codec](https://en.wikipedia.org/wiki/Audio_codec): Device/program that compresses/decompresses digital audio
* [Boolean algebra](https://en.wikipedia.org/wiki/Boolean_algebra): Algebra in which variables are either true or false
* [BTB](https://en.wikipedia.org/wiki/Branch_target_predictor): Branch target buffer
* [Cache](https://en.wikipedia.org/wiki/Cache_%28computing%29): Local storage of program and/or data for future use.
* [Cache coherence](https://en.wikipedia.org/wiki/Cache_coherence): Consistency of shared data that is stored in multiple local caches. 
* [CAM](https://en.wikipedia.org/wiki/Content-addressable_memory): Content addressable memory
* [CISC](https://en.wikipedia.org/wiki/Complex_instruction_set_computing): Complex instruction set computing
* [Coprocessor](https://en.wikipedia.org/wiki/Coprocessor): A processor used to supplement operations of a primary (host) processor.
* [CPI](https://en.wikipedia.org/wiki/Cycles_per_instruction): Cycles per instruction
* [CPU](https://en.wikipedia.org/wiki/Central_processing_unit): Central processing unit
* [CRC](https://en.wikipedia.org/wiki/Cyclic_redundancy_check): Cyclic redundancy check
* [CSA](https://en.wikipedia.org/wiki/Carry-save_adder): Carry save adder 
* [DAC](https://en.wikipedia.org/wiki/Digital-to-analog_converter): Digital to Analog Converter
* [Distributed Computing](https://en.wikipedia.org/wiki/Distributed_computing): Computer with components working towards common goal with without strict coupling.
* [DLL](https://en.wikipedia.org/wiki/Delay-locked_loop): Delay locked loop
* [DMA](https://en.wikipedia.org/wiki/Direct_memory_access): Direct memory access
* [DDR](https://en.wikipedia.org/wiki/Double_data_rate) Double data rate
* [DDS](https://en.wikipedia.org/wiki/Direct_digital_synthesizer): Direct digital synthesis
* [DSM](https://en.wikipedia.org/wiki/Distributed_shared_memory): Distributed shared memory
* [DSP](https://en.wikipedia.org/wiki/Digital_signal_processor): Digital signal processor
* [ECC](https://en.wikipedia.org/wiki/ECC_memory): Error correcting code
* [Ethernet](https://en.wikipedia.org/wiki/Ethernet): Family of standard network technologies
* [Fault Tolerance](https://en.wikipedia.org/wiki/Fault_tolerance): The ability of a system to keep operating in the event of failure of one of its components. 
* [FRAM](https://en.wikipedia.org/wiki/Ferroelectric_RAM): Non-volatile RAM based on ferroelectric layer.
* [FPGA](https://en.wikipedia.org/wiki/Field-programmable_gate_array): Field-programmable gate array is a chip that can be reprogrammed "in the field".
* [FIFO](https://en.wikipedia.org/wiki/FIFO_%28computing_and_electronics%29): First in first out buffer
* [GPU](https://en.wikipedia.org/wiki/Graphics_processing_unit): Integrated circuit for accelerating the creation of graphics on a display.
* [DRAM](https://en.wikipedia.org/wiki/Dynamic_random-access_memory): Dynamic random-access semiconductor memory
* [Flash](https://en.wikipedia.org/wiki/Flash_memory): Non-volatile semiconductor memory
* [FFT](https://en.wikipedia.org/wiki/Fast_Fourier_transform): Fast Fourier transform
* [FPU](https://en.wikipedia.org/wiki/Floating_point): Floating point unit
* [GPIO](https://en.wikipedia.org/wiki/General-purpose_input/output): IO controllable at run time
* [Gray code](https://en.wikipedia.org/wiki/Gray_code): Binary system where successive values differ by one bit
* [HBM](https://en.wikipedia.org/wiki/High_Bandwidth_Memory): High bandwidth memory
* [I2C](https://en.wikipedia.org/wiki/I%C2%B2C): Multi-master 2 wire bus
* [LAN](https://en.wikipedia.org/wiki/Local_area_network): Local area network
* [LFSR](https://en.wikipedia.org/wiki/Linear_feedback_shift_register): Linear feedback shift register
* [LSB](https://en.wikipedia.org/wiki/Least_significant_bit): Least significant bit
* [LVDS](https://en.wikipedia.org/wiki/Low-voltage_differential_signaling): Low-voltage differential signaling (also TIA/EIA-644)
* [MII](https://en.wikipedia.org/wiki/Media-independent_interface): Media independent interface for PHY chips
* [MIMD](https://en.wikipedia.org/wiki/MIMD): Multiple instructions multiple data architecture
* [MMU](https://en.wikipedia.org/wiki/Memory_management_unit): Memory management unit
* [MSB](https://en.wikipedia.org/wiki/Most_significant_bit): Most significant bit
* [MUX](https://en.wikipedia.org/wiki/Multiplexer): Multiplexer
* [Multiplier](https://en.wikipedia.org/wiki/Binary_multiplier): Binary multiplier
* [NCO](https://en.wikipedia.org/wiki/Numerically_controlled_oscillator): Numerically controlled oscillator
* [NOC](https://en.wikipedia.org/wiki/Network_on_a_chip): Network on a chip
* [Parallel Computing](https://en.wikipedia.org/wiki/Parallel_computing): A type of computation where many operations are carried out simultanesouly. 
* [PCM](https://en.wikipedia.org/wiki/Phase-change_memory): Phase change memory
* [PCIe](https://en.wikipedia.org/wiki/PCI_Express): High Speed serial computer expansion bus
* [PIC](https://en.wikipedia.org/wiki/Programmable_Interrupt_Controller): Programmable interrupt controller
* [Priority Encoder](https://en.wikipedia.org/wiki/Priority_encoder): A circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs
* [PLL](https://en.wikipedia.org/wiki/Phase-locked_loop): Phase locked loop
* [PWM](https://en.wikipedia.org/wiki/Pulse-width_modulation): Pulse width modulation
* [Q](https://en.wikipedia.org/wiki/Q_%28number_format%29): Q fixed point number format
* [RAID](https://en.wikipedia.org/wiki/RAID): Redundant array of disks
* [Reconfigurable Computing](https://en.wikipedia.org/wiki/Reconfigurable_computing): Collection of customizable datapaths connected together by a fabric
* [RISC](https://en.wikipedia.org/wiki/Reduced_instruction_set_computing): Reduced instruction set computing
* [ROM](https://en.wikipedia.org/wiki/Read-only_memory): Read only memory (denser than RAM)
* [SBC](https://en.wikipedia.org/wiki/Single-board_computer): Single board computers
* [SDR](https://en.wikipedia.org/wiki/Software-defined_radio): Software defined radio
* [SERDES](https://en.wikipedia.org/wiki/SerDes): Serializer/deserializer
* [Shift Register](https://en.wikipedia.org/wiki/Shift_register): Set of registers that shifts bits one position at a time
* [SIMD](https://en.wikipedia.org/wiki/SIMD): Single instruction multiple data
* [Schmitt Trigger](https://en.wikipedia.org/wiki/Schmitt_trigger): Comparator circuit with hysteresis
* [SPI](https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus): Synchronous 4 wire master/slave interface
* [SRAM](https://en.wikipedia.org/wiki/Static_random-access_memory): Static random access semiconductor memory
* [TLB](https://en.wikipedia.org/wiki/Translation_lookaside_buffer): Translation lookaside buffer
* [UART](https://en.wikipedia.org/wiki/Universal_asynchronous_receiver/transmitter): Asynchronous 2 wire point to point interface<commit_msg>Added the definition of lookup table<commit_after>Chip Design Glossary
===============================

## Chip Architecture

* [ADC](https://en.wikipedia.org/wiki/Analog-to-digital_converter): Analog to Digital Converter
* [AES](https://en.wikipedia.org/wiki/Advanced_Encryption_Standard): Advanced encryption standard
* [Adder](https://en.wikipedia.org/wiki/Adder_%28electronics%29): Circuit to add two numbers
* [ALU](https://en.wikipedia.org/wiki/Arithmetic_logic_unit): Arithmetic logic unit
* [Amdahl's Law](https://en.wikipedia.org/wiki/Amdahl%27s_law): Amdahl's law of diminishing returns for speeding up fixed workloads
* [Arbiter](https://en.wikipedia.org/wiki/Arbiter_%28electronics%29): Arbitrates between competing requesters
* [ASIC](https://en.wikipedia.org/wiki/Application-specific_integrated_circuit): Application specific integrated circuit.
* [Audio codec](https://en.wikipedia.org/wiki/Audio_codec): Device/program that compresses/decompresses digital audio
* [Boolean algebra](https://en.wikipedia.org/wiki/Boolean_algebra): Algebra in which variables are either true or false
* [BTB](https://en.wikipedia.org/wiki/Branch_target_predictor): Branch target buffer
* [Cache](https://en.wikipedia.org/wiki/Cache_%28computing%29): Local storage of program and/or data for future use.
* [Cache coherence](https://en.wikipedia.org/wiki/Cache_coherence): Consistency of shared data that is stored in multiple local caches. 
* [CAM](https://en.wikipedia.org/wiki/Content-addressable_memory): Content addressable memory
* [CISC](https://en.wikipedia.org/wiki/Complex_instruction_set_computing): Complex instruction set computing
* [Coprocessor](https://en.wikipedia.org/wiki/Coprocessor): A processor used to supplement operations of a primary (host) processor.
* [CPI](https://en.wikipedia.org/wiki/Cycles_per_instruction): Cycles per instruction
* [CPU](https://en.wikipedia.org/wiki/Central_processing_unit): Central processing unit
* [CRC](https://en.wikipedia.org/wiki/Cyclic_redundancy_check): Cyclic redundancy check
* [CSA](https://en.wikipedia.org/wiki/Carry-save_adder): Carry save adder 
* [DAC](https://en.wikipedia.org/wiki/Digital-to-analog_converter): Digital to Analog Converter
* [Distributed Computing](https://en.wikipedia.org/wiki/Distributed_computing): Computer with components working towards common goal with without strict coupling.
* [DLL](https://en.wikipedia.org/wiki/Delay-locked_loop): Delay locked loop
* [DMA](https://en.wikipedia.org/wiki/Direct_memory_access): Direct memory access
* [DDR](https://en.wikipedia.org/wiki/Double_data_rate) Double data rate
* [DDS](https://en.wikipedia.org/wiki/Direct_digital_synthesizer): Direct digital synthesis
* [DSM](https://en.wikipedia.org/wiki/Distributed_shared_memory): Distributed shared memory
* [DSP](https://en.wikipedia.org/wiki/Digital_signal_processor): Digital signal processor
* [ECC](https://en.wikipedia.org/wiki/ECC_memory): Error correcting code
* [Ethernet](https://en.wikipedia.org/wiki/Ethernet): Family of standard network technologies
* [Fault Tolerance](https://en.wikipedia.org/wiki/Fault_tolerance): The ability of a system to keep operating in the event of failure of one of its components. 
* [FRAM](https://en.wikipedia.org/wiki/Ferroelectric_RAM): Non-volatile RAM based on ferroelectric layer.
* [FPGA](https://en.wikipedia.org/wiki/Field-programmable_gate_array): Field-programmable gate array is a chip that can be reprogrammed "in the field".
* [FIFO](https://en.wikipedia.org/wiki/FIFO_%28computing_and_electronics%29): First in first out buffer
* [GPU](https://en.wikipedia.org/wiki/Graphics_processing_unit): Integrated circuit for accelerating the creation of graphics on a display.
* [DRAM](https://en.wikipedia.org/wiki/Dynamic_random-access_memory): Dynamic random-access semiconductor memory
* [Flash](https://en.wikipedia.org/wiki/Flash_memory): Non-volatile semiconductor memory
* [FFT](https://en.wikipedia.org/wiki/Fast_Fourier_transform): Fast Fourier transform
* [FPU](https://en.wikipedia.org/wiki/Floating_point): Floating point unit
* [GPIO](https://en.wikipedia.org/wiki/General-purpose_input/output): IO controllable at run time
* [Gray code](https://en.wikipedia.org/wiki/Gray_code): Binary system where successive values differ by one bit
* [HBM](https://en.wikipedia.org/wiki/High_Bandwidth_Memory): High bandwidth memory
* [I2C](https://en.wikipedia.org/wiki/I%C2%B2C): Multi-master 2 wire bus
* [LAN](https://en.wikipedia.org/wiki/Local_area_network): Local area network
* [LFSR](https://en.wikipedia.org/wiki/Linear_feedback_shift_register): Linear feedback shift register
* [LSB](https://en.wikipedia.org/wiki/Least_significant_bit): Least significant bit
* [LUT] (https://en.wikipedia.org/wiki/Lookup_table): An array that replaces runtime computation with a simpler array indexing operation 
* [LVDS](https://en.wikipedia.org/wiki/Low-voltage_differential_signaling): Low-voltage differential signaling (also TIA/EIA-644)
* [MII](https://en.wikipedia.org/wiki/Media-independent_interface): Media independent interface for PHY chips
* [MIMD](https://en.wikipedia.org/wiki/MIMD): Multiple instructions multiple data architecture
* [MMU](https://en.wikipedia.org/wiki/Memory_management_unit): Memory management unit
* [MSB](https://en.wikipedia.org/wiki/Most_significant_bit): Most significant bit
* [MUX](https://en.wikipedia.org/wiki/Multiplexer): Multiplexer
* [Multiplier](https://en.wikipedia.org/wiki/Binary_multiplier): Binary multiplier
* [NCO](https://en.wikipedia.org/wiki/Numerically_controlled_oscillator): Numerically controlled oscillator
* [NOC](https://en.wikipedia.org/wiki/Network_on_a_chip): Network on a chip
* [Parallel Computing](https://en.wikipedia.org/wiki/Parallel_computing): A type of computation where many operations are carried out simultanesouly. 
* [PCM](https://en.wikipedia.org/wiki/Phase-change_memory): Phase change memory
* [PCIe](https://en.wikipedia.org/wiki/PCI_Express): High Speed serial computer expansion bus
* [PIC](https://en.wikipedia.org/wiki/Programmable_Interrupt_Controller): Programmable interrupt controller
* [Priority Encoder](https://en.wikipedia.org/wiki/Priority_encoder): A circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs
* [PLL](https://en.wikipedia.org/wiki/Phase-locked_loop): Phase locked loop
* [PWM](https://en.wikipedia.org/wiki/Pulse-width_modulation): Pulse width modulation
* [Q](https://en.wikipedia.org/wiki/Q_%28number_format%29): Q fixed point number format
* [RAID](https://en.wikipedia.org/wiki/RAID): Redundant array of disks
* [Reconfigurable Computing](https://en.wikipedia.org/wiki/Reconfigurable_computing): Collection of customizable datapaths connected together by a fabric
* [RISC](https://en.wikipedia.org/wiki/Reduced_instruction_set_computing): Reduced instruction set computing
* [ROM](https://en.wikipedia.org/wiki/Read-only_memory): Read only memory (denser than RAM)
* [SBC](https://en.wikipedia.org/wiki/Single-board_computer): Single board computers
* [SDR](https://en.wikipedia.org/wiki/Software-defined_radio): Software defined radio
* [SERDES](https://en.wikipedia.org/wiki/SerDes): Serializer/deserializer
* [Shift Register](https://en.wikipedia.org/wiki/Shift_register): Set of registers that shifts bits one position at a time
* [SIMD](https://en.wikipedia.org/wiki/SIMD): Single instruction multiple data
* [Schmitt Trigger](https://en.wikipedia.org/wiki/Schmitt_trigger): Comparator circuit with hysteresis
* [SPI](https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus): Synchronous 4 wire master/slave interface
* [SRAM](https://en.wikipedia.org/wiki/Static_random-access_memory): Static random access semiconductor memory
* [TLB](https://en.wikipedia.org/wiki/Translation_lookaside_buffer): Translation lookaside buffer
* [UART](https://en.wikipedia.org/wiki/Universal_asynchronous_receiver/transmitter): Asynchronous 2 wire point to point interface
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