<commit_before>/*
 * gomacro - A Go interpreter with Lisp-like macros
 *
 * Copyright (C) 2019 <NAME>
 *
 *     This Source Code Form is subject to the terms of the Mozilla Public
 *     License, v. 2.0. If a copy of the MPL was not distributed with this
 *     file, You can obtain one at http://mozilla.org/MPL/2.0/.
 *
 *
 * op3.go
 *
 *  Created on Jan 27, 2019
 *      Author <NAME>
 */

package arm64

// ============================================================================
// three-arg instruction

var op3vals = map[Op3]uint8{
	AND3: 0x0A,
	ADD3: 0x0B,
	ADC3: 0x1A, // add with carry
	OR3:  0x2A,
	XOR3: 0x4A,
	SUB3: 0x4B,
	SBB3: 0x5A, // subtract with borrow
}

// return 32bit value used to encode operation on Reg,Reg,Reg
func op3val(op Op3) uint32 {
	var val uint32
	switch op {
	case SHL3:
		val = 0x1AC02000
	case SHR3:
		// logical i.e. zero-extended right shift is 0x1AC02400
		// arithmetic i.e. sign-extended right shift is 0x1AC02800
		val = 0x1AC02400
	case MUL3:
		// 0x1B007C00 because MUL3 a,b,c is an alias for MADD4 xzr,a,b,c
		val = 0x1B007C00
	case DIV3:
		// unsigned division is 0x1AC00800
		// signed division is 0x1AC00C00
		val = 0x1AC00800
	case REM3:
		errorf("internal error, operation %v needs to be implemented as {s|u}div followed by msub", op)
	default:
		val = uint32(op3vals[op]) << 24
		if val == 0 {
			errorf("unknown Op2 instruction: %v", op)
		}
	}
	return val
}

// return 32bit value used to encode operation on Reg,Const,Reg
func immval(op Op3) uint32 {
	switch op {
	case AND3:
		return 0x12 << 24
	case ADD3:
		return 0x11 << 24
	case SHL3, SHR3:
		// immediate constant is encoded differently
		return 0x53 << 24
	case OR3:
		return 0x32 << 24
	case XOR3:
		return 0x52 << 24
	case SUB3:
		return 0x51 << 24
	default:
		errorf("cannot encode Op2 instruction %v with immediate constant", op)
		return 0
	}
}

// ============================================================================
func (arch Arm64) Op3(asm *Asm, op Op3, a Arg, b Arg, dst Arg) *Asm {
	arch.op3(asm, op, a, b, dst)
	return asm
}

func (arch Arm64) op3(asm *Asm, op Op3, a Arg, b Arg, dst Arg) Arm64 {
	// validate kinds
	assert(a.Kind() == dst.Kind())
	switch op {
	case SHL3, SHR3:
		assert(!b.Kind().Signed())
	case GETIDX, SETIDX:
		errorf("unimplemented: %v %v,%v,%v", op, op, a, b, dst)<commit_msg>fix call to errorf() in jit/arm64/op3.go<commit_after>/*
 * gomacro - A Go interpreter with Lisp-like macros
 *
 * Copyright (C) 2019 <NAME>
 *
 *     This Source Code Form is subject to the terms of the Mozilla Public
 *     License, v. 2.0. If a copy of the MPL was not distributed with this
 *     file, You can obtain one at http://mozilla.org/MPL/2.0/.
 *
 *
 * op3.go
 *
 *  Created on Jan 27, 2019
 *      Author <NAME>
 */

package arm64

// ============================================================================
// three-arg instruction

var op3vals = map[Op3]uint8{
	AND3: 0x0A,
	ADD3: 0x0B,
	ADC3: 0x1A, // add with carry
	OR3:  0x2A,
	XOR3: 0x4A,
	SUB3: 0x4B,
	SBB3: 0x5A, // subtract with borrow
}

// return 32bit value used to encode operation on Reg,Reg,Reg
func op3val(op Op3) uint32 {
	var val uint32
	switch op {
	case SHL3:
		val = 0x1AC02000
	case SHR3:
		// logical i.e. zero-extended right shift is 0x1AC02400
		// arithmetic i.e. sign-extended right shift is 0x1AC02800
		val = 0x1AC02400
	case MUL3:
		// 0x1B007C00 because MUL3 a,b,c is an alias for MADD4 xzr,a,b,c
		val = 0x1B007C00
	case DIV3:
		// unsigned division is 0x1AC00800
		// signed division is 0x1AC00C00
		val = 0x1AC00800
	case REM3:
		errorf("internal error, operation %v needs to be implemented as {s|u}div followed by msub", op)
	default:
		val = uint32(op3vals[op]) << 24
		if val == 0 {
			errorf("unknown Op2 instruction: %v", op)
		}
	}
	return val
}

// return 32bit value used to encode operation on Reg,Const,Reg
func immval(op Op3) uint32 {
	switch op {
	case AND3:
		return 0x12 << 24
	case ADD3:
		return 0x11 << 24
	case SHL3, SHR3:
		// immediate constant is encoded differently
		return 0x53 << 24
	case OR3:
		return 0x32 << 24
	case XOR3:
		return 0x52 << 24
	case SUB3:
		return 0x51 << 24
	default:
		errorf("cannot encode Op2 instruction %v with immediate constant", op)
		return 0
	}
}

// ============================================================================
func (arch Arm64) Op3(asm *Asm, op Op3, a Arg, b Arg, dst Arg) *Asm {
	arch.op3(asm, op, a, b, dst)
	return asm
}

func (arch Arm64) op3(asm *Asm, op Op3, a Arg, b Arg, dst Arg) Arm64 {
	// validate kinds
	assert(a.Kind() == dst.Kind())
	switch op {
	case SHL3, SHR3:
		assert(!b.Kind().Signed())
	case GETIDX, SETIDX:
		errorf("unimplemented: %v %v,%v,%v", op, a, b, dst)
{'fraction_non_alphanumeric': 0.17294994675186368, 'fraction_numerical': 0.07816826411075613, 'mean_word_length': 3.348148148148148, 'pattern_counts': {'":': 0, '<': 35, '<?xml version=': 0, '>': 7, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '2707765', 'n_tokens_mistral': 2064, 'n_tokens_neox': 1773, 'n_words': 595}