<commit_before>  <!-- set: ai sw=1 ts=1 sta et -->
  <!-- A diagram for the iCE40 PLB "Logic Cell" is shown in;
        http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/iCE/iCE40LPHXFamilyDataSheet.pdf
        Architecture iCE40 LP/HX Family Data Sheet
         * Figure 2-2. PLB Block Diagram

       It is 8 x (SB_CARRY + SB_LUT4 + FF)
    -->
  <pb_type name="PLB" xmlns:xi="http://www.w3.org/2001/XInclude">
   <!-- SB_LUT4 inputs -->
   <input  name="I0" num_pins="4" equivalent="false"/>
   <input  name="I1" num_pins="4" equivalent="false"/>
   <input  name="I2" num_pins="4" equivalent="false"/>
   <input  name="I3" num_pins="4" equivalent="false"/>
   <input  name="I4" num_pins="4" equivalent="false"/>
   <input  name="I5" num_pins="4" equivalent="false"/>
   <input  name="I6" num_pins="4" equivalent="false"/>
   <input  name="I7" num_pins="4" equivalent="false"/>
   <!-- D Flipflop outputs -->
   <output  name="O0" num_pins="1" equivalent="false"/>
   <output  name="O1" num_pins="1" equivalent="false"/>
   <output  name="O2" num_pins="1" equivalent="false"/>
   <output  name="O3" num_pins="1" equivalent="false"/>
   <output  name="O4" num_pins="1" equivalent="false"/>
   <output  name="O5" num_pins="1" equivalent="false"/>
   <output  name="O6" num_pins="1" equivalent="false"/>
   <output  name="O7" num_pins="1" equivalent="false"/>

   <!-- D Flipflop controls -->
   <clock  name="CLK" num_pins="1"/>
   <input name="EN" num_pins="1" equivalent="false"/>
   <input name="SR" num_pins="1" equivalent="false"/>

   <!-- Carry chain -->
   <input name="FCIN"  num_pins="1" equivalent="false"/>
   <output name="FCOUT" num_pins="1" equivalent="false"/>

   <!-- A PLB contains the same 'cell' repeated 8 times. -->
   <pb_type name="PLB_CELL" num_pb="8">
    <!-- Data -->
    <input  name="I" num_pins="4" equivalent="false"/>
    <output name="O" num_pins="1" equivalent="false"/>

    <!-- Flipflop controls -->
    <clock name="CLK" num_pins="1" />
    <input name="EN"  num_pins="1" equivalent="false"/>
    <input name="SR"  num_pins="1" equivalent="false"/>

    <!-- Fast carry -->
    <input name="FCIN"  num_pins="1" equivalent="false"/>
    <output name="FCOUT" num_pins="1" equivalent="false"/>

    <!-- 4 input LUT -->
    <xi:include href="../../primatives/sb_lut/pb_type.xml"/>

    <!-- D FlipFlop -->
    <xi:include href="../../primatives/sb_ff/pb_type.xml"/>

    <!-- SB_CARRY -->
    <xi:include href="../../primatives/sb_carry/pb_type.xml"/>

    <!-- Connect the PLB_CELL together -->
    <interconnect>
     <complete name="I0" input="PLB_CELL.I[0:0]" output="LUT.I[0:0]"/>
     <complete name="I1" input="PLB_CELL.I[1:1]" output="LUT.I[1:1] SB_CARRY.I0"/>
     <complete name="I2" input="PLB_CELL.I[2:2]" output="LUT.I[2:2] SB_CARRY.I1"/>
     <mux      name="I3" input="PLB_CELL.I[3:3] PLB_CELL.FCIN" output="LUT.I[3:3]"/>
     <mux      name="O"  input="LUT.O SB_FF.Q"   output="PLB_CELL.O"/>

     <direct   name="FF_D"  input="LUT.O"        output="SB_FF.D">
      <!--
       <pack_pattern name="LUT2FF" in_port="LUT.O" out_port="SB_FF.D"/>
      -->
     </direct>
     <direct name="FF_CK" input="PLB_CELL.CLK" output="SB_FF.C"/>
     <direct name="FF_EN" input="PLB_CELL.EN"  output="SB_FF.E"/>
     <direct name="FF_SR" input="PLB_CELL.SR"  output="SB_FF.S"/>

     <direct name="FCIN"  input="PLB_CELL.FCIN"  output="SB_CARRY.CI"/>
     <direct name="FCOUT" input="SB_CARRY.CO"    output="PLB_CELL.FCOUT"/>

     <!-- Find LUT+FF pairs in netlist -->
    </interconnect>
   </pb_type>

   <interconnect>
    <!-- Inputs -->
    <direct name="I0" input="PLB.I0" output="PLB_CELL[0:0].I" />
    <direct name="I1" input="PLB.I1" output="PLB_CELL[1:1].I" />
    <direct name="I2" input="PLB.I2" output="PLB_CELL[2:2].I" />
    <direct name="I3" input="PLB.I3" output="PLB_CELL[3:3].I" />
    <direct name="I4" input="PLB.I4" output="PLB_CELL[4:4].I" />
    <direct name="I5" input="PLB.I5" output="PLB_CELL[5:5].I" />
    <direct name="I6" input="PLB.I6" output="PLB_CELL[6:6].I" />
    <direct name="I7" input="PLB.I7" output="PLB_CELL[7:7].I" />
    <!-- Outputs -->
    <direct name="O0" input="PLB_CELL[0:0].O" output="PLB.O0" />
    <direct name="O1" input="PLB_CELL[1:1].O" output="PLB.O1" />
    <direct name="O2" input="PLB_CELL[2:2].O" output="PLB.O2" />
    <direct name="O3" input="PLB_CELL[3:3].O" output="PLB.O3" />
    <direct name="O4" input="PLB_CELL[4:4].O" output="PLB.O4" />
    <direct name="O5" input="PLB_CELL[5:5].O" output="PLB.O5" />
    <direct name="O6" input="PLB_CELL[6:6].O" output="PLB.O6" />
    <direct name="O7" input="PLB_CELL[7:7].O" output="PLB.O7" />
    <!-- All flipflops inside a PLB share the CLK, SR & CE signal -->
    <complete name="CLK" input="PLB.CLK" output="PLB_CELL[7:0].CLK" />
    <!-- <mux name="SR" input="GND PLB.SR" output="PLB_CELL[7:0].SR" /> -->
    <complete name="SR" input="PLB.SR" output="PLB_CELL[7:0].SR" />
    <!-- <mux name="EN" input="VCC PLB.EN" output="PLB_CELL[7:0].EN" /> -->
    <complete name="EN" input="PLB.EN" output="PLB_CELL[7:0].EN" />

    <!-- Carry chain -->
    <direct name="FCOUT" input="PLB_CELL[0:0].FCOUT" output="PLB.FCOUT"/>
    <direct name="FCC0"  input="PLB_CELL[1:1].FCOUT" output="PLB_CELL[0:0].FCIN"/>
    <direct name="FCC1"  input="PLB_CELL[2:2].FCOUT" output="PLB_CELL[1:1].FCIN"/>
    <direct name="FCC2"  input="PLB_CELL[3:3].FCOUT" output="PLB_CELL[2:2].FCIN"/>
    <direct name="FCC3"  input="PLB_CELL[4:4].FCOUT" output="PLB_CELL[3:3].FCIN"/>
    <direct name="FCC4"  input="PLB_CELL[5:5].FCOUT" output="PLB_CELL[4:4].FCIN"/>
    <direct name="FCC5"  input="PLB_CELL[6:6].FCOUT" output="PLB_CELL[5:5].FCIN"/>
    <direct name="FCIN"  input="PLB.FCIN"            output="PLB_CELL[6:6].FCIN"/>
   </interconnect>

   <fc default_in_type="frac" default_in_val="0.0" default_out_type="frac" default_out_val="0.0">
    <!-- Connect all the ports to 2 local tracks -->
    <fc_override fc_type="abs" fc_val="2" port_name="I0" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="I1" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="I2" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="I3" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="I4" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="I5" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="I6" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="I7" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="O0" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="O1" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="O2" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="O3" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="O4" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="O5" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="O6" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="O7" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="EN" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="SR" segment_name="local"/>
    <fc_override fc_type="abs" fc_val="2" port_name="CLK" segment_name="local"/>

    <!-- Carry chain doesn't connect to the interconnect -->
    <fc_override fc_type="frac" fc_val="0" port_name="PLB.FCOUT"/>
    <fc_override fc_type="frac" fc_val="0" port_name="PLB.FCIN"/>
   </fc>

   <pinlocations pattern="custom"><commit_msg>ice40: Adding pack-pattern for carry-chain.<commit_after>  <!-- set: ai sw=1 ts=1 sta et -->
  <!-- A diagram for the iCE40 PLB "Logic Cell" is shown in;
        http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/iCE/iCE40LPHXFamilyDataSheet.pdf
        Architecture iCE40 LP/HX Family Data Sheet
         * Figure 2-2. PLB Block Diagram

       It is 8 x (SB_CARRY + SB_LUT4 + FF)
    -->
  <pb_type name="PLB" xmlns:xi="http://www.w3.org/2001/XInclude">
   <!-- SB_LUT4 inputs -->
   <input  name="I0" num_pins="4" equivalent="false"/>
   <input  name="I1" num_pins="4" equivalent="false"/>
   <input  name="I2" num_pins="4" equivalent="false"/>
   <input  name="I3" num_pins="4" equivalent="false"/>
   <input  name="I4" num_pins="4" equivalent="false"/>
   <input  name="I5" num_pins="4" equivalent="false"/>
   <input  name="I6" num_pins="4" equivalent="false"/>
   <input  name="I7" num_pins="4" equivalent="false"/>
   <!-- D Flipflop outputs -->
   <output  name="O0" num_pins="1" equivalent="false"/>
   <output  name="O1" num_pins="1" equivalent="false"/>
   <output  name="O2" num_pins="1" equivalent="false"/>
   <output  name="O3" num_pins="1" equivalent="false"/>
   <output  name="O4" num_pins="1" equivalent="false"/>
   <output  name="O5" num_pins="1" equivalent="false"/>
   <output  name="O6" num_pins="1" equivalent="false"/>
   <output  name="O7" num_pins="1" equivalent="false"/>

   <!-- D Flipflop controls -->
   <clock  name="CLK" num_pins="1"/>
   <input name="EN" num_pins="1" equivalent="false"/>
   <input name="SR" num_pins="1" equivalent="false"/>

   <!-- Carry chain -->
   <input name="FCIN"  num_pins="1" equivalent="false"/>
   <output name="FCOUT" num_pins="1" equivalent="false"/>

   <!-- A PLB contains the same 'cell' repeated 8 times. -->
   <pb_type name="PLB_CELL" num_pb="8">
    <!-- Data -->
    <input  name="I" num_pins="4" equivalent="false"/>
    <output name="O" num_pins="1" equivalent="false"/>

    <!-- Flipflop controls -->
    <clock name="CLK" num_pins="1" />
    <input name="EN"  num_pins="1" equivalent="false"/>
    <input name="SR"  num_pins="1" equivalent="false"/>

    <!-- Fast carry -->
    <input name="FCIN"  num_pins="1" equivalent="false"/>
    <output name="FCOUT" num_pins="1" equivalent="false"/>

    <!-- 4 input LUT -->
    <xi:include href="../../primatives/sb_lut/pb_type.xml"/>

    <!-- D FlipFlop -->
    <xi:include href="../../primatives/sb_ff/pb_type.xml"/>

    <!-- SB_CARRY -->
    <xi:include href="../../primatives/sb_carry/pb_type.xml"/>

    <!-- Connect the PLB_CELL together -->
    <interconnect>
     <complete name="I0" input="PLB_CELL.I[0:0]" output="LUT.I[0:0]"/>
     <complete name="I1" input="PLB_CELL.I[1:1]" output="LUT.I[1:1] SB_CARRY.I0">
     </complete>
     <complete name="I2" input="PLB_CELL.I[2:2]" output="LUT.I[2:2] SB_CARRY.I1">
     </complete>
     <mux      name="I3" input="PLB_CELL.I[3:3] PLB_CELL.FCIN" output="LUT.I[3:3]">
     </mux>
     <mux      name="O"  input="LUT.O SB_FF.Q"   output="PLB_CELL.O">
     </mux>

     <direct   name="FF_D"  input="LUT.O"        output="SB_FF.D">
      <!--
       <pack_pattern name="LUT2FF" in_port="LUT.O" out_port="SB_FF.D"/>
      -->
     </direct>
     <direct name="FF_CK" input="PLB_CELL.CLK" output="SB_FF.C"/>
     <direct name="FF_EN" input="PLB_CELL.EN"  output="SB_FF.E"/>
     <direct name="FF_SR" input="PLB_CELL.SR"  output="SB_FF.S"/>

     <direct name="FCIN"  input="PLB_CELL.FCIN"  output="SB_CARRY.CI">
      <pack_pattern name="CARRYCHAIN" in_port="PLB_CELL.FCIN" out_port="SB_CARRY.CI"/>
     </direct>
     <direct name="FCOUT" input="SB_CARRY.CO"    output="PLB_CELL.FCOUT">
      <pack_pattern name="CARRYCHAIN" in_port="SB_CARRY.CO" out_port="PLB_CELL.FCOUT"/>
     </direct>

     <!-- Find LUT+FF pairs in netlist -->
    </interconnect>
   </pb_type>

   <interconnect>
    <!-- Inputs -->
    <direct name="I0" input="PLB.I0" output="PLB_CELL[0:0].I" />
    <direct name="I1" input="PLB.I1" output="PLB_CELL[1:1].I" />
    <direct name="I2" input="PLB.I2" output="PLB_CELL[2:2].I" />
    <direct name="I3" input="PLB.I3" output="PLB_CELL[3:3].I" />
    <direct name="I4" input="PLB.I4" output="PLB_CELL[4:4].I" />
    <direct name="I5" input="PLB.I5" output="PLB_CELL[5:5].I" />
    <direct name="I6" input="PLB.I6" output="PLB_CELL[6:6].I" />
    <direct name="I7" input="PLB.I7" output="PLB_CELL[7:7].I" />
    <!-- Outputs -->
    <direct name="O0" input="PLB_CELL[0:0].O" output="PLB.O0" />
    <direct name="O1" input="PLB_CELL[1:1].O" output="PLB.O1" />
    <direct name="O2" input="PLB_CELL[2:2].O" output="PLB.O2" />
    <direct name="O3" input="PLB_CELL[3:3].O" output="PLB.O3" />
    <direct name="O4" input="PLB_CELL[4:4].O" output="PLB.O4" />
    <direct name="O5" input="PLB_CELL[5:5].O" output="PLB.O5" />
    <direct name="O6" input="PLB_CELL[6:6].O" output="PLB.O6" />
    <direct name="O7" input="PLB_CELL[7:7].O" output="PLB.O7" />
    <!-- All flipflops inside a PLB share the CLK, SR & CE signal -->
    <complete name="CLK" input="PLB.CLK" output="PLB_CELL[7:0].CLK" />
    <!-- <mux name="SR" input="GND PLB.SR" output="PLB_CELL[7:0].SR" /> -->
    <complete name="SR" input="PLB.SR" output="PLB_CELL[7:0].SR" />
    <!-- <mux name="EN" input="VCC PLB.EN" output="PLB_CELL[7:0].EN" /> -->
    <complete name="EN" input="PLB.EN" output="PLB_CELL[7:0].EN" />

    <!-- Carry chain -->
    <direct name="FCOUT" input="PLB_CELL[0:0].FCOUT" output="PLB.FCOUT">
      <pack_pattern name="CARRYCHAIN" in_port="PLB_CELL[0:0].FCOUT" out_port="PLB.FCOUT"/>
    </direct>
    <direct name="FCC0"  input="PLB_CELL[1:1].FCOUT" output="PLB_CELL[0:0].FCIN">
      <pack_pattern name="CARRYCHAIN" in_port="PLB_CELL[1:1].FCOUT" out_port="PLB_CELL[0:0].FCIN"/>
    </direct>
    <direct name="FCC1"  input="PLB_CELL[2:2].FCOUT" output="PLB_CELL[1:1].FCIN">
      <pack_pattern name="CARRYCHAIN" in_port="PLB_CELL[2:2].FCOUT" out_port="PLB_CELL[1:1].FCIN"/>
    </direct>
    <direct name="FCC2"  input="PLB_CELL[3:3].FCOUT" output="PLB_CELL[2:2].FCIN">
      <pack_pattern name="CARRYCHAIN" in_port="PLB_CELL[3:3].FCOUT" out_port="PLB_CELL[2:2].FCIN"/>
    </direct>
    <direct name="FCC3"  input="PLB_CELL[4:4].FCOUT" output="PLB_CELL[3:3].FCIN">
      <pack_pattern name="CARRYCHAIN" in_port="PLB_CELL[4:4].FCOUT" out_port="PLB_CELL[3:3].FCIN"/>
    </direct>
    <direct name="FCC4"  input="PLB_CELL[5:5].FCOUT" output="PLB_CELL[4:4].FCIN">
      <pack_pattern name="CARRYCHAIN" in_port="PLB_CELL[5:5].FCOUT" out_port="PLB_CELL[4:4].FCIN"/>
    </direct>
    <direct name="FCC5"  input="PLB_CELL[6:6].FCOUT" output="PLB_CELL[5:5].FCIN">
      <pack_pattern name="CARRYCHAIN" in_port="PLB_CELL[6:6].FCOUT" out_port="PLB_CELL[5:5].FCIN"/>
    </direct>
    <direct name="FCIN"  input="PLB.FCIN"            output="PLB_CELL[6:6].FCIN">
      <pack_pattern name="CARRYCHAIN" in_port="PLB.FCIN"            out_port="PLB_CELL[6:6].FCIN"/>
    </direct>
   </interconnect>

   <fc default_in_type="frac" default_in_val="0.0" default_out_type="frac" default_out_val="0.0">
    <!-- Connect all the ports to 2 local tracks -->
    <fc_override fc_type="abs" fc_val="2" port_name="I0"  segment_name="local" />
    <fc_override fc_type="abs" fc_val="2" port_name="I1"  segment_name="local" />
    <fc_override fc_type="abs" fc_val="2" port_name="I2"  segment_name="local" />
    <fc_override fc_type="abs" fc_val="2" port_name="I3"  segment_name="local" />
    <fc_override fc_type="abs" fc_val="2" port_name="I4"  segment_name="local" />
    <fc_override fc_type="abs" fc_val="2" port_name="I5"  segment_name="local" />
    <fc_override fc_type="abs" fc_val="2" port_name="I6"  segment_name="local" />
    <fc_override fc_type="abs" fc_val="2" port_name="I7"  segment_name="local" />
    <fc_override fc_type="abs" fc_val="2" port_name="O0"  segment_name="local" />
    <fc_override fc_type="abs" fc_val="2" port_name="O1"  segment_name="local" />
    <fc_override fc_type="abs" fc_val="2" port_name="O2"  segment_name="local" />
    <fc_override fc_type="abs" fc_val="2" port_name="O3"  segment_name="local" />
    <fc_override fc_type="abs" fc_val="2" port_name="O4"  segment_name="local" />
    <fc_override fc_type="abs" fc_val="2" port_name="O5"  segment_name="local" />
    <fc_override fc_type="abs" fc_val="2" port_name="O6"  segment_name="local" />
    <fc_override fc_type="abs" fc_val="2" port_name="O7"  segment_name="local" />
    <fc_override fc_type="abs" fc_val="2" port_name="EN"  segment_name="local" />
    <fc_override fc_type="abs" fc_val="2" port_name="SR"  segment_name="local" />
    <fc_override fc_type="abs" fc_val="2" port_name="CLK" segment_name="local" />

    <!-- Carry chain doesn't connect to the interconnect -->
    <fc_override fc_type="frac" fc_val="0" port_name="PLB.FCOUT"/>
    <fc_override fc_type="frac" fc_val="0" port_name="PLB.FCIN"/>
   </fc>

   <pinlocations pattern="custom">
{'fraction_non_alphanumeric': 0.21284006966548555, 'fraction_numerical': 0.030388565251336257, 'mean_word_length': 4.006614552014431, 'pattern_counts': {'":': 0, '<': 283, '<?xml version=': 0, '>': 283, 'https://': 0, 'lorem ipsum': 0, 'www.': 4, 'xml': 8}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '5777870', 'n_tokens_mistral': 7061, 'n_tokens_neox': 6857, 'n_words': 1087}