<commit_before>/****************************************************************************
**
** Copyright (C) 2019 <NAME> <<EMAIL>>
** Contact: http://www.qt.io/licensing
**
** This file is part of Qbs.
**
** Commercial License Usage
** Licensees holding valid commercial Qt licenses may use this file in
** accordance with the commercial license agreement provided with the
** Software or, alternatively, in accordance with the terms contained in
** a written agreement between you and The Qt Company. For licensing terms and
** conditions see http://www.qt.io/terms-conditions. For further information
** use the contact form at http://www.qt.io/contact-us.
**
** GNU Lesser General Public License Usage
** Alternatively, this file may be used under the terms of the GNU Lesser
** General Public License version 2.1 or version 3 as published by the Free
** Software Foundation and appearing in the file LICENSE.LGPLv21 and
** LICENSE.LGPLv3 included in the packaging of this file.  Please review the
** following information to ensure the GNU Lesser General Public License
** requirements will be met: https://www.gnu.org/licenses/lgpl.html and
** http://www.gnu.org/licenses/old-licenses/lgpl-2.1.html.
**
** In addition, as a special exception, The Qt Company gives you certain additional
** rights.  These rights are described in The Qt Company LGPL Exception
** version 1.1, included in the file LGPL_EXCEPTION.txt in this package.
**
****************************************************************************/

#include "armgeneralsettingsgroup_v8.h"

#include "../../iarewutils.h"

#include <QtCore/qdir.h>

namespace qbs {
namespace v8 {

constexpr int kGeneralArchiveVersion = 3;
constexpr int kGeneralDataVersion = 30;

namespace ArmGeneral {

struct CpuCoreEntry final
{
    enum CpuCoreCode { Arm7tdmi = 0,
                       Arm7tdmis = 1,
                       Arm710t = 2,
                       Arm720t = 3,
                       Arm740t = 4,
                       Arm7ejs = 5,
                       Arm9tdmi = 6,
                       Arm920t = 7,
                       Arm922t = 8,
                       Arm940t = 9,
                       Arm9e = 10,
                       Arm9es = 11,
                       Arm926ejs = 12,
                       Arm946es = 13,
                       Arm966es = 14,
                       Arm968es = 15,
                       Arm10e = 16,
                       Arm1020e = 17,
                       Arm1022e = 18,
                       Arm1026ejs = 19,
                       Arm1136j = 20,
                       Arm1136js = 21,
                       Arm1176j = 24,
                       Arm1176js = 25,
                       Xscale = 32,
                       XscaleIr7 = 33,
                       CortexM0 = 34,
                       CortexM0Plus = 35,
                       CortexM1 = 36,
                       CortexMs1 = 37,
                       CortexM3 = 38,
                       CortexM4 = 39,
                       CortexM7 = 41,
                       CortexR4 = 42,
                       CortexR5 = 44,
                       CortexR7 = 46,
                       CortexR8 = 48,
                       CortexR52 = 49,
                       CortexA5 = 50,
                       CortexA7 = 52,
                       CortexA8 = 53,
                       CortexA9 = 54,
                       CortexA15 = 55,
                       CortexA17 = 56,
                       CortexM23 = 58,
                       CortexM33 = 59 };

    CpuCoreCode coreCode = Arm7tdmi;
    QByteArray targetFlag;
};

// Dictionary of known ARM CPU cores and its compiler options.
static const CpuCoreEntry cpusDict[] = {
    {CpuCoreEntry::Arm7tdmi, "arm7tdmi"}, // same as 'sc100'
    {CpuCoreEntry::Arm7tdmis, "arm7tdmi-s"},
    {CpuCoreEntry::Arm710t, "arm710t"},
    {CpuCoreEntry::Arm720t, "arm720t"},
    {CpuCoreEntry::Arm740t, "arm740t"},
    {CpuCoreEntry::Arm7ejs, "arm7ej-s"},
    {CpuCoreEntry::Arm9tdmi, "arm9tdmi"},
    {CpuCoreEntry::Arm920t, "arm920t"},
    {CpuCoreEntry::Arm922t, "arm922t"},
    {CpuCoreEntry::Arm940t, "arm940t"},
    {CpuCoreEntry::Arm9e, "arm9e"},
    {CpuCoreEntry::Arm9es, "arm9e-s"},
    {CpuCoreEntry::Arm926ejs, "arm926ej-s"},
    {CpuCoreEntry::Arm946es, "arm946e-s"},
    {CpuCoreEntry::Arm966es, "arm966e-s"},
    {CpuCoreEntry::Arm968es, "arm968e-s"},
    {CpuCoreEntry::Arm10e, "arm10e"},
    {CpuCoreEntry::Arm1020e, "arm1020e"},
    {CpuCoreEntry::Arm1022e, "arm1022e"},
    {CpuCoreEntry::Arm1026ejs, "arm1026ej-s"},
    {CpuCoreEntry::Arm1136j, "arm1136j"},
    {CpuCoreEntry::Arm1136js, "arm1136j-s"},
    {CpuCoreEntry::Arm1176j, "arm1176j"},
    {CpuCoreEntry::Arm1176js, "arm1176j-s"},
    {CpuCoreEntry::Xscale, "xscale"},
    {CpuCoreEntry::XscaleIr7, "xscale-ir7"},
    {CpuCoreEntry::CortexM0, "cortex-m0"},
    {CpuCoreEntry::CortexM0Plus, "cortex-m0+"}, // same as 'sc000'
    {CpuCoreEntry::CortexM1, "cortex-m1"},
    {CpuCoreEntry::CortexMs1, "cortex-ms1"},
    {CpuCoreEntry::CortexM3, "cortex-m3"}, // same as 'sc300'
    {CpuCoreEntry::CortexM4, "cortex-m4"},
    {CpuCoreEntry::CortexM7, "cortex-m7"},
    {CpuCoreEntry::CortexR4, "cortex-r4"},
    {CpuCoreEntry::CortexR5, "cortex-r5"},
    {CpuCoreEntry::CortexR7, "cortex-r7"},
    {CpuCoreEntry::CortexR8, "cortex-r8"},
    {CpuCoreEntry::CortexR52, "cortex-r52"},
    {CpuCoreEntry::CortexA5, "cortex-a5"},
    {CpuCoreEntry::CortexA7, "cortex-a7"},
    {CpuCoreEntry::CortexA8, "cortex-a8"},
    {CpuCoreEntry::CortexA9, "cortex-a9"},
    {CpuCoreEntry::CortexA15, "cortex-a15"},
    {CpuCoreEntry::CortexA17, "cortex-a17"},
    {CpuCoreEntry::CortexM23, "cortex-m23"},
    {CpuCoreEntry::CortexM33, "cortex-m33"},
};

struct FpuCoreEntry final
{
    enum FpuRegistersCount { NoFpuRegisters,
                             Fpu16Registers,
                             Fpu32Registers };

    enum FpuCoreCode { NoVfp = 0,
                       Vfp2 = 2,
                       Vfp3d16 = 3,
                       Vfp3 = 3,
                       Vfp4sp = 4,
                       Vfp4d16 = 5,
                       Vfp4 = 5,
                       Vfp5sp = 6,
                       Vfp5d16 = 7,
                       Vfp9s = 8 };

    FpuCoreCode coreCode = NoVfp;
    FpuRegistersCount regsCount = NoFpuRegisters;
    QByteArray targetFlag;
};
<commit_msg>Fix compilation errors with MSVC2015<commit_after>/****************************************************************************
**
** Copyright (C) 2019 <NAME> <<EMAIL>>
** Contact: http://www.qt.io/licensing
**
** This file is part of Qbs.
**
** Commercial License Usage
** Licensees holding valid commercial Qt licenses may use this file in
** accordance with the commercial license agreement provided with the
** Software or, alternatively, in accordance with the terms contained in
** a written agreement between you and The Qt Company. For licensing terms and
** conditions see http://www.qt.io/terms-conditions. For further information
** use the contact form at http://www.qt.io/contact-us.
**
** GNU Lesser General Public License Usage
** Alternatively, this file may be used under the terms of the GNU Lesser
** General Public License version 2.1 or version 3 as published by the Free
** Software Foundation and appearing in the file LICENSE.LGPLv21 and
** LICENSE.LGPLv3 included in the packaging of this file.  Please review the
** following information to ensure the GNU Lesser General Public License
** requirements will be met: https://www.gnu.org/licenses/lgpl.html and
** http://www.gnu.org/licenses/old-licenses/lgpl-2.1.html.
**
** In addition, as a special exception, The Qt Company gives you certain additional
** rights.  These rights are described in The Qt Company LGPL Exception
** version 1.1, included in the file LGPL_EXCEPTION.txt in this package.
**
****************************************************************************/

#include "armgeneralsettingsgroup_v8.h"

#include "../../iarewutils.h"

#include <QtCore/qdir.h>

namespace qbs {
namespace v8 {

constexpr int kGeneralArchiveVersion = 3;
constexpr int kGeneralDataVersion = 30;

namespace ArmGeneral {

struct CpuCoreEntry final
{
    enum CpuCoreCode { Arm7tdmi = 0,
                       Arm7tdmis = 1,
                       Arm710t = 2,
                       Arm720t = 3,
                       Arm740t = 4,
                       Arm7ejs = 5,
                       Arm9tdmi = 6,
                       Arm920t = 7,
                       Arm922t = 8,
                       Arm940t = 9,
                       Arm9e = 10,
                       Arm9es = 11,
                       Arm926ejs = 12,
                       Arm946es = 13,
                       Arm966es = 14,
                       Arm968es = 15,
                       Arm10e = 16,
                       Arm1020e = 17,
                       Arm1022e = 18,
                       Arm1026ejs = 19,
                       Arm1136j = 20,
                       Arm1136js = 21,
                       Arm1176j = 24,
                       Arm1176js = 25,
                       Xscale = 32,
                       XscaleIr7 = 33,
                       CortexM0 = 34,
                       CortexM0Plus = 35,
                       CortexM1 = 36,
                       CortexMs1 = 37,
                       CortexM3 = 38,
                       CortexM4 = 39,
                       CortexM7 = 41,
                       CortexR4 = 42,
                       CortexR5 = 44,
                       CortexR7 = 46,
                       CortexR8 = 48,
                       CortexR52 = 49,
                       CortexA5 = 50,
                       CortexA7 = 52,
                       CortexA8 = 53,
                       CortexA9 = 54,
                       CortexA15 = 55,
                       CortexA17 = 56,
                       CortexM23 = 58,
                       CortexM33 = 59 };

    // Required to compile in MSVC2015.
    CpuCoreEntry(CpuCoreCode cc, QByteArray tf)
        : coreCode(cc), targetFlag(std::move(tf))
    {}

    CpuCoreCode coreCode = Arm7tdmi;
    QByteArray targetFlag;
};

// Dictionary of known ARM CPU cores and its compiler options.
static const CpuCoreEntry cpusDict[] = {
    {CpuCoreEntry::Arm7tdmi, "arm7tdmi"}, // same as 'sc100'
    {CpuCoreEntry::Arm7tdmis, "arm7tdmi-s"},
    {CpuCoreEntry::Arm710t, "arm710t"},
    {CpuCoreEntry::Arm720t, "arm720t"},
    {CpuCoreEntry::Arm740t, "arm740t"},
    {CpuCoreEntry::Arm7ejs, "arm7ej-s"},
    {CpuCoreEntry::Arm9tdmi, "arm9tdmi"},
    {CpuCoreEntry::Arm920t, "arm920t"},
    {CpuCoreEntry::Arm922t, "arm922t"},
    {CpuCoreEntry::Arm940t, "arm940t"},
    {CpuCoreEntry::Arm9e, "arm9e"},
    {CpuCoreEntry::Arm9es, "arm9e-s"},
    {CpuCoreEntry::Arm926ejs, "arm926ej-s"},
    {CpuCoreEntry::Arm946es, "arm946e-s"},
    {CpuCoreEntry::Arm966es, "arm966e-s"},
    {CpuCoreEntry::Arm968es, "arm968e-s"},
    {CpuCoreEntry::Arm10e, "arm10e"},
    {CpuCoreEntry::Arm1020e, "arm1020e"},
    {CpuCoreEntry::Arm1022e, "arm1022e"},
    {CpuCoreEntry::Arm1026ejs, "arm1026ej-s"},
    {CpuCoreEntry::Arm1136j, "arm1136j"},
    {CpuCoreEntry::Arm1136js, "arm1136j-s"},
    {CpuCoreEntry::Arm1176j, "arm1176j"},
    {CpuCoreEntry::Arm1176js, "arm1176j-s"},
    {CpuCoreEntry::Xscale, "xscale"},
    {CpuCoreEntry::XscaleIr7, "xscale-ir7"},
    {CpuCoreEntry::CortexM0, "cortex-m0"},
    {CpuCoreEntry::CortexM0Plus, "cortex-m0+"}, // same as 'sc000'
    {CpuCoreEntry::CortexM1, "cortex-m1"},
    {CpuCoreEntry::CortexMs1, "cortex-ms1"},
    {CpuCoreEntry::CortexM3, "cortex-m3"}, // same as 'sc300'
    {CpuCoreEntry::CortexM4, "cortex-m4"},
    {CpuCoreEntry::CortexM7, "cortex-m7"},
    {CpuCoreEntry::CortexR4, "cortex-r4"},
    {CpuCoreEntry::CortexR5, "cortex-r5"},
    {CpuCoreEntry::CortexR7, "cortex-r7"},
    {CpuCoreEntry::CortexR8, "cortex-r8"},
    {CpuCoreEntry::CortexR52, "cortex-r52"},
    {CpuCoreEntry::CortexA5, "cortex-a5"},
    {CpuCoreEntry::CortexA7, "cortex-a7"},
    {CpuCoreEntry::CortexA8, "cortex-a8"},
    {CpuCoreEntry::CortexA9, "cortex-a9"},
    {CpuCoreEntry::CortexA15, "cortex-a15"},
    {CpuCoreEntry::CortexA17, "cortex-a17"},
    {CpuCoreEntry::CortexM23, "cortex-m23"},
    {CpuCoreEntry::CortexM33, "cortex-m33"},
};

struct FpuCoreEntry final
{
    enum FpuRegistersCount { NoFpuRegisters,
                             Fpu16Registers,
                             Fpu32Registers };

    enum FpuCoreCode { NoVfp = 0,
                       Vfp2 = 2,
                       Vfp3d16 = 3,
                       Vfp3 = 3,
                       Vfp4sp = 4,
                       Vfp4d16 = 5,
                       Vfp4 = 5,
                       Vfp5sp = 6,
                       Vfp5d16 = 7,
                       Vfp9s = 8 };


    // Required to compile in MSVC2015.
    FpuCoreEntry(FpuCoreCode cc, FpuRegistersCount rc,
                 QByteArray tf)
        : coreCode(cc), regsCount(rc), targetFlag(std::move(tf))
    {}

    FpuCoreCode coreCode = NoVfp;
    FpuRegistersCount regsCount = NoFpuRegisters;
    QByteArray targetFlag;
};

{'fraction_non_alphanumeric': 0.13465648854961831, 'fraction_numerical': 0.06442748091603054, 'mean_word_length': 1.9243303571428572, 'pattern_counts': {'":': 0, '<': 11, '<?xml version=': 0, '>': 11, 'https://': 2, 'lorem ipsum': 0, 'www.': 10, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '1565867', 'n_tokens_mistral': 4812, 'n_tokens_neox': 4131, 'n_words': 929}