<commit_before>/*-
 * Copyright (c) 2000 <NAME>
 * Copyright (c) 2000 <NAME>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

/*
 * Fixes for 830/845G support: <NAME> <<EMAIL>>
 * 852GM/855GM/865G support added by <NAME> <<EMAIL>>
 */

#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");

#include "opt_bus.h"

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/proc.h>

#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <pci/agppriv.h>
#include <pci/agpreg.h>

#include <vm/vm.h>
#include <vm/vm_object.h>
#include <vm/vm_page.h>
#include <vm/vm_pageout.h>
#include <vm/pmap.h>

#include <machine/bus.h>
#include <machine/resource.h>
#include <machine/md_var.h>
#include <sys/rman.h>

MALLOC_DECLARE(M_AGP);

enum {
	CHIP_I810,	/* i810/i815 */
	CHIP_I830,	/* 830M/845G */
	CHIP_I855,	/* 852GM/855GM/865G */
	CHIP_I915,	/* 915G/915GM */
	CHIP_I965,	/* G965 */
	CHIP_G33,	/* G33/Q33/Q35 */
};

/* The i810 through i855 have the registers at BAR 1, and the GATT gets
 * allocated by us.  The i915 has registers in BAR 0 and the GATT is at the
 * start of the stolen memory, and should only be accessed by the OS through
 * BAR 3.  The G965 has registers and GATT in the same BAR (0) -- first 512KB
 * is registers, second 512KB is GATT.
 */
static struct resource_spec agp_i810_res_spec[] = {
	{ SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE },
	{ -1, 0 }
};

static struct resource_spec agp_i915_res_spec[] = {
	{ SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
	{ SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
	{ -1, 0 }
};

static struct resource_spec agp_i965_res_spec[] = {
	{ SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
	{ -1, 0 }
};

struct agp_i810_softc {
	struct agp_softc agp;
	u_int32_t initial_aperture;	/* aperture size at startup */
	struct agp_gatt *gatt;
	int chiptype;			/* i810-like or i830 */
	u_int32_t dcache_size;		/* i810 only */
	u_int32_t stolen;		/* number of i830/845 gtt entries for stolen memory */
	device_t bdev;			/* bridge device */

	void *argb_cursor;		/* contigmalloc area for ARGB cursor */

	struct resource_spec * sc_res_spec;
	struct resource *sc_res[2];
};

/* For adding new devices, devid is the id of the graphics controller
 * (pci:0:2:0, for example).  The placeholder (usually at pci:0:2:1) for the
 * second head should never be added.  The bridge_offset is the offset to
 * subtract from devid to get the id of the hostb that the device is on.
 */
static const struct agp_i810_match {
	int devid;
	int chiptype;
	int bridge_offset;
	char *name;
} agp_i810_matches[] = {
	{0x71218086, CHIP_I810, 0x00010000,
	    "Intel 82810 (i810 GMCH) SVGA controller"},
	{0x71238086, CHIP_I810, 0x00010000,
	    "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"},
	{0x71258086, CHIP_I810, 0x00010000,
	    "Intel 82810E (i810E GMCH) SVGA controller"},
	{0x11328086, CHIP_I810, 0x00020000,
	    "Intel 82815 (i815 GMCH) SVGA controller"},
	{0x35778086, CHIP_I830, 0x00020000,
	    "Intel 82830M (830M GMCH) SVGA controller"},
	{0x35828086, CHIP_I855, 0x00020000,
	    "Intel 82852/5"},
	{0x25728086, CHIP_I855, 0x00020000,
	    "Intel 82865G (865G GMCH) SVGA controller"},
	{0x25828086, CHIP_I915, 0x00020000,
	    "Intel 82915G (915G GMCH) SVGA controller"},
	{0x258A8086, CHIP_I915, 0x00020000,
	    "Intel E7221 SVGA controller"},
	{0x25928086, CHIP_I915, 0x00020000,
	    "Intel 82915GM (915GM GMCH) SVGA controller"},
	{0x27728086, CHIP_I915, 0x00020000,
	    "Intel 82945G (945G GMCH) SVGA controller"},
	{0x27A28086, CHIP_I915, 0x00020000,
	    "Intel 82945GM (945GM GMCH) SVGA controller"},
	{0x27A28086, CHIP_I915, 0x00020000,
	    "Intel 945GME SVGA controller"},
	{0x29728086, CHIP_I965, 0x00020000,
	    "Intel 946GZ SVGA controller"},
	{0x29828086, CHIP_I965, 0x00020000,
	    "Intel G965 SVGA controller"},
	{0x29928086, CHIP_I965, 0x00020000,
	    "Intel Q965 SVGA controller"},
	{0x29a28086, CHIP_I965, 0x00020000,
	    "Intel G965 SVGA controller"},
/*
	{0x29b28086, CHIP_G33, 0x00020000,<commit_msg>MFC rev 1.11 agp.4<commit_after>/*-
 * Copyright (c) 2000 <NAME>
 * Copyright (c) 2000 <NAME>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

/*
 * Fixes for 830/845G support: <NAME> <<EMAIL>>
 * 852GM/855GM/865G support added by <NAME> <<EMAIL>>
 */

#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");

#include "opt_bus.h"

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/proc.h>

#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <pci/agppriv.h>
#include <pci/agpreg.h>

#include <vm/vm.h>
#include <vm/vm_object.h>
#include <vm/vm_page.h>
#include <vm/vm_pageout.h>
#include <vm/pmap.h>

#include <machine/bus.h>
#include <machine/resource.h>
#include <machine/md_var.h>
#include <sys/rman.h>

MALLOC_DECLARE(M_AGP);

enum {
	CHIP_I810,	/* i810/i815 */
	CHIP_I830,	/* 830M/845G */
	CHIP_I855,	/* 852GM/855GM/865G */
	CHIP_I915,	/* 915G/915GM */
	CHIP_I965,	/* G965 */
	CHIP_G33,	/* G33/Q33/Q35 */
};

/* The i810 through i855 have the registers at BAR 1, and the GATT gets
 * allocated by us.  The i915 has registers in BAR 0 and the GATT is at the
 * start of the stolen memory, and should only be accessed by the OS through
 * BAR 3.  The G965 has registers and GATT in the same BAR (0) -- first 512KB
 * is registers, second 512KB is GATT.
 */
static struct resource_spec agp_i810_res_spec[] = {
	{ SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE },
	{ -1, 0 }
};

static struct resource_spec agp_i915_res_spec[] = {
	{ SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
	{ SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
	{ -1, 0 }
};

static struct resource_spec agp_i965_res_spec[] = {
	{ SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
	{ -1, 0 }
};

struct agp_i810_softc {
	struct agp_softc agp;
	u_int32_t initial_aperture;	/* aperture size at startup */
	struct agp_gatt *gatt;
	int chiptype;			/* i810-like or i830 */
	u_int32_t dcache_size;		/* i810 only */
	u_int32_t stolen;		/* number of i830/845 gtt entries for stolen memory */
	device_t bdev;			/* bridge device */

	void *argb_cursor;		/* contigmalloc area for ARGB cursor */

	struct resource_spec * sc_res_spec;
	struct resource *sc_res[2];
};

/* For adding new devices, devid is the id of the graphics controller
 * (pci:0:2:0, for example).  The placeholder (usually at pci:0:2:1) for the
 * second head should never be added.  The bridge_offset is the offset to
 * subtract from devid to get the id of the hostb that the device is on.
 */
static const struct agp_i810_match {
	int devid;
	int chiptype;
	int bridge_offset;
	char *name;
} agp_i810_matches[] = {
	{0x71218086, CHIP_I810, 0x00010000,
	    "Intel 82810 (i810 GMCH) SVGA controller"},
	{0x71238086, CHIP_I810, 0x00010000,
	    "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"},
	{0x71258086, CHIP_I810, 0x00010000,
	    "Intel 82810E (i810E GMCH) SVGA controller"},
	{0x11328086, CHIP_I810, 0x00020000,
	    "Intel 82815 (i815 GMCH) SVGA controller"},
	{0x35778086, CHIP_I830, 0x00020000,
	    "Intel 82830M (830M GMCH) SVGA controller"},
	{0x25628086, CHIP_I830, 0x00020000,
	    "Intel 82845M (845M GMCH) SVGA controller"},
	{0x35828086, CHIP_I855, 0x00020000,
	    "Intel 82852/5"},
	{0x25728086, CHIP_I855, 0x00020000,
	    "Intel 82865G (865G GMCH) SVGA controller"},
	{0x25828086, CHIP_I915, 0x00020000,
	    "Intel 82915G (915G GMCH) SVGA controller"},
	{0x258A8086, CHIP_I915, 0x00020000,
	    "Intel E7221 SVGA controller"},
	{0x25928086, CHIP_I915, 0x00020000,
	    "Intel 82915GM (915GM GMCH) SVGA controller"},
	{0x27728086, CHIP_I915, 0x00020000,
	    "Intel 82945G (945G GMCH) SVGA controller"},
	{0x27A28086, CHIP_I915, 0x00020000,
	    "Intel 82945GM (945GM GMCH) SVGA controller"},
	{0x27A28086, CHIP_I915, 0x00020000,
	    "Intel 945GME SVGA controller"},
	{0x29728086, CHIP_I965, 0x00020000,
	    "Intel 946GZ SVGA controller"},
	{0x29828086, CHIP_I965, 0x00020000,
	    "Intel G965 SVGA controller"},
	{0x29928086, CHIP_I965, 0x00020000,
	    "Intel Q965 SVGA controller"},
	{0x29a28086, CHIP_I965, 0x00020000,
	    "Intel G965 SVGA controller"},
/*
	{0x29b28086, CHIP_G33, 0x00020000,
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