<commit_before>[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.Testbench.assert'"
    , "type" :
"assert' :: (Eq a,Show a) -- (ARG[0],ARG[1])
         => SClock t      -- ^ ARG[2]
         -> String        -- ^ ARG[3]
         -> Signal' t a   -- ^ Checked value (ARG[4])
         -> Signal' t a   -- ^ Expected value (ARG[5])
         -> Signal' t b   -- ^ Return valued (ARG[6])
         -> Signal' t b"
    , "templateD" :
"assert_~SYM[0] : block
  -- pragma translate_off
  function slv2string (slv : std_logic_vector) return STRING is
     variable result : string (1 to slv'length);
     variable res_l : string (1 to 3);
     variable r : integer;
   begin
     r := 1;
     for i in slv'range loop
        res_l := std_logic'image(slv(i));
        result(r) := res_l(2);
        r := r + 1;
     end loop;
     return result;
  end;
  signal actual   : ~TYP[4];
  signal expected : ~TYP[5];
  -- pragma translate_on
begin
  -- pragma translate_off
  actual   <= ~ARG[4];
  expected <= ~ARG[5];
  process(~CLK[2],~RST[2]) is
  begin
    if (rising_edge(~CLK[2]) or rising_edge(~RST[2])) then
      assert (actual = expected) report (~LIT[3] & \", expected: \" & slv2string(toSLV(expected)) & \", actual: \" & slv2string(toSLV(actual))) severity error;
    end if;
  end process;
  -- pragma translate_on
  ~RESULT <= ~ARG[6];
end block;"
    }
  }
]<commit_msg>Mark begin/end assert VHDL primitive<commit_after>[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.Testbench.assert'"
    , "type" :
"assert' :: (Eq a,Show a) -- (ARG[0],ARG[1])
         => SClock t      -- ^ ARG[2]
         -> String        -- ^ ARG[3]
         -> Signal' t a   -- ^ Checked value (ARG[4])
         -> Signal' t a   -- ^ Expected value (ARG[5])
         -> Signal' t b   -- ^ Return valued (ARG[6])
         -> Signal' t b"
    , "templateD" :
"-- assert begin
assert_~SYM[0] : block
  -- pragma translate_off
  function slv2string (slv : std_logic_vector) return STRING is
     variable result : string (1 to slv'length);
     variable res_l : string (1 to 3);
     variable r : integer;
   begin
     r := 1;
     for i in slv'range loop
        res_l := std_logic'image(slv(i));
        result(r) := res_l(2);
        r := r + 1;
     end loop;
     return result;
  end;
  signal actual   : ~TYP[4];
  signal expected : ~TYP[5];
  -- pragma translate_on
begin
  -- pragma translate_off
  actual   <= ~ARG[4];
  expected <= ~ARG[5];
  process(~CLK[2],~RST[2]) is
  begin
    if (rising_edge(~CLK[2]) or rising_edge(~RST[2])) then
      assert (actual = expected) report (~LIT[3] & \", expected: \" & slv2string(toSLV(expected)) & \", actual: \" & slv2string(toSLV(actual))) severity error;
    end if;
  end process;
  -- pragma translate_on
  ~RESULT <= ~ARG[6];
end block;
-- assert end"
    }
  }
]
{'fraction_non_alphanumeric': 0.1689989235737352, 'fraction_numerical': 0.0193756727664155, 'mean_word_length': 2.311163895486936, 'pattern_counts': {'":': 0, '<': 9, '<?xml version=': 0, '>': 15, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '3308030', 'n_tokens_mistral': 1045, 'n_tokens_neox': 1022, 'n_words': 262}