<commit_before>/*
 * Author: <AUTHORNAME>
 * Committer: <COMMITTERNAME>
 *
 * Create Date:    Tue Sep 20 15:07:10 CEST 2016 
 * Module Name:    J1 - Toplevel CPU (Core, Memory)
 * Project Name:   J1Sc - A simple J1 implementation in Scala using Spinal HDL
 *
 * Hash: 0a82e2997654f501bf8937447a1521127602ea03
 * Date: Tue Nov 1 15:35:55 2016 +0100
 */
import spinal.core._
import spinal.lib._

class J1(wordSize            : Int = 16,
         dataStackIdxWidth   : Int =  8,
         returnStackIdxWidth : Int =  6,
         addrWidth           : Int = 13,
         startAddress        : Int =  0) extends Component {

  // I/O ports
  val io = new Bundle {

    // I/O signals for memory data port
    val writeEnable = out Bool
    val dataAddress  = out UInt(addrWidth bits)
    val dataWrite = out Bits(wordSize bits)
    val dataRead = in Bits(wordSize bits)

  }.setName("")

  // Signals for main memory
  val memWriteEnable = Bool
  val memAdr = UInt(addrWidth bits)
  val memWrite = Bits(wordSize bits)
  val memRead = Bits(wordSize bits)

  // Create main memory
  def content = List(B"1000_0000_0000_0111", //  0. Push 7
                     B"1000_0000_0000_0011", //  1. Push 3
                     B"0000_0000_0000_0100", //  2. Jump 4
                     B"1000_0000_0000_0001", //  3. Push 1
                     B"1000_0000_0000_1111", //  4. Push 15
                     B"0110_0010_0000_0011", //  5. Add, drop and push
                     B"0110_0010_0000_0001", //  6. Add and push
                     B"0110_0010_0000_0000", //  7. Add and no push
                     B"0010_0000_0000_1011", //  8. Jump 11 if tos is zero
                     B"1000_0000_0000_0000", //  9. Push 0
                     B"0010_0000_0000_1010", // 10. Jump 10 if tos is zero
                     B"0100_0000_0010_0000", // 11. Call 32
                     B"1000_0000_0000_0001", // 12. Push 1
                     B"0110_0111_0000_0001", // 13. Compare tos and nos push result
                     B"1000_0000_0000_0011", // 14. Push 3
                     B"1000_0000_0000_0011", // 15. Push 3
                     B"0110_0111_0000_0001", // 16. Compare tos and nos push result
                     B"1101_0101_0101_0101", // 17. Push 0x5555
                     B"1000_0000_0000_0000", // 18. Push 0x0000
                     B"0110_0000_0100_0000", // 19. ALU I/O operation
                     B"0110_0000_0000_0000", // 20. ALU I/O operation (wait state)
                     B"0110_0000_0000_0000", // 21. Clear I/O
                     B"0110_0000_0000_0000", // 22. Clear I/O (wait state)
                     B"0000_0000_0001_0111", // 23. Jump 23
                     B"0110_0000_0000_0000", // 24. NOP
                     B"0110_0000_0000_0000", // 25. NOP
                     B"0110_0000_0000_0000", // 26. NOP
                     B"0110_0000_0000_0000", // 27. NOP
                     B"0110_0000_0000_0000", // 28. NOP
                     B"0110_0000_0000_0000", // 29. NOP<commit_msg>New LED pattern for test<commit_after>/*
 * Author: <AUTHORNAME>
 * Committer: <COMMITTERNAME>
 *
 * Create Date:    Tue Sep 20 15:07:10 CEST 2016 
 * Module Name:    J1 - Toplevel CPU (Core, Memory)
 * Project Name:   J1Sc - A simple J1 implementation in Scala using Spinal HDL
 *
 * Hash: 0a82e2997654f501bf8937447a1521127602ea03
 * Date: Tue Nov 1 15:35:55 2016 +0100
 */
import spinal.core._
import spinal.lib._

class J1(wordSize            : Int = 16,
         dataStackIdxWidth   : Int =  8,
         returnStackIdxWidth : Int =  6,
         addrWidth           : Int = 13,
         startAddress        : Int =  0) extends Component {

  // I/O ports
  val io = new Bundle {

    // I/O signals for memory data port
    val writeEnable = out Bool
    val dataAddress  = out UInt(addrWidth bits)
    val dataWrite = out Bits(wordSize bits)
    val dataRead = in Bits(wordSize bits)

  }.setName("")

  // Signals for main memory
  val memWriteEnable = Bool
  val memAdr = UInt(addrWidth bits)
  val memWrite = Bits(wordSize bits)
  val memRead = Bits(wordSize bits)

  // Create main memory
  def content = List(B"1000_0000_0000_0111", //  0. Push 7
                     B"1000_0000_0000_0011", //  1. Push 3
                     B"0000_0000_0000_0100", //  2. Jump 4
                     B"1000_0000_0000_0001", //  3. Push 1
                     B"1000_0000_0000_1111", //  4. Push 15
                     B"0110_0010_0000_0011", //  5. Add, drop and push
                     B"0110_0010_0000_0001", //  6. Add and push
                     B"0110_0010_0000_0000", //  7. Add and no push
                     B"0010_0000_0000_1011", //  8. Jump 11 if tos is zero
                     B"1000_0000_0000_0000", //  9. Push 0
                     B"0010_0000_0000_1010", // 10. Jump 10 if tos is zero
                     B"0100_0000_0010_0000", // 11. Call 32
                     B"1000_0000_0000_0001", // 12. Push 1
                     B"0110_0111_0000_0001", // 13. Compare tos and nos push result
                     B"1000_0000_0000_0011", // 14. Push 3
                     B"1000_0000_0000_0011", // 15. Push 3
                     B"0110_0111_0000_0001", // 16. Compare tos and nos push result
                     B"1101_0101_0101_0111", // 17. Push 0x5557
                     B"1000_0000_0000_0000", // 18. Push 0x0000
                     B"0110_0000_0100_0000", // 19. ALU I/O operation
                     B"0110_0000_0000_0000", // 20. ALU I/O operation (wait state)
                     B"0110_0000_0000_0000", // 21. Clear I/O
                     B"0110_0000_0000_0000", // 22. Clear I/O (wait state)
                     B"0000_0000_0001_0111", // 23. Jump 23
                     B"0110_0000_0000_0000", // 24. NOP
                     B"0110_0000_0000_0000", // 25. NOP
                     B"0110_0000_0000_0000", // 26. NOP
                     B"0110_0000_0000_0000", // 27. NOP
                     B"0110_0000_0000_0000", // 28. NOP
                     B"0110_0000_0000_0000", // 29. NOP
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