<commit_before>properties:
32 bit instructions
16 registers
3 address

r0-r15 - 32bit

LR = r15

instruction forms
33222222222211111111110000000000
10987654321098765432109876543210
--------------------------------
00ppddddppppaaaaiiiiiiiiiiiiiiii
01ppddddppppaaaabbbbxxxxxxxxxxxx
10ppddddiiiiiiiiiiiiiiiiiiiiiiii
11xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

	alu ops
add			0?  00 d<4> 0000 a<4> b<4>,imm		a + b
sub			0?  00 d<4> 0001 a<4> b<4>,imm		a - b
rsb			0?  00 d<4> 0010 a<4> b<4>,imm		b - a
and			0?  00 d<4> 0011 a<4> b<4>,imm		a & b
or			0?  00 d<4> 0100 a<4> b<4>,imm		a | b
xor			0?  00 d<4> 0101 a<4> b<4>,imm		a ^ b
lsl			0?  00 d<4> 0110 a<4> b<4>,imm		a << b
lsr			0?  00 d<4> 0111 a<4> b<4>,imm		a >> b
asr			0?  00 d<4> 1000 a<4> b<4>,imm		a >> b, sign extend
mov			0?  00 d<4> 1001 ign  b<4>,imm		b
mvb			0?  00 d<4> 1010 ign  b<4>,imm		b & 0xffff
mvt			0?  00 d<4> 1011 a<4> b<4>,imm		a | (b << 16)

slt			0?  00 d<4> 1100 a<4> b<4>,imm		a < b
slte		0?  00 d<4> 1101 a<4> b<4>,imm		a <= b
seq			0?  00 d<4> 1110 a<4> b<4>,imm		a == b

	load/store
ldr			0?  01 d<4> 0000 a<4> b<4>,imm		ldr Rd, [Ra + Rb]
str	        0?  10 d<4> 0000 a<b> b<4>,imm		str Rd, [Ra + Rb]

	unused
			00  11xxxx  xxxxxxxxxxxxxxxxxxxxx

	branch
bc			10  00 d<4> imm<24>			- if (r)  { pc += (sign(imm << 2)) }
blc			10  01 d<4> imm<24>			- if (r)  { lr = pc + 4, pc += (sign(imm << 2)) }
bnc			10  10 d<4> imm<24>			- if (!r) { pc += (sign(imm << 2)) }
blnc		10  11 d<4> imm<24>			- if (!r) { lr = pc + 4, pc += (sign(imm << 2)) }

	unused
			11  xxxxxxx xxxxxxxxxxxxxxxxxxxxx

pseudo instructions:
mvn	a, b	-	rsb a, b, #0
not	a, b	-	xor a, b, #0

common algorithms:

a < b and branch
clt     cr, a, b
bz      cr

a > b and branch
slte    cr, a, b
bz      cr

a <= b and branch
clte    cr, a, b
bz      cr

a >= b and branch
slt     cr, a, b
bz      cr

a == b and branch
ceq     cr, a, b
bz      cr

a != b and branch
seq     cr, a, b
bz      cr

test for negative
clt     a, #0

64bit add   c = a + b
add     cl, al, bl
slt     cr, cl, al
add     ch, ah, bh
bz	cr, skip
add     ch, ch, t
skip:

<commit_msg>clean up the isa.txt file to display nicer on a 8 space tab editor<commit_after># vi: set ts=8
properties:
32 bit instructions
16 registers
3 address

r0-r15 - 32bit

LR = r15

instruction forms
33222222222211111111110000000000
10987654321098765432109876543210
--------------------------------
00ppddddppppaaaaiiiiiiiiiiiiiiii
01ppddddppppaaaabbbbxxxxxxxxxxxx
10ppddddiiiiiiiiiiiiiiiiiiiiiiii
11xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

all immediates are sign extended

			00 -- immediate version
			01 -- register,register

	alu ops
add			0?  00 d<4> 0000 a<4> b<4>,imm<16>	a + b
sub			0?  00 d<4> 0001 a<4> b<4>,imm<16>	a - b
rsb			0?  00 d<4> 0010 a<4> b<4>,imm<16>	b - a
and			0?  00 d<4> 0011 a<4> b<4>,imm<16>	a & b
or			0?  00 d<4> 0100 a<4> b<4>,imm<16>	a | b
xor			0?  00 d<4> 0101 a<4> b<4>,imm<16>	a ^ b
lsl			0?  00 d<4> 0110 a<4> b<4>,imm<16>	a << b
lsr			0?  00 d<4> 0111 a<4> b<4>,imm<16>	a >> b
asr			0?  00 d<4> 1000 a<4> b<4>,imm<16>	a >> b, sign extend
mov			0?  00 d<4> 1001 ign  b<4>,imm<16>	b
mvb			0?  00 d<4> 1010 ign  b<4>,imm<16>	b & 0xffff
mvt			0?  00 d<4> 1011 a<4> b<4>,imm<16>	a | (b << 16)

slt			0?  00 d<4> 1100 a<4> b<4>,imm<16>	a < b
slte			0?  00 d<4> 1101 a<4> b<4>,imm<16>	a <= b
seq			0?  00 d<4> 1110 a<4> b<4>,imm<16>	a == b

unused			0?  00 d<4> 1111 a<4> b<4>,imm<16>

	load/store
ldr			0?  01 d<4> 0000 a<4> b<4>,imm<16>	ldr Rd, [Ra + Rb]
str	        	0?  10 d<4> 0000 a<b> b<4>,imm<16>	str Rd, [Ra + Rb]

	unused
			0?  11xxxx  xxxxxxxxxxxxxxxxxxxxx

	branch
bc			10  00 d<4> imm<24>			- if (r)  { pc += (sign(imm << 2)) }
blc			10  01 d<4> imm<24>			- if (r)  { lr = pc + 4, pc += (sign(imm << 2)) }
bnc			10  10 d<4> imm<24>			- if (!r) { pc += (sign(imm << 2)) }
blnc			10  11 d<4> imm<24>			- if (!r) { lr = pc + 4, pc += (sign(imm << 2)) }

	unused
			11  xxxxxxx xxxxxxxxxxxxxxxxxxxxx

pseudo instructions:
mvn	a, b	-	rsb a, b, #0
not	a, b	-	xor a, b, #0

common algorithms:

a < b and branch
clt     cr, a, b
bz      cr

a > b and branch
slte    cr, a, b
bz      cr

a <= b and branch
clte    cr, a, b
bz      cr

a >= b and branch
slt     cr, a, b
bz      cr

a == b and branch
ceq     cr, a, b
bz      cr

a != b and branch
seq     cr, a, b
bz      cr

test for negative
clt     a, #0

64bit add   c = a + b
add     cl, al, bl
slt     cr, cl, al
add     ch, ah, bh
add     ch, ch, cr


{'fraction_non_alphanumeric': 0.1600723490843319, 'fraction_numerical': 0.14673298666063758, 'mean_word_length': 2.3263157894736843, 'pattern_counts': {'":': 0, '<': 170, '<?xml version=': 0, '>': 150, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 20, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '5050467', 'n_tokens_mistral': 2666, 'n_tokens_neox': 2177, 'n_words': 722}