<commit_before>/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  <NAME> <<EMAIL>>
 *  
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *  
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#include "kernel/register.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"

static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global)
{
	name = RTLIL::escape_id(name);

	if (module->count_id(name) != 0)
	{
		RTLIL::Wire *wire = NULL;

		if (module->wires.count(name) > 0)
			wire = module->wires.at(name);

		if (wire != NULL && wire->width != width)
			wire = NULL;

		if (wire != NULL && wire->port_input != flag_input)
			wire = NULL;

		if (wire != NULL && wire->port_output != flag_output)
			wire = NULL;

		if (wire == NULL)
			log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str());
		log("Skipping module %s as it already has such an object.\n", module->name.c_str());
		return;
	}

	RTLIL::Wire *wire = new RTLIL::Wire;
	wire->name = name;
	wire->width = width;
	wire->port_input = flag_input;
	wire->port_output = flag_output;
	module->add(wire);

	if (flag_input || flag_output) {
		wire->port_id = module->wires.size();
		module->fixup_ports();
	}

	log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());

	if (!flag_global)
		return;

	for (auto &it : module->cells)
	{
		if (design->modules.count(it.second->type) == 0)
			continue;

		RTLIL::Module *mod = design->modules.at(it.second->type);
		if (!design->selected_whole_module(mod->name))
			continue;
		if (mod->get_bool_attribute("\\placeholder"))
			continue;
		if (it.second->connections.count(name) > 0)
			continue;

		it.second->connections[name] = wire;
		log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
	}
}
<commit_msg>Fixed a bug in "add -global_input"<commit_after>/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  <NAME> <<EMAIL>>
 *  
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *  
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#include "kernel/register.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"

static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global)
{
	RTLIL::Wire *wire = NULL;
	name = RTLIL::escape_id(name);

	if (module->count_id(name) != 0)
	{
		if (module->wires.count(name) > 0)
			wire = module->wires.at(name);

		if (wire != NULL && wire->width != width)
			wire = NULL;

		if (wire != NULL && wire->port_input != flag_input)
			wire = NULL;

		if (wire != NULL && wire->port_output != flag_output)
			wire = NULL;

		if (wire == NULL)
			log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str());

		log("Module %s already has such an object.\n", module->name.c_str());
	}
	else
	{
		wire = new RTLIL::Wire;
		wire->name = name;
		wire->width = width;
		wire->port_input = flag_input;
		wire->port_output = flag_output;
		module->add(wire);

		if (flag_input || flag_output) {
			wire->port_id = module->wires.size();
			module->fixup_ports();
		}

		log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
	}

	if (!flag_global)
		return;

	for (auto &it : module->cells)
	{
		if (design->modules.count(it.second->type) == 0)
			continue;

		RTLIL::Module *mod = design->modules.at(it.second->type);
		if (!design->selected_whole_module(mod->name))
			continue;
		if (mod->get_bool_attribute("\\placeholder"))
			continue;
		if (it.second->connections.count(name) > 0)
			continue;

		it.second->connections[name] = wire;
		log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
	}
}

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