<commit_before># HardCamlYosys

Use the opensource verilog synthesis tool [Yosys](http://www.clifford.at/yosys)
to read a synthesizable verilog design, convert it to a structural netlist
and save it in a JSON file.

This library can read the JSON netlist file and reconstruct the design in HardCaml.

### Status

HardCaml does not support tri-state buffers in general.  Circuits 
with tri-states will not work.
<commit_msg>add build status to readme<commit_after># HardCamlYosys

[![Build Status](https://travis-ci.org/ujamjar/hardcaml-yosys.svg?branch=master)](https://travis-ci.org/ujamjar/hardcaml-yosys)

Use the opensource verilog synthesis tool [Yosys](http://www.clifford.at/yosys)
to read a synthesizable verilog design, convert it to a structural netlist
and save it in a JSON file.

This library can read the JSON netlist file and reconstruct the design in HardCaml.

### Status

HardCaml does not support tri-state buffers in general.  Circuits 
with tri-states will not work.

{'fraction_non_alphanumeric': 0.07692307692307693, 'fraction_numerical': 0.0, 'mean_word_length': 4.716763005780347, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 3, 'https://': 2, 'lorem ipsum': 0, 'www.': 2, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '6355854', 'n_tokens_mistral': 320, 'n_tokens_neox': 312, 'n_words': 120}