<commit_before>; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx -x86-experimental-vector-widening-legalization | FileCheck %s

; Check that we perform a scalar XOR on i32.

; CHECK: pull_bitcast
; CHECK: xorl
; CHECK: ret
define void @pull_bitcast (<4 x i8>* %pA, <4 x i8>* %pB) {
  %A = load <4 x i8>, <4 x i8>* %pA
  %B = load <4 x i8>, <4 x i8>* %pB
  %C = xor <4 x i8> %A, %B
  store <4 x i8> %C, <4 x i8>* %pA
  ret void
}

; CHECK: multi_use_swizzle
; CHECK: pshufd
; CHECK-NEXT: pshufd
; CHECK-NEXT: pblendw
; CHECK-NEXT: pshufd
; CHECK-NEXT: pshufd
; CHECK-NEXT: pxor
; CHECK-NEXT: ret
define <4 x i32> @multi_use_swizzle (<4 x i32>* %pA, <4 x i32>* %pB) {
  %A = load <4 x i32>, <4 x i32>* %pA
  %B = load <4 x i32>, <4 x i32>* %pB
  %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 6>
  %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 2, i32 2>
  %S2 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 2>
  %R = xor <4 x i32> %S1, %S2
  ret <4 x i32> %R
}

; CHECK: pull_bitcast2
; CHECK: xorl
; CHECK: ret
define <4 x i8> @pull_bitcast2 (<4 x i8>* %pA, <4 x i8>* %pB, <4 x i8>* %pC) {
  %A = load <4 x i8>, <4 x i8>* %pA
  store <4 x i8> %A, <4 x i8>* %pC
  %B = load <4 x i8>, <4 x i8>* %pB
  %C = xor <4 x i8> %A, %B
  store <4 x i8> %C, <4 x i8>* %pA
  ret <4 x i8> %C
}



; CHECK: reverse_1
; CHECK-NOT: pshufd
; CHECK: ret
define <4 x i32> @reverse_1 (<4 x i32>* %pA, <4 x i32>* %pB) {
  %A = load <4 x i32>, <4 x i32>* %pA
  %B = load <4 x i32>, <4 x i32>* %pB
  %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
  %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
  ret <4 x i32> %S1
}


; CHECK: no_reverse_shuff
; CHECK: pshufd
; CHECK: ret
define <4 x i32> @no_reverse_shuff (<4 x i32>* %pA, <4 x i32>* %pB) {
  %A = load <4 x i32>, <4 x i32>* %pA
  %B = load <4 x i32>, <4 x i32>* %pB
  %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
  %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
  ret <4 x i32> %S1
}<commit_msg>[x86] fix test specifications and auto-generate checks<commit_after>; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -x86-experimental-vector-widening-legalization | FileCheck %s

; Check that we perform a scalar XOR on i32.

define void @pull_bitcast(<4 x i8>* %pA, <4 x i8>* %pB) {
; CHECK-LABEL: pull_bitcast:
; CHECK:       # BB#0:
; CHECK-NEXT:    movl (%rsi), %eax
; CHECK-NEXT:    xorl %eax, (%rdi)
; CHECK-NEXT:    retq
  %A = load <4 x i8>, <4 x i8>* %pA
  %B = load <4 x i8>, <4 x i8>* %pB
  %C = xor <4 x i8> %A, %B
  store <4 x i8> %C, <4 x i8>* %pA
  ret void
}

define <4 x i32> @multi_use_swizzle(<4 x i32>* %pA, <4 x i32>* %pB) {
; CHECK-LABEL: multi_use_swizzle:
; CHECK:       # BB#0:
; CHECK-NEXT:    vpshufd {{.*#+}} xmm0 = mem[0,1,1,2]
; CHECK-NEXT:    vpshufd {{.*#+}} xmm1 = mem[1,1,2,3]
; CHECK-NEXT:    vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
; CHECK-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,3,2,2]
; CHECK-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,2]
; CHECK-NEXT:    vpxor %xmm0, %xmm1, %xmm0
; CHECK-NEXT:    retq
  %A = load <4 x i32>, <4 x i32>* %pA
  %B = load <4 x i32>, <4 x i32>* %pB
  %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 6>
  %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 2, i32 2>
  %S2 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 2>
  %R = xor <4 x i32> %S1, %S2
  ret <4 x i32> %R
}

define <4 x i8> @pull_bitcast2(<4 x i8>* %pA, <4 x i8>* %pB, <4 x i8>* %pC) {
; CHECK-LABEL: pull_bitcast2:
; CHECK:       # BB#0:
; CHECK-NEXT:    movl (%rdi), %eax
; CHECK-NEXT:    movl %eax, (%rdx)
; CHECK-NEXT:    xorl (%rsi), %eax
; CHECK-NEXT:    vmovd %eax, %xmm0
; CHECK-NEXT:    movl %eax, (%rdi)
; CHECK-NEXT:    retq
  %A = load <4 x i8>, <4 x i8>* %pA
  store <4 x i8> %A, <4 x i8>* %pC
  %B = load <4 x i8>, <4 x i8>* %pB
  %C = xor <4 x i8> %A, %B
  store <4 x i8> %C, <4 x i8>* %pA
  ret <4 x i8> %C
}

define <4 x i32> @reverse_1(<4 x i32>* %pA, <4 x i32>* %pB) {
; CHECK-LABEL: reverse_1:
; CHECK:       # BB#0:
; CHECK-NEXT:    vmovaps (%rdi), %xmm0
; CHECK-NEXT:    retq
  %A = load <4 x i32>, <4 x i32>* %pA
  %B = load <4 x i32>, <4 x i32>* %pB
  %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
  %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
  ret <4 x i32> %S1
}

define <4 x i32> @no_reverse_shuff(<4 x i32>* %pA, <4 x i32>* %pB) {
; CHECK-LABEL: no_reverse_shuff:
; CHECK:       # BB#0:
; CHECK-NEXT:    vpshufd {{.*#+}} xmm0 = mem[2,3,2,3]
; CHECK-NEXT:    retq
  %A = load <4 x i32>, <4 x i32>* %pA
  %B = load <4 x i32>, <4 x i32>* %pB
  %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
  %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
  ret <4 x i32> %S1
}

{'fraction_non_alphanumeric': 0.19777479378476884, 'fraction_numerical': 0.12027623249568387, 'mean_word_length': 2.896860986547085, 'pattern_counts': {'":': 0, '<': 157, '<?xml version=': 0, '>': 155, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '5878763', 'n_tokens_mistral': 2987, 'n_tokens_neox': 2719, 'n_words': 924}