<commit_before><?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
	xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
	xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<import file="copyright.xml"/>

<import file="nvchipsets.xml" />
<import file="nv50_defs.xml" />
<import file="nv50_vm.xml" />
<import file="pci.xml" />

<group name="nv_pci">
	<use-group name="pci_config_head"/>
	<use-group name="pci_config_normal"/>
	<reg32 offset="0x40" name="SUBSYSTEM_ID_WR">
		<bitfield low="0" high="15" name="VENDOR"/>
		<bitfield low="16" high="31" name="SUBSYSTEM"/>
	</reg32>
	<stripe offset="0x44">
		<use-group name="pci_config_agp"/>
	</stripe>
	<reg32 offset="0x50" name="ROM_SHADOW_ENABLE"/>
	<reg32 offset="0x54" name="VGA_ENABLE"/>
	<stripe offset="0x60">
		<use-group name="pci_config_pm"/>
	</stripe>
	<stripe offset="0x68" variants="NV41-">
		<use-group name="pci_config_msi64_nomask"/>
	</stripe>
	<stripe offset="0x78" variants="NV41-">
		<use-group name="pci_config_exp_endpoint"/>
	</stripe>
	<reg32 offset="0x198" name="P2P_OUT_WRITE_SETUP_ADDR_LOW" stride="8" length="3" variants="NV50:NVC0"/>
	<reg32 offset="0x19c" name="P2P_OUT_WRITE_SETUP_ADDR_HIGH" stride="8" length="3" variants="NV50:NVC0"/>
	<reg32 offset="0x1b0" name="P2P_OUT_WRITE_WINDOW_ADDR_LOW" stride="8" length="3" variants="NV50:NVC0"/>
	<reg32 offset="0x1b4" name="P2P_OUT_WRITE_WINDOW_ADDR_HIGH" stride="8" length="3" variants="NV50:NVC0"/>
</group>

<domain name="NV_PCI" varset="chipset">
	<use-group name="nv_pci"/>
</domain>

<domain name="NV_MMIO" bare="yes" prefix="chipset">
	<array offset="0x1000" name="PBUS" stride="0x1000" length="1">
		<reg32 offset="0x100" name="INTR">
			<bitfield pos="3" name="MMIO_FAULT" variants="NV41-"/>
			<bitfield pos="26" name="USER" variants="NV50-" />
		</reg32>
		<reg32 offset="0x140" name="INTR_EN">
			<bitfield pos="3" name="MMIO_FAULT" variants="NV41-"/>
			<bitfield pos="26" name="USER" variants="NV50-" />
		</reg32>
		<reg32 offset="0x150" name="INTR_USER_TRIGGER" variants="NV50-"/>
		<reg32 offset="0x154" name="INTR_USER_SCRATCH" length="4" variants="NV50-"/>
		<stripe offset="0x300" name="HWSQ" variants="NV17:NV20 NV25:NVC0">
			<reg32 offset="0x304" name="CONTROL">
			</reg32>
			<reg32 offset="0x308" name="STATE">
				<bitfield low="0" high="7" name="IP"/>
				<bitfield pos="8" name="ACTIVE"/>
			</reg32>
			<reg32 offset="0x30c" name="TRIGGER"><commit_msg>nv/pbus: Nailed down USER2 interrupt.<commit_after><?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
	xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
	xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<import file="copyright.xml"/>

<import file="nvchipsets.xml" />
<import file="nv50_defs.xml" />
<import file="nv50_vm.xml" />
<import file="pci.xml" />

<group name="nv_pci">
	<use-group name="pci_config_head"/>
	<use-group name="pci_config_normal"/>
	<reg32 offset="0x40" name="SUBSYSTEM_ID_WR">
		<bitfield low="0" high="15" name="VENDOR"/>
		<bitfield low="16" high="31" name="SUBSYSTEM"/>
	</reg32>
	<stripe offset="0x44">
		<use-group name="pci_config_agp"/>
	</stripe>
	<reg32 offset="0x50" name="ROM_SHADOW_ENABLE"/>
	<reg32 offset="0x54" name="VGA_ENABLE"/>
	<stripe offset="0x60">
		<use-group name="pci_config_pm"/>
	</stripe>
	<stripe offset="0x68" variants="NV41-">
		<use-group name="pci_config_msi64_nomask"/>
	</stripe>
	<stripe offset="0x78" variants="NV41-">
		<use-group name="pci_config_exp_endpoint"/>
	</stripe>
	<reg32 offset="0x198" name="P2P_OUT_WRITE_SETUP_ADDR_LOW" stride="8" length="3" variants="NV50:NVC0"/>
	<reg32 offset="0x19c" name="P2P_OUT_WRITE_SETUP_ADDR_HIGH" stride="8" length="3" variants="NV50:NVC0"/>
	<reg32 offset="0x1b0" name="P2P_OUT_WRITE_WINDOW_ADDR_LOW" stride="8" length="3" variants="NV50:NVC0"/>
	<reg32 offset="0x1b4" name="P2P_OUT_WRITE_WINDOW_ADDR_HIGH" stride="8" length="3" variants="NV50:NVC0"/>
</group>

<domain name="NV_PCI" varset="chipset">
	<use-group name="nv_pci"/>
</domain>

<domain name="NV_MMIO" bare="yes" prefix="chipset">
	<array offset="0x1000" name="PBUS" stride="0x1000" length="1">
		<reg32 offset="0x100" name="INTR">
			<bitfield pos="3" name="MMIO_FAULT" variants="NV41-"/>
			<bitfield pos="26" name="USER" variants="NV50-" />
			<bitfield pos="28" name="USER2" variants="NVC0-" />
		</reg32>
		<reg32 offset="0x140" name="INTR_EN">
			<bitfield pos="3" name="MMIO_FAULT" variants="NV41-"/>
			<bitfield pos="26" name="USER" variants="NV50-" />
			<bitfield pos="28" name="USER2" variants="NVC0-" />
		</reg32>
		<reg32 offset="0x150" name="INTR_USER_TRIGGER" variants="NV50-"/>
		<reg32 offset="0x154" name="INTR_USER_SCRATCH" length="4" variants="NV50-"/>
		<reg32 offset="0x170" name="INTR_USER2_TRIGGER" variants="NVC0-"/>
		<reg32 offset="0x174" name="INTR_USER2_SCRATCH" length="4" variants="NVC0-"/>

		<stripe offset="0x300" name="HWSQ" variants="NV17:NV20 NV25:NVC0">
			<reg32 offset="0x304" name="CONTROL">
			</reg32>
			<reg32 offset="0x308" name="STATE">
				<bitfield low="0" high="7" name="IP"/>
				<bitfield pos="8" name="ACTIVE"/>
			</reg32>
			<reg32 offset="0x30c" name="TRIGGER">
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