<commit_before>/*
 * Copyright (c) 2013 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *           
 *     http://www.apache.org/licenses/LICENSE-2.0

 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License. 
 */

#include "vmm_defs.h"

/*
UINT8 hw_isr (void)
// ISR handler. Pushes hardcoded CPU ID onto stack and jumps to vector routine
// Stack offsets on entry:
// eax register will contain result         Bits 7-0: #Physical Address Bits
//                               Bits 15-8: #Virtual Address Bits
{
    UINT8   result;
    asm volatile(
.macro isr_entry_macro vector
        push vector
        jmp  hw_isr_c_wrapper
.endm
    : 
    : [addr] "m" (addr), [extension] "m" (extension), [hint] "m" (hint)
    :"%rax", "%rcx", "%rdx", "%r8");
}
*/
#define FAULT_CLASS 2
extern UINT16 exception_class;
void hw_isr_c_wrapper(unsigned long int index)
{
	asm volatile("push %%rax \n\t" //     # offset 08
		"push %%rbx \n\t" //    # offset 00
//        # If an exception fault is detected, save the GPRs
//        # for the assertion debug buffer
		"movq %0, %%rbx \n\t" // qword ptr [%rsp+$0x10h]    # vector number
//        # all exception faults have vector number up to 19
		"cmpq $19, %%rbx \n\t"
		"jg L_continue \n\t"
// # check the exception type
		"lea exception_class, %%rax \n\t" 
//RNB: the addl/subl instructions are to derefernce the (%rbx + %rax),
// and then restore the %ebx to original location
		"addq %%rax, %%rbx \n\t"
		"movzbl (%%rbx),  %%ebx \n\t"
		"subq %%rax, %%rbx \n\t"
		"cmpl %%ebx, 2 \n\t"
		"jne L_continue \n\t"
//        # Save GPRs
		"movq 0x08(%%rsp), %%rax \n\t" //this is rax
		"movq g_exception_gpr, %%rbx \n\t"
		"movq %%rax, (%%rbx) \n\t"
		"movq (%%rsp), %%rax \n\t"  //          # this is rbx
		"movq %%rax, 8(%%rbx) \n\t"
//	now save all other GP registers except RIP,RSP,RFLAGS
		"movq %%rcx, 16(%%rbx) \n\t"
		"movq %%rdx, 24(%%rbx) \n\t"
		"movq %%rdi, 32(%%rbx) \n\t"
		"movq %%rsi, 40(%%rbx) \n\t"
		"movq %%rbp, 48(%%rbx) \n\t"
		"movq %%r8, 64(%%rbx) \n\t"
		"movq %%r9, 72(%%rbx) \n\t"
		"movq %%r10, 80(%%rbx) \n\t"
		"movq %%r11, 88(%%rbx) \n\t"
		"movq %%r12, 96(%%rbx) \n\t"
		"movq %%r13, 104(%%rbx) \n\t"
		"movq %%r14, 112(%%rbx) \n\t"
		"movq %%r15, 120(%%rbx) \n\t"
		"L_continue: \n\t"
		"pop %%rbx \n\t"
		"pop %%rax \n\t"
/*
        #; save context and prepare stack for C-function
        #; at this point stack contains
        #;..................................
        #; [       SS         ]
        #; [       RSP        ]
        #; [      RFLAGS      ]
        #; [       CS         ]
        #; [       RIP        ] <= here RSP should point prior iret
        #; [[   errcode      ]]    optionally
        #; [    vector ID     ] <= RSP
*/
		"push %%rcx \n\t"	//save RCX which used for argument passing
		"movq %%rsp, %%rcx \n\t"
		"add $8, %%rcx \n\t" //now RCX points to the location of vector ID
		"push %%rdx \n\t"
		"push %%rax \n\t"
		"push %%r8 \n\t"
		"push %%r9 \n\t"
		"push %%r10 \n\t"
		"push %%r11 \n\t"
		"push %%r15 \n\t"  //used for saving unaligned stack
		"movq %%rsp, %%r15 \n\t" //# save RSP prior alignment
		"and $0x0FFFFFFFFFFFFFFF0, %%rsp \n\t" //# align on 16 bytes boundary
		"sub $0x020, %%rsp \n\t" //      # prepare space for C-function
		"call isr_c_handler \n\t"
		"movq %%r15, %%rsp \n\t" //# restore unaligned RSP
		"pop %%r15 \n\t"
		"pop %%r11 \n\t"
		"pop %%r10 \n\t"
		"pop %%r9 \n\t"
		"pop %%r8 \n\t"
		"pop %%rax \n\t"
		"pop %%rdx \n\t"
		"pop %%rcx \n\t"
		"pop %%rsp \n\t"	//isr_c_handler replaces vector ID with pointer to the
//                                # RIP. Just pop the pointer to the RIP into RSP.
		"iretq"
		:"=r" (index)
		:"r" (index)
		:
	);
}


//the functions below instantiate isr_entry_macro for 256 vectors (IDT entries)

void isr_entry_00() {
	//isr_entry_macro $0x000
	int arg = 0x000;
	hw_isr_c_wrapper(arg);
}

void isr_entry_01() {
	int arg = 0x001;
	hw_isr_c_wrapper(arg);
}

void isr_entry_02() {
	int arg = 0x002;
	hw_isr_c_wrapper(arg);
}

void isr_entry_03() {
	int arg = 0x003;
	hw_isr_c_wrapper(arg);
}

void isr_entry_04() {
	int arg = 0x004;<commit_msg>Local label convention used.<commit_after>/*
 * Copyright (c) 2013 Intel Corporation
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *           
 *     http://www.apache.org/licenses/LICENSE-2.0

 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License. 
 */

#include "vmm_defs.h"

/*
UINT8 hw_isr (void)
// ISR handler. Pushes hardcoded CPU ID onto stack and jumps to vector routine
// Stack offsets on entry:
// eax register will contain result         Bits 7-0: #Physical Address Bits
//                               Bits 15-8: #Virtual Address Bits
{
    UINT8   result;
    asm volatile(
.macro isr_entry_macro vector
        push vector
        jmp  hw_isr_c_wrapper
.endm
    : 
    : [addr] "m" (addr), [extension] "m" (extension), [hint] "m" (hint)
    :"%rax", "%rcx", "%rdx", "%r8");
}
*/
#define FAULT_CLASS 2
extern UINT16 exception_class;
void hw_isr_c_wrapper(unsigned long int index)
{
	asm volatile("push %%rax \n\t" //     # offset 08
		"push %%rbx \n\t" //    # offset 00
//        # If an exception fault is detected, save the GPRs
//        # for the assertion debug buffer
		"movq %0, %%rbx \n\t" // qword ptr [%rsp+$0x10h]    # vector number
//        # all exception faults have vector number up to 19
		"cmpq $19, %%rbx \n\t"
		"jg 1f \n\t"
// # check the exception type
		"lea exception_class, %%rax \n\t" 
//RNB: the addl/subl instructions are to derefernce the (%rbx + %rax),
// and then restore the %ebx to original location
		"addq %%rax, %%rbx \n\t"
		"movzbl (%%rbx),  %%ebx \n\t"
		"subq %%rax, %%rbx \n\t"
		"cmpl %%ebx, 2 \n\t"
		"jne 1f\n\t"
//        # Save GPRs
		"movq 0x08(%%rsp), %%rax \n\t" //this is rax
		"movq g_exception_gpr, %%rbx \n\t"
		"movq %%rax, (%%rbx) \n\t"
		"movq (%%rsp), %%rax \n\t"  //          # this is rbx
		"movq %%rax, 8(%%rbx) \n\t"
//	now save all other GP registers except RIP,RSP,RFLAGS
		"movq %%rcx, 16(%%rbx) \n\t"
		"movq %%rdx, 24(%%rbx) \n\t"
		"movq %%rdi, 32(%%rbx) \n\t"
		"movq %%rsi, 40(%%rbx) \n\t"
		"movq %%rbp, 48(%%rbx) \n\t"
		"movq %%r8, 64(%%rbx) \n\t"
		"movq %%r9, 72(%%rbx) \n\t"
		"movq %%r10, 80(%%rbx) \n\t"
		"movq %%r11, 88(%%rbx) \n\t"
		"movq %%r12, 96(%%rbx) \n\t"
		"movq %%r13, 104(%%rbx) \n\t"
		"movq %%r14, 112(%%rbx) \n\t"
		"movq %%r15, 120(%%rbx) \n\t"
		"1: \n\t"
		"pop %%rbx \n\t"
		"pop %%rax \n\t"
/*
        #; save context and prepare stack for C-function
        #; at this point stack contains
        #;..................................
        #; [       SS         ]
        #; [       RSP        ]
        #; [      RFLAGS      ]
        #; [       CS         ]
        #; [       RIP        ] <= here RSP should point prior iret
        #; [[   errcode      ]]    optionally
        #; [    vector ID     ] <= RSP
*/
		"push %%rcx \n\t"	//save RCX which used for argument passing
		"movq %%rsp, %%rcx \n\t"
		"add $8, %%rcx \n\t" //now RCX points to the location of vector ID
		"push %%rdx \n\t"
		"push %%rax \n\t"
		"push %%r8 \n\t"
		"push %%r9 \n\t"
		"push %%r10 \n\t"
		"push %%r11 \n\t"
		"push %%r15 \n\t"  //used for saving unaligned stack
		"movq %%rsp, %%r15 \n\t" //# save RSP prior alignment
		"and $0x0FFFFFFFFFFFFFFF0, %%rsp \n\t" //# align on 16 bytes boundary
		"sub $0x020, %%rsp \n\t" //      # prepare space for C-function
		"call isr_c_handler \n\t"
		"movq %%r15, %%rsp \n\t" //# restore unaligned RSP
		"pop %%r15 \n\t"
		"pop %%r11 \n\t"
		"pop %%r10 \n\t"
		"pop %%r9 \n\t"
		"pop %%r8 \n\t"
		"pop %%rax \n\t"
		"pop %%rdx \n\t"
		"pop %%rcx \n\t"
		"pop %%rsp \n\t"	//isr_c_handler replaces vector ID with pointer to the
//                                # RIP. Just pop the pointer to the RIP into RSP.
		"iretq"
		:[index] "+r" (index)
		://[index] "r" (index)
		:
	);
}


//the functions below instantiate isr_entry_macro for 256 vectors (IDT entries)

void isr_entry_00() {
	//isr_entry_macro $0x000
	int arg = 0x000;
	hw_isr_c_wrapper(arg);
}

void isr_entry_01() {
	int arg = 0x001;
	hw_isr_c_wrapper(arg);
}

void isr_entry_02() {
	int arg = 0x002;
	hw_isr_c_wrapper(arg);
}

void isr_entry_03() {
	int arg = 0x003;
	hw_isr_c_wrapper(arg);
}

void isr_entry_04() {
	int arg = 0x004;
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