<commit_before>/**
\defgroup intrinsic_CPU_gr Intrinsic Functions for CPU Instructions
@{
\brief Functions that generate specific Cortex-M CPU Instructions.
\details
The following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler.
Refer to the \ref ref_man_sec for detailed information about these Cortex-M instructions.

\note
When using the <b>Arm Compiler Version 5 Toolchain</b> the following \ref intrinsic_CPU_gr are implemented using the Embedded Assembler. 
As the Embedded Assembler may cause side effects (Refer to <b>Arm Compiler v5.xx User Guide - Using the Inline and Embedded Assemblers of the Arm Compiler</b> for more information)
it is possible to disable the following intrinsic functions and therefore the usage of the Embedded Assembler with the <b><i>define __NO_EMBEDDED_ASM</i></b>: 
 - \ref __REV16
 - \ref __REVSH
 - \ref __RRX


*/
/**************************************************************************************************/
/** \brief  No Operation

    This function does nothing. This instruction can be used for code alignment purposes.
 */
void __NOP(void);


/**************************************************************************************************/
/** \brief  Wait For Interrupt

    WFI is a hint instruction that suspends execution until one of the following events occurs:
    - A non-masked interrupt occurs and is taken.
    - An interrupt masked by PRIMASK becomes pending.
    - A Debug Entry request.
 */
void __WFI(void);


/**************************************************************************************************/
/** \brief  Wait For Event

    Wait For Event is a hint instruction that permits the processor to enter
    a low-power state until an events occurs:
    \li If the <b>event register is 0</b>, then WFE suspends execution until one of the following events occurs:
    - An exception, unless masked by the exception mask registers or the current priority level.
    - An exception enters the Pending state, if SEVONPEND in the System Control Register is set.
    - A Debug Entry request, if Debug is enabled.
    - An event signaled by a peripheral or another processor in a multiprocessor system using
    the SEV instruction.
    
    \li If the <b>event register is 1</b>, then WFE clears it to 0 and returns immediately.
    
 */
void __WFE(void);


/**************************************************************************************************/
/** \brief  Send Event

    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 */
void __SEV(void);


/**************************************************************************************************/
/** \brief  Set Breakpoint

This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.

\param [in]    value  is ignored by the processor. If required, a debugger can use it to obtain additional information about the breakpoint.
*/
void __BKPT(uint8_t value);


/**************************************************************************************************/
/** \brief  Instruction Synchronization Barrier

    Instruction Synchronization Barrier flushes the pipeline in the processor, 
    so that all instructions following the ISB are fetched from cache or 
    memory, after the instruction has been completed.
 */
void __ISB(void);


/**************************************************************************************************/
/** \brief  Data Synchronization Barrier

\details
This function acts as a special kind of Data Memory Barrier. 
It completes when all explicit memory accesses before this instruction complete.
 */
void __DSB(void);


/**************************************************************************************************/
/** \brief  Data Memory Barrier

\details
This function ensures the apparent order of the explicit memory operations before 
and after the instruction, without ensuring their completion.
 */
void __DMB(void);


/**************************************************************************************************/
/**
  \brief   Reverse byte order (32 bit)
  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
uint32_t __REV(uint32_t value);


/**************************************************************************************************/
/**
  \brief   Reverse byte order (16 bit)
  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
uint32_t __REV16(uint32_t value);


/**************************************************************************************************/
/**
  \brief   Reverse byte order (16 bit)
  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
int32_t __REVSH(int32_t value);


/**************************************************************************************************/
/**
  \brief   Reverse bit order of value<commit_msg>Corrected documentation for REVSH -> int16_t __REVSH(int16_t value);<commit_after>/**
\defgroup intrinsic_CPU_gr Intrinsic Functions for CPU Instructions
@{
\brief Functions that generate specific Cortex-M CPU Instructions.
\details
The following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler.
Refer to the \ref ref_man_sec for detailed information about these Cortex-M instructions.

\note
When using the <b>Arm Compiler Version 5 Toolchain</b> the following \ref intrinsic_CPU_gr are implemented using the Embedded Assembler. 
As the Embedded Assembler may cause side effects (Refer to <b>Arm Compiler v5.xx User Guide - Using the Inline and Embedded Assemblers of the Arm Compiler</b> for more information)
it is possible to disable the following intrinsic functions and therefore the usage of the Embedded Assembler with the <b><i>define __NO_EMBEDDED_ASM</i></b>: 
 - \ref __REV16
 - \ref __REVSH
 - \ref __RRX


*/
/**************************************************************************************************/
/** \brief  No Operation

    This function does nothing. This instruction can be used for code alignment purposes.
 */
void __NOP(void);


/**************************************************************************************************/
/** \brief  Wait For Interrupt

    WFI is a hint instruction that suspends execution until one of the following events occurs:
    - A non-masked interrupt occurs and is taken.
    - An interrupt masked by PRIMASK becomes pending.
    - A Debug Entry request.
 */
void __WFI(void);


/**************************************************************************************************/
/** \brief  Wait For Event

    Wait For Event is a hint instruction that permits the processor to enter
    a low-power state until an events occurs:
    \li If the <b>event register is 0</b>, then WFE suspends execution until one of the following events occurs:
    - An exception, unless masked by the exception mask registers or the current priority level.
    - An exception enters the Pending state, if SEVONPEND in the System Control Register is set.
    - A Debug Entry request, if Debug is enabled.
    - An event signaled by a peripheral or another processor in a multiprocessor system using
    the SEV instruction.
    
    \li If the <b>event register is 1</b>, then WFE clears it to 0 and returns immediately.
    
 */
void __WFE(void);


/**************************************************************************************************/
/** \brief  Send Event

    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 */
void __SEV(void);


/**************************************************************************************************/
/** \brief  Set Breakpoint

This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.

\param [in]    value  is ignored by the processor. If required, a debugger can use it to obtain additional information about the breakpoint.
*/
void __BKPT(uint8_t value);


/**************************************************************************************************/
/** \brief  Instruction Synchronization Barrier

    Instruction Synchronization Barrier flushes the pipeline in the processor, 
    so that all instructions following the ISB are fetched from cache or 
    memory, after the instruction has been completed.
 */
void __ISB(void);


/**************************************************************************************************/
/** \brief  Data Synchronization Barrier

\details
This function acts as a special kind of Data Memory Barrier. 
It completes when all explicit memory accesses before this instruction complete.
 */
void __DSB(void);


/**************************************************************************************************/
/** \brief  Data Memory Barrier

\details
This function ensures the apparent order of the explicit memory operations before 
and after the instruction, without ensuring their completion.
 */
void __DMB(void);


/**************************************************************************************************/
/**
  \brief   Reverse byte order (32 bit)
  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
uint32_t __REV(uint32_t value);


/**************************************************************************************************/
/**
  \brief   Reverse byte order (16 bit)
  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
uint32_t __REV16(uint32_t value);


/**************************************************************************************************/
/**
  \brief   Reverse byte order (16 bit)
  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
  \param [in]    value  Value to reverse
  \return               Reversed value
 */
int16_t __REVSH(int16_t value);


/**************************************************************************************************/
/**
  \brief   Reverse bit order of value
{'fraction_non_alphanumeric': 0.2677666144345101, 'fraction_numerical': 0.014747903032537561, 'mean_word_length': 4.465994962216625, 'pattern_counts': {'":': 0, '<': 27, '<?xml version=': 0, '>': 28, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '7542383', 'n_tokens_mistral': 2684, 'n_tokens_neox': 2432, 'n_words': 1139}