<commit_before>create_project -force -part $::env(XRAY_PART) design design

read_verilog ../top.v
synth_design -top top

set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports a]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports y]

create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
set_param tcl.collectionResultDisplayLimit 0

place_design
route_design

write_checkpoint -force design.dcp
# write_bitstream -force design.bit

proc write_clb_ppips_db {filename tile} {
	set fp [open $filename "w"]
	set tile [get_tiles $tile]
	set tile_type [get_property TILE_TYPE $tile]

	foreach pip [get_pips -of_objects $tile] {
		set dst_wire [get_wires -downhill -of_objects $pip]
		if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
			set src_wire [get_wires -uphill -of_objects $pip]
			puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
		}
	}

	close $fp
}

proc write_int_ppips_db {filename tile} {
	set fp [open $filename "w"]
	set tile [get_tiles $tile]<commit_msg>Fix fuzzing of "hint" pseudo-pips<commit_after>create_project -force -part $::env(XRAY_PART) design design

read_verilog ../top.v
synth_design -top top

set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports a]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports y]

create_pblock roi
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
set_param tcl.collectionResultDisplayLimit 0

place_design
route_design

write_checkpoint -force design.dcp
# write_bitstream -force design.bit

proc write_clb_ppips_db {filename tile} {
	set fp [open $filename "w"]
	set tile [get_tiles $tile]
	set tile_type [get_property TILE_TYPE $tile]

	foreach pip [get_pips -of_objects $tile] {
		set dst_wire [get_wires -downhill -of_objects $pip]
		if {[get_property IS_PSEUDO $pip]} {
			set src_wire [get_wires -uphill -of_objects $pip]
			puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] hint"
		} elseif {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
			set src_wire [get_wires -uphill -of_objects $pip]
			puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
		}
	}

	close $fp
}

proc write_int_ppips_db {filename tile} {
	set fp [open $filename "w"]
	set tile [get_tiles $tile]
{'fraction_non_alphanumeric': 0.12181818181818181, 'fraction_numerical': 0.008, 'mean_word_length': 5.338709677419355, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 3, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '2988766', 'n_tokens_mistral': 1119, 'n_tokens_neox': 1067, 'n_words': 264}