<commit_before>#ifndef __CONFIG_H
#define __CONFIG_H

#include <cassert>
#include <string>
#include <utility>
#include <vector>
#include "common.h"

namespace dramcore {

extern std::function<Address(uint64_t)> AddressMapping; //TODO - @shawn - Fix duplicate declaration. Is global really necessary?

enum class DRAMProtocol {
    DDR3,
    DDR4,
    GDDR5,
    GDDR5X,
    LPDDR,
    LPDDR3,
    LPDDR4,
    HBM,
    HBM2,
    HMC,
    SIZE
};

class Config {
public:
    Config(std::string config_file);

    //DRAM physical structure
    DRAMProtocol protocol;
    uint32_t channel_size;
    uint32_t channels;
    uint32_t ranks;
    uint32_t banks;
    uint32_t bankgroups;
    uint32_t banks_per_group;
    uint32_t rows;
    uint32_t columns;
    uint32_t device_width;
    uint32_t bus_width;
    uint32_t BL;

    //Generic DRAM timing parameters
    uint32_t burst_cycle;   // seperate BL with timing since fot GDDRx it's not BL/2
    uint32_t AL;
    uint32_t CL;
    uint32_t CWL;
    uint32_t RL;
    uint32_t WL;
    uint32_t tCCD_L;
    uint32_t tCCD_S;
    uint32_t tRTRS;
    uint32_t tRTP;
    uint32_t tWTR_L;
    uint32_t tWTR_S;
    uint32_t tWR;
    uint32_t tRP;
    uint32_t tRRD_L;
    uint32_t tRRD_S;
    uint32_t tRAS;
    uint32_t tRCD;
    uint32_t tRFC;
    uint32_t tRC;
    uint32_t tCKESR;
    uint32_t tXS;
    uint32_t tRFCb;
    uint32_t tRREFD;
    uint32_t tREFI;
    uint32_t tREFIb;
    uint32_t tFAW;
    uint32_t tRPRE;  // read preamble and write preamble are important
    uint32_t tWPRE;
    uint32_t read_delay;
    uint32_t write_delay;

    // LPDDR4 and GDDR5
    uint32_t tPPD;
    // GDDR5 
    uint32_t t32AW;
    uint32_t tRCDRD;
    uint32_t tRCDWR;

    // HMC 
    unsigned int num_links;
    unsigned int num_dies;
    unsigned int link_width;
    unsigned int link_speed;
    unsigned int num_vaults;
    unsigned int block_size;  // block size in bytes
    unsigned int xbar_queue_depth;

    std::string address_mapping;
    std::string queue_structure;
    uint32_t queue_size;
    std::string refresh_strategy;
    uint32_t idle_cycles_for_self_refresh;
    bool aggressive_precharging_enabled;
    bool req_buffering_enabled;

    std::string validation_output_file;

    uint32_t epoch_period;
    std::string stats_file;
    std::string cummulative_stats_file;
    std::string epoch_stats_file;
    std::string stats_file_csv;
    std::string cummulative_stats_file_csv;
    std::string epoch_stats_file_csv;

    //Computed parameters
    uint32_t channel_width, rank_width, bankgroup_width, bank_width, row_width, column_width, throwaway_bits;

    bool IsGDDR() const {return (protocol == DRAMProtocol::GDDR5 || protocol == DRAMProtocol::GDDR5X);}
    bool IsHBM() const {return (protocol == DRAMProtocol::HBM || protocol == DRAMProtocol::HBM2);}
    bool IsHMC() const {return (protocol == DRAMProtocol::HMC);}
private:
    DRAMProtocol GetDRAMProtocol(std::string protocol_str);
    void CalculateSize();
    void SetAddressMapping();
};

}
#endif
<commit_msg>undo changes for request id...<commit_after>#ifndef __CONFIG_H
#define __CONFIG_H

#include <cassert>
#include <string>
#include <utility>
#include <vector>
#include "common.h"

namespace dramcore {

enum class DRAMProtocol {
    DDR3,
    DDR4,
    GDDR5,
    GDDR5X,
    LPDDR,
    LPDDR3,
    LPDDR4,
    HBM,
    HBM2,
    HMC,
    SIZE
};

class Config {
public:
    Config(std::string config_file);

    //DRAM physical structure
    DRAMProtocol protocol;
    uint32_t channel_size;
    uint32_t channels;
    uint32_t ranks;
    uint32_t banks;
    uint32_t bankgroups;
    uint32_t banks_per_group;
    uint32_t rows;
    uint32_t columns;
    uint32_t device_width;
    uint32_t bus_width;
    uint32_t BL;

    //Generic DRAM timing parameters
    uint32_t burst_cycle;   // seperate BL with timing since fot GDDRx it's not BL/2
    uint32_t AL;
    uint32_t CL;
    uint32_t CWL;
    uint32_t RL;
    uint32_t WL;
    uint32_t tCCD_L;
    uint32_t tCCD_S;
    uint32_t tRTRS;
    uint32_t tRTP;
    uint32_t tWTR_L;
    uint32_t tWTR_S;
    uint32_t tWR;
    uint32_t tRP;
    uint32_t tRRD_L;
    uint32_t tRRD_S;
    uint32_t tRAS;
    uint32_t tRCD;
    uint32_t tRFC;
    uint32_t tRC;
    uint32_t tCKESR;
    uint32_t tXS;
    uint32_t tRFCb;
    uint32_t tRREFD;
    uint32_t tREFI;
    uint32_t tREFIb;
    uint32_t tFAW;
    uint32_t tRPRE;  // read preamble and write preamble are important
    uint32_t tWPRE;
    uint32_t read_delay;
    uint32_t write_delay;

    // LPDDR4 and GDDR5
    uint32_t tPPD;
    // GDDR5 
    uint32_t t32AW;
    uint32_t tRCDRD;
    uint32_t tRCDWR;

    // HMC 
    unsigned int num_links;
    unsigned int num_dies;
    unsigned int link_width;
    unsigned int link_speed;
    unsigned int num_vaults;
    unsigned int block_size;  // block size in bytes
    unsigned int xbar_queue_depth;

    std::string address_mapping;
    std::string queue_structure;
    uint32_t queue_size;
    std::string refresh_strategy;
    uint32_t idle_cycles_for_self_refresh;
    bool aggressive_precharging_enabled;
    bool req_buffering_enabled;

    std::string validation_output_file;

    uint32_t epoch_period;
    std::string stats_file;
    std::string cummulative_stats_file;
    std::string epoch_stats_file;
    std::string stats_file_csv;
    std::string cummulative_stats_file_csv;
    std::string epoch_stats_file_csv;

    //Computed parameters
    uint32_t channel_width, rank_width, bankgroup_width, bank_width, row_width, column_width, throwaway_bits;

    bool IsGDDR() const {return (protocol == DRAMProtocol::GDDR5 || protocol == DRAMProtocol::GDDR5X);}
    bool IsHBM() const {return (protocol == DRAMProtocol::HBM || protocol == DRAMProtocol::HBM2);}
    bool IsHMC() const {return (protocol == DRAMProtocol::HMC);}
private:
    DRAMProtocol GetDRAMProtocol(std::string protocol_str);
    void CalculateSize();
    void SetAddressMapping();
};

}
#endif

{'fraction_non_alphanumeric': 0.07648344259539418, 'fraction_numerical': 0.039334341906202726, 'mean_word_length': 3.2318634423897583, 'pattern_counts': {'":': 0, '<': 12, '<?xml version=': 0, '>': 12, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '1958606', 'n_tokens_mistral': 2362, 'n_tokens_neox': 2201, 'n_words': 524}