<commit_before>-- | Utilities for pipelining streams consisting of data, and valid, ready signals
module Clash.Stream.Pipeline (
        forwardPipeline,
        skidBuffer
    ) where

import Clash.Prelude

-- | Break combinational paths in the forward direction only
forwardPipeline
    :: forall dom a
    .  (HiddenClockResetEnable dom, NFDataX a)
    => Signal dom Bool
    -> Signal dom a
    -> Signal dom Bool
    -> (Signal dom Bool, Signal dom a, Signal dom Bool)
forwardPipeline vldIn datIn readyIn = (vldOut, datOut, readyOut)
    where

    readyOut :: Signal dom Bool
    readyOut =  readyIn .||. fmap not vldOut

    vldOut :: Signal dom Bool
    vldOut =  register False $ vldIn .||. (vldOut .&&. fmap not readyIn)

    datOut :: Signal dom a
    datOut =  regEn (errorX "initial stream pipeline value") readyOut datIn

-- | Break combinational paths in both the forward and reverse directions. https://zipcpu.com/blog/2019/05/22/skidbuffer.html.
skidBuffer
    :: forall dom a
    .  (HiddenClockResetEnable dom, NFDataX a)
    => Signal dom Bool
    -> Signal dom a
    -> Signal dom Bool<commit_msg>forwardPipeline tweaks<commit_after>-- | Utilities for pipelining streams consisting of data, and valid, ready signals
module Clash.Stream.Pipeline (
        forwardPipeline,
        skidBuffer
    ) where

import Clash.Prelude

-- | Break combinational paths in the forward direction only
forwardPipeline
    :: forall dom a
    .  (HiddenClockResetEnable dom, NFDataX a)
    => Signal dom Bool
    -> Signal dom a
    -> Signal dom Bool
    -> (Signal dom Bool, Signal dom a, Signal dom Bool)
forwardPipeline vldIn datIn readyIn = (vldOut, datOut, readyOut)
    where

    readyOut :: Signal dom Bool
    readyOut =  readyIn .||. fmap not vldOut

    vldOut :: Signal dom Bool
    vldOut =  register False $ vldIn .||. fmap not readyOut

    datOut :: Signal dom a
    datOut =  regEn (errorX "initial stream forwardPipeline value") readyOut datIn

-- | Break combinational paths in both the forward and reverse directions. https://zipcpu.com/blog/2019/05/22/skidbuffer.html.
skidBuffer
    :: forall dom a
    .  (HiddenClockResetEnable dom, NFDataX a)
    => Signal dom Bool
    -> Signal dom a
    -> Signal dom Bool
{'fraction_non_alphanumeric': 0.08217954443948192, 'fraction_numerical': 0.007146047342563644, 'mean_word_length': 2.9160839160839163, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 17, 'https://': 2, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '2858107', 'n_tokens_mistral': 719, 'n_tokens_neox': 660, 'n_words': 245}