<commit_before>package fpgatidbits

import Chisel._
import fpgatidbits.Testbenches._
import fpgatidbits.ocm._
import fpgatidbits.streams._
import fpgatidbits.SimUtils._
import fpgatidbits.axi._
import fpgatidbits.dma._
import fpgatidbits.PlatformWrapper._
import fpgatidbits.hlstools._
import java.io.{File,FileInputStream,FileOutputStream}
import sys.process._

object TidbitsMakeUtils {
  type AccelInstFxn = PlatformWrapperParams => GenericAccelerator
  type PlatformInstFxn = AccelInstFxn => PlatformWrapper
  type PlatformMap = Map[String, PlatformInstFxn]

  val platformMap: PlatformMap = Map(
    "ZedBoard" -> {f => new ZedBoardWrapper(f)},
    "PYNQZ1" -> {f => new PYNQZ1Wrapper(f)},
    "PYNQU96" -> {f => new PYNQU96Wrapper(f)},
    "PYNQU96CC" -> {f => new PYNQU96CCWrapper(f)},
    "GenericSDAccel" -> {f => new GenericSDAccelWrapper(f)},
    "ZC706" -> {f => new ZC706Wrapper(f)},
    "WX690T" -> {f => new WolverinePlatformWrapper(f)},
    "VerilatedTester" -> {f => new VerilatedTesterWrapper(f)},
    "Tester" -> {f => new TesterWrapper(f)}
  )

  // handy to have a few commonly available Xilinx FPGA boards here
  val fpgaPartMap = Map(
    "ZedBoard" -> "xc7z020clg400-1",
    "PYNQZ1" -> "xc7z020clg400-1",
    "PYNQU96" -> "xczu3eg-sbva484-1-i",
    "PYNQU96CC" -> "xczu3eg-sbva484-1-i",
    "ZC706" -> "xc7z045ffg900-2",
    "KU115" -> "xcku115-flvb2104-2-e",
    "VerilatedTester" -> "xczu3eg-sbva484-1-i", // use Ultra96 part for tester
    "VU9P" -> "xcvu9p-flgb2104-2-i"
  )

  def fileCopy(from: String, to: String) = {
    s"cp -f $from $to" !
  }

  def fileCopyBulk(fromDir: String, toDir: String, fileNames: Seq[String]) = {
    for(f <- fileNames)
      fileCopy(s"$fromDir/$f", s"$toDir/$f")
  }

  def makeEmulatorLibrary(accInst: AccelInstFxn, outDir: String, gOpts: Seq[String] = Seq(), chiselOpts: Seq[String] = Seq()) = {
    val fullDir = s"realpath $outDir".!!.filter(_ >= ' ')
    val platformInst = platformMap("Tester")
    val drvDir = getClass.getResource("/cpp/platform-wrapper-regdriver").getPath
    val chiselArgs = Array("--backend","c","--targetDir", fullDir) ++ chiselOpts

    chiselMain(chiselArgs, () => Module(platformInst(accInst)))
    val p = platformInst(accInst)
    // build reg driver
    p.generateRegDriver(s"$fullDir")
    // copy emulator driver and SW support files<commit_msg>[ZCU104] add ZCU104 platforms to TidbitsMakeUtils<commit_after>package fpgatidbits

import Chisel._
import fpgatidbits.Testbenches._
import fpgatidbits.ocm._
import fpgatidbits.streams._
import fpgatidbits.SimUtils._
import fpgatidbits.axi._
import fpgatidbits.dma._
import fpgatidbits.PlatformWrapper._
import fpgatidbits.hlstools._
import java.io.{File,FileInputStream,FileOutputStream}
import sys.process._

object TidbitsMakeUtils {
  type AccelInstFxn = PlatformWrapperParams => GenericAccelerator
  type PlatformInstFxn = AccelInstFxn => PlatformWrapper
  type PlatformMap = Map[String, PlatformInstFxn]

  val platformMap: PlatformMap = Map(
    "ZedBoard" -> {f => new ZedBoardWrapper(f)},
    "PYNQZ1" -> {f => new PYNQZ1Wrapper(f)},
    "PYNQU96" -> {f => new PYNQU96Wrapper(f)},
    "PYNQU96CC" -> {f => new PYNQU96CCWrapper(f)},
    "PYNQZCU104" -> {f => new PYNQZCU104Wrapper(f)},
    "PYNQZCU104CC" -> {f => new PYNQZCU104CCWrapper(f)},
    "GenericSDAccel" -> {f => new GenericSDAccelWrapper(f)},
    "ZC706" -> {f => new ZC706Wrapper(f)},
    "WX690T" -> {f => new WolverinePlatformWrapper(f)},
    "VerilatedTester" -> {f => new VerilatedTesterWrapper(f)},
    "Tester" -> {f => new TesterWrapper(f)}
  )

  // handy to have a few commonly available Xilinx FPGA boards here
  val fpgaPartMap = Map(
    "ZedBoard" -> "xc7z020clg400-1",
    "PYNQZ1" -> "xc7z020clg400-1",
    "PYNQU96" -> "xczu3eg-sbva484-1-i",
    "PYNQU96CC" -> "xczu3eg-sbva484-1-i",
    "PYNQZCU104" -> "xczu7ev-ffvc1156-2-e",
    "PYNQZCU104CC" -> "xczu7ev-ffvc1156-2-e",
    "ZC706" -> "xc7z045ffg900-2",
    "KU115" -> "xcku115-flvb2104-2-e",
    "VerilatedTester" -> "xczu3eg-sbva484-1-i", // use Ultra96 part for tester
    "VU9P" -> "xcvu9p-flgb2104-2-i"
  )

  def fileCopy(from: String, to: String) = {
    s"cp -f $from $to" !
  }

  def fileCopyBulk(fromDir: String, toDir: String, fileNames: Seq[String]) = {
    for(f <- fileNames)
      fileCopy(s"$fromDir/$f", s"$toDir/$f")
  }

  def makeEmulatorLibrary(accInst: AccelInstFxn, outDir: String, gOpts: Seq[String] = Seq(), chiselOpts: Seq[String] = Seq()) = {
    val fullDir = s"realpath $outDir".!!.filter(_ >= ' ')
    val platformInst = platformMap("Tester")
    val drvDir = getClass.getResource("/cpp/platform-wrapper-regdriver").getPath
    val chiselArgs = Array("--backend","c","--targetDir", fullDir) ++ chiselOpts

    chiselMain(chiselArgs, () => Module(platformInst(accInst)))
    val p = platformInst(accInst)
    // build reg driver
    p.generateRegDriver(s"$fullDir")
    // copy emulator driver and SW support files
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{'dir': 'git-commits-cleaned', 'id': '2349620', 'n_tokens_mistral': 2051, 'n_tokens_neox': 1905, 'n_words': 366}