<commit_before>Spike Hardware
==============

This project provides hardware peripherals to spike, the RISC-V ISA
simulator.

TODO
----

 * device tree partitioning of flash
   * added to riscv_spikehw_defconfig (DONE)
   * device tree entry for flash works (DONE)
   * device tree entry for partitions works (registers)
   * vmlinux partition (DONE)
   * root partition (DONE)
 * spikehw registering a flash device with spike (DONE)
 * copy vmlinux to flash
 * pass address of vmlinux in flash to bbl
 * modify spike to boot from boot rom if no executable passed as an argument
 * ...

Building SpikeHW
----------------

To get the sources:

    git clone git://github.com/cambridgehackers/fpgamake
    git clone git://github.com/cambridgehackers/buildcache
    git clone git://github.com/cambridgehackers/connectal

I extended spike to enable devices to be registered from extlib's.

    git clone git://github.com/cambridgehackers/cambridgehackers/riscv-isa-sim

    cd connectal/tests/spikehw
    make build.vc707g2 test-spikehw.vc707g2

To test it, assuming connectal is installed:

    cd connectal/tests/spikehw
    ./test-spikehw.vc707g2

You should see output like the following:

    jamey@bdbm07:~/connectal/tests/spikehw$ ./test-spikehw.vc707g2
    buffer /home/jamey/connectal/tests/spikehw/vc707g2/bin/connectal.so
    fpgajtag: elf input file, len 1459190 class 2
    fpgajtag: unzip input file, len 1040655
    fpgajtag: Digilent:Digilent Adept USB Device:210203860922; bcd:700<commit_msg>this version was able to boot vmlinux from the FPGA parallel flash<commit_after>Spike Hardware
==============

This project provides hardware peripherals to spike, the RISC-V ISA
simulator.

TODO
----

 * device tree partitioning of flash
   * added to riscv_spikehw_defconfig (DONE)
   * device tree entry for flash works (DONE)
   * device tree entry for partitions works (registers)
   * vmlinux partition (DONE)
   * root partition (DONE)
 * spikehw registering a flash device with spike (DONE)
 * restore console input (wtf)
 * copy vmlinux to flash (via /etc/init.d/rc) (DONE?)
 * pass address of vmlinux in flash to bbl (in riscy version of riscv-pk)
 * boot vmlinux from flash to login prompt (DONE)

 * modify spike to boot from boot rom if no executable passed as an argument
 * update /etc/default/volatiles for read only root
 * change /etc/default/rcS ROOTFS_READ_ONLY=yes
 * modify spike to use portalmem for dram so DMA from FPGA works
 * fix ioremap() so that all 128MB of flash can be mapped
 * switch to coreboot instead of bbl
 * ...

Building SpikeHW
----------------

To get the sources:

    git clone git://github.com/cambridgehackers/fpgamake
    git clone git://github.com/cambridgehackers/buildcache
    git clone git://github.com/cambridgehackers/connectal

I extended spike to enable devices to be registered from extlib's.

    git clone git://github.com/cambridgehackers/cambridgehackers/riscv-isa-sim

    cd connectal/tests/spikehw
    make build.vc707g2 test-spikehw.vc707g2

To test it, assuming connectal is installed:

    cd connectal/tests/spikehw
    ./test-spikehw.vc707g2

You should see output like the following:

    jamey@bdbm07:~/connectal/tests/spikehw$ ./test-spikehw.vc707g2
    buffer /home/jamey/connectal/tests/spikehw/vc707g2/bin/connectal.so
    fpgajtag: elf input file, len 1459190 class 2
    fpgajtag: unzip input file, len 1040655
    fpgajtag: Digilent:Digilent Adept USB Device:210203860922; bcd:700
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