<commit_before>[BITS 32]

extern kmain
extern idtp
extern irq_handler
extern gdt_pointer
extern generic_interrupt_handler
extern disable_preemption
extern save_current_task_state
extern schedule_outside_interrupt_context

global gdt_load
global idt_load
global tss_flush
global _start
global asm_context_switch_x86
global asm_kernel_context_switch_x86
global kernel_yield
global panic_save_current_state

section .text

_start:

   ; before jump to kernel, we have to setup a basic paging
   ; in order to map the kernel from 0x100000 to 0xC0000000 (+3 GB)

   ; let's put the page directory at 0x1000 (+ 4 KB)

   mov edi, 0x1000

   .l1:
   mov dword [edi], 0
   add edi, 4
   cmp edi, 0x2000
   jne .l1

   ; let's put the first page table at 0x2000 (+ 8 KB)
   mov eax, 0
   .l2:

   mov ebx, eax
   or ebx, 3  ; present, rw
   mov [edi], ebx

   add eax, 0x1000 ; += 4K
   add edi, 4

   cmp edi, 0x3000
   jne .l2

   ; xchg bx, bx ; bochs magic break

   mov eax, 0x2003    ; = 0x2000 | preset,rw

   ; identity map the first low 4 MB
   ; this is necessary for executing the 'jmp eax' below)
   ; otherwise, just after 'mov cr0, eax', EIP will point to an invalid address

   mov [0x1000], eax
   mov [0x1C00], eax  ; map them also to 0xC0000000

   mov ebx, 0x1000
   mov cr3, ebx     ; set page dir physical address

   mov eax, cr0
   or eax, 0x80000000 ; paging ON
   or eax, 0x10000    ; WP ON (write protect for supervisor)
   mov cr0, eax       ; enable paging!

   mov eax, 0xC0100400
   jmp eax        ; jump to next instruction using the high virtual address

   times 1024-($-$$) db 0

   ; the current EIP is 0xC0100400

   mov esp, 0xC000FFF0 ; +64 KB - 16
   jmp kmain   ; now, really jump to kernel's code which uses 0xC0100000 as ORG

gdt_load:
   lgdt [gdt_pointer]
   ret

idt_load:
    lidt [idtp]
    ret

tss_flush:
   mov ax, 0x2B      ; Load the index of our TSS structure - The index is
                     ; 0x28, as it is the 5th selector and each is 8 bytes
                     ; long, but we set the bottom two bits (making 0x2B)
                     ; so that it has an RPL of 3, not zero.
   ltr ax            ; Load 0x2B into the task state register.
   ret


asm_context_switch_x86:

   pop eax ; return addr (ignored)
<commit_msg>[kernel boot] Removing an useless waste of 1K in kernelAsm<commit_after>[BITS 32]

extern kmain
extern idtp
extern irq_handler
extern gdt_pointer
extern generic_interrupt_handler
extern disable_preemption
extern save_current_task_state
extern schedule_outside_interrupt_context

global gdt_load
global idt_load
global tss_flush
global _start
global asm_context_switch_x86
global asm_kernel_context_switch_x86
global kernel_yield
global panic_save_current_state

section .text

_start:

   ; before jump to kernel, we have to setup a basic paging
   ; in order to map the kernel from 0x100000 to 0xC0000000 (+3 GB)

   ; let's put the page directory at 0x1000 (+ 4 KB)

   mov edi, 0x1000

   .l1:
   mov dword [edi], 0
   add edi, 4
   cmp edi, 0x2000
   jne .l1

   ; let's put the first page table at 0x2000 (+ 8 KB)
   mov eax, 0
   .l2:

   mov ebx, eax
   or ebx, 3  ; present, rw
   mov [edi], ebx

   add eax, 0x1000 ; += 4K
   add edi, 4

   cmp edi, 0x3000
   jne .l2

   ; xchg bx, bx ; bochs magic break

   mov eax, 0x2003    ; = 0x2000 | preset,rw

   ; identity map the first low 4 MB
   ; this is necessary for executing the 'jmp eax' below)
   ; otherwise, just after 'mov cr0, eax', EIP will point to an invalid address

   mov [0x1000], eax
   mov [0x1C00], eax  ; map them also to 0xC0000000

   mov ebx, 0x1000
   mov cr3, ebx     ; set page dir physical address

   mov eax, cr0
   or eax, 0x80000000 ; paging ON
   or eax, 0x10000    ; WP ON (write protect for supervisor)
   mov cr0, eax       ; enable paging!

   mov eax, .next_step
   jmp eax        ; Jump to next instruction using the high virtual address.

                  ; This is necessary since here the EIP is still a physical
                  ; address, while in the kernel the physical identity mapping
                  ; is removed. We need to continue using high (+3 GB)
                  ; virtual addresses. The trick works because this file is
                  ; part of the original kernel ELF binary where the ORG
                  ; is set to +3 GB.

.next_step:
   mov esp, 0xC000FFF0 ; +64 KB - 16
   jmp kmain   ; now, really jump to kernel's code which uses 0xC0100000 as ORG

gdt_load:
   lgdt [gdt_pointer]
   ret

idt_load:
    lidt [idtp]
    ret

tss_flush:
   mov ax, 0x2B      ; Load the index of our TSS structure - The index is
                     ; 0x28, as it is the 5th selector and each is 8 bytes
                     ; long, but we set the bottom two bits (making 0x2B)
                     ; so that it has an RPL of 3, not zero.
   ltr ax            ; Load 0x2B into the task state register.
   ret


asm_context_switch_x86:

   pop eax ; return addr (ignored)

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