<commit_before>/*
 * Copyright (c) 2018 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/** @file
 * @brief I2S bus (SSP) driver for Intel CAVS.
 *
 * Limitations:
 * - DMA is used in simple single block transfer mode (with linked list
 *   enabled) and "interrupt on full transfer completion" mode.
 */

#include <errno.h>
#include <string.h>
#include <sys/__assert.h>
#include <kernel.h>
#include <device.h>
#include <init.h>
#include <drivers/dma.h>
#include <drivers/i2s.h>
#include <soc.h>
#include "i2s_cavs.h"

#define LOG_DOMAIN dev_i2s_cavs
#define LOG_LEVEL CONFIG_I2S_LOG_LEVEL
#include <logging/log.h>
LOG_MODULE_REGISTER(LOG_DOMAIN);

#define I2S_IRQ_CONNECT(i2s_id)					\
	IRQ_CONNECT(I2S##i2s_id##_CAVS_IRQ,			\
			CONFIG_I2S_CAVS_IRQ_PRI,		\
			i2s_cavs_isr,				\
			DEVICE_GET(i2s##i2s_id##_cavs), 0)

#define I2S_DEVICE_NAME(i2s_id)		i2s##i2s_id##_cavs
#define I2S_DEVICE_DATA_NAME(i2s_id)	i2s##i2s_id##_cavs_data
#define I2S_DEVICE_CONFIG_NAME(i2s_id)	i2s##i2s_id##_cavs_config

#define I2S_DEVICE_CONFIG_DEFINE(i2s_id)				\
	static const struct i2s_cavs_config i2s##i2s_id##_cavs_config = {\
		.regs = (struct i2s_cavs_ssp *)SSP_BASE(i2s_id),	\
		.mn_regs = (struct i2s_cavs_mn_div *)SSP_MN_DIV_BASE(i2s_id),\
		.irq_id = I2S##i2s_id##_CAVS_IRQ,		\
		.irq_connect = i2s##i2s_id##_cavs_irq_connect,	\
	}

#define I2S_DMA_CHANNEL(i2s_id, dir)				\
		CONFIG_I2S_CAVS_##i2s_id##_DMA_##dir##_CHANNEL

#define I2S_DEVICE_OBJECT_DECLARE(i2s_id)			\
	DEVICE_DECLARE(I2S_DEVICE_NAME(i2s_id))

#define I2S_DEVICE_OBJECT(i2s_id)				\
		DEVICE_GET(I2S_DEVICE_NAME(i2s_id))

#define I2S_DEVICE_DATA_DEFINE(i2s_id)				\
	static struct i2s_cavs_dev_data i2s##i2s_id##_cavs_data = {\
		.tx = {						\
			.dma_channel = I2S_DMA_CHANNEL(i2s_id, TX),	\
			.dma_cfg = {				\
				.source_burst_length = CAVS_I2S_DMA_BURST_SIZE,\
				.dest_burst_length = CAVS_I2S_DMA_BURST_SIZE,\
				.dma_callback = i2s_dma_tx_callback,	\
				.user_data = I2S_DEVICE_OBJECT(i2s_id),\
				.complete_callback_en = 1,	\
				.error_callback_en = 1,		\
				.block_count = 1,		\
				.head_block =			\
				&i2s##i2s_id##_cavs_data.tx.dma_block,\
				.channel_direction = MEMORY_TO_PERIPHERAL,\
				.dma_slot = DMA_HANDSHAKE_SSP##i2s_id##_TX,\
			},					\
		},						\
		.rx = {						\
			.dma_channel = I2S_DMA_CHANNEL(i2s_id, RX),	\
			.dma_cfg = {				\
				.source_burst_length = CAVS_I2S_DMA_BURST_SIZE,\
				.dest_burst_length = CAVS_I2S_DMA_BURST_SIZE,\
				.dma_callback = i2s_dma_rx_callback,\
				.user_data = I2S_DEVICE_OBJECT(i2s_id),\
				.complete_callback_en = 1,	\
				.error_callback_en = 1,		\
				.block_count = 1,		\
				.head_block =			\
				&i2s##i2s_id##_cavs_data.rx.dma_block,\
				.channel_direction = PERIPHERAL_TO_MEMORY,\
				.dma_slot = DMA_HANDSHAKE_SSP##i2s_id##_RX,\
				},				\
		},						\
	}

#define I2S_DEVICE_AND_API_INIT(i2s_id)				\
	DEVICE_AND_API_INIT(I2S_DEVICE_NAME(i2s_id),		\
			CONFIG_I2S_CAVS_##i2s_id##_NAME,	\
			i2s_cavs_initialize,			\
			&I2S_DEVICE_DATA_NAME(i2s_id),		\
			&I2S_DEVICE_CONFIG_NAME(i2s_id),	\
			POST_KERNEL,				\
			CONFIG_I2S_INIT_PRIORITY,		\
			&i2s_cavs_driver_api)

/* length of the buffer queue */
#define I2S_CAVS_BUF_Q_LEN			2

#define CAVS_SSP_WORD_SIZE_BITS_MIN     4
#define CAVS_SSP_WORD_SIZE_BITS_MAX     32<commit_msg>i2s: cavs: cast device struct to void ptr for DMA user data<commit_after>/*
 * Copyright (c) 2018 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/** @file
 * @brief I2S bus (SSP) driver for Intel CAVS.
 *
 * Limitations:
 * - DMA is used in simple single block transfer mode (with linked list
 *   enabled) and "interrupt on full transfer completion" mode.
 */

#include <errno.h>
#include <string.h>
#include <sys/__assert.h>
#include <kernel.h>
#include <device.h>
#include <init.h>
#include <drivers/dma.h>
#include <drivers/i2s.h>
#include <soc.h>
#include "i2s_cavs.h"

#define LOG_DOMAIN dev_i2s_cavs
#define LOG_LEVEL CONFIG_I2S_LOG_LEVEL
#include <logging/log.h>
LOG_MODULE_REGISTER(LOG_DOMAIN);

#define I2S_IRQ_CONNECT(i2s_id)					\
	IRQ_CONNECT(I2S##i2s_id##_CAVS_IRQ,			\
			CONFIG_I2S_CAVS_IRQ_PRI,		\
			i2s_cavs_isr,				\
			DEVICE_GET(i2s##i2s_id##_cavs), 0)

#define I2S_DEVICE_NAME(i2s_id)		i2s##i2s_id##_cavs
#define I2S_DEVICE_DATA_NAME(i2s_id)	i2s##i2s_id##_cavs_data
#define I2S_DEVICE_CONFIG_NAME(i2s_id)	i2s##i2s_id##_cavs_config

#define I2S_DEVICE_CONFIG_DEFINE(i2s_id)				\
	static const struct i2s_cavs_config i2s##i2s_id##_cavs_config = {\
		.regs = (struct i2s_cavs_ssp *)SSP_BASE(i2s_id),	\
		.mn_regs = (struct i2s_cavs_mn_div *)SSP_MN_DIV_BASE(i2s_id),\
		.irq_id = I2S##i2s_id##_CAVS_IRQ,		\
		.irq_connect = i2s##i2s_id##_cavs_irq_connect,	\
	}

#define I2S_DMA_CHANNEL(i2s_id, dir)				\
		CONFIG_I2S_CAVS_##i2s_id##_DMA_##dir##_CHANNEL

#define I2S_DEVICE_OBJECT_DECLARE(i2s_id)			\
	DEVICE_DECLARE(I2S_DEVICE_NAME(i2s_id))

#define I2S_DEVICE_OBJECT(i2s_id)				\
		DEVICE_GET(I2S_DEVICE_NAME(i2s_id))

#define I2S_DEVICE_DATA_DEFINE(i2s_id)				\
	static struct i2s_cavs_dev_data i2s##i2s_id##_cavs_data = {\
		.tx = {						\
			.dma_channel = I2S_DMA_CHANNEL(i2s_id, TX),	\
			.dma_cfg = {				\
				.source_burst_length = CAVS_I2S_DMA_BURST_SIZE,\
				.dest_burst_length = CAVS_I2S_DMA_BURST_SIZE,\
				.dma_callback = i2s_dma_tx_callback,	\
				.user_data = (void *)I2S_DEVICE_OBJECT(i2s_id),\
				.complete_callback_en = 1,	\
				.error_callback_en = 1,		\
				.block_count = 1,		\
				.head_block =			\
				&i2s##i2s_id##_cavs_data.tx.dma_block,\
				.channel_direction = MEMORY_TO_PERIPHERAL,\
				.dma_slot = DMA_HANDSHAKE_SSP##i2s_id##_TX,\
			},					\
		},						\
		.rx = {						\
			.dma_channel = I2S_DMA_CHANNEL(i2s_id, RX),	\
			.dma_cfg = {				\
				.source_burst_length = CAVS_I2S_DMA_BURST_SIZE,\
				.dest_burst_length = CAVS_I2S_DMA_BURST_SIZE,\
				.dma_callback = i2s_dma_rx_callback,\
				.user_data = (void *)I2S_DEVICE_OBJECT(i2s_id),\
				.complete_callback_en = 1,	\
				.error_callback_en = 1,		\
				.block_count = 1,		\
				.head_block =			\
				&i2s##i2s_id##_cavs_data.rx.dma_block,\
				.channel_direction = PERIPHERAL_TO_MEMORY,\
				.dma_slot = DMA_HANDSHAKE_SSP##i2s_id##_RX,\
				},				\
		},						\
	}

#define I2S_DEVICE_AND_API_INIT(i2s_id)				\
	DEVICE_AND_API_INIT(I2S_DEVICE_NAME(i2s_id),		\
			CONFIG_I2S_CAVS_##i2s_id##_NAME,	\
			i2s_cavs_initialize,			\
			&I2S_DEVICE_DATA_NAME(i2s_id),		\
			&I2S_DEVICE_CONFIG_NAME(i2s_id),	\
			POST_KERNEL,				\
			CONFIG_I2S_INIT_PRIORITY,		\
			&i2s_cavs_driver_api)

/* length of the buffer queue */
#define I2S_CAVS_BUF_Q_LEN			2

#define CAVS_SSP_WORD_SIZE_BITS_MIN     4
#define CAVS_SSP_WORD_SIZE_BITS_MAX     32
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