<commit_before>

Arquivos de teste
~/Dropbox/CSOC-DFT-Tests/dft-psynth/atpg/testresults/verilog/VER.FULLSCAN.capeta_soc_pads_atpg.data.logic.ex1.ts2
~/Dropbox/CSOC-DFT-Tests/dft-psynth/atpg/testresults/verilog/VER.FULLSCAN.capeta_soc_pads_atpg.data.scan.ex1.ts1

Codigos de comando dentro do arquivo de ATPG (Cadence ET)
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901<commit_msg>Updating<commit_after>
# ATPG Files
<!-- ~/Dropbox/CSOC-DFT-Tests/dft-psynth/atpg/testresults/verilog/VER.FULLSCAN.capeta_soc_pads_atpg.data.logic.ex1.ts2
~/Dropbox/CSOC-DFT-Tests/dft-psynth/atpg/testresults/verilog/VER.FULLSCAN.capeta_soc_pads_atpg.data.scan.ex1.ts1
 -->
- `VER.FULLSCAN.capeta_soc_pads_atpg.data.logic.ex1.ts2`
- `VER.FULLSCAN.capeta_soc_pads_atpg.data.scan.ex1.ts1`

# ATPG Commnads
Codigos de comando dentro do arquivo de ATPG (Cadence ET)
- `000`: 
- `100`: 
- `200`: 
- `201`: 
- `202`: 
- `203`: 
- `300`: 
- `301`: 
- `400`: 
- `500`: 
- `501`: 
- `600`: 
- `100`: 
- `900`: 
- `901`: 

# Setup
<img src="samples/verilog/csoc_test/setup.svg"  width="600px">

# FPGA
<img src="samples/verilog/csoc_test/blocks.svg" width="600px">
{'fraction_non_alphanumeric': 0.16681222707423582, 'fraction_numerical': 0.0943231441048035, 'mean_word_length': 4.162162162162162, 'pattern_counts': {'":': 0, '<': 6, '<?xml version=': 0, '>': 6, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '2902658', 'n_tokens_mistral': 632, 'n_tokens_neox': 548, 'n_words': 72}