<commit_before>/*-
 * Copyright (c) 2003 <NAME>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * $FreeBSD$
 */

#ifndef _DEV_IC_Z8530_H_
#define	_DEV_IC_Z8530_H_

/*
 * Channel B control:	0
 * Channel B data:	1
 * Channel A control:	2
 * Channel A data:	3
 *
 * We expect a seperate subregion for each channel.
 */
#define	REG_CTRL	0
#define	REG_DATA	1

/* Write registers. */
#define	WR_CR		0	/* Command Register. */
#define	WR_IDT		1	/* Interrupt and Data Transfer Mode. */
#define	WR_IV		2	/* Interrupt Vector (shared). */
#define	WR_RPC		3	/* Receive Parameters and Control. */
#define	WR_MPM		4	/* Miscellaneous Parameters and Modes. */
#define	WR_TPC		5	/* Transmit Parameters and Control. */
#define	WR_SCAF		6	/* Sync Character or (SDLC) Address Field. */
#define	WR_SCF		7	/* Sync Character or (SDCL) Flag. */
#define	WR_EFC		7	/* Extended Feature and FIFO Control. */
#define	WR_TB		8	/* Transmit Buffer. */
#define	WR_MIC		9	/* Master Interrupt Control (shared). */
#define	WR_MCB1		10	/* Miscellaneous Control Bits (part 1 :-). */
#define	WR_CMC		11	/* Clock Mode Control. */
#define	WR_TCL		12	/* BRG Time Constant Low. */
#define	WR_TCH		13	/* BRG Time Constant High. */
#define	WR_MCB2		14	/* Miscellaneous Control Bits (part 2 :-). */
#define	WR_IC		15	/* Interrupt Control. */

/* Read registers. */
#define	RR_BES		0	/* Buffer and External Status. */
#define	RR_SRC		1	/* Special Receive Condition. */
#define	RR_IV		2	/* Interrupt Vector. */
#define	RR_IP		3	/* Interrupt Pending (ch A only). */
#define	RR_MPM		4	/* Miscellaneous Parameters and Modes. */
#define	RR_TPC		5	/* Transmit Parameters and Control. */
#define	RR_BCL		6	/* Byte Count Low. */
#define	RR_BCH		7	/* Byte Count High. */
#define	RR_RB		8	/* Receive Buffer. */
#define	RR_RPC		9	/* Receive Parameters and Contro. */
#define	RR_MSB		10	/* Miscellaneous Status Bits. */
#define	RR_MCB1		11	/* Miscellaneous Control Bits (part 1). */
#define	RR_TCL		12	/* BRG Time Constant Low. */
#define	RR_TCH		13	/* BRG Time Constant High. */
#define	RR_EFC		14	/* Extended Feature and FIFO Control. */
#define	RR_IC		15	/* Interrupt Control. */

/* Buffer and External Status (RR0). */
#define	BES_BRK		0x80	/* Break (Abort). */
#define	BES_TXU		0x40	/* Tx Underrun (EOM). */
#define	BES_CTS		0x20	/* CTS. */
#define	BES_SYNC	0x10	/* Sync. */
#define	BES_DCD		0x08	/* DCD. */
#define	BES_TXE		0x04	/* Tx Empty. */<commit_msg>MFp4: Add CHAN_A & CHAN_B for channel register offsets. While here, fix a comment.<commit_after>/*-
 * Copyright (c) 2003 <NAME>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * $FreeBSD$
 */

#ifndef _DEV_IC_Z8530_H_
#define	_DEV_IC_Z8530_H_

/*
 * Channel B control:	0
 * Channel B data:	1
 * Channel A control:	2
 * Channel A data:	3
 */

/* The following apply when using a device-scoped bus handle */
#define	CHAN_A		2
#define	CHAN_B		0

#define	REG_CTRL	0
#define	REG_DATA	1

/* Write registers. */
#define	WR_CR		0	/* Command Register. */
#define	WR_IDT		1	/* Interrupt and Data Transfer Mode. */
#define	WR_IV		2	/* Interrupt Vector (shared). */
#define	WR_RPC		3	/* Receive Parameters and Control. */
#define	WR_MPM		4	/* Miscellaneous Parameters and Modes. */
#define	WR_TPC		5	/* Transmit Parameters and Control. */
#define	WR_SCAF		6	/* Sync Character or (SDLC) Address Field. */
#define	WR_SCF		7	/* Sync Character or (SDCL) Flag. */
#define	WR_EFC		7	/* Extended Feature and FIFO Control. */
#define	WR_TB		8	/* Transmit Buffer. */
#define	WR_MIC		9	/* Master Interrupt Control (shared). */
#define	WR_MCB1		10	/* Miscellaneous Control Bits (part 1 :-). */
#define	WR_CMC		11	/* Clock Mode Control. */
#define	WR_TCL		12	/* BRG Time Constant Low. */
#define	WR_TCH		13	/* BRG Time Constant High. */
#define	WR_MCB2		14	/* Miscellaneous Control Bits (part 2 :-). */
#define	WR_IC		15	/* Interrupt Control. */

/* Read registers. */
#define	RR_BES		0	/* Buffer and External Status. */
#define	RR_SRC		1	/* Special Receive Condition. */
#define	RR_IV		2	/* Interrupt Vector. */
#define	RR_IP		3	/* Interrupt Pending (ch A only). */
#define	RR_MPM		4	/* Miscellaneous Parameters and Modes. */
#define	RR_TPC		5	/* Transmit Parameters and Control. */
#define	RR_BCL		6	/* Byte Count Low. */
#define	RR_BCH		7	/* Byte Count High. */
#define	RR_RB		8	/* Receive Buffer. */
#define	RR_RPC		9	/* Receive Parameters and Control. */
#define	RR_MSB		10	/* Miscellaneous Status Bits. */
#define	RR_MCB1		11	/* Miscellaneous Control Bits (part 1). */
#define	RR_TCL		12	/* BRG Time Constant Low. */
#define	RR_TCH		13	/* BRG Time Constant High. */
#define	RR_EFC		14	/* Extended Feature and FIFO Control. */
#define	RR_IC		15	/* Interrupt Control. */

/* Buffer and External Status (RR0). */
#define	BES_BRK		0x80	/* Break (Abort). */
#define	BES_TXU		0x40	/* Tx Underrun (EOM). */
#define	BES_CTS		0x20	/* CTS. */
#define	BES_SYNC	0x10	/* Sync. */
#define	BES_DCD		0x08	/* DCD. */
#define	BES_TXE		0x04	/* Tx Empty. */
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