<commit_before>; =============================================================================
; BareMetal -- a 64-bit OS written in Assembly for x86-64 systems
; Copyright (C) 2008-2014 Return Infinity -- see LICENSE.TXT
;
; Intel i8254x NIC.
; =============================================================================

align 16
db 'DEBUG: I8254X   '
align 16


; -----------------------------------------------------------------------------
; Initialize an Intel 8254x NIC
;  IN:	BL  = Bus number of the Intel device
;	CL  = Device/Slot number of the Intel device
os_net_i8254x_init:
	push rsi
	push rdx
	push rcx
	push rax

	; Read BAR4, If BAR4 is all 0'z then we are using 32-bit addresses

	; Grab the Base I/O Address of the device
	mov dl, 0x04				; BAR0
	call os_pci_read_reg
	and eax, 0xFFFFFFF0			; EAX now holds the Base Memory IO Address (clear the low 4 bits)
	mov dword [os_NetIOBaseMem], eax

	; Grab the IRQ of the device
	mov dl, 0x0F				; Get device's IRQ number from PCI Register 15 (IRQ is bits 7-0)
	call os_pci_read_reg
	mov [os_NetIRQ], al			; AL holds the IRQ

	; Grab the MAC address
	mov rsi, [os_NetIOBaseMem]
	mov eax, [rsi+0x5400]				; RAL
	cmp eax, 0x00000000
	je os_net_i8254x_init_get_MAC_via_EPROM
	mov [os_NetMAC], al
	shr eax, 8
	mov [os_NetMAC+1], al
	shr eax, 8
	mov [os_NetMAC+2], al
	shr eax, 8
	mov [os_NetMAC+3], al
	mov eax, [rsi+0x5404]				; RAH
	mov [os_NetMAC+4], al
	shr eax, 8
	mov [os_NetMAC+5], al
	jmp os_net_i8254x_init_done_MAC

os_net_i8254x_init_get_MAC_via_EPROM:
	mov rsi, [os_NetIOBaseMem]
	mov eax, 0x00000001
	mov [rsi+0x14], eax
	mov eax, [rsi+0x14]
	shr eax, 16
	mov [os_NetMAC], al
	shr eax, 8
	mov [os_NetMAC+1], al
	mov eax, 0x00000101
	mov [rsi+0x14], eax
	mov eax, [rsi+0x14]
	shr eax, 16
	mov [os_NetMAC+2], al
	shr eax, 8
	mov [os_NetMAC+3], al
	mov eax, 0x00000201
	mov [rsi+0x14], eax
	mov eax, [rsi+0x14]
	shr eax, 16
	mov [os_NetMAC+4], al
	shr eax, 8
	mov [os_NetMAC+5], al
os_net_i8254x_init_done_MAC:

	; Reset the device
	call os_net_i8254x_reset

	pop rax
	pop rcx
	pop rdx
	pop rsi
	ret
; -----------------------------------------------------------------------------


; -----------------------------------------------------------------------------
; os_net_i8254x_reset - Reset an Intel 8254x NIC
;  IN:	Nothing
; OUT:	Nothing, all registers preserved
os_net_i8254x_reset:
	mov rsi, [os_NetIOBaseMem]
	mov rdi, rsi

	mov eax, 0xFFFFFFFF
	mov [rsi+I8254X_REG_IMC], eax		; Disable all interrupt causes
	mov eax, [rsi+I8254X_REG_ICR]		; Clear any pending interrupts
	xor eax, eax
	mov [rsi+I8254X_REG_ITR], eax		; Disable interrupt throttling logic

	mov eax, 0x00000030
	mov [rsi+I8254X_REG_PBA], eax		; PBA: set the RX buffer size to 48KB (TX buffer is calculated as 64-RX buffer)

	mov eax, 0x08008060
	mov [rsi+I8254X_REG_TXCW], eax		; TXCW: set ANE, TxConfigWord (Half/Full duplex, Next Page Request)

	mov eax, [rsi+I8254X_REG_CTRL]
	btr eax, 3
	bts eax, 6
	bts eax, 5
	btr eax, 31
	btr eax, 30
	btr eax, 7
	mov [rsi+I8254X_REG_CTRL], eax		; CTRL: clear LRST, set SLU and ASDE, clear RSTPHY, VME, and ILOS

	push rdi
	add rdi, 0x5200				; MTA: reset
	mov eax, 0xFFFFFFFF
	stosd
	stosd
	stosd
	stosd
	pop rdi

	mov rax, os_eth_rx_buffer
	mov [rsi+I8254X_REG_RDBAL], eax		; Receive Descriptor Base Address Low
	shr rax, 32
	mov [rsi+I8254X_REG_RDBAH], eax		; Receive Descriptor Base Address High
	mov eax, (32 * 16)
	mov [rsi+I8254X_REG_RDLEN], eax		; Receive Descriptor Length
	xor eax, eax<commit_msg>Fix bug in i8254x driver. Wrong bit was set.<commit_after>; =============================================================================
; BareMetal -- a 64-bit OS written in Assembly for x86-64 systems
; Copyright (C) 2008-2014 Return Infinity -- see LICENSE.TXT
;
; Intel i8254x NIC.
; =============================================================================

align 16
db 'DEBUG: I8254X   '
align 16


; -----------------------------------------------------------------------------
; Initialize an Intel 8254x NIC
;  IN:	BL  = Bus number of the Intel device
;	CL  = Device/Slot number of the Intel device
os_net_i8254x_init:
	push rsi
	push rdx
	push rcx
	push rax

	; Read BAR4, If BAR4 is all 0'z then we are using 32-bit addresses

	; Grab the Base I/O Address of the device
	mov dl, 0x04				; BAR0
	call os_pci_read_reg
	and eax, 0xFFFFFFF0			; EAX now holds the Base Memory IO Address (clear the low 4 bits)
	mov dword [os_NetIOBaseMem], eax

	; Grab the IRQ of the device
	mov dl, 0x0F				; Get device's IRQ number from PCI Register 15 (IRQ is bits 7-0)
	call os_pci_read_reg
	mov [os_NetIRQ], al			; AL holds the IRQ

	; Grab the MAC address
	mov rsi, [os_NetIOBaseMem]
	mov eax, [rsi+0x5400]				; RAL
	cmp eax, 0x00000000
	je os_net_i8254x_init_get_MAC_via_EPROM
	mov [os_NetMAC], al
	shr eax, 8
	mov [os_NetMAC+1], al
	shr eax, 8
	mov [os_NetMAC+2], al
	shr eax, 8
	mov [os_NetMAC+3], al
	mov eax, [rsi+0x5404]				; RAH
	mov [os_NetMAC+4], al
	shr eax, 8
	mov [os_NetMAC+5], al
	jmp os_net_i8254x_init_done_MAC

os_net_i8254x_init_get_MAC_via_EPROM:
	mov rsi, [os_NetIOBaseMem]
	mov eax, 0x00000001
	mov [rsi+0x14], eax
	mov eax, [rsi+0x14]
	shr eax, 16
	mov [os_NetMAC], al
	shr eax, 8
	mov [os_NetMAC+1], al
	mov eax, 0x00000101
	mov [rsi+0x14], eax
	mov eax, [rsi+0x14]
	shr eax, 16
	mov [os_NetMAC+2], al
	shr eax, 8
	mov [os_NetMAC+3], al
	mov eax, 0x00000201
	mov [rsi+0x14], eax
	mov eax, [rsi+0x14]
	shr eax, 16
	mov [os_NetMAC+4], al
	shr eax, 8
	mov [os_NetMAC+5], al
os_net_i8254x_init_done_MAC:

	; Reset the device
	call os_net_i8254x_reset

	pop rax
	pop rcx
	pop rdx
	pop rsi
	ret
; -----------------------------------------------------------------------------


; -----------------------------------------------------------------------------
; os_net_i8254x_reset - Reset an Intel 8254x NIC
;  IN:	Nothing
; OUT:	Nothing, all registers preserved
os_net_i8254x_reset:
	mov rsi, [os_NetIOBaseMem]
	mov rdi, rsi

	mov eax, 0xFFFFFFFF
	mov [rsi+I8254X_REG_IMC], eax		; Disable all interrupt causes
	mov eax, [rsi+I8254X_REG_ICR]		; Clear any pending interrupts
	xor eax, eax
	mov [rsi+I8254X_REG_ITR], eax		; Disable interrupt throttling logic

	mov eax, 0x00000030
	mov [rsi+I8254X_REG_PBA], eax		; PBA: set the RX buffer size to 48KB (TX buffer is calculated as 64-RX buffer)

	mov eax, 0x80008060
	mov [rsi+I8254X_REG_TXCW], eax		; TXCW: set ANE, TxConfigWord (Half/Full duplex, Next Page Request)

	mov eax, [rsi+I8254X_REG_CTRL]
	btr eax, 3
	bts eax, 6
	bts eax, 5
	btr eax, 31
	btr eax, 30
	btr eax, 7
	mov [rsi+I8254X_REG_CTRL], eax		; CTRL: clear LRST, set SLU and ASDE, clear RSTPHY, VME, and ILOS

	push rdi
	add rdi, 0x5200				; MTA: reset
	mov eax, 0xFFFFFFFF
	stosd
	stosd
	stosd
	stosd
	pop rdi

	mov rax, os_eth_rx_buffer
	mov [rsi+I8254X_REG_RDBAL], eax		; Receive Descriptor Base Address Low
	shr rax, 32
	mov [rsi+I8254X_REG_RDBAH], eax		; Receive Descriptor Base Address High
	mov eax, (32 * 16)
	mov [rsi+I8254X_REG_RDLEN], eax		; Receive Descriptor Length
	xor eax, eax
{'fraction_non_alphanumeric': 0.1846724703867561, 'fraction_numerical': 0.07306978735550164, 'mean_word_length': 2.9705382436260623, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 3, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 10, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '3290770', 'n_tokens_mistral': 3336, 'n_tokens_neox': 2886, 'n_words': 883}