<commit_before><?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
	xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
	xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<import file="copyright.xml"/>

<import file="nvchipsets.xml" />
<import file="graph/nv50_pgraph.xml" />

<group name="nvc0_tpc">
	<array offset="0x000" name="POLY" stride="0x200" length="1">
		<reg32 offset="0x048" name="POLY2ESETUP">
			<bitfield low="0" high="27" name="ADDRESS" shr="12"/>
			<bitfield pos="28" name="VALID"/>
		</reg32>
		<reg32 offset="0x054" name="PM_UNK054"/>
		<reg32 offset="0x05c" name="TFB_UNFUCKUP_OFFSET_QUERIES">
			<doc>If set to 0, the 9097/1b0c/0d005002 query will return bytes written
			since the last time TFB_BUFFER_OFFSET (9097/0390) was written.
			Set it to 1 to make it return the full/absolute offset, which is required
			for a sane implementation of transform feedback.
			(Setting only on GPC[0].TPC[0] seems enough.)</doc>
		</reg32>
		<reg32 offset="0x060" name="VSTATUS" access="r">
			<bitfield low="0" high="2" name="UNK0" type="NV50_VSTATUS"/>
			<bitfield low="3" high="5" name="UNK1" type="NV50_VSTATUS"/>
			<bitfield low="6" high="8" name="UNK2" type="NV50_VSTATUS"/>
			<bitfield low="9" high="11" name="UNK3" type="NV50_VSTATUS"/>
			<bitfield low="12" high="14" name="UNK4" type="NV50_VSTATUS"/>
			<bitfield low="15" high="17" name="UNK5" type="NV50_VSTATUS"/>
			<bitfield low="18" high="20" name="UNK6" type="NV50_VSTATUS"/>
			<bitfield low="21" high="23" name="UNK7" type="NV50_VSTATUS"/>
			<bitfield low="24" high="26" name="UNK8" type="NV50_VSTATUS"/>
			<bitfield low="27" high="29" name="UNK9" type="NV50_VSTATUS"/>
		</reg32>
		<reg32 offset="0x064" name="CTX_UNK064"/>
		<stripe offset="0x68" name="HW_BLK">
			<use-group name="nvc0_hw_blk"/>
		</stripe>
		<reg32 offset="0x084" name="TRAP">
			<bitfield name="CLEAR" pos="30" />
			<bitfield name="ENABLE" pos="31" />
		</reg32>
		<reg32 offset="0x088" name="TPCID"/> <!-- ctx-switched -->
	</array>
	<array offset="0x200" name="TEX" stride="0x100" length="1">
		<reg32 offset="0x00" name="CTX_UNK00"/>
		<reg32 offset="0x04" name="CTX_UNK04"/>
		<reg32 offset="0x08" name="CTX_UNK08"/>
		<reg32 offset="0x0c" name="CTX_UNK0C"/>
		<reg32 offset="0x10" name="CTX_UNK10"/>
		<reg32 offset="0x14" name="CTX_UNK14"/>
		<reg32 offset="0x1c" name="CTX_UNK1C"/>
		<reg32 offset="0x20" name="CTX_UNK20"/>
		<reg32 offset="0x24" name="TRAP">
			<bitfield name="CLEAR" pos="30" />
			<bitfield name="ENABLE" pos="31" />
		</reg32>
		<reg32 offset="0x30" name="CTX_UNK30" variants="NVE4-"/>
		<reg32 offset="0x38" name="VSTATUS_0" length="2" access="r">
			<bitfield low="0" high="2" name="UNK0" type="NV50_VSTATUS"/>
			<bitfield low="4" high="6" name="UNK1" type="NV50_VSTATUS"/>
			<bitfield low="8" high="10" name="UNK2" type="NV50_VSTATUS"/>
			<bitfield low="11" high="13" name="UNK3" type="NV50_VSTATUS"/>
			<bitfield low="14" high="16" name="UNK4" type="NV50_VSTATUS"/>
			<bitfield low="17" high="19" name="UNK5" type="NV50_VSTATUS"/>
			<bitfield low="20" high="22" name="UNK6" type="NV50_VSTATUS"/>
			<bitfield low="23" high="25" name="UNK7" type="NV50_VSTATUS"/>
			<bitfield low="26" high="28" name="UNK8" type="NV50_VSTATUS"/>
			<bitfield low="29" high="31" name="UNK9" type="NV50_VSTATUS"/>
		</reg32>
		<stripe offset="0x40" name="HW_CGBLK0">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x48" name="HW_CGBLK1">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x50" name="HW_CGBLK2">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x58" name="HW_CGBLK3">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x60" name="HW_CGBLK4">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x68" name="HW_CGBLK5">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x70" name="HW_CGBLK6">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x78" name="HW_CGBLK7">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x80" name="HW_CGBLK8">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x88" name="HW_PGBLK0">
			<use-group name="nvc0_hw_pgblk"/>
		</stripe>
		<stripe offset="0x90" name="HW_PGBLK1">
			<use-group name="nvc0_hw_pgblk"/>
		</stripe>
		<stripe offset="0x98" name="HW_PGBLK2">
			<use-group name="nvc0_hw_pgblk"/>
		</stripe>
		<stripe offset="0xa0" name="HW_PGBLK3">
			<use-group name="nvc0_hw_pgblk"/>
		</stripe>
		<reg32 offset="0xc4" name="CTX_UNKC4" variants="NVE4-"/>
		<stripe offset="0xcc" name="HW_BLK" variants="NVC4-">
			<use-group name="nvc0_hw_blk"/>
		</stripe>
		<reg32 offset="0xdc" name="VSTATUS_1" access="r">
			<bitfield low="0" high="2" name="UNK0" type="NV50_VSTATUS"/>
			<bitfield low="4" high="6" name="UNK1" type="NV50_VSTATUS"/>
			<bitfield low="8" high="10" name="UNK2" type="NV50_VSTATUS"/>
			<bitfield low="11" high="13" name="UNK3" type="NV50_VSTATUS"/>
		</reg32>
	</array>
	<!-- moved to GPC+0x3000 on NVE4 -->
	<array offset="0x300" name="TPBUS" variants="NVC0:NVE4" stride="0x100" length="1">
		<reg32 offset="0x00" name="TPC_GPCID" length="44"> <!-- ctx-switched -->
			<bitfield low="0" high="4" name="0"/>
			<bitfield low="5" high="9" name="1"/>
			<bitfield low="10" high="14" name="2"/>
			<bitfield low="15" high="19" name="3"/>
			<bitfield low="20" high="24" name="4"/>
			<bitfield low="25" high="29" name="5"/>
		</reg32>
		<reg32 offset="0xd0" name="UNKD0"> <!-- ctx-switched -->
			<bitfield low="0" high="7" name="ROP_COUNT"/>
			<bitfield low="8" high="15" name="GPC_COUNT"/>
			<bitfield low="16" high="28" name="UNK16"/>
		</reg32>
		<reg32 offset="0xe0" name="CTX_UNKE0"/>
		<reg32 offset="0xe4" name="CTX_UNKE4"/>
		<stripe offset="0xe8" name="HW_BLK">
			<use-group name="nvc0_hw_blk"/>
		</stripe>
	</array>
	<array offset="0x400" name="UNK400" stride="0x80" length="1">
		<reg32 offset="0x00" name="CTX_UNK00"/>
		<reg32 offset="0x04" name="CTX_UNK04"/>
		<reg32 offset="0x08" name="CTX_UNK08"/>
		<reg32 offset="0x0c" name="PM_UNK0C"/>
		<reg32 offset="0x10" name="VSTATUS" access="r">
			<bitfield low="0" high="2" name="UNK0" type="NV50_VSTATUS"/>
			<bitfield low="3" high="5" name="UNK1" type="NV50_VSTATUS"/>
			<bitfield low="6" high="8" name="UNK2" type="NV50_VSTATUS"/>
			<bitfield low="9" high="11" name="UNK3" type="NV50_VSTATUS"/>
		</reg32>
		<reg32 offset="0x20" name="CTX_UNK20"/>
		<reg32 offset="0x24" name="CTX_UNK24" variants="NVE4-"/>
		<reg32 offset="0x28" name="CTX_UNK28" variants="NVE4-"/>
		<stripe offset="0x70" name="HW_BLK">
			<use-group name="nvc0_hw_blk"/>
		</stripe>
	</array>
	<array offset="0x480" name="L1" stride="0x80" length="1">
		<reg32 offset="0x0c" name="TRAP">
			<bitfield pos="1" name="GLOBAL_MAP_READ"/> <!-- not passed up to TPC.TRAP, causes VM fault -->
			<bitfield pos="2" name="GLOBAL_MAP_WRITE"/> <!-- not passed up to TPC.TRAP, causes VM fault -->
			<bitfield pos="30" name="CLEAR"/>
			<bitfield pos="31" name="ENABLE"/>
		</reg32>
		<reg32 offset="0x28" name="PM_UNK28"/>
		<reg32 offset="0x4c" name="BLCG0"/>
		<stripe offset="0x54" name="HW_CGBLK1">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x5c" name="HW_CGBLK2">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<reg32 offset="0x64" name="ELPG0"/><commit_msg>rnndb/pgraph/nvc0/L1: add a performance monitoring reg<commit_after><?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
	xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
	xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<import file="copyright.xml"/>

<import file="nvchipsets.xml" />
<import file="graph/nv50_pgraph.xml" />

<group name="nvc0_tpc">
	<array offset="0x000" name="POLY" stride="0x200" length="1">
		<reg32 offset="0x048" name="POLY2ESETUP">
			<bitfield low="0" high="27" name="ADDRESS" shr="12"/>
			<bitfield pos="28" name="VALID"/>
		</reg32>
		<reg32 offset="0x054" name="PM_UNK054"/>
		<reg32 offset="0x05c" name="TFB_UNFUCKUP_OFFSET_QUERIES">
			<doc>If set to 0, the 9097/1b0c/0d005002 query will return bytes written
			since the last time TFB_BUFFER_OFFSET (9097/0390) was written.
			Set it to 1 to make it return the full/absolute offset, which is required
			for a sane implementation of transform feedback.
			(Setting only on GPC[0].TPC[0] seems enough.)</doc>
		</reg32>
		<reg32 offset="0x060" name="VSTATUS" access="r">
			<bitfield low="0" high="2" name="UNK0" type="NV50_VSTATUS"/>
			<bitfield low="3" high="5" name="UNK1" type="NV50_VSTATUS"/>
			<bitfield low="6" high="8" name="UNK2" type="NV50_VSTATUS"/>
			<bitfield low="9" high="11" name="UNK3" type="NV50_VSTATUS"/>
			<bitfield low="12" high="14" name="UNK4" type="NV50_VSTATUS"/>
			<bitfield low="15" high="17" name="UNK5" type="NV50_VSTATUS"/>
			<bitfield low="18" high="20" name="UNK6" type="NV50_VSTATUS"/>
			<bitfield low="21" high="23" name="UNK7" type="NV50_VSTATUS"/>
			<bitfield low="24" high="26" name="UNK8" type="NV50_VSTATUS"/>
			<bitfield low="27" high="29" name="UNK9" type="NV50_VSTATUS"/>
		</reg32>
		<reg32 offset="0x064" name="CTX_UNK064"/>
		<stripe offset="0x68" name="HW_BLK">
			<use-group name="nvc0_hw_blk"/>
		</stripe>
		<reg32 offset="0x084" name="TRAP">
			<bitfield name="CLEAR" pos="30" />
			<bitfield name="ENABLE" pos="31" />
		</reg32>
		<reg32 offset="0x088" name="TPCID"/> <!-- ctx-switched -->
	</array>
	<array offset="0x200" name="TEX" stride="0x100" length="1">
		<reg32 offset="0x00" name="CTX_UNK00"/>
		<reg32 offset="0x04" name="CTX_UNK04"/>
		<reg32 offset="0x08" name="CTX_UNK08"/>
		<reg32 offset="0x0c" name="CTX_UNK0C"/>
		<reg32 offset="0x10" name="CTX_UNK10"/>
		<reg32 offset="0x14" name="CTX_UNK14"/>
		<reg32 offset="0x1c" name="CTX_UNK1C"/>
		<reg32 offset="0x20" name="CTX_UNK20"/>
		<reg32 offset="0x24" name="TRAP">
			<bitfield name="CLEAR" pos="30" />
			<bitfield name="ENABLE" pos="31" />
		</reg32>
		<reg32 offset="0x30" name="CTX_UNK30" variants="NVE4-"/>
		<reg32 offset="0x38" name="VSTATUS_0" length="2" access="r">
			<bitfield low="0" high="2" name="UNK0" type="NV50_VSTATUS"/>
			<bitfield low="4" high="6" name="UNK1" type="NV50_VSTATUS"/>
			<bitfield low="8" high="10" name="UNK2" type="NV50_VSTATUS"/>
			<bitfield low="11" high="13" name="UNK3" type="NV50_VSTATUS"/>
			<bitfield low="14" high="16" name="UNK4" type="NV50_VSTATUS"/>
			<bitfield low="17" high="19" name="UNK5" type="NV50_VSTATUS"/>
			<bitfield low="20" high="22" name="UNK6" type="NV50_VSTATUS"/>
			<bitfield low="23" high="25" name="UNK7" type="NV50_VSTATUS"/>
			<bitfield low="26" high="28" name="UNK8" type="NV50_VSTATUS"/>
			<bitfield low="29" high="31" name="UNK9" type="NV50_VSTATUS"/>
		</reg32>
		<stripe offset="0x40" name="HW_CGBLK0">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x48" name="HW_CGBLK1">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x50" name="HW_CGBLK2">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x58" name="HW_CGBLK3">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x60" name="HW_CGBLK4">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x68" name="HW_CGBLK5">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x70" name="HW_CGBLK6">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x78" name="HW_CGBLK7">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x80" name="HW_CGBLK8">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x88" name="HW_PGBLK0">
			<use-group name="nvc0_hw_pgblk"/>
		</stripe>
		<stripe offset="0x90" name="HW_PGBLK1">
			<use-group name="nvc0_hw_pgblk"/>
		</stripe>
		<stripe offset="0x98" name="HW_PGBLK2">
			<use-group name="nvc0_hw_pgblk"/>
		</stripe>
		<stripe offset="0xa0" name="HW_PGBLK3">
			<use-group name="nvc0_hw_pgblk"/>
		</stripe>
		<reg32 offset="0xc4" name="CTX_UNKC4" variants="NVE4-"/>
		<stripe offset="0xcc" name="HW_BLK" variants="NVC4-">
			<use-group name="nvc0_hw_blk"/>
		</stripe>
		<reg32 offset="0xdc" name="VSTATUS_1" access="r">
			<bitfield low="0" high="2" name="UNK0" type="NV50_VSTATUS"/>
			<bitfield low="4" high="6" name="UNK1" type="NV50_VSTATUS"/>
			<bitfield low="8" high="10" name="UNK2" type="NV50_VSTATUS"/>
			<bitfield low="11" high="13" name="UNK3" type="NV50_VSTATUS"/>
		</reg32>
	</array>
	<!-- moved to GPC+0x3000 on NVE4 -->
	<array offset="0x300" name="TPBUS" variants="NVC0:NVE4" stride="0x100" length="1">
		<reg32 offset="0x00" name="TPC_GPCID" length="44"> <!-- ctx-switched -->
			<bitfield low="0" high="4" name="0"/>
			<bitfield low="5" high="9" name="1"/>
			<bitfield low="10" high="14" name="2"/>
			<bitfield low="15" high="19" name="3"/>
			<bitfield low="20" high="24" name="4"/>
			<bitfield low="25" high="29" name="5"/>
		</reg32>
		<reg32 offset="0xd0" name="UNKD0"> <!-- ctx-switched -->
			<bitfield low="0" high="7" name="ROP_COUNT"/>
			<bitfield low="8" high="15" name="GPC_COUNT"/>
			<bitfield low="16" high="28" name="UNK16"/>
		</reg32>
		<reg32 offset="0xe0" name="CTX_UNKE0"/>
		<reg32 offset="0xe4" name="CTX_UNKE4"/>
		<stripe offset="0xe8" name="HW_BLK">
			<use-group name="nvc0_hw_blk"/>
		</stripe>
	</array>
	<array offset="0x400" name="UNK400" stride="0x80" length="1">
		<reg32 offset="0x00" name="CTX_UNK00"/>
		<reg32 offset="0x04" name="CTX_UNK04"/>
		<reg32 offset="0x08" name="CTX_UNK08"/>
		<reg32 offset="0x0c" name="PM_UNK0C"/>
		<reg32 offset="0x10" name="VSTATUS" access="r">
			<bitfield low="0" high="2" name="UNK0" type="NV50_VSTATUS"/>
			<bitfield low="3" high="5" name="UNK1" type="NV50_VSTATUS"/>
			<bitfield low="6" high="8" name="UNK2" type="NV50_VSTATUS"/>
			<bitfield low="9" high="11" name="UNK3" type="NV50_VSTATUS"/>
		</reg32>
		<reg32 offset="0x20" name="CTX_UNK20"/>
		<reg32 offset="0x24" name="CTX_UNK24" variants="NVE4-"/>
		<reg32 offset="0x28" name="CTX_UNK28" variants="NVE4-"/>
		<stripe offset="0x70" name="HW_BLK">
			<use-group name="nvc0_hw_blk"/>
		</stripe>
	</array>
	<array offset="0x480" name="L1" stride="0x80" length="1">
		<reg32 offset="0x0c" name="TRAP">
			<bitfield pos="1" name="GLOBAL_MAP_READ"/> <!-- not passed up to TPC.TRAP, causes VM fault -->
			<bitfield pos="2" name="GLOBAL_MAP_WRITE"/> <!-- not passed up to TPC.TRAP, causes VM fault -->
			<bitfield pos="30" name="CLEAR"/>
			<bitfield pos="31" name="ENABLE"/>
		</reg32>
		<reg32 offset="0x28" name="PM">
			<bitfield low="0" high="5" name="SEL"/>
			<bitfield pos="31" name="ENABLE"/>
		</reg32>
		<reg32 offset="0x4c" name="BLCG0"/>
		<stripe offset="0x54" name="HW_CGBLK1">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<stripe offset="0x5c" name="HW_CGBLK2">
			<use-group name="nvc0_hw_cgblk"/>
		</stripe>
		<reg32 offset="0x64" name="ELPG0"/>
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