<commit_before>/*
 * SuperH Timer Support - CMT
 *
 *  Copyright (C) 2008 <NAME>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/sh_timer.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>

struct sh_cmt_priv {
	void __iomem *mapbase;
	struct clk *clk;
	unsigned long width; /* 16 or 32 bit version of hardware block */
	unsigned long overflow_bit;
	unsigned long clear_bits;
	struct irqaction irqaction;
	struct platform_device *pdev;

	unsigned long flags;
	unsigned long match_value;
	unsigned long next_match_value;
	unsigned long max_match_value;
	unsigned long rate;
	raw_spinlock_t lock;
	struct clock_event_device ced;
	struct clocksource cs;
	unsigned long total_cycles;
	bool cs_enabled;
};

static DEFINE_RAW_SPINLOCK(sh_cmt_lock);

#define CMSTR -1 /* shared register */
#define CMCSR 0 /* channel register */
#define CMCNT 1 /* channel register */
#define CMCOR 2 /* channel register */

static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	void __iomem *base = p->mapbase;
	unsigned long offs;

	if (reg_nr == CMSTR) {
		offs = 0;
		base -= cfg->channel_offset;
	} else
		offs = reg_nr;

	if (p->width == 16)
		offs <<= 1;
	else {
		offs <<= 2;
		if ((reg_nr == CMCNT) || (reg_nr == CMCOR))
			return ioread32(base + offs);
	}

	return ioread16(base + offs);
}

static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_priv *p)
{
	return sh_cmt_read(p, CMSTR);
}

static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_priv *p)
{
	return sh_cmt_read(p, CMCSR);
}

static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_priv *p)
{
	return sh_cmt_read(p, CMCNT);
}

static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
				unsigned long value)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	void __iomem *base = p->mapbase;
	unsigned long offs;

	if (reg_nr == CMSTR) {
		offs = 0;
		base -= cfg->channel_offset;
	} else
		offs = reg_nr;

	if (p->width == 16)
		offs <<= 1;
	else {
		offs <<= 2;
		if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) {
			iowrite32(value, base + offs);
			return;
		}
	}

	iowrite16(value, base + offs);
}

static inline void sh_cmt_write_cmstr(struct sh_cmt_priv *p,
				      unsigned long value)
{
	sh_cmt_write(p, CMSTR, value);
}

static inline void sh_cmt_write_cmcsr(struct sh_cmt_priv *p,
				      unsigned long value)
{
	sh_cmt_write(p, CMCSR, value);
}

static inline void sh_cmt_write_cmcnt(struct sh_cmt_priv *p,
				      unsigned long value)
{
	sh_cmt_write(p, CMCNT, value);
}

static inline void sh_cmt_write_cmcor(struct sh_cmt_priv *p,
				      unsigned long value)
{
	sh_cmt_write(p, CMCOR, value);
}

static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
					int *has_wrapped)
{
	unsigned long v1, v2, v3;
	int o1, o2;

	o1 = sh_cmt_read_cmcsr(p) & p->overflow_bit;

	/* Make sure the timer value is stable. Stolen from acpi_pm.c */
	do {
		o2 = o1;
		v1 = sh_cmt_read_cmcnt(p);
		v2 = sh_cmt_read_cmcnt(p);
		v3 = sh_cmt_read_cmcnt(p);
		o1 = sh_cmt_read_cmcsr(p) & p->overflow_bit;
	} while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
			  || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));

	*has_wrapped = o1;
	return v2;
}


static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	unsigned long flags, value;

	/* start stop register shared by multiple timer channels */
	raw_spin_lock_irqsave(&sh_cmt_lock, flags);
	value = sh_cmt_read_cmstr(p);

	if (start)
		value |= 1 << cfg->timer_bit;
	else
		value &= ~(1 << cfg->timer_bit);

	sh_cmt_write_cmstr(p, value);
	raw_spin_unlock_irqrestore(&sh_cmt_lock, flags);
}

static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
{
	int k, ret;
<commit_msg>clocksource: sh_cmt: CMSTR and CMCSR register access update<commit_after>/*
 * SuperH Timer Support - CMT
 *
 *  Copyright (C) 2008 <NAME>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/sh_timer.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>

struct sh_cmt_priv {
	void __iomem *mapbase;
	struct clk *clk;
	unsigned long width; /* 16 or 32 bit version of hardware block */
	unsigned long overflow_bit;
	unsigned long clear_bits;
	struct irqaction irqaction;
	struct platform_device *pdev;

	unsigned long flags;
	unsigned long match_value;
	unsigned long next_match_value;
	unsigned long max_match_value;
	unsigned long rate;
	raw_spinlock_t lock;
	struct clock_event_device ced;
	struct clocksource cs;
	unsigned long total_cycles;
	bool cs_enabled;
};

static inline unsigned long sh_cmt_read16(void __iomem *base,
					  unsigned long offs)
{
	return ioread16(base + (offs << 1));
}

static inline void sh_cmt_write16(void __iomem *base, unsigned long offs,
				  unsigned long value)
{
	iowrite16(value, base + (offs << 1));
}

#define CMCSR 0 /* channel register */
#define CMCNT 1 /* channel register */
#define CMCOR 2 /* channel register */

static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
{
	void __iomem *base = p->mapbase;
	unsigned long offs = reg_nr;

	if (p->width == 16) {
		offs <<= 1;
		return ioread16(base + offs);
	} else {
		offs <<= 2;
		return ioread32(base + offs);
	}
}

static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_priv *p)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;

	return sh_cmt_read16(p->mapbase - cfg->channel_offset, 0);
}

static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_priv *p)
{
	return sh_cmt_read16(p->mapbase, CMCSR);
}

static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_priv *p)
{
	return sh_cmt_read(p, CMCNT);
}

static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
				unsigned long value)
{
	void __iomem *base = p->mapbase;
	unsigned long offs = reg_nr;

	if (p->width == 16) {
		offs <<= 1;
		iowrite16(value, base + offs);
	} else {
		offs <<= 2;
		iowrite32(value, base + offs);
	}
}

static inline void sh_cmt_write_cmstr(struct sh_cmt_priv *p,
				      unsigned long value)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;

	sh_cmt_write16(p->mapbase - cfg->channel_offset, 0, value);
}

static inline void sh_cmt_write_cmcsr(struct sh_cmt_priv *p,
				      unsigned long value)
{
	sh_cmt_write16(p->mapbase, CMCSR, value);
}

static inline void sh_cmt_write_cmcnt(struct sh_cmt_priv *p,
				      unsigned long value)
{
	sh_cmt_write(p, CMCNT, value);
}

static inline void sh_cmt_write_cmcor(struct sh_cmt_priv *p,
				      unsigned long value)
{
	sh_cmt_write(p, CMCOR, value);
}

static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
					int *has_wrapped)
{
	unsigned long v1, v2, v3;
	int o1, o2;

	o1 = sh_cmt_read_cmcsr(p) & p->overflow_bit;

	/* Make sure the timer value is stable. Stolen from acpi_pm.c */
	do {
		o2 = o1;
		v1 = sh_cmt_read_cmcnt(p);
		v2 = sh_cmt_read_cmcnt(p);
		v3 = sh_cmt_read_cmcnt(p);
		o1 = sh_cmt_read_cmcsr(p) & p->overflow_bit;
	} while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
			  || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));

	*has_wrapped = o1;
	return v2;
}

static DEFINE_RAW_SPINLOCK(sh_cmt_lock);

static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
{
	struct sh_timer_config *cfg = p->pdev->dev.platform_data;
	unsigned long flags, value;

	/* start stop register shared by multiple timer channels */
	raw_spin_lock_irqsave(&sh_cmt_lock, flags);
	value = sh_cmt_read_cmstr(p);

	if (start)
		value |= 1 << cfg->timer_bit;
	else
		value &= ~(1 << cfg->timer_bit);

	sh_cmt_write_cmstr(p, value);
	raw_spin_unlock_irqrestore(&sh_cmt_lock, flags);
}

static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
{
	int k, ret;

{'fraction_non_alphanumeric': 0.11180826990331208, 'fraction_numerical': 0.017177535486525407, 'mean_word_length': 4.205032119914347, 'pattern_counts': {'":': 0, '<': 73, '<?xml version=': 0, '>': 81, 'https://': 0, 'lorem ipsum': 0, 'www.': 0, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '5258697', 'n_tokens_mistral': 3881, 'n_tokens_neox': 3672, 'n_words': 1045}