<commit_before>
/* Simulator for the moxie processor
   Copyright 2014 <NAME>
   Distributed under the MIT/X11 software license, see the accompanying
   file COPYING or http://www.opensource.org/licenses/mit-license.php.
*/

#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <signal.h>
#include <errno.h>
#include "sandbox.h"

#define INLINE inline

static FILE *tracefile = stdout;

/* Extract the signed 10-bit offset from a 16-bit branch
   instruction.  */
#define INST2OFFSET(o) ((((signed short)((o & ((1<<10)-1))<<6))>>6)<<1)

#define EXTRACT_WORD(addr) \
  (  (sim_core_read_aligned_1 (mach, addr)) \
   + (sim_core_read_aligned_1 (mach, addr+1) << 8) \
   + (sim_core_read_aligned_1 (mach, addr+2) << 16) \
   + (sim_core_read_aligned_1 (mach, addr+3) << 24) )

#define cpu mach.cpu

static uint32_t sim_core_read_aligned_1(machine& mach, uint32_t addr)
{
	uint32_t ret;
	if (!mach.read8(addr, ret))
		return 0xffffffffU;
	return ret;
}

static uint32_t sim_core_read_aligned_2(machine& mach, uint32_t addr)
{
	uint32_t ret;
	if (!mach.read16(addr, ret))
		return 0xffffffffU;
	return ret;
}

static uint32_t sim_core_read_aligned_4(machine& mach, uint32_t addr)
{
	uint32_t ret;
	if (!mach.read32(addr, ret))
		return 0xffffffffU;
	return ret;
}

/* Write a 1 byte value to memory.  */

static void INLINE 
wbat (machine& mach, word pc, word x, word v)
{
  mach.write8(x, v);
  // TODO: handle failure
}

/* Write a 2 byte value to memory.  */

static void INLINE 
wsat (machine& mach, word pc, word x, word v)
{
  mach.write16(x, v);
  // TODO: handle failure
}

/* Write a 4 byte value to memory.  */

static void INLINE 
wlat (machine& mach, word pc, word x, word v)
{
  mach.write32(x, v);
  // TODO: handle failure
}

/* Read 2 bytes from memory.  */

static int INLINE 
rsat (machine& mach, word pc, word x)
{
  return (sim_core_read_aligned_2 (mach, x));
}

/* Read 1 byte from memory.  */

static int INLINE 
rbat (machine& mach, word pc, word x)
{
  return (sim_core_read_aligned_1 (mach, x));
}

/* Read 4 bytes from memory.  */

static int INLINE 
rlat (machine& mach, word pc, word x)
{
  return (sim_core_read_aligned_4 (mach, x));
}

#define TRACE(str) if (mach.tracing) fprintf(tracefile,"0x%08x, %s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", opc, str, cpu.asregs.regs[0], cpu.asregs.regs[1], cpu.asregs.regs[2], cpu.asregs.regs[3], cpu.asregs.regs[4], cpu.asregs.regs[5], cpu.asregs.regs[6], cpu.asregs.regs[7], cpu.asregs.regs[8], cpu.asregs.regs[9], cpu.asregs.regs[10], cpu.asregs.regs[11], cpu.asregs.regs[12], cpu.asregs.regs[13], cpu.asregs.regs[14], cpu.asregs.regs[15]);

void
sim_resume (machine& mach, unsigned long long cpu_budget)
{
  int step = 0;

  word pc, opc;
  unsigned long long insts;
  unsigned short inst;

  cpu.asregs.exception = step ? SIGTRAP: 0;
  pc = cpu.asregs.regs[PC_REGNO];
  insts = cpu.asregs.insts;

  /* Run instructions here. */
  do 
    {
      opc = pc;

      /* Fetch the instruction at pc.  */
      inst = ((sim_core_read_aligned_1 (mach, pc))
	    + (sim_core_read_aligned_1 (mach, pc+1) << 8));

      /* Decode instruction.  */
      if (inst & (1 << 15))
	{
	  if (inst & (1 << 14))
	    {
	      /* This is a Form 3 instruction.  */
	      int opcode = (inst >> 10 & 0xf);

	      switch (opcode)
		{
		case 0x00: /* beq */
		  {
		    TRACE("beq");
		    if (cpu.asregs.cc & CC_EQ)
		      pc += INST2OFFSET(inst);
		  }<commit_msg>interp: alias 'cpu' at C++ not cpp level<commit_after>
/* Simulator for the moxie processor
   Copyright 2014 <NAME>
   Distributed under the MIT/X11 software license, see the accompanying
   file COPYING or http://www.opensource.org/licenses/mit-license.php.
*/

#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <signal.h>
#include <errno.h>
#include "sandbox.h"

#define INLINE inline

static FILE *tracefile = stdout;

/* Extract the signed 10-bit offset from a 16-bit branch
   instruction.  */
#define INST2OFFSET(o) ((((signed short)((o & ((1<<10)-1))<<6))>>6)<<1)

#define EXTRACT_WORD(addr) \
  (  (sim_core_read_aligned_1 (mach, addr)) \
   + (sim_core_read_aligned_1 (mach, addr+1) << 8) \
   + (sim_core_read_aligned_1 (mach, addr+2) << 16) \
   + (sim_core_read_aligned_1 (mach, addr+3) << 24) )

static uint32_t sim_core_read_aligned_1(machine& mach, uint32_t addr)
{
	uint32_t ret;
	if (!mach.read8(addr, ret))
		return 0xffffffffU;
	return ret;
}

static uint32_t sim_core_read_aligned_2(machine& mach, uint32_t addr)
{
	uint32_t ret;
	if (!mach.read16(addr, ret))
		return 0xffffffffU;
	return ret;
}

static uint32_t sim_core_read_aligned_4(machine& mach, uint32_t addr)
{
	uint32_t ret;
	if (!mach.read32(addr, ret))
		return 0xffffffffU;
	return ret;
}

/* Write a 1 byte value to memory.  */

static void INLINE 
wbat (machine& mach, word pc, word x, word v)
{
  mach.write8(x, v);
  // TODO: handle failure
}

/* Write a 2 byte value to memory.  */

static void INLINE 
wsat (machine& mach, word pc, word x, word v)
{
  mach.write16(x, v);
  // TODO: handle failure
}

/* Write a 4 byte value to memory.  */

static void INLINE 
wlat (machine& mach, word pc, word x, word v)
{
  mach.write32(x, v);
  // TODO: handle failure
}

/* Read 2 bytes from memory.  */

static int INLINE 
rsat (machine& mach, word pc, word x)
{
  return (sim_core_read_aligned_2 (mach, x));
}

/* Read 1 byte from memory.  */

static int INLINE 
rbat (machine& mach, word pc, word x)
{
  return (sim_core_read_aligned_1 (mach, x));
}

/* Read 4 bytes from memory.  */

static int INLINE 
rlat (machine& mach, word pc, word x)
{
  return (sim_core_read_aligned_4 (mach, x));
}

#define TRACE(str) if (mach.tracing) fprintf(tracefile,"0x%08x, %s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", opc, str, cpu.asregs.regs[0], cpu.asregs.regs[1], cpu.asregs.regs[2], cpu.asregs.regs[3], cpu.asregs.regs[4], cpu.asregs.regs[5], cpu.asregs.regs[6], cpu.asregs.regs[7], cpu.asregs.regs[8], cpu.asregs.regs[9], cpu.asregs.regs[10], cpu.asregs.regs[11], cpu.asregs.regs[12], cpu.asregs.regs[13], cpu.asregs.regs[14], cpu.asregs.regs[15]);

void
sim_resume (machine& mach, unsigned long long cpu_budget)
{
  int step = 0;

  word pc, opc;
  unsigned long long insts;
  unsigned short inst;
  cpuState& cpu = mach.cpu;

  cpu.asregs.exception = step ? SIGTRAP: 0;
  pc = cpu.asregs.regs[PC_REGNO];
  insts = cpu.asregs.insts;

  /* Run instructions here. */
  do 
    {
      opc = pc;

      /* Fetch the instruction at pc.  */
      inst = ((sim_core_read_aligned_1 (mach, pc))
	    + (sim_core_read_aligned_1 (mach, pc+1) << 8));

      /* Decode instruction.  */
      if (inst & (1 << 15))
	{
	  if (inst & (1 << 14))
	    {
	      /* This is a Form 3 instruction.  */
	      int opcode = (inst >> 10 & 0xf);

	      switch (opcode)
		{
		case 0x00: /* beq */
		  {
		    TRACE("beq");
		    if (cpu.asregs.cc & CC_EQ)
		      pc += INST2OFFSET(inst);
		  }
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