<commit_before>/*
 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#ifndef __SUNXI_MMAP_H__
#define __SUNXI_MMAP_H__

/* Memory regions */
#define SUNXI_ROM_BASE			0x00000000
#define SUNXI_ROM_SIZE			0x00010000
#define SUNXI_SRAM_BASE			0x00010000
#define SUNXI_SRAM_SIZE			0x00044000
#define SUNXI_SRAM_A1_BASE		0x00010000
#define SUNXI_SRAM_A1_SIZE		0x00008000
#define SUNXI_SRAM_A2_BASE		0x00044000
#define SUNXI_SRAM_A2_SIZE		0x00010000
#define SUNXI_SRAM_C_BASE		0x00018000
#define SUNXI_SRAM_C_SIZE		0x0001c000
#define SUNXI_DEV_BASE			0x01000000
#define SUNXI_DEV_SIZE			0x01000000
#define SUNXI_DRAM_BASE			0x40000000
#define SUNXI_DRAM_SIZE			0x80000000

/* Memory-mapped devices */
#define SUNXI_CPU_MBIST_BASE		0x01502000
#define SUNXI_CPUCFG_BASE		0x01700000
#define SUNXI_SYSCON_BASE		0x01c00000
#define SUNXI_SRAM_VER_REG		(SUNXI_SYSCON_BASE + 0x24)
#define SUNXI_DMA_BASE			0x01c02000
#define SUNXI_KEYMEM_BASE		0x01c0b000
#define SUNXI_SMHC0_BASE		0x01c0f000
#define SUNXI_SMHC1_BASE		0x01c10000
#define SUNXI_SMHC2_BASE		0x01c11000
#define SUNXI_SID_BASE			0x01c14000
#define SUNXI_MSGBOX_BASE		0x01c17000
#define SUNXI_SPINLOCK_BASE		0x01c18000
#define SUNXI_CCU_BASE			0x01c20000
#define SUNXI_CCU_SEC_SWITCH_REG	(SUNXI_CCU_BASE + 0x2f0)
#define SUNXI_PIO_BASE			0x01c20800
#define SUNXI_TIMER_BASE		0x01c20c00<commit_msg>allwinner: sun50i_a64: remove unneeded VER_REG offset<commit_after>/*
 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#ifndef __SUNXI_MMAP_H__
#define __SUNXI_MMAP_H__

/* Memory regions */
#define SUNXI_ROM_BASE			0x00000000
#define SUNXI_ROM_SIZE			0x00010000
#define SUNXI_SRAM_BASE			0x00010000
#define SUNXI_SRAM_SIZE			0x00044000
#define SUNXI_SRAM_A1_BASE		0x00010000
#define SUNXI_SRAM_A1_SIZE		0x00008000
#define SUNXI_SRAM_A2_BASE		0x00044000
#define SUNXI_SRAM_A2_SIZE		0x00010000
#define SUNXI_SRAM_C_BASE		0x00018000
#define SUNXI_SRAM_C_SIZE		0x0001c000
#define SUNXI_DEV_BASE			0x01000000
#define SUNXI_DEV_SIZE			0x01000000
#define SUNXI_DRAM_BASE			0x40000000
#define SUNXI_DRAM_SIZE			0x80000000

/* Memory-mapped devices */
#define SUNXI_CPU_MBIST_BASE		0x01502000
#define SUNXI_CPUCFG_BASE		0x01700000
#define SUNXI_SYSCON_BASE		0x01c00000
#define SUNXI_DMA_BASE			0x01c02000
#define SUNXI_KEYMEM_BASE		0x01c0b000
#define SUNXI_SMHC0_BASE		0x01c0f000
#define SUNXI_SMHC1_BASE		0x01c10000
#define SUNXI_SMHC2_BASE		0x01c11000
#define SUNXI_SID_BASE			0x01c14000
#define SUNXI_MSGBOX_BASE		0x01c17000
#define SUNXI_SPINLOCK_BASE		0x01c18000
#define SUNXI_CCU_BASE			0x01c20000
#define SUNXI_CCU_SEC_SWITCH_REG	(SUNXI_CCU_BASE + 0x2f0)
#define SUNXI_PIO_BASE			0x01c20800
#define SUNXI_TIMER_BASE		0x01c20c00
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