<commit_before># SweRV RISC-V Core<sup>TM</sup> 1.5 from Western Digital
## Release Notes


This is a bug-fix and performance-improvement release.  No new functionality
is added to the SweRV core.


## Bug fixes:

1. Hart incorrectly cleared dmcontrol.dmactive on reset (reported by
   Codasip).
2. Hart never asserted the dmstatus.allrunning signal on reset which
   caused a timeout in OpenOCD (reported by Codasip).
3. Debug module failed to auto-increment register on system-bus access
   of size 64-bit (reported by Codasip).
4. The core_rst_n signal was incorrectly connected (reported by Codasip).
5. Moudule/instance renamed for tool compatibility.
6. The program counter was getting corrupted when the load/store unit
   indicated both a single-bit and a double-bit error in the same
   cycle.
7. The MSTATUS control register was not being updated as expected when
   both a non-maskable-interrupt and an MSTATUS-write happened in the
   same cycle.
8. Write to SBDATA0 was not starting an system-bus write access when
   sbreadonaddr/sbreadondata is set.
9. Minstret was incorrectly counting ecall/ebreak instructions
10. The dec_tlu_mpc_halted_only signal was not set for MPC halt after
    reset.
11. The MEPC control register was not being updated when a
    firmware-halt request was followed by a timer interrupt.
12. The MINSTRETH control register was being incremented when
    performance counters were disabled.
13. Bus driver contained combinational logic from multiple clock
    domains that sometimes caused a glitch.
14. System bus reads were always being made with 64-bit size for the
    AXI bus which is incorrect for IO access.
15. DCCM single bit errors were counted for instruction that did not
    commit.
16. ICCM Single Bit Errors were double counted.
17. Load/store unit was not detecting access faults when DCCM and PIC
    memories are next to each other.
18. Single bit ECC errors on data load were not always corrected in
    the DCCM.
19. ECC single bit error were not always corrected in the DCCM for DMA
    access.
20. Single bit Errors detected while reading ICCM through DMA were not
    being corrected in memory.


## Improvements:

1. Improved performance by removing redundant term in decode stall
   logic.
2. Reduced power used by the ICCM memory arrays.


## Testbench Improvements:

1. AXI4 and AHB-Lite support.
2. Updated bus memory to be persistent and handle larger programs.
3. Makefile supports ability to run with source or pre-generated hex
   files.
4. Makefile supports targets for coremarks benchmark (issue #25).
5. Questa support in Makefile (Issue #19).



# SweRV RISC-V Core<sup>TM</sup> 1.4 from Western Digital
## Release Notes
Move declarations to top of Verilog file to fix fpga compile issues.


# SweRV RISC-V Core<sup>TM</sup> 1.3 from Western Digital
## Release Notes
1. Make the FPGA optimization code work with the latest version of Verilator.[Pull request #13](https://github.com/chipsalliance/Cores-SweRV/pull/12)
1. Move JTAG TAP to swerv_wrapper module. [Pull request #10](https://github.com/chipsalliance/Cores-SweRV/pull/10)

# SweRV RISC-V Core<sup>TM</sup> 1.2 from Western Digital
## Release Notes
1. SWERV core RISCV compatibility improvements
    * The ebreak and ecall instructions are no longer counted in the MINSRET
	  control and status register.
    * Write to SBDATA0 does not start SB write access when both
	  sbreadonaddr/sbreadondata are zero. This fixes issue number
	  5 on github.

1. FPGA support: Add fpga_optimize option to swerv.config which
   eliminates over 90% of clock-gating enabling faster FPGA
   simulation.
   
1. Usability: Untabified all the verilog files.  This fixes issue number 3 on github.

# SweRV RISC-V Core<sup>TM</sup> 1.1 from Western Digital
## Release Notes
1. SWERV core RISCV compatibility improvements

    * Illegal instructions no longer increment minstret
    * Debug single-step command no longer executes multiple instructions
    * For instructions, MTVAL register holds the address that actually
      triggered an access fault
    * DICAD1 debug CSR ECC read size enhancements

1. SWERV core performance enhancements

    * Improved instruction fetch unit external memory access performance
    * Instruction fetcher no longer stalls due to DMA ICCM requests
    * Improved performance of streaming stores
    * Improved performance of divide instruction
    * Improved I/O Timing 
    * Non-idempotent Ld/St changed to non-posted in MFDC
    * DMA QoS Configurable in MFDC

1. SWERV core miscellaneous changes

    * Non-word access to PIC memory generates access-error
    * Improved streaming performance with unified read/write buffer
    * Non-idempotent load enhancements
    * Debug, single-step, and trigger enhancements
    * DMA, IFU, and LSU interaction enhancements
    * Bus error handling improvements
    * DMA h-ready addition
    * DMA slave error response enhancements

1. Added memory protection windows
    
	* Now able to define up to eight instruction fetch windows and up to eight
	  data load/store windows. See the programmer reference manual for more
	  details.
<commit_msg>Formatting changes.<commit_after># SweRV RISC-V Core<sup>TM</sup> 1.5 from Western Digital
## Release Notes


This is a bug-fix and performance-improvement release.  No new functionality
is added to the SweRV core.


1. Bug fixes:

* Hart incorrectly cleared dmcontrol.dmactive on reset (reported by
  Codasip).
* Hart never asserted the dmstatus.allrunning signal on reset which
  caused a timeout in OpenOCD (reported by Codasip).
* Debug module failed to auto-increment register on system-bus access
  of size 64-bit (reported by Codasip).
* The core_rst_n signal was incorrectly connected (reported by Codasip).
* Moudule/instance renamed for tool compatibility.
* The program counter was getting corrupted when the load/store unit
  indicated both a single-bit and a double-bit error in the same
  cycle.
* The MSTATUS control register was not being updated as expected when
  both a non-maskable-interrupt and an MSTATUS-write happened in the
  same cycle.
* Write to SBDATA0 was not starting an system-bus write access when
  sbreadonaddr/sbreadondata is set.
* Minstret was incorrectly counting ecall/ebreak instructions
* The dec_tlu_mpc_halted_only signal was not set for MPC halt after
  reset.
* The MEPC control register was not being updated when a
  firmware-halt request was followed by a timer interrupt.
* The MINSTRETH control register was being incremented when
  performance counters were disabled.
* Bus driver contained combinational logic from multiple clock
  domains that sometimes caused a glitch.
* System bus reads were always being made with 64-bit size for the
  AXI bus which is incorrect for IO access.
* DCCM single bit errors were counted for instruction that did not
  commit.
* ICCM Single Bit Errors were double counted.
* Load/store unit was not detecting access faults when DCCM and PIC
  memories are next to each other.
* Single bit ECC errors on data load were not always corrected in
  the DCCM.
* ECC single bit error were not always corrected in the DCCM for DMA
  access.
* Single bit Errors detected while reading ICCM through DMA were not
  being corrected in memory.


2. Improvements:

* Improved performance by removing redundant term in decode stall
  logic.
* Reduced power used by the ICCM memory arrays.


3. Testbench Improvements:

* AXI4 and AHB-Lite support.
* Updated bus memory to be persistent and handle larger programs.
* Makefile supports ability to run with source or pre-generated hex
  files.
* Makefile supports targets for coremarks benchmark (issue #25).
* Questa support in Makefile (Issue #19).



# SweRV RISC-V Core<sup>TM</sup> 1.4 from Western Digital
## Release Notes
Move declarations to top of Verilog file to fix fpga compile issues.


# SweRV RISC-V Core<sup>TM</sup> 1.3 from Western Digital
## Release Notes
1. Make the FPGA optimization code work with the latest version of Verilator.[Pull request #13](https://github.com/chipsalliance/Cores-SweRV/pull/12)
1. Move JTAG TAP to swerv_wrapper module. [Pull request #10](https://github.com/chipsalliance/Cores-SweRV/pull/10)

# SweRV RISC-V Core<sup>TM</sup> 1.2 from Western Digital
## Release Notes
1. SWERV core RISCV compatibility improvements
    * The ebreak and ecall instructions are no longer counted in the MINSRET
	  control and status register.
    * Write to SBDATA0 does not start SB write access when both
	  sbreadonaddr/sbreadondata are zero. This fixes issue number
	  5 on github.

1. FPGA support: Add fpga_optimize option to swerv.config which
   eliminates over 90% of clock-gating enabling faster FPGA
   simulation.
   
1. Usability: Untabified all the verilog files.  This fixes issue number 3 on github.

# SweRV RISC-V Core<sup>TM</sup> 1.1 from Western Digital
## Release Notes
1. SWERV core RISCV compatibility improvements

    * Illegal instructions no longer increment minstret
    * Debug single-step command no longer executes multiple instructions
    * For instructions, MTVAL register holds the address that actually
      triggered an access fault
    * DICAD1 debug CSR ECC read size enhancements

1. SWERV core performance enhancements

    * Improved instruction fetch unit external memory access performance
    * Instruction fetcher no longer stalls due to DMA ICCM requests
    * Improved performance of streaming stores
    * Improved performance of divide instruction
    * Improved I/O Timing 
    * Non-idempotent Ld/St changed to non-posted in MFDC
    * DMA QoS Configurable in MFDC

1. SWERV core miscellaneous changes

    * Non-word access to PIC memory generates access-error
    * Improved streaming performance with unified read/write buffer
    * Non-idempotent load enhancements
    * Debug, single-step, and trigger enhancements
    * DMA, IFU, and LSU interaction enhancements
    * Bus error handling improvements
    * DMA h-ready addition
    * DMA slave error response enhancements

1. Added memory protection windows
    
	* Now able to define up to eight instruction fetch windows and up to eight
	  data load/store windows. See the programmer reference manual for more
	  details.

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