<commit_before>/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  <NAME> <<EMAIL>>
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#ifndef CELLTYPES_H
#define CELLTYPES_H

#include "kernel/yosys.h"

YOSYS_NAMESPACE_BEGIN

struct CellType
{
	RTLIL::IdString type;
	pool<RTLIL::IdString> inputs, outputs;
	bool is_evaluable;
};

struct CellTypes
{
	dict<RTLIL::IdString, CellType> cell_types;

	CellTypes()
	{
	}

	CellTypes(RTLIL::Design *design)
	{
		setup(design);
	}

	void setup(RTLIL::Design *design = NULL)
	{
		if (design)
			setup_design(design);

		setup_internals();
		setup_internals_mem();
		setup_stdcells();
		setup_stdcells_mem();
	}

	void setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false)
	{
		CellType ct = {type, inputs, outputs, is_evaluable};
		cell_types[ct.type] = ct;
	}

	void setup_module(RTLIL::Module *module)
	{
		pool<RTLIL::IdString> inputs, outputs;
		for (RTLIL::IdString wire_name : module->ports) {
			RTLIL::Wire *wire = module->wire(wire_name);
			if (wire->port_input)
				inputs.insert(wire->name);
			if (wire->port_output)
				outputs.insert(wire->name);
		}
		setup_type(module->name, inputs, outputs);
	}

	void setup_design(RTLIL::Design *design)
	{
		for (auto module : design->modules())
			setup_module(module);
	}

	void setup_internals()
	{
		std::vector<RTLIL::IdString> unary_ops = {
			"$not", "$pos", "$neg",
			"$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
			"$logic_not", "$slice", "$lut", "$sop"
		};

		std::vector<RTLIL::IdString> binary_ops = {
			"$and", "$or", "$xor", "$xnor",
			"$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
			"$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
			"$add", "$sub", "$mul", "$div", "$mod", "$pow",
			"$logic_and", "$logic_or", "$concat", "$macc"
		};
		IdString A = "\\A", B = "\\B", S = "\\S", Y = "\\Y";
		IdString P = "\\P", G = "\\G", C = "\\C", X = "\\X";
		IdString BI = "\\BI", CI = "\\CI", CO = "\\CO", EN = "\\EN";

		for (auto type : unary_ops)
			setup_type(type, {A}, {Y}, true);

		for (auto type : binary_ops)
			setup_type(type, {A, B}, {Y}, true);

		for (auto type : std::vector<RTLIL::IdString>({"$mux", "$pmux"}))
			setup_type(type, {A, B, S}, {Y}, true);

		setup_type("$lcu", {P, G, CI}, {CO}, true);
		setup_type("$alu", {A, B, CI, BI}, {X, Y, CO}, true);
		setup_type("$fa", {A, B, C}, {X, Y}, true);

		setup_type("$tribuf", {A, EN}, {Y}, true);

		setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
		setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
		setup_type("$live", {A, EN}, pool<RTLIL::IdString>(), true);
		setup_type("$fair", {A, EN}, pool<RTLIL::IdString>(), true);
		setup_type("$cover", {A, EN}, pool<RTLIL::IdString>(), true);
		setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true);
		setup_type("$anyconst", pool<RTLIL::IdString>(), {Y}, true);
		setup_type("$anyseq", pool<RTLIL::IdString>(), {Y}, true);
		setup_type("$allconst", pool<RTLIL::IdString>(), {Y}, true);
		setup_type("$allseq", pool<RTLIL::IdString>(), {Y}, true);
		setup_type("$equiv", {A, B}, {Y}, true);
	}

	void setup_internals_mem()
	{
		IdString SET = "\\SET", CLR = "\\CLR", CLK = "\\CLK", ARST = "\\ARST", EN = "\\EN";
		IdString Q = "\\Q", D = "\\D", ADDR = "\\ADDR", DATA = "\\DATA", RD_EN = "\\RD_EN";
		IdString RD_CLK = "\\RD_CLK", RD_ADDR = "\\RD_ADDR", WR_CLK = "\\WR_CLK", WR_EN = "\\WR_EN";
		IdString WR_ADDR = "\\WR_ADDR", WR_DATA = "\\WR_DATA", RD_DATA = "\\RD_DATA";
		IdString CTRL_IN = "\\CTRL_IN", CTRL_OUT = "\\CTRL_OUT";

		setup_type("$sr", {SET, CLR}, {Q});
		setup_type("$ff", {D}, {Q});
		setup_type("$dff", {CLK, D}, {Q});
		setup_type("$dffe", {CLK, EN, D}, {Q});
		setup_type("$dffsr", {CLK, SET, CLR, D}, {Q});
		setup_type("$adff", {CLK, ARST, D}, {Q});
		setup_type("$dlatch", {EN, D}, {Q});
		setup_type("$dlatchsr", {EN, SET, CLR, D}, {Q});

		setup_type("$memrd", {CLK, EN, ADDR}, {DATA});
		setup_type("$memwr", {CLK, EN, ADDR, DATA}, pool<RTLIL::IdString>());
		setup_type("$meminit", {ADDR, DATA}, pool<RTLIL::IdString>());
		setup_type("$mem", {RD_CLK, RD_EN, RD_ADDR, WR_CLK, WR_EN, WR_ADDR, WR_DATA}, {RD_DATA});

		setup_type("$fsm", {CLK, ARST, CTRL_IN}, {CTRL_OUT});
	}

	void setup_stdcells()
	{
		IdString A = "\\A", B = "\\B", C = "\\C", D = "\\D";
		IdString E = "\\E", F = "\\F", G = "\\G", H = "\\H";
		IdString I = "\\I", J = "\\J", K = "\\K", L = "\\L";
		IdString M = "\\I", N = "\\N", O = "\\O", P = "\\P";
		IdString S = "\\S", T = "\\T", U = "\\U", V = "\\V";
		IdString Y = "\\Y";

		setup_type("$_BUF_", {A}, {Y}, true);
		setup_type("$_NOT_", {A}, {Y}, true);
		setup_type("$_AND_", {A, B}, {Y}, true);
		setup_type("$_NAND_", {A, B}, {Y}, true);
		setup_type("$_OR_",  {A, B}, {Y}, true);
		setup_type("$_NOR_",  {A, B}, {Y}, true);
		setup_type("$_XOR_", {A, B}, {Y}, true);
		setup_type("$_XNOR_", {A, B}, {Y}, true);
		setup_type("$_ANDNOT_", {A, B}, {Y}, true);<commit_msg>Fix IdString M in setup_stdcells()<commit_after>/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  <NAME> <<EMAIL>>
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#ifndef CELLTYPES_H
#define CELLTYPES_H

#include "kernel/yosys.h"

YOSYS_NAMESPACE_BEGIN

struct CellType
{
	RTLIL::IdString type;
	pool<RTLIL::IdString> inputs, outputs;
	bool is_evaluable;
};

struct CellTypes
{
	dict<RTLIL::IdString, CellType> cell_types;

	CellTypes()
	{
	}

	CellTypes(RTLIL::Design *design)
	{
		setup(design);
	}

	void setup(RTLIL::Design *design = NULL)
	{
		if (design)
			setup_design(design);

		setup_internals();
		setup_internals_mem();
		setup_stdcells();
		setup_stdcells_mem();
	}

	void setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false)
	{
		CellType ct = {type, inputs, outputs, is_evaluable};
		cell_types[ct.type] = ct;
	}

	void setup_module(RTLIL::Module *module)
	{
		pool<RTLIL::IdString> inputs, outputs;
		for (RTLIL::IdString wire_name : module->ports) {
			RTLIL::Wire *wire = module->wire(wire_name);
			if (wire->port_input)
				inputs.insert(wire->name);
			if (wire->port_output)
				outputs.insert(wire->name);
		}
		setup_type(module->name, inputs, outputs);
	}

	void setup_design(RTLIL::Design *design)
	{
		for (auto module : design->modules())
			setup_module(module);
	}

	void setup_internals()
	{
		std::vector<RTLIL::IdString> unary_ops = {
			"$not", "$pos", "$neg",
			"$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
			"$logic_not", "$slice", "$lut", "$sop"
		};

		std::vector<RTLIL::IdString> binary_ops = {
			"$and", "$or", "$xor", "$xnor",
			"$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
			"$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
			"$add", "$sub", "$mul", "$div", "$mod", "$pow",
			"$logic_and", "$logic_or", "$concat", "$macc"
		};
		IdString A = "\\A", B = "\\B", S = "\\S", Y = "\\Y";
		IdString P = "\\P", G = "\\G", C = "\\C", X = "\\X";
		IdString BI = "\\BI", CI = "\\CI", CO = "\\CO", EN = "\\EN";

		for (auto type : unary_ops)
			setup_type(type, {A}, {Y}, true);

		for (auto type : binary_ops)
			setup_type(type, {A, B}, {Y}, true);

		for (auto type : std::vector<RTLIL::IdString>({"$mux", "$pmux"}))
			setup_type(type, {A, B, S}, {Y}, true);

		setup_type("$lcu", {P, G, CI}, {CO}, true);
		setup_type("$alu", {A, B, CI, BI}, {X, Y, CO}, true);
		setup_type("$fa", {A, B, C}, {X, Y}, true);

		setup_type("$tribuf", {A, EN}, {Y}, true);

		setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
		setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
		setup_type("$live", {A, EN}, pool<RTLIL::IdString>(), true);
		setup_type("$fair", {A, EN}, pool<RTLIL::IdString>(), true);
		setup_type("$cover", {A, EN}, pool<RTLIL::IdString>(), true);
		setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true);
		setup_type("$anyconst", pool<RTLIL::IdString>(), {Y}, true);
		setup_type("$anyseq", pool<RTLIL::IdString>(), {Y}, true);
		setup_type("$allconst", pool<RTLIL::IdString>(), {Y}, true);
		setup_type("$allseq", pool<RTLIL::IdString>(), {Y}, true);
		setup_type("$equiv", {A, B}, {Y}, true);
	}

	void setup_internals_mem()
	{
		IdString SET = "\\SET", CLR = "\\CLR", CLK = "\\CLK", ARST = "\\ARST", EN = "\\EN";
		IdString Q = "\\Q", D = "\\D", ADDR = "\\ADDR", DATA = "\\DATA", RD_EN = "\\RD_EN";
		IdString RD_CLK = "\\RD_CLK", RD_ADDR = "\\RD_ADDR", WR_CLK = "\\WR_CLK", WR_EN = "\\WR_EN";
		IdString WR_ADDR = "\\WR_ADDR", WR_DATA = "\\WR_DATA", RD_DATA = "\\RD_DATA";
		IdString CTRL_IN = "\\CTRL_IN", CTRL_OUT = "\\CTRL_OUT";

		setup_type("$sr", {SET, CLR}, {Q});
		setup_type("$ff", {D}, {Q});
		setup_type("$dff", {CLK, D}, {Q});
		setup_type("$dffe", {CLK, EN, D}, {Q});
		setup_type("$dffsr", {CLK, SET, CLR, D}, {Q});
		setup_type("$adff", {CLK, ARST, D}, {Q});
		setup_type("$dlatch", {EN, D}, {Q});
		setup_type("$dlatchsr", {EN, SET, CLR, D}, {Q});

		setup_type("$memrd", {CLK, EN, ADDR}, {DATA});
		setup_type("$memwr", {CLK, EN, ADDR, DATA}, pool<RTLIL::IdString>());
		setup_type("$meminit", {ADDR, DATA}, pool<RTLIL::IdString>());
		setup_type("$mem", {RD_CLK, RD_EN, RD_ADDR, WR_CLK, WR_EN, WR_ADDR, WR_DATA}, {RD_DATA});

		setup_type("$fsm", {CLK, ARST, CTRL_IN}, {CTRL_OUT});
	}

	void setup_stdcells()
	{
		IdString A = "\\A", B = "\\B", C = "\\C", D = "\\D";
		IdString E = "\\E", F = "\\F", G = "\\G", H = "\\H";
		IdString I = "\\I", J = "\\J", K = "\\K", L = "\\L";
		IdString M = "\\M", N = "\\N", O = "\\O", P = "\\P";
		IdString S = "\\S", T = "\\T", U = "\\U", V = "\\V";
		IdString Y = "\\Y";

		setup_type("$_BUF_", {A}, {Y}, true);
		setup_type("$_NOT_", {A}, {Y}, true);
		setup_type("$_AND_", {A, B}, {Y}, true);
		setup_type("$_NAND_", {A, B}, {Y}, true);
		setup_type("$_OR_",  {A, B}, {Y}, true);
		setup_type("$_NOR_",  {A, B}, {Y}, true);
		setup_type("$_XOR_", {A, B}, {Y}, true);
		setup_type("$_XNOR_", {A, B}, {Y}, true);
		setup_type("$_ANDNOT_", {A, B}, {Y}, true);
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