<commit_before>.. currentmodule:: myhdl

.. _conv-usage:

*******************
Conversion examples
*******************


.. _conv-usage-intro:

Introduction
============

In this chapter, we will demonstrate the conversion process with a
number of examples. For the concepts of MyHDL conversion,
read the companion chapter :ref:`conv`.

.. _conv-usage-seq:

A small sequential design
=========================

Consider the following MyHDL code for an incrementer module::

    ACTIVE_LOW, INACTIVE_HIGH = 0, 1

    def Inc(count, enable, clock, reset):
        
        """ Incrementer with enable.
        
        count -- output
        enable -- control input, increment when 1
        clock -- clock input
        reset -- asynchronous reset input
        n -- counter max value
        
        """
        
        @always_seq(clock.posedge, reset=reset)
        def incLogic():
            if enable:
                count.next = count + 1

        return incLogic


Normally, to simulate the design, we would elaborate it as follows::

    m = 8

    count = Signal(modbv(0)[m:])
    enable = Signal(bool(0))
    clock  = Signal(bool(0))
    reset = ResetSignal(0, active=0, async=True)

    inc_inst = Inc(count, enable, clock, reset)

``inc_inst`` is an elaborated design instance that can be simulated. To convert
it to Verilog, we change the last line as follows::

   inc_inst = toVerilog(Inc, count, enable, clock, reset, n=n)

Again, this creates an instance that can be simulated, but as a side effect, it
also generates an equivalent Verilog module in file :file:`Inc.v`. The Verilog
code looks as follows::

    module Inc (
        count,
        enable,
        clock,
        reset
    );<commit_msg>cleaned up a conversion example, removed unused code<commit_after>.. currentmodule:: myhdl

.. _conv-usage:

*******************
Conversion examples
*******************


.. _conv-usage-intro:

Introduction
============

In this chapter, we will demonstrate the conversion process with a
number of examples. For the concepts of MyHDL conversion,
read the companion chapter :ref:`conv`.

.. _conv-usage-seq:

A small sequential design
=========================

Consider the following MyHDL code for an incrementer module::


    def Inc(count, enable, clock, reset):
        
        """ Incrementer with enable.
        
        count -- output
        enable -- control input, increment when 1
        clock -- clock input
        reset -- asynchronous reset input
        
        """
        
        @always_seq(clock.posedge, reset=reset)
        def incLogic():
            if enable:
                count.next = count + 1

        return incLogic


Normally, to simulate the design, we would elaborate it as follows::

    m = 8

    count = Signal(modbv(0)[m:])
    enable = Signal(bool(0))
    clock  = Signal(bool(0))
    reset = ResetSignal(0, active=0, async=True)

    inc_inst = Inc(count, enable, clock, reset)

``inc_inst`` is an elaborated design instance that can be simulated. To convert
it to Verilog, we change the last line as follows::

   inc_inst = toVerilog(Inc, count, enable, clock, reset)

Again, this creates an instance that can be simulated, but as a side effect, it
also generates an equivalent Verilog module in file :file:`Inc.v`. The Verilog
code looks as follows::

    module Inc (
        count,
        enable,
        clock,
        reset
    );
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