<commit_before>#!/usr/bin/env python3
# -*- coding: utf-8 -*-

from hwt.hdl.types.defs import BIT
from hwt.interfaces.std import Rst, Signal, Clk
from hwt.synthesizer.unit import Unit


# http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf
class ClkSynchronizer(Unit):
    """
    Signal synchronization between two clock domains

    :attention: multibits signals should not be sychronized using this sychronizer
        instead handshake or req-ack sychronization should be used for controll signals
        and main data should be passed over couble of registers

    .. hwt-schematic::
    """

    def _config(self):
        self.DATA_TYP = BIT

    def _declr(self):
        self.rst = Rst()

        self.inData = Signal(dtype=self.DATA_TYP)
        self.inClk = Clk()

        self.outData = Signal(dtype=self.DATA_TYP)._m()
        self.outClk = Clk()

    def _impl(self):
        def reg(name, clk):
            return self._reg(name,
                             self.DATA_TYP,
                             clk=clk,
                             rst=self.rst,
                             defVal=0)
        inReg = reg("inReg", self.inClk)
        outReg0 = reg("outReg0", self.outClk)
        outReg1 = reg("outReg1", self.outClk)

        inReg(self.inData)

        outReg0(inReg)
        outReg1(outReg0)
        self.outData(outReg1)<commit_msg>ClkSynchronizer: add missing clk association<commit_after>#!/usr/bin/env python3
# -*- coding: utf-8 -*-

from hwt.hdl.types.defs import BIT
from hwt.interfaces.std import Rst, Signal, Clk
from hwt.synthesizer.unit import Unit


# http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf
class ClkSynchronizer(Unit):
    """
    Signal synchronization between two clock domains

    :attention: multibits signals should not be sychronized using this sychronizer
        instead handshake or req-ack sychronization should be used for controll signals
        and main data should be passed over couble of registers

    .. hwt-schematic::
    """

    def _config(self):
        self.DATA_TYP = BIT

    def _declr(self):
        self.rst = Rst()

        self.inClk = Clk()
        with self._associated(clk=self.inClk):
            self.inData = Signal(dtype=self.DATA_TYP)

        self.outClk = Clk()
        with self._associated(clk=self.outClk):
            self.outData = Signal(dtype=self.DATA_TYP)._m()

    def _impl(self):
        def reg(name, clk):
            return self._reg(name,
                             self.DATA_TYP,
                             clk=clk,
                             rst=self.rst,
                             defVal=0)
        inReg = reg("inReg", self.inClk)
        outReg0 = reg("outReg0", self.outClk)
        outReg1 = reg("outReg1", self.outClk)

        inReg(self.inData)

        outReg0(inReg)
        outReg1(outReg0)
        self.outData(outReg1)
{'fraction_non_alphanumeric': 0.1, 'fraction_numerical': 0.010380622837370242, 'mean_word_length': 2.0335781741867787, 'pattern_counts': {'":': 0, '<': 3, '<?xml version=': 0, '>': 3, 'https://': 0, 'lorem ipsum': 0, 'www.': 2, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 0, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '6795688', 'n_tokens_mistral': 962, 'n_tokens_neox': 904, 'n_words': 205}