<commit_before># J1Sc - A simple reimplementation of the [J1 CPU](http://www.excamera.com/sphinx/fpga-j1.html) in Scala using Spinal HDL

## How to build J1Sc and Swapforth

To build the J1Sc, you need first to create the VDHL / Verilog sources. The implementation is written by using *Spinal HDL* (https://github.com/SpinalHDL/SpinalHDL). Hence these sources are generated by a Scala program (Spinal HDL is a compelling Scala library that can be used to generate VHDL and Verilog code.

* Install OpenJDK 8

* Install a running Scala system and sbt

* Clone the latest version of Spinal HDL (at least version 1.4.1)
   (see https://github.com/SpinalHDL/SpinalHDL)

* Setup Spinal HDL
   (see http://spinalhdl.github.io/SpinalDoc/spinal_getting_started/)

* Install gforth (e.g. `sudo apt-get install gforth`)

* Change directory to the new clone of SpinalHDL and run `sbt publish-local` inside

* Clone J1Sc

* Change directory to J1Sc

* Run `cd toolchain/forth && make && cd ../..` to build the forth core system

## A FORTH Shell/Terminal for J1Sc
<NAME> offers an excellent terminal for embedded FORTH systems, which supports linux on x86 and Raspberry/Raspbian. Besides 430CamelForth , 430eForth , 4e4th, AmForth, anyForth , Mecrisp , Mecrisp-Stellaris , noForth and STM8 eForth it also supports the J1Sc with Swapforth now (thank you Manfred!). This solution gives a much higher comfort than the original Python-based terminals from Swapforth. Hence it is (strongly) suggested to use e4thcom instead the provided python-scripts. The python scripts are not very comfortable (you have been warned!) and reconnecting to your J1Sc doesn't work (at least for me).

Download the latest e4thcom (https://wiki.forth-ev.de/doku.php/en:projects:e4thcom) and install it according to the documentation (copy it to the installation directory) the e4thcom-plugin swapforth-j1sc.efc from support/e4thcom/.

Start enjoying e4thcom by the following command-line by `e4thcom -d ttyUSB1 -b B115200 -t swapforth-j1sc`. In case anything does not work, please check for the correct transmission rate (B115200 for the Nexys4 and B38400 for the simulation) and the serial device (e.g. `/dev/tnt0` for the simulation). Make sure that the PATH-variable is set correctly and your J1Sc instance is connected to `/dev/ttyUSB1` or modify the command-line accordingly to your situation.

The descriptions below show how to work with J1Sc _without_ e4thcom. I give you advise _not_ to do so because the shell scripts `bin/confsX` are unflexible and uncomfortable. Be warned!

## Supported prototyping boards
### J1Sc for a Digilent Nexys4 and Nexys4DDR board

* We will build the J1Sc variant J1Nexys4X (either using the VHDL or the Verilog version) by `sbt run` (select the Nexys4X configuration to be generated). The generated files can be found in `gen/src/vhdl/J1Nexys4X.vhd` and `gen/src/verilog/J1Nexys4X.v`. You need `Board_<BOARDNAME>.vhd` and `PLL.vhd` in `src/main/vhdl/arch` or the corresponding Verilog versions in `src/main/verilog/arch` as toplevel for synthesis.
A Xilinx Vivado project file `J1Sc.xpr` for the VHDL version can be found in `vprj/vhdl/J1Sc` and the Verilog version is in `vprj/verilog/J1Sc`. Note that J1Sc runs fine with a 100Mhz clock on a Nexys4 DDR from Digilent. Constraint files for the Nexys4 DDR can be found in `/src/main/xilinx/nexys4ddr` the corresponding files for the Nexys4 can be found in `/src/main/xilinx/nexys4`.

* Next build J1Nexys4X (see `gen/src/vhdl` or `gen/src/verilog`) which is the J1Sc variant used fo Neys4X boards. Send the .bit file to your FPGA/board (use either `src/main/vhdl/arch/Nexys4DDR/BoardNexys4DDR.vhd` or `src/main/verilog/arch/Nexys4DDR/BoardNexys4DDR.v` as toplevel module)<commit_msg>Added a remark about the new e4thcom version<commit_after># J1Sc - A simple reimplementation of the [J1 CPU](http://www.excamera.com/sphinx/fpga-j1.html) in Scala using Spinal HDL

## How to build J1Sc and Swapforth

To build the J1Sc, you need first to create the VDHL / Verilog sources. The implementation is written by using *Spinal HDL* (https://github.com/SpinalHDL/SpinalHDL). Hence these sources are generated by a Scala program (Spinal HDL is a compelling Scala library that can be used to generate VHDL and Verilog code.

* Install OpenJDK 8

* Install a running Scala system and sbt

* Clone the latest version of Spinal HDL (at least version 1.4.1)
   (see https://github.com/SpinalHDL/SpinalHDL)

* Setup Spinal HDL
   (see http://spinalhdl.github.io/SpinalDoc/spinal_getting_started/)

* Install gforth (e.g. `sudo apt-get install gforth`)

* Change directory to the new clone of SpinalHDL and run `sbt publish-local` inside

* Clone J1Sc

* Change directory to J1Sc

* Run `cd toolchain/forth && make && cd ../..` to build the forth core system

## A FORTH Shell/Terminal for J1Sc
<NAME> offers an excellent terminal for embedded FORTH systems, which supports linux on x86 and Raspberry/Raspbian. Besides 430CamelForth , 430eForth , 4e4th, AmForth, anyForth , Mecrisp , Mecrisp-Stellaris , noForth and STM8 eForth it also supports the J1Sc with Swapforth now (thank you Manfred!). This solution gives a much higher comfort than the original Python-based terminals from Swapforth. Hence it is (strongly) suggested to use e4thcom instead the provided python-scripts. The python scripts are not very comfortable (you have been warned!) and reconnecting to your J1Sc doesn't work (at least for me).

Download the latest e4thcom (https://wiki.forth-ev.de/doku.php/en:projects:e4thcom) and install it according to the documentation (copy it to the installation directory) the e4thcom-plugin swapforth-j1sc.efc from support/e4thcom/. Version 0.8.2 works out of the box, because it has the swapforth-plugin in the distribution. Hence, You don't have to copy swapforth-j1sc.efc!

Start enjoying e4thcom by the following command-line by `e4thcom -d ttyUSB1 -b B115200 -t swapforth-j1sc`. In case anything does not work, please check for the correct transmission rate (B115200 for the Nexys4 and B38400 for the simulation) and the serial device (e.g. `/dev/tnt0` for the simulation). Make sure that the PATH-variable is set correctly and your J1Sc instance is connected to `/dev/ttyUSB1` or modify the command-line accordingly to your situation.

The descriptions below show how to work with J1Sc _without_ e4thcom. I give you advise _not_ to do so because the shell scripts `bin/confsX` are unflexible and uncomfortable. Be warned!

## Supported prototyping boards
### J1Sc for a Digilent Nexys4 and Nexys4DDR board

* We will build the J1Sc variant J1Nexys4X (either using the VHDL or the Verilog version) by `sbt run` (select the Nexys4X configuration to be generated). The generated files can be found in `gen/src/vhdl/J1Nexys4X.vhd` and `gen/src/verilog/J1Nexys4X.v`. You need `Board_<BOARDNAME>.vhd` and `PLL.vhd` in `src/main/vhdl/arch` or the corresponding Verilog versions in `src/main/verilog/arch` as toplevel for synthesis.
A Xilinx Vivado project file `J1Sc.xpr` for the VHDL version can be found in `vprj/vhdl/J1Sc` and the Verilog version is in `vprj/verilog/J1Sc`. Note that J1Sc runs fine with a 100Mhz clock on a Nexys4 DDR from Digilent. Constraint files for the Nexys4 DDR can be found in `/src/main/xilinx/nexys4ddr` the corresponding files for the Nexys4 can be found in `/src/main/xilinx/nexys4`.

* Next build J1Nexys4X (see `gen/src/vhdl` or `gen/src/verilog`) which is the J1Sc variant used fo Neys4X boards. Send the .bit file to your FPGA/board (use either `src/main/vhdl/arch/Nexys4DDR/BoardNexys4DDR.vhd` or `src/main/verilog/arch/Nexys4DDR/BoardNexys4DDR.v` as toplevel module)
{'fraction_non_alphanumeric': 0.07426778242677824, 'fraction_numerical': 0.02392782426778243, 'mean_word_length': 4.40947666195191, 'pattern_counts': {'":': 0, '<': 7, '<?xml version=': 0, '>': 7, 'https://': 6, 'lorem ipsum': 0, 'www.': 2, 'xml': 0}, 'pii_count': 0, 'substrings_counts': 0, 'word_list_counts': {'cursed_substrings.json': 2, 'profanity_word_list.json': 0, 'sexual_word_list.json': 0, 'zh_pornsignals.json': 0}}
{'dir': 'git-commits-cleaned', 'id': '431154', 'n_tokens_mistral': 2625, 'n_tokens_neox': 2449, 'n_words': 1032}