<commit_before>/*
 * Copyright 2014, NICTA
 *
 * This software may be distributed and modified according to the terms of
 * the GNU General Public License version 2. Note that NO WARRANTY is provided.
 * See "LICENSE_GPLv2.txt" for details.
 *
 * @TAG(NICTA_GPL)
 */

#include <ethdrivers/intel.h>
#include <assert.h>
#include <ethdrivers/helpers.h>

typedef enum e1000_family {
    e1000_82580 = 1,
    e1000_82574
} e1000_family_t;

/* An alignment of 128 bytes is required for most structures by the hardware, except for actual packets */
#define DMA_ALIGN 128
/* This driver is hard coded to use 2k buffers, don't just change this */
#define BUF_SIZE 2048

// TX Descriptor Status Bits
#define TX_DD BIT(0) /* Descriptor Done */
/* Descriptor CMD Bits */
#define TX_CMD_EOP BIT(0) /* End of Packet */
#define TX_CMD_IFCS BIT(1) /* Insert FCS (CRC) */
#define TX_CMD_RS BIT(3) /* Report status */
#define TX_CMD_IDE BIT(7) /* Interrupt Delay Enable */

// RX Descriptor Status Bits
#define RX_DD BIT(0) /* Descriptor Done */
#define RX_EOP BIT(1) /* End of Packet */


#define REG(x,y) (*(volatile uint32_t*)(((uintptr_t)(x)->iobase) + (y)))

#define REG_CTRL(x) REG(x, 0x0)
#define REG_82580_IMC(x) REG(x, 0x150c)
#define REG_82574_IMC(x) REG(x, 0xD8)
#define REG_STATUS(x) REG(x, 0x8)
#define REG_82580_TXDCTL(x, y) REG(x, 0xE028 + 0x40 * (y))
#define REG_82574_TXDCTL(x, y) REG(x, 0x3828 + 0x100 * (y))
#define REG_MTA(x, y) REG(x, 0x5200 + 4 * (y))
#define REG_RCTL(x) REG(x, 0x100)
#define REG_EERD(x) REG(x, 0x14)
#define REG_TCTL(x) REG(x, 0x0400)
#define REG_82580_TDBAL(x, y) REG(x, 0xE000 + (y) * 0x40)
#define REG_82574_TDBAL(x, y) REG(x, 0x3800 + (y) * 0x100)
#define REG_82580_TDBAH(x, y) REG(x, 0xE004 + (y) * 0x40)
#define REG_82574_TDBAH(x, y) REG(x, 0x3804 + (y) * 0x100)
#define REG_82580_TDLEN(x, y) REG(x, 0xE008 + (y) * 0x40)
#define REG_82574_TDLEN(x, y) REG(x, 0x3808 + (y) * 0x100)
#define REG_82580_TDH(x, y) REG(x, 0xE010 + (y) * 0x40)
#define REG_82574_TDH(x, y) REG(x, 0x3810 + (y) * 0x100)
#define REG_82580_TDT(x, y) REG(x, 0xE018 + (y) * 0x40)
#define REG_82574_TDT(x, y) REG(x, 0x3818 + (y) * 0x100)
#define REG_82580_RDBAL(x, y) REG(x, 0xC000 + (y) * 0x40)
#define REG_82574_RDBAL(x, y) REG(x, 0x2800 + (y) * 0x100)
#define REG_82580_RDBAH(x, y) REG(x, 0xC004 + (y) * 0x40)
#define REG_82574_RDBAH(x, y) REG(x, 0x2804 + (y) * 0x100)
#define REG_82580_RDLEN(x, y) REG(x, 0xC008 + (y) * 0x40)
#define REG_82574_RDLEN(x, y) REG(x, 0x2808 + (y) * 0x100)
#define REG_82580_RDH(x, y) REG(x, 0xc010 + (y) * 0x40)
#define REG_82574_RDH(x, y) REG(x, 0x2810 + (y) * 0x100)
#define REG_82580_RDT(x, y) REG(x, 0xc018 + (y) * 0x40)
#define REG_82574_RDT(x, y) REG(x, 0x2818 + (y) * 0x100)
#define REG_82580_RXDCTL(x, y) REG(x, 0xc028 + (y) * 0x40)
#define REG_82574_RXDCTL(x, y) REG(x, 0x2828 + (y) * 0x100)
#define REG_82580_IMS(x) REG(x, 0x1508)
#define REG_82574_IMS(x) REG(x, 0xD0)
#define REG_82580_ICR(x) REG(x, 0x1500)
#define REG_82574_ICR(x) REG(x, 0xC0)
#define REG_TIPG(x) REG(x, 0x410)
#define REG_82574_RDTR(x) REG(x, 0x2820)
#define REG_82574_RADV(x) REG(x, 0x282c)
#define REG_82574_RAID(x) REG(x, 0x2c08)
#define REG_82574_TIDV(x) REG(x, 0x3820)
#define REG_82574_TADV(x) REG(x, 0x382c)
#define REG_82574_PBA(x) REG(x, 0x1000)
#define REG_MDIC(x) REG(x, 0x20)
#define REG_82574_GCR(x) REG(x, 0x5B00)
#define REG_82574_FCT(x) REG(x, 0x030)
#define REG_82574_FCAL(x) REG(x, 0x028)
#define REG_82574_FCAH(x) REG(x, 0x02c)

#define IMC_82580_RESERVED_BITS (BIT(1) | BIT(3) | BIT(5) | BIT(9) | BIT(15) | BIT(16) | BIT(17) | BIT(21) | BIT(23) | BIT(27) | BIT(31))
#define IMC_82574_RESERVED_BITS (BIT(3) | BIT(5) | BIT(8) | (0b11111 << 10) | BIT(19) | (0b1111111 << 25))

#define CTRL_82580_RESERVED_BITS (BIT(24) | BIT(25))
#define CTRL_82574_RESERVED_BITS (BIT(1) | (0b11 << 3) | BIT(7) | BIT(10) | (0b1111111 << 13) | (0b11111 << 21) | BIT(29))
#define CTRL_SLU BIT(6)
#define CTRL_RST BIT(26)

#define STATUS_LU BIT(1)

#define STATUS_82580_LAN_ID_OFFSET 2
#define STATUS_82580_LAN_ID_MASK (BIT(2) | BIT(3))

#define RCTL_82580_RESERVED_BITS (BIT(0) | BIT(10) | BIT(11) | BIT(27) | BIT(28) | BIT(29) | BIT(30) | BIT(31))
#define RCTL_82574_RESERVED_BITS (BIT(0) | BIT(14) | BIT(21) | BIT(24) | BIT(31))
#define RCTL_82574_RDMTS_OFFSET (8)
#define RCTL_82574_RDMTS_1_4 (0b10 << RCTL_82574_RDMTS_OFFSET)
#define RCTL_EN BIT(1)
#define RCTL_UPE BIT(3)
#define RCTL_MPE BIT(4)
#define RCTL_BAM BIT(15)

#define TXDCTL_82580_RESERVED_BITS (0)
#define TXDCTL_82574_RESERVED_BITS (0)<commit_msg>libethdrivers: Force constant to be 32-bit type<commit_after>/*
 * Copyright 2014, NICTA
 *
 * This software may be distributed and modified according to the terms of
 * the GNU General Public License version 2. Note that NO WARRANTY is provided.
 * See "LICENSE_GPLv2.txt" for details.
 *
 * @TAG(NICTA_GPL)
 */

#include <ethdrivers/intel.h>
#include <assert.h>
#include <ethdrivers/helpers.h>

typedef enum e1000_family {
    e1000_82580 = 1,
    e1000_82574
} e1000_family_t;

/* An alignment of 128 bytes is required for most structures by the hardware, except for actual packets */
#define DMA_ALIGN 128
/* This driver is hard coded to use 2k buffers, don't just change this */
#define BUF_SIZE 2048

// TX Descriptor Status Bits
#define TX_DD BIT(0) /* Descriptor Done */
/* Descriptor CMD Bits */
#define TX_CMD_EOP BIT(0) /* End of Packet */
#define TX_CMD_IFCS BIT(1) /* Insert FCS (CRC) */
#define TX_CMD_RS BIT(3) /* Report status */
#define TX_CMD_IDE BIT(7) /* Interrupt Delay Enable */

// RX Descriptor Status Bits
#define RX_DD BIT(0) /* Descriptor Done */
#define RX_EOP BIT(1) /* End of Packet */


#define REG(x,y) (*(volatile uint32_t*)(((uintptr_t)(x)->iobase) + (y)))

#define REG_CTRL(x) REG(x, 0x0)
#define REG_82580_IMC(x) REG(x, 0x150c)
#define REG_82574_IMC(x) REG(x, 0xD8)
#define REG_STATUS(x) REG(x, 0x8)
#define REG_82580_TXDCTL(x, y) REG(x, 0xE028 + 0x40 * (y))
#define REG_82574_TXDCTL(x, y) REG(x, 0x3828 + 0x100 * (y))
#define REG_MTA(x, y) REG(x, 0x5200 + 4 * (y))
#define REG_RCTL(x) REG(x, 0x100)
#define REG_EERD(x) REG(x, 0x14)
#define REG_TCTL(x) REG(x, 0x0400)
#define REG_82580_TDBAL(x, y) REG(x, 0xE000 + (y) * 0x40)
#define REG_82574_TDBAL(x, y) REG(x, 0x3800 + (y) * 0x100)
#define REG_82580_TDBAH(x, y) REG(x, 0xE004 + (y) * 0x40)
#define REG_82574_TDBAH(x, y) REG(x, 0x3804 + (y) * 0x100)
#define REG_82580_TDLEN(x, y) REG(x, 0xE008 + (y) * 0x40)
#define REG_82574_TDLEN(x, y) REG(x, 0x3808 + (y) * 0x100)
#define REG_82580_TDH(x, y) REG(x, 0xE010 + (y) * 0x40)
#define REG_82574_TDH(x, y) REG(x, 0x3810 + (y) * 0x100)
#define REG_82580_TDT(x, y) REG(x, 0xE018 + (y) * 0x40)
#define REG_82574_TDT(x, y) REG(x, 0x3818 + (y) * 0x100)
#define REG_82580_RDBAL(x, y) REG(x, 0xC000 + (y) * 0x40)
#define REG_82574_RDBAL(x, y) REG(x, 0x2800 + (y) * 0x100)
#define REG_82580_RDBAH(x, y) REG(x, 0xC004 + (y) * 0x40)
#define REG_82574_RDBAH(x, y) REG(x, 0x2804 + (y) * 0x100)
#define REG_82580_RDLEN(x, y) REG(x, 0xC008 + (y) * 0x40)
#define REG_82574_RDLEN(x, y) REG(x, 0x2808 + (y) * 0x100)
#define REG_82580_RDH(x, y) REG(x, 0xc010 + (y) * 0x40)
#define REG_82574_RDH(x, y) REG(x, 0x2810 + (y) * 0x100)
#define REG_82580_RDT(x, y) REG(x, 0xc018 + (y) * 0x40)
#define REG_82574_RDT(x, y) REG(x, 0x2818 + (y) * 0x100)
#define REG_82580_RXDCTL(x, y) REG(x, 0xc028 + (y) * 0x40)
#define REG_82574_RXDCTL(x, y) REG(x, 0x2828 + (y) * 0x100)
#define REG_82580_IMS(x) REG(x, 0x1508)
#define REG_82574_IMS(x) REG(x, 0xD0)
#define REG_82580_ICR(x) REG(x, 0x1500)
#define REG_82574_ICR(x) REG(x, 0xC0)
#define REG_TIPG(x) REG(x, 0x410)
#define REG_82574_RDTR(x) REG(x, 0x2820)
#define REG_82574_RADV(x) REG(x, 0x282c)
#define REG_82574_RAID(x) REG(x, 0x2c08)
#define REG_82574_TIDV(x) REG(x, 0x3820)
#define REG_82574_TADV(x) REG(x, 0x382c)
#define REG_82574_PBA(x) REG(x, 0x1000)
#define REG_MDIC(x) REG(x, 0x20)
#define REG_82574_GCR(x) REG(x, 0x5B00)
#define REG_82574_FCT(x) REG(x, 0x030)
#define REG_82574_FCAL(x) REG(x, 0x028)
#define REG_82574_FCAH(x) REG(x, 0x02c)

#define IMC_82580_RESERVED_BITS ((uint32_t)(BIT(1) | BIT(3) | BIT(5) | BIT(9) | BIT(15) | BIT(16) | BIT(17) | BIT(21) | BIT(23) | BIT(27) | BIT(31)))
#define IMC_82574_RESERVED_BITS (BIT(3) | BIT(5) | BIT(8) | (0b11111 << 10) | BIT(19) | (0b1111111 << 25))

#define CTRL_82580_RESERVED_BITS (BIT(24) | BIT(25))
#define CTRL_82574_RESERVED_BITS (BIT(1) | (0b11 << 3) | BIT(7) | BIT(10) | (0b1111111 << 13) | (0b11111 << 21) | BIT(29))
#define CTRL_SLU BIT(6)
#define CTRL_RST BIT(26)

#define STATUS_LU BIT(1)

#define STATUS_82580_LAN_ID_OFFSET 2
#define STATUS_82580_LAN_ID_MASK (BIT(2) | BIT(3))

#define RCTL_82580_RESERVED_BITS (BIT(0) | BIT(10) | BIT(11) | BIT(27) | BIT(28) | BIT(29) | BIT(30) | BIT(31))
#define RCTL_82574_RESERVED_BITS (BIT(0) | BIT(14) | BIT(21) | BIT(24) | BIT(31))
#define RCTL_82574_RDMTS_OFFSET (8)
#define RCTL_82574_RDMTS_1_4 (0b10 << RCTL_82574_RDMTS_OFFSET)
#define RCTL_EN BIT(1)
#define RCTL_UPE BIT(3)
#define RCTL_MPE BIT(4)
#define RCTL_BAM BIT(15)

#define TXDCTL_82580_RESERVED_BITS (0)
#define TXDCTL_82574_RESERVED_BITS (0)
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