<commit_before>#include "common.h"
#include "cpu.h"
#include "cprint.h"

#define EXG_IN_PROGRESS 1

/*
 * --------------------------------------------------------------------
 *                   |    Exec Time    |  Data Bus Usage
 *         EXG       |      INSTR      |    INSTR
 * ------------------+-----------------+-------------------------------
 *   .L :            |                 |
 *     Dx,Dy         |  6(1/0)         |  np       n
 *     Ax,Ay         |  6(1/0)         |  np       n
 *     Dx,Ay         |  6(1/0)         |  np       n
 */
static void exg(struct cpu *cpu, WORD op)
{
  LONG t;
  int rx,ry;

  ENTER;

  switch(cpu->instr_state) {
  case INSTR_STATE_NONE:
    cpu->instr_state = EXG_IN_PROGRESS;
    cpu_prefetch();
    break;
  case EXG_IN_PROGRESS:
    rx = (op&0xe00)>>9;
    ry = (op&7);
    switch(op&0xf8) {
    case 0x40: /* Dx,Dy */
      t = cpu->d[rx];
      cpu->d[rx] = cpu->d[ry];
      cpu->d[ry] = t;
      break;
    case 0x48:/* Ax,Ay */
      t = cpu->a[rx];
      cpu->a[rx] = cpu->a[ry];
      cpu->a[ry] = t;
      break;
    case 0x88:/* Dx,Ay */
      t = cpu->d[rx];
      cpu->d[rx] = cpu->a[ry];
      cpu->a[ry] = t;
      break;
    }
    ADD_CYCLE(2);
    cpu->instr_state = INSTR_STATE_FINISHED;
    break;
  }
}
<commit_msg>Add missing cycles to EXG.<commit_after>#include "common.h"
#include "cpu.h"
#include "cprint.h"

#define EXG_IN_PROGRESS 1

/*
 * --------------------------------------------------------------------
 *                   |    Exec Time    |  Data Bus Usage
 *         EXG       |      INSTR      |    INSTR
 * ------------------+-----------------+-------------------------------
 *   .L :            |                 |
 *     Dx,Dy         |  6(1/0)         |  np       n
 *     Ax,Ay         |  6(1/0)         |  np       n
 *     Dx,Ay         |  6(1/0)         |  np       n
 */
static void exg(struct cpu *cpu, WORD op)
{
  LONG t;
  int rx,ry;

  ENTER;

  switch(cpu->instr_state) {
  case INSTR_STATE_NONE:
    ADD_CYCLE(4);
    cpu->instr_state = EXG_IN_PROGRESS;
    cpu_prefetch();
    break;
  case EXG_IN_PROGRESS:
    rx = (op&0xe00)>>9;
    ry = (op&7);
    switch(op&0xf8) {
    case 0x40: /* Dx,Dy */
      t = cpu->d[rx];
      cpu->d[rx] = cpu->d[ry];
      cpu->d[ry] = t;
      break;
    case 0x48:/* Ax,Ay */
      t = cpu->a[rx];
      cpu->a[rx] = cpu->a[ry];
      cpu->a[ry] = t;
      break;
    case 0x88:/* Dx,Ay */
      t = cpu->d[rx];
      cpu->d[rx] = cpu->a[ry];
      cpu->a[ry] = t;
      break;
    }
    ADD_CYCLE(2);
    cpu->instr_state = INSTR_STATE_FINISHED;
    break;
  }
}

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